From 7877739197f9e0216b796fbd4cc869e65653a9ac Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Fri, 4 Apr 2025 15:19:57 +0100
Subject: [PATCH] Add TSMC 16nm initial flow
---
.gitignore | 4 +
.../28pin/Synopsys_FC/floorplan/floorplan.def | 13 +
.../28pin/Synopsys_FC/floorplan/floorplan.tcl | 51 +++
.../floorplan/floorplan_compare_data.txt | 32 ++
.../28pin/Synopsys_FC/floorplan/fp.tcl | 103 ++++++
.../28pin/Synopsys_FC/floorplan/mapfile | 1 +
.../28pin/Synopsys_FC/inputs/constraints.sdc | 74 +++++
.../28pin/Synopsys_FC/inputs/nanosoc.upf | 0
ASIC/TSMC16nm/28pin/Synopsys_FC/makefile | 17 +
.../Synopsys_FC/scripts/1_design_setup.tcl | 35 ++
.../28pin/Synopsys_FC/scripts/2_floorplan.tcl | 49 +++
.../28pin/Synopsys_FC/scripts/3_synthesis.tcl | 26 ++
.../28pin/Synopsys_FC/scripts/4_cts.tcl | 23 ++
.../28pin/Synopsys_FC/scripts/5_route.tcl | 9 +
.../scripts/synopsys_library_setup.tcl | 96 ++++++
ASIC/TSMC16nm/rom_via.spec | 37 +++
ASIC/TSMC16nm/sram_32k.spec | 50 +++
.../tsmc16fcll/nanosoc_chip_pads_28pin.v | 307 ++++++++++++++++++
flows/makefile.asic | 6 +
makefile | 12 +
.../nanosoc_control/verilog/nanosoc_pin_mux.v | 74 ++---
.../verilog/nanosoc_ss_systemctrl.v | 6 +-
nanosoc/synopsys_28nm_slm_integration | 2 +-
23 files changed, 986 insertions(+), 41 deletions(-)
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.def
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/fp.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/mapfile
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/constraints.sdc
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/nanosoc.upf
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/makefile
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/1_design_setup.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/2_floorplan.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/3_synthesis.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/4_cts.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/5_route.tcl
create mode 100644 ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/synopsys_library_setup.tcl
create mode 100644 ASIC/TSMC16nm/rom_via.spec
create mode 100644 ASIC/TSMC16nm/sram_32k.spec
create mode 100644 ASIC/nanosoc_chip_pads/tsmc16fcll/nanosoc_chip_pads_28pin.v
diff --git a/.gitignore b/.gitignore
index 2675ddb..e023287 100644
--- a/.gitignore
+++ b/.gitignore
@@ -47,6 +47,10 @@ ASIC/*/*/Synopsys_FC/cln28ht_pmk
ASIC/*/*/Synopsys_FC/cln28ht_ret
ASIC/*/*/Synopsys_FC/io_lib
ASIC/*/*/Synopsys_FC/legalizer_debug_plots
+
+ASIC/*/*/Synopsys_FC/libs
+ASIC/*/*/Synopsys_FC/work
+
ASIC/Synopsys/Formality/FM_INFO/*
ASIC/Synopsys/ICC2/CLIBs
ASIC/Synopsys/ICC2/PreFrameCheck
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.def b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.def
new file mode 100644
index 0000000..e60e8ea
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.def
@@ -0,0 +1,13 @@
+#
+# Fusion Compiler write_def
+# Release : U-2022.12
+# User Name : dwn1c21
+# Date : Fri Apr 4 11:36:26 2025
+#
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN nanosoc_chip_pads ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 0 1020192 ) ( 1020384 1020192 ) ( 1020384 0 ) ;
+END DESIGN
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.tcl
new file mode 100644
index 0000000..627ff42
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan.tcl
@@ -0,0 +1,51 @@
+################################################################################
+#
+# Created by fc write_floorplan on Fri Apr 4 11:36:26 2025
+#
+################################################################################
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+source ${_dirName__0}/fp.tcl
+
+if { [get_attribute -name view_name [current_block]] == "design" } {
+ set __fp_crnt_design_name__ [get_attribute -name design_name [current_block]]
+ set __fp_crnt_label_name__ [get_attribute -name label_name [current_block]]
+ set __fp_crnt_lib_name__ [get_attribute -name lib_name [current_block]]
+ set __fp_crnt_lib_path__ [get_attribute -name source_file_name [current_lib]]
+ set __fp_crnt_abs_name__ ${__fp_crnt_lib_name__}:${__fp_crnt_design_name__}
+ set __fp_crnt_abs_path__ ${__fp_crnt_lib_path__}/${__fp_crnt_design_name__}
+ if { [string length ${__fp_crnt_label_name__} ] != 0 } {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}/${__fp_crnt_label_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/design_label.${__fp_crnt_label_name__}/abs
+ } else {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/abs
+ }
+ if { [sizeof_collection [get_blocks -quiet ${__fp_crnt_abs_name__}]] != 0} {
+ if { [get_attribute -name has_editable_abstract [current_block]] } {
+ echo "Design [get_attribute -name full_name [current_block]] has editable abstract view. Re-creating the abstract view after floorplan loading..."
+ set __fp_crnt_abs_type__ [get_attribute -quiet -name abstract_view_type [current_block]]
+ if { [string length ${__fp_crnt_abs_type__} ] == 0 } {
+ if { [file exists "${__fp_crnt_abs_path__}/abs.mc"] } {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ } else {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ }
+ } elseif { ${__fp_crnt_abs_type__} == "placement" } {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ } else {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ }
+ }
+ }
+}
+
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan_compare_data.txt b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
new file mode 100644
index 0000000..711bb4e
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
@@ -0,0 +1,32 @@
+################################################################################
+#
+# Created by fc compare_floorplans on Fri Apr 4 11:36:26 2025
+#
+# DO NOT EDIT - automatically generated file
+#
+################################################################################
+
+START nanosoc_chip_pads
+ MACROS
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {99.9840 849.3600} {117.7140 920.2080} }
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {703.0950 472.8000} {920.4000 621.9360} }
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {703.0950 323.6640} {920.4000 472.8000} }
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {703.0950 771.0720} {920.4000 920.2080} }
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {703.0950 621.9360} {920.4000 771.0720} }
+ PINS
+ VDDIO { {510.1920 510.0960} {510.1921 510.0961} }
+ VDDACC { {510.1920 510.0960} {510.1921 510.0961} }
+ CLK { {-16.5300 17.1090} {-8.4300 26.1090} }
+ TEST { {-16.5300 17.1090} {-8.4300 26.1090} }
+ NRST { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P0[3] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P0[2] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P0[1] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P0[0] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P1[3] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P1[2] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P1[1] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ P1[0] { {-16.5300 17.1090} {-8.4300 26.1090} }
+ SWDIO { {-16.5300 17.1090} {-8.4300 26.1090} }
+ SWDCK { {-16.5300 17.1090} {-8.4300 26.1090} }
+END nanosoc_chip_pads
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/fp.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/fp.tcl
new file mode 100644
index 0000000..e383664
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/fp.tcl
@@ -0,0 +1,103 @@
+################################################################################
+#
+# Created by fc write_floorplan on Fri Apr 4 11:36:26 2025
+#
+################################################################################
+
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+################################################################################
+# Read DEF
+################################################################################
+
+read_def ${_dirName__0}/floorplan.def
+
+################################################################################
+# Macros
+################################################################################
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R180
+set_attribute -quiet -objects $cellInst -name origin -value { 117.7140 920.2080 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 703.0950 472.8000 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 703.0950 323.6640 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 703.0950 771.0720 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 703.0950 621.9360 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+
+################################################################################
+# User attributes of macros
+################################################################################
+
+
+################################################################################
+# Module Boundaries
+################################################################################
+
+set hbCells [get_cells -quiet -filter hierarchy_type==boundary -hierarchical]
+if [sizeof_collection $hbCells] {
+ set_cell_hierarchy_type -type normal $hbCells
+}
+
+
+################################################################################
+# I/O guides
+################################################################################
+
+remove_io_guides -all
+
+create_io_guide -name _default_io_ring1.left -side left -line { {0.0000 \
+ 74.4960} 871.2000 } -offset {0.0000 0.0000}
+create_io_guide -name _default_io_ring1.bottom -side bottom -line { {945.8880 \
+ 0.0000} 871.3920 } -offset {0.0000 0.0000}
+create_io_guide -name _default_io_ring1.right -side right -line { {1020.3840 \
+ 945.6960} 871.2000 } -offset {0.0000 0.0000}
+create_io_guide -name _default_io_ring1.top -side top -line { {74.4960 \
+ 1020.1920} 871.3920 } -offset {0.0000 0.0000}
+
+################################################################################
+# User attributes of I/O guides
+################################################################################
+
+
+################################################################################
+# User attributes of current block
+################################################################################
+
+define_user_attribute -classes design -type string LEF58_EDGETYPE
+define_user_attribute -classes design -type double ioCellOffsetX
+define_user_attribute -classes design -type double ioCellOffsetY
+
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/mapfile b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/mapfile
new file mode 100644
index 0000000..1af7533
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/floorplan/mapfile
@@ -0,0 +1 @@
+nanosoc_chip_pads FLOORPLAN fp.tcl
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/constraints.sdc b/ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/constraints.sdc
new file mode 100644
index 0000000..d3d9823
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/constraints.sdc
@@ -0,0 +1,74 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### CLOCK DEFINITION
+
+set EXTCLK "clk";
+set SWDCLK "swdclk";
+set_units -capacitance pF;
+set_units -power mW;
+set EXTCLK_PERIOD 4166.67;
+set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
+set CLK_ERROR 350; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
+set INTER_CLOCK_UNCERTAINTY 100
+
+### Power constraints
+set_max_dynamic_power 20
+set_max_leakage_power 0.1
+
+create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
+create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
+
+set_clock_uncertainty $CLK_ERROR [get_clocks $EXTCLK]
+set_clock_uncertainty $CLK_ERROR [get_clocks $SWDCLK]
+
+set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $SWDCLK] -rise_to [get_clocks $EXTCLK]
+set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $EXTCLK] -rise_to [get_clocks $SWDCLK]
+
+### Multicycle path through asynchronous clock domains
+set_multicycle_path 2 -setup -end -from SWDCK -to CLK
+set_multicycle_path 1 -hold -end -from SWDCK -to CLK
+set_multicycle_path 2 -setup -end -from CLK -to SWDCK
+set_multicycle_path 1 -hold -end -from CLK -to SWDCK
+
+set_false_path -hold -from CLK -to SWDCK
+
+### Multicycle path through pads
+set_false_path -through uPAD_SWDIO_IO
+set_multicycle_path 2 -through uPAD_SWDIO_IO
+#set_false_path -through uPAD_P0_*
+#set_false_path -through uPAD_P1_*
+
+set_multicycle_path 2 -from uPAD_SWDIO_IO/I -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/IE -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/DS -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/OEN -to uPAD_SWDIO_IO/C
+
+set_multicycle_path 2 -from uPAD_P0_*/I -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/IE -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/DS -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/OEN -to uPAD_P0_*/C
+
+set_multicycle_path 2 -from uPAD_P1_*/I -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/IE -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/DS -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/OEN -to uPAD_P1_*/C
+
+#### DELAY DEFINITION
+
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 100 [get_ports NRST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 100 [get_ports TEST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 100 [get_ports P0]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 100 [get_ports P1]
+set_input_delay -clock [get_clocks $SWDCLK] -add_delay 200 [get_ports SWDIO]
+
+set_max_capacitance 3 [all_outputs]
+set_max_fanout 10 [all_inputs]
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/nanosoc.upf b/ASIC/TSMC16nm/28pin/Synopsys_FC/inputs/nanosoc.upf
new file mode 100644
index 0000000..e69de29
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/makefile b/ASIC/TSMC16nm/28pin/Synopsys_FC/makefile
new file mode 100644
index 0000000..64941d5
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/makefile
@@ -0,0 +1,17 @@
+LIB_DIR := ./libs
+WORK_DIR := ./work
+REPORTS_DIR := $(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+LOG_DIR := $(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+
+gen_fusion_libs:
+ @mkdir -p $(LIB_DIR)
+ @(cd $(LIB_DIR); \
+ lc_shell;)
+
+fusion_design_setup:
+ @mkdir -p $(REPORTS_DIR)
+ @mkdir -p $(LOG_DIR)
+ @mkdir -p $(WORK_DIR)
+ @(cd $(WORK_DIR); \
+ fc_shell -f ../scripts/1_design_setup.tcl;)
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/1_design_setup.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/1_design_setup.tcl
new file mode 100644
index 0000000..4aa2ce2
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/1_design_setup.tcl
@@ -0,0 +1,35 @@
+# Import verilog and setup libraries
+
+set_host_options -max_cores 8 -num_processes 8
+
+# Set paths !!! Please edit for your system !!!
+set cln16fcll_tech_path /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0
+
+set cln16fcll_tech_file $cln16fcll_tech_path/ndm/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_tech.tf
+set TLU_dir $cln16fcll_tech_path/synopsys_tluplus/9m_2xa1xd3xe2z_utrdl
+
+set TLU_cbest $TLU_dir/cbest.tluplus
+set TLU_cworst $TLU_dir/cworst.tluplus
+set TLU_rcbest $TLU_dir/rcbest.tluplus
+set TLU_rcworst $TLU_dir/rcworst.tluplus
+set TLU_map $TLU_dir/tluplus.map
+
+#Create the design library
+create_lib nanosoc_chip_pads.dlib \
+ -technology $cln16fcll_tech_file \
+ -ref_libs {../libs/cln16fcll ../libs/arm_io_lib ../libs/SRAM_32K ../libs/ROM_VIA}
+
+
+# Read in the verilog for
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc16fcll/nanosoc_chip_pads_28pin.v
+
+elaborate nanosoc_chip_pads
+set_top_module nanosoc_chip_pads
+
+read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map
+read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map
+read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map
+read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map
+
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/2_floorplan.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/2_floorplan.tcl
new file mode 100644
index 0000000..30265a3
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/2_floorplan.tcl
@@ -0,0 +1,49 @@
+set_host_options -max_cores 8 -num_processes 8
+
+open_lib nanosoc_chip_pads.dlib
+open_block nanosoc_chip_pads
+
+initialize_floorplan -control_type die -use_site_row -side_length {1020.384 1020.384} -core_offset 99.984
+source ../floorplan/floorplan.tcl
+
+create_io_ring -corner_height 74.496
+
+#source ./io_plan.tcl
+
+read_sdc ../inputs/constraints.sdc
+
+load_upf ../inputs/nanosoc.upf
+
+#source ./power_plan.tcl
+connect_pg_net -create_nets_only
+connect_pg_net -automatic
+
+create_pg_ring_pattern ring_pattern -nets {VDD VSS} -horizontal_layer M8 -vertical_layer M9 -horizontal_width {5} -vertical_width {5} -horizontal_spacing {2} -vertical_spacing {2}
+set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core
+compile_pg -strategies core_ring -ignore_drc
+
+create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M5} {width: 4} {pitch: 30.566} {offset: 21.5}} {{horizontal_layer: M6} {width: 4} {pitch: 30} {offset: 20}}} -via_rule {{intersection : all}}
+set_pg_strategy M5M6_mesh -core -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} \
+ -extension {{stop : first_target}}
+compile_pg -strategies M5M6_mesh -ignore_drc
+
+create_pg_std_cell_conn_pattern std_pattern -layers {M2} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.14 0.14}
+set_pg_strategy std_cell_strat -pattern {{name: std_pattern} {nets: {VDD VSS}}} -core
+compile_pg -strategies std_cell_strat -ignore_drc
+
+place_io
+create_cell {CORNER1 CORNER2 CORNER3 CORNER4} /home/dwn1c21/SoC-Labs/TAPEOUT/nov2025/accelerator-project/nanosoc_tech/ASIC/TSMC16nm/28pin/Synopsys_FC/libs/arm_io_lib:PCORNER_18_18_NT_DR.timing
+
+# source ./init_placement.tcl
+source /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0/ndm/9m_2xa1xd3xe2z_utrdl/antenna_rules.tcl
+source /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0/ndm/9m_2xa1xd3xe2z_utrdl/icc2_route_options.tcl
+source /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0/ndm/9m_2xa1xd3xe2z_utrdl/icc2_rvi_mapping.tcl
+source /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0/ndm/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_icc2_route_options.tcl
+source /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0/ndm/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_icc2_routing_tracks.tcl
+
+set_voltage -min 0.88 -corners default -object_list [get_supply_nets {VDD}] 0.72
+set_voltage -min 0.0 -corners default -object_list [get_supply_nets {VSS}] 0.0
+
+save_block
+save_lib nanosoc_chip_pads.dlib
+close_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/3_synthesis.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/3_synthesis.tcl
new file mode 100644
index 0000000..c271da1
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/3_synthesis.tcl
@@ -0,0 +1,26 @@
+set_host_options -max_cores 16 -num_processes 16
+set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+current_corner default
+set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125 -library nanosoc_chip_pads.dlib
+set_operating_conditions -max_library cln16fcll -max ffgnp_cbestccbestt_min_0p88v_m40c -min_library cln16fcll -min ssgnp_cworstccworstt_max_0p72v_125c
+set_process_number -early 1 -late 1 -corners default
+set_temperature -min -40 -corners default 125
+set_voltage 0.72 -min 0.88 -corners default
+
+
+# Compile fusion takes about 6.5 hrs to run
+compile_fusion
+save_lib nanosoc_chip_pads.dlib
+
+redirect -tee -file $REPORT_DIR/timing_03a_compile_fusion_max.rep {report_timing -delay_type max}
+redirect -tee -file $REPORT_DIR/timing_03a_compile_fusion_min.rep {report_timing -delay_type min}
+
+place_opt
+
+redirect -tee -file $REPORT_DIR/timing_03b_place_opt_max.rep {report_timing -delay_type max}
+redirect -tee -file $REPORT_DIR/timing_03b_place_opt_min.rep {report_timing -delay_type min}
+
+
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/4_cts.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/4_cts.tcl
new file mode 100644
index 0000000..68f1d35
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/4_cts.tcl
@@ -0,0 +1,23 @@
+set_host_options -max_cores 16 -num_processes 16
+set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+
+synthesize_clock_trees
+check_clock_trees
+
+report_timing
+
+redirect -tee -file $REPORT_DIR/timing_04a_CTS_max.rep {report_timing -delay_type max}
+redirect -tee -file $REPORT_DIR/timing_04a_CTS_min.rep {report_timing -delay_type min}
+
+save_lib nanosoc_chip_pads.dlib
+
+clock_opt
+
+report_timing
+
+redirect -tee -file $REPORT_DIR/timing_04b_Clockopt_max.rep {report_timing -delay_type max}
+redirect -tee -file $REPORT_DIR/timing_04b_Clockopt_min.rep {report_timing -delay_type min}
+
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/5_route.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/5_route.tcl
new file mode 100644
index 0000000..54c32e0
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/5_route.tcl
@@ -0,0 +1,9 @@
+set_host_options -max_cores 16 -num_processes 16
+set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+
+route_auto
+
+redirect -tee -file $REPORT_DIR/timing_05_route_auto_max.rep {report_timing -delay_type max}
+redirect -tee -file $REPORT_DIR/timing_05_route_auto_min.rep {report_timing -delay_type min}
diff --git a/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/synopsys_library_setup.tcl b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/synopsys_library_setup.tcl
new file mode 100644
index 0000000..cd06c28
--- /dev/null
+++ b/ASIC/TSMC16nm/28pin/Synopsys_FC/scripts/synopsys_library_setup.tcl
@@ -0,0 +1,96 @@
+## Paths Please Edit for your system
+set cln16fcll_tech_path /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/arm_tech/r3p0
+set standard_cell_base_path /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/sc9mcpp96c_base_svt_c24/r2p0
+set arm_io_base_path /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/io_gppr_t18_mv08_fs18_rvt_dr/r1p3
+set pmk_base_path /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/sc9mcpp96c_pmk_svt_c24/r2p0
+set ret_base_path /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/sc9mcpp96c_rklo_lvt_svt_c20_c24/r1p0
+
+# Technology files
+set cln16fcll_tech_file $cln16fcll_tech_path/ndm/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_tech.tf
+set cln16fcll_lef_file $cln16fcll_tech_path/lef/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_tech.lef
+
+# Standard Cell libraries
+set standard_cell_lef_file $standard_cell_base_path/lef/sc9mcpp96c_cln16fcll001_base_svt_c24.lef
+set standard_cell_gds_file $standard_cell_base_path/gds2/sc9mcpp96c_cln16fcll001_base_svt_c24.gds2
+set standard_cell_db_file_ss_0p72v_125C $standard_cell_base_path/db/sc9mcpp96c_cln16fcll001_base_svt_c24_ssgnp_cworstccworstt_max_0p72v_125c.db
+set standard_cell_db_file_tt_0p80v_25C $standard_cell_base_path/db/sc9mcpp96c_cln16fcll001_base_svt_c24_tt_typical_max_0p80v_25c.db
+set standard_cell_db_file_ff_0p88v_m40C $standard_cell_base_path/db/sc9mcpp96c_cln16fcll001_base_svt_c24_ffgnp_cbestccbestt_min_0p88v_m40c.db
+set standard_cell_antenna_file $standard_cell_base_path/milkyway/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_cln16fcll001_base_svt_c24_antenna.clf
+
+# Arm IO Library
+set arm_io_lef_file $arm_io_base_path/lef/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_9m_2xa1xd3xe2z_fc.lef
+set arm_io_gds_file $arm_io_base_path/gds2/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_9m_2xa1xd3xe2z_fc.gds2
+set arm_io_db_file_ss_0p72v_125C $arm_io_base_path/db/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_ssgnp_cworstccworstt_0p72v_1p62v_125c.db
+set arm_io_db_file_tt_0p80v_25C $arm_io_base_path/db/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_tt_typical_0p80v_1p80v_25c.db
+set arm_io_db_file_ff_0p88v_m40C $arm_io_base_path/db/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_ffgnp_cbestccbestt_0p88v_1p98v_m40c.db
+set arm_io_antenna_file $arm_io_base_path/milkyway/9m_2xa1xd3xe2z_fc/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_antenna.clf
+
+# 32K SRAM PATHS
+set SRAM_32K_PATH $env(SOCLABS_PROJECT_DIR)/memories/sram_32k
+set SRAM_32K_lef_file $SRAM_32K_PATH/sram_32k.lef
+set SRAM_32K_gds_file $SRAM_32K_PATH/sram_32k.gds2
+set SRAM_32K_lib_file_ss $SRAM_32K_PATH/sram_32k_ssgnp_0p72v_0p72v_125c.lib
+set SRAM_32K_lib_file_tt $SRAM_32K_PATH/sram_32k_tt_0p80v_0p80v_25c.lib
+set SRAM_32K_lib_file_ff $SRAM_32K_PATH/sram_32k_ffgnp_0p88v_0p88v_m40c.lib
+set SRAM_32K_db_file_ss $SRAM_32K_PATH/sram_32k_ssgnp_0p72v_0p72v_125c.db
+set SRAM_32K_db_file_tt $SRAM_32K_PATH/sram_32k_tt_0p80v_0p80v_25c.db
+set SRAM_32K_db_file_ff $SRAM_32K_PATH/sram_32k_ffgnp_0p88v_0p88v_m40c.db
+
+# ROM PATHS
+set ROM_VIA_PATH $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+set ROM_VIA_lef_file $ROM_VIA_PATH/rom_via.lef
+set ROM_VIA_gds_file $ROM_VIA_PATH/rom_via.gds2
+set ROM_VIA_lib_file_ss $ROM_VIA_PATH/rom_via_ssgnp_0p72v_0p72v_125c.lib
+set ROM_VIA_lib_file_tt $ROM_VIA_PATH/rom_via_tt_0p80v_0p80v_25c.lib
+set ROM_VIA_lib_file_ff $ROM_VIA_PATH/rom_via_ffgnp_0p88v_0p88v_m40c.lib
+set ROM_VIA_db_file_ss $ROM_VIA_PATH/rom_via_ssgnp_0p72v_0p72v_125c.db
+set ROM_VIA_db_file_tt $ROM_VIA_PATH/rom_via_tt_0p80v_0p80v_25c.db
+set ROM_VIA_db_file_ff $ROM_VIA_PATH/rom_via_ffgnp_0p88v_0p88v_m40c.db
+
+# 32K SRAMs
+read_lib $SRAM_32K_lib_file_ss
+write_lib -output $SRAM_32K_db_file_ss -format db sram_32k_ssgnp_0p72v_0p72v_125c
+close_lib -all
+
+read_lib $SRAM_32K_lib_file_tt
+write_lib -output $SRAM_32K_db_file_tt -format db sram_32k_tt_0p80v_0p80v_25c
+close_lib -all
+
+read_lib $SRAM_32K_lib_file_ff
+write_lib -output $SRAM_32K_db_file_ff -format db sram_32k_ffgnp_0p88v_0p88v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $SRAM_32K_db_file_ss $SRAM_32K_db_file_tt $SRAM_32K_db_file_ff] -lefs $SRAM_32K_lef_file -technology $cln16fcll_tech_file SRAM_32K
+save_fusion_lib SRAM_32K
+close_fusion_lib SRAM_32K
+
+# ROM VIA
+read_lib $ROM_VIA_lib_file_ss
+write_lib -output $ROM_VIA_db_file_ss -format db rom_via_ssgnp_0p72v_0p72v_125c
+close_lib -all
+
+read_lib $ROM_VIA_lib_file_tt
+write_lib -output $ROM_VIA_db_file_tt -format db rom_via_tt_0p80v_0p80v_25c
+close_lib -all
+
+read_lib $ROM_VIA_lib_file_ff
+write_lib -output $ROM_VIA_db_file_ff -format db rom_via_ffgnp_0p88v_0p88v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $ROM_VIA_db_file_ss $ROM_VIA_db_file_tt $ROM_VIA_db_file_ff] -lefs $ROM_VIA_lef_file -technology $cln16fcll_tech_file ROM_VIA
+save_fusion_lib ROM_VIA
+close_fusion_lib ROM_VIA
+
+
+
+# Create standard cell fusion library
+create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p72v_125C $standard_cell_db_file_tt_0p80v_25C $standard_cell_db_file_ff_0p88v_m40C] -lefs [list $cln16fcll_lef_file $standard_cell_lef_file] -technology $cln16fcll_tech_file cln16fcll
+save_fusion_lib cln16fcll
+close_fusion_lib cln16fcll
+
+# Create Arm IO Library
+create_fusion_lib -dbs [list $arm_io_db_file_ss_0p72v_125C $arm_io_db_file_tt_0p80v_25C $arm_io_db_file_ff_0p88v_m40C] -lefs [list $cln16fcll_lef_file $arm_io_lef_file] -technology $cln16fcll_tech_file arm_io_lib
+save_fusion_lib arm_io_lib
+close_fusion_lib arm_io_lib
+
+exit
\ No newline at end of file
diff --git a/ASIC/TSMC16nm/rom_via.spec b/ASIC/TSMC16nm/rom_via.spec
new file mode 100644
index 0000000..a7d1046
--- /dev/null
+++ b/ASIC/TSMC16nm/rom_via.spec
@@ -0,0 +1,37 @@
+# user spec file, compiler rom_via_hdd_lvt_mvt, version r1p1
+
+EOL_guardband = 0
+activity_factor = 10
+back_biasing = off
+bits = 32
+bmux = on
+bus_notation = on
+check_instname = on
+code_file = bootrom.rcf
+corners = ffgnp_0p88v_0p88v_125c,ffgnp_0p88v_0p88v_m40c,ssgnp_0p72v_0p72v_125c,ssgnp_0p72v_0p72v_m40c,tt_0p80v_0p80v_25c,tt_0p80v_0p80v_85c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+fci_type = not_fci
+frequency = 500
+instname = rom_via
+irem_gds2_by_phyvtools = 0
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = rom_via
+metal_stack = 2Xa1Xd
+mode = addr
+mux = 8
+mvt = LP
+name_case = upper
+pipeline = off
+power_gating = on
+power_type = otc
+prefix =
+pwr_gnd_rename = vdde:VDDE,vsse:VSSE
+right_bus_delim = ]
+rows_p_bl = 128
+site_def = on
+top_layer = m5-m10
+words = 256
diff --git a/ASIC/TSMC16nm/sram_32k.spec b/ASIC/TSMC16nm/sram_32k.spec
new file mode 100644
index 0000000..7bb01b3
--- /dev/null
+++ b/ASIC/TSMC16nm/sram_32k.spec
@@ -0,0 +1,50 @@
+# user spec file, compiler sram_sp_hde_svt_mvt, version r4p1
+
+EOL_guardband = 0
+PG_PINS_domain = VDDPE
+activity_factor = 10
+atf = off
+back_biasing = off
+bits = 32
+bmux = off
+bus_notation = on
+check_instname = on
+compiler_type = sp
+corners = ffgnp_0p88v_0p88v_125c,ffgnp_0p88v_0p88v_m40c,ssgnp_0p72v_0p72v_125c,ssgnp_0p72v_0p72v_m40c,tt_0p80v_0p80v_25c,tt_0p80v_0p80v_85c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+fci_type = not_fci
+flexible_banking = 4
+frequency = 500
+instname = sram_32k
+irem_gds2_by_phyvtools = 0
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = sram_32k
+lren_bankmask = off
+metal_stack = 2Xa1Xd
+mux = 8
+mvt = LP
+name_case = upper
+pipeline = off
+power_gating = off
+power_type = otc
+prefix =
+pwr_gnd_rename = vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+rcols = 2
+redundancy = off
+retention = on
+right_bus_delim = ]
+rows_p_bl = 256
+rrows = 0
+scan = off
+scan_type = pseudo
+ser = none
+site_def = off
+vmin_assist = off
+words = 8192
+wp_size = 1
+write_mask = on
+write_thru = off
diff --git a/ASIC/nanosoc_chip_pads/tsmc16fcll/nanosoc_chip_pads_28pin.v b/ASIC/nanosoc_chip_pads/tsmc16fcll/nanosoc_chip_pads_28pin.v
new file mode 100644
index 0000000..116eaa7
--- /dev/null
+++ b/ASIC/nanosoc_chip_pads/tsmc16fcll/nanosoc_chip_pads_28pin.v
@@ -0,0 +1,307 @@
+//-----------------------------------------------------------------------------
+// Top-Level Pad implementation for TSMC65nm
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+module nanosoc_chip_pads (
+ inout wire VDDIO,
+ inout wire VDD,
+ inout wire VSS,
+ inout wire VDDACC,
+
+ input wire CLK, // input
+ input wire TEST, // input
+ input wire NRST, // active low reset
+ inout wire [3:0] P0,
+ inout wire [3:0] P1,
+ inout wire SWDIO,
+ input wire SWDCK
+);
+
+
+//------------------------------------
+// internal wires
+
+ wire clk_i;
+ wire test_i;
+ wire nrst_i;
+ wire [15:0] p0_i; // level-shifted input from pad
+ wire [15:0] p0_o; // output port drive
+ wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_i; // level-shifted input from pad
+ wire [15:0] p1_o; // output port drive
+ wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
+
+ wire swdio_i;
+ wire swdio_o;
+ wire swdio_e;
+ wire swdio_z;
+ wire swdclk_i;
+ wire VSSIO;
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0 nanosoc Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip u_nanosoc_chip (
+`ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ .VDDACC (VDDACC),
+`endif
+ .clk_i(clk_i),
+ .test_i(test_i),
+ .nrst_i(nrst_i),
+ .p0_i(p0_i), // level-shifted input from pad
+ .p0_o(p0_o), // output port drive
+ .p0_e(p0_e), // active high output drive enable (pad tech dependent)
+ .p0_z(p0_z), // active low output drive enable (pad tech dependent)
+ .p1_i(p1_i), // level-shifted input from pad
+ .p1_o(p1_o), // output port drive
+ .p1_e(p1_e), // active high output drive enable (pad tech dependent)
+ .p1_z(p1_z), // active low output drive enable (pad tech dependent)
+ .swdio_i(swdio_i),
+ .swdio_o(swdio_o),
+ .swdio_e(swdio_e),
+ .swdio_z(swdio_z),
+ .swdclk_i(swdclk_i)
+ );
+
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+ // --------------------------------------------------------------------------------
+ // IO pad (TSMC 65nm mapping)
+ // --------------------------------------------------------------------------------
+
+// Pad IO power supplies
+
+PDVDD_18_18_NT_DR_H uPAD_VDDIO_0(
+ );
+PDVDD_18_18_NT_DR_H uPAD_VDDIO_1(
+ );
+PDVDD_18_18_NT_DR_H uPAD_VDDIO_2(
+ );
+PDVDD_18_18_NT_DR_H uPAD_VDDIO_3(
+ );
+
+
+
+// Core power supplies
+
+PVDD_08_08_NT_DR_H uPAD_VDD_0(
+ .VDD(VDD)
+ );
+PVDD_08_08_NT_DR_H uPAD_VDD_1(
+ .VDD(VDD)
+ );
+PVDD_08_08_NT_DR_H uPAD_VDD_2(
+ .VDD(VDD)
+ );
+PVDD_08_08_NT_DR_H uPAD_VDD_3(
+ .VDD(VDD)
+ );
+
+PVSS_08_08_NT_DR_H uPAD_VSS_0(
+ .VSS(VSS)
+ );
+PVSS_08_08_NT_DR_H uPAD_VSS_1(
+ .VSS(VSS)
+ );
+PVSS_08_08_NT_DR_H uPAD_VSS_2(
+ .VSS(VSS)
+ );
+PVSS_08_08_NT_DR_H uPAD_VSS_3(
+ .VSS(VSS)
+ );
+// Accelerator Power supplies
+PVDD_08_08_NT_DR_H uPAD_VDDACC_0(
+ .VDD(VDDACC)
+ );
+PVDD_08_08_NT_DR_H uPAD_VDDACC_1(
+ .VDD(VDDACC)
+ );
+PVDD_08_08_NT_DR_H uPAD_VDDACC_2(
+ .VDD(VDDACC)
+ );
+
+// Clock, Reset and Serial Wire Debug ports
+
+PBIDIRN_18_18_FS_DR_H uPAD_CLK_I (
+ .IE(tiehi),
+ .Y(clk_i),
+ .PE(tielo),
+ .A(tielo),
+ .PAD(CLK)
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_TEST_I (
+ .IE(tiehi),
+ .Y(test_i),
+ .PE(tielo),
+ .A(tielo),
+ .PAD(TEST)
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_NRST_I (
+ .IE(tiehi),
+ .Y(nrst_i),
+ .PE(tielo),
+ .A(tielo),
+ .PAD(NRST)
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_SWDIO_IO (
+ .IE(swdio_z),
+ .Y(swdio_i),
+ .PE(tielo),
+ .A(swdio_o),
+ .PAD(SWDIO)
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_SWDCK_I (
+ .IE(tiehi),
+ .Y(swdclk_i),
+ .PE(tielo),
+ .A(tielo),
+ .PAD(SWDCK)
+ );
+
+// GPI.I Port 0 x 16
+
+PBIDIRN_18_18_FS_DR_H uPAD_P0_00 (
+ .IE(p0_z[00]),
+ .Y(p0_i[00]),
+ .PE(p0_z[00]&p0_o[00]),
+ .A(p0_o[00]),
+ .PAD(P0[00])
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_P0_01 (
+ .IE(p0_z[01]),
+ .Y(p0_i[01]),
+ .PE(p0_z[01]&p0_o[01]),
+ .A(p0_o[01]),
+ .PAD(P0[01])
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_P0_02 (
+ .IE(p0_z[02]),
+ .Y(p0_i[02]),
+ .PE(p0_z[02]&p0_o[02]),
+ .A(p0_o[02]),
+ .PAD(P0[02])
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_P0_03 (
+ .IE(p0_z[03]),
+ .Y(p0_i[03]),
+ .PE(p0_z[03]&p0_o[03]),
+ .A(p0_o[03]),
+ .PAD(P0[03])
+ );
+// GPI.I Port 1 x 16
+
+PBIDIRN_18_18_FS_DR_H uPAD_P1_00 (
+ .IE(p1_z[00]),
+ .Y(p1_i[00]),
+ .PE(p1_z[00]&p1_o[00]),
+ .A(p1_o[00]),
+ .PAD(P1[00])
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_P1_01 (
+ .IE(p1_z[01]),
+ .Y(p1_i[01]),
+ .PE(p1_z[01]&p1_o[01]),
+ .A(p1_o[01]),
+ .PAD(P1[01])
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_P1_02 (
+ .IE(p1_z[02]),
+ .Y(p1_i[02]),
+ .PE(p1_z[02]&p1_o[02]),
+ .A(p1_o[02]),
+ .PAD(P1[02])
+ );
+
+PBIDIRN_18_18_FS_DR_H uPAD_P1_03 (
+ .IE(p1_z[03]),
+ .Y(p1_i[03]),
+ .PE(p1_z[03]&p1_o[03]),
+ .A(p1_o[03]),
+ .PAD(P1[03])
+ );
+
+
+// GPIO unused pin tie offs
+
+assign p0_i[4] = p0_o[4] & p0_e[4];
+assign p0_i[5] = p0_o[5] & p0_e[5];
+assign p0_i[6] = p0_o[6] & p0_e[6];
+assign p0_i[7] = p0_o[7] & p0_e[7];
+assign p0_i[8] = p0_o[8] & p0_e[8];
+assign p0_i[9] = p0_o[9] & p0_e[9];
+assign p0_i[10] = p0_o[10] & p0_e[10];
+assign p0_i[11] = p0_o[11] & p0_e[11];
+assign p0_i[12] = p0_o[12] & p0_e[12];
+assign p0_i[13] = p0_o[13] & p0_e[13];
+assign p0_i[14] = p0_o[14] & p0_e[14];
+assign p0_i[15] = p0_o[15] & p0_e[15];
+
+assign p1_i[4] = p1_o[4] & p1_e[4];
+assign p1_i[5] = p1_o[5] & p1_e[5];
+assign p1_i[6] = p1_o[6] & p1_e[6];
+assign p1_i[7] = p1_o[7] & p1_e[7];
+assign p1_i[8] = p1_o[8] & p1_e[8];
+assign p1_i[9] = p1_o[9] & p1_e[9];
+assign p1_i[10] = p1_o[10] & p1_e[10];
+assign p1_i[11] = p1_o[11] & p1_e[11];
+assign p1_i[12] = p1_o[12] & p1_e[12];
+assign p1_i[13] = p1_o[13] & p1_e[13];
+assign p1_i[14] = p1_o[14] & p1_e[14];
+assign p1_i[15] = p1_o[15] & p1_e[15];
+
+
+endmodule
+
+
+
diff --git a/flows/makefile.asic b/flows/makefile.asic
index 0218064..ba4bd93 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -46,6 +46,7 @@ RF_16K_DIR := $(MEMORIES_DIR)/rf_16k
RF_08K_DIR := $(MEMORIES_DIR)/rf_08k
ROM_DIR := $(MEMORIES_DIR)/bootrom
SRAM_16K_DIR := $(MEMORIES_DIR)/sram_16k
+SRAM_32K_DIR := $(MEMORIES_DIR)/sram_32k
REPORTS_FOLDER := $(IMP_NANOSOC_ASIC_DIR)/reports
SYN_LOGS := $(IMP_NANOSOC_ASIC_DIR)/logs
@@ -133,6 +134,11 @@ gen_memories_backend_28nm: bootrom
gen_memories_28nm: gen_memories_frontend_28nm gen_memories_backend_28nm
+gen_memories_16nm:
+ @mkdir -p $(MEMORIES_DIR)
+ @mkdir -p $(SRAM_32K_DIR)
+ @mkdir -p $(ROM_DIR)
+
convert_mem_to_db:
lc_shell -no_log -f $(NANOSOC_SYNTH_DIR)/synopsys_lib_conversion.tcl
diff --git a/makefile b/makefile
index e4eb5e5..1fb3308 100644
--- a/makefile
+++ b/makefile
@@ -165,6 +165,18 @@ ifdef SNPS_PVT_VM_0_INCLUDE
endif
+# ASIC MEMORY INCLUSION
+ifeq ($(ASIC),yes)
+ ifeq ($(NODE),16)
+ FLIST_INCLUDES += $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_ip_TSMC16nm.flist
+ else ifeq ($(NODE),28)
+ FLIST_INCLUDES += $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_ip_TSMC28nm.flist
+ else
+ FLIST_INCLUDES += $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_ip.flist
+ endif
+endif
+
+
# System Design Filelist
ifeq ($(QUICKSTART),yes)
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
diff --git a/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v b/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
index 96049ac..1de2acd 100644
--- a/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
+++ b/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
@@ -86,8 +86,8 @@ module nanosoc_pin_mux (
// input wire i_swdoen,
// IO pads
- inout wire [15:0] P0, // legacy
- inout wire [15:0] P1, // legacy
+ //inout wire [15:0] P0, // legacy
+ //inout wire [15:0] P1, // legacy
output wire [15:0] p1_out_mux, //alt-function mux
output wire [15:0] p1_out_en_mux //alt-function mux
@@ -117,8 +117,8 @@ module nanosoc_pin_mux (
assign timer0_extin = p1_in[8];
assign timer1_extin = p1_in[9];
- assign p0_in = P0;
- assign p1_in = P1;
+ //assign p0_in = P0;
+ //assign p1_in = P1;
// Output function mux
assign p0_out_mux = p0_out; // No function muxing for Port 0
@@ -155,39 +155,39 @@ module nanosoc_pin_mux (
// Output tristate
- assign P0[ 0] = p0_out_en_mux[ 0] ? p0_out_mux[ 0] : 1'bz;
- assign P0[ 1] = p0_out_en_mux[ 1] ? p0_out_mux[ 1] : 1'bz;
- assign P0[ 2] = p0_out_en_mux[ 2] ? p0_out_mux[ 2] : 1'bz;
- assign P0[ 3] = p0_out_en_mux[ 3] ? p0_out_mux[ 3] : 1'bz;
- assign P0[ 4] = p0_out_en_mux[ 4] ? p0_out_mux[ 4] : 1'bz;
- assign P0[ 5] = p0_out_en_mux[ 5] ? p0_out_mux[ 5] : 1'bz;
- assign P0[ 6] = p0_out_en_mux[ 6] ? p0_out_mux[ 6] : 1'bz;
- assign P0[ 7] = p0_out_en_mux[ 7] ? p0_out_mux[ 7] : 1'bz;
- assign P0[ 8] = p0_out_en_mux[ 8] ? p0_out_mux[ 8] : 1'bz;
- assign P0[ 9] = p0_out_en_mux[ 9] ? p0_out_mux[ 9] : 1'bz;
- assign P0[10] = p0_out_en_mux[10] ? p0_out_mux[10] : 1'bz;
- assign P0[11] = p0_out_en_mux[11] ? p0_out_mux[11] : 1'bz;
- assign P0[12] = p0_out_en_mux[12] ? p0_out_mux[12] : 1'bz;
- assign P0[13] = p0_out_en_mux[13] ? p0_out_mux[13] : 1'bz;
- assign P0[14] = p0_out_en_mux[14] ? p0_out_mux[14] : 1'bz;
- assign P0[15] = p0_out_en_mux[15] ? p0_out_mux[15] : 1'bz;
-
- assign P1[ 0] = p1_out_en_mux[ 0] ? p1_out_mux[ 0] : 1'bz;
- assign P1[ 1] = p1_out_en_mux[ 1] ? p1_out_mux[ 1] : 1'bz;
- assign P1[ 2] = p1_out_en_mux[ 2] ? p1_out_mux[ 2] : 1'bz;
- assign P1[ 3] = p1_out_en_mux[ 3] ? p1_out_mux[ 3] : 1'bz;
- assign P1[ 4] = p1_out_en_mux[ 4] ? p1_out_mux[ 4] : 1'bz;
- assign P1[ 5] = p1_out_en_mux[ 5] ? p1_out_mux[ 5] : 1'bz;
- assign P1[ 6] = p1_out_en_mux[ 6] ? p1_out_mux[ 6] : 1'bz;
- assign P1[ 7] = p1_out_en_mux[ 7] ? p1_out_mux[ 7] : 1'bz;
- assign P1[ 8] = p1_out_en_mux[ 8] ? p1_out_mux[ 8] : 1'bz;
- assign P1[ 9] = p1_out_en_mux[ 9] ? p1_out_mux[ 9] : 1'bz;
- assign P1[10] = p1_out_en_mux[10] ? p1_out_mux[10] : 1'bz;
- assign P1[11] = p1_out_en_mux[11] ? p1_out_mux[11] : 1'bz;
- assign P1[12] = p1_out_en_mux[12] ? p1_out_mux[12] : 1'bz;
- assign P1[13] = p1_out_en_mux[13] ? p1_out_mux[13] : 1'bz;
- assign P1[14] = p1_out_en_mux[14] ? p1_out_mux[14] : 1'bz;
- assign P1[15] = p1_out_en_mux[15] ? p1_out_mux[15] : 1'bz;
+ //assign P0[ 0] = p0_out_en_mux[ 0] ? p0_out_mux[ 0] : 1'bz;
+ //assign P0[ 1] = p0_out_en_mux[ 1] ? p0_out_mux[ 1] : 1'bz;
+ //assign P0[ 2] = p0_out_en_mux[ 2] ? p0_out_mux[ 2] : 1'bz;
+ //assign P0[ 3] = p0_out_en_mux[ 3] ? p0_out_mux[ 3] : 1'bz;
+ //assign P0[ 4] = p0_out_en_mux[ 4] ? p0_out_mux[ 4] : 1'bz;
+ //assign P0[ 5] = p0_out_en_mux[ 5] ? p0_out_mux[ 5] : 1'bz;
+ //assign P0[ 6] = p0_out_en_mux[ 6] ? p0_out_mux[ 6] : 1'bz;
+ //assign P0[ 7] = p0_out_en_mux[ 7] ? p0_out_mux[ 7] : 1'bz;
+ //assign P0[ 8] = p0_out_en_mux[ 8] ? p0_out_mux[ 8] : 1'bz;
+ //assign P0[ 9] = p0_out_en_mux[ 9] ? p0_out_mux[ 9] : 1'bz;
+ //assign P0[10] = p0_out_en_mux[10] ? p0_out_mux[10] : 1'bz;
+ //assign P0[11] = p0_out_en_mux[11] ? p0_out_mux[11] : 1'bz;
+ //assign P0[12] = p0_out_en_mux[12] ? p0_out_mux[12] : 1'bz;
+ //assign P0[13] = p0_out_en_mux[13] ? p0_out_mux[13] : 1'bz;
+ //assign P0[14] = p0_out_en_mux[14] ? p0_out_mux[14] : 1'bz;
+ //assign P0[15] = p0_out_en_mux[15] ? p0_out_mux[15] : 1'bz;
+//
+ //assign P1[ 0] = p1_out_en_mux[ 0] ? p1_out_mux[ 0] : 1'bz;
+ //assign P1[ 1] = p1_out_en_mux[ 1] ? p1_out_mux[ 1] : 1'bz;
+ //assign P1[ 2] = p1_out_en_mux[ 2] ? p1_out_mux[ 2] : 1'bz;
+ //assign P1[ 3] = p1_out_en_mux[ 3] ? p1_out_mux[ 3] : 1'bz;
+ //assign P1[ 4] = p1_out_en_mux[ 4] ? p1_out_mux[ 4] : 1'bz;
+ //assign P1[ 5] = p1_out_en_mux[ 5] ? p1_out_mux[ 5] : 1'bz;
+ //assign P1[ 6] = p1_out_en_mux[ 6] ? p1_out_mux[ 6] : 1'bz;
+ //assign P1[ 7] = p1_out_en_mux[ 7] ? p1_out_mux[ 7] : 1'bz;
+ //assign P1[ 8] = p1_out_en_mux[ 8] ? p1_out_mux[ 8] : 1'bz;
+ //assign P1[ 9] = p1_out_en_mux[ 9] ? p1_out_mux[ 9] : 1'bz;
+ //assign P1[10] = p1_out_en_mux[10] ? p1_out_mux[10] : 1'bz;
+ //assign P1[11] = p1_out_en_mux[11] ? p1_out_mux[11] : 1'bz;
+ //assign P1[12] = p1_out_en_mux[12] ? p1_out_mux[12] : 1'bz;
+ //assign P1[13] = p1_out_en_mux[13] ? p1_out_mux[13] : 1'bz;
+ //assign P1[14] = p1_out_en_mux[14] ? p1_out_mux[14] : 1'bz;
+ //assign P1[15] = p1_out_en_mux[15] ? p1_out_mux[15] : 1'bz;
/*
// synopsys translate_off
diff --git a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 18ca5fe..2780844 100644
--- a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -239,9 +239,9 @@ module nanosoc_ss_systemctrl #(
// IO pads
.p1_out_mux (P1_OUT_MUX),
- .p1_out_en_mux (P1_OUT_EN_MUX),
- .P0 ( ), //P0),
- .P1 ( ) //P1),
+ .p1_out_en_mux (P1_OUT_EN_MUX)
+ // .P0 ( ), //P0),
+ // .P1 ( ) //P1),
// .nTRST (1'b1), // Not needed if serial-wire debug is used
// .TDI (1'b0), // Not needed if serial-wire debug is used
diff --git a/nanosoc/synopsys_28nm_slm_integration b/nanosoc/synopsys_28nm_slm_integration
index e88b3d4..4c4e598 160000
--- a/nanosoc/synopsys_28nm_slm_integration
+++ b/nanosoc/synopsys_28nm_slm_integration
@@ -1 +1 @@
-Subproject commit e88b3d4335b8416b5d78322f45e099ac9a12a1d0
+Subproject commit 4c4e598a2982a099f5871df1df2515068a288eab
--
GitLab