From 77ce3e1683e6f714a4c31e5071d19cacf82e772a Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Fri, 28 Apr 2023 22:01:44 +0100 Subject: [PATCH] SOC1-167: Updated CI Script to reflect refactoring changes --- .gitlab-ci.yml | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a712e8f..118d0ed 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -34,7 +34,7 @@ build-job-Z2: # This job runs in the build stage, which runs first. - cd ../DMA-230_MicroDMA_Controller/ - tar -xf PL230-r0p0-02rel2-1.tar.gz # move to fpga_imp directory and run the fpga build script for pynq z2 - - cd ../../nanosoc/systems/mcu/fpga_imp/ + - cd ../../nanosoc/system/fpga_imp/ - if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi - FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - if test -f "$FILE"; then @@ -49,9 +49,9 @@ build-job-Z2: # This job runs in the build stage, which runs first. artifacts: paths: # Keep the generated bit and hwh file from fpga build script - - ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - - ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh - - ./systems/mcu/fpga_imp/CI_verification/load_bitfile.py + - ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit + - ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh + - ./system/fpga_imp/CI_verification/load_bitfile.py tags: - Vivado2021.1 @@ -67,7 +67,7 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. - cd ../DMA-230_MicroDMA_Controller/ - tar -xf PL230-r0p0-02rel2-1.tar.gz # move to fpga_imp directory and run the fpga build script for pynq z2 - - cd ../../nanosoc/systems/mcu/fpga_imp/ + - cd ../../nanosoc/system/fpga_imp/ - if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi - FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - if test -f "$FILE"; then @@ -82,9 +82,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. artifacts: paths: # Keep the generated bit and hwh file from fpga build script - - ./systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - - ./systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh - - ./systems/mcu/fpga_imp/CI_verification/load_bitfile.py + - ./system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit + - ./system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh + - ./system/fpga_imp/CI_verification/load_bitfile.py tags: - VLAB-ZCU @@ -95,9 +95,9 @@ deploy-job-Z2: # This job runs in the deploy stage. - echo "Deploying application to Z2" # use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board # could probably set this up as scp with RSA keys in future - - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit ./design_1.bit' - - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh ./design_1.hwh' - - cd ./systems/mcu/fpga_imp/CI_verification + - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit ./design_1.bit' + - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh ./design_1.hwh' + - cd ./system/fpga_imp/CI_verification - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py' # get root access on host machine, this was found to be needed because other screen would not work # however a more elegant solution would be better @@ -148,11 +148,11 @@ deploy-job-ZCU104: # This job runs in the deploy stage. - screen -r zynq -X stuff "./ZCU104_connect.sh \n" - sleep 10 # use scp to copy over bit files and python script - - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py ./ \n" + - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/CI_verification/load_bitfile.py ./ \n" - sleep 2 - - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n" + - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n" - sleep 2 - - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n" + - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n" - sleep 2 # Need root access to load the overlay onto the FPGA - screen -r zynq -X stuff "sudo su\n" -- GitLab