diff --git a/fpga/makefile.targets b/fpga/makefile.targets
index 41b1ca313bda73e240777372e0cf78bfb147e948..a9509073b1e2df118938ec8c9c2a3eb93e4f77ab 100644
--- a/fpga/makefile.targets
+++ b/fpga/makefile.targets
@@ -18,6 +18,16 @@ else ifeq ($(FPGA),zcu104)
XILINX_PART := xczu7ev-ffvc1156-2-e
BOARD_NAME := pynq_zcu104
PLATFORM := pynq
+else ifeq ($(FPGA),kr260)
+# XILINX_PART := xck26-sfvc784-2LV-c
+ XILINX_PART := xczu5cg-sfvc784-2LV-e
+ BOARD_NAME := pynq_kr260
+ PLATFORM := pynq
+else ifeq ($(FPGA),kv260)
+# XILINX_PART := xck26-sfvc784-2LV-c
+ XILINX_PART := xczu5cg-sfvc784-2LV-e
+ BOARD_NAME := pynq_kv260
+ PLATFORM := pynq
else ifeq ($(FPGA),z2)
XILINX_PART := xc7z020clg400-1
BOARD_NAME := pynq_z2
@@ -26,4 +36,4 @@ else # Default to z2
XILINX_PART := xc7z020clg400-1
BOARD_NAME := pynq_z2
PLATFORM := pynq
-endif
\ No newline at end of file
+endif
diff --git a/fpga/targets/pynq_kr260/fpga_pinmap.xdc b/fpga/targets/pynq_kr260/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..480bfc2ecc2c5211fc038e1c425e14cb80519a10
--- /dev/null
+++ b/fpga/targets/pynq_kr260/fpga_pinmap.xdc
@@ -0,0 +1,290 @@
+##################################################################################
+## ##
+## KR260 IO subset XDC ##
+## ##
+##################################################################################
+
+######################## PMOD 1 Upper ########################
+set_property PACKAGE_PIN H12 [get_ports {PMOD0_0}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_0}]
+
+set_property PACKAGE_PIN E10 [get_ports {PMOD0_1}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_1}]
+
+set_property PACKAGE_PIN D10 [get_ports {PMOD0_2}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_2}]
+
+set_property PACKAGE_PIN C11 [get_ports {PMOD0_3}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_3}]
+
+######################## PMOD 1 Lower ########################
+set_property PACKAGE_PIN B10 [get_ports {PMOD0_4}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_4}]
+
+set_property PACKAGE_PIN E12 [get_ports {PMOD0_5}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_5}]
+
+set_property PACKAGE_PIN D11 [get_ports {PMOD0_6}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_6}]
+
+set_property PACKAGE_PIN B11 [get_ports {PMOD0_7}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_7}]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
+## ######################## PMOD 2 Upper ########################
+## set_property PACKAGE_PIN J11 [get_ports {PMOD1_0}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_0}]
+
+## set_property PACKAGE_PIN J10 [get_ports {PMOD1_1}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_1}]
+
+## set_property PACKAGE_PIN K13 [get_ports {PMOD1_2}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_2}]
+
+## set_property PACKAGE_PIN K12 [get_ports {PMOD1_3}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_3}]
+
+## ######################## PMOD 2 Lower ########################
+## set_property PACKAGE_PIN H11 [get_ports {PMOD1_4}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_4}]
+
+## set_property PACKAGE_PIN G10 [get_ports {PMOD1_5}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_5}]
+
+## set_property PACKAGE_PIN F12 [get_ports {PMOD1_6}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_6}]
+
+## set_property PACKAGE_PIN F11 [get_ports {PMOD1_7}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_7}]
+
+## ######################## PMOD 3 Upper ########################
+## set_property PACKAGE_PIN AE12 [get_ports {PMOD2_0}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_0}]
+
+## set_property PACKAGE_PIN AF12 [get_ports {PMOD2_1}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_1}]
+
+## set_property PACKAGE_PIN AG10 [get_ports {PMOD2_2}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_2}]
+
+## set_property PACKAGE_PIN AH10 [get_ports {PMOD2_3}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_3}]
+
+## ######################## PMOD 3 Lower ########################
+## set_property PACKAGE_PIN AF11 [get_ports {PMOD2_4}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_4}]
+
+## set_property PACKAGE_PIN AG11 [get_ports {PMOD2_5}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_5}]
+
+## set_property PACKAGE_PIN AH12 [get_ports {PMOD2_6}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_6}]
+
+## set_property PACKAGE_PIN AH11 [get_ports {PMOD2_7}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_7}]
+
+## ######################## PMOD 4 Upper ########################
+## set_property PACKAGE_PIN AC12 [get_ports {PMOD3_0}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_0}]
+
+## set_property PACKAGE_PIN AD12 [get_ports {PMOD3_1}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_1}]
+
+## set_property PACKAGE_PIN AE10 [get_ports {PMOD3_2}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_2}]
+
+## set_property PACKAGE_PIN AF10 [get_ports {PMOD3_3}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_3}]
+
+## ######################## PMOD 4 Lower ########################
+## set_property PACKAGE_PIN AD11 [get_ports {PMOD3_4}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_4}]
+
+## set_property PACKAGE_PIN AD10 [get_ports {PMOD3_5}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_5}]
+
+## set_property PACKAGE_PIN AA11 [get_ports {PMOD3_6}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_6}]
+
+## set_property PACKAGE_PIN AA10 [get_ports {PMOD3_7}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_7}]
+
+ ######################## PMOD generic ########################
+ set_property SLEW SLOW [get_ports PMOD*];
+ set_property DRIVE 4 [get_ports PMOD*];
+
+## ######################## Raspberry Pi GPIO Header ########################
+## ### AXI GPIO ###
+## set_property PACKAGE_PIN AD15 [get_ports {rpi_gpio[0]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[0]}]
+
+## set_property PACKAGE_PIN AD14 [get_ports {rpi_gpio[1]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[1]}]
+
+## set_property PACKAGE_PIN AE15 [get_ports {rpi_gpio[2]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[2]}]
+
+## set_property PACKAGE_PIN AE14 [get_ports {rpi_gpio[3]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[3]}]
+
+## set_property PACKAGE_PIN AG14 [get_ports {rpi_gpio[4]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[4]}]
+
+## set_property PACKAGE_PIN AH14 [get_ports {rpi_gpio[5]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[5]}]
+
+## set_property PACKAGE_PIN AG13 [get_ports {rpi_gpio[6]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[6]}]
+
+## set_property PACKAGE_PIN AH13 [get_ports {rpi_gpio[7]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[7]}]
+
+## set_property PACKAGE_PIN AC14 [get_ports {rpi_gpio[8]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[8]}]
+
+## set_property PACKAGE_PIN AC13 [get_ports {rpi_gpio[9]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[9]}]
+
+## set_property PACKAGE_PIN AE13 [get_ports {rpi_gpio[10]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[10]}]
+
+## set_property PACKAGE_PIN AF13 [get_ports {rpi_gpio[11]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[11]}]
+
+## set_property PACKAGE_PIN AA13 [get_ports {rpi_gpio[12]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[12]}]
+
+## set_property PACKAGE_PIN AB13 [get_ports {rpi_gpio[13]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[13]}]
+
+## set_property PACKAGE_PIN W14 [get_ports {rpi_gpio[14]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[14]}]
+
+## set_property PACKAGE_PIN W13 [get_ports {rpi_gpio[15]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[15]}]
+
+## set_property PACKAGE_PIN AB15 [get_ports {rpi_gpio[16]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[16]}]
+
+## set_property PACKAGE_PIN AB14 [get_ports {rpi_gpio[17]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[17]}]
+
+## set_property PACKAGE_PIN Y14 [get_ports {rpi_gpio[18]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[18]}]
+
+## set_property PACKAGE_PIN Y13 [get_ports {rpi_gpio[19]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[19]}]
+
+## set_property PACKAGE_PIN W12 [get_ports {rpi_gpio[20]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[20]}]
+
+## set_property PACKAGE_PIN W11 [get_ports {rpi_gpio[21]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[21]}]
+
+## set_property PACKAGE_PIN Y12 [get_ports {rpi_gpio[22]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[22]}]
+
+## set_property PACKAGE_PIN AA12 [get_ports {rpi_gpio[23]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[23]}]
+
+## set_property PACKAGE_PIN Y9 [get_ports {rpi_gpio[24]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[24]}]
+
+## set_property PACKAGE_PIN AA8 [get_ports {rpi_gpio[25]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[25]}]
+
+## set_property PACKAGE_PIN AB10 [get_ports {rpi_gpio[26]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[26]}]
+
+## set_property PACKAGE_PIN AB9 [get_ports {rpi_gpio[27]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[27]}]
+
+## ### Special Functions ###
+## #set_property PACKAGE_PIN AD15 [get_ports {rpi_gpio0_id_sd}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio0_id_sd}]
+
+## #set_property PACKAGE_PIN AD14 [get_ports {rpi_gpio1_id_sc}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio1_id_sc}]
+
+## #set_property PACKAGE_PIN AE15 [get_ports {rpi_gpio2_sda}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio2_sda}]
+
+## #set_property PACKAGE_PIN AE14 [get_ports {rpi_gpio3_scl}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio3_scl}]
+
+## #set_property PACKAGE_PIN AG14 [get_ports {rpi_gpio4_gpclk0}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio4_gpclk0}]
+
+## #set_property PACKAGE_PIN AH14 [get_ports {rpi_gpio5}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio5}]
+
+## #set_property PACKAGE_PIN AG13 [get_ports {rpi_gpio6}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio6}]
+
+## #set_property PACKAGE_PIN AH13 [get_ports {rpi_gpio7_ce1}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio7_ce1}]
+
+## #set_property PACKAGE_PIN AC14 [get_ports {rpi_gpio8_ce0}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio8_ce0}]
+
+## #set_property PACKAGE_PIN AC13 [get_ports {rpi_gpio9_miso}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio9_miso}]
+
+## #set_property PACKAGE_PIN AE13 [get_ports {rpi_gpio10_mosi}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio10_mosi}]
+
+## #set_property PACKAGE_PIN AF13 [get_ports {rpi_gpio11_sclk}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio11_sclk}]
+
+## #set_property PACKAGE_PIN AA13 [get_ports {rpi_gpio12_pwm0}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio12_pwm0}]
+
+## #set_property PACKAGE_PIN AB13 [get_ports {rpi_gpio13_pwm1}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio13_pwm1}]
+
+## #set_property PACKAGE_PIN W14 [get_ports {rpi_gpio14_txd}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio14_txd}]
+
+## #set_property PACKAGE_PIN W13 [get_ports {rpi_gpio15_rxd}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio15_rxd}]
+
+## #set_property PACKAGE_PIN AB15 [get_ports {rpi_gpio16}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio16}]
+
+## #set_property PACKAGE_PIN AB14 [get_ports {rpi_gpio17}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio17}]
+
+## #set_property PACKAGE_PIN Y14 [get_ports {rpi_gpio18_pcm_clk}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio18_pcm_clk}]
+
+## #set_property PACKAGE_PIN Y13 [get_ports {rpi_gpio19_pcm_fs}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio19_pcm_fs}]
+
+## #set_property PACKAGE_PIN W12 [get_ports {rpi_gpio20_pcm_din}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio20_pcm_din}]
+
+## #set_property PACKAGE_PIN W11 [get_ports {rpi_gpio21_pcm_dout}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio21_pcm_dout}]
+
+## #set_property PACKAGE_PIN Y12 [get_ports {rpi_gpio22}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio22}]
+
+## #set_property PACKAGE_PIN AA12 [get_ports {rpi_gpio23}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio23}]
+
+## #set_property PACKAGE_PIN Y9 [get_ports {rpi_gpio24}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio24}]
+
+## #set_property PACKAGE_PIN AA8 [get_ports {rpi_gpio25}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio25}]
+
+## #set_property PACKAGE_PIN AB10 [get_ports {rpi_gpio26}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio26}]
+
+## #set_property PACKAGE_PIN AB9 [get_ports {rpi_gpio27}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio27}]
+
+## ######################## PMOD generic ########################
+## set_property SLEW SLOW [get_ports rpi_*];
+## set_property DRIVE 4 [get_ports rpi_*];
diff --git a/fpga/targets/pynq_kr260/fpga_timing.xdc b/fpga/targets/pynq_kr260/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..879aaadbadf756cabae24bf0f3f919d9951a8e5d
--- /dev/null
+++ b/fpga/targets/pynq_kr260/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/fpga/targets/pynq_kr260/nanosoc_design_wrapper.v b/fpga/targets/pynq_kr260/nanosoc_design_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..742a7c14b6cca8eaa83c2ef241cce1c3c879f8bf
--- /dev/null
+++ b/fpga/targets/pynq_kr260/nanosoc_design_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target nanosoc_design_wrapper.bd
+//Design : nanosoc_design_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module nanosoc_design_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ nanosoc_design nanosoc_design_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ac6bf09ac1dcf825b19e62f2c6539a951367e915
--- /dev/null
+++ b/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
@@ -0,0 +1,1154 @@
+
+################################################################
+# This is a generated script based on design: nanosoc_design
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source nanosoc_design_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {0} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+ set_property -dict [ list \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+ CONFIG.PSU_MIO_0_DIRECTION {out} \
+ CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_0_POLARITY {Default} \
+ CONFIG.PSU_MIO_16_DIRECTION {inout} \
+ CONFIG.PSU_MIO_16_POLARITY {Default} \
+ CONFIG.PSU_MIO_17_DIRECTION {inout} \
+ CONFIG.PSU_MIO_17_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_DIRECTION {in} \
+ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_18_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_SLEW {fast} \
+ CONFIG.PSU_MIO_19_DIRECTION {out} \
+ CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_19_POLARITY {Default} \
+ CONFIG.PSU_MIO_1_DIRECTION {inout} \
+ CONFIG.PSU_MIO_1_POLARITY {Default} \
+ CONFIG.PSU_MIO_20_DIRECTION {out} \
+ CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_20_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_DIRECTION {in} \
+ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_21_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DIRECTION {out} \
+ CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_24_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_DIRECTION {in} \
+ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_25_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DIRECTION {out} \
+ CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_27_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_DIRECTION {in} \
+ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_28_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_SLEW {fast} \
+ CONFIG.PSU_MIO_29_DIRECTION {out} \
+ CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_29_POLARITY {Default} \
+ CONFIG.PSU_MIO_2_DIRECTION {inout} \
+ CONFIG.PSU_MIO_2_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_DIRECTION {in} \
+ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_30_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DIRECTION {inout} \
+ CONFIG.PSU_MIO_3_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_DIRECTION {in} \
+ CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_45_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_SLEW {fast} \
+ CONFIG.PSU_MIO_46_DIRECTION {inout} \
+ CONFIG.PSU_MIO_46_POLARITY {Default} \
+ CONFIG.PSU_MIO_47_DIRECTION {inout} \
+ CONFIG.PSU_MIO_47_POLARITY {Default} \
+ CONFIG.PSU_MIO_48_DIRECTION {inout} \
+ CONFIG.PSU_MIO_48_POLARITY {Default} \
+ CONFIG.PSU_MIO_49_DIRECTION {inout} \
+ CONFIG.PSU_MIO_49_POLARITY {Default} \
+ CONFIG.PSU_MIO_4_DIRECTION {inout} \
+ CONFIG.PSU_MIO_4_POLARITY {Default} \
+ CONFIG.PSU_MIO_50_DIRECTION {inout} \
+ CONFIG.PSU_MIO_50_POLARITY {Default} \
+ CONFIG.PSU_MIO_51_DIRECTION {out} \
+ CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_51_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_DIRECTION {in} \
+ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_52_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_SLEW {fast} \
+ CONFIG.PSU_MIO_53_DIRECTION {in} \
+ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_53_POLARITY {Default} \
+ CONFIG.PSU_MIO_53_SLEW {fast} \
+ CONFIG.PSU_MIO_54_DIRECTION {inout} \
+ CONFIG.PSU_MIO_54_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_DIRECTION {in} \
+ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_55_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_SLEW {fast} \
+ CONFIG.PSU_MIO_56_DIRECTION {inout} \
+ CONFIG.PSU_MIO_56_POLARITY {Default} \
+ CONFIG.PSU_MIO_57_DIRECTION {inout} \
+ CONFIG.PSU_MIO_57_POLARITY {Default} \
+ CONFIG.PSU_MIO_58_DIRECTION {out} \
+ CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_58_POLARITY {Default} \
+ CONFIG.PSU_MIO_59_DIRECTION {inout} \
+ CONFIG.PSU_MIO_59_POLARITY {Default} \
+ CONFIG.PSU_MIO_5_DIRECTION {out} \
+ CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_5_POLARITY {Default} \
+ CONFIG.PSU_MIO_60_DIRECTION {inout} \
+ CONFIG.PSU_MIO_60_POLARITY {Default} \
+ CONFIG.PSU_MIO_61_DIRECTION {inout} \
+ CONFIG.PSU_MIO_61_POLARITY {Default} \
+ CONFIG.PSU_MIO_62_DIRECTION {inout} \
+ CONFIG.PSU_MIO_62_POLARITY {Default} \
+ CONFIG.PSU_MIO_63_DIRECTION {inout} \
+ CONFIG.PSU_MIO_63_POLARITY {Default} \
+ CONFIG.PSU_MIO_64_DIRECTION {out} \
+ CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_64_POLARITY {Default} \
+ CONFIG.PSU_MIO_65_DIRECTION {out} \
+ CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_65_POLARITY {Default} \
+ CONFIG.PSU_MIO_66_DIRECTION {out} \
+ CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_66_POLARITY {Default} \
+ CONFIG.PSU_MIO_67_DIRECTION {out} \
+ CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_67_POLARITY {Default} \
+ CONFIG.PSU_MIO_68_DIRECTION {out} \
+ CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_68_POLARITY {Default} \
+ CONFIG.PSU_MIO_69_DIRECTION {out} \
+ CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_69_POLARITY {Default} \
+ CONFIG.PSU_MIO_6_DIRECTION {out} \
+ CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_6_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_DIRECTION {in} \
+ CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_70_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_SLEW {fast} \
+ CONFIG.PSU_MIO_71_DIRECTION {in} \
+ CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_71_POLARITY {Default} \
+ CONFIG.PSU_MIO_71_SLEW {fast} \
+ CONFIG.PSU_MIO_72_DIRECTION {in} \
+ CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_72_POLARITY {Default} \
+ CONFIG.PSU_MIO_72_SLEW {fast} \
+ CONFIG.PSU_MIO_73_DIRECTION {in} \
+ CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_73_POLARITY {Default} \
+ CONFIG.PSU_MIO_73_SLEW {fast} \
+ CONFIG.PSU_MIO_74_DIRECTION {in} \
+ CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_74_POLARITY {Default} \
+ CONFIG.PSU_MIO_74_SLEW {fast} \
+ CONFIG.PSU_MIO_75_DIRECTION {in} \
+ CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_75_POLARITY {Default} \
+ CONFIG.PSU_MIO_75_SLEW {fast} \
+ CONFIG.PSU_MIO_76_DIRECTION {out} \
+ CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_76_POLARITY {Default} \
+ CONFIG.PSU_MIO_77_DIRECTION {inout} \
+ CONFIG.PSU_MIO_77_POLARITY {Default} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
+SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
+1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
+1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
+3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
+3}\
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+ CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+ CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+ CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+ CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+ CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+ CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+ CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+ CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+ CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+ CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+ CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+ CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+ CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+ CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+ CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+ CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+ CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB0__RESET__ENABLE {0} \
+ CONFIG.PSU__USB1__RESET__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ ] $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/fpga/targets/pynq_kv260/fpga_pinmap.xdc b/fpga/targets/pynq_kv260/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..480bfc2ecc2c5211fc038e1c425e14cb80519a10
--- /dev/null
+++ b/fpga/targets/pynq_kv260/fpga_pinmap.xdc
@@ -0,0 +1,290 @@
+##################################################################################
+## ##
+## KR260 IO subset XDC ##
+## ##
+##################################################################################
+
+######################## PMOD 1 Upper ########################
+set_property PACKAGE_PIN H12 [get_ports {PMOD0_0}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_0}]
+
+set_property PACKAGE_PIN E10 [get_ports {PMOD0_1}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_1}]
+
+set_property PACKAGE_PIN D10 [get_ports {PMOD0_2}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_2}]
+
+set_property PACKAGE_PIN C11 [get_ports {PMOD0_3}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_3}]
+
+######################## PMOD 1 Lower ########################
+set_property PACKAGE_PIN B10 [get_ports {PMOD0_4}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_4}]
+
+set_property PACKAGE_PIN E12 [get_ports {PMOD0_5}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_5}]
+
+set_property PACKAGE_PIN D11 [get_ports {PMOD0_6}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_6}]
+
+set_property PACKAGE_PIN B11 [get_ports {PMOD0_7}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_7}]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
+## ######################## PMOD 2 Upper ########################
+## set_property PACKAGE_PIN J11 [get_ports {PMOD1_0}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_0}]
+
+## set_property PACKAGE_PIN J10 [get_ports {PMOD1_1}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_1}]
+
+## set_property PACKAGE_PIN K13 [get_ports {PMOD1_2}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_2}]
+
+## set_property PACKAGE_PIN K12 [get_ports {PMOD1_3}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_3}]
+
+## ######################## PMOD 2 Lower ########################
+## set_property PACKAGE_PIN H11 [get_ports {PMOD1_4}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_4}]
+
+## set_property PACKAGE_PIN G10 [get_ports {PMOD1_5}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_5}]
+
+## set_property PACKAGE_PIN F12 [get_ports {PMOD1_6}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_6}]
+
+## set_property PACKAGE_PIN F11 [get_ports {PMOD1_7}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD1_7}]
+
+## ######################## PMOD 3 Upper ########################
+## set_property PACKAGE_PIN AE12 [get_ports {PMOD2_0}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_0}]
+
+## set_property PACKAGE_PIN AF12 [get_ports {PMOD2_1}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_1}]
+
+## set_property PACKAGE_PIN AG10 [get_ports {PMOD2_2}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_2}]
+
+## set_property PACKAGE_PIN AH10 [get_ports {PMOD2_3}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_3}]
+
+## ######################## PMOD 3 Lower ########################
+## set_property PACKAGE_PIN AF11 [get_ports {PMOD2_4}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_4}]
+
+## set_property PACKAGE_PIN AG11 [get_ports {PMOD2_5}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_5}]
+
+## set_property PACKAGE_PIN AH12 [get_ports {PMOD2_6}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_6}]
+
+## set_property PACKAGE_PIN AH11 [get_ports {PMOD2_7}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD2_7}]
+
+## ######################## PMOD 4 Upper ########################
+## set_property PACKAGE_PIN AC12 [get_ports {PMOD3_0}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_0}]
+
+## set_property PACKAGE_PIN AD12 [get_ports {PMOD3_1}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_1}]
+
+## set_property PACKAGE_PIN AE10 [get_ports {PMOD3_2}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_2}]
+
+## set_property PACKAGE_PIN AF10 [get_ports {PMOD3_3}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_3}]
+
+## ######################## PMOD 4 Lower ########################
+## set_property PACKAGE_PIN AD11 [get_ports {PMOD3_4}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_4}]
+
+## set_property PACKAGE_PIN AD10 [get_ports {PMOD3_5}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_5}]
+
+## set_property PACKAGE_PIN AA11 [get_ports {PMOD3_6}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_6}]
+
+## set_property PACKAGE_PIN AA10 [get_ports {PMOD3_7}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {PMOD3_7}]
+
+ ######################## PMOD generic ########################
+ set_property SLEW SLOW [get_ports PMOD*];
+ set_property DRIVE 4 [get_ports PMOD*];
+
+## ######################## Raspberry Pi GPIO Header ########################
+## ### AXI GPIO ###
+## set_property PACKAGE_PIN AD15 [get_ports {rpi_gpio[0]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[0]}]
+
+## set_property PACKAGE_PIN AD14 [get_ports {rpi_gpio[1]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[1]}]
+
+## set_property PACKAGE_PIN AE15 [get_ports {rpi_gpio[2]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[2]}]
+
+## set_property PACKAGE_PIN AE14 [get_ports {rpi_gpio[3]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[3]}]
+
+## set_property PACKAGE_PIN AG14 [get_ports {rpi_gpio[4]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[4]}]
+
+## set_property PACKAGE_PIN AH14 [get_ports {rpi_gpio[5]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[5]}]
+
+## set_property PACKAGE_PIN AG13 [get_ports {rpi_gpio[6]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[6]}]
+
+## set_property PACKAGE_PIN AH13 [get_ports {rpi_gpio[7]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[7]}]
+
+## set_property PACKAGE_PIN AC14 [get_ports {rpi_gpio[8]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[8]}]
+
+## set_property PACKAGE_PIN AC13 [get_ports {rpi_gpio[9]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[9]}]
+
+## set_property PACKAGE_PIN AE13 [get_ports {rpi_gpio[10]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[10]}]
+
+## set_property PACKAGE_PIN AF13 [get_ports {rpi_gpio[11]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[11]}]
+
+## set_property PACKAGE_PIN AA13 [get_ports {rpi_gpio[12]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[12]}]
+
+## set_property PACKAGE_PIN AB13 [get_ports {rpi_gpio[13]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[13]}]
+
+## set_property PACKAGE_PIN W14 [get_ports {rpi_gpio[14]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[14]}]
+
+## set_property PACKAGE_PIN W13 [get_ports {rpi_gpio[15]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[15]}]
+
+## set_property PACKAGE_PIN AB15 [get_ports {rpi_gpio[16]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[16]}]
+
+## set_property PACKAGE_PIN AB14 [get_ports {rpi_gpio[17]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[17]}]
+
+## set_property PACKAGE_PIN Y14 [get_ports {rpi_gpio[18]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[18]}]
+
+## set_property PACKAGE_PIN Y13 [get_ports {rpi_gpio[19]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[19]}]
+
+## set_property PACKAGE_PIN W12 [get_ports {rpi_gpio[20]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[20]}]
+
+## set_property PACKAGE_PIN W11 [get_ports {rpi_gpio[21]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[21]}]
+
+## set_property PACKAGE_PIN Y12 [get_ports {rpi_gpio[22]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[22]}]
+
+## set_property PACKAGE_PIN AA12 [get_ports {rpi_gpio[23]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[23]}]
+
+## set_property PACKAGE_PIN Y9 [get_ports {rpi_gpio[24]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[24]}]
+
+## set_property PACKAGE_PIN AA8 [get_ports {rpi_gpio[25]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[25]}]
+
+## set_property PACKAGE_PIN AB10 [get_ports {rpi_gpio[26]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[26]}]
+
+## set_property PACKAGE_PIN AB9 [get_ports {rpi_gpio[27]}]
+## set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio[27]}]
+
+## ### Special Functions ###
+## #set_property PACKAGE_PIN AD15 [get_ports {rpi_gpio0_id_sd}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio0_id_sd}]
+
+## #set_property PACKAGE_PIN AD14 [get_ports {rpi_gpio1_id_sc}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio1_id_sc}]
+
+## #set_property PACKAGE_PIN AE15 [get_ports {rpi_gpio2_sda}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio2_sda}]
+
+## #set_property PACKAGE_PIN AE14 [get_ports {rpi_gpio3_scl}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio3_scl}]
+
+## #set_property PACKAGE_PIN AG14 [get_ports {rpi_gpio4_gpclk0}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio4_gpclk0}]
+
+## #set_property PACKAGE_PIN AH14 [get_ports {rpi_gpio5}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio5}]
+
+## #set_property PACKAGE_PIN AG13 [get_ports {rpi_gpio6}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio6}]
+
+## #set_property PACKAGE_PIN AH13 [get_ports {rpi_gpio7_ce1}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio7_ce1}]
+
+## #set_property PACKAGE_PIN AC14 [get_ports {rpi_gpio8_ce0}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio8_ce0}]
+
+## #set_property PACKAGE_PIN AC13 [get_ports {rpi_gpio9_miso}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio9_miso}]
+
+## #set_property PACKAGE_PIN AE13 [get_ports {rpi_gpio10_mosi}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio10_mosi}]
+
+## #set_property PACKAGE_PIN AF13 [get_ports {rpi_gpio11_sclk}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio11_sclk}]
+
+## #set_property PACKAGE_PIN AA13 [get_ports {rpi_gpio12_pwm0}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio12_pwm0}]
+
+## #set_property PACKAGE_PIN AB13 [get_ports {rpi_gpio13_pwm1}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio13_pwm1}]
+
+## #set_property PACKAGE_PIN W14 [get_ports {rpi_gpio14_txd}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio14_txd}]
+
+## #set_property PACKAGE_PIN W13 [get_ports {rpi_gpio15_rxd}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio15_rxd}]
+
+## #set_property PACKAGE_PIN AB15 [get_ports {rpi_gpio16}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio16}]
+
+## #set_property PACKAGE_PIN AB14 [get_ports {rpi_gpio17}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio17}]
+
+## #set_property PACKAGE_PIN Y14 [get_ports {rpi_gpio18_pcm_clk}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio18_pcm_clk}]
+
+## #set_property PACKAGE_PIN Y13 [get_ports {rpi_gpio19_pcm_fs}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio19_pcm_fs}]
+
+## #set_property PACKAGE_PIN W12 [get_ports {rpi_gpio20_pcm_din}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio20_pcm_din}]
+
+## #set_property PACKAGE_PIN W11 [get_ports {rpi_gpio21_pcm_dout}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio21_pcm_dout}]
+
+## #set_property PACKAGE_PIN Y12 [get_ports {rpi_gpio22}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio22}]
+
+## #set_property PACKAGE_PIN AA12 [get_ports {rpi_gpio23}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio23}]
+
+## #set_property PACKAGE_PIN Y9 [get_ports {rpi_gpio24}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio24}]
+
+## #set_property PACKAGE_PIN AA8 [get_ports {rpi_gpio25}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio25}]
+
+## #set_property PACKAGE_PIN AB10 [get_ports {rpi_gpio26}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio26}]
+
+## #set_property PACKAGE_PIN AB9 [get_ports {rpi_gpio27}]
+## #set_property IOSTANDARD LVCMOS33 [get_ports {rpi_gpio27}]
+
+## ######################## PMOD generic ########################
+## set_property SLEW SLOW [get_ports rpi_*];
+## set_property DRIVE 4 [get_ports rpi_*];
diff --git a/fpga/targets/pynq_kv260/fpga_timing.xdc b/fpga/targets/pynq_kv260/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..879aaadbadf756cabae24bf0f3f919d9951a8e5d
--- /dev/null
+++ b/fpga/targets/pynq_kv260/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/fpga/targets/pynq_kv260/nanosoc_design_wrapper.v b/fpga/targets/pynq_kv260/nanosoc_design_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..742a7c14b6cca8eaa83c2ef241cce1c3c879f8bf
--- /dev/null
+++ b/fpga/targets/pynq_kv260/nanosoc_design_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target nanosoc_design_wrapper.bd
+//Design : nanosoc_design_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module nanosoc_design_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ nanosoc_design nanosoc_design_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ac6bf09ac1dcf825b19e62f2c6539a951367e915
--- /dev/null
+++ b/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
@@ -0,0 +1,1154 @@
+
+################################################################
+# This is a generated script based on design: nanosoc_design
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source nanosoc_design_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {0} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+ set_property -dict [ list \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+ CONFIG.PSU_MIO_0_DIRECTION {out} \
+ CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_0_POLARITY {Default} \
+ CONFIG.PSU_MIO_16_DIRECTION {inout} \
+ CONFIG.PSU_MIO_16_POLARITY {Default} \
+ CONFIG.PSU_MIO_17_DIRECTION {inout} \
+ CONFIG.PSU_MIO_17_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_DIRECTION {in} \
+ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_18_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_SLEW {fast} \
+ CONFIG.PSU_MIO_19_DIRECTION {out} \
+ CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_19_POLARITY {Default} \
+ CONFIG.PSU_MIO_1_DIRECTION {inout} \
+ CONFIG.PSU_MIO_1_POLARITY {Default} \
+ CONFIG.PSU_MIO_20_DIRECTION {out} \
+ CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_20_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_DIRECTION {in} \
+ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_21_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DIRECTION {out} \
+ CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_24_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_DIRECTION {in} \
+ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_25_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DIRECTION {out} \
+ CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_27_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_DIRECTION {in} \
+ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_28_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_SLEW {fast} \
+ CONFIG.PSU_MIO_29_DIRECTION {out} \
+ CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_29_POLARITY {Default} \
+ CONFIG.PSU_MIO_2_DIRECTION {inout} \
+ CONFIG.PSU_MIO_2_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_DIRECTION {in} \
+ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_30_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DIRECTION {inout} \
+ CONFIG.PSU_MIO_3_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_DIRECTION {in} \
+ CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_45_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_SLEW {fast} \
+ CONFIG.PSU_MIO_46_DIRECTION {inout} \
+ CONFIG.PSU_MIO_46_POLARITY {Default} \
+ CONFIG.PSU_MIO_47_DIRECTION {inout} \
+ CONFIG.PSU_MIO_47_POLARITY {Default} \
+ CONFIG.PSU_MIO_48_DIRECTION {inout} \
+ CONFIG.PSU_MIO_48_POLARITY {Default} \
+ CONFIG.PSU_MIO_49_DIRECTION {inout} \
+ CONFIG.PSU_MIO_49_POLARITY {Default} \
+ CONFIG.PSU_MIO_4_DIRECTION {inout} \
+ CONFIG.PSU_MIO_4_POLARITY {Default} \
+ CONFIG.PSU_MIO_50_DIRECTION {inout} \
+ CONFIG.PSU_MIO_50_POLARITY {Default} \
+ CONFIG.PSU_MIO_51_DIRECTION {out} \
+ CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_51_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_DIRECTION {in} \
+ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_52_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_SLEW {fast} \
+ CONFIG.PSU_MIO_53_DIRECTION {in} \
+ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_53_POLARITY {Default} \
+ CONFIG.PSU_MIO_53_SLEW {fast} \
+ CONFIG.PSU_MIO_54_DIRECTION {inout} \
+ CONFIG.PSU_MIO_54_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_DIRECTION {in} \
+ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_55_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_SLEW {fast} \
+ CONFIG.PSU_MIO_56_DIRECTION {inout} \
+ CONFIG.PSU_MIO_56_POLARITY {Default} \
+ CONFIG.PSU_MIO_57_DIRECTION {inout} \
+ CONFIG.PSU_MIO_57_POLARITY {Default} \
+ CONFIG.PSU_MIO_58_DIRECTION {out} \
+ CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_58_POLARITY {Default} \
+ CONFIG.PSU_MIO_59_DIRECTION {inout} \
+ CONFIG.PSU_MIO_59_POLARITY {Default} \
+ CONFIG.PSU_MIO_5_DIRECTION {out} \
+ CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_5_POLARITY {Default} \
+ CONFIG.PSU_MIO_60_DIRECTION {inout} \
+ CONFIG.PSU_MIO_60_POLARITY {Default} \
+ CONFIG.PSU_MIO_61_DIRECTION {inout} \
+ CONFIG.PSU_MIO_61_POLARITY {Default} \
+ CONFIG.PSU_MIO_62_DIRECTION {inout} \
+ CONFIG.PSU_MIO_62_POLARITY {Default} \
+ CONFIG.PSU_MIO_63_DIRECTION {inout} \
+ CONFIG.PSU_MIO_63_POLARITY {Default} \
+ CONFIG.PSU_MIO_64_DIRECTION {out} \
+ CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_64_POLARITY {Default} \
+ CONFIG.PSU_MIO_65_DIRECTION {out} \
+ CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_65_POLARITY {Default} \
+ CONFIG.PSU_MIO_66_DIRECTION {out} \
+ CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_66_POLARITY {Default} \
+ CONFIG.PSU_MIO_67_DIRECTION {out} \
+ CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_67_POLARITY {Default} \
+ CONFIG.PSU_MIO_68_DIRECTION {out} \
+ CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_68_POLARITY {Default} \
+ CONFIG.PSU_MIO_69_DIRECTION {out} \
+ CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_69_POLARITY {Default} \
+ CONFIG.PSU_MIO_6_DIRECTION {out} \
+ CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_6_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_DIRECTION {in} \
+ CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_70_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_SLEW {fast} \
+ CONFIG.PSU_MIO_71_DIRECTION {in} \
+ CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_71_POLARITY {Default} \
+ CONFIG.PSU_MIO_71_SLEW {fast} \
+ CONFIG.PSU_MIO_72_DIRECTION {in} \
+ CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_72_POLARITY {Default} \
+ CONFIG.PSU_MIO_72_SLEW {fast} \
+ CONFIG.PSU_MIO_73_DIRECTION {in} \
+ CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_73_POLARITY {Default} \
+ CONFIG.PSU_MIO_73_SLEW {fast} \
+ CONFIG.PSU_MIO_74_DIRECTION {in} \
+ CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_74_POLARITY {Default} \
+ CONFIG.PSU_MIO_74_SLEW {fast} \
+ CONFIG.PSU_MIO_75_DIRECTION {in} \
+ CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_75_POLARITY {Default} \
+ CONFIG.PSU_MIO_75_SLEW {fast} \
+ CONFIG.PSU_MIO_76_DIRECTION {out} \
+ CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_76_POLARITY {Default} \
+ CONFIG.PSU_MIO_77_DIRECTION {inout} \
+ CONFIG.PSU_MIO_77_POLARITY {Default} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
+SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
+1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
+1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
+3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
+3}\
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+ CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+ CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+ CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+ CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+ CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+ CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+ CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+ CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+ CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+ CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+ CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+ CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+ CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+ CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+ CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+ CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+ CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB0__RESET__ENABLE {0} \
+ CONFIG.PSU__USB1__RESET__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ ] $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs