diff --git a/flist/corstone101_ip_ASIC.flist b/flist/corstone101_ip_ASIC.flist
new file mode 100644
index 0000000000000000000000000000000000000000..f23121f2b7f19e0f0300de8a193eef41ca5e2ece
--- /dev/null
+++ b/flist/corstone101_ip_ASIC.flist
@@ -0,0 +1,86 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= Corstone-101 search path =============
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+
+// CMSDK APB Timer IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v
+
+// CMSDK Dual Timers IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v
+
+// CMSDK APB UART IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v
+
+// CMSDK APB Watchdog IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v
+
+// CMSDK APB Slave Mux IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+
+// CMSDK APB Subystem Top IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v
+
+// CMSDK AHB Slave Mux IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
+
+// CMSDK AHB Default Slave IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
+
+// CMSDK AHB GPIO IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
+
+// CMSDK AHB to APB Bridge IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+
+// CMSDK IOP to GPIO IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
+
+// CMSDK Clockgate Models
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v
+
+// CMSDK Memory Models
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v
+
+
+// CMSDK AHB to SRAM bridge IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
\ No newline at end of file
diff --git a/flist/nanosoc_ASIC.flist b/flist/nanosoc_ASIC.flist
new file mode 100644
index 0000000000000000000000000000000000000000..0ca625025ed71576576522b1456668282866038f
--- /dev/null
+++ b/flist/nanosoc_ASIC.flist
@@ -0,0 +1,33 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Top-level Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC IP search path =============
+
+// Include NanoSoC IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
+
+// Include Corstone IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_ip_ASIC.flist
+
+// SLCore Files
+-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0.flist
+
+// Debug IP
+-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
+
+// DMAC IP
+-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
diff --git a/fpga/targets/arm_mps3/fpga_pinmap.xdc b/fpga/targets/arm_mps3/fpga_pinmap.xdc
index 5fbe61eb28f3d716824d54418909d555a4f29ad4..88bb6d2abeba7c8fd16de7716393cca1d03f5d20 100644
--- a/fpga/targets/arm_mps3/fpga_pinmap.xdc
+++ b/fpga/targets/arm_mps3/fpga_pinmap.xdc
@@ -1,3 +1,4 @@
+set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
# -----------------------------------------------------------------------------
# Purpose : Main timing constraints and pin list for MPS3
# -----------------------------------------------------------------------------
@@ -6,7 +7,118 @@
# Pin Assigment
####################################################################################
-set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_* ETH_* USB_* CLCD_* USER_nLED* USER_SW* USER_nPB* HDMI_* CS_* SH_ADC* UART_*}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_FIFOSEL]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_nOE]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS18 [get_ports ETH_INT]
+set_property IOSTANDARD LVCMOS18 [get_ports ETH_nCS]
+set_property IOSTANDARD LVCMOS18 [get_ports ETH_nOE]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_DACK]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_DREQ]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_INT]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_BL]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_CS]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_RD]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_RS]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_RST]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TINT]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TNC]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TSCL]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TSDA]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_WR_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nPB[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nPB[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports HDMI_CSCL]
+set_property IOSTANDARD LVCMOS18 [get_ports HDMI_CSDA]
+set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TCK]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TDI]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TDO]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TMS]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_T_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_T_CTL]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_nDET]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_nSRST]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_nTRST]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_CK]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_CS]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_DI]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[4]}]
@@ -629,7 +741,6 @@ set_property PACKAGE_PIN AE28 [get_ports {UART_RX_F[2]}]
set_property PACKAGE_PIN AD30 [get_ports {UART_RX_F[3]}]
set_property PACKAGE_PIN AF27 [get_ports {UART_TX_F[0]}]
set_property PACKAGE_PIN AE30 [get_ports {UART_TX_F[1]}]
-set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
set_property PACKAGE_PIN AD29 [get_ports {UART_TX_F[3]}]
set_property PACKAGE_PIN AN26 [get_ports USB_DACK]
set_property PACKAGE_PIN AN24 [get_ports USB_DREQ]
@@ -872,44 +983,4 @@ set_property BITSTREAM.STARTUP.MATCH_CYCLE Auto [current_design]
set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
set_property CONFIG_MODE S_SELECTMAP [current_design]
-set_property PACKAGE_PIN AR26 [get_ports NRST]
-set_property PACKAGE_PIN AR27 [get_ports {P0[0]}]
-set_property PACKAGE_PIN AW29 [get_ports {P0[10]}]
-set_property PACKAGE_PIN BA25 [get_ports {P0[11]}]
-set_property PACKAGE_PIN BB25 [get_ports {P0[12]}]
-set_property PACKAGE_PIN AY28 [get_ports {P0[13]}]
-set_property PACKAGE_PIN BA28 [get_ports {P0[14]}]
-set_property PACKAGE_PIN AY26 [get_ports {P0[15]}]
-set_property PACKAGE_PIN AR28 [get_ports {P0[1]}]
-set_property PACKAGE_PIN AT28 [get_ports {P0[2]}]
-set_property PACKAGE_PIN AU25 [get_ports {P0[3]}]
-set_property PACKAGE_PIN AU26 [get_ports {P0[4]}]
-set_property PACKAGE_PIN AU27 [get_ports {P0[5]}]
-set_property PACKAGE_PIN AV28 [get_ports {P0[6]}]
-set_property PACKAGE_PIN BB26 [get_ports {P0[7]}]
-set_property PACKAGE_PIN BB27 [get_ports {P0[8]}]
-set_property PACKAGE_PIN AW28 [get_ports {P0[9]}]
-set_property PACKAGE_PIN AW26 [get_ports {P1[0]}]
-set_property PACKAGE_PIN AY21 [get_ports {P1[10]}]
-set_property PACKAGE_PIN AY22 [get_ports {P1[11]}]
-set_property PACKAGE_PIN BA22 [get_ports {P1[12]}]
-set_property PACKAGE_PIN AT22 [get_ports {P1[13]}]
-set_property PACKAGE_PIN AT23 [get_ports {P1[14]}]
-set_property PACKAGE_PIN AR25 [get_ports {P1[15]}]
-set_property PACKAGE_PIN AY27 [get_ports {P1[1]}]
-set_property PACKAGE_PIN AW23 [get_ports {P1[2]}]
-set_property PACKAGE_PIN AY23 [get_ports {P1[3]}]
-set_property PACKAGE_PIN AW25 [get_ports {P1[4]}]
-set_property PACKAGE_PIN BB21 [get_ports {P1[5]}]
-set_property PACKAGE_PIN BB22 [get_ports {P1[6]}]
-set_property PACKAGE_PIN BA23 [get_ports {P1[7]}]
-set_property PACKAGE_PIN BA24 [get_ports {P1[8]}]
-set_property PACKAGE_PIN AW21 [get_ports {P1[9]}]
-set_property PACKAGE_PIN AW24 [get_ports SWCLKTCK]
-set_property PACKAGE_PIN AU22 [get_ports SWDIOTMS]
-set_property PACKAGE_PIN AV23 [get_ports VDD]
-set_property PACKAGE_PIN AT24 [get_ports VDDIO]
-set_property PACKAGE_PIN AT25 [get_ports VSS]
-set_property PACKAGE_PIN AV21 [get_ports VSSIO]
-set_property PACKAGE_PIN AY25 [get_ports XTAL1]
-set_property PACKAGE_PIN AV22 [get_ports XTAL2]
+
diff --git a/fpga/targets/arm_mps3/fpga_timing.xdc b/fpga/targets/arm_mps3/fpga_timing.xdc
index 78ac5e66193d3180e0df08f400cc924f8f74e8be..23677a726e5026e2ad86b27165879129dad79b4a 100644
--- a/fpga/targets/arm_mps3/fpga_timing.xdc
+++ b/fpga/targets/arm_mps3/fpga_timing.xdc
@@ -4,96 +4,19 @@
## ##
##################################################################################
-create_clock -name CLK -period 30 [get_ports XTAL1]
-create_clock -name VCLK -period 30 -waveform {5 20}
-
-create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
-create_clock -name VSWCLK -period 60 -waveform {5 35}
-
-set_clock_groups -name async_clk_swclock -asynchronous \
--group [get_clocks -include_generated_clocks CLK] \
--group [get_clocks -include_generated_clocks SWCLK]
-
-set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
-set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
-set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
-set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
-set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
-set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
-set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
-set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
-
-#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
-#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
-#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
-#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
-#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
-#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
-#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
-#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
-
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
-
+create_clock -period 100.000 -name CS_TCK -waveform {0.000 50.000} [get_ports CS_TCK]
+create_clock -period 20.000 -name {OSCCLK[1]} -waveform {0.000 10.000} [get_ports {OSCCLK[1]}]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports {UART_RX_F[*]}]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports {UART_RX_F[*]}]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports CB_nRST]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports CB_nRST]
+set_input_delay -clock [get_clocks CS_TCK] -min -add_delay 5.000 [get_ports CS_TMS]
+set_input_delay -clock [get_clocks CS_TCK] -max -add_delay 9.000 [get_ports CS_TMS]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports CS_nSRST]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports CS_nSRST]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay -5.000 [get_ports {SH0_IO[*]}]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports {SH0_IO[*]}]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 0.000 [get_ports {UART_TX_F[*]}]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 6.000 [get_ports {UART_TX_F[*]}]
+set_output_delay -clock [get_clocks CS_TCK] -min -add_delay -1.000 [get_ports CS_TMS]
+set_output_delay -clock [get_clocks CS_TCK] -max -add_delay 5.000 [get_ports CS_TMS]
diff --git a/fpga/targets/arm_mps3/nanosoc_design_wrapper.v b/fpga/targets/arm_mps3/nanosoc_design_wrapper.v
index 2509954dbaedf58d59c2aa0a0b457fac45119dde..ed3d2223346fd4c06df33f9c092bd99bf7cbda5f 100644
--- a/fpga/targets/arm_mps3/nanosoc_design_wrapper.v
+++ b/fpga/targets/arm_mps3/nanosoc_design_wrapper.v
@@ -352,8 +352,9 @@ BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
assign SMBM_nWAIT = 1'b1;
assign CFG_DATAOUT = 1'b0;
wire nRST;
- reg rst_sync0, rst_sync1;
+ reg rst_sync0, rst_sync1, rst_sync2;
assign nRST_in = CB_nRST || CS_nSRST;
+ assign nRST = rst_sync2;
always @(posedge ACLK)
if (~nRST_in) begin
@@ -362,11 +363,9 @@ BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
end else begin
rst_sync0 <= 1'b1;
rst_sync1 <= rst_sync0;
+ rst_sync2 <= rst_sync1;
end
- assign nRST = rst_sync1;
-
-
nanosoc_design nanosoc_design_i
(.UART_RX(UART_RX_F[2]),
.UART_TX(UART_TX_F[2]),
diff --git a/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
index 2608b77948f9da2c4f54265f53d5daf7a813b4ca..105a5b2f0a55914ccc05706439a8bf4a82caf29c 100644
--- a/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
@@ -7,6 +7,7 @@
# IP Integrator Tcl commands easier.
################################################################
+
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
@@ -35,7 +36,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
################################################################
# To test this script, run the following commands from Vivado Tcl console:
-# source nanosoc_design_script.tcl
+# source design_1_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
@@ -49,7 +50,7 @@ if { $list_projs eq "" } {
# CHANGE DESIGN NAME HERE
variable design_name
-set design_name nanosoc_design
+set design_name design_1
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
@@ -408,8 +409,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.NUM_SI {1} \
] $smartconnect_0
- # Create instance: uart_axi_master_0, and set properties
- set uart_axi_master_0 [ create_bd_cell -type ip -vlnv user.org:user:uart_axi_master:1.0 uart_axi_master_0 ]
+ # Create instance: uart_to_AXI_master_0, and set properties
+ set uart_to_AXI_master_0 [ create_bd_cell -type ip -vlnv ultraembedded:user:uart_axi_master:1.0 uart_to_AXI_master_0 ]
set_property -dict [ list \
CONFIG.CLK_SPEED {50000000} \
CONFIG.C_M00_AXI_ARUSER_WIDTH {4} \
@@ -418,7 +419,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.C_M00_AXI_ID_WIDTH {4} \
CONFIG.C_M00_AXI_RUSER_WIDTH {4} \
CONFIG.C_M00_AXI_WUSER_WIDTH {4} \
- ] $uart_axi_master_0
+ ] $uart_to_AXI_master_0
# Create instance: xlconstant_0, and set properties
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
@@ -453,12 +454,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
- connect_bd_intf_net -intf_net uart_axi_master_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins uart_axi_master_0/M00_AXI]
+ connect_bd_intf_net -intf_net uart_to_AXI_master_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins uart_to_AXI_master_0/M00_AXI]
# Create port connections
connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
- connect_bd_net -net UART_RX_1 [get_bd_pins UART_RX] [get_bd_pins uart_axi_master_0/UART_RX]
+ connect_bd_net -net UART_RX_1 [get_bd_pins UART_RX] [get_bd_pins uart_to_AXI_master_0/UART_RX]
connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
@@ -492,12 +493,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ext_reset_in] [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins uart_axi_master_0/m00_axi_aresetn]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ext_reset_in] [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins uart_to_AXI_master_0/m00_axi_aresetn]
connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
- connect_bd_net -net uart_axi_master_0_UART_TX [get_bd_pins UART_TX] [get_bd_pins uart_axi_master_0/UART_TX]
+ connect_bd_net -net uart_to_AXI_master_0_UART_TX [get_bd_pins UART_TX] [get_bd_pins uart_to_AXI_master_0/UART_TX]
connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins uart_axi_master_0/m00_axi_aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins uart_to_AXI_master_0/m00_axi_aclk]
# Restore current instance
current_bd_instance $oldCurInst
@@ -540,10 +541,10 @@ proc create_root_design { parentCell } {
# Create ports
set EXT_CLK [ create_bd_port -dir I -type clk -freq_hz 50000000 EXT_CLK ]
- # set_property -dict [ list \
- # CONFIG.ASSOCIATED_ASYNC_RESET {nRST_CPU} \
- # CONFIG.ASSOCIATED_RESET {nRST_CPU} \
- #] $EXT_CLK
+ set_property -dict [ list \
+ CONFIG.ASSOCIATED_ASYNC_RESET {nRST_CPU} \
+ CONFIG.ASSOCIATED_RESET {nRST_CPU} \
+ ] $EXT_CLK
set UART_RX [ create_bd_port -dir I UART_RX ]
set UART_TX [ create_bd_port -dir O UART_TX ]
set nRST_CPU [ create_bd_port -dir I -type rst nRST_CPU ]
@@ -578,14 +579,14 @@ proc create_root_design { parentCell } {
# Create address segments
assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
- assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
- assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
# Restore current instance
@@ -597,10 +598,22 @@ proc create_root_design { parentCell } {
# End of create_root_design()
-##################################################################
-# MAIN FLOW
-##################################################################
-
-#create_root_design ""
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+available_tcl_procs
\ No newline at end of file
diff --git a/software/common/validation/dma_bandwidth_test.c b/software/common/validation/dma_bandwidth_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..77d726a2bfd90cb21841eb3507adc807520d0dad
--- /dev/null
+++ b/software/common/validation/dma_bandwidth_test.c
@@ -0,0 +1,643 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the connectivity of the DMA-230 including
+ interrupt and done signals
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#include "config_id.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+
+int pl230_dma_detect(void);
+int ID_Check(const unsigned int id_array[], unsigned int offset);
+void dma_memory_copy (unsigned int src, unsigned int dest, unsigned int size, unsigned int num);
+void dma_data_struct_init(void);
+void dma_pl230_init(void);
+int dma_simple_test(void);
+int dma_interrupt_test(void);
+int dma_event_test(void);
+void delay(void);
+
+ /* Maximum to 32 DMA channel */
+#define MAX_NUM_OF_DMA_CHANNELS 32
+ /* SRAM in example system is 64K bytes */
+//#define RAM_ADDRESS_MAX 0x3000FFFF
+#define RAM_ADDRESS_MAX 0x80000FFF
+
+typedef struct /* 4 words */
+{
+ volatile unsigned long SrcEndPointer;
+ volatile unsigned long DestEndPointer;
+ volatile unsigned long Control;
+ volatile unsigned long unused;
+} pl230_dma_channel_data;
+
+
+typedef struct /* 8 words per channel */
+{ /* only one channel in the example uDMA setup */
+ volatile pl230_dma_channel_data Primary[MAX_NUM_OF_DMA_CHANNELS];
+ volatile pl230_dma_channel_data Alternate[MAX_NUM_OF_DMA_CHANNELS];
+} pl230_dma_data_structure;
+
+pl230_dma_data_structure *dma_data;
+
+volatile unsigned int source_data_array[4]; /* Data array for memory DMA test */
+volatile unsigned int dest_data_array[4]; /* Data array for memory DMA test */
+
+#if defined ( __CC_ARM )
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ unsigned int address_test_read(unsigned int addr);
+#endif
+
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+int main (void)
+{
+ int result=0;
+ temp_data=0;
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - DMA Bandwidth Test - revision $Revision: 371321 $\n");
+
+
+ if (pl230_dma_detect()!=0) {
+ return 0; /* Quit test if DMA is not present */
+ }
+
+ dma_done_irq_expected = 0;
+ dma_done_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ dma_data_struct_init();
+ dma_pl230_init();
+ result += dma_simple_test();
+ result += dma_interrupt_test();
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+/* --------------------------------------------------------------- */
+/* Detect if DMA controller is present or not */
+/* --------------------------------------------------------------- */
+
+int pl230_dma_detect(void)
+{
+ int result;
+ int volatile rdata; /* dummy variable for read data in bus fault testing */
+ unsigned const int pl230_id[12] = {
+ 0x30, 0xB2, 0x0B, 0x00,
+ 0x0D, 0xF0, 0x05, 0xB1};
+ puts("Detect if DMA controller is present...");
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ rdata = address_test_read(CMSDK_PL230_BASE+ 0xFE0);
+ hardfault_expected = 0;
+ result = hardfault_occurred ? 1 : ID_Check(&pl230_id[0], CMSDK_PL230_BASE);
+ hardfault_occurred = 0;
+ if (result!=0) {
+ puts("** TEST SKIPPED ** DMA controller is not present.\n");
+ UartEndSimulation();
+ }
+ return(result);
+}
+
+int ID_Check(const unsigned int id_array[], unsigned int offset)
+{
+int i;
+unsigned long expected_val, actual_val;
+unsigned long compare_mask;
+int mismatch = 0;
+unsigned long test_addr;
+
+ /* Check the peripheral ID and component ID */
+ for (i=0;i<8;i++) {
+ test_addr = offset + 4*i + 0xFE0;
+ expected_val = id_array[i];
+ actual_val = HW32_REG(test_addr);
+
+ /* create mask to ignore version numbers */
+ if (i==2) { compare_mask = 0xF0;} // mask out version field
+ else { compare_mask = 0x00;} // compare whole value
+
+ if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
+ printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
+ mismatch++;
+ }
+
+ } // end_for
+return (mismatch);
+}
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA data structure */
+/* --------------------------------------------------------------- */
+void dma_data_struct_init(void)
+{
+ int i; /* loop counter */
+ unsigned int ptr;
+
+ int ch_num; /* number of channels */
+ unsigned int blksize; /* Size of DMA data structure in bytes */
+ unsigned int blkmask; /* address mask */
+
+
+ ch_num = (((CMSDK_DMA->DMA_STATUS) >> 16) & 0x1F)+1;
+ blksize = ch_num * 32;
+ if (ch_num > 16) blkmask = 0x3FF; /* 17 to 32 */
+ else if (ch_num > 8) blkmask = 0x1FF; /* 9 to 16 */
+ else if (ch_num > 4) blkmask = 0x0FF; /* 5 to 8 */
+ else if (ch_num > 2) blkmask = 0x07F; /* 3 to 4 */
+ else if (ch_num > 1) blkmask = 0x07F; /* 2 */
+ else blkmask = 0x03F; /* 1 */
+
+ /* Create DMA data structure in RAM after stack
+ In the linker script, a 1KB memory stack above stack is reserved
+ so we can use this space for putting the DMA data structure.
+ */
+
+// ptr = HW32_REG(0); /* Read Top of Stack */
+ ptr = 0x80000000; /* DMA memory bank */
+
+ /* the DMA data structure must be aligned to the size of the data structure */
+ if ((ptr & blkmask) != 0x0)
+ ptr = (ptr + blksize) & ~blkmask;
+
+ if ((ptr + blksize) > (RAM_ADDRESS_MAX + 1)) {
+ puts ("ERROR : Not enough RAM space for DMA data structure.");
+ UartEndSimulation();
+ }
+
+ /* Set pointer to the reserved space */
+ dma_data = (pl230_dma_data_structure *) ptr;
+ ptr = (unsigned int) &dma_data->Primary->SrcEndPointer;
+
+ printf ("dma structure block address = %x\n", ptr);
+
+ for (i=0; i<1; i++) {
+ dma_data->Primary->SrcEndPointer = 0;
+ dma_data->Primary->DestEndPointer = 0;
+ dma_data->Primary->Control = 0;
+ dma_data->Alternate->SrcEndPointer = 0;
+ dma_data->Alternate->DestEndPointer = 0;
+ dma_data->Alternate->Control = 0;
+ }
+
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA PL230 */
+/* --------------------------------------------------------------- */
+void dma_pl230_init(void)
+{
+ unsigned int current_state;
+ puts ("Initialize PL230");
+ current_state = CMSDK_DMA->DMA_STATUS;
+ printf ("- # of channels allowed : %d\n",(((current_state) >> 16) & 0x1F)+1);
+ /* Debugging printfs: */
+ /*printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));*/
+ /*printf ("- Current master enable : %x\n",(((current_state) >> 0) & 0x1));*/
+
+ /* Wait until current DMA complete */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ if (!((current_state==0) || (current_state==0x8) || (current_state==0x9))) {
+ puts ("- wait for DMA IDLE/STALLED/DONE");
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+
+ }
+ while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
+ /* Wait if not IDLE/STALLED/DONE */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+ }
+ CMSDK_DMA->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ CMSDK_DMA->CTRL_BASE_PTR = (unsigned int) &dma_data->Primary->SrcEndPointer;
+ /* Set DMA data structure address */
+ CMSDK_DMA->CHNL_ENABLE_CLR = 0xFFFFFFFF; /* Disable all channels */
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+ CMSDK_DMA->DMA_CFG = 1; /* Enable DMA controller */
+
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* DMA memory copy */
+/* --------------------------------------------------------------- */
+void dma_memory_copy (unsigned int src, unsigned int dest, unsigned int size, unsigned int num)
+{
+ unsigned long src_end_pointer = src + ((1<<size)*(num-1));
+ unsigned long dst_end_pointer = dest + ((1<<size)*(num-1));
+ unsigned long control = (size << 30) | /* dst_inc */
+ (size << 28) | /* dst_size */
+ (size << 26) | /* src_inc */
+ (size << 24) | /* src_size */
+ (size << 21) | /* dst_prot_ctrl - HPROT[3:1] */
+ (size << 18) | /* src_prot_ctrl - HPROT[3:1] */
+ (0 << 14) | /* R_power */
+ ((num-1)<< 4) | /* n_minus_1 */
+ (0 << 3) | /* next_useburst */
+ (2 << 0) ; /* cycle_ctrl - auto */
+
+ /* By default the PL230 is little-endian; if the processor is configured
+ * big-endian then the configuration data that is written to memory must be
+ * byte-swapped before being written. This is also true if the processor is
+ * little-endian and the PL230 is big-endian.
+ * Remove the __REV usage if the processor and PL230 are configured with the
+ * same endianness
+ * */
+ dma_data->Primary->SrcEndPointer = (EXPECTED_BE) ? __REV(src_end_pointer) : (src_end_pointer);
+ dma_data->Primary->DestEndPointer = (EXPECTED_BE) ? __REV(dst_end_pointer) : (dst_end_pointer);
+ dma_data->Primary->Control = (EXPECTED_BE) ? __REV(control ) : (control );
+ /* Debugging printfs: */
+ /*printf ("SrcEndPointer = %x\n", dma_data->Primary->SrcEndPointer);*/
+ /*printf ("DestEndPointer = %x\n", dma_data->Primary->DestEndPointer);*/
+
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+ CMSDK_DMA->CHNL_SW_REQUEST = (1<<0); /* request channel 0 DMA */
+
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* Simple software DMA test */
+/* --------------------------------------------------------------- */
+int dma_simple_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ unsigned int current_state;
+
+
+ puts("uDMA simple test");
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<1024;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ /* Start timer */
+ CMSDK_TIMER0->
+
+ dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 2, 4);
+ do { /* Wait until PL230 DMA controller return to idle state */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ } while (current_state!=0);
+
+ for (i=0;i<4;i++) {
+ /* Debugging printf: */
+ /*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
+ if (dest_data_array[i]!= i){
+ printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
+ err_code |= (1<<i);
+ }
+ }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : simple DMA failed (0x%x)\n", err_code);
+ return_val=1;
+ } else {
+ puts ("-Passed");
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* Simple DMA interrupt test */
+/* --------------------------------------------------------------- */
+int dma_interrupt_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ unsigned int current_state;
+
+
+ puts("DMA interrupt test");
+ puts("- DMA done");
+
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 2, 4);
+ delay();
+ /* Can't guarantee that there is sleep support, so use a polling loop */
+ do { /* Wait until PL230 DMA controller return to idle state */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ } while (current_state!=0);
+
+ for (i=0;i<4;i++) {
+ /* Debugging printf: */
+ /*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
+ if (dest_data_array[i]!= i){
+ printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
+ err_code |= (1<<i);
+ }
+ }
+
+ if (dma_done_irq_occurred==0){
+ puts ("ERROR: DMA done IRQ missing");
+ err_code |= (1<<4);
+ }
+
+ puts("- DMA err");
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_error_irq_expected = 1;
+ dma_error_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ /* Generate DMA transfer to invalid memory location */
+ dma_memory_copy ((unsigned int) &source_data_array[0],0xEF000000, 2, 4);
+ delay();
+ /* Can't guarantee that there is sleep support, so use a polling loop */
+ do { /* Wait until PL230 DMA controller return to idle state */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ } while (current_state!=0);
+
+ if (dma_error_irq_occurred==0){
+ puts ("ERROR: DMA err IRQ missing");
+ err_code |= (1<<5);
+ }
+
+
+ /* Clear up */
+ dma_done_irq_expected = 0;
+ dma_done_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ NVIC_DisableIRQ(DMA_IRQn);
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : DMA done interrupt failed (0x%x)\n", err_code);
+ return_val=1;
+ } else {
+ puts ("-Passed");
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* DMA event test */
+/* --------------------------------------------------------------- */
+int dma_event_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ unsigned int current_state;
+
+
+ puts("DMA event test");
+ puts("- DMA done event to RXEV");
+
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_DisableIRQ(DMA_IRQn);
+
+ /* Clear event register - by setting event with SEV and then clear it with WFE */
+ __SEV();
+ __WFE(); /* First WFE will not enter sleep because of previous event */
+
+ dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 2, 4);
+ __WFE(); /* This will cause the processor to enter sleep */
+
+ /* Processor woken up */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ if (current_state!=0) {
+ puts ("ERROR: DMA status should be IDLE after wake up");
+ err_code |= (1<<5);
+ }
+
+ for (i=0;i<4;i++) {
+ /*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
+ if (dest_data_array[i]!= i){
+ printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
+ err_code |= (1<<i);
+ }
+ }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : DMA event failed (0x%x)\n", err_code);
+ return_val=1;
+ } else {
+ puts ("-Passed");
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* DMA interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void DMA_Handler(void)
+{
+if ((CMSDK_DMA->ERR_CLR & 1) != 0) {
+ /* DMA interrupt is caused by DMA error */
+ dma_error_irq_occurred ++;
+ CMSDK_DMA->ERR_CLR = 1; /* Clear dma_err */
+ if (dma_error_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+else {
+ // DMA interrupt is caused by DMA done
+ dma_done_irq_occurred ++;
+ if (dma_done_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA done interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+}
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+ ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
+
+void delay(void)
+{
+ int i;
+ for (i=0;i<5;i++){
+ __ISB();
+ }
+ return;
+}
+
diff --git a/synthesis/genus.tcl b/synthesis/genus.tcl
index d4e8ca14b4d095a6841f4fefd16c4bac5d66b90a..0c07cc3866e69bf4f93ceaf95556edac93fd21c1 100644
--- a/synthesis/genus.tcl
+++ b/synthesis/genus.tcl
@@ -1,9 +1,12 @@
-set_db init_lib_search_path $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/
-set_db library sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib
+set_db init_lib_search_path ./
+set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib
+set RF_LIB ../../../cadence_flow/memory/rf/rf_sp_hdf_tt_1p20v_1p20v_25c.lib
+set_db / .library "$BASE_LIB $RF_LIB"
source $::env(SOCLABS_PROJECT_DIR)/imp/fpga/nanosoc/flist/genus_flist.tcl
elaborate nanosoc_chip_pads
+set_db syn_generic_effort high
syn_generic
diff --git a/synthesis/synopsys.tcl b/synthesis/synopsys.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..71c951721745dbf9f79caf93850b4b438b3a1952
--- /dev/null
+++ b/synthesis/synopsys.tcl
@@ -0,0 +1,36 @@
+create_design nanosoc_ASIC
+
+#####
+# Set search_path
+#
+# List locations where your standard cell libraries may be located
+#
+#####
+set search_path [list . $search_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/sdb/ /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/ /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf]
+
+######
+# Set Target Library
+#
+# Set a default target library for Design Compiler to target when compiling a design
+#
+######
+set target_library "sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db RF_LIB_tt_1p20v_1p20v_25c.db"
+
+######
+# Set Link Library
+#
+# Set a default link library for Design Compiler to target when compiling a design
+#
+######
+set link_library sc9_cln65lp_base_rvt.sdb
+
+source $::env(SOCLABS_PROJECT_DIR)/imp/fpga/nanosoc/flist/synopsys_flist.tcl
+
+current_design nanosoc_chip_pads
+
+compile
+
+write -hierarchy -format verilog -output ./nanosoc_chip_pads.vm
+
+
+exit
\ No newline at end of file