From 67f078ed182b87b25f226fd20e9e0f95e3508045 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 28 Apr 2023 16:41:29 +0100
Subject: [PATCH] SOC1-167: Prefixed other verif and test_io verilog files with
nanosoc
---
system/src/nanosoc_ahb_busmatrix/makefile | 5 ++++-
.../test_io/{axi_stream_io => }/verilog/axi_stream_io_v1_0.v | 2 +-
.../{axi_stream_io => }/verilog/axi_stream_io_v1_0_axi_s.v | 2 +-
.../ADPcontrol_v1_0.v => verilog/nanosoc_adp_control_v1_0.v} | 0
.../verilog/ADPmanager.v => verilog/nanosoc_adp_manager.v} | 2 +-
.../nanosoc_ft1248_stream_io_v1_0.v} | 2 +-
system/test_io/{ => verilog}/nanosoc_ft1248x1_adpio.v | 0
.../nanosoc_axi_stream_io_8_buffer.v} | 0
.../nanosoc_axi_stream_io_8_rxd_to_file.v} | 0
.../nanosoc_axi_stream_io_8_txd_from_file.v} | 0
system/verif/{ => verilog}/nanosoc_clkreset.v | 0
.../{dma_log_to_file.v => verilog/nanosoc_dma_log_to_file.v} | 2 +-
.../nanosoc_ft1248x1_to_axi_streamio_v1_0.v} | 2 +-
.../{ft1248x1_track.v => verilog/nanosoc_ft1248x1_track.v} | 0
system/verif/{tb_nanosoc.v => verilog/nanosoc_tb.v} | 2 +-
.../nanosoc_track_tb_iostream.v} | 2 +-
system/verif/{ => verilog}/nanosoc_uart_capture.v | 0
17 files changed, 12 insertions(+), 9 deletions(-)
rename system/test_io/{axi_stream_io => }/verilog/axi_stream_io_v1_0.v (95%)
rename system/test_io/{axi_stream_io => }/verilog/axi_stream_io_v1_0_axi_s.v (96%)
rename system/test_io/{adp_control/verilog/ADPcontrol_v1_0.v => verilog/nanosoc_adp_control_v1_0.v} (100%)
rename system/test_io/{adp_control/verilog/ADPmanager.v => verilog/nanosoc_adp_manager.v} (99%)
rename system/test_io/{ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v => verilog/nanosoc_ft1248_stream_io_v1_0.v} (97%)
rename system/test_io/{ => verilog}/nanosoc_ft1248x1_adpio.v (100%)
rename system/verif/{axi_stream_io_8_buffer.v => verilog/nanosoc_axi_stream_io_8_buffer.v} (100%)
rename system/verif/{axi_stream_io_8_rxd_to_file.v => verilog/nanosoc_axi_stream_io_8_rxd_to_file.v} (100%)
rename system/verif/{axi_stream_io_8_txd_from_file.v => verilog/nanosoc_axi_stream_io_8_txd_from_file.v} (100%)
rename system/verif/{ => verilog}/nanosoc_clkreset.v (100%)
rename system/verif/{dma_log_to_file.v => verilog/nanosoc_dma_log_to_file.v} (99%)
rename system/verif/{ft1248x1_to_axi_stream_io_v1_0.v => verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v} (99%)
rename system/verif/{ft1248x1_track.v => verilog/nanosoc_ft1248x1_track.v} (100%)
rename system/verif/{tb_nanosoc.v => verilog/nanosoc_tb.v} (99%)
rename system/verif/{track_tb_iostream.v => verilog/nanosoc_track_tb_iostream.v} (99%)
rename system/verif/{ => verilog}/nanosoc_uart_capture.v (100%)
diff --git a/system/src/nanosoc_ahb_busmatrix/makefile b/system/src/nanosoc_ahb_busmatrix/makefile
index 176c8bf..7455cec 100644
--- a/system/src/nanosoc_ahb_busmatrix/makefile
+++ b/system/src/nanosoc_ahb_busmatrix/makefile
@@ -17,6 +17,9 @@ MATRIX_NAME ?= nanosoc_ahb32_4x7
# Top-level directory of Bus Matrix
BUS_MATRIX_DIR ?= $(NANOSOC_TECH_DIR)/systems/nanosoc/src/nanosoc_ahb_busmatrix
+# Directory location of BuildBusMatrix Script
+SOURCE_DIR = $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_busmatrix
+
# Location of Bus Matrix XML
XML_DIR = $(BUS_MATRIX_DIR)/xml
@@ -30,4 +33,4 @@ GEN_OPTIONS = -notimescales -xmldir $(XML_DIR) -cfg $(MATRIX_NAME).xml -ipxact
build:
@echo "Generating NanoSoC Bus Matrix"
- @bin/BuildBusMatrix.pl $(GEN_OPTIONS)
\ No newline at end of file
+ @$(SOURCE_DIR)/bin/BuildBusMatrix.pl $(GEN_OPTIONS)
\ No newline at end of file
diff --git a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v b/system/test_io/verilog/axi_stream_io_v1_0.v
similarity index 95%
rename from system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
rename to system/test_io/verilog/axi_stream_io_v1_0.v
index a229917..0c52be8 100755
--- a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
+++ b/system/test_io/verilog/axi_stream_io_v1_0.v
@@ -1,7 +1,7 @@
`timescale 1 ns / 1 ps
- module iostream_v1_0 #
+ module axi_stream_io_v1_0 #
(
// Users to add parameters here
diff --git a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v b/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
similarity index 96%
rename from system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
rename to system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
index d8e6eea..303780e 100755
--- a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
+++ b/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
@@ -1,7 +1,7 @@
`timescale 1 ns / 1 ps
- module iostream_v1_0_axi #
+ module axi_stream_io_v1_0_axi_s #
(
// Users to add parameters here
diff --git a/system/test_io/adp_control/verilog/ADPcontrol_v1_0.v b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
similarity index 100%
rename from system/test_io/adp_control/verilog/ADPcontrol_v1_0.v
rename to system/test_io/verilog/nanosoc_adp_control_v1_0.v
diff --git a/system/test_io/adp_control/verilog/ADPmanager.v b/system/test_io/verilog/nanosoc_adp_manager.v
similarity index 99%
rename from system/test_io/adp_control/verilog/ADPmanager.v
rename to system/test_io/verilog/nanosoc_adp_manager.v
index a6bc70c..d536157 100755
--- a/system/test_io/adp_control/verilog/ADPmanager.v
+++ b/system/test_io/verilog/nanosoc_adp_manager.v
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// soclabs ASCII Debug Protocol controller
+// SoCLabs ASCII Debug Protocol controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
diff --git a/system/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v b/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
similarity index 97%
rename from system/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
rename to system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
index 00cf6c4..21b14bc 100755
--- a/system/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
+++ b/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
@@ -9,7 +9,7 @@
// Copyright � 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module ft1248_stream_io_v1_0 #
+module nanosoc_ft1248_stream_io_v1_0 #
(
// Users to add parameters here
// FTDI Interface 1,2,4 width supported
diff --git a/system/test_io/nanosoc_ft1248x1_adpio.v b/system/test_io/verilog/nanosoc_ft1248x1_adpio.v
similarity index 100%
rename from system/test_io/nanosoc_ft1248x1_adpio.v
rename to system/test_io/verilog/nanosoc_ft1248x1_adpio.v
diff --git a/system/verif/axi_stream_io_8_buffer.v b/system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
similarity index 100%
rename from system/verif/axi_stream_io_8_buffer.v
rename to system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
diff --git a/system/verif/axi_stream_io_8_rxd_to_file.v b/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
similarity index 100%
rename from system/verif/axi_stream_io_8_rxd_to_file.v
rename to system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
diff --git a/system/verif/axi_stream_io_8_txd_from_file.v b/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
similarity index 100%
rename from system/verif/axi_stream_io_8_txd_from_file.v
rename to system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
diff --git a/system/verif/nanosoc_clkreset.v b/system/verif/verilog/nanosoc_clkreset.v
similarity index 100%
rename from system/verif/nanosoc_clkreset.v
rename to system/verif/verilog/nanosoc_clkreset.v
diff --git a/system/verif/dma_log_to_file.v b/system/verif/verilog/nanosoc_dma_log_to_file.v
similarity index 99%
rename from system/verif/dma_log_to_file.v
rename to system/verif/verilog/nanosoc_dma_log_to_file.v
index 9458671..68f61eb 100644
--- a/system/verif/dma_log_to_file.v
+++ b/system/verif/verilog/nanosoc_dma_log_to_file.v
@@ -9,7 +9,7 @@
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module dma_log_to_file
+module nanosoc_dma_log_to_file
#(parameter FILENAME = "dma.log",
parameter NUM_CHNLS = 2,
parameter NUM_CHNL_BITS = 1,
diff --git a/system/verif/ft1248x1_to_axi_stream_io_v1_0.v b/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
similarity index 99%
rename from system/verif/ft1248x1_to_axi_stream_io_v1_0.v
rename to system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
index 96ba001..983594d 100644
--- a/system/verif/ft1248x1_to_axi_stream_io_v1_0.v
+++ b/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
@@ -13,7 +13,7 @@
// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
//-----------------------------------------------------------------------------
- module ft1248x1_to_axi_stream_io_v1_0 #
+ module nanosoc_ft1248x1_to_axi_streamio_v1_0 #
(
// Users to add parameters here
diff --git a/system/verif/ft1248x1_track.v b/system/verif/verilog/nanosoc_ft1248x1_track.v
similarity index 100%
rename from system/verif/ft1248x1_track.v
rename to system/verif/verilog/nanosoc_ft1248x1_track.v
diff --git a/system/verif/tb_nanosoc.v b/system/verif/verilog/nanosoc_tb.v
similarity index 99%
rename from system/verif/tb_nanosoc.v
rename to system/verif/verilog/nanosoc_tb.v
index 09a7493..4db768f 100644
--- a/system/verif/tb_nanosoc.v
+++ b/system/verif/verilog/nanosoc_tb.v
@@ -37,7 +37,7 @@
//
`timescale 1ns/1ps
-module tb_nanosoc;
+module nanosoc_tb;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
diff --git a/system/verif/track_tb_iostream.v b/system/verif/verilog/nanosoc_track_tb_iostream.v
similarity index 99%
rename from system/verif/track_tb_iostream.v
rename to system/verif/verilog/nanosoc_track_tb_iostream.v
index 4ca22a0..4517662 100644
--- a/system/verif/track_tb_iostream.v
+++ b/system/verif/verilog/nanosoc_track_tb_iostream.v
@@ -13,7 +13,7 @@
// Abstract : track output stream for testbench signalling
//-----------------------------------------------------------------------------
-module track_tb_iostream
+module nanosoc_track_tb_iostream
(
input wire aclk,
input wire aresetn,
diff --git a/system/verif/nanosoc_uart_capture.v b/system/verif/verilog/nanosoc_uart_capture.v
similarity index 100%
rename from system/verif/nanosoc_uart_capture.v
rename to system/verif/verilog/nanosoc_uart_capture.v
--
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