diff --git a/system/src/nanosoc_ahb_busmatrix/makefile b/system/src/nanosoc_ahb_busmatrix/makefile
index 176c8bf74e23bb0afa04e26e7b1980d28194df44..7455cec4c8d8d6971c2c7c63487a9fa20a2e7ba2 100644
--- a/system/src/nanosoc_ahb_busmatrix/makefile
+++ b/system/src/nanosoc_ahb_busmatrix/makefile
@@ -17,6 +17,9 @@ MATRIX_NAME ?= nanosoc_ahb32_4x7
 # Top-level directory of Bus Matrix
 BUS_MATRIX_DIR  ?= $(NANOSOC_TECH_DIR)/systems/nanosoc/src/nanosoc_ahb_busmatrix
 
+# Directory location of BuildBusMatrix Script
+SOURCE_DIR  = $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_busmatrix
+
 # Location of Bus Matrix XML
 XML_DIR     = $(BUS_MATRIX_DIR)/xml
 
@@ -30,4 +33,4 @@ GEN_OPTIONS  = -notimescales -xmldir $(XML_DIR) -cfg $(MATRIX_NAME).xml -ipxact
 
 build: 
 	@echo "Generating NanoSoC Bus Matrix"
-	@bin/BuildBusMatrix.pl $(GEN_OPTIONS)
\ No newline at end of file
+	@$(SOURCE_DIR)/bin/BuildBusMatrix.pl $(GEN_OPTIONS)
\ No newline at end of file
diff --git a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v b/system/test_io/verilog/axi_stream_io_v1_0.v
similarity index 95%
rename from system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
rename to system/test_io/verilog/axi_stream_io_v1_0.v
index a229917f1d1ba9277051b772cfebef6767cacd0e..0c52be8420c4f63ab7eab0db84cc185a5073bcc6 100755
--- a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
+++ b/system/test_io/verilog/axi_stream_io_v1_0.v
@@ -1,7 +1,7 @@
 
 `timescale 1 ns / 1 ps
 
-	module iostream_v1_0 #
+	module axi_stream_io_v1_0 #
 	(
 		// Users to add parameters here
 
diff --git a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v b/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
similarity index 96%
rename from system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
rename to system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
index d8e6eea56a867b6dc1a997a0094d8d7da474bdc1..303780efefce184c1f353751c71280794b5348bd 100755
--- a/system/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
+++ b/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
@@ -1,7 +1,7 @@
 
 `timescale 1 ns / 1 ps
 
-	module iostream_v1_0_axi #
+	module axi_stream_io_v1_0_axi_s #
 	(
 		// Users to add parameters here
 
diff --git a/system/test_io/adp_control/verilog/ADPcontrol_v1_0.v b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
similarity index 100%
rename from system/test_io/adp_control/verilog/ADPcontrol_v1_0.v
rename to system/test_io/verilog/nanosoc_adp_control_v1_0.v
diff --git a/system/test_io/adp_control/verilog/ADPmanager.v b/system/test_io/verilog/nanosoc_adp_manager.v
similarity index 99%
rename from system/test_io/adp_control/verilog/ADPmanager.v
rename to system/test_io/verilog/nanosoc_adp_manager.v
index a6bc70c0911aabe9484efb5758009440f0a5960a..d536157e632237f992d3e00cacd0d03cc47786eb 100755
--- a/system/test_io/adp_control/verilog/ADPmanager.v
+++ b/system/test_io/verilog/nanosoc_adp_manager.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// soclabs ASCII Debug Protocol controller
+// SoCLabs ASCII Debug Protocol controller
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
diff --git a/system/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v b/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
similarity index 97%
rename from system/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
rename to system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
index 00cf6c4410401e14dce313ff36561503cb364f50..21b14bc7923dcadcbd85c628c777319e1f831a66 100755
--- a/system/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
+++ b/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
@@ -9,7 +9,7 @@
 // Copyright � 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
-module ft1248_stream_io_v1_0 #
+module nanosoc_ft1248_stream_io_v1_0 #
 	(
 		// Users to add parameters here
 		// FTDI Interface 1,2,4 width supported
diff --git a/system/test_io/nanosoc_ft1248x1_adpio.v b/system/test_io/verilog/nanosoc_ft1248x1_adpio.v
similarity index 100%
rename from system/test_io/nanosoc_ft1248x1_adpio.v
rename to system/test_io/verilog/nanosoc_ft1248x1_adpio.v
diff --git a/system/verif/axi_stream_io_8_buffer.v b/system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
similarity index 100%
rename from system/verif/axi_stream_io_8_buffer.v
rename to system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
diff --git a/system/verif/axi_stream_io_8_rxd_to_file.v b/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
similarity index 100%
rename from system/verif/axi_stream_io_8_rxd_to_file.v
rename to system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
diff --git a/system/verif/axi_stream_io_8_txd_from_file.v b/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
similarity index 100%
rename from system/verif/axi_stream_io_8_txd_from_file.v
rename to system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
diff --git a/system/verif/nanosoc_clkreset.v b/system/verif/verilog/nanosoc_clkreset.v
similarity index 100%
rename from system/verif/nanosoc_clkreset.v
rename to system/verif/verilog/nanosoc_clkreset.v
diff --git a/system/verif/dma_log_to_file.v b/system/verif/verilog/nanosoc_dma_log_to_file.v
similarity index 99%
rename from system/verif/dma_log_to_file.v
rename to system/verif/verilog/nanosoc_dma_log_to_file.v
index 9458671e89b82b9621086e7f223761a6db684987..68f61eb4a29ee9a53046621be0209cf20a36797c 100644
--- a/system/verif/dma_log_to_file.v
+++ b/system/verif/verilog/nanosoc_dma_log_to_file.v
@@ -9,7 +9,7 @@
 // Copyright (C) 2023, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
-module dma_log_to_file
+module nanosoc_dma_log_to_file
   #(parameter FILENAME = "dma.log",
     parameter NUM_CHNLS = 2,
     parameter NUM_CHNL_BITS = 1,
diff --git a/system/verif/ft1248x1_to_axi_stream_io_v1_0.v b/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
similarity index 99%
rename from system/verif/ft1248x1_to_axi_stream_io_v1_0.v
rename to system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
index 96ba001af4ac83c70af5558f18e61f79f0f73c5d..983594d6858b7ce986651131cf45d53cb40e15f4 100644
--- a/system/verif/ft1248x1_to_axi_stream_io_v1_0.v
+++ b/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
@@ -13,7 +13,7 @@
 // Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
 //-----------------------------------------------------------------------------
 
- module ft1248x1_to_axi_stream_io_v1_0 #
+ module nanosoc_ft1248x1_to_axi_streamio_v1_0 #
  (
          // Users to add parameters here
 
diff --git a/system/verif/ft1248x1_track.v b/system/verif/verilog/nanosoc_ft1248x1_track.v
similarity index 100%
rename from system/verif/ft1248x1_track.v
rename to system/verif/verilog/nanosoc_ft1248x1_track.v
diff --git a/system/verif/tb_nanosoc.v b/system/verif/verilog/nanosoc_tb.v
similarity index 99%
rename from system/verif/tb_nanosoc.v
rename to system/verif/verilog/nanosoc_tb.v
index 09a7493df578707579d36da5eef77dc0e2818276..4db768ff2634a4c55b67d0ceb105270431687155 100644
--- a/system/verif/tb_nanosoc.v
+++ b/system/verif/verilog/nanosoc_tb.v
@@ -37,7 +37,7 @@
 //
 `timescale 1ns/1ps
 
-module tb_nanosoc;
+module nanosoc_tb;
 
   wire        XTAL1;   // crystal pin 1
   wire        XTAL2;   // crystal pin 2
diff --git a/system/verif/track_tb_iostream.v b/system/verif/verilog/nanosoc_track_tb_iostream.v
similarity index 99%
rename from system/verif/track_tb_iostream.v
rename to system/verif/verilog/nanosoc_track_tb_iostream.v
index 4ca22a050e6265223f12ca7efa1155bc8f7708f5..45176626f5c52f6f2e754d1d05dd6c5911554ebb 100644
--- a/system/verif/track_tb_iostream.v
+++ b/system/verif/verilog/nanosoc_track_tb_iostream.v
@@ -13,7 +13,7 @@
 // Abstract : track output stream for testbench signalling
 //-----------------------------------------------------------------------------
 
-module track_tb_iostream
+module nanosoc_track_tb_iostream
   (
   input  wire       aclk,
   input  wire       aresetn,
diff --git a/system/verif/nanosoc_uart_capture.v b/system/verif/verilog/nanosoc_uart_capture.v
similarity index 100%
rename from system/verif/nanosoc_uart_capture.v
rename to system/verif/verilog/nanosoc_uart_capture.v