diff --git a/system/html/v2html_doc.tgz b/system/html/v2html_doc.tgz
new file mode 100644
index 0000000000000000000000000000000000000000..44358042a2d561553fb420d0c2f9fb625e395449
Binary files /dev/null and b/system/html/v2html_doc.tgz differ
diff --git a/system/makefile b/system/makefile
index fde6089f3274b4802e6374c7199c74d84007195d..59eaff51169a5e3cf25828862577dfd181ca9585 100644
--- a/system/makefile
+++ b/system/makefile
@@ -38,12 +38,12 @@
# Configurations
# Directory of Testcodes
-NANOSOC_SYSTEMS_DIR ?= $(NANOSOC_TECH_DIR)/systems
-NANOSOC_SW_DIR ?= $(NANOSOC_TECH_DIR)/software
+NANOSOC_SYSTEM_DIR ?= $(NANOSOC_TECH_DIR)/system
+NANOSOC_SW_DIR ?= $(NANOSOC_TECH_DIR)/software
-NANOSOC_MCU_DIR := $(NANOSOC_SYSTEMS_DIR)/mcu
-VERILOG_DIR := $(NANOSOC_MCU_DIR)/verilog
-TESTCODES_DIR := $(NANOSOC_MCU_DIR)/testcodes
+NANOSOC_HTML_DIR := $(NANOSOC_SYSTEM_DIR)/html
+VERILOG_DIR := $(NANOSOC_SYSTEM_DIR)/verilog
+TESTCODES_DIR := $(NANOSOC_SYSTEM_DIR)/testcodes
# Name of test directory (e.g. hello, dhry)
# TESTNAME must be specified on the make command line
@@ -381,15 +381,15 @@ compile_all_code: bootrom debugtester
v2html:
echo building HTML tree
- @if [ ! -d $(NANOSOC_MCU_DIR)/v2html_doc ] ; then \
- mkdir $(NANOSOC_MCU_DIR)/v2html_doc; \
+ @if [ ! -d $(NANOSOC_HTML_DIR)/build ] ; then \
+ mkdir $(NANOSOC_HTML_DIR)/build; \
fi
- @(cd $(NANOSOC_MCU_DIR)/v2html_doc; \
+ @(cd $(NANOSOC_HTML_DIR)/build; \
rm *.html; rm *.gif; rm *.gz; \
~/tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht nanosoc_chip ; \
cp -p tb_nanosoc.v.html hierarchy.html ; \
cd $(SIM_DIR) ; )
- gtar zcvf $(NANOSOC_MCU_DIR)/v2html_doc.tgz $(NANOSOC_MCU_DIR)/v2html_doc
+ gtar zcvf $(NANOSOC_HTML_DIR)/v2html_doc.tgz $(NANOSOC_HTML_DIR)/build
# Remove all software compilation results
diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/verilog/nanosoc_chip.v
index 336667bd98b55186c12ef1865775104df5e2b584..3da5bf35ded703280c19483d18abbfe2dbc89478 100644
--- a/system/src/verilog/nanosoc_chip.v
+++ b/system/src/verilog/nanosoc_chip.v
@@ -198,7 +198,7 @@ localparam CORTEX_M0 = 1;
wire SYSRESETREQ; // processor system reset request
wire WDOGRESETREQ; // watchdog system reset request
wire HRESETREQ; // Combined system reset request
- wire cmsdk_SYSRESETREQ; // Combined system reset request
+ wire NANOSOC_SYSRESETREQ; // Combined system reset request
wire clk_ctrl_sys_reset_req;
wire PMUHRESETREQ;
wire PMUDBGRESETREQ;
@@ -250,15 +250,15 @@ localparam CORTEX_M0 = 1;
// System Reset request can be from processor or watchdog
// or when lockup happens and the control flag is set.
- assign cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
+ assign NANOSOC_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
ADPRESETREQ |
(LOCKUP & LOCKUPRESET);
assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
// Clock controller to generate reset and clock signals
- cmsdk_mcu_clkctrl
+ nanosoc_mcu_clkctrl
#(.CLKGATE_PRESENT(CLKGATE_PRESENT))
- u_cmsdk_mcu_clkctrl(
+ u_nanosoc_mcu_clkctrl(
// inputs
.XTAL1 (CLK),
.NRST (nrst_in),
@@ -298,7 +298,7 @@ localparam CORTEX_M0 = 1;
.FCLK (FCLK),
.HCLK (gated_hclk),
.DCLK (gated_dclk),
- .SYSRESETREQ (cmsdk_SYSRESETREQ),
+ .SYSRESETREQ (NANOSOC_SYSRESETREQ),
.PMUHRESETREQ (PMUHRESETREQ),
.PMUDBGRESETREQ (PMUDBGRESETREQ),
.RSTBYPASS (TESTMODE),
@@ -316,7 +316,7 @@ localparam CORTEX_M0 = 1;
( // Inputs
.FCLK (FCLK),
.PORESETn (PORESETn),
- .HRESETREQ (cmsdk_SYSRESETREQ), // from processor / watchdog
+ .HRESETREQ (NANOSOC_SYSRESETREQ), // from processor / watchdog
.PMUENABLE (PMUENABLE), // from System Controller
.WICENACK (WICENACK), // from WIC in integration
@@ -1218,7 +1218,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
assign HAUSER_adp [1:0] = 2'b00; // Address USER signals
assign HWUSER_adp [1:0] = 2'b00; // Write-data USER signals
- cmsdk_apb_usrt u_apb_usrt_com (
+ nanosoc_apb_usrt u_apb_usrt_com (
.PCLK (PCLK), // Peripheral clock
.PCLKG (PCLKG), // Gated PCLK for bus
.PRESETn (PRESETn), // Reset
@@ -1603,7 +1603,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
assign swdio_e = SWDOEN;
assign swdio_z = !SWDOEN;
- cmsdk_mcu_pin_mux
+ nanosoc_mcu_pin_mux
u_pin_mux (
// UART
.uart0_rxd (uart0_rxd),
diff --git a/system/src/verilog/nanosoc_cpu.v b/system/src/verilog/nanosoc_cpu.v
index 29ee363f19602a0cf2c732d59f0e9ec1f8a7c229..281e242cd09d1aa98c5aef2cf75dd9771af8307d 100644
--- a/system/src/verilog/nanosoc_cpu.v
+++ b/system/src/verilog/nanosoc_cpu.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -234,9 +234,9 @@ module nanosoc_cpu #(
// -------------------------------
// SysTick signals
// -------------------------------
- cmsdk_mcu_stclkctrl
+ nanosoc_mcu_stclkctrl
#(.DIV_RATIO (18'd01000))
- u_cmsdk_mcu_stclkctrl (
+ u_nanosoc_mcu_stclkctrl (
.FCLK (FCLK),
.SYSRESETn (HRESETn),
diff --git a/system/src/verilog/nanosoc_sysio.v b/system/src/verilog/nanosoc_sysio.v
index 5b5f208fb3af232372de3de0865567e255898a08..c6a271ceef9eb6df67f29111d38e5b3ffaa128ee 100644
--- a/system/src/verilog/nanosoc_sysio.v
+++ b/system/src/verilog/nanosoc_sysio.v
@@ -262,7 +262,7 @@ module nanosoc_sysio
// -------------------------------
// System ROM Table
// -------------------------------
- cmsdk_ahb_cs_rom_table
+ nanosoc_ahb_cs_rom_table
#(//.JEPID (),
//.JEPCONTINUATION (),
//.PARTNUMBER (),
@@ -297,8 +297,8 @@ module nanosoc_sysio
// Peripherals
// -------------------------------
- cmsdk_mcu_sysctrl #(.BE (BE))
- u_cmsdk_mcu_sysctrl
+ nanosoc_mcu_sysctrl #(.BE (BE))
+ u_nanosoc_mcu_sysctrl
(
// AHB Inputs
.HCLK (HCLK),
diff --git a/system/v2html_doc.tgz b/system/v2html_doc.tgz
deleted file mode 100644
index 35a2312298d655fb41fcb88be1aebe16587d1059..0000000000000000000000000000000000000000
Binary files a/system/v2html_doc.tgz and /dev/null differ
diff --git a/system/src/verilog/nanososc_clkreset.v b/system/verif/nanosoc_clkreset.v
similarity index 100%
rename from system/src/verilog/nanososc_clkreset.v
rename to system/verif/nanosoc_clkreset.v
diff --git a/system/verif/tb_nanosoc.v b/system/verif/tb_nanosoc.v
index 56c848c3c9801973c9b5ac7bffda536f37ba1bc1..09a7493df578707579d36da5eef77dc0e2818276 100644
--- a/system/verif/tb_nanosoc.v
+++ b/system/verif/tb_nanosoc.v
@@ -123,7 +123,7 @@ SROM_Ax32
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
- cmsdk_clkreset u_cmsdk_clkreset(
+ nanosoc_clkreset u_nanosoc_clkreset(
.CLK (XTAL1),
.NRST (NRST)
);
@@ -358,8 +358,8 @@ ft1248x1_track
.FTDI_IP2UART_o (ft_txd2uart) // Transmitted data to UART capture
);
- cmsdk_uart_capture #(.LOGFILENAME("ft1248_op.log"))
- u_cmsdk_uart_capture1(
+ nanosoc_uart_capture #(.LOGFILENAME("ft1248_op.log"))
+ u_nanosoc_uart_capture1(
.RESETn (NRST),
.CLK (ft_clk2uart),
.RXD (ft_rxd2uart),
@@ -368,8 +368,8 @@ ft1248x1_track
.AUXCTRL ()
);
- cmsdk_uart_capture #(.LOGFILENAME("ft1248_ip.log"))
- u_cmsdk_uart_capture2(
+ nanosoc_uart_capture #(.LOGFILENAME("ft1248_ip.log"))
+ u_nanosoc_uart_capture2(
.RESETn (NRST),
.CLK (ft_clk2uart),
.RXD (ft_txd2uart),