diff --git a/fpga/makefile b/flows/makefile.fpga similarity index 84% rename from fpga/makefile rename to flows/makefile.fpga index 98890a60d6abc453d30ba79754c21d5ee2b7827f..705eb9144701577de8e3f1c943dfdf0e01e2e0e0 100644 --- a/fpga/makefile +++ b/flows/makefile.fpga @@ -16,22 +16,14 @@ include $(SOCLABS_NANOSOC_TECH_DIR)/fpga/makefile.targets VIVIADO_VERSION ?= 2021_1 # NanoSoC Synthesis Properties -VENDOR ?= soclabs.org -CORE_REV ?= 2 - -# System Design Filelist -ifeq ($(QUICKSTART),yes) - DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist -else - DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist - NANOSOC_DEFINES += DMAC_0_PL230 -endif +NANOSOC_VENDOR ?= soclabs.org +NANOSOC_CORE_REV ?= 2 # Top-level of RTL design to Implement -COMPONENT_TOP ?= nanosoc_chip +COMPONENT_TOP ?= nanosoc_chip # Name of Implemented Chip Design (Including Socket IP) -DESIGN_NAME ?= nanosoc_design +DESIGN_NAME ?= nanosoc_design # Location to build FPGA files IMPLEMENTATION_DIR ?= $(SOCLABS_PROJECT_DIR)/imp/fpga @@ -66,30 +58,13 @@ else ifeq ($(PLATFORM), pynq) OUTPUT_DIR ?= $(IMPLEMENTATION_DIR)/output/$(BOARD_NAME)/overlays endif -# Is an accelerator subsystem present in the design? -ACCELERATOR ?= yes - -ifeq ($(ACCELERATOR),yes) - ACCELERATOR_SUBSYSTEM = ACCELERATOR_SUBSYSTEM -else - ACCELERATOR_SUBSYSTEM = 0 -endif - -# Defines to pass to filelist compile -NANOSOC_DEFINES += $(ACCELERATOR_SUBSYSTEM) - - # Compile Testcodes and Bootrom code: @echo Compiling Firmware @$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) bootrom -defs_nanosoc: - @mkdir -p $(DEFINES_DIR) - @$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE) - # Generate TCL filelist from flists -flist_nanosoc: defs_nanosoc +flist_nanosoc: gen_defs @mkdir -p $(TCL_FLIST_DIR) @(cd $(TCL_FLIST_DIR); \ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);) @@ -103,8 +78,8 @@ package_nanosoc: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST) package_nanosoc: export FPGA_COMPONENT_LIB = $(IMP_NANOSOC_DIR) package_nanosoc: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM) package_nanosoc: export FPGA_COMPONENT_TOP = $(COMPONENT_TOP) -package_nanosoc: export FPGA_VENDOR = $(VENDOR) -package_nanosoc: export FPGA_CORE_REV = $(CORE_REV) +package_nanosoc: export FPGA_NANOSOC_VENDOR = $(NANOSOC_VENDOR) +package_nanosoc: export FPGA_NANOSOC_CORE_REV = $(NANOSOC_CORE_REV) # Package NanoSoC IP package_nanosoc: code flist_nanosoc diff --git a/flows/makefile.lint b/flows/makefile.lint new file mode 100644 index 0000000000000000000000000000000000000000..dbfe8d52d41a36c8acc7ad3960a330deb5117534 --- /dev/null +++ b/flows/makefile.lint @@ -0,0 +1,41 @@ +#----------------------------------------------------------------------------- +# NanoSoC Lint Design Makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright (C) 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +# Include Lint Checks +include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks + +# Lint-related Directories +LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/nanosoc +LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/hal +LINT_INFO_SLCOREM0_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/hal +LINT_INFO_SLDMA230_DIR = $(SOCLABS_SLDMA230_TECH_DIR)/hal +LINT_INFO_SOCDEBUG_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal + +# HAL Black Box FIles +HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb +HAL_BLACK_BOX += -design_info $(LINT_INFO_DIR)/corstone101_ip.bb +HAL_BLACK_BOX += -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb +HAL_BLACK_BOX += -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb + +# HAL Waivers +HAL_WAIVE = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive +HAL_WAIVE += -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive +HAL_WAIVE += -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive +HAL_WAIVE += -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive + +# Top-level Module to Lint +LINT_TOP ?= nanosoc_chip_pads + +# Target from Running Cadence Xcellium Lint Tool +lint_xm: bootrom defs_gen + @rm -rf $(LINT_DIR) + @mkdir -p $(LINT_DIR) + @cd $(LINT_DIR); xrun -hal -f $(DESIGN_VC) $(DEFINES_VC) +debug "-timescale 1ns/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK) \ No newline at end of file diff --git a/flows/makefile.regression b/flows/makefile.regression new file mode 100644 index 0000000000000000000000000000000000000000..75d5d90962ce2c185128cde7e3a7892df02bc3dd --- /dev/null +++ b/flows/makefile.regression @@ -0,0 +1,98 @@ +#----------------------------------------------------------------------------- +# NanoSoC Regression Makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright (C) 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +# How many tests to Run In Parallel in a Regression +PARALLEL_TESTS = 4 + +# Regression Simulation Timeout +TIMEOUT = 20m + +# Create a Directory to Run a Regression in +$(eval REGRESSION_NAME =$(shell date +%Y_%m_%d_%H_%M_%S)) +$(eval REGRESSION_DIR = $(SIM_TOP_DIR)/regression_$(REGRESSION_NAME)) + +# Create List of Make Targets +TEST_LIST_MTI = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do if ! grep -Fxq "$$line" $(EXCLUDE_LIST_FLIE); then echo mti_$$line; fi; done) +TEST_LIST_XM = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do if ! grep -Fxq "$$line" $(EXCLUDE_LIST_FLIE); then echo xm_$$line; fi; done) +TEST_LIST_VCS = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do if ! grep -Fxq "$$line" $(EXCLUDE_LIST_FLIE); then echo vcs_$$line; fi; done) + +# Create Make templates for Make Targets +define mti_template +.PHONY: mti_$(1) +mti_$(1): + @echo Starting Test $(1) + @$$(MAKE) regression_test_mti TESTNAME=$(1) >> /dev/null 2>&1 + @if cat $$(REGRESSION)/$(1).log | grep " TEST PASSED "; then echo "$(1): PASSED" >> $$(REGRESSION)/RESULTS.log; elif cat $$(REGRESSION)/$(1).log | grep " TEST SKIPPED "; then echo "$(1): SKIPPED"; else echo "$(1): FAILED" >> $$(REGRESSION)/RESULTS.log; fi > /dev/null + @echo Finished Test $(1) +endef + +define xm_template +.PHONY: xm_$(1) +xm_$(1): + @echo Starting Test $(1) + @$$(MAKE) regression_test_xm TESTNAME=$(1) >> /dev/null 2>&1 + @if cat $$(REGRESSION)/$(1).log | grep " TEST PASSED "; then echo "$(1): PASSED" >> $$(REGRESSION)/RESULTS.log; elif cat $$(REGRESSION)/$(1).log | grep " TEST SKIPPED "; then echo "$(1): SKIPPED"; else echo "$(1): FAILED" >> $$(REGRESSION)/RESULTS.log; fi > /dev/null + @echo Finished Test $(1) +endef + +define vcs_template +.PHONY: vcs_$(1) +vcs_$(1): + @echo Starting Test $(1) + @$$(MAKE) regression_test_vcs TESTNAME=$(1) >> /dev/null 2>&1 + @if cat $$(REGRESSION)/$(1).log | grep -i " TEST PASSED "; then echo "$(1): PASSED" >> $$(REGRESSION)/RESULTS.log; elif cat $$(REGRESSION)/$(1).log | grep -i " TEST SKIPPED "; then echo "$(1): SKIPPED"; else echo "$(1): FAILED" >> $$(REGRESSION)/RESULTS.log; fi > /dev/null + @echo Finished Test $(1) +endef + +# Generate Targets from Templates using Test List +$(foreach TESTNAME,$(TEST_LIST), $(eval $(call mti_template,$(TESTNAME)))) +$(foreach TESTNAME,$(TEST_LIST), $(eval $(call xm_template,$(TESTNAME)))) +$(foreach TESTNAME,$(TEST_LIST), $(eval $(call vcs_template,$(TESTNAME)))) + +# Make Simulate Targets with Timeouts and Error Handling +regression_test_mti: + @timeout $(TIMEOUT) $(MAKE) run_mti TESTNAME=$(TESTNAME) > $(REGRESSION)/$(TESTNAME).log || true + +regression_test_xm: + @timeout $(TIMEOUT) $(MAKE) run_xm TESTNAME=$(TESTNAME) > $(REGRESSION)/$(TESTNAME).log || true + +regression_test_vcs: + @timeout $(TIMEOUT) $(MAKE) run_vxs TESTNAME=$(TESTNAME) > $(REGRESSION)/$(TESTNAME).log || true + +# Target to Display Regression Results on Command Line +regression_results: + @echo -------------------------------------------- + @echo Results: + @echo -------------------------------------------- + @python $(SOCLABS_SOCTOOLS_FLOW_DIR)/tools/regression_result.py $(REGRESSION)/RESULTS.log + +# Regression Simulator Redirect +regression: regression_$(SIMULATOR) + +# Create a Target for Running Simulation Regressions +regression_$(SIMULATOR): compile_$(SIMULATOR) bootrom debugtester + @mkdir -p $(REGRESSION_DIR) + @echo + @echo + @echo + @echo + @echo -------------------------------------------- + @echo Running Regression: $(REGRESSION_NAME) + @echo -------------------------------------------- + @echo Simulator: $(SIMULATOR) + @echo -------------------------------------------- + @$(MAKE) -j$(PARALLEL_TESTS) all_tests_$(SIMULATOR) REGRESSION=$(REGRESSION_DIR) + @$(MAKE) -j1 regression_results REGRESSION=$(REGRESSION_DIR) + +# Create Targets with dependencies for all tests for simulator +all_tests_mti : $(TEST_LIST_MTI) +all_tests_vcs : $(TEST_LIST_VCS) +all_tests_xm : $(TEST_LIST_XM) \ No newline at end of file diff --git a/flows/makefile.simulate b/flows/makefile.simulate new file mode 100644 index 0000000000000000000000000000000000000000..fd8b7966ef80b57a27a8f62482900be9514cbe82 --- /dev/null +++ b/flows/makefile.simulate @@ -0,0 +1,131 @@ +#----------------------------------------------------------------------------- +# NanoSoC Simulation Makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright (C) 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +# ADP command File +DEFAULT_ADP_FILE = $(SIM_DIR)/adp.cmd +ADP_FILE ?= $(DEFAULT_ADP_FILE) +ADP_OPTIONS := -define ADP_FILE=\"$(ADP_FILE)\" + +# MTI options +MTI_VC_OPTIONS = +acc +MTI_VC_OPTIONS += -suppress 2892 +MTI_VC_OPTIONS += -f $(TBENCH_VC) $(ADP_OPTIONS) + +MTI_RUN_OPTIONS = -voptargs=+acc + +# VCS options +VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug +VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc +VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS) + +# XM verilog options +XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC +XM_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS) + +# Create a List of PHONY Targets +.PHONY: compile_$(SIMULATOR) run_$(SIMULATOR) sim_$(SIMULATOR) + +# ------- Simulator redirect ----------- + +compile: compile_$(SIMULATOR) + +run: run_$(SIMULATOR) + +sim: sim_$(SIMULATOR) + +# Preload IMEM in Simulation +compile_mti: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD +compile_vcs: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD +compile_xm: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD + +# ------- VCS ----------- + +# Compile RTL +compile_vcs : gen_defs + vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) $(DEFINES_VC) | tee compile_vcs.log + +# Run simulation in batch mode +run_vcs : code + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + @echo quit > quit.do + ./simv $(VCS_SIM_OPTION) < quit.do | tee logs/run_$(TESTNAME).log ; + +# Run simulation in interactive mode +sim_vcs : code + ./simv -gui +vcs+lic+wait +vcs+flush+log & + +# ------- XM ----------- + +# Compile RTL +compile_xm : bootrom gen_defs + @echo ADP_FILE + @echo $(ADP_OPTIONS) + cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ns/1ps -top $(TB_TOP) | tee compile_xm.log + cd $(SIM_DIR); xmvlog -work worklib -f xmvlog_ver.args | tee -a compile_xm.log + cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log + +# Note : If coverage is required, you can add -coverage all to xmelab + +# Run simulation in batch mode +run_xm : code compile_xm + @if [ ! -d $(SIM_DIR)/logs ] ; then \ + mkdir $(SIM_DIR)/logs; \ + fi + @echo run > $(SIM_DIR)/run.tcl.tmp + @echo exit >> $(SIM_DIR)/run.tcl.tmp + @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl + cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ; + +# Run simulation in interactive mode +sim_xm : code compile_xm + cd $(SIM_DIR); xmsim -gui $(XMSIM_OPTIONS) + +# ------- MTI ----------- + +# Compile RTL +compile_mti : bootrom gen_defs + @echo ADP_FILE + @echo $(ADP_OPTIONS) + @echo $(ADP_FILE) + @echo $(ADP_PATH) + cd $(SIM_DIR) + @if [ -d work ] ; then \ + true ; \ + else \ + vlib work; \ + fi + cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log + +# Run simulation in batch mode +run_mti : code compile_mti + @if [ ! -d $(SIM_DIR)/logs ] ; then \ + mkdir $(SIM_DIR)/logs; \ + fi + @echo "run -all" > $(SIM_DIR)/run.tcl.tmp + @echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp + @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl + cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -c $(TB_TOP) -do run.tcl | tee $(SIM_DIR)/logs/run_$(TESTNAME).log ; + +run_mti_to: + timeout 2s $(MAKE) run_mti >> /dev/null 2>&1 + +run_mti_wrap: + $(MAKE) run_mti_to + +# Run simulation in interactive mode +sim_mti : code compile_mti + cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -gui $(TB_TOP) & + +# Create work directory +lib_mti : + vlib work \ No newline at end of file diff --git a/flows/makefile.software b/flows/makefile.software new file mode 100644 index 0000000000000000000000000000000000000000..cd750bcac640d5518025374b4a34647009319d56 --- /dev/null +++ b/flows/makefile.software @@ -0,0 +1,199 @@ +#----------------------------------------------------------------------------- +# NanoSoC Software Compilation Makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright (C) 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +# Software Directory +NANOSOC_SW_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/software + +# Default to DS-5 tool-chain +TOOL_CHAIN = ds5 + +# Software make options +# - Pass onto the software makefile to define targetted CPU type +# You can append additional make options for testcode here +SW_MAKE_OPTIONS = CPU_PRODUCT=CORTEX_M0 TOOL_CHAIN=$(TOOL_CHAIN) + +# Bootrom Parameters: +# Boot Loader image +BOOTLOADER ?= bootloader +BOOTROM_ADDRW ?= 8 +BOOTROM_HEX ?= $(SOCLABS_NANOSOC_TECH_DIR)/testcodes/bootloader/$(BOOTLOADER).hex +BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom + +# Debug Tester image +DEBUGTESTER = debugtester + +# code target is used by other simulation targets (e.g. run_mti, sim_mti) +# Before simulation, bootrom and testcode need to be compiled. +code : testcode bootrom debugtester + +# Compile bootloader +# Note : The use of ls after compile allows the computing server to sync up +bootrom: + @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\ + $(MAKE) all $(SW_MAKE_OPTIONS) ;\ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(BOOTLOADER).hex ;\ + while [ ! -e $(BOOTLOADER).hex ] ; do \ + echo Wait for hex file ...; \ + ls > /dev/null; \ + sleep 5; \ + done; \ + if [ ! -e $(BOOTLOADER).hex ] ; then \ + echo Problem reading hex file ;\ + exit 1; \ + fi ;\ + mkdir -p $(BOOTROM_BUILD_DIR)/verilog/ ;\ + mkdir -p $(BOOTROM_BUILD_DIR)/bintxt/ ;\ + python3 bootrom_gen.py -a $(BOOTROM_ADDRW) -i $(BOOTLOADER).hex -v $(BOOTROM_BUILD_DIR)/verilog/bootrom.v -b $(BOOTROM_BUILD_DIR)/bintxt/bootrom.bintxt ) + mkdir -p $(SIM_DIR)/bootloader + cp $(BOOTROM_HEX) $(SIM_DIR)/bootloader/$(BOOTLOADER).hex + +# Compile test code +# Note : The use of ls after compile allows the computing server to sync up +testcode: +ifeq ($(TESTNAME),) + $(error Please specify TESTNAME on the make command line) +endif + @(if [ -d "$(TESTCODES_DIR)/$(TESTNAME)" ] ; then \ + cd $(TESTCODES_DIR)/$(TESTNAME) ;\ + $(MAKE) all $(SW_MAKE_OPTIONS) ; \ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(TESTNAME).hex ;\ + if [ -e $(TESTNAME).hex ] ; then \ + mkdir -p $(SIM_DIR) ; \ + cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ + cp adp.cmd $(SIM_DIR)/adp.cmd ; \ + else \ + while [ ! -e $(TESTNAME).hex ] ; do \ + echo Wait for $(TESTNAME).hex file ...; \ + ls > /dev/null ; \ + sleep 5 ; \ + done; \ + if [ -e $(TESTNAME).hex ] ; then \ + mkdir -p $(SIM_DIR) ; \ + cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ + cp $(TESTNAME).hex ../../image.hex ; \ + else \ + echo Problem reading hex file ;\ + exit 1; \ + fi ;\ + fi ;\ + cd $(SIM_DIR) ;\ + elif [ -d "$(PROJ_SW_DIR)/$(TESTNAME)" ] ; then \ + cd $(PROJ_SW_DIR)/$(TESTNAME) ;\ + $(MAKE) all $(SW_MAKE_OPTIONS) ; \ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(TESTNAME).hex ;\ + if [ -e $(TESTNAME).hex ] ; then \ + mkdir -p $(SIM_DIR) ; \ + cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ + cp adp.cmd $(SIM_DIR)/adp.cmd ; \ + else \ + while [ ! -e $(TESTNAME).hex ] ; do \ + echo Wait for $(TESTNAME).hex file ...; \ + ls > /dev/null ; \ + sleep 5 ; \ + done; \ + if [ -e $(TESTNAME).hex ] ; then \ + mkdir -p $(SIM_DIR) ; \ + cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ + else \ + echo Problem reading hex file ;\ + exit 1; \ + fi ;\ + fi ;\ + cd $(SIM_DIR) ;\ + else \ + echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\ + exit 1 ;\ + fi ;\ + ) + + +# Compile debugtester +# Note : The use of ls after compile allows the computing server to sync up +debugtester: + @(cd $(NANOSOC_SW_DIR)/debug_tester ;\ + $(MAKE) all $(SW_MAKE_OPTIONS) ;\ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(DEBUGTESTER)_le.hex ;\ + if [ -e $(DEBUGTESTER)_le.hex ] ; then \ + cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\ + else \ + while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \ + echo Wait for hex file ...; \ + ls > /dev/null ; \ + sleep 5 ; \ + done; \ + if [ -e $(DEBUGTESTER)_le.hex ] ; then \ + mkdir -p $(SIM_DIR) ;\ + cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\ + fi ;\ + fi ;\ + echo Copy $(DEBUGTESTER)_be.hex ;\ + if [ -e $(DEBUGTESTER)_be.hex ] ; then \ + mkdir -p $(SIM_DIR) ;\ + cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\ + else \ + while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \ + echo Wait for hex file ...;\ + ls > /dev/null ;\ + sleep 5 ; \ + done; \ + if [ -e $(DEBUGTESTER)_be.hex ] ; then \ + cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\ + fi ;\ + fi ;\ + if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \ + echo Problem reading hex file ;\ + exit 1 ;\ + fi ;\ + cd $(SIM_DIR) ) + +# Compile all software including boot ROM +compile_all_code: bootrom debugtester + for thistest in $(TEST_LIST) ; do \ + echo Compiling $$thistest ; \ + echo Removing old image.hex ;\ + rm -f image.hex ;\ + $(MAKE) testcode TESTNAME=$$thistest;\ + if [ -e $(SIM_DIR)/$$thistest/image.hex ] ; then \ + echo OK - image.hex created for test $$thistest ;\ + else \ + echo ERROR - image.hex NOT created for test $$thistest ;\ + exit 1; \ + fi ; \ + done + +# Remove all software compilation results +clean_all_code: + @(cd $(NANOSOC_SW_DIR)/debug_tester ; $(MAKE) clean; ) + @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; $(MAKE) clean; ) + @for thistest in $(TEST_LIST) ; do \ + echo Cleaning $$thistest ... ; \ + if [ -e $(TESTCODES_DIR)/$$thistest ]; then \ + cd $(TESTCODES_DIR)/$$thistest ; \ + $(MAKE) clean; \ + elif [ -e $(PROJ_SW_DIR)/$$thistest ]; then \ + cd $(PROJ_SW_DIR)/$$thistest ; \ + $(MAKE) clean; \ + fi \ + done + @rm -rf $(BOOTROM_BUILD_DIR) + +# Remove only bootloader and default selected test +clean_code: + @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; $(MAKE) clean; cd $(SIM_DIR); ) + @(cd $(TESTCODES_DIR)/$(TESTNAME) ; $(MAKE) clean; cd $(SIM_DIR); ) \ No newline at end of file diff --git a/makefile b/makefile index 5a0b9f4a614fce33f70fe5e1f246c79033829149..d36d6ec2a671289711f413bb29d3813a90f9a664 100644 --- a/makefile +++ b/makefile @@ -1,5 +1,6 @@ #----------------------------------------------------------------------------- -# NanoSoC Simulation Makefile +# NanoSoC Top-Level Makefile +# - Includes other Makefiles in flow directory # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. # # Contributors @@ -9,42 +10,25 @@ # Copyright (C) 2021-3, SoC Labs (www.soclabs.org) #----------------------------------------------------------------------------- -#----------------------------------------------------------------------------- -# The confidential and proprietary information contained in this file may -# only be used by a person authorised under and to the extent permitted -# by a subsisting licensing agreement from Arm Limited or its affiliates. -# -# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates. -# ALL RIGHTS RESERVED -# -# This entire notice must be reproduced on all copies of this file -# and copies of this file may only be made by a person if such person is -# permitted to do so under the terms of a subsisting license agreement -# from Arm Limited or its affiliates. -# -# SVN Information -# -# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -# -# Revision : $Revision: 371321 $ -# -# Release Information : Cortex-M System Design Kit-r1p1-00rel0 -#----------------------------------------------------------------------------- -# -# Cortex-M0/Cortex-M0+ System Design Kit simulation make file -# -#----------------------------------------------------------------------------- -# -# Configurations +#------------------------------------- +# - Commonly Overloaded Variables +#------------------------------------- +# Name of test directory - Default Test is Hello World +TESTNAME ?= hello + +# Simulator type (mti/vcs/xm) +SIMULATOR = mti -# Include Lint Checks -include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks +# Is an accelerator subsystem present in the design? +ACCELERATOR ?= yes -# Directory of Testcodes -NANOSOC_SYSTEM_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/system -NANOSOC_SW_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/software +# Is the Arm QuickStart being used? +QUICKSTART ?= no -VERILOG_DIR := $(NANOSOC_SYSTEM_DIR)/verilog +#------------------------------------- +# - Directory Setups +#------------------------------------- +# Directory of Testcodes TESTCODES_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/testcodes # Project System Directory @@ -52,60 +36,33 @@ FPGA_IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga PROJ_SYS_DIR := $(SOCLABS_PROJECT_DIR)/system PROJ_SW_DIR ?= $(PROJ_SYS_DIR)/testcodes -# Name of test directory (e.g. hello, dhry) -# TESTNAME must be specified on the make command line -TESTNAME = +# Directory to put simulation files +SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim +SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME) +#------------------------------------- +# - Test List Variables +#------------------------------------- # List of all tests (this is used when running 'make all/clean') -TEST_LIST_FILE ?= $(TESTCODES_DIR)/software_list.txt -TEST_LIST_FILE += $(PROJ_SW_DIR)/software_list.txt -TEST_LIST = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do echo $$line; done) +TEST_LIST_FILE ?= $(TESTCODES_DIR)/software_list.txt +TEST_LIST_FILE += $(PROJ_SW_DIR)/software_list.txt +TEST_LIST = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do echo $$line; done) # List of Tests to Exclude from Regression EXCLUDE_LIST_FLIE = $(PROJ_SW_DIR)/regression_exclude.txt -# Default to DS-5 tool-chain -TOOL_CHAIN = ds5 - -# Select System Components (Set here but not currently used) -CPU_PRODUCT ?= CORTEX_M0 -DMA_PRODUCT ?= DMA_230 - - -# Directory to put simulation files -SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim - -SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME) - -# ADP command File -# Defaultly set to demo adp command file -DEFAULT_ADP_FILE = $(SIM_DIR)/adp.cmd -ADP_FILE ?= $(DEFAULT_ADP_FILE) -ADP_OPTIONS := -define ADP_FILE=\"$(ADP_FILE)\" - -# Bootrom Parameters: -# Boot Loader image -BOOTLOADER ?= bootloader -BOOTROM_ADDRW ?= 8 -BOOTROM_HEX ?= $(SOCLABS_NANOSOC_TECH_DIR)/testcodes/bootloader/$(BOOTLOADER).hex -BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom - -# Simulator Defines -DEFINES_VC += $(MEM_INIT) +define+CORTEX_M0 +define+USE_TARMAC - -# Is an accelerator subsystem present in the design? -ACCELERATOR ?= yes +#------------------------------------- +# - Verilog Defines and Filelists +#------------------------------------- +# Simulator/Lint Defines +DEFINES_VC += +define+CORTEX_M0 +define+USE_TARMAC +# Set Variables depending on whether Accelerator is in System ifeq ($(ACCELERATOR),yes) DEFINES_VC += +define+ACCELERATOR_SUBSYSTEM NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM endif -NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD - -# Is the Arm QuickStart being used? -QUICKSTART ?= no - # System Design Filelist ifeq ($(QUICKSTART),yes) DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist @@ -122,599 +79,40 @@ else NANOSOC_DEFINES += DMAC_0_PL230 endif +# Make variables visible to target shells export ARM_CORTEX_M0_DIR export ARM_CORSTONE_101_DIR -# Simulator type (mti/vcs/xm) -SIMULATOR = mti - - - -LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/nanosoc -LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/hal -LINT_INFO_SLCOREM0_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/hal -LINT_INFO_SLDMA230_DIR = $(SOCLABS_SLDMA230_TECH_DIR)/hal -LINT_INFO_SOCDEBUG_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal - -LINT_TOP = nanosoc_chip_pads - -# MTI option -MTI_VC_OPTIONS = +acc -MTI_VC_OPTIONS += -suppress 2892 -MTI_VC_OPTIONS += -f $(TBENCH_VC) $(ADP_OPTIONS) - -MTI_RUN_OPTIONS = -voptargs=+acc - -# VCS option -VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug -VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc -VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS) - -# XM verilog option -XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC -XM_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS) - -HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb -HAL_BLACK_BOX += -design_info $(LINT_INFO_DIR)/corstone101_ip.bb -HAL_BLACK_BOX += -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb -HAL_BLACK_BOX += -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb - -HAL_WAIVE = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive -HAL_WAIVE += -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive -HAL_WAIVE += -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive -HAL_WAIVE += -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive - # Location of Defines File -DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/ -DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v - -# Debug Tester image -DEBUGTESTER = debugtester - -# Software make options -# - Pass onto the software makefile to define targetted CPU type -# You can append additional make options for testcode here -SW_MAKE_OPTIONS = CPU_PRODUCT=$(CPU_PRODUCT) TOOL_CHAIN=$(TOOL_CHAIN) - -# How many tests to Run In Parallel in a Regression -PARALLEL_TESTS = 4 +DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/ +DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v -# Regression Simulation Timeout -TIMEOUT = 5m +#------------------------------------------ +# - Include Makefiles for Specific Flows +#------------------------------------------ +# Include Software Compilation Makefile +include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.software -# Name of generated filelist by python script -TCL_FLIST_DIR := $(FPGA_IMP_DIR)/flist -TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl +# Include Linting Makefile +include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.lint -# FPGA_Flow -tcl_flist: - @echo building TCL flist - @mkdir -p $(TCL_FLIST_DIR) - @(cd $(TCL_FLIST_DIR); \ - $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) ;) +# Include Simulation Makefile +include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.simulate -# Create a Directory to Run a Regression in -$(eval REGRESSION_NAME =$(shell date +%Y_%m_%d_%H_%M_%S)) -$(eval REGRESSION_DIR = $(SIM_TOP_DIR)/regression_$(REGRESSION_NAME)) +# Include Regression Simulation Makefile +include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.regression -# Create List of Make Targets -TEST_LIST_MTI = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do if ! grep -Fxq "$$line" $(EXCLUDE_LIST_FLIE); then echo mti_$$line; fi; done) -TEST_LIST_XM = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do if ! grep -Fxq "$$line" $(EXCLUDE_LIST_FLIE); then echo xm_$$line; fi; done) -TEST_LIST_VCS = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do if ! grep -Fxq "$$line" $(EXCLUDE_LIST_FLIE); then echo vcs_$$line; fi; done) +# Include FPGA Makefile +include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.fpga -# Create templates for Make Targets -define mti_template -.PHONY: mti_$(1) -mti_$(1): - @echo Starting Test $(1) - @$$(MAKE) regression_test_mti TESTNAME=$(1) >> /dev/null 2>&1 - @if cat $$(REGRESSION)/$(1).log | grep " TEST PASSED "; then echo "$(1): PASSED" >> $$(REGRESSION)/RESULTS.log; elif cat $$(REGRESSION)/$(1).log | grep " TEST SKIPPED "; then echo "$(1): SKIPPED"; else echo "$(1): FAILED" >> $$(REGRESSION)/RESULTS.log; fi > /dev/null - @echo Finished Test $(1) -endef - -define xm_template -.PHONY: xm_$(1) -xm_$(1): - @echo Starting Test $(1) - @$$(MAKE) regression_test_xm TESTNAME=$(1) >> /dev/null 2>&1 - @if cat $$(REGRESSION)/$(1).log | grep " TEST PASSED "; then echo "$(1): PASSED" >> $$(REGRESSION)/RESULTS.log; elif cat $$(REGRESSION)/$(1).log | grep " TEST SKIPPED "; then echo "$(1): SKIPPED"; else echo "$(1): FAILED" >> $$(REGRESSION)/RESULTS.log; fi > /dev/null - @echo Finished Test $(1) -endef - -define vcs_template -.PHONY: vcs_$(1) -vcs_$(1): - @echo Starting Test $(1) - @$$(MAKE) regression_test_vcs TESTNAME=$(1) >> /dev/null 2>&1 - @if cat $$(REGRESSION)/$(1).log | grep -i " TEST PASSED "; then echo "$(1): PASSED" >> $$(REGRESSION)/RESULTS.log; elif cat $$(REGRESSION)/$(1).log | grep -i " TEST SKIPPED "; then echo "$(1): SKIPPED"; else echo "$(1): FAILED" >> $$(REGRESSION)/RESULTS.log; fi > /dev/null - @echo Finished Test $(1) -endef - -# Generate Targets from Templates using Test List -$(foreach TESTNAME,$(TEST_LIST), $(eval $(call mti_template,$(TESTNAME)))) -$(foreach TESTNAME,$(TEST_LIST), $(eval $(call xm_template,$(TESTNAME)))) -$(foreach TESTNAME,$(TEST_LIST), $(eval $(call vcs_template,$(TESTNAME)))) - -# Make Simulate Targets with timeouts -regression_test_mti: - @timeout $(TIMEOUT) $(MAKE) run_mti TESTNAME=$(TESTNAME) > $(REGRESSION)/$(TESTNAME).log || true - -regression_test_xm: - @timeout $(TIMEOUT) $(MAKE) run_xm TESTNAME=$(TESTNAME) > $(REGRESSION)/$(TESTNAME).log || true - -regression_test_vcs: - @timeout $(TIMEOUT) $(MAKE) run_vxs TESTNAME=$(TESTNAME) > $(REGRESSION)/$(TESTNAME).log || true - -# Create a List of PHONY Targets -.PHONY: run_$(SIMULATOR) sim_$(SIMULATOR) all_$(SIMULATOR) test_$(SIMULATOR) - -# ------- Simulator redirect ----------- - -compile : compile_$(SIMULATOR) - - -run : run_$(SIMULATOR) - - -sim : sim_$(SIMULATOR) - - -all : all_$(SIMULATOR) - -# ------- VCS ----------- - -# Compile RTL -compile_vcs : defs_gen - vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) $(DEFINES_VC) | tee compile_vcs.log - - -# Run simulation in batch mode -run_vcs : code - @if [ ! -d logs ] ; then \ - mkdir logs; \ - fi - @echo quit > quit.do - ./simv $(VCS_SIM_OPTION) < quit.do | tee logs/run_$(TESTNAME).log ; - -# Run simulation in interactive mode -sim_vcs : code - ./simv -gui +vcs+lic+wait +vcs+flush+log & - -# ------- XM ----------- - - -# Compile RTL -compile_xm : bootrom defs_gen - @echo ADP_FILE - @echo $(ADP_OPTIONS) - cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ns/1ps -top $(TB_TOP) | tee compile_xm.log - cd $(SIM_DIR); xmvlog -work worklib -f xmvlog_ver.args | tee -a compile_xm.log - cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log - -lint_xm: bootrom defs_gen - @rm -rf $(LINT_DIR) - @mkdir -p $(LINT_DIR) - cd $(LINT_DIR); xrun -hal -f $(DESIGN_VC) $(DEFINES_VC) +debug "-timescale 1ns/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK) - -# Note : If coverage is required, you can add -coverage all to xmelab - -# Run simulation in batch mode -run_xm : code compile_xm - @if [ ! -d $(SIM_DIR)/logs ] ; then \ - mkdir $(SIM_DIR)/logs; \ - fi - @echo run > $(SIM_DIR)/run.tcl.tmp - @echo exit >> $(SIM_DIR)/run.tcl.tmp - @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl - cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ; - # @$(MAKE) verify - -# Run simulation in interactive mode -sim_xm : code compile_xm - cd $(SIM_DIR); xmsim -gui $(XMSIM_OPTIONS) - # @$(MAKE) verify - -# ------- MTI ----------- - -# Compile RTL -compile_mti : bootrom defs_gen - @echo ADP_FILE - @echo $(ADP_OPTIONS) - @echo $(ADP_FILE) - @echo $(ADP_PATH) - cd $(SIM_DIR) - @if [ -d work ] ; then \ - true ; \ - else \ - vlib work; \ - fi - cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log - -# Run simulation in batch mode -run_mti : code compile_mti - @if [ ! -d $(SIM_DIR)/logs ] ; then \ - mkdir $(SIM_DIR)/logs; \ - fi - @echo "run -all" > $(SIM_DIR)/run.tcl.tmp - @echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp - @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl - cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -c $(TB_TOP) -do run.tcl | tee $(SIM_DIR)/logs/run_$(TESTNAME).log ; - -run_mti_to: - timeout 2s $(MAKE) run_mti >> /dev/null 2>&1 - -run_mti_wrap: - $(MAKE) run_mti_to -test_mti: - @echo $(TESTNAME) - -# Run simulation in interactive mode -sim_mti : code compile_mti - cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -gui $(TB_TOP) & - -# Create work directory -lib_mti : - vlib work - -# Create Targets with dependencies for all tests for simulator -all_mti : $(TEST_LIST_MTI) -all_vcs : $(TEST_LIST_VCS) -all_xm : $(TEST_LIST_XM) - -regression_results: - @echo -------------------------------------------- - @echo Results: - @echo -------------------------------------------- - @python $(SOCLABS_SOCTOOLS_FLOW_DIR)/tools/regression_result.py $(REGRESSION)/RESULTS.log - -# Create a Target for Running Simulation Regressions -regression_$(SIMULATOR): compile_$(SIMULATOR) bootrom debugtester - @mkdir -p $(REGRESSION_DIR) - @echo - @echo - @echo - @echo - @echo -------------------------------------------- - @echo Running Regression: $(REGRESSION_NAME) - @echo -------------------------------------------- - @echo Simulator: $(SIMULATOR) - @echo -------------------------------------------- - @$(MAKE) -j$(PARALLEL_TESTS) all_$(SIMULATOR) REGRESSION=$(REGRESSION_DIR) - @$(MAKE) -j1 regression_results REGRESSION=$(REGRESSION_DIR) - -defs_gen: +#------------------------------------------ +# - Common Targets Across Flows +#------------------------------------------ +# Generate Defines File for NanoSoC +gen_defs: @mkdir -p $(DEFINES_DIR) @$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE) -# ------- Software ----------- - -# code target is used by other simulation targets (e.g. run_mti, sim_mti) -# Before simulation, bootrom and testcode need to be compiled. -code : testcode bootrom debugtester - -# Compile bootloader -# Note : The use of ls after compile allows the computing server to sync up -bootrom: - @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\ - $(MAKE) all $(SW_MAKE_OPTIONS) ;\ - echo Compile done ;\ - ls > /dev/null ;\ - echo Copy $(BOOTLOADER).hex ;\ - while [ ! -e $(BOOTLOADER).hex ] ; do \ - echo Wait for hex file ...; \ - ls > /dev/null; \ - sleep 5; \ - done; \ - if [ ! -e $(BOOTLOADER).hex ] ; then \ - echo Problem reading hex file ;\ - exit 1; \ - fi ;\ - mkdir -p $(BOOTROM_BUILD_DIR)/verilog/ ;\ - mkdir -p $(BOOTROM_BUILD_DIR)/bintxt/ ;\ - python3 bootrom_gen.py -a $(BOOTROM_ADDRW) -i $(BOOTLOADER).hex -v $(BOOTROM_BUILD_DIR)/verilog/bootrom.v -b $(BOOTROM_BUILD_DIR)/bintxt/bootrom.bintxt ) - mkdir -p $(SIM_DIR)/bootloader - cp $(BOOTROM_HEX) $(SIM_DIR)/bootloader/$(BOOTLOADER).hex - -# Compile test code -# Note : The use of ls after compile allows the computing server to sync up -testcode: -ifeq ($(TESTNAME),) - $(error Please specify TESTNAME on the make command line) -endif - @(if [ -d "$(TESTCODES_DIR)/$(TESTNAME)" ] ; then \ - cd $(TESTCODES_DIR)/$(TESTNAME) ;\ - $(MAKE) all $(SW_MAKE_OPTIONS) ; \ - echo Compile done ;\ - ls > /dev/null ;\ - echo Copy $(TESTNAME).hex ;\ - if [ -e $(TESTNAME).hex ] ; then \ - mkdir -p $(SIM_DIR) ; \ - cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ - cp adp.cmd $(SIM_DIR)/adp.cmd ; \ - else \ - while [ ! -e $(TESTNAME).hex ] ; do \ - echo Wait for $(TESTNAME).hex file ...; \ - ls > /dev/null ; \ - sleep 5 ; \ - done; \ - if [ -e $(TESTNAME).hex ] ; then \ - mkdir -p $(SIM_DIR) ; \ - cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ - cp $(TESTNAME).hex ../../image.hex ; \ - else \ - echo Problem reading hex file ;\ - exit 1; \ - fi ;\ - fi ;\ - cd $(SIM_DIR) ;\ - elif [ -d "$(PROJ_SW_DIR)/$(TESTNAME)" ] ; then \ - cd $(PROJ_SW_DIR)/$(TESTNAME) ;\ - $(MAKE) all $(SW_MAKE_OPTIONS) ; \ - echo Compile done ;\ - ls > /dev/null ;\ - echo Copy $(TESTNAME).hex ;\ - if [ -e $(TESTNAME).hex ] ; then \ - mkdir -p $(SIM_DIR) ; \ - cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ - cp adp.cmd $(SIM_DIR)/adp.cmd ; \ - else \ - while [ ! -e $(TESTNAME).hex ] ; do \ - echo Wait for $(TESTNAME).hex file ...; \ - ls > /dev/null ; \ - sleep 5 ; \ - done; \ - if [ -e $(TESTNAME).hex ] ; then \ - mkdir -p $(SIM_DIR) ; \ - cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \ - else \ - echo Problem reading hex file ;\ - exit 1; \ - fi ;\ - fi ;\ - cd $(SIM_DIR) ;\ - else \ - echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\ - exit 1 ;\ - fi ;\ - ) - - -# Compile debugtester -# Note : The use of ls after compile allows the computing server to sync up -debugtester: - @(cd $(NANOSOC_SW_DIR)/debug_tester ;\ - $(MAKE) all $(SW_MAKE_OPTIONS) ;\ - echo Compile done ;\ - ls > /dev/null ;\ - echo Copy $(DEBUGTESTER)_le.hex ;\ - if [ -e $(DEBUGTESTER)_le.hex ] ; then \ - cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\ - else \ - while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \ - echo Wait for hex file ...; \ - ls > /dev/null ; \ - sleep 5 ; \ - done; \ - if [ -e $(DEBUGTESTER)_le.hex ] ; then \ - mkdir -p $(SIM_DIR) ;\ - cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\ - fi ;\ - fi ;\ - echo Copy $(DEBUGTESTER)_be.hex ;\ - if [ -e $(DEBUGTESTER)_be.hex ] ; then \ - mkdir -p $(SIM_DIR) ;\ - cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\ - else \ - while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \ - echo Wait for hex file ...;\ - ls > /dev/null ;\ - sleep 5 ; \ - done; \ - if [ -e $(DEBUGTESTER)_be.hex ] ; then \ - cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\ - fi ;\ - fi ;\ - if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \ - echo Problem reading hex file ;\ - exit 1 ;\ - fi ;\ - cd $(SIM_DIR) ) - -# Compile all software including boot ROM -compile_all_code: bootrom debugtester - for thistest in $(TEST_LIST) ; do \ - echo Compiling $$thistest ; \ - echo Removing old image.hex ;\ - rm -f image.hex ;\ - $(MAKE) testcode TESTNAME=$$thistest;\ - if [ -e $(SIM_DIR)/$$thistest/image.hex ] ; then \ - echo OK - image.hex created for test $$thistest ;\ - else \ - echo ERROR - image.hex NOT created for test $$thistest ;\ - exit 1; \ - fi ; \ - done - -# Remove all software compilation results -clean_all_code: - @(cd $(NANOSOC_SW_DIR)/debug_tester ; $(MAKE) clean; ) - @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; $(MAKE) clean; ) - @for thistest in $(TEST_LIST) ; do \ - echo Cleaning $$thistest ... ; \ - if [ -e $(TESTCODES_DIR)/$$thistest ]; then \ - cd $(TESTCODES_DIR)/$$thistest ; \ - $(MAKE) clean; \ - elif [ -e $(PROJ_SW_DIR)/$$thistest ]; then \ - cd $(PROJ_SW_DIR)/$$thistest ; \ - $(MAKE) clean; \ - fi \ - done - @rm -rf $(BOOTROM_BUILD_DIR) - -# Remove only bootloader and default selected test -clean_code: - @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; $(MAKE) clean; cd $(SIM_DIR); ) - @(cd $(TESTCODES_DIR)/$(TESTNAME) ; $(MAKE) clean; cd $(SIM_DIR); ) - -# ----- verification ------ -verify: - @python3 $(SOCLABS_SOCTOOLS_FLOW_DIR)/tools/adp_verify.py - -# ------- FPGA ------------ - -# Call Make recipies in fpga directory -build_fpga: - $(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR)/fpga build_fpga $@ - -clean_fpga: - $(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR)/fpga clean_fpga $@ - -clean_fpga_all: - $(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR)/fpga clean_fpga_all $@ - -# ------- clean ----------- - # Remove RTL compile files, log files, software compile files clean : clean_all_code - @rm -rf $(SIM_DIR) - @if [ -d work ] ; then \ - rm -rf work ; \ - fi - @if [ -e tarmac0.log ] ; then \ - rm tarmac0.log ; \ - fi - @if [ -e tarmac1.log ] ; then \ - rm tarmac1.log ; \ - fi - @if [ -e tarmac0track.log ] ; then \ - rm tarmac0track.log ; \ - fi - @if [ -e ft1248_ip.log ] ; then \ - rm ft1248_ip.log ; \ - fi - @if [ -e ft1248_op.log ] ; then \ - rm ft1248_op.log ; \ - fi - @if [ -e uart.log ] ; then \ - rm uart.log ; \ - fi - @if [ -e uart0.log ] ; then \ - rm uart0.log ; \ - fi - @if [ -e uart1.log ] ; then \ - rm uart1.log ; \ - fi - @if [ -e uart2.log ] ; then \ - rm uart2.log ; \ - fi - @if [ -e uart3.log ] ; then \ - rm uart3.log ; \ - fi - @if [ -e vsim.wlf ] ; then \ - rm vsim.wlf ; \ - fi - @if [ -e image.hex ] ; then \ - rm image.hex ; \ - fi - @if [ -e date_file ] ; then \ - rm date_file ; \ - fi - @if [ -e bootrom.v ] ; then \ - rm bootrom.v ; \ - fi - @if [ -e bootrom.bintxt ] ; then \ - rm bootrom.bintxt ; \ - fi - @if [ -e bootloader.hex ] ; then \ - rm bootloader.hex ; \ - fi - @if [ -e debugtester_le.hex ] ; then \ - rm debugtester_le.hex ; \ - fi - @if [ -e debugtester_be.hex ] ; then \ - rm debugtester_be.hex ; \ - fi - @if [ -e compile_mti.log ] ; then \ - rm compile_mti.log ; \ - fi - @if [ -e vish_stacktrace.vstf ] ; then \ - rm vish_stacktrace.vstf ; \ - fi - @if [ -e compile_vcs.log ] ; then \ - rm compile_vcs.log ; \ - fi - @if [ -e compile_xm.log ] ; then \ - rm compile_xm.log ; \ - fi - @if [ -e transcript ] ; then \ - rm transcript ; \ - fi - @if [ -e simv ] ; then \ - rm simv ; \ - fi - @if [ -d csrc ] ; then \ - rm -rf csrc ; \ - fi - @if [ -d simv.daidir ] ; then \ - rm -rf simv.daidir ; \ - fi - @if [ -e inter.vpd ] ; then \ - rm -rf inter.vpd ; \ - fi - @if [ -e quit.do ] ; then \ - rm -rf quit.do ; \ - fi - @if [ -e ucli.key ] ; then \ - rm -rf ucli.key ; \ - fi - @if [ -d DVEfiles ] ; then \ - rm -rf DVEfiles ; \ - fi - @if [ -d INCA_libs ] ; then \ - rm -rf INCA_libs ; \ - fi - @if [ -d cov_work ] ; then \ - rm -rf cov_work ; \ - fi - @if [ -e hdl.var ] ; then \ - rm -rf hdl.var ; \ - fi - @if [ -e xmelab.args ] ; then \ - rm -rf xmelab.args ; \ - fi - @if [ -e xmvlog.args ] ; then \ - rm -rf xmvlog.args ; \ - fi - @if [ -e xmsim.args ] ; then \ - rm -rf xmsim.args ; \ - fi - @if [ -e xmprep.log ] ; then \ - rm -rf xmprep.log ; \ - fi - @if [ -e xmelab.log ] ; then \ - rm -rf xmelab.log ; \ - fi - @if [ -e xmvlog.log ] ; then \ - rm -rf xmvlog.log ; \ - fi - @if [ -e xmsim.log ] ; then \ - rm -rf xmsim.log ; \ - fi - @if [ -e run.tcl ] ; then \ - rm -rf run.tcl ; \ - fi - @if [ -e RUN_XM ] ; then \ - rm -rf RUN_XM ; \ - fi - @if [ -e xmsim.key ] ; then \ - rm -rf xmsim.key ; \ - fi - @if [ -e cds.lib ] ; then \ - rm -rf cds.lib ; \ - fi - @if [ -e logs ] ; then \ - rm -rf logs ; \ - fi - @if [ -e ../v2html_doc ] ; then \ - rm -rf ../v2html_doc ; \ - fi + @rm -rf $(SIM_DIR) \ No newline at end of file diff --git a/nanosoc/slcorem0_tech b/nanosoc/slcorem0_tech index 2e3cb7902130b7bd3979f6cfdb97aa04d0a610a3..27142533eecdb9d8c337b778a479210ec6bcc661 160000 --- a/nanosoc/slcorem0_tech +++ b/nanosoc/slcorem0_tech @@ -1 +1 @@ -Subproject commit 2e3cb7902130b7bd3979f6cfdb97aa04d0a610a3 +Subproject commit 27142533eecdb9d8c337b778a479210ec6bcc661 diff --git a/nanosoc/sldma230_tech b/nanosoc/sldma230_tech index dad4b9fa4c4e22062fcebb8b433569643797e98c..431c5a7933bcbde8da0d584f850384e6e8c3ed3b 160000 --- a/nanosoc/sldma230_tech +++ b/nanosoc/sldma230_tech @@ -1 +1 @@ -Subproject commit dad4b9fa4c4e22062fcebb8b433569643797e98c +Subproject commit 431c5a7933bcbde8da0d584f850384e6e8c3ed3b diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech index 33796d25907f46d8fd3f7831ebd05673e944b8d4..2e9197ffb6721c1b5bbd52f92d62a3bbed37dacb 160000 --- a/nanosoc/socdebug_tech +++ b/nanosoc/socdebug_tech @@ -1 +1 @@ -Subproject commit 33796d25907f46d8fd3f7831ebd05673e944b8d4 +Subproject commit 2e9197ffb6721c1b5bbd52f92d62a3bbed37dacb