From 60a1204a2788d2aa2334e5dad0de195d46d1e310 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Mon, 19 Feb 2024 12:50:54 +0000
Subject: [PATCH] Update ASIC flow
---
.../Cadence/scripts/design_import_noDFT.tcl | 7 +-
ASIC/44pin/Cadence/scripts/filler.tcl | 13 ++++
ASIC/44pin/Cadence/scripts/genus.tcl | 2 +-
ASIC/44pin/Cadence/scripts/genus_nodft.tcl | 3 +-
ASIC/44pin/Cadence/scripts/nanosoc.mmmc | 2 +-
ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io | 2 +-
ASIC/44pin/Cadence/scripts/place.tcl | 4 +-
ASIC/44pin/Cadence/scripts/pnr_flow.tcl | 35 +++++-----
ASIC/44pin/Cadence/scripts/power_plan.tcl | 1 +
ASIC/44pin/Cadence/scripts/tieoff_exclude | 5 ++
ASIC/44pin/Mentor/LVS | 8 +++
ASIC/constraints.sdc | 65 ++++++++++---------
.../tsmc65lp/nanosoc_chip_pads_44pin.v | 40 ++++++++----
flows/makefile.asic | 10 ++-
.../pads/glib/verilog/nanosoc_chip_pads.v | 17 ++++-
verif/tb/verilog/nanosoc_tb.v | 2 +
16 files changed, 144 insertions(+), 72 deletions(-)
create mode 100644 ASIC/44pin/Cadence/scripts/filler.tcl
create mode 100644 ASIC/44pin/Mentor/LVS
diff --git a/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl b/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
index 2aaa9d6..2a7ede1 100644
--- a/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
+++ b/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
@@ -14,10 +14,11 @@ read_mmmc nanosoc.mmmc
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
-set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
+#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
-set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
-set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/iolib/tpbn65v_200b_FE/TSMCHOME/digital/Back_End/lef/tpbn65v_200b/cup/9m/9M_6X1Z1U/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
diff --git a/ASIC/44pin/Cadence/scripts/filler.tcl b/ASIC/44pin/Cadence/scripts/filler.tcl
new file mode 100644
index 0000000..3219c08
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/filler.tcl
@@ -0,0 +1,13 @@
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -fill_gap -merge true -power_domain ACCEL -check_drc true
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -fill_gap -merge true -power_domain TOP -check_drc true
+
+add_filler_gaps 0.8 -effort high
+
+
+
+
+
+check_filler > check_filler.log
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true -fix_drc
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true -fix_drc
+
diff --git a/ASIC/44pin/Cadence/scripts/genus.tcl b/ASIC/44pin/Cadence/scripts/genus.tcl
index 964a721..3ff6e5f 100644
--- a/ASIC/44pin/Cadence/scripts/genus.tcl
+++ b/ASIC/44pin/Cadence/scripts/genus.tcl
@@ -54,7 +54,7 @@ set_db hinst:nanosoc_chip_pads/u_nanosoc_chip_cfg .dft_dont_scan true
define_test_signal -name TEST -active high -shared_input -hookup_pin u_nanosoc_chip/test_i -function test_mode -index 0 TEST
define_test_signal -name CLK -active high -hookup_pin u_nanosoc_chip/clk_i -function test_clock -index 0 CLK
define_test_signal -name NRST -active low -hookup_pin u_nanosoc_chip/nrst_i -function async_set_reset -index 0 NRST
-define_test_signal -name SWDCK -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SWDCK
+define_test_signal -name SE -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SE
define_scan_chain -name chain_ACCEL -sdi P0[0] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[0] -sdo P1[0] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[0] -shared_output -shared_input
define_scan_chain -name chain_TOP_1 -sdi P0[1] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[1] -sdo P1[1] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[1] -shared_output -shared_input
define_scan_chain -name chain_TOP_2 -sdi P0[2] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[2] -sdo P1[2] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[2] -shared_output -shared_input
diff --git a/ASIC/44pin/Cadence/scripts/genus_nodft.tcl b/ASIC/44pin/Cadence/scripts/genus_nodft.tcl
index a9bbe21..6f01ef0 100644
--- a/ASIC/44pin/Cadence/scripts/genus_nodft.tcl
+++ b/ASIC/44pin/Cadence/scripts/genus_nodft.tcl
@@ -11,7 +11,7 @@
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
-
+set_multi_cpu_usage -local_cpu 8
## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
@@ -50,6 +50,7 @@ read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
set_db syn_generic_effort high
set_db syn_map_effort high
+set_db syn_opt_effort high
syn_generic
syn_map
diff --git a/ASIC/44pin/Cadence/scripts/nanosoc.mmmc b/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
index 8c0b52a..6e6c726 100644
--- a/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
+++ b/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
@@ -95,4 +95,4 @@ create_analysis_view -name typical_analysis_view_hold -constraint_mode default_c
create_analysis_view -name typical_analysis_view -constraint_mode default_constraint_mode -delay_corner typical_delay_corner
-set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
+set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
diff --git a/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io b/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
index 290c50d..6b01846 100644
--- a/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
+++ b/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
@@ -37,7 +37,7 @@
(bottom
(inst name="uPAD_P0_02" offset=149.29 place_status=placed )
(inst name="uPAD_VDDACC_1" offset=257.86 place_status=placed )
- (inst name="uPAD_VDDIO_1" offset=366.43 place_status=placed )
+ (inst name="uPAD_SE_I" offset=366.43 place_status=placed )
(inst name="uPAD_VDD_1" offset=475.00 place_status=placed )
(inst name="uPAD_VSS_1" offset=583.57 place_status=placed )
(inst name="uPAD_P0_01" offset=692.14 place_status=placed )
diff --git a/ASIC/44pin/Cadence/scripts/place.tcl b/ASIC/44pin/Cadence/scripts/place.tcl
index 4a94713..0ca4c53 100644
--- a/ASIC/44pin/Cadence/scripts/place.tcl
+++ b/ASIC/44pin/Cadence/scripts/place.tcl
@@ -9,9 +9,9 @@ set_db design_process_node 65
set_db place_global_cong_effort auto
set_db place_global_timing_effort high
-### Uniform Cell Distribution
-
+### Uniform Cell Distribution and fill gap
set_db place_global_uniform_density true
+set_db place_detail_legalization_inst_gap 2
### Placement Mode Config
set_db place_design_floorplan_mode false
diff --git a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
index a383dd6..68704dd 100644
--- a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
+++ b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
@@ -38,25 +38,33 @@ source power_plan.tcl
### Power Route
source power_route.tcl
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
+report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing_late.rep
+report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing_early.rep
+
uniquify nanosoc_chip_pads -verbose
write_db nanosoc_chip_pads
### Placement
source place.tcl
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
-reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware false
+report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing_late.rep
+report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing_early.rep
+
+reorder_scan
write_db nanosoc_chip_pads
### CTS
source clock_tree_synthesis.tcl
-reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware true
+reorder_scan -clock_aware true
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
+report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing_late.rep
+report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing_early.rep
write_db nanosoc_chip_pads
+### Add fillers
+source filler.tcl
+
### Routing
source route.tcl
@@ -65,13 +73,6 @@ report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route
check_antenna
write_db nanosoc_chip_pads
-### Add filler cells
-#eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
-#eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
-add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true
-add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true
-add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true -fix_drc
-add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true -fix_drc
delete_routes -net VDDIO
source place_bondpads.tcl
@@ -83,11 +84,6 @@ write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
-merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
-output_macros -unit 1000 -mode all
-
-write_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.v
-write_sdf $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.sdf
-
-
report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
@@ -95,4 +91,9 @@ report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical.rep
+set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
+
+write_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.v
+write_sdf -min_view default_analysis_view_hold -typical_view typical_analysis_view -max_view default_analysis_view_setup $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.sdf
+
write_db nanosoc_chip_pads
diff --git a/ASIC/44pin/Cadence/scripts/power_plan.tcl b/ASIC/44pin/Cadence/scripts/power_plan.tcl
index e3d70dc..52c08f9 100644
--- a/ASIC/44pin/Cadence/scripts/power_plan.tcl
+++ b/ASIC/44pin/Cadence/scripts/power_plan.tcl
@@ -17,6 +17,7 @@ set_db add_rings_stacked_via_bottom_layer M1
### Adding Rings
add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
### Adding Stripes
set_db add_stripes_ignore_block_check true
diff --git a/ASIC/44pin/Cadence/scripts/tieoff_exclude b/ASIC/44pin/Cadence/scripts/tieoff_exclude
index a684166..c28aa79 100644
--- a/ASIC/44pin/Cadence/scripts/tieoff_exclude
+++ b/ASIC/44pin/Cadence/scripts/tieoff_exclude
@@ -1,3 +1,8 @@
+uPAD_SE_I/IE
+uPAD_SE_I/PE
+uPAD_SE_I/DS
+uPAD_SE_I/I
+uPAD_SE_I/OEN
uPAD_CLK_I/IE
uPAD_CLK_I/PE
uPAD_CLK_I/DS
diff --git a/ASIC/44pin/Mentor/LVS b/ASIC/44pin/Mentor/LVS
new file mode 100644
index 0000000..4205367
--- /dev/null
+++ b/ASIC/44pin/Mentor/LVS
@@ -0,0 +1,8 @@
+*lvsRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/lvs/calibre.lvs
+*lvsRunDir: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/./LVS
+*lvsLayoutPaths: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/nanosoc_srimanth_17_02_24.gds
+*lvsLayoutPrimary: nanosoc_chip_pads
+*lvsSourcePath: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_lvt/r0p0/verilog/sc12_cln65lp_base_lvt.v
+*lvsSourceSystem: VERILOG
+*lvsSourcePrimary: nanosoc_chip_pads
+*cmnV2LVS_LastTranslation: 1708338090
diff --git a/ASIC/constraints.sdc b/ASIC/constraints.sdc
index 06f2c75..fa229e0 100644
--- a/ASIC/constraints.sdc
+++ b/ASIC/constraints.sdc
@@ -16,49 +16,56 @@ set SWDCLK "swdclk";
set_units -time ns;
set_units -capacitance pF;
-set EXTCLK_PERIOD 4.1667;
+set EXTCLK_PERIOD 4.16667;
set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
+set CLK_ERROR [expr 0.1*$EXTCLK_PERIOD];
+set INTER_CLOCK_UNCERTAINTY 0.1
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
-set SKEW 0.800
-set_clock_uncertainty [expr 0.17*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
-set_clock_uncertainty [expr 0.17*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
+set_clock_uncertainty $CLK_ERROR [get_clocks $EXTCLK]
+set_clock_uncertainty $CLK_ERROR [get_clocks $SWDCLK]
-set MINRISE 0.20
-set MAXRISE 0.25
-set MINFALL 0.20
-set MAXFALL 0.25
+set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $SWDCLK] -rise_to [get_clocks $EXTCLK]
+set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $EXTCLK] -rise_to [get_clocks $SWDCLK]
-set_clock_transition -rise -min $MINRISE [get_clocks $EXTCLK]
-set_clock_transition -rise -max $MAXRISE [get_clocks $EXTCLK]
-set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
-set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
+### Multicycle path through asynchronous clock domains
+set_multicycle_path 2 -setup -end -from SWDCK -to CLK
+set_multicycle_path 1 -hold -end -from SWDCK -to CLK
+set_multicycle_path 2 -setup -end -from CLK -to SWDCK
+set_multicycle_path 1 -hold -end -from CLK -to SWDCK
-set_clock_transition -rise -min $MINRISE [get_clocks $SWDCLK]
-set_clock_transition -rise -max $MAXRISE [get_clocks $SWDCLK]
-set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
-set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
+set_false_path -hold -from CLK -to SWDCK
### Multicycle path through pads
-
-#set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
set_false_path -through uPAD_SWDIO_IO
-set_multicycle_path -through uPAD_SWDIO_IO
-set_false_path -through uPAD_P0_*
-set_false_path -through uPAD_P1_*
-#set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/*
-#set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/*
+set_multicycle_path 2 -through uPAD_SWDIO_IO
+#set_false_path -through uPAD_P0_*
+#set_false_path -through uPAD_P1_*
+
+set_multicycle_path 2 -from uPAD_SWDIO_IO/I -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/IE -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/DS -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/OEN -to uPAD_SWDIO_IO/C
+
+set_multicycle_path 2 -from uPAD_P0_*/I -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/IE -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/DS -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/OEN -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P1_*/I -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/IE -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/DS -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/OEN -to uPAD_P1_*/C
#### DELAY DEFINITION
-set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
-set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports TEST]
-set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
-set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
-set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIO]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports NRST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports TEST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P0]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P1]
+set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.1 [get_ports SWDIO]
set_max_capacitance 3 [all_outputs]
-set_max_fanout 10 [all_inputs]
\ No newline at end of file
+set_max_fanout 10 [all_inputs]
diff --git a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
index edeb7e4..08ae5f4 100644
--- a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
+++ b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
@@ -44,6 +44,7 @@ module nanosoc_chip_pads (
inout wire VSS,
inout wire VDDACC,
+ input wire SE,
input wire CLK, // input
input wire TEST, // input
input wire NRST, // active low reset
@@ -104,6 +105,8 @@ wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
+wire pad_se_i;
+
// connect up high order GPIOs
assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
@@ -128,7 +131,7 @@ nanosoc_chip_cfg #(
,.pad_nrst_i (pad_nrst_i )
,.pad_test_i (pad_test_i )
// Alternate/reconfigurable IP and associated bidirectional I/O
- ,.pad_altin_i (pad_swdclk_i ) // SWCLK/UARTRXD/SCAN-ENABLE
+ ,.pad_altin_i (pad_se_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
@@ -211,7 +214,7 @@ nanosoc_chip_cfg #(
.swdio_o(soc_swd_dio_o),
.swdio_e(soc_swd_dio_e),
.swdio_z(soc_swd_dio_z),
- .swdclk_i(soc_swd_clk_i)
+ .swdclk_i(pad_swdclk_i)
);
@@ -224,9 +227,9 @@ nanosoc_chip_cfg #(
PVDD2CDG uPAD_VDDIO_0(
.VDDPST(VDDIO)
);
-PVDD2CDG uPAD_VDDIO_1(
- .VDDPST(VDDIO)
- );
+//PVDD2CDG uPAD_VDDIO_1(
+// .VDDPST(VDDIO)
+// );
PVDD2CDG uPAD_VDDIO_2(
.VDDPST(VDDIO)
);
@@ -234,11 +237,11 @@ PVDD2POC uPAD_VDDIO_3(
.VDDPST(VDDIO)
);
-PVSS3CDG uPAD_VSSIO_0(
- .VSS(VSS)
+PVSS2CDG uPAD_VSSIO_0(
+ .VSSPST(VSSIO)
);
-PVSS3CDG uPAD_VSSIO_1(
- .VSS(VSS)
+PVSS2CDG uPAD_VSSIO_1(
+ .VSSPST(VSSIO)
);
// Core power supplies
@@ -256,16 +259,16 @@ PVDD1CDG uPAD_VDD_3(
.VDD(VDD)
);
-PVSS3CDG uPAD_VSS_0(
+PVSS1CDG uPAD_VSS_0(
.VSS(VSS)
);
-PVSS3CDG uPAD_VSS_1(
+PVSS1CDG uPAD_VSS_1(
.VSS(VSS)
);
-PVSS3CDG uPAD_VSS_2(
+PVSS1CDG uPAD_VSS_2(
.VSS(VSS)
);
-PVSS3CDG uPAD_VSS_3(
+PVSS1CDG uPAD_VSS_3(
.VSS(VSS)
);
// Accelerator Power supplies
@@ -281,6 +284,17 @@ PVDD1CDG uPAD_VDDACC_2(
// Clock, Reset and Serial Wire Debug ports
+PRDW0408SCDG uPAD_SE_I (
+ .IE(tiehi),
+ .C(pad_se_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(SE)
+ );
+
+
PRDW0408SCDG uPAD_CLK_I (
.IE(tiehi),
.C(pad_clk_i),
diff --git a/flows/makefile.asic b/flows/makefile.asic
index 4d9e6d9..070b8d7 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -38,7 +38,8 @@ MEMORIES_DIR := $(SOCLABS_PROJECT_DIR)/memories
RF_16K_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_16k.spec
RF_08K_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_08k.spec
ROM_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rom_via.spec
-BOOTROM_BIN_FILE := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
+BOOTROM_BIN_FILE_IN := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
+BOOTROM_BIN_FILE := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.rcf
RF_16K_DIR := $(MEMORIES_DIR)/rf_16k
RF_08K_DIR := $(MEMORIES_DIR)/rf_08k
ROM_DIR := $(MEMORIES_DIR)/bootrom
@@ -77,6 +78,7 @@ gen_memories: bootrom
@mkdir -p $(RF_16K_DIR)
@mkdir -p $(RF_08K_DIR)
@mkdir -p $(ROM_DIR)
+ cp $(BOOTROM_BIN_FILE_IN) $(BOOTROM_BIN_FILE)
echo "Generating register file memory libraries"
echo "16K RF"
cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_16K_SPEC_FILE);
@@ -99,6 +101,12 @@ syn_genus_44pin:
@mkdir -p $(SYN_LOGS)
cd $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts; genus -f $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts/genus.tcl -log $(SYN_LOGS)/nanosoc_synth_genus.log
+syn_genus_44pin_noDFT:
+ @mkdir -p $(REPORTS_FOLDER)
+ @mkdir -p $(NETLIST_FOLDER)
+ @mkdir -p $(SYN_LOGS)
+ cd $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts; genus -f $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts/genus_nodft.tcl -log $(SYN_LOGS)/nanosoc_synth_genus_noDFT.log
+
syn_dc:
@mkdir -p $(REPORTS_FOLDER)
@mkdir -p $(NETLIST_FOLDER)/Synopsys
diff --git a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
index ccd6303..e83521e 100644
--- a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+++ b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
@@ -43,7 +43,8 @@ module nanosoc_chip_pads (
inout wire VDD,
inout wire VSS,
inout wire VDDACC,
-`endif
+`endif
+ input wire SE,
inout wire CLK, // input
inout wire TEST, // output
inout wire NRST, // active low reset
@@ -103,6 +104,9 @@ wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
+wire pad_se_i;
+
+
// connect up high order GPIOs
assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
@@ -126,7 +130,7 @@ nanosoc_chip_cfg #(
,.pad_nrst_i (pad_nrst_i )
,.pad_test_i (pad_test_i )
// Alternate/reconfigurable IP and associated bidirectional I/O
- ,.pad_altin_i (pad_swdclk_i ) // SWCLK/UARTRXD/SCAN-ENABLE
+ ,.pad_altin_i (pad_se_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
@@ -213,7 +217,7 @@ nanosoc_chip_cfg #(
.swdio_o (soc_swd_dio_o),
.swdio_e (soc_swd_dio_e),
.swdio_z (soc_swd_dio_z),
- .swdclk_i (soc_swd_clk_i)
+ .swdclk_i (pad_swd_clk_i)
);
@@ -250,6 +254,13 @@ PAD_VDDSOC uPAD_VDDACC_1(
// Clock, Reset and Serial Wire Debug ports
+PAD_INOUT8MA_NOE uPAD_SE_I (
+ .PAD (SE),
+ .O (tielo),
+ .I (pad_se_i),
+ .NOE (tiehi)
+ );
+
PAD_INOUT8MA_NOE uPAD_CLK_I (
.PAD (CLK),
.O (tielo),
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 7028c23..8f41a20 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -135,6 +135,7 @@ initial begin
.VSS (VSS),
.VDDACC (VDDACC),
`endif
+ .SE (1'b0),
.CLK (CLK), // input
.TEST (TEST), // input
.NRST (NRST), // active low reset
@@ -153,6 +154,7 @@ initial begin
.VSS (VSS),
.VDDACC (VDDACC),
`endif
+ .SE (1'b0),
.CLK (CLK), // input
.TEST (TEST), // input
.NRST (NRST), // active low reset
--
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