From 5b1ffaf671011d95d91cc3d8f4becae2dbcef3aa Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Wed, 2 Oct 2024 15:31:32 +0100
Subject: [PATCH] merge extio8x4 interface and tests
---
extio8x4-axis/rtl/extio8x4_axis_initiator.v | 153 +
extio8x4-axis/rtl/extio8x4_axis_target.v | 126 +
extio8x4-axis/rtl/extio8x4_ifsm.v | 422 +
extio8x4-axis/rtl/extio8x4_sync.v | 46 +
extio8x4-axis/rtl/extio8x4_tfsm.v | 313 +
flist/nanosoc.flist | 3 +
flist/nanosoc_tb.flist | 4 +-
flist/nanosoc_vip.flist | 3 +-
.../nanosoc_chip/chip/verilog/nanosoc_chip.v | 80 +-
.../sysio/verilog/nanosoc_region_sysio.v | 59 +-
.../sysio/verilog/nanosoc_sysio_apb_ss.v | 99 +-
.../sysio/verilog/nanosoc_sysio_decode.v | 41 +-
.../debug/verilog/nanosoc_ss_debug.v | 87 +-
.../verilog/nanosoc_ss_systemctrl.v | 67 +-
.../nanosoc_system/verilog/nanosoc_system.v | 408 +-
nanosoc/socdebug_tech | 2 +-
.../Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h | 16 +-
.../CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s | 51 +-
software/common/bootloader/bootloader.c | 1 -
software/common/demos/interrupt_demo.c | 28 +-
software/common/validation/apb_mux_tests.c | 8 +-
.../common/validation/uart_driver_tests.c | 27 +-
software/common/validation/uart_tests.c | 90 +-
testcodes/apb_mux_tests/apb_mux_tests.hex | 68 +-
testcodes/bootloader/bootloader.hex | 622 +-
testcodes/debug_tests/debug_tests.hex | 500 +-
.../default_slaves_tests.hex | 270 +-
testcodes/dhry/dhry.hex | 362 +-
testcodes/dma350_tests/dma350_tests.hex | 7286 +++++++++-------
testcodes/dma_tests/dma_tests.hex | 362 +-
testcodes/dualtimer_demo/dualtimer_demo.hex | 400 +-
.../gpio_driver_tests/gpio_driver_tests.hex | 474 +-
testcodes/hello/hello.hex | 242 +-
testcodes/interrupt_demo/interrupt_demo.hex | 862 +-
testcodes/memory_tests/memory_tests.hex | 396 +-
testcodes/romtable_tests/romtable_tests.hex | 608 +-
testcodes/self_reset_demo/self_reset_demo.hex | 328 +-
testcodes/sleep_demo/sleep_demo.hex | 374 +-
.../timer_driver_tests/timer_driver_tests.hex | 494 +-
testcodes/timer_tests/timer_tests.hex | 354 +-
.../uart_driver_tests/uart_driver_tests.hex | 3454 ++++----
testcodes/uart_tests/uart_tests.hex | 7550 +++++++++--------
testcodes/watchdog_demo/watchdog_demo.hex | 326 +-
verif/tb/verilog/nanosoc_tb.v | 236 +-
verif/tb/verilog/nanosoc_tb_qs.v | 2 +
.../nanosoc_axi_stream_io_8_rxd_to_file.v | 9 +-
.../nanosoc_axi_stream_io_8_txd_from_file.v | 5 +-
verif/trace/verilog/soclabs_axis8_capture.v | 274 +
48 files changed, 16750 insertions(+), 11242 deletions(-)
create mode 100644 extio8x4-axis/rtl/extio8x4_axis_initiator.v
create mode 100644 extio8x4-axis/rtl/extio8x4_axis_target.v
create mode 100644 extio8x4-axis/rtl/extio8x4_ifsm.v
create mode 100644 extio8x4-axis/rtl/extio8x4_sync.v
create mode 100644 extio8x4-axis/rtl/extio8x4_tfsm.v
create mode 100644 verif/trace/verilog/soclabs_axis8_capture.v
diff --git a/extio8x4-axis/rtl/extio8x4_axis_initiator.v b/extio8x4-axis/rtl/extio8x4_axis_initiator.v
new file mode 100644
index 0000000..5224cc7
--- /dev/null
+++ b/extio8x4-axis/rtl/extio8x4_axis_initiator.v
@@ -0,0 +1,153 @@
+//-----------------------------------------------------------------------------
+// 8-bit extio transfer over 4-bit data plane - initiator
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : Initiator FSM wrapped with synchronizers
+//-----------------------------------------------------------------------------
+
+
+module extio8x4_axis_initiator
+ (
+ input wire clk,
+ input wire resetn,
+ input wire testmode,
+// RX 4-channel AXIS interface
+ output wire axis_rx0_tready,
+ input wire axis_rx0_tvalid,
+ input wire [7:0] axis_rx0_tdata8,
+ output wire axis_rx1_tready,
+ input wire axis_rx1_tvalid,
+ input wire [7:0] axis_rx1_tdata8,
+ input wire axis_tx0_tready,
+ output wire axis_tx0_tvalid,
+ output wire [7:0] axis_tx0_tdata8,
+ input wire axis_tx1_tready,
+ output wire axis_tx1_tvalid,
+ output wire [7:0] axis_tx1_tdata8,
+// external io interface
+ input wire [3:0] iodata4_a,
+ output wire [3:0] iodata4_o,
+ output wire [3:0] iodata4_e,
+ output wire [3:0] iodata4_t,
+ output wire ioreq1_o,
+ output wire ioreq2_o,
+ input wire ioack_a
+ );
+
+wire ioack_s;
+wire [3:0] iodata4_s;
+
+extio8x4_sync u_extio8x4_sync_ioack
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(ioack_a),
+ .sig_s(ioack_s)
+ );
+
+extio8x4_sync u_extio8x4_sync_iodata0
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(iodata4_a[0]),
+ .sig_s(iodata4_s[0])
+ );
+
+extio8x4_sync u_extio8x4_sync_iodata1
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(iodata4_a[1]),
+ .sig_s(iodata4_s[1])
+ );
+
+extio8x4_sync u_extio8x4_sync_iodata2
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(iodata4_a[2]),
+ .sig_s(iodata4_s[2])
+ );
+
+extio8x4_sync u_extio8x4_sync_iodata3
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(iodata4_a[3]),
+ .sig_s(iodata4_s[3])
+ );
+
+extio8x4_ifsm u_extio8x4_ifsm
+ (
+ .clk ( clk ),
+ .resetn ( resetn ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_i ( iodata4_a ),
+ .iodata4_s ( iodata4_s ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_o ( ioreq1_o ),
+ .ioreq2_o ( ioreq2_o ),
+ .ioack_s ( ioack_s )
+ );
+
+endmodule
+
+/*
+extio8x4_axis_initiator u_extio8x4_axis_initiator
+ (
+ .clk ( clk ),
+ .resetn ( resetn ),
+ .testmode ( testmode ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_a ( iodata4_a ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_o ( ioreq1_a ),
+ .ioreq2_o ( ioreq2_a ),
+ .ioack_a ( ioack_a )
+ );
+
+*/
diff --git a/extio8x4-axis/rtl/extio8x4_axis_target.v b/extio8x4-axis/rtl/extio8x4_axis_target.v
new file mode 100644
index 0000000..f1fa65b
--- /dev/null
+++ b/extio8x4-axis/rtl/extio8x4_axis_target.v
@@ -0,0 +1,126 @@
+//-----------------------------------------------------------------------------
+// 8-bit extio transfer over 4-bit data plane - target
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : target FSM wrapped with synchronizers
+//-----------------------------------------------------------------------------
+
+
+module extio8x4_axis_target
+ (
+ input wire clk,
+ input wire resetn,
+ input wire testmode,
+// RX 4-channel AXIS interface
+ output wire axis_rx0_tready,
+ input wire axis_rx0_tvalid,
+ input wire [7:0] axis_rx0_tdata8,
+ output wire axis_rx1_tready,
+ input wire axis_rx1_tvalid,
+ input wire [7:0] axis_rx1_tdata8,
+ input wire axis_tx0_tready,
+ output wire axis_tx0_tvalid,
+ output wire [7:0] axis_tx0_tdata8,
+ input wire axis_tx1_tready,
+ output wire axis_tx1_tvalid,
+ output wire [7:0] axis_tx1_tdata8,
+// external io interface
+ input wire [3:0] iodata4_i,
+ output wire [3:0] iodata4_o,
+ output wire [3:0] iodata4_e,
+ output wire [3:0] iodata4_t,
+ input wire ioreq1_a,
+ input wire ioreq2_a,
+ output wire ioack_o
+ );
+
+wire ioreq1_s;
+wire ioreq2_s;
+
+extio8x4_sync u_extio8x4_sync_ioreq1
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(ioreq1_a),
+ .sig_s(ioreq1_s)
+ );
+
+extio8x4_sync u_extio8x4_sync_ioreq2
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(ioreq2_a),
+ .sig_s(ioreq2_s)
+ );
+
+
+extio8x4_tfsm u_extio8x4_tfsm
+ (
+ .clk ( clk ),
+ .resetn ( resetn ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_i ( iodata4_i ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_s ( ioreq1_s ),
+ .ioreq2_s ( ioreq2_s ),
+ .ioack_o ( ioack_o )
+ );
+
+endmodule
+
+/*
+extio8x4_axis_target u_extio8x4_axis_target
+ (
+ .clk ( clk ),
+ .resetn ( resetn ),
+ .testmode ( testmode ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_i ( iodata4_i ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_a ( ioreq1_i ),
+ .ioreq2_a ( ioreq2_i ),
+ .ioack_o ( ioack_o )
+ );
+
+*/
diff --git a/extio8x4-axis/rtl/extio8x4_ifsm.v b/extio8x4-axis/rtl/extio8x4_ifsm.v
new file mode 100644
index 0000000..073415c
--- /dev/null
+++ b/extio8x4-axis/rtl/extio8x4_ifsm.v
@@ -0,0 +1,422 @@
+//-----------------------------------------------------------------------------
+// 8-bit extio transfer over 4-bit data plane - initiator
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : Initiator state machine and sequencer
+//-----------------------------------------------------------------------------
+
+
+module extio8x4_ifsm
+ (
+ input wire clk,
+ input wire resetn,
+// RX 4-channel AXIS interface
+ output wire axis_rx0_tready,
+ input wire axis_rx0_tvalid,
+ input wire [7:0] axis_rx0_tdata8,
+ output wire axis_rx1_tready,
+ input wire axis_rx1_tvalid,
+ input wire [7:0] axis_rx1_tdata8,
+ input wire axis_tx0_tready,
+ output wire axis_tx0_tvalid,
+ output wire [7:0] axis_tx0_tdata8,
+ input wire axis_tx1_tready,
+ output wire axis_tx1_tvalid,
+ output wire [7:0] axis_tx1_tdata8,
+// external io interface
+ input wire [3:0] iodata4_i,
+ input wire [3:0] iodata4_s,
+ output wire [3:0] iodata4_o,
+ output wire [3:0] iodata4_e,
+ output wire [3:0] iodata4_t,
+ output wire ioreq1_o,
+ output wire ioreq2_o,
+ input wire ioack_s
+ );
+
+// Fair priority sequencer
+// return next 12 transactions - to support 1,2,3 and 4 requests
+function [23:0] FNpriority_seq12x2;
+input [3:0] req4;
+case (req4[3:0])
+4'b0001: FNpriority_seq12x2 = 24'b00_00_00_00_00_00_00_00_00_00_00_00; // chan 0
+4'b0010: FNpriority_seq12x2 = 24'b01_01_01_01_01_01_01_01_01_01_01_01; // chan 1
+4'b0011: FNpriority_seq12x2 = 24'b01_00_01_00_01_00_01_00_01_00_01_00; // chan 0/1
+4'b0100: FNpriority_seq12x2 = 24'b10_10_10_10_10_10_10_10_10_10_10_10; // chan 2
+4'b0101: FNpriority_seq12x2 = 24'b10_00_10_00_10_00_10_00_10_00_10_00; // chan 0/2
+4'b0110: FNpriority_seq12x2 = 24'b10_01_10_01_10_01_10_01_10_01_10_01; // chan 1/2
+4'b0111: FNpriority_seq12x2 = 24'b10_01_00_10_01_00_10_01_00_10_01_00; // chan 0/1/2
+4'b1000: FNpriority_seq12x2 = 24'b11_11_11_11_11_11_11_11_11_11_11_11; // chan 3
+4'b1001: FNpriority_seq12x2 = 24'b11_00_11_00_11_00_11_00_11_00_11_00; // chan 0/3
+4'b1010: FNpriority_seq12x2 = 24'b11_01_11_01_11_01_11_01_11_01_11_01; // chan 1/3
+4'b1011: FNpriority_seq12x2 = 24'b11_01_00_11_01_00_11_01_00_11_01_00; // chan 0/1/3
+4'b1100: FNpriority_seq12x2 = 24'b11_10_11_10_11_10_11_10_11_10_11_10; // chan 2/3
+4'b1101: FNpriority_seq12x2 = 24'b11_10_00_11_10_00_11_10_00_11_10_00; // chan 0/2/3
+4'b1110: FNpriority_seq12x2 = 24'b11_10_01_11_10_01_11_10_01_11_10_01; // chan 1/2/3
+4'b1111: FNpriority_seq12x2 = 24'b11_10_01_00_11_10_01_00_11_10_01_00; // chan 0/1/2/3
+default: FNpriority_seq12x2 = 24'b0; // (no requests)
+endcase
+endfunction
+
+function [1:0] FNmap_patt2code2;
+input [23:0] priority_seq12x2;
+input [3:0] seq12_no;
+case (seq12_no[3:0])
+4'b0000: FNmap_patt2code2 = priority_seq12x2[ 1: 0];
+4'b0001: FNmap_patt2code2 = priority_seq12x2[ 3: 2];
+4'b0010: FNmap_patt2code2 = priority_seq12x2[ 5: 4];
+4'b0011: FNmap_patt2code2 = priority_seq12x2[ 7: 6];
+4'b0100: FNmap_patt2code2 = priority_seq12x2[ 9: 8];
+4'b0101: FNmap_patt2code2 = priority_seq12x2[11:10];
+4'b0110: FNmap_patt2code2 = priority_seq12x2[13:12];
+4'b0111: FNmap_patt2code2 = priority_seq12x2[15:14];
+4'b1000: FNmap_patt2code2 = priority_seq12x2[17:16];
+4'b1001: FNmap_patt2code2 = priority_seq12x2[19:18];
+4'b1010: FNmap_patt2code2 = priority_seq12x2[21:20];
+4'b1011: FNmap_patt2code2 = priority_seq12x2[23:22];
+default: FNmap_patt2code2 = 2'b00; // (illegal seq no)
+endcase
+endfunction
+
+
+reg ack;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ ack <= 1'b0;
+ else
+ ack <= ioack_s;
+end
+
+wire ack_change = ack ^ ioack_s;
+
+
+// state[0] = ioreq1
+// state[1] = ioreq2
+// state[2] = CTL4_EN
+// state[3] = WD4H_EN
+// state[4] = WD4L_EN
+// state[5] = WDONE
+// state[6] = RD4H_EN
+// state[7] = RD4L_EN
+// state[8] = RXDONE
+// state[9] = TX
+
+localparam STAT = 10'b0_000_0000_00;
+localparam RXC1 = 10'b0_000_0000_01;
+localparam RXC2 = 10'b0_000_0001_11;
+localparam RXDH = 10'b0_001_0000_01;
+localparam RXDL = 10'b0_010_0000_11;
+localparam RXDZ = 10'b0_100_0000_01;
+localparam TXDH = 10'b1_000_0010_01;
+localparam TXDL = 10'b1_000_0100_11;
+localparam TXDZ = 10'b1_000_1000_01;
+
+reg [9:0] fsm_state;
+reg [9:0] nxt_fsm_state;
+
+reg [3:0] cmd4;
+
+wire start_xfer;
+
+// ifsm next-state seqeuncer
+always @(*)
+ case (fsm_state)
+ STAT: nxt_fsm_state = (!ioack_s & (start_xfer)) ? RXC1 : STAT;
+ RXC1: nxt_fsm_state = ( ioack_s) ? RXC2 : RXC1;
+ RXC2: nxt_fsm_state = (!ioack_s) ? ((cmd4[0]) ? RXDH : TXDH) : RXC2;
+ RXDH: nxt_fsm_state = ( ioack_s) ? RXDL : RXDH;
+ RXDL: nxt_fsm_state = (!ioack_s) ? RXDZ : RXDL;
+ RXDZ: nxt_fsm_state = ( ioack_s) ? STAT : RXDZ;
+ TXDH: nxt_fsm_state = ( ioack_s) ? TXDL : TXDH;
+ TXDL: nxt_fsm_state = (!ioack_s) ? TXDZ : TXDL;
+ TXDZ: nxt_fsm_state = ( ioack_s) ? STAT : TXDZ;
+ default: nxt_fsm_state = STAT;
+ endcase
+
+// state update
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn) begin
+ fsm_state <= 10'h000;
+ end else begin
+ fsm_state <= nxt_fsm_state;
+ end
+end
+
+wire status_valid = !fsm_state[0];
+
+// stream buffers with valid qualifiers
+reg [8:0] rx0_reg9;
+reg [8:0] rx1_reg9;
+reg [8:0] tx0_reg9;
+reg [8:0] tx1_reg9;
+
+// axis request per channel to FSM, hold until ack
+wire rx0_axis_req;
+wire rx1_axis_req;
+wire tx0_axis_req;
+wire tx1_axis_req;
+// axis request acknowledge per channel, from FSM, 1-cycle pulse
+wire rx0_axis_ack;
+wire rx1_axis_ack;
+wire tx0_axis_ack;
+wire tx1_axis_ack;
+
+reg req_rx0;
+reg req_rx1;
+reg req_tx0;
+reg req_tx1;
+
+// data ports
+wire [7:0] tx_axis_rdata8;
+wire [7:0] rx0_axis_wdata8;
+wire [7:0] rx1_axis_wdata8;
+
+
+// axis RX1 port interface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rx0_reg9 <= 9'b0_00000000;
+ else begin
+ if (!rx0_reg9[8] & axis_rx0_tvalid) rx0_reg9 <= {1'b1,axis_rx0_tdata8[7:0]};
+ else if (rx0_reg9[8] & rx0_axis_ack) rx0_reg9[8] <= 1'b0;
+ end
+end
+assign axis_rx0_tready = !rx0_reg9[8];
+assign rx0_axis_wdata8 = rx0_reg9[7:0];
+assign rx0_axis_req = rx0_reg9[8];
+
+// axis RX2 port interface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rx1_reg9 <= 9'b0_00000000;
+ else begin
+ if (!rx1_reg9[8] & axis_rx1_tvalid) rx1_reg9 <= {1'b1,axis_rx1_tdata8[7:0]};
+ else if (rx1_reg9[8] & rx1_axis_ack) rx1_reg9[8] <= 1'b0;
+ end
+end
+assign axis_rx1_tready = !rx1_reg9[8];
+assign rx1_axis_wdata8 = rx1_reg9[7:0];
+assign rx1_axis_req = rx1_reg9[8];
+
+// axis TX1 port interface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ tx0_reg9 <= 9'b0_00000000;
+ else begin
+ if (!tx0_reg9[8] & tx0_axis_ack) tx0_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
+ else if (tx0_reg9[8] & axis_tx0_tready) tx0_reg9[8] <= 1'b0;
+ end
+end
+assign axis_tx0_tvalid = tx0_reg9[8];
+assign axis_tx0_tdata8[7:0] = tx0_reg9[7:0];
+assign tx0_axis_req = !tx0_reg9[8];
+
+// axis tx2 port interextio8x4_ifsmface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ tx1_reg9 <= 9'b0_00000000;
+ else begin
+ if (!tx1_reg9[8] & tx1_axis_ack) tx1_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
+ else if (tx1_reg9[8] & axis_tx1_tready) tx1_reg9[8] <= 1'b0;
+ end
+end
+assign axis_tx1_tvalid = tx1_reg9[8];
+assign axis_tx1_tdata8[7:0] = tx1_reg9[7:0];
+assign tx1_axis_req = !tx1_reg9[8];
+
+// virtual channel requests, only valid during status phase
+wire vtx0_req = status_valid & !iodata4_s[0] & req_tx0;
+wire vrx0_req = status_valid & !iodata4_s[1] & req_rx0;
+wire vtx1_req = status_valid & !iodata4_s[2] & req_tx1;
+wire vrx1_req = status_valid & !iodata4_s[3] & req_rx1;
+
+wire [3:0] active_req4 = {vtx1_req, vrx1_req, vtx0_req, vrx0_req};
+
+// any active request
+wire cmd4_req = (vtx0_req | vrx0_req | vtx1_req | vrx1_req);
+assign start_xfer = (cmd4_req & !ioack_s);
+
+// 12 cycle sequencer counter
+reg [3:0] seq_cnt12;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ seq_cnt12 <= 4'b0000;
+ else
+ if (start_xfer) seq_cnt12 <= (seq_cnt12 >= 11) ? 4'b0000 : (seq_cnt12+4'b0001);
+end
+
+wire [3:0] cmd4_nxt;
+
+// command resister
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ cmd4 <= 4'b0000; // invalid xfer pattern
+ else if (cmd4_req)
+ cmd4 <= cmd4_nxt;
+end
+
+
+// simplest fixed priority scheme: RX0, RX1, TX0, TX1 (decreasing)
+/*
+assign cmd4_nxt[0] = (vrx0_req | vrx1_req); // Read/not-write always has priority
+assign cmd4_nxt[1] = !(vrx0_req | vtx0_req);
+*/
+assign cmd4_nxt[1:0] = FNmap_patt2code2(FNpriority_seq12x2(active_req4), seq_cnt12);
+/* */
+
+assign cmd4_nxt[3:2] = 2'b00; // fixed 8-bit transfer
+
+// write data resister - for the committed channel
+reg [7:0] wdata8;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ wdata8 <= 8'b00000000; // avoid X propagation
+ else if (start_xfer & !cmd4_nxt[0]) // capture selected wdata
+ wdata8 <= (cmd4_nxt[1]) ? rx1_axis_wdata8[7:0] : rx0_axis_wdata8[7:0];
+end
+
+// request handshake
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_rx0 <= 1'b0; // avoid X propagation
+ else if (rx0_axis_req & !req_rx0) // capture rx_req front edge
+ req_rx0 <= 1'b1;
+ else if (rx0_axis_ack & req_rx0)
+ req_rx0 <= 1'b0;
+end
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_rx1 <= 1'b0; // avoid X propagation
+ else if (rx1_axis_req & !req_rx1) // capture rx_req front edge
+ req_rx1 <= 1'b1;
+ else if (rx1_axis_ack & req_rx1)
+ req_rx1 <= 1'b0;
+end
+
+// request handshake
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_tx0 <= 1'b0; // avoid X propagation
+ else if (tx0_axis_req & !req_tx0) // capture tx_req front edge
+ req_tx0 <= 1'b1;
+ else if (tx0_axis_ack & req_tx0)
+ req_tx0 <= 1'b0;
+end
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_tx1 <= 1'b0; // avoid X propagation
+ else if (tx1_axis_req & !req_tx1) // capture tx_req front edge
+ req_tx1 <= 1'b1;
+ else if (tx1_axis_ack & req_tx1)
+ req_tx1 <= 1'b0;
+end
+
+
+// fsm decodes:
+// request signalling
+assign ioreq1_o = fsm_state[0];
+assign ioreq2_o = fsm_state[1];
+// dataout mux
+wire cmd_state = fsm_state[2];
+wire wdh_state = fsm_state[3];
+wire wdl_state = fsm_state[4];
+wire wdone = fsm_state[5];
+// datain sel
+wire rdh_state = fsm_state[6];
+wire rdl_state = fsm_state[7];
+wire rdone = fsm_state[8];
+
+// IO Write Data
+assign iodata4_o = ({4{cmd_state}} & cmd4)
+ | ({4{wdh_state}} & wdata8[7:4])
+ | ({4{wdl_state}} & wdata8[3:0])
+ | ({4{wdone}} & wdata8[3:0])
+ ;
+
+assign iodata4_e = {4{|(fsm_state[4:2])}};
+assign iodata4_t = ~iodata4_e;
+
+// and ack
+assign rx0_axis_ack = !cmd4[1] & !cmd4[0] & wdone & ack_change;
+assign rx1_axis_ack = cmd4[1] & !cmd4[0] & wdone & ack_change;
+
+// IO Read data
+// first register high nibble read data
+reg [3:0] rd4_hi;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rd4_hi <= 4'b0000; // initialize
+ else if (rdh_state & ack_change)
+ rd4_hi <= iodata4_i[3:0];
+end
+
+reg [3:0] rd4_lo;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rd4_lo <= 4'b0000; // initialize
+ else if (rdl_state & ack_change)
+ rd4_lo <= iodata4_i[3:0];
+end
+
+assign tx_axis_rdata8 = {rd4_hi[3:0],rd4_lo[3:0]};
+
+// then ack with 8-bit data to selected axis buffer
+assign tx0_axis_ack = !cmd4[1] & cmd4[0] & rdone & ack_change;
+assign tx1_axis_ack = cmd4[1] & cmd4[0] & rdone & ack_change;
+
+endmodule
+
+/*
+extio8x4_ifsm u_extio8x4_ifsm
+ (
+ .clk ( clk ),
+ .resetn ( resetn ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_i ( iodata4_i ),
+ .iodata4_s ( iodata4_s ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_o ( ioreq1_o ),
+ .ioreq2_o ( ioreq2_o ),
+ .ioack_s ( ioack_s )
+ );
+
+*/
diff --git a/extio8x4-axis/rtl/extio8x4_sync.v b/extio8x4-axis/rtl/extio8x4_sync.v
new file mode 100644
index 0000000..ed8d53f
--- /dev/null
+++ b/extio8x4-axis/rtl/extio8x4_sync.v
@@ -0,0 +1,46 @@
+//-----------------------------------------------------------------------------
+// 8-bit extio transfer over 4-bit data plane - initiator
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module extio8x4_sync
+ (
+ input wire clk,
+ input wire resetn,
+ input wire testmode,
+ input wire sig_a,
+ output wire sig_s
+ );
+
+reg [2:1] sig_r;
+
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ sig_r <= 2'b00; // default
+ else
+ sig_r <= {sig_r[1], sig_a}; // shift left
+end
+
+assign sig_s = (testmode) ? sig_a : sig_r[2];
+
+endmodule
+
+/*
+extio8x4_sync, u_extio8x4_sync_1
+ (
+ .clk(clk),
+ .resetn(resetn),
+ .testmode(testmode),
+ .sig_a(sig_i),
+ .sig_s(sig_s)
+ );
+
+*/
diff --git a/extio8x4-axis/rtl/extio8x4_tfsm.v b/extio8x4-axis/rtl/extio8x4_tfsm.v
new file mode 100644
index 0000000..b1d7372
--- /dev/null
+++ b/extio8x4-axis/rtl/extio8x4_tfsm.v
@@ -0,0 +1,313 @@
+//-----------------------------------------------------------------------------
+// 8-bit extio transfer over 4-bit data plane - target
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : Initiator state machine and sequencer
+//-----------------------------------------------------------------------------
+
+
+module extio8x4_tfsm
+ (
+ input wire clk,
+ input wire resetn,
+// RX 4-channel AXIS interface
+ output wire axis_rx0_tready,
+ input wire axis_rx0_tvalid,
+ input wire [7:0] axis_rx0_tdata8,
+ output wire axis_rx1_tready,
+ input wire axis_rx1_tvalid,
+ input wire [7:0] axis_rx1_tdata8,
+ input wire axis_tx0_tready,
+ output wire axis_tx0_tvalid,
+ output wire [7:0] axis_tx0_tdata8,
+ input wire axis_tx1_tready,
+ output wire axis_tx1_tvalid,
+ output wire [7:0] axis_tx1_tdata8,
+// external io interface
+ input wire [3:0] iodata4_i,
+ output wire [3:0] iodata4_o,
+ output wire [3:0] iodata4_e,
+ output wire [3:0] iodata4_t,
+ input wire ioreq1_s,
+ input wire ioreq2_s,
+ output wire ioack_o
+ );
+
+
+// axis request per channel to FSM, hold until ack
+wire rx0_axis_req;
+wire rx1_axis_req;
+wire tx0_axis_req;
+wire tx1_axis_req;
+// axis request acknowledge per channel, from FSM, 1-cycle pulse
+wire rx0_axis_ack;
+wire rx1_axis_ack;
+wire tx0_axis_ack;
+wire tx1_axis_ack;
+
+reg req_rx0;
+reg req_rx1;
+reg req_tx0;
+reg req_tx1;
+
+// data ports
+wire [7:0] tx_axis_rdata8;
+wire [7:0] rx0_axis_wdata8;
+wire [7:0] rx1_axis_wdata8;
+
+
+wire ack_nxt = ioreq1_s ^ ioreq2_s;
+
+reg ack;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ ack <= 1'b0;
+ else
+ ack <= ack_nxt;
+end
+
+wire ack_change = ack ^ ack_nxt;
+
+
+// state[0] = ACK
+// state[1] = CTL4_EN
+// state[2] = RD4H_EN
+// state[3] = RD4L_EN
+// state[4] = STAT_EN
+// state[5] = WD4H_EN
+// state[6] = WD4L_EN
+
+
+localparam STAT = 8'b0_001_000_0;
+localparam RXC1 = 8'b0_000_001_1;
+localparam RXDH = 8'b0_000_010_0;
+localparam RXDL = 8'b0_000_100_1;
+localparam RXDZ = 8'b0_000_000_0;
+localparam STAZ = 8'b0_001_000_1;
+
+localparam TXCZ = 8'b1_000_000_0;
+localparam TXDH = 8'b1_010_000_1;
+localparam TXDL = 8'b1_100_000_0;
+
+reg [7:0] fsm_state;
+reg [7:0] nxt_fsm_state;
+
+// ifsm next-state seqeuncer
+always @(*)
+ case (fsm_state)
+ STAT: nxt_fsm_state = ( ioreq1_s) ? RXC1 : STAT;
+ RXC1: nxt_fsm_state = (!ioreq2_s) ? RXC1 : (iodata4_i[0]) ? TXCZ : RXDH;
+ RXDH: nxt_fsm_state = ( ioreq2_s) ? RXDH : RXDL;
+ RXDL: nxt_fsm_state = (!ioreq2_s) ? RXDL : RXDZ;
+ RXDZ: nxt_fsm_state = ( ioreq2_s) ? RXDZ : STAZ;
+ STAZ: nxt_fsm_state = ( ioreq1_s) ? STAZ : STAT;
+ TXCZ: nxt_fsm_state = ( ioreq2_s) ? TXCZ : TXDH;
+ TXDH: nxt_fsm_state = (!ioreq2_s) ? TXDH : TXDL;
+ TXDL: nxt_fsm_state = ( ioreq2_s) ? TXDL : STAZ;
+ default: nxt_fsm_state = STAT;
+ endcase
+
+// state update
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn) begin
+ fsm_state <= STAT;
+ end else
+ fsm_state <= nxt_fsm_state;
+ end
+
+assign ioack_o = fsm_state[0];
+// 3 input sample enable
+wire cmd_state = fsm_state[1];
+wire rdh_state = fsm_state[2];
+wire rdl_state = fsm_state[3];
+// 3 output enable
+wire fif_state = fsm_state[4];
+wire wdh_state = fsm_state[5];
+wire wdl_state = fsm_state[6];
+
+// command resister
+reg [3:0] cmd4;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ cmd4 <= 4'b1111; // invalid xfer pattern
+ else if (cmd_state & ack_change)
+ cmd4 <= iodata4_i[3:0];
+end
+
+wire [3:0] fifo_stat = ~{req_tx1, req_rx1, req_tx0, req_rx0 };
+// IO Write Data
+assign iodata4_o = ({4{fif_state}} & fifo_stat)
+ | ({4{wdh_state}} & ((cmd4[1]) ? rx1_axis_wdata8[7:4] : rx0_axis_wdata8[7:4]))
+ | ({4{wdl_state}} & ((cmd4[1]) ? rx1_axis_wdata8[3:0] : rx0_axis_wdata8[3:0]))
+ ;
+
+assign iodata4_e = {4{|(fsm_state[6:4])}};
+assign iodata4_t = {4{!iodata4_e}};
+
+// and ack
+assign rx0_axis_ack = !cmd4[1] & cmd4[0] & wdl_state & ack_change;
+assign rx1_axis_ack = cmd4[1] & cmd4[0] & wdl_state & ack_change;
+
+// IO Read data
+// first register high nibble read data
+reg [3:0] rd4_hi;
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rd4_hi <= 4'b0000; // initialize
+ else if (rdh_state & ack_change)
+ rd4_hi <= iodata4_i[3:0];
+end
+
+assign tx_axis_rdata8 = {rd4_hi[3:0],iodata4_i[3:0]};
+
+// then ack with 8-bit data to selected axis buffer
+assign tx0_axis_ack = !cmd4[1] & !cmd4[0] & rdl_state & ack_change;
+assign tx1_axis_ack = cmd4[1] & !cmd4[0] & rdl_state & ack_change;
+
+// stream buffers with valid qualifiers
+reg [8:0] rx0_reg9;
+reg [8:0] rx1_reg9;
+reg [8:0] tx0_reg9;
+reg [8:0] tx1_reg9;
+
+// axis RX1 port interface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rx0_reg9 <= 9'b0_00000000;
+ else begin
+ if (!rx0_reg9[8] & axis_rx0_tvalid) rx0_reg9 <= {1'b1,axis_rx0_tdata8[7:0]};
+ else if (rx0_reg9[8] & rx0_axis_ack) rx0_reg9[8] <= 1'b0;
+ end
+end
+assign axis_rx0_tready = !rx0_reg9[8];
+assign rx0_axis_wdata8 = rx0_reg9[7:0];
+assign rx0_axis_req = rx0_reg9[8] & !fsm_state[2] & !fsm_state[3];
+
+// axis RX2 port interface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ rx1_reg9 <= 9'b0_00000000;
+ else begin
+ if (!rx1_reg9[8] & axis_rx1_tvalid) rx1_reg9 <= {1'b1,axis_rx1_tdata8[7:0]};
+ else if (rx1_reg9[8] & rx1_axis_ack) rx1_reg9[8] <= 1'b0;
+ end
+end
+assign axis_rx1_tready = !rx1_reg9[8];
+assign rx1_axis_wdata8 = rx1_reg9[7:0];
+assign rx1_axis_req = rx1_reg9[8] & !fsm_state[2] & !fsm_state[3];
+
+// axis TX1 port interface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ tx0_reg9 <= 9'b0_00000000;
+ else begin
+ if (!tx0_reg9[8] & tx0_axis_ack) tx0_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
+ else if (tx0_reg9[8] & axis_tx0_tready) tx0_reg9[8] <= 1'b0;
+ end
+end
+assign axis_tx0_tvalid = tx0_reg9[8];
+assign axis_tx0_tdata8[7:0] = tx0_reg9[7:0];
+assign tx0_axis_req = !tx0_reg9[8];
+
+// axis tx2 port interextio8x4_ifsmface
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ tx1_reg9 <= 9'b0_00000000;
+ else begin
+ if (!tx1_reg9[8] & tx1_axis_ack) tx1_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
+ else if (tx1_reg9[8] & axis_tx1_tready) tx1_reg9[8] <= 1'b0;
+ end
+end
+assign axis_tx1_tvalid = tx1_reg9[8];
+assign axis_tx1_tdata8[7:0] = tx1_reg9[7:0];
+assign tx1_axis_req = !tx1_reg9[8];
+
+
+// request handshake
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_rx0 <= 1'b0; // avoid X propagation
+ else if (rx0_axis_req & !req_rx0) // capture rx_req front edge
+ req_rx0 <= 1'b1;
+ else if (rx0_axis_ack & req_rx0)
+ req_rx0 <= 1'b0;
+end
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_rx1 <= 1'b0; // avoid X propagation
+ else if (rx1_axis_req & !req_rx1) // capture rx_req front edge
+ req_rx1 <= 1'b1;
+ else if (rx1_axis_ack & req_rx1)
+ req_rx1 <= 1'b0;
+end
+
+// request handshake
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_tx0 <= 1'b0; // avoid X propagation
+ else if (tx0_axis_req & !req_tx0) // capture tx_req front edge
+ req_tx0 <= 1'b1;
+ else if (tx0_axis_ack & req_tx0)
+ req_tx0 <= 1'b0;
+end
+always @(posedge clk or negedge resetn)
+begin
+ if (!resetn)
+ req_tx1 <= 1'b0; // avoid X propagation
+ else if (tx1_axis_req & !req_tx1) // capture tx_req front edge
+ req_tx1 <= 1'b1;
+ else if (tx1_axis_ack & req_tx1)
+ req_tx1 <= 1'b0;
+end
+
+endmodule
+
+/*
+extio8x4_ifsm u_extio8x4_tfsm
+ (
+ .clk ( clk ),
+ .resetn ( resetn ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_i ( iodata4_i ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_s ( ioreq1_s ),
+ .ioreq2_s ( ioreq2_s ),
+ .ioack_o ( ioack_o )
+ );
+
+*/
diff --git a/flist/nanosoc.flist b/flist/nanosoc.flist
index 2873314..56ca5e4 100644
--- a/flist/nanosoc.flist
+++ b/flist/nanosoc.flist
@@ -20,6 +20,9 @@
// NanoSoC Chip Pads Level
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
diff --git a/flist/nanosoc_tb.flist b/flist/nanosoc_tb.flist
index 8873895..d6cb28b 100644
--- a/flist/nanosoc_tb.flist
+++ b/flist/nanosoc_tb.flist
@@ -19,9 +19,11 @@
// - Top-level testbench
$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_target.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_tfsm.v
// Include NanoSoC Testbench Components
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist
// Include Corstone VIP Components
--f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
\ No newline at end of file
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
diff --git a/flist/nanosoc_vip.flist b/flist/nanosoc_vip.flist
index 7b8db83..284ad30 100644
--- a/flist/nanosoc_vip.flist
+++ b/flist/nanosoc_vip.flist
@@ -20,10 +20,11 @@
$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/soclabs_axis8_capture.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
diff --git a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 07ffa27..12253d7 100644
--- a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -74,31 +74,14 @@ module nanosoc_chip #(
wire CPU_0_SWDO; // SWD data output
wire CPU_0_SWDOEN; // SWD data enable
- // FT1248 Interace - FT1248
- wire FT_CLK_O; // SCLK
- wire FT_SSN_O; // SS_N
- wire FT_MISO_I; // MISO
- wire [FT1248_WIDTH-1:0] FT_MIOSIO_O; // MIOSIO tristate when enabled
- wire [FT1248_WIDTH-1:0] FT_MIOSIO_E; // MIOSIO tristate enable (active hi)
- wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z; // MIOSIO tristate enable (active lo)
- wire [FT1248_WIDTH-1:0] FT_MIOSIO_I; // MIOSIO tristate input
-
- // GPIO interface
- wire [7:0] GPO8;
- wire [7:0] GPI8;
-
// GPIO
wire [15:0] P0_IN; // GPIO 0 inputs
wire [15:0] P0_OUT; // GPIO 0 outputs
wire [15:0] P0_OUTEN; // GPIO 0 output enables
- wire [15:0] P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
- wire [15:0] P1_IN_MUX; // level-shifted input from pad
+ wire [15:0] P1_IN; // level-shifted input from pad
wire [15:0] P1_OUT; // GPIO 1 outputs
wire [15:0] P1_OUTEN; // GPIO 1 output enables
- wire [15:0] P1_OUT_MUX; // GPIO 1 aOutput Port Drive
- wire [15:0] P1_OUT_EN_MUX; // Active High output drive enable (pad tech dependent)
- wire [15:0] P1_ALTFUNC; // GPIO 1 alternate function (pin mux)
//--------------------------
// FPGA-Specific Wiring - Should be own Module
@@ -141,50 +124,20 @@ module nanosoc_chip #(
assign swdio_z = !CPU_0_SWDOEN;
//--------------------------
- // FT1248 Wiring
+ // PIO pad control
//--------------------------
assign P0_IN = p0_i;
assign p0_o = P0_OUT;
assign p0_e = P0_OUTEN;
assign p0_z = ~P0_OUTEN;
-
- assign FT_MISO_I = p1_i[0]; // FT_MISO INPUT pad configuration
- assign P1_IN_MUX[0] = p1_i[0];
- assign p1_o[0] = 1'b0;
- assign p1_e[0] = 1'b0;
- assign p1_z[0] = 1'b1;
-
- assign P1_IN_MUX[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
- assign p1_o[1] = FT_CLK_O;
- assign p1_e[1] = 1'b1;
- assign p1_z[1] = 1'b0;
-
- assign FT_MIOSIO_I = p1_i[2]; // FT_MIOSIO INOUT pad configuration
- assign P1_IN_MUX[2] = p1_i[2];
- assign p1_o[2] = FT_MIOSIO_O;
- assign p1_e[2] = FT_MIOSIO_E;
- assign p1_z[2] = FT_MIOSIO_Z;
- assign P1_IN_MUX[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
- assign p1_o[3] = FT_SSN_O;
- assign p1_e[3] = 1'b1;
- assign p1_z[3] = 1'b0;
- assign P1_IN_MUX[4] = (alt_mode) ? uart_rxd_i : p1_i[4]; // RXD2
- assign uart_txd_o = P1_OUT_MUX[5]; // TXD2
+ assign P1_IN = p1_i;
+ assign p1_o[15:0] = P1_OUT[15:0];
+ assign p1_e[15:0] = P1_OUTEN[15:0];
+ assign p1_z[15:0] = ~P1_OUTEN[15:0];
- assign P1_IN_MUX[15:5] = p1_i[15:5]; // IO MUX controlled bidirectionals
- assign p1_o[15:4] = P1_OUT_MUX[15:4];
- assign p1_e[15:4] = P1_OUT_EN_MUX[15:4];
- assign p1_z[15:4] = ~P1_OUT_EN_MUX[15:4];
-
- //--------------------------
- // GPIO Interface Assignment
- //--------------------------
-
- assign GPI8 = GPO8;
-
//--------------------------
// System Instantiation
//--------------------------
@@ -207,30 +160,13 @@ module nanosoc_chip #(
.CPU_0_SWDO(CPU_0_SWDO),
.CPU_0_SWDOEN(CPU_0_SWDOEN),
- // FT1248 Interace - FT1248
- .FT_CLK_O(FT_CLK_O),
- .FT_SSN_O(FT_SSN_O),
- .FT_MISO_I(FT_MISO_I),
- .FT_MIOSIO_O(FT_MIOSIO_O),
- .FT_MIOSIO_E(FT_MIOSIO_E),
- .FT_MIOSIO_Z(FT_MIOSIO_Z),
- .FT_MIOSIO_I(FT_MIOSIO_I),
-
- // GPIO interface
- .GPO8(GPO8),
- .GPI8(GPI8),
-
// GPIO
.P0_IN(P0_IN),
.P0_OUT(P0_OUT),
.P0_OUTEN(P0_OUTEN),
- .P0_ALTFUNC(P0_ALTFUNC),
- .P1_IN(P1_IN_MUX),
+ .P1_IN(P1_IN), //_MUX),
.P1_OUT(P1_OUT),
- .P1_OUTEN(P1_OUTEN),
- .P1_ALTFUNC(P1_ALTFUNC),
- .P1_OUT_MUX(P1_OUT_MUX),
- .P1_OUT_EN_MUX(P1_OUT_EN_MUX)
+ .P1_OUTEN(P1_OUTEN)
);
endmodule
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 3d3526c..b08b10a 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -82,12 +82,29 @@ module nanosoc_region_sysio #(
output wire PMUENABLE, // System Controller cfg - Enable PMU
// IO signalling
- input wire uart0_rxd, // Uart 0 receive data
- output wire uart0_txd, // Uart 0 transmit data
- output wire uart0_txen, // Uart 0 transmit data enable
- input wire uart1_rxd, // Uart 1 receive data
- output wire uart1_txd, // Uart 1 transmit data
- output wire uart1_txen, // Uart 1 transmit data enable
+// input wire uart0_rxd, // Uart 0 receive data
+// output wire uart0_txd, // Uart 0 transmit data
+// output wire uart0_txen, // Uart 0 transmit data enable
+ // USRT0 TXD axi byte stream
+ output wire usrt0_txd_tvalid,
+ output wire [ 7:0] usrt0_txd_tdata,
+ input wire usrt0_txd_tready,
+ // USRT0 RXD axi byte stream
+ input wire usrt0_rxd_tvalid,
+ input wire [ 7:0] usrt0_rxd_tdata,
+ output wire usrt0_rxd_tready,
+// input wire uart1_rxd, // Uart 1 receive data
+// output wire uart1_txd, // Uart 1 transmit data
+// output wire uart1_txen, // Uart 1 transmit data enable
+ // USRT1 TXD axi byte stream
+ output wire usrt1_txd_tvalid,
+ output wire [ 7:0] usrt1_txd_tdata,
+ input wire usrt1_txd_tready,
+ // USRT1 RXD axi byte stream
+ input wire usrt1_rxd_tvalid,
+ input wire [ 7:0] usrt1_rxd_tdata,
+ output wire usrt1_rxd_tready,
+ //UART2
input wire uart2_rxd, // Uart 2 receive data
output wire uart2_txd, // Uart 2 transmit data
output wire uart2_txen, // Uart 2 transmit data enable
@@ -375,8 +392,8 @@ module nanosoc_region_sysio #(
.INCLUDE_APB_TIMER0 (1), // Include simple timer #0
.INCLUDE_APB_TIMER1 (1), // Include simple timer #1
.INCLUDE_APB_DUALTIMER0 (1), // Include dual timer module
- .INCLUDE_APB_UART0 (0), // Exclude simple UART #0
- .INCLUDE_APB_UART1 (0), // Exclude simple UART #1
+ .INCLUDE_APB_USRT0 (1), // Replace simple UART #0 with USRT0
+ .INCLUDE_APB_USRT1 (1), // Replace simple UART #1 with USRT1
.INCLUDE_APB_UART2 (1), // Include simple UART #2.
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
@@ -433,13 +450,25 @@ module nanosoc_region_sysio #(
// Peripherals
// UART
- .uart0_rxd (uart0_rxd),
- .uart0_txd (uart0_txd),
- .uart0_txen (uart0_txen),
-
- .uart1_rxd (uart1_rxd),
- .uart1_txd (uart1_txd),
- .uart1_txen (uart1_txen),
+// .uart0_rxd (uart0_rxd),
+// .uart0_txd (uart0_txd),
+// .uart0_txen (uart0_txen),
+ .usrt0_txd_tvalid (usrt0_txd_tvalid),
+ .usrt0_txd_tdata (usrt0_txd_tdata ),
+ .usrt0_txd_tready (usrt0_txd_tready),
+ .usrt0_rxd_tvalid (usrt0_rxd_tvalid),
+ .usrt0_rxd_tdata (usrt0_rxd_tdata ),
+ .usrt0_rxd_tready (usrt0_rxd_tready),
+
+// .uart1_rxd (uart1_rxd),
+// .uart1_txd (uart1_txd),
+// .uart1_txen (uart1_txen),
+ .usrt1_txd_tvalid (usrt1_txd_tvalid),
+ .usrt1_txd_tdata (usrt1_txd_tdata ),
+ .usrt1_txd_tready (usrt1_txd_tready),
+ .usrt1_rxd_tvalid (usrt1_rxd_tvalid),
+ .usrt1_rxd_tdata (usrt1_rxd_tdata ),
+ .usrt1_rxd_tready (usrt1_rxd_tready),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
index 368acd4..55cace0 100755
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
@@ -59,8 +59,8 @@ module nanosoc_sysio_apb_ss #(
parameter INCLUDE_APB_TIMER0 = 1, // Include simple timer #0
parameter INCLUDE_APB_TIMER1 = 1, // Include simple timer #1
parameter INCLUDE_APB_DUALTIMER0 = 1, // Include dual timer module
- parameter INCLUDE_APB_UART0 = 1, // Include simple UART #0
- parameter INCLUDE_APB_UART1 = 1, // Include simple UART #1
+ parameter INCLUDE_APB_USRT0 = 1, // Include simple UART #0
+ parameter INCLUDE_APB_USRT1 = 1, // Include simple UART #1
parameter INCLUDE_APB_UART2 = 1, // Include simple UART #2.
// Note : UART #2 is required for text messages
// display and to enable debug tester in
@@ -139,15 +139,32 @@ module nanosoc_sysio_apb_ss #(
output wire APBACTIVE,
// Peripherals
- // UART
- input wire uart0_rxd,
- output wire uart0_txd,
- output wire uart0_txen,
-
- input wire uart1_rxd,
- output wire uart1_txd,
- output wire uart1_txen,
-
+ // USRT0
+// input wire uart0_rxd,
+// output wire uart0_txd,
+// output wire uart0_txen,
+ // USRT0 TXD axi byte stream
+ output wire usrt0_txd_tvalid,
+ output wire [ 7:0] usrt0_txd_tdata,
+ input wire usrt0_txd_tready,
+ // USRT0 RXD axi byte stream
+ input wire usrt0_rxd_tvalid,
+ input wire [ 7:0] usrt0_rxd_tdata,
+ output wire usrt0_rxd_tready,
+
+// input wire uart1_rxd,
+// output wire uart1_txd,
+// output wire uart1_txen,
+ // USRT1 TXD axi byte stream
+ output wire usrt1_txd_tvalid,
+ output wire [ 7:0] usrt1_txd_tdata,
+ input wire usrt1_txd_tready,
+ // USRT1 RXD axi byte stream
+ input wire usrt1_rxd_tvalid,
+ input wire [ 7:0] usrt1_rxd_tdata,
+ output wire usrt1_rxd_tready,
+
+ // UART2
input wire uart2_rxd,
output wire uart2_txd,
output wire uart2_txen,
@@ -354,8 +371,8 @@ module nanosoc_sysio_apb_ss #(
.PORT1_ENABLE (INCLUDE_APB_TIMER1), // timer 1
.PORT2_ENABLE (INCLUDE_APB_DUALTIMER0), // dual timer 0
.PORT3_ENABLE (1), // not used
- .PORT4_ENABLE (INCLUDE_APB_UART0), // uart 0
- .PORT5_ENABLE (INCLUDE_APB_UART1), // uart 1
+ .PORT4_ENABLE (INCLUDE_APB_USRT0), // uart 0
+ .PORT5_ENABLE (INCLUDE_APB_USRT1), // uart 1
.PORT6_ENABLE (INCLUDE_APB_UART2), // uart 2
.PORT7_ENABLE (1), // not used
.PORT8_ENABLE (INCLUDE_APB_WATCHDOG), // watchdog
@@ -601,8 +618,8 @@ module nanosoc_sysio_apb_ss #(
// -----------------------------------------------------------------
// UARTs
- generate if (INCLUDE_APB_UART0 == 1) begin : gen_apb_uart_0
- cmsdk_apb_uart u_apb_uart_0 (
+ generate if (INCLUDE_APB_USRT0 == 1) begin : gen_apb_uart_0
+ socdebug_usrt_control u_apb_usrt_0 (
.PCLK (PCLK), // Peripheral clock
.PCLKG (PCLKG), // Gated PCLK for bus
.PRESETn (PRESETn), // Reset
@@ -619,12 +636,22 @@ module nanosoc_sysio_apb_ss #(
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
- .RXD (uart0_rxd), // Receive data
+// .RXD (uart0_rxd), // Receive data
+//
+// .TXD (uart0_txd), // Transmit data
+// .TXEN (uart0_txen), // Transmit Enabled
+//
+// .BAUDTICK (), // Baud rate x16 tick output (for testing)
- .TXD (uart0_txd), // Transmit data
- .TXEN (uart0_txen), // Transmit Enabled
+ // USRT0 Interface - From USRT TXD
+ .TX_VALID_o (usrt0_txd_tvalid),
+ .TX_DATA8_o (usrt0_txd_tdata),
+ .TX_READY_i (usrt0_txd_tready),
- .BAUDTICK (), // Baud rate x16 tick output (for testing)
+ // USRT1 Interface - To USRT RXD
+ .RX_VALID_i (usrt0_rxd_tvalid),
+ .RX_DATA8_i (usrt0_rxd_tdata),
+ .RX_READY_o (usrt0_rxd_tready),
.TXINT (uart0_txint), // Transmit Interrupt
.RXINT (uart0_rxint), // Receive Interrupt
@@ -637,8 +664,11 @@ module nanosoc_sysio_apb_ss #(
assign uart0_prdata = {32{1'b0}};
assign uart0_pready = 1'b1;
assign uart0_pslverr = 1'b0;
- assign uart0_txd = 1'b1;
- assign uart0_txen = 1'b0;
+// assign uart0_txd = 1'b1;
+// assign uart0_txen = 1'b0;
+ assign usrt0_txd_tvalid = 1'b0;
+ assign usrt0_txd_tdata = {8{1'b0}};
+ assign usrt0_rxd_tready = 1'b0;
assign uart0_txint = 1'b0;
assign uart0_rxint = 1'b0;
assign uart0_txovrint = 1'b0;
@@ -646,8 +676,8 @@ module nanosoc_sysio_apb_ss #(
assign uart0_combined_int = 1'b0;
end endgenerate
- generate if (INCLUDE_APB_UART1 == 1) begin : gen_apb_uart_1
- cmsdk_apb_uart u_apb_uart_1 (
+ generate if (INCLUDE_APB_USRT1 == 1) begin : gen_apb_uart_1
+ socdebug_usrt_control u_apb_usrt_1 (
.PCLK (PCLK), // Peripheral clock
.PCLKG (PCLKG), // Gated PCLK for bus
.PRESETn (PRESETn), // Reset
@@ -664,12 +694,20 @@ module nanosoc_sysio_apb_ss #(
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
- .RXD (uart1_rxd), // Receive data
+// .RXD (uart1_rxd), // Receive data
+// .TXD (uart1_txd), // Transmit data
+// .TXEN (uart1_txen), // Transmit Enabled
+// .BAUDTICK (), // Baud rate x16 tick output (for testing)
+ // USRT1 Interface - From USRT TXD
+ .TX_VALID_o (usrt1_txd_tvalid),
+ .TX_DATA8_o (usrt1_txd_tdata),
+ .TX_READY_i (usrt1_txd_tready),
- .TXD (uart1_txd), // Transmit data
- .TXEN (uart1_txen), // Transmit Enabled
+ // USRT1 Interface - To USRT RXD
+ .RX_VALID_i (usrt1_rxd_tvalid),
+ .RX_DATA8_i (usrt1_rxd_tdata),
+ .RX_READY_o (usrt1_rxd_tready),
- .BAUDTICK (), // Baud rate x16 tick output (for testing)
.TXINT (uart1_txint), // Transmit Interrupt
.RXINT (uart1_rxint), // Receive Interrupt
@@ -682,8 +720,11 @@ module nanosoc_sysio_apb_ss #(
assign uart1_prdata = {32{1'b0}};
assign uart1_pready = 1'b1;
assign uart1_pslverr = 1'b0;
- assign uart1_txd = 1'b1;
- assign uart1_txen = 1'b0;
+// assign uart1_txd = 1'b1;
+// assign uart1_txen = 1'b0;
+ assign usrt1_txd_tvalid = 1'b0;
+ assign usrt1_txd_tdata = {8{1'b0}};
+ assign usrt1_rxd_tready = 1'b0;
assign uart1_txint = 1'b0;
assign uart1_rxint = 1'b0;
assign uart1_txovrint = 1'b0;
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
index d338ff8..5cb63f0 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -49,8 +49,7 @@ module nanosoc_sysio_decode #(
parameter BASEADDR_GPIO1 = 32'h4001_1000,
// Sysctrl base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000,
- parameter BASEADDR_ADC = 32'h4002_0000,
- parameter BASEADDR_PVT = 32'h4002_1000
+ parameter BASEADDR_ADC = 32'h4002_0000
)(
// System Address
input wire hsel,
@@ -63,9 +62,6 @@ module nanosoc_sysio_decode #(
output wire sysctrl_hsel,
`ifdef AMS_PERIPHERALS
output wire adcsys_hsel,
- `endif
- `ifdef SNPS_PVT_MONITORING
- output wire pvtsys_hsel,
`endif
// Default slave
output wire defslv_hsel
@@ -92,38 +88,21 @@ module nanosoc_sysio_decode #(
`ifdef AMS_PERIPHERALS
assign adcsys_hsel = hsel & (haddr[31:12]==
BASEADDR_ADC[31:12]); // 0x40020000
-`endif
-`ifdef SNPS_PVT_MONITORING
- assign pvtsys_hsel = hsel & (haddr[31:12]==
- BASEADDR_PVT[31:12]); // 0x40021000
`endif
// ----------------------------------------------------------
// Default slave decode logic
// ----------------------------------------------------------
`ifdef AMS_PERIPHERALS
- `ifdef SNPS_PVT_MONITORING
- assign defslv_hsel = ~(apbsys_hsel |
- gpio0_hsel | gpio1_hsel |
- sysctrl_hsel | adcsys_hsel | pvtsys_hsel
- );
- `else
- assign defslv_hsel = ~(apbsys_hsel |
- gpio0_hsel | gpio1_hsel |
- sysctrl_hsel | adcsys_hsel
- );
- `endif
+ assign defslv_hsel = ~(apbsys_hsel |
+ gpio0_hsel | gpio1_hsel |
+ sysctrl_hsel | adcsys_hsel
+ );
`else
- `ifdef SNPS_PVT_MONITORING
- assign defslv_hsel = ~(apbsys_hsel |
- gpio0_hsel | gpio1_hsel |
- sysctrl_hsel | pvtsys_hsel
- );
- `else
- assign defslv_hsel = ~(apbsys_hsel |
- gpio0_hsel | gpio1_hsel |
- sysctrl_hsel
- );
- `endif
+ assign defslv_hsel = ~(apbsys_hsel |
+ gpio0_hsel | gpio1_hsel |
+ sysctrl_hsel
+ );
+
`endif
endmodule
diff --git a/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v b/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
index c58aa93..c831fcf 100644
--- a/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
+++ b/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
@@ -13,15 +13,8 @@ module nanosoc_ss_debug #(
// System Parameters
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
-
- parameter APB_ADDR_W = 12, // APB Address Width
- parameter APB_DATA_W = 32, // APB Data Width
-
// SoCDebug Parameters
- parameter PROMPT_CHAR = "]",
- parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
- parameter [7:0] FT1248_CLKDIV = 8'd03 // Clock Division Ratio
+ parameter PROMPT_CHAR = "]"
)(
// System Clocks and Resets
input wire SYS_HCLK,
@@ -42,39 +35,35 @@ module nanosoc_ss_debug #(
input wire [SYS_DATA_W-1:0] DEBUG_HRDATA,
input wire DEBUG_HREADY,
input wire DEBUG_HRESP,
+
+ // USRT0 TXD axi byte stream
+ output wire ADP_RXD_TVALID_o,
+ output wire [ 7:0] ADP_RXD_TDATA_o ,
+ input wire ADP_RXD_TREADY_i,
+ // USRT0 RXD axi byte stream
+ input wire ADP_TXD_TVALID_i,
+ input wire [ 7:0] ADP_TXD_TDATA_i ,
+ output wire ADP_TXD_TREADY_o,
- // APB Slave Interface - USRT
- input wire DEBUG_PSEL, // Device select
- input wire [APB_ADDR_W-1:0] DEBUG_PADDR, // Address
- input wire DEBUG_PENABLE, // Transfer control
- input wire DEBUG_PWRITE, // Write control
- input wire [APB_DATA_W-1:0] DEBUG_PWDATA, // Write data
- output wire [APB_DATA_W-1:0] DEBUG_PRDATA, // Read data
- output wire DEBUG_PREADY, // Device ready
- output wire DEBUG_PSLVERR, // Device error response
-
- // FT1248 Interace - FT1248
- output wire FT_CLK_O, // SCLK
- output wire FT_SSN_O, // SS_N
- input wire FT_MISO_I, // MISO
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
- input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
-
+ // USRT0 TXD axi byte stream
+ output wire STD_RXD_TVALID_o,
+ output wire [ 7:0] STD_RXD_TDATA_o ,
+ input wire STD_RXD_TREADY_i,
+ // USRT0 RXD axi byte stream
+ input wire STD_TXD_TVALID_i,
+ input wire [ 7:0] STD_TXD_TDATA_i ,
+ output wire STD_TXD_TREADY_o,
+
// GPIO interface
output wire [7:0] GPO8,
input wire [7:0] GPI8
);
-
+
//---------------------------
// SoCDebug Instantiation
//---------------------------
socdebug_ahb #(
- .PROMPT_CHAR(PROMPT_CHAR),
- .FT1248_WIDTH(FT1248_WIDTH),
- .FT1248_CLKON(FT1248_CLKON),
- .FT1248_CLKDIV(FT1248_CLKDIV)
+ .PROMPT_CHAR(PROMPT_CHAR)
) u_socdebug (
// AHB-lite Master Interface - ADP
.HCLK(SYS_HCLK),
@@ -91,31 +80,23 @@ module nanosoc_ss_debug #(
.HREADY_i(DEBUG_HREADY),
.HRESP_i(DEBUG_HRESP),
- // APB Slave Interface - USRT
- .PCLK(SYS_PCLK),
- .PCLKG(SYS_PCLKG),
- .PRESETn(SYS_PRESETn),
- .PSEL_i(DEBUG_PSEL),
- .PADDR_i(DEBUG_PADDR[APB_ADDR_W-1:2]),
- .PENABLE_i(DEBUG_PENABLE),
- .PWRITE_i(DEBUG_PWRITE),
- .PWDATA_i(DEBUG_PWDATA),
- .PRDATA_o(DEBUG_PRDATA),
- .PREADY_o(DEBUG_PREADY),
- .PSLVERR_o(DEBUG_PSLVERR),
+ .ADP_RXD_TVALID_o(ADP_RXD_TVALID_o),
+ .ADP_RXD_TDATA_o( ADP_RXD_TDATA_o ),
+ .ADP_RXD_TREADY_i(ADP_RXD_TREADY_i),
+ .ADP_TXD_TVALID_i(ADP_TXD_TVALID_i),
+ .ADP_TXD_TDATA_i (ADP_TXD_TDATA_i ),
+ .ADP_TXD_TREADY_o(ADP_TXD_TREADY_o),
- // FT1248 Interace - FT1248
- .FT_CLK_O(FT_CLK_O),
- .FT_SSN_O(FT_SSN_O),
- .FT_MISO_I(FT_MISO_I),
- .FT_MIOSIO_O(FT_MIOSIO_O),
- .FT_MIOSIO_E(FT_MIOSIO_E),
- .FT_MIOSIO_Z(FT_MIOSIO_Z),
- .FT_MIOSIO_I(FT_MIOSIO_I),
+ .STD_RXD_TVALID_o(STD_RXD_TVALID_o),
+ .STD_RXD_TDATA_o( STD_RXD_TDATA_o ),
+ .STD_RXD_TREADY_i(STD_RXD_TREADY_i),
+ .STD_TXD_TVALID_i(STD_TXD_TVALID_i),
+ .STD_TXD_TDATA_i (STD_TXD_TDATA_i ),
+ .STD_TXD_TREADY_o(STD_TXD_TREADY_o),
// GPIO interface
.GPO8_o(GPO8),
.GPI8_i(GPI8)
);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 40e17a3..18ca5fe 100644
--- a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -118,7 +118,24 @@ module nanosoc_ss_systemctrl #(
input wire CPU_LOCKUP, // Processor status - Locked up
input wire CPU_SLEEPING,
input wire CPU_SLEEPDEEP,
-
+
+ // USRT0 TXD axi byte stream
+ output wire USRT0_TXD_TVALID,
+ output wire [ 7:0] USRT0_TXD_TDATA,
+ input wire USRT0_TXD_TREADY,
+ // USRT0 RXD axi byte stream
+ input wire USRT0_RXD_TVALID,
+ input wire [ 7:0] USRT0_RXD_TDATA,
+ output wire USRT0_RXD_TREADY,
+ // USRT1 TXD axi byte stream
+ output wire USRT1_TXD_TVALID,
+ output wire [ 7:0] USRT1_TXD_TDATA,
+ input wire USRT1_TXD_TREADY,
+ // USRT1 RXD axi byte stream
+ input wire USRT1_RXD_TVALID,
+ input wire [ 7:0] USRT1_RXD_TDATA,
+ output wire USRT1_RXD_TREADY,
+
// GPIO
input wire [15:0] P0_IN, // GPIO 0 inputs
output wire [15:0] P0_OUT, // GPIO 0 outputs
@@ -136,12 +153,13 @@ module nanosoc_ss_systemctrl #(
// -------------------------------
wire apbactive;
- wire uart0_rxd; // Uart 0 receive data
- wire uart0_txd; // Uart 0 transmit data
- wire uart0_txen; // Uart 0 transmit data enable
- wire uart1_rxd; // Uart 1 receive data
- wire uart1_txd; // Uart 1 transmit data
- wire uart1_txen; // Uart 1 transmit data enable
+// wire uart0_rxd; // Uart 0 receive data
+// wire uart0_txd; // Uart 0 transmit data
+// wire uart0_txen; // Uart 0 transmit data enable
+// wire uart1_rxd; // Uart 1 receive data
+// wire uart1_txd; // Uart 1 transmit data
+// wire uart1_txen; // Uart 1 transmit data enable
+
wire uart2_rxd; // Uart 2 receive data
wire uart2_txd; // Uart 2 transmit data
wire uart2_txen; // Uart 2 transmit data enable
@@ -184,12 +202,12 @@ module nanosoc_ss_systemctrl #(
// -------------------------------
nanosoc_pin_mux u_pin_mux (
// UART
- .uart0_rxd (uart0_rxd),
- .uart0_txd (uart0_txd),
- .uart0_txen (uart0_txen),
- .uart1_rxd (uart1_rxd),
- .uart1_txd (uart1_txd),
- .uart1_txen (uart1_txen),
+ .uart0_rxd ( ),
+ .uart0_txd (1'b1),
+ .uart0_txen (1'b1),
+ .uart1_rxd ( ),
+ .uart1_txd (1'b1),
+ .uart1_txen (1'b1),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
@@ -306,12 +324,21 @@ module nanosoc_ss_systemctrl #(
.PMUENABLE(SYS_PMUENABLE),
// IO signaling
- .uart0_rxd(uart1_txd), // crossover
- .uart0_txd(uart0_txd),
- .uart0_txen(uart0_txen),
- .uart1_rxd(uart0_txd), // crossover
- .uart1_txd(uart1_txd),
- .uart1_txen(uart1_txen),
+// USRT0
+ .usrt0_txd_tvalid (USRT0_TXD_TVALID),
+ .usrt0_txd_tdata (USRT0_TXD_TDATA ),
+ .usrt0_txd_tready (USRT0_TXD_TREADY),
+ .usrt0_rxd_tvalid (USRT0_RXD_TVALID),
+ .usrt0_rxd_tdata (USRT0_RXD_TDATA ),
+ .usrt0_rxd_tready (USRT0_RXD_TREADY),
+// USRT1
+ .usrt1_txd_tvalid (USRT1_TXD_TVALID),
+ .usrt1_txd_tdata (USRT1_TXD_TDATA ),
+ .usrt1_txd_tready (USRT1_TXD_TREADY),
+ .usrt1_rxd_tvalid (USRT1_RXD_TVALID),
+ .usrt1_rxd_tdata (USRT1_RXD_TDATA ),
+ .usrt1_rxd_tready (USRT1_RXD_TREADY),
+// UART2
.uart2_rxd(uart2_rxd),
.uart2_txd(uart2_txd),
.uart2_txen(uart2_txen),
@@ -358,4 +385,4 @@ module nanosoc_ss_systemctrl #(
.HRESP(SYSTABLE_HRESP),
.HREADYOUT(SYSTABLE_HREADYOUT)
);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index d45e5bf..4e4b3c1 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -63,7 +63,7 @@ module nanosoc_system #(
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
- parameter [7:0] FT1248_CLKDIV = 8'd03, // Clock Division Ratio
+ parameter [7:0] FT1248_CLKDIV = 8'd15, // Clock Division Ratio (4x4 for RP-PIO)
// Address of System ROM Table
parameter SYSTABLE_BASE = 32'hF000_0000, // Base Address of System ROM Table
@@ -92,31 +92,35 @@ module nanosoc_system #(
output wire CPU_0_SWDO, // SWD data output
output wire CPU_0_SWDOEN, // SWD data output enable
- // FT1248 Interace - FT1248
- output wire FT_CLK_O, // SCLK
- output wire FT_SSN_O, // SS_N
- input wire FT_MISO_I, // MISO
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
- input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
-
- // GPIO interface
- output wire [7:0] GPO8,
- input wire [7:0] GPI8,
-
// GPIO
input wire [15:0] P0_IN, // GPIO 0 inputs
output wire [15:0] P0_OUT, // GPIO 0 outputs
output wire [15:0] P0_OUTEN, // GPIO 0 output enables
- output wire [15:0] P0_ALTFUNC, // GPIO 0 alternate function (pin mux)
input wire [15:0] P1_IN, // GPIO 1 inputs
output wire [15:0] P1_OUT, // GPIO 1 outputs
- output wire [15:0] P1_OUTEN, // GPIO 1 output enables
- output wire [15:0] P1_ALTFUNC, // GPIO 1 alternate function (pin mux)
- output wire [15:0] P1_OUT_MUX, // GPIO 1 Output Port Drive
- output wire [15:0] P1_OUT_EN_MUX // Active High output drive enable (pad tech dependent)
+ output wire [15:0] P1_OUTEN // GPIO 1 output enables
);
+
+// system General purpose I/O ports - before NANOSOC specific mappings
+ wire [15:0] SYS_P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
+ wire [15:0] SYS_P1_ALTFUNC; // GPIO 1 alternate function (pin mux)
+ wire [15:0] SYS_P0_IN; // GPIO 0 inputs
+ wire [15:0] SYS_P0_OUT; // GPIO 0 outputs
+ wire [15:0] SYS_P0_OUTEN; // GPIO 0 output enables
+ wire [15:0] SYS_P1_IN; // GPIO 1 inputs
+ wire [15:0] SYS_P1_OUT; // GPIO 1 outputs
+ wire [15:0] SYS_P1_OUTEN; // GPIO 1 output enables
+ wire [15:0] SYS_P1_OUT_MUX; // GPIO 1 Output Port Drive
+ wire [15:0] SYS_P1_OUT_EN_MUX; // Active High output drive enable (pad tech dependent)
+
+ wire FT_CLK_O; // SCLK
+ wire FT_SSN_O; // SS_N
+ wire FT_MISO_I; // MISO
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_O; // MIOSIO tristate output when enabled
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_E; // MIOSIO tristate output enable (active hi)
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z; // MIOSIO tristate output enable (active lo)
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_I; // MIOSIO tristate input
+
//--------------------------
// Local Parameters
//--------------------------
@@ -165,6 +169,11 @@ module nanosoc_system #(
wire CPU_LOCKUP; // Combined Lockup from CPUs
wire CPU_SLEEPDEEP; // Combined Sleepdeep from CPUs
wire CPU_SLEEPING; // Combined sleeping from CPUs
+
+
+ // ADP GPIO interface
+ wire [7:0] ADP_GPO8;
+ wire [7:0] ADP_GPI8 = ADP_GPO8;
//--------------------------
// CPU Subsystem
@@ -646,11 +655,49 @@ module nanosoc_system #(
// Reset Request Wiring
//--------------------------
- assign DEBUG_RESETREQ = GPO8[0];
-
+ assign DEBUG_RESETREQ = ADP_GPO8[0];
+
+ // USRT0 TXD axi byte stream
+ wire USRT0_TXD_TVALID;
+ wire [ 7:0] USRT0_TXD_TDATA ;
+ wire USRT0_TXD_TREADY;
+ // USRT0 RXD axi byte stream
+ wire USRT0_RXD_TVALID;
+ wire [ 7:0] USRT0_RXD_TDATA ;
+ wire USRT0_RXD_TREADY;
+ // USRT1 TXD axi byte stream
+ wire USRT1_TXD_TVALID;
+ wire [ 7:0] USRT1_TXD_TDATA ;
+ wire USRT1_TXD_TREADY;
+ // USRT1 RXD axi byte stream
+ wire USRT1_RXD_TVALID;
+ wire [ 7:0] USRT1_RXD_TDATA ;
+ wire USRT1_RXD_TREADY;
+
+ wire ADP_RXD_TVALID;
+ wire [ 7:0] ADP_RXD_TDATA ;
+ wire ADP_RXD_TREADY;
+ wire ADP_TXD_TVALID;
+ wire [ 7:0] ADP_TXD_TDATA ;
+ wire ADP_TXD_TREADY;
+
+ // STDIN to ADP controller
+ wire STD_RXD_TVALID;
+ wire [ 7:0] STD_RXD_TDATA;
+ wire STD_RXD_TREADY;
+ // STDOUT to ADP controller
+ wire STD_TXD_TVALID;
+ wire [ 7:0] STD_TXD_TDATA;
+ wire STD_TXD_TREADY;
+
+ wire FT1248MODE = P1_IN[7]; // added to support EXTIO mapping
+
// Sideband Wiring
//--------------------------
+ wire [7:0] FT_CLKDIV;
+ assign FT_CLKDIV = FT1248_CLKDIV;
+
assign CPU_0_RXEV = DMAC_ANY_DONE;
// Instantiate Subsystem
@@ -659,16 +706,8 @@ module nanosoc_system #(
// System Parameters
.SYS_ADDR_W(SYS_ADDR_W),
.SYS_DATA_W(SYS_DATA_W),
-
- // APB Parameters
- .APB_ADDR_W(APB_ADDR_W),
- .APB_DATA_W(APB_DATA_W),
-
// SoCDebug Parameters
- .PROMPT_CHAR(PROMPT_CHAR),
- .FT1248_WIDTH(FT1248_WIDTH),
- .FT1248_CLKON(FT1248_CLKON),
- .FT1248_CLKDIV(FT1248_CLKDIV)
+ .PROMPT_CHAR(PROMPT_CHAR)
) u_ss_debug (
// System Clocks and Resets
.SYS_HCLK(SYS_HCLK),
@@ -690,28 +729,113 @@ module nanosoc_system #(
.DEBUG_HREADY(DEBUG_HREADY),
.DEBUG_HRESP(DEBUG_HRESP),
- // APB Slave Interface - USRT
- .DEBUG_PSEL(DEBUG_PSEL),
- .DEBUG_PADDR(SYSIO_PADDR),
- .DEBUG_PENABLE(SYSIO_PENABLE),
- .DEBUG_PWRITE(SYSIO_PWRITE),
- .DEBUG_PWDATA(SYSIO_PWDATA),
- .DEBUG_PRDATA(DEBUG_PRDATA),
- .DEBUG_PREADY(DEBUG_PREADY),
- .DEBUG_PSLVERR(DEBUG_PSLVERR),
-
- // FT1248 Interface - FT1248
- .FT_CLK_O(FT_CLK_O),
- .FT_SSN_O(FT_SSN_O),
- .FT_MISO_I(FT_MISO_I),
- .FT_MIOSIO_O(FT_MIOSIO_O),
- .FT_MIOSIO_E(FT_MIOSIO_E),
- .FT_MIOSIO_Z(FT_MIOSIO_Z),
- .FT_MIOSIO_I(FT_MIOSIO_I),
-
+ .ADP_RXD_TVALID_o(ADP_RXD_TVALID),
+ .ADP_RXD_TDATA_o( ADP_RXD_TDATA ),
+ .ADP_RXD_TREADY_i(ADP_RXD_TREADY),
+ .ADP_TXD_TVALID_i(ADP_TXD_TVALID),
+ .ADP_TXD_TDATA_i (ADP_TXD_TDATA ),
+ .ADP_TXD_TREADY_o(ADP_TXD_TREADY),
+
+ .STD_RXD_TVALID_o(STD_RXD_TVALID),
+ .STD_RXD_TDATA_o( STD_RXD_TDATA ),
+ .STD_RXD_TREADY_i(STD_RXD_TREADY),
+ .STD_TXD_TVALID_i(STD_TXD_TVALID),
+ .STD_TXD_TDATA_i (STD_TXD_TDATA ),
+ .STD_TXD_TREADY_o(STD_TXD_TREADY),
+
// GPIO interface
- .GPO8(GPO8),
- .GPI8(GPI8)
+ .GPO8(ADP_GPO8),
+ .GPI8(ADP_GPI8)
+ );
+
+ // Instantiation of USRT Controller
+ socdebug_usrt_control u_usrt_control (
+ // APB Clock and Reset Signals
+ .PCLK (SYS_PCLK),
+ .PCLKG (SYS_PCLKG), // Gated PCLK for bus
+ .PRESETn (SYS_PRESETn),
+
+ // APB Interface Signals
+ .PSEL (DEBUG_PSEL),
+ .PADDR (SYSIO_PADDR[11:2]),
+ .PENABLE (SYSIO_PENABLE),
+ .PWRITE (SYSIO_PWRITE),
+ .PWDATA (SYSIO_PWDATA),
+ .PRDATA (DEBUG_PRDATA),
+ .PREADY (DEBUG_PREADY),
+ .PSLVERR (DEBUG_PSLVERR),
+
+ .ECOREVNUM (4'h0),
+
+ // ADP Interface - From USRT to ADP
+ .TX_VALID_o (STD_TXD_TVALID),
+ .TX_DATA8_o (STD_TXD_TDATA ),
+ .TX_READY_i (STD_TXD_TREADY),
+
+ // ADP Interface - From ADP to USRT
+ .RX_VALID_i (STD_RXD_TVALID),
+ .RX_DATA8_i (STD_RXD_TDATA ),
+ .RX_READY_o (STD_RXD_TREADY),
+
+ // Interrupt Interfaces
+ .TXINT ( ), // Transmit Interrupt
+ .RXINT ( ), // Receive Interrupt
+ .TXOVRINT ( ), // Transmit Overrun Interrupt
+ .RXOVRINT ( ), // Receive Overrun Interrupt
+ .UARTINT ( ) // Combined Interrupt
+ );
+
+
+wire FT_ADP_RXD_TVALID ;
+wire [7:0] FT_ADP_RXD_TDATA ;
+wire FT_ADP_RXD_TREADY ;
+wire FT_ADP_TXD_TVALID ;
+wire [7:0] FT_ADP_TXD_TDATA ;
+wire FT_ADP_TXD_TREADY ;
+
+wire EXT_ADP_RXD_TVALID ;
+wire [7:0] EXT_ADP_RXD_TDATA ;
+wire EXT_ADP_RXD_TREADY ;
+wire EXT_ADP_TXD_TVALID ;
+wire [7:0] EXT_ADP_TXD_TDATA ;
+wire EXT_ADP_TXD_TREADY ;
+
+wire EXT_DAT_RXD_TVALID ;
+wire [7:0] EXT_DAT_RXD_TDATA ;
+wire EXT_DAT_RXD_TREADY ;
+wire EXT_DAT_TXD_TVALID ;
+wire [7:0] EXT_DAT_TXD_TDATA ;
+wire EXT_DAT_TXD_TREADY ;
+
+/// See the AXI stream muxes by EXTIO interface (below)
+
+ // Instantiation of FT1248 Controller
+ socdebug_ft1248_control #(
+ .FT1248_WIDTH (FT1248_WIDTH),
+ .FT1248_CLKON (FT1248_CLKON)
+ ) u_ft1248_control (
+ .clk (SYS_HCLK),
+ .resetn (SYS_HRESETn),
+ .ft_clkdiv (FT_CLKDIV),
+ .ft_clk_o (FT_CLK_O),
+ .ft_ssn_o (FT_SSN_O),
+ .ft_miso_i (FT_MISO_I),
+ .ft_miosio_o (FT_MIOSIO_O),
+ .ft_miosio_e (FT_MIOSIO_E),
+ .ft_miosio_z (FT_MIOSIO_Z),
+ .ft_miosio_i (FT_MIOSIO_I),
+
+ // ADP Interface - FT1248 to ADP
+ .txd_tvalid (FT_ADP_TXD_TVALID),
+ .txd_tdata (FT_ADP_TXD_TDATA ),
+ .txd_tready (FT_ADP_TXD_TREADY),
+ .txd_tlast ( ),
+
+ // ADP Interface - FT_ADP to FT1248
+ .rxd_tvalid (FT_ADP_RXD_TVALID),
+ .rxd_tdata (FT_ADP_RXD_TDATA ),
+ .rxd_tready (FT_ADP_RXD_TREADY),
+ .rxd_tlast (1'b0)
);
//--------------------------
@@ -1083,29 +1207,183 @@ module nanosoc_system #(
.CPU_LOCKUP(CPU_LOCKUP),
.CPU_SLEEPING(CPU_SLEEPING),
.CPU_SLEEPDEEP(CPU_SLEEPDEEP),
+
+ // USRT0
+ .USRT0_TXD_TVALID (USRT0_TXD_TVALID),
+ .USRT0_TXD_TDATA (USRT0_TXD_TDATA ),
+ .USRT0_TXD_TREADY (USRT0_TXD_TREADY),
+ .USRT0_RXD_TVALID (USRT0_RXD_TVALID),
+ .USRT0_RXD_TDATA (USRT0_RXD_TDATA ),
+ .USRT0_RXD_TREADY (USRT0_RXD_TREADY),
+ // USRT1
+ .USRT1_TXD_TVALID (USRT1_TXD_TVALID),
+ .USRT1_TXD_TDATA (USRT1_TXD_TDATA ),
+ .USRT1_TXD_TREADY (USRT1_TXD_TREADY),
+ .USRT1_RXD_TVALID (USRT1_RXD_TVALID),
+ .USRT1_RXD_TDATA (USRT1_RXD_TDATA ),
+ .USRT1_RXD_TREADY (USRT1_RXD_TREADY),
// GPIO
- .P0_IN(P0_IN),
- .P0_OUT(P0_OUT),
- .P0_OUTEN(P0_OUTEN),
- .P0_ALTFUNC(P0_ALTFUNC),
- .P1_IN(P1_IN),
- .P1_OUT(P1_OUT),
- .P1_OUTEN(P1_OUTEN),
- .P1_ALTFUNC(P1_ALTFUNC),
- .P1_OUT_MUX(P1_OUT_MUX),
- .P1_OUT_EN_MUX(P1_OUT_EN_MUX)
+ .P0_IN (SYS_P0_IN),
+ .P0_OUT (SYS_P0_OUT),
+ .P0_OUTEN (SYS_P0_OUTEN),
+ .P0_ALTFUNC (SYS_P0_ALTFUNC),
+ .P1_IN (SYS_P1_IN),
+ .P1_OUT (SYS_P1_OUT),
+ .P1_OUTEN (SYS_P1_OUTEN),
+ .P1_ALTFUNC (SYS_P1_ALTFUNC),
+ .P1_OUT_MUX (SYS_P1_OUT_MUX),
+ .P1_OUT_EN_MUX (SYS_P1_OUT_EN_MUX)
);
-
+
+
+// ADP input routing
+ assign ADP_RXD_TREADY = (FT1248MODE) ? FT_ADP_RXD_TREADY : EXT_ADP_RXD_TREADY;
+ assign ADP_TXD_TVALID = (FT1248MODE) ? FT_ADP_TXD_TVALID : EXT_ADP_TXD_TVALID;
+ assign ADP_TXD_TDATA = (FT1248MODE) ? FT_ADP_TXD_TDATA : EXT_ADP_TXD_TDATA;
+
+// FT1248 ADP output routing
+ assign FT_ADP_RXD_TVALID = (FT1248MODE) ? ADP_RXD_TVALID : 1'b0;
+ assign FT_ADP_RXD_TDATA = (FT1248MODE) ? ADP_RXD_TDATA : 8'b00000000;
+ assign FT_ADP_TXD_TREADY = (FT1248MODE) ? ADP_TXD_TREADY : 1'b0;
+
+// EXTIO ADP output routing
+ assign EXT_ADP_RXD_TVALID = (FT1248MODE) ? 1'b0 : ADP_RXD_TVALID;
+ assign EXT_ADP_RXD_TDATA = (FT1248MODE) ? 8'b00000000 : ADP_RXD_TDATA;
+ assign EXT_ADP_TXD_TREADY = (FT1248MODE) ? 1'b0 : ADP_TXD_TREADY;
+
+// USRT0 input loopback test - or disable
+ assign USRT0_RXD_TVALID = (FT1248MODE) ? USRT1_TXD_TVALID : 1'b0;
+ assign USRT0_RXD_TDATA = (FT1248MODE) ? USRT1_TXD_TDATA : 8'b00000000;
+ assign USRT0_TXD_TREADY = (FT1248MODE) ? USRT1_RXD_TREADY : 1'b0;
+
+// USRT1 input loopback - or EXT DAT
+ assign USRT1_RXD_TVALID = (FT1248MODE) ? USRT0_TXD_TVALID : EXT_DAT_TXD_TVALID ;
+ assign USRT1_RXD_TDATA = (FT1248MODE) ? USRT0_TXD_TDATA : EXT_DAT_TXD_TDATA;
+ assign USRT1_TXD_TREADY = (FT1248MODE) ? USRT0_RXD_TREADY : EXT_DAT_RXD_TREADY;
+
+// EXT DAT RXD
+ assign EXT_DAT_RXD_TVALID = (FT1248MODE) ? 1'b0 : USRT1_TXD_TVALID;
+ assign EXT_DAT_RXD_TDATA = (FT1248MODE) ? 8'b00000000 : USRT1_TXD_TDATA ;
+ assign EXT_DAT_TXD_TREADY = (FT1248MODE) ? 1'b0 : USRT1_RXD_TREADY;
+
+
+wire [3:0] iodata4_i;
+wire [3:0] iodata4_o;
+wire [3:0] iodata4_e;
+wire [3:0] iodata4_t;
+wire ioreq1_o;
+wire ioreq2_o;
+wire ioack_i ;
+
+
+extio8x4_axis_initiator u_extio8x4_axis_initiator
+ (
+ .clk ( SYS_HCLK ),
+ .resetn ( SYS_HRESETn ),
+ .testmode ( SYS_TESTMODE ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tvalid ( EXT_ADP_RXD_TVALID ),
+ .axis_rx0_tdata8 ( EXT_ADP_RXD_TDATA ),
+ .axis_rx0_tready ( EXT_ADP_RXD_TREADY ),
+ .axis_rx1_tvalid ( EXT_DAT_RXD_TVALID ),
+ .axis_rx1_tdata8 ( EXT_DAT_RXD_TDATA ),
+ .axis_rx1_tready ( EXT_DAT_RXD_TREADY ),
+ .axis_tx0_tvalid ( EXT_ADP_TXD_TVALID ),
+ .axis_tx0_tdata8 ( EXT_ADP_TXD_TDATA ),
+ .axis_tx0_tready ( EXT_ADP_TXD_TREADY ),
+ .axis_tx1_tvalid ( EXT_DAT_TXD_TVALID ),
+ .axis_tx1_tdata8 ( EXT_DAT_TXD_TDATA ),
+ .axis_tx1_tready ( EXT_DAT_TXD_TREADY ),
+// external io interface
+ .iodata4_a ( iodata4_i ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_o ( ioreq1_o ),
+ .ioreq2_o ( ioreq2_o ),
+ .ioack_a ( ioack_i )
+ );
+
+ // --------------------------------------------------------------------------------
+ // EXTIO8x4 stream interface - enabled when P1[7] input is low
+ // default in previous testbenches was pullup (for FT1248, UART2)
+ //
+ // v1 mapping was: v2 config
+ // P1[0] - ft_miso_in ioreq1_o
+ // P1[1] - ft_clk_out ioreq2_o
+ // P1[2] - ft_miosio_io ioack_i
+ // P1[3] - ft_ssn_out iodata[0]
+ // P1[4] - uart2_rxd iodata[1]
+ // P1[5] - uart2_txd iodata[2]
+ // P1[6] - reserved (pullup) iodata[3]
+ // P1[7] - reserved (pullup) 1'b0
+ // --------------------------------------------------------------------------------
+
+
+// SOC specific IO mapping - PORT0
+ assign SYS_P0_IN[15:0] = P0_IN[15:0];
+ assign P0_OUT[15:0] = SYS_P0_OUT[15:0];
+ assign P0_OUTEN[15:0] = SYS_P0_OUTEN[15:0];
+
+
+// PORT 1 [7] - low for EXTIO, high for FT1248/UART2
+
+// reassign PORT1[3:0] to FT1248x1 interface
+ assign FT_MISO_I = (FT1248MODE) ? P1_IN[0] : 1'b0; // FT_MISO INPUT pad configuration
+ assign P1_OUTEN[0] = (FT1248MODE) ? 1'b0 : 1'b1; // IOREQ1 output
+ assign P1_OUT[0] = (FT1248MODE) ? 1'b0 : ioreq1_o;
+ assign SYS_P1_IN[0] = (FT1248MODE) ? 1'b0 : ioreq1_o; // P1_IN[0]
+
+ assign P1_OUT[1] = (FT1248MODE) ? FT_CLK_O : ioreq2_o; // FT_CLK OUTPUT pad configuration
+ assign P1_OUTEN[1] = (FT1248MODE) ? 1'b1 : 1'b1;
+ assign SYS_P1_IN[1] = (FT1248MODE) ? 1'b0 : ioreq2_o; // P1_IN[1]
+
+ assign FT_MIOSIO_I[0] = (FT1248MODE) ? P1_IN[2] : 1'b0; // FT_MIOSIO INOUT pad configuration
+ assign P1_OUT[2] = (FT1248MODE) ? FT_MIOSIO_O[0] : 1'b0;
+ assign P1_OUTEN[2] = (FT1248MODE) ? FT_MIOSIO_E[0] : 1'b0;
+ assign SYS_P1_IN[2] = (FT1248MODE) ? 1'b0 : P1_IN[2]; // P1_IN[2];
+ assign ioack_i = (FT1248MODE) ? 1'b1 : P1_IN[2];
+
+ assign P1_OUT[3] = (FT1248MODE) ? FT_SSN_O : iodata4_o[0]; // FT_SSN OUTPUT pad configuration
+ assign P1_OUTEN[3] = (FT1248MODE) ? 1'b1 : iodata4_e[0];
+ assign SYS_P1_IN[3] = (FT1248MODE) ? 1'b1 : P1_IN[3];
+ assign iodata4_i[0] = (FT1248MODE) ? 1'b1 : P1_IN[3];
+
+ assign P1_OUT[4] = (FT1248MODE) ? SYS_P1_OUT_MUX[4] : iodata4_o[1];
+ assign P1_OUTEN[4] = (FT1248MODE) ? SYS_P1_OUT_EN_MUX[4] : iodata4_e[1];
+ assign SYS_P1_IN[4] = (FT1248MODE) ? P1_IN[4] : SYS_P1_OUT_MUX[5];
+ assign iodata4_i[1] = (FT1248MODE) ? 1'b1 : P1_IN[4];
+
+ assign P1_OUT[5] = (FT1248MODE) ? SYS_P1_OUT_MUX[5] : iodata4_o[2];
+ assign P1_OUTEN[5] = (FT1248MODE) ? SYS_P1_OUT_EN_MUX[5] : iodata4_e[2];
+ assign SYS_P1_IN[5] = P1_IN[5];
+ assign iodata4_i[2] = (FT1248MODE) ? 1'b1 : P1_IN[5];
+
+ assign P1_OUT[6] = (FT1248MODE) ? SYS_P1_OUT_MUX[6] : iodata4_o[3];
+ assign P1_OUTEN[6] = (FT1248MODE) ? SYS_P1_OUT_EN_MUX[6] : iodata4_e[3];
+ assign SYS_P1_IN[6] = P1_IN[6];
+ assign iodata4_i[3] = (FT1248MODE) ? 1'b1 : P1_IN[6];
+
+ assign P1_OUT[7] = SYS_P1_OUT_MUX[7];
+ assign P1_OUTEN[7] = SYS_P1_OUT_EN_MUX[7];
+ assign SYS_P1_IN[7] = P1_IN[7];
+
+// the rest of PORT1[3:0] is GPIO/AltFunction
+ assign SYS_P1_IN[15:8] = P1_IN[15:8];
+ assign P1_OUT[15:8] = SYS_P1_OUT_MUX[15:8];
+ assign P1_OUTEN[15:8] = SYS_P1_OUT_EN_MUX[15:8];
+
//--------------------------
// Interrupt Wiring
//--------------------------
- assign CPU_0_IRQ [3:0] = EXP_IRQ [3:0];
+ assign CPU_0_IRQ [ 3: 0] = SYS_APB_IRQ[ 3: 0]; // nanansocv1: EXP_IRQ[3:0];
assign CPU_0_IRQ [ 5: 4] = SYS_APB_IRQ[ 5: 4];
assign CPU_0_IRQ [ 6] = SYS_APB_IRQ[ 6] | SYS_GPIO0_ANY_IRQ;
assign CPU_0_IRQ [ 7] = SYS_APB_IRQ[ 7] | SYS_GPIO1_ANY_IRQ;
- assign CPU_0_IRQ [14: 8] = SYS_APB_IRQ[14: 8];
+ assign CPU_0_IRQ [10: 8] = SYS_APB_IRQ[10: 8];
+ assign CPU_0_IRQ [14:11] = EXP_IRQ[3:0]; // nanosocv1: SYS_APB_IRQ[14:11];
assign CPU_0_IRQ [15] = SYS_APB_IRQ[15] | DMAC_ANY_DONE | DMAC_ANY_ERROR;
assign CPU_0_IRQ [31:16] = SYS_APB_IRQ[31:16] | SYS_GPIO0_IRQ[15:0];
@@ -1303,4 +1581,4 @@ module nanosoc_system #(
.SYSTABLE_HREADYMUX(SYSTABLE_HREADY)
);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech
index 7572912..05781fa 160000
--- a/nanosoc/socdebug_tech
+++ b/nanosoc/socdebug_tech
@@ -1 +1 @@
-Subproject commit 7572912a3cde67880b0579db6f2e970ebaf2002d
+Subproject commit 05781fa353a8918c8206e9cc10b7e8aaef5203aa
diff --git a/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h b/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
index f5201f5..12260d1 100644
--- a/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
+++ b/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
@@ -77,10 +77,10 @@ typedef enum IRQn
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/
- EXP0_IRQn = 0, /*!< was UARTRX0_IRQn Interrupt */
- EXP1_IRQn = 1, /*!< was UARTTX0_IRQn Interrupt */
- EXP2_IRQn = 2, /*!< was UARTRX1_IRQn Interrupt */
- EXP3_IRQn = 3, /*!< was UARTTX1_IRQn Interrupt */
+ UARTRX0_IRQn = 0, /*!< was UARTRX0_IRQn Interrupt */
+ UARTTX0_IRQn = 1, /*!< was UARTTX0_IRQn Interrupt */
+ UARTRX1_IRQn = 2, /*!< was UARTRX1_IRQn Interrupt */
+ UARTTX1_IRQn = 3, /*!< was UARTTX1_IRQn Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
@@ -88,10 +88,10 @@ typedef enum IRQn
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
- EXPB_IRQn = 11, /*!< was IRQ11 - Unused */
- EXPC_IRQn = 12, /*!< was UART 0 Overflow Interrupt */
- EXPD_IRQn = 13, /*!< was UART 1 Overflow Interrupt */
- UARTOVF2_IRQn = 14, /*!< UART 2 Overflow Interrupt */
+ EXP0_IRQn = 11, /*!< was IRQ11 - Unused */
+ EXP1_IRQn = 12, /*!< was UART 0 Overflow Interrupt */
+ EXP2_IRQn = 13, /*!< was UART 1 Overflow Interrupt */
+ EXP3_IRQn = 14, /*!< UART 2 Overflow Interrupt */
DMA_IRQn = 15, /*!< PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
diff --git a/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s b/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
index 8a0bf63..c1d57cf 100644
--- a/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
+++ b/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
@@ -76,10 +76,10 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
- DCD EXP0_Handler ; was: UARTRX0_Handler
- DCD EXP1_Handler ; was: UARTTX0_Handler
- DCD EXP2_Handler ; was: UARTRX1_Handler
- DCD EXP3_Handler ; was: UARTTX1_Handler
+ DCD UARTRX0_Handler ; UARTRX0_Handler was: EXPA_Handler
+ DCD UARTTX0_Handler ; UARTTX0_Handler was: EXPB_Handler
+ DCD UARTRX1_Handler ; UARTRX1_Handler was: EXPC_Handler
+ DCD UARTTX1_Handler ; UARTTX1_Handler was: EXPD_Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
@@ -87,10 +87,10 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
- DCD EXPB_Handler ; was: Reserved
- DCD EXPC_Handler ; was: UARTOVF0_Handler Overflow Handler
- DCD EXPD_Handler ; was: UARTOVF1_Handler Overflow Handler
- DCD UARTOVF2_Handler ; UART 2 Overflow Handler
+ DCD EXP0_Handler ; was: Reserved
+ DCD EXP1_Handler ; was: UARTOVF0_Handler Overflow Handler
+ DCD EXP2_Handler ; was: UARTOVF1_Handler Overflow Handler
+ DCD EXP3_Handler ; was: UART 2 Overflow Handler
DCD DMA_Handler ; DMA handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
@@ -152,10 +152,10 @@ SysTick_Handler PROC
B .
ENDP
Default_Handler PROC
- EXPORT EXP0_Handler [WEAK]
- EXPORT EXP1_Handler [WEAK]
- EXPORT EXP2_Handler [WEAK]
- EXPORT EXP3_Handler [WEAK]
+ EXPORT UARTRX0_Handler [WEAK]
+ EXPORT UARTTX0_Handler [WEAK]
+ EXPORT UARTRX1_Handler [WEAK]
+ EXPORT UARTTX1_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
@@ -163,10 +163,10 @@ Default_Handler PROC
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
- EXPORT EXPB_Handler [WEAK]
- EXPORT EXPC_Handler [WEAK]
- EXPORT EXPD_Handler [WEAK]
- EXPORT UARTOVF2_Handler [WEAK]
+ EXPORT EXP0_Handler [WEAK]
+ EXPORT EXP1_Handler [WEAK]
+ EXPORT EXP2_Handler [WEAK]
+ EXPORT EXP3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
@@ -184,10 +184,14 @@ Default_Handler PROC
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
-EXP0_Handler
-EXP1_Handler
-EXP2_Handler
-EXP3_Handler
+;EXP0_Handler
+;EXP1_Handler
+;EXP2_Handler
+;EXP3_Handler
+UARTRX0_Handler
+UARTTX0_Handler
+UARTRX1_Handler
+UARTTX1_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
@@ -195,9 +199,10 @@ PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
-EXPB_Handler
-EXPC_Handler
-EXPD_Handler
+EXP0_Handler
+EXP1_Handler
+EXP2_Handler
+EXP3_Handler
UARTOVF2_Handler
DMA_Handler
PORT0_0_Handler
diff --git a/software/common/bootloader/bootloader.c b/software/common/bootloader/bootloader.c
index c1b3664..1d4f0b1 100644
--- a/software/common/bootloader/bootloader.c
+++ b/software/common/bootloader/bootloader.c
@@ -73,7 +73,6 @@ unsigned char UartPutc(unsigned char my_ch)
// return (my_ch);
while (((CMSDK_USRT2->STATE & 1)==1) && ((CMSDK_UART2->STATE & 1)==1)); // Wait if both Transmit Holding registers full
if ((CMSDK_USRT2->STATE & 1)==0) CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
- if ((CMSDK_UART2->STATE & 1)==0) CMSDK_UART2->DATA = my_ch; // write to transmit holding register
return (my_ch);
}
// Uart string output
diff --git a/software/common/demos/interrupt_demo.c b/software/common/demos/interrupt_demo.c
index d412301..f77d805 100644
--- a/software/common/demos/interrupt_demo.c
+++ b/software/common/demos/interrupt_demo.c
@@ -162,13 +162,13 @@ void UartExample(void)
// Ensure Interrupt is not pending
- NVIC_ClearPendingIRQ(EXP1_IRQn); // NVIC_ClearPendingIRQ(UARTTX0_IRQn);
- NVIC_ClearPendingIRQ(EXP2_IRQn); // NVIC_ClearPendingIRQ(UARTRX1_IRQn);
+ NVIC_ClearPendingIRQ(UARTTX1_IRQn);
+ NVIC_ClearPendingIRQ(UARTRX1_IRQn);
// Enable Interrupts
- NVIC_EnableIRQ(EXP1_IRQn); // NVIC_EnableIRQ(UARTTX0_IRQn);
- NVIC_EnableIRQ(EXP2_IRQn); // NVIC_EnableIRQ(UARTRX1_IRQn);
+ NVIC_EnableIRQ(UARTTX1_IRQn);
+ NVIC_EnableIRQ(UARTRX1_IRQn);
/* Initialize UART in cross over configuration
uint32_t CMSDK_uart_init(CMSDK_UART_TypeDef *CMSDK_UART,
@@ -184,8 +184,8 @@ void UartExample(void)
UART #0 - transmit
UART #1 - receive
*/
- CMSDK_uart_init(CMSDK_UART0, 0x200, 1, 0, 1, 0, 0, 0);
- CMSDK_uart_init(CMSDK_UART1, 0x200, 0, 1, 0, 1, 0, 0);
+// CMSDK_uart_init(CMSDK_UART0, 0x200, 1, 0, 1, 0, 0, 0);
+ CMSDK_uart_init(CMSDK_UART1, 0x200, 1, 1, 1, 1, 0, 0);
rx_count = 0;
tx_count = 0;
@@ -194,7 +194,7 @@ void UartExample(void)
/* Start first character transfer */
tx_count++;
- CMSDK_uart_SendChar(CMSDK_UART0, str_tx[0]); // send the character
+ CMSDK_uart_SendChar(CMSDK_UART1, str_tx[0]); // send the character
/* The rest of the transfers are handled by interrupts */
while(transmission_complete==0) // loop until transmission completed
@@ -206,8 +206,8 @@ void UartExample(void)
printf ("Received message : %s\n", str_rx);
- NVIC_DisableIRQ(EXP1_IRQn); // NVIC_DisableIRQ(UARTTX0_IRQn); -disable both UART0 TX and UART1 RX IRQs
- NVIC_DisableIRQ(EXP2_IRQn); // NVIC_DisableIRQ(UARTRX1_IRQn);
+ NVIC_DisableIRQ(UARTTX1_IRQn); //-disable both UART1 TX and UART1 RX IRQs
+ NVIC_DisableIRQ(UARTRX1_IRQn);
return;
}
@@ -403,23 +403,23 @@ else
// Handlers
// ----------------------------------------------------------
// ---------------------------------
-// UART 0 Interrupt service routines
+// UART 1 TX Interrupt service routines
// ---------------------------------
//
-void UARTTX0_Handler(void)
+void UARTTX1_Handler(void)
{
- CMSDK_uart_ClearTxIRQ(CMSDK_UART0); // clear TX IRQ
+ CMSDK_uart_ClearTxIRQ(CMSDK_UART1); // clear TX IRQ
// If the message output is not finished, output next character
if (tx_count < uart_str_length) {
- CMSDK_uart_SendChar(CMSDK_UART0,str_tx[tx_count]);
+ CMSDK_uart_SendChar(CMSDK_UART1,str_tx[tx_count]);
tx_count++;
}
}
// ---------------------------------
-// UART 1 Interrupt service routines
+// UART 1 RX Interrupt service routines
// ---------------------------------
void UARTRX1_Handler(void)
diff --git a/software/common/validation/apb_mux_tests.c b/software/common/validation/apb_mux_tests.c
index 57005e6..e877753 100644
--- a/software/common/validation/apb_mux_tests.c
+++ b/software/common/validation/apb_mux_tests.c
@@ -108,10 +108,10 @@ int main (void)
if ( ID_Check(&apb_dualtimer_id[0], CMSDK_DUALTIMER_BASE) == 1 ) err_code |= 1<<2;
puts ("3: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x40003000 ) == 1 ) err_code |= 1<<3;
- puts ("4: UART 0 - Not Implemented");
- if ( ID_Check(&blank_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4;
- puts ("5: UART 1 - Not Implemented");
- if ( ID_Check(&blank_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5;
+ puts ("4: UART 0 - mapped to USRT");
+ if ( ID_Check(&apb_uart_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4;
+ puts ("5: UART 1 - mapped to USRT");
+ if ( ID_Check(&apb_uart_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5;
puts ("6: UART 2");
if ( ID_Check(&apb_uart_id[0], CMSDK_UART2_BASE ) == 1 ) err_code |= 1<<6;
puts ("7: blank - default slave (generates slave error)");
diff --git a/software/common/validation/uart_driver_tests.c b/software/common/validation/uart_driver_tests.c
index 4f073b1..175133f 100644
--- a/software/common/validation/uart_driver_tests.c
+++ b/software/common/validation/uart_driver_tests.c
@@ -82,7 +82,7 @@ int main (void)
result |= Uart_Init();
result |= Uart_Buffull();
- result |= Uart_OR();
+// result |= Uart_OR();
result |= Uart_IRQ();
if (result == 0) {
@@ -168,6 +168,7 @@ int Uart_Buffull(void) //function for testing the Buffer full functi
i = 0; /* transmit character counter */
k = 0; /* receive character counter */
+
while((CMSDK_uart_GetTxBufferFull(CMSDK_UART0) == 0)){ //while the TX buffer is not full send it data to transmit
CMSDK_UART0->DATA = (uint32_t)transmit[i];
i++;
@@ -187,6 +188,8 @@ int Uart_Buffull(void) //function for testing the Buffer full functi
printf("** TEST FAILED **, Error Code: (0x%x)", err_code);
}
+ if(CMSDK_uart_GetRxBufferFull(CMSDK_UART1) == 1) CMSDK_uart_ReceiveChar(CMSDK_UART1);
+
i = 0;
while(k < 12){ //while received string is not the length of the original string
@@ -303,10 +306,11 @@ int Uart_IRQ(void){
char transmit[12] = "hello world";
puts("\nStage 4 IRQ\n");
+/*
puts("- Stage 4a Overrun IRQ\n");
- NVIC_EnableIRQ(EXPC_IRQn); //enable both UART0 and UART1 overflow IRQs
- NVIC_EnableIRQ(EXPD_IRQn);
+ NVIC_EnableIRQ(EXP0_IRQn); //enable both UART0 and UART1 overflow IRQs
+ NVIC_EnableIRQ(EXP1_IRQn);
while(uart_txorirq_counter <= 3) //repeat until 3 TX OR IRQs have occurred
{
@@ -326,6 +330,7 @@ int Uart_IRQ(void){
printf("** TEST FAILED ** UART RX Overrun Error, Error Code: (0x%x)", err_code);
}
else puts("UART RX Overrun Passed");
+*/
j = 0;
uart_data_received = 1; //set uart_data_received to one so that the first character is sent
@@ -338,14 +343,16 @@ int Uart_IRQ(void){
- when received flag has been set send the next character from transmit variable
- repeat until all characters have been received*/
- NVIC_EnableIRQ(EXP1_IRQn); //enable both UART0 TX and UART1 RX IRQs
- NVIC_EnableIRQ(EXP2_IRQn);
+ NVIC_EnableIRQ(UARTTX0_IRQn); //enable both UART0 TX and UART1 RX IRQs
+ NVIC_EnableIRQ(UARTRX1_IRQn);
while(j < 11) /*while j, the received character counter, is less than 11, the number of characters to be sent*/
{ /* uart_data_received and uart_data_sent are updated by TX and RX handlers */
if(uart_data_received){
- puts("UART TX IRQ ....data sent"); //if the data has been received (which is set in the
+//// puts("UART TX IRQ ....data sent"); //if the data has been received (which is set in the
+// printf("UART TX IRQ ....data sent.... "); //if the data has been received (which is set in the
CMSDK_uart_SendChar(CMSDK_UART0, transmit[i]); //RX IRQ) then send the character corresponding to
+// printf("....%c\n", transmit[i]);
i++; //the character counter, i, increment character counter
uart_data_received = 0;
}
@@ -365,10 +372,10 @@ int Uart_IRQ(void){
puts("** TEST FAILED ** Strings Do Not Match!");
}
- NVIC_DisableIRQ(EXPC_IRQn);
- NVIC_DisableIRQ(EXPD_IRQn); //disable all the enabled IRQs
- NVIC_DisableIRQ(EXP1_IRQn);
- NVIC_DisableIRQ(EXP2_IRQn);
+ NVIC_DisableIRQ(EXP0_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn); //disable all the enabled IRQs
+ NVIC_DisableIRQ(UARTTX0_IRQn);
+ NVIC_DisableIRQ(UARTRX1_IRQn);
if(!err_code) return 0;
else return 8;
diff --git a/software/common/validation/uart_tests.c b/software/common/validation/uart_tests.c
index 9811537..7beffea 100644
--- a/software/common/validation/uart_tests.c
+++ b/software/common/validation/uart_tests.c
@@ -141,14 +141,14 @@ int main (void)
result += simple_uart_baud_test();
result += uart_enable_ctrl_test(CMSDK_UART0);
result += uart_tx_rx_irq_test(CMSDK_UART0);
- result += uart_tx_rx_overflow_test(CMSDK_UART0);
+// result += uart_tx_rx_overflow_test(CMSDK_UART0);
puts("\nUART 1 for transmit, UART 0 for receive\n");
result += simple_uart_test(CMSDK_UART1, 16, DISPLAY);
result += uart_enable_ctrl_test(CMSDK_UART1);
result += uart_tx_rx_irq_test(CMSDK_UART1);
- result += uart_tx_rx_overflow_test(CMSDK_UART1);
+// result += uart_tx_rx_overflow_test(CMSDK_UART1);
puts("\nUART 2 interrupt connectivity test\n");
result += uart2_interrupt_test();
@@ -558,7 +558,7 @@ int uart_enable_ctrl_test(CMSDK_UART_TypeDef *CMSDK_UART)
return(return_val);
}
/* --------------------------------------------------------------- */
-/* UART tx & rx interrupt test */
+/* UART tx & rx interrupt test */
/* --------------------------------------------------------------- */
int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART)
@@ -596,14 +596,14 @@ int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART)
uart1_irq_expected=0;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(UARTTX0_IRQn);
}
if (CMSDK_UART==CMSDK_UART1){
uart0_irq_expected=0;
uart1_irq_expected=1;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(UARTTX1_IRQn);
}
TX_UART->CTRL = UART_CTRL_TXEN | UART_CTRL_TXIRQEN;
@@ -640,14 +640,14 @@ int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART)
uart1_irq_expected=0;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(UARTTX0_IRQn);
}
if (CMSDK_UART==CMSDK_UART1){
uart0_irq_expected=0;
uart1_irq_expected=0;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(UARTTX1_IRQn);
}
TX_UART->CTRL = UART_CTRL_TXEN; /* No interrupt generation */
@@ -679,14 +679,14 @@ int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART)
uart1_irq_expected=1;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(UARTRX1_IRQn);
}
if (CMSDK_UART==CMSDK_UART1){
uart0_irq_expected=1;
uart1_irq_expected=0;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXP0_IRQn);
+ NVIC_EnableIRQ(UARTRX0_IRQn);
}
TX_UART->CTRL = UART_CTRL_TXEN ; /* No interrupt generation */
@@ -748,10 +748,10 @@ int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART)
while ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
ctmp=RX_UART->DATA;
}
- NVIC_DisableIRQ(EXP0_IRQn);
- NVIC_DisableIRQ(EXP3_IRQn);
- NVIC_DisableIRQ(EXP1_IRQn);
- NVIC_DisableIRQ(EXP3_IRQn);
+ NVIC_DisableIRQ(UARTRX0_IRQn);
+ NVIC_DisableIRQ(UARTTX0_IRQn);
+ NVIC_DisableIRQ(UARTRX1_IRQn);
+ NVIC_DisableIRQ(UARTTX1_IRQn);
if (err_code != 0) {
printf ("ERROR : uart interrupt enable failed (0x%x)\n", err_code);
@@ -848,14 +848,14 @@ int uart_tx_rx_overflow_test(CMSDK_UART_TypeDef *CMSDK_UART)
uart1_irq_expected=0;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXPC_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
}
if (CMSDK_UART==CMSDK_UART1){
uart0_irq_expected=0;
uart1_irq_expected=1;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXPD_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
}
__DSB();
@@ -871,8 +871,8 @@ int uart_tx_rx_overflow_test(CMSDK_UART_TypeDef *CMSDK_UART)
TX_UART->CTRL = UART_CTRL_TXEN ; /* No interrupt generation */
RX_UART->CTRL = UART_CTRL_RXEN ; /* No interrupt generation */
- NVIC_DisableIRQ(EXPC_IRQn);
- NVIC_DisableIRQ(EXPD_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
uart0_irq_expected = 0;
uart1_irq_expected = 0;
@@ -900,14 +900,14 @@ int uart_tx_rx_overflow_test(CMSDK_UART_TypeDef *CMSDK_UART)
uart1_irq_expected=1;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXPD_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
}
if (CMSDK_UART==CMSDK_UART1){
uart0_irq_expected=1;
uart1_irq_expected=0;
uart0_irq_occurred=0;
uart1_irq_occurred=0;
- NVIC_EnableIRQ(EXPC_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
}
__DSB();
@@ -933,8 +933,8 @@ int uart_tx_rx_overflow_test(CMSDK_UART_TypeDef *CMSDK_UART)
ctmp=RX_UART->DATA;
}
- NVIC_DisableIRQ(EXPC_IRQn);
- NVIC_DisableIRQ(EXPD_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
if (err_code != 0) {
printf ("ERROR : uart overflow test failed (0x%x)\n", err_code);
@@ -969,7 +969,7 @@ int uart2_interrupt_test(void){
NVIC_DisableIRQ(UARTTX2_IRQn);
puts ("\n- UART 2 TX overflow IRQ");
- NVIC_EnableIRQ(UARTOVF2_IRQn);
+ NVIC_EnableIRQ(EXP3_IRQn);
CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_TXOVRIRQEN | UART_CTRL_HIGHSPEEDTX;
CMSDK_UART2->DATA = '.';
CMSDK_UART2->DATA = '.';
@@ -977,7 +977,7 @@ int uart2_interrupt_test(void){
for (i=0; i<3;i++){ __ISB(); } /* small delay */
if (uart2_irq_occurred==0) { err_code += (1<<1);}
uart2_irq_occurred = 0;
- NVIC_DisableIRQ(UARTOVF2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
puts ("\n- UART 2 RX IRQ");
/* UART 2 RXD is shared with GPIO1[4] */
@@ -996,20 +996,20 @@ int uart2_interrupt_test(void){
uart2_irq_occurred = 0;
NVIC_DisableIRQ(UARTRX2_IRQn);
- puts ("\n- UART 2 RX overflow IRQ");
- NVIC_EnableIRQ(UARTOVF2_IRQn);
- CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_RXEN | UART_CTRL_RXOVRIRQEN | UART_CTRL_HIGHSPEEDTX;
- /* First character */
- CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
- for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
- CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
- delay_for_character();
- /* Second character */
- CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
- for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
- CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
- delay_for_character();
- if (uart2_irq_occurred==0) { err_code += (1<<4);}
+// puts ("\n- UART 2 RX overflow IRQ");
+// NVIC_EnableIRQ(EXP3_IRQn);
+// CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_RXEN | UART_CTRL_RXOVRIRQEN | UART_CTRL_HIGHSPEEDTX;
+// /* First character */
+// CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
+// for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
+// CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
+// delay_for_character();
+// /* Second character */
+// CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
+// for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
+// CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
+// delay_for_character();
+// if (uart2_irq_occurred==0) { err_code += (1<<4);}
/* Remove receive data in buffer */
while ((CMSDK_UART2->STATE & UART_STATE_RXFULL)!=0) {
@@ -1017,7 +1017,7 @@ int uart2_interrupt_test(void){
}
/* clear up */
uart2_irq_occurred = 0;
- NVIC_DisableIRQ(UARTOVF2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_HIGHSPEEDTX;
CMSDK_GPIO1->OUTENABLECLR = (1<<4);
@@ -1027,8 +1027,10 @@ int uart2_interrupt_test(void){
if (err_code != 0) {
- printf ("ERROR : uart overflow test failed (0x%x)\n", err_code);
- return_val =1;
+// printf ("ERROR : uart overflow test failed (0x%x)\n", err_code);
+// return_val =1;
+ printf ("NOTE : uart overflow test failed - nIRQ not wired (0x%x)\n", err_code);
+ return_val =0;
err_code = 0;
}
@@ -1052,8 +1054,10 @@ void delay_for_character(void)
int uart0_id_check(void)
{
if ((HW32_REG(CMSDK_UART0_BASE + 0xFE0) != 0x21) ||
- (HW32_REG(CMSDK_UART0_BASE + 0xFE4) != 0xB8))
+ (HW32_REG(CMSDK_UART0_BASE + 0xFE4) != 0xB8)) {
+ printf ("CMSDK_UART0_BASE + 0xFE0 = %02x, expected 0x21\n", HW32_REG(CMSDK_UART0_BASE + 0xFE0));
return 1; /* part ID does not match */
+ }
else
return 0;
}
@@ -1061,8 +1065,10 @@ else
int uart1_id_check(void)
{
if ((HW32_REG(CMSDK_UART1_BASE + 0xFE0) != 0x21) ||
- (HW32_REG(CMSDK_UART1_BASE + 0xFE4) != 0xB8))
+ (HW32_REG(CMSDK_UART1_BASE + 0xFE4) != 0xB8)) {
+ printf ("CMSDK_UART1_BASE + 0xFE0 = %02x, expected 0x21\n", HW32_REG(CMSDK_UART1_BASE + 0xFE0));
return 1; /* part ID does not match */
+ }
else
return 0;
}
diff --git a/testcodes/apb_mux_tests/apb_mux_tests.hex b/testcodes/apb_mux_tests/apb_mux_tests.hex
index 0cf2e36..a2ff325 100644
--- a/testcodes/apb_mux_tests/apb_mux_tests.hex
+++ b/testcodes/apb_mux_tests/apb_mux_tests.hex
@@ -1028,7 +1028,7 @@ EA
FB
DA
49
-D2
+DB
48
FF
F7
@@ -1042,15 +1042,15 @@ D1
20
04
43
-D7
+D8
A0
00
F0
DF
FB
-DD
+DE
49
-CC
+D5
48
FF
F7
@@ -1064,15 +1064,15 @@ D1
20
04
43
-DA
+DB
A0
00
F0
D4
FB
-DB
-49
DC
+49
+D0
48
FF
F7
@@ -1202,7 +1202,7 @@ F0
FB
F6
49
-BB
+AF
48
FF
F7
@@ -1886,26 +1886,30 @@ AC
20
2D
20
-4E
-6F
-74
-20
-49
6D
+61
+70
70
-6C
-65
-6D
-65
-6E
-74
65
64
+20
+74
+6F
+20
+55
+53
+52
+54
+00
00
00
40
00
40
+6C
+0D
+00
+00
35
3A
20
@@ -1918,21 +1922,21 @@ AC
20
2D
20
-4E
-6F
-74
-20
-49
6D
+61
+70
70
-6C
-65
-6D
-65
-6E
-74
65
64
+20
+74
+6F
+20
+55
+53
+52
+54
+00
00
00
50
@@ -1954,10 +1958,6 @@ AC
60
00
40
-6C
-0D
-00
-00
37
3A
20
diff --git a/testcodes/bootloader/bootloader.hex b/testcodes/bootloader/bootloader.hex
index 8363b23..c8c4811 100644
--- a/testcodes/bootloader/bootloader.hex
+++ b/testcodes/bootloader/bootloader.hex
@@ -2,16 +2,16 @@
04
00
30
-29
-03
+95
+02
00
10
-31
-03
+9D
+02
00
10
-33
-03
+9F
+02
00
10
00
@@ -42,8 +42,8 @@
00
00
00
-35
-03
+A1
+02
00
10
00
@@ -54,140 +54,140 @@
00
00
00
-37
-03
+A3
+02
00
10
-39
-03
+A5
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
-3B
-03
+A7
+02
00
10
00
@@ -250,11 +250,11 @@ AB
43
18
47
-D0
+3C
02
00
00
-F0
+5C
02
00
00
@@ -324,8 +324,8 @@ B5
BD
00
F0
-0F
-F9
+C5
+F8
11
46
FF
@@ -334,12 +334,12 @@ F7
FF
00
F0
-68
+59
F8
00
F0
-27
-F9
+DD
+F8
03
B4
FF
@@ -350,8 +350,8 @@ FF
BC
00
F0
-2D
-F9
+E3
+F8
00
00
00
@@ -366,61 +366,71 @@ F9
47
00
00
-41
-21
-53
+29
48
+00
+22
+82
+60
+29
49
01
-01
61
01
21
81
60
-51
-48
-81
-60
-51
+28
49
+8A
+60
+03
+22
+8A
+60
+27
+4B
20
-20
-88
+22
+9A
61
-70
-47
-4E
-49
4A
68
D2
07
-FC
+01
D1
-4A
+23
+22
+0A
+60
+41
68
-D2
+C9
07
-00
+01
D1
-08
+7E
+21
+01
60
70
47
+1D
4A
+1E
49
-03
-78
-00
-2B
-09
+4B
+68
+DB
+07
+02
D0
-4A
+53
68
-D2
+DB
07
-FC
+F9
D1
4A
68
@@ -428,104 +438,50 @@ D2
07
00
D1
-0B
+08
60
-40
-1C
-00
-2B
-F2
-D1
70
47
-10
+30
B5
-44
-4C
-21
-68
-41
-48
-00
-29
-0A
-D0
-42
-A3
-1A
-78
-00
-2A
-21
-D0
-41
-68
-C9
-07
-FC
-D1
-41
-68
-C9
-07
-17
-D0
-17
-E0
-42
-A3
-1A
+04
+46
+25
78
00
-2A
-09
-D0
-41
-68
-C9
-07
-FC
-D1
-41
-68
-C9
-07
-00
-D1
+2D
02
-60
-5B
+D0
+28
+46
+FF
+F7
+EB
+FF
+64
1C
00
-2A
-F2
-D1
-04
-22
-41
-68
-C9
-07
-FC
+2D
+F6
D1
-41
+30
+BD
+10
+B5
+14
+4C
+20
68
-C9
-07
00
-D1
-02
-60
-FE
-E7
-02
-60
-5B
-1C
-00
-2A
-DA
-D1
+28
+0B
+D0
+13
+A0
+FF
+F7
+EC
+FF
00
20
20
@@ -540,172 +496,52 @@ F3
8F
FF
F7
-A2
+B8
FF
10
BD
-10
-B5
-41
-21
-26
-48
-49
-01
-01
-61
-01
-21
-81
-60
-24
-48
-81
-60
-24
-4A
-20
-21
-91
-61
-30
-A3
-1A
-78
-00
-2A
-09
-D0
-41
-68
-C9
-07
-FC
-D1
-41
-68
-C9
-07
-00
-D1
-02
-60
-5B
-1C
-00
-2A
-F2
-D1
-1D
-4C
-21
-68
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diff --git a/testcodes/dma_tests/dma_tests.hex b/testcodes/dma_tests/dma_tests.hex
index 0a3b4a1..c6226ee 100644
--- a/testcodes/dma_tests/dma_tests.hex
+++ b/testcodes/dma_tests/dma_tests.hex
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@@ -3098,13 +3152,59 @@ D1
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D5
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@@ -3112,24 +3212,48 @@ C0
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@@ -3138,6 +3262,18 @@ E0
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70
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@@ -3236,7 +3372,7 @@ FF
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FF
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@@ -3482,8 +3618,8 @@ B5
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40
1C
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FF
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BD
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FF
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FE
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@@ -3738,8 +3874,8 @@ BD
BD
00
00
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FF
01
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FF
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BD
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00
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00
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00
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diff --git a/testcodes/dualtimer_demo/dualtimer_demo.hex b/testcodes/dualtimer_demo/dualtimer_demo.hex
index 5b1e313..b6cb43d 100644
--- a/testcodes/dualtimer_demo/dualtimer_demo.hex
+++ b/testcodes/dualtimer_demo/dualtimer_demo.hex
@@ -250,12 +250,12 @@ AB
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18
47
-C0
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00
00
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00
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F0
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46
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F0
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B4
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F0
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F0
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1C
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20
F8
BD
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FF
7D
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00
F0
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6D
1C
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20
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00
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1C
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4D
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FF
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FF
7D
20
@@ -974,7 +974,7 @@ FF
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00
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1C
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20
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00
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6D
1C
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00
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20
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00
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1C
0A
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4F
01
@@ -1130,7 +1130,7 @@ FE
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6D
1C
@@ -1208,7 +1208,7 @@ BA
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48
00
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7F
1C
@@ -1256,7 +1256,7 @@ BD
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48
00
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1C
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00
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1C
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20
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00
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7F
1C
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64
20
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00
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FC
7F
1C
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20
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00
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1C
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00
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6D
1C
0A
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00
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1C
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1C
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00
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20
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1C
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53
A0
00
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46
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00
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@@ -3984,7 +3984,7 @@ E0
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BD
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6B
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BD
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47
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00
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BD
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@@ -4536,24 +4636,48 @@ C0
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00
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@@ -4562,6 +4686,18 @@ E0
10
01
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70
47
00
@@ -4574,7 +4710,7 @@ B5
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FF
F7
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FF
40
1C
@@ -4594,7 +4730,7 @@ D1
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FF
F7
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FF
10
BD
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FF
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FF
60
BC
@@ -4690,7 +4826,7 @@ C0
46
FE
F7
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FF
10
BD
@@ -4794,8 +4930,8 @@ BD
24
0A
00
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00
00
00
@@ -4810,8 +4946,8 @@ DC
01
00
00
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00
00
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@@ -4843,9 +4979,9 @@ F4
00
00
00
-E1
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00
00
00
diff --git a/testcodes/gpio_driver_tests/gpio_driver_tests.hex b/testcodes/gpio_driver_tests/gpio_driver_tests.hex
index 92b805e..7da9c8a 100644
--- a/testcodes/gpio_driver_tests/gpio_driver_tests.hex
+++ b/testcodes/gpio_driver_tests/gpio_driver_tests.hex
@@ -250,11 +250,11 @@ AB
43
18
47
-50
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15
00
00
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15
00
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D1
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BD
00
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01
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1F
BD
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11
46
FF
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48
01
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FD
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22
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01
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01
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01
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98
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00
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01
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48
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00
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6D
1C
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@@ -766,7 +766,7 @@ AA
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00
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00
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00
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01
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80
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ED
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0B
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4E
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00
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46
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00
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00
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FF
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6A
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00
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1C
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@@ -1122,8 +1122,8 @@ DB
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00
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6A
01
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@@ -1238,7 +1238,7 @@ CA
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@@ -1258,7 +1258,7 @@ FF
46
00
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1C
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6A
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6A
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FF
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FE
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@@ -1392,8 +1392,8 @@ C7
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00
F0
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00
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6A
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00
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6A
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FD
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00
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FD
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A0
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FC
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FC
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46
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FC
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48
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FC
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FC
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FC
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00
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46
00
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00
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46
EF
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FC
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@@ -2676,7 +2676,7 @@ D0
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FC
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25
@@ -2704,14 +2704,14 @@ E5
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00
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46
00
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FB
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46
@@ -2756,8 +2756,8 @@ D8
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2C
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00
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FC
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FC
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@@ -2934,11 +2934,11 @@ E3
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00
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@@ -3896,7 +3896,7 @@ BD
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00
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47
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00
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D2
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@@ -4284,24 +4384,48 @@ C0
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00
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@@ -4310,6 +4434,18 @@ E0
10
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68
08
@@ -4840,8 +4976,8 @@ FF
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FE
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28
08
@@ -4978,7 +5114,7 @@ B5
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FE
40
1C
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FE
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FF
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FD
00
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@@ -5294,7 +5430,7 @@ BD
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FB
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FE
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BD
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00
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16
00
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00
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00
00
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@@ -5747,9 +5883,9 @@ BD
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00
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00
00
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diff --git a/testcodes/hello/hello.hex b/testcodes/hello/hello.hex
index 1b445b1..b45557f 100644
--- a/testcodes/hello/hello.hex
+++ b/testcodes/hello/hello.hex
@@ -250,12 +250,12 @@ AB
43
18
47
-68
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02
00
00
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00
00
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46
FF
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00
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@@ -592,20 +692,48 @@ C0
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47
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FF
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FF
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@@ -690,8 +830,8 @@ BD
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00
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@@ -899,9 +1039,9 @@ BD
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diff --git a/testcodes/interrupt_demo/interrupt_demo.hex b/testcodes/interrupt_demo/interrupt_demo.hex
index 6b27dd3..f2c5d4d 100644
--- a/testcodes/interrupt_demo/interrupt_demo.hex
+++ b/testcodes/interrupt_demo/interrupt_demo.hex
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04
00
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-99
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0A
00
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00
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00
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@@ -532,15 +512,15 @@ D1
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diff --git a/testcodes/memory_tests/memory_tests.hex b/testcodes/memory_tests/memory_tests.hex
index 03f2378..a4eb285 100644
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diff --git a/testcodes/romtable_tests/romtable_tests.hex b/testcodes/romtable_tests/romtable_tests.hex
index 6c47143..83dcf62 100644
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diff --git a/testcodes/self_reset_demo/self_reset_demo.hex b/testcodes/self_reset_demo/self_reset_demo.hex
index 94436bc..6f91c15 100644
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diff --git a/testcodes/sleep_demo/sleep_demo.hex b/testcodes/sleep_demo/sleep_demo.hex
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diff --git a/testcodes/uart_driver_tests/uart_driver_tests.hex b/testcodes/uart_driver_tests/uart_driver_tests.hex
index 9d21a95..0ea7591 100644
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diff --git a/testcodes/uart_tests/uart_tests.hex b/testcodes/uart_tests/uart_tests.hex
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diff --git a/testcodes/watchdog_demo/watchdog_demo.hex b/testcodes/watchdog_demo/watchdog_demo.hex
index a8ee6b3..60a3d51 100644
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00
18
@@ -3251,9 +3387,9 @@ BC
00
00
00
-E1
-F5
-05
+1C
+4E
+0E
00
00
00
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 4fcef6a..e4ff4e7 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -68,15 +68,16 @@ module nanosoc_tb;
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
- wire debug_test_en1;
- wire debug_test_en2;
+ wire debug_test_en1; // UART2 output trace (CMSDK)
+ wire debug_test_en2; // FT1248 output trace (nanosoc V1)
+ wire debug_test_en3; // EXTIO output trace (nanosoc V2)
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
- assign debug_test_en = debug_test_en1 | debug_test_en2; // FT1248 or UART2 control
+ assign debug_test_en = debug_test_en1 | debug_test_en2 | debug_test_en3; // UART2, FT1248 or EXTIO
//-----------------------------------------
// System options
@@ -117,7 +118,7 @@ initial
`ifdef VCD_SIM
initial begin
$dumpfile("waves.vcd");
- $dumpvars(0,u_nanosoc_chip_pads);
+ $dumpvars(6,u_nanosoc_chip_pads);
end
`endif // VCD_SIM
@@ -204,7 +205,8 @@ initial begin
pullup(P1[ 4]);
pullup(P1[ 5]);
pullup(P1[ 6]);
- pullup(P1[ 7]);
+// pullup(P1[ 7]);
+ pulldown(P1[ 7]);
pullup(P1[ 8]);
pullup(P1[ 9]);
pullup(P1[10]);
@@ -214,6 +216,178 @@ initial begin
pullup(P1[14]);
pullup(P1[15]);
+`ifdef FAST_SIM
+ parameter FAST_LOAD = 1;
+`else
+ parameter FAST_LOAD = 0;
+`endif
+
+ // --------------------------------------------------------------------------------
+ // EXTIO8x4 stream interface - enabled when P1[7] is low
+ // default in previous testbenches was pullup (for FT1248, UART2)
+ //
+ // v1 mapping was: v2 config
+ // P1[0] - ft_miso_in ioreq1
+ // P1[1] - ft_clk_out ioreq2
+ // P1[2] - ft_miosio_io ioack
+ // P1[3] - ft_ssn_out iodata[0]
+ // P1[4] - uart2_rxd iodata[1]
+ // P1[5] - uart2_txd iodata[2]
+ // P1[6] - reserved (1) iodata[3]
+ // P1[7] - reserved (1) zero
+ // --------------------------------------------------------------------------------
+
+// 4-channel AXIS interface - Subordinate side
+ wire axis_rx0_tready;
+ wire axis_rx0_tvalid;
+ wire [7:0] axis_rx0_tdata8;
+ wire axis_rx1_tready;
+ wire axis_rx1_tvalid;
+ wire [7:0] axis_rx1_tdata8;
+ wire axis_tx0_tready;
+ wire axis_tx0_tvalid;
+ wire [7:0] axis_tx0_tdata8;
+ wire axis_tx1_tready;
+ wire axis_tx1_tvalid;
+ wire [7:0] axis_tx1_tdata8;
+// external io interface
+ tri [3:0] iodata4;
+ wire [3:0] iodata4_i;
+ wire [3:0] iodata4_o;
+ wire [3:0] iodata4_e;
+ wire [3:0] iodata4_t;
+ wire ioreq1;
+ wire ioreq2;
+ wire ioack;
+
+wire test_done;
+
+wire FT1248MODE = P1[7];
+wire end_sim = test_done & !FT1248MODE & !ioreq1 & !ioreq2 & !ioack;
+ always @(posedge PCLK)
+ if (end_sim) begin
+ $stop;
+ end
+
+extio8x4_axis_target u_extio8x4_axis_target
+ (
+ .clk ( CLK ),
+ .resetn ( NRST ),
+ .testmode ( TEST ),
+// RX 4-channel AXIS interface
+ .axis_rx0_tready ( axis_rx0_tready ),
+ .axis_rx0_tvalid ( axis_rx0_tvalid ),
+ .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+ .axis_rx1_tready ( axis_rx1_tready ),
+ .axis_rx1_tvalid ( axis_rx1_tvalid ),
+ .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+ .axis_tx0_tready ( axis_tx0_tready ),
+ .axis_tx0_tvalid ( axis_tx0_tvalid ),
+ .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+ .axis_tx1_tready ( axis_tx1_tready ),
+ .axis_tx1_tvalid ( axis_tx1_tvalid ),
+ .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+ .iodata4_i ( iodata4_i ),
+ .iodata4_o ( iodata4_o ),
+ .iodata4_e ( iodata4_e ),
+ .iodata4_t ( iodata4_t ),
+ .ioreq1_a ( ioreq1 ),
+ .ioreq2_a ( ioreq2 ),
+ .ioack_o ( ioack )
+ );
+
+// tristate buffer emulation
+ assign ioreq1 = FT1248MODE ? 1'b0 : P1[0];
+ assign ioreq2 = FT1248MODE ? 1'b0 : P1[1];
+ bufif0 #1 (P1[2], ioack, FT1248MODE);
+ bufif0 #1 (P1[3], iodata4_o[0], (iodata4_t[0] | FT1248MODE));
+ bufif0 #1 (P1[4], iodata4_o[1], (iodata4_t[1] | FT1248MODE));
+ bufif0 #1 (P1[5], iodata4_o[2], (iodata4_t[2] | FT1248MODE));
+ bufif0 #1 (P1[6], iodata4_o[3], (iodata4_t[3] | FT1248MODE));
+ assign iodata4_i = {4{FT1248MODE}} | P1[6:3];
+
+`ifndef COCOTB_SIM
+
+ nanosoc_axi_stream_io_8_txd_from_file #(
+ .TXDFILENAME(ADP_FILENAME),
+// .CODEFILENAME("null.hex"),
+ .FAST_LOAD(FAST_LOAD)
+ ) u_nanosoc_axi_stream_io_adp_txd_from_file (
+ .aclk (CLK),
+ .aresetn (NRST),
+ .txd8_ready (axis_rx0_tready),
+ .txd8_valid (axis_rx0_tvalid),
+ .txd8_data (axis_rx0_tdata8)
+ );
+
+`ifndef COCOTB_SIM
+ nanosoc_axi_stream_io_8_rxd_to_file#(
+ .RXDFILENAME("logs/extadp_in.log")
+ ) u_nanosoc_axi_stream_io_8_adprxd_to_file (
+ .aclk (CLK),
+ .aresetn (NRST),
+ .eof_received ( ),
+ .rxd8_ready ( ), //axis_rx0_tready),
+ .rxd8_valid (axis_rx0_tvalid & axis_rx0_tready),
+ .rxd8_data (axis_rx0_tdata8)
+ );
+`endif
+
+/*
+ nanosoc_axi_stream_io_8_txd_from_file #(
+ .TXDFILENAME(ADP_FILENAME),
+// .CODEFILENAME("null.hex"),
+ .FAST_LOAD(FAST_LOAD)
+ ) u_nanosoc_axi_stream_io_dat_txd_from_file (
+ .aclk (CLK),
+ .aresetn (NRST),
+ .txd8_ready (axis_rx1_tready),
+ .txd8_valid (axis_rx1_tvalid),
+ .txd8_data (axis_rx1_tdata8)
+ );
+*/
+
+ nanosoc_axi_stream_io_8_rxd_to_file#(
+ .RXDFILENAME("logs/extadp_out.log"),
+ .VERBOSE(0)
+ ) u_nanosoc_axi_stream_io_stream_adp_rxd_to_file (
+ .aclk (CLK),
+ .aresetn (NRST),
+ .eof_received (test_done),
+ .rxd8_ready (axis_tx0_tready),
+ .rxd8_valid (axis_tx0_tvalid),
+ .rxd8_data (axis_tx0_tdata8)
+ );
+
+ soclabs_axis8_capture #(.LOGFILENAME("logs/extio_adp_out.log"))
+ u_soclabs_axis8_capture1(
+ .RESETn (NRST),
+ .CLK (CLK),
+ .RXD8_READY ( ),
+ .RXD8_VALID (axis_tx0_tvalid & axis_tx0_tready),
+ .RXD8_DATA (axis_tx0_tdata8),
+ .DEBUG_TESTER_ENABLE (debug_test_en3),
+ .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
+ .AUXCTRL ()
+ );
+
+
+ nanosoc_axi_stream_io_8_rxd_to_file#(
+ .RXDFILENAME("logs/extdat_out.log")
+ ) u_nanosoc_axi_stream_io_extdata_8_rxd_to_file (
+ .aclk (CLK),
+ .aresetn (NRST),
+ .eof_received ( ),
+ .rxd8_ready ( ), //axis_tx1_tready),
+ .rxd8_valid (axis_tx1_tvalid & axis_tx1_tready),
+ .rxd8_data (axis_tx1_tdata8)
+ );
+
+assign axis_tx1_tready = axis_rx1_tready;
+assign axis_rx1_tvalid = axis_tx1_tvalid;
+assign axis_rx1_tdata8 = axis_tx1_tdata8;
+`endif
// --------------------------------------------------------------------------------
// UART output capture
@@ -246,7 +420,8 @@ initial begin
wire baudx16_clk = bauddiv[8]; //prefer:// !baudclken;
- wire UARTXD = P1[5];
+/// wire UARTXD = P1[5];
+ wire UARTXD = P1[5] | FT1248MODE; // high if in EXTIO mode
reg UARTXD_del;
always @(negedge NRST or posedge baudx16_clk)
if (!NRST)
@@ -286,7 +461,7 @@ reg baud_clk_del;
.RESETn (NRST),
.CLK (uart_clk), //PCLK),
.RXD (UARTXD), // UART 2 use for StdOut
- .DEBUG_TESTER_ENABLE (debug_test_en2),
+ .DEBUG_TESTER_ENABLE (debug_test_en1),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
@@ -296,16 +471,32 @@ reg baud_clk_del;
// FTDI IO capture
// --------------------------------------------------------------------------------
- // UART connection cross over for UART test
- // assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
- // assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
+ // UART connection
+/// assign P1[4] = P1[5]; // loopback UART2
+
+ bufif1 #1 (P1[4], P1[5], FT1248MODE);
- assign P1[4] = P1[5]; // loopback UART2
+/// wire ft_clk_out = P1[1];
+/// wire ft_miso_in;
+/// assign P1[0] = ft_miso_in;
+/// wire ft_ssn_out = P1[3];
- wire ft_clk_out = P1[1];
+ wire ft_clk_out;
wire ft_miso_in;
- assign P1[0] = ft_miso_in;
- wire ft_ssn_out = P1[3];
+ wire ft_ssn_out;
+
+ assign ft_clk_out = (FT1248MODE) ? P1[1] : 1'b0;
+ bufif1 #1 (P1[0], ft_miso_in, FT1248MODE);
+ assign ft_ssn_out = (FT1248MODE) ? P1[3] : 1'b1;
+
+ wire ft_miosio_o;
+ wire ft_miosio_z;
+ wire ft_miosio_i;
+/// assign ft_miosio_i = P1[2]; // & ft_miosio_z;
+/// assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
+ assign ft_miosio_i = (FT1248MODE) ? P1[2] : 1'b0; // & ft_miosio_z;
+ bufif1 #1 (P1[2], ft_miosio_o, (FT1248MODE & !ft_miosio_z));
+
//
// AXI stream io testing
@@ -319,15 +510,10 @@ reg baud_clk_del;
wire rxd8_tvalid;
wire [7:0] rxd8_tdata ;
-`ifdef FAST_SIM
- parameter FAST_LOAD = 1;
-`else
- parameter FAST_LOAD = 0;
-`endif
-
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
.TXDFILENAME(ADP_FILENAME),
+// .CODEFILENAME("null.hex"),
.FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_8_txd_from_file (
.aclk (CLK),
@@ -338,11 +524,6 @@ reg baud_clk_del;
);
`endif
- wire ft_miosio_o;
- wire ft_miosio_z;
- wire ft_miosio_i = P1[2]; // & ft_miosio_z;
- assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
-
nanosoc_ft1248x1_to_axi_streamio_v1_0 u_nanosoc_ft1248x1_to_axi_streamio_v1_0
(
.ft_clk_i (ft_clk_out),
@@ -367,6 +548,7 @@ reg baud_clk_del;
) u_nanosoc_axi_stream_io_8_rxd_to_file (
.aclk (CLK),
.aresetn (NRST),
+ .eof_received ( ),
.rxd8_ready (rxd8_tready),
.rxd8_valid (rxd8_tvalid),
.rxd8_data (rxd8_tdata)
@@ -381,7 +563,7 @@ nanosoc_track_tb_iostream
.rxd8_ready (rxd8_tready),
.rxd8_valid (rxd8_tvalid),
.rxd8_data (rxd8_tdata),
- .DEBUG_TESTER_ENABLE (debug_test_en1),
+ .DEBUG_TESTER_ENABLE (debug_test_en2),
.AUXCTRL ( ),
.SIMULATIONEND( )
);
@@ -410,7 +592,7 @@ nanosoc_ft1248x1_track
.RESETn (NRST),
.CLK (ft_clk2uart),
.RXD (ft_rxd2uart),
- .DEBUG_TESTER_ENABLE (debug_test_en1),
+ .DEBUG_TESTER_ENABLE ( ), //debug_test_en2), //driven by u_nanosoc_track_tb_iostream
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
diff --git a/verif/tb/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
index cdf1ee1..b0b8597 100644
--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -113,6 +113,7 @@ SROM_Ax32
.VSS (VSS),
.VDDACC (VDDACC),
`endif
+ .SE (1'b0),
.CLK (CLK), // input
.TEST (TEST), // output
.NRST (NRST), // active low reset
@@ -337,6 +338,7 @@ reg baud_clk_del;
) u_nanosoc_axi_stream_io_8_rxd_to_file (
.aclk (CLK),
.aresetn (NRST),
+ .eof_received ( ),
.rxd8_ready (rxd8_tready),
.rxd8_valid (rxd8_tvalid),
.rxd8_data (rxd8_tdata)
diff --git a/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v b/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
index 9c28431..1ba2b85 100644
--- a/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+++ b/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
@@ -21,6 +21,7 @@ module nanosoc_axi_stream_io_8_rxd_to_file
(
input wire aclk,
input wire aresetn,
+ output wire eof_received,
output wire rxd8_ready,
input wire rxd8_valid,
input wire [7:0] rxd8_data
@@ -40,7 +41,9 @@ module nanosoc_axi_stream_io_8_rxd_to_file
reg nxt_end_simulation;
reg reg_end_simulation;
-
+
+assign eof_received = nxt_end_simulation;
+
initial
begin
ready <= 0;
@@ -62,8 +65,10 @@ module nanosoc_axi_stream_io_8_rxd_to_file
ch = (rxd8_data & 8'hff);
if (ch==8'h04) // Stop simulation if 0x04 is received
nxt_end_simulation <= 1'b1;
- else
+ else begin
$fwrite(fd, "%c", ch);
+ if (VERBOSE) $write("%c", ch);
+ end
end
$write("** %m : log file closed after stream RX terminated **\n");
$fclose(fd);
diff --git a/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v b/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
index eb37044..2be4004 100644
--- a/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+++ b/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
@@ -147,7 +147,10 @@ localparam BUFSIZE = (64 * 1024);
$write("** %m : input file length measured as: %d **\n", flen);
if (flen > 0) flen=flen-1; // correct for extra char count(???)
// now output the entire adp buffer to the stream
- flen = flen + clen+25;
+ if (FAST_LOAD==0)
+ flen = flen + clen+25;
+ else
+ flen = flen + clen+17;
fp = 0;
valid <= 0;
begin
diff --git a/verif/trace/verilog/soclabs_axis8_capture.v b/verif/trace/verilog/soclabs_axis8_capture.v
new file mode 100644
index 0000000..b98a00b
--- /dev/null
+++ b/verif/trace/verilog/soclabs_axis8_capture.v
@@ -0,0 +1,274 @@
+//-----------------------------------------------------------------------------
+// soclabs 8-bit-axi-character stream capture
+// based on Arm UART RXD capture with file logging adapted from Arm CMSDK Uart Capture
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : A device to capture serial data
+//-----------------------------------------------------------------------------
+// This module assume CLK is same frequency as baud rate.
+// In the example UART a test mode is used to enable data output as maximum
+// speed (PCLK). In such case we can connect CLK signal directly to PCLK.
+// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
+// accordingly as well.
+//
+// This module stop the simulation when character 0x04 is received.
+// An output called SIMULATION_END is set for 1 cycle before simulation is
+// terminated to allow other testbench component like profiler (if any)
+// to output reports before the simulation stop.
+//
+// This model also support ESCAPE (0x1B, decimal 27) code sequence
+// ESC - 0x10 - XY Capture XY to AUXCTRL output
+// ESC - 0x11 Set DEBUG_TESTER_ENABLE to 1
+// ESC - 0x12 Clear DEBUG_TESTER_ENABLE to 0
+
+
+module soclabs_axis8_capture
+ #(parameter LOGFILENAME = "soc_capture.log",
+ parameter VERBOSE = 0)
+ (
+ input wire RESETn, // Power on reset
+ input wire CLK, // Clock (baud rate)
+ input wire RXD, // Received data
+
+ output wire RXD8_READY,
+ input wire RXD8_VALID,
+ input wire [7:0] RXD8_DATA,
+
+ output wire SIMULATIONEND, // Simulation end indicator
+ output wire DEBUG_TESTER_ENABLE, // Enable debug tester
+ output wire [7:0] AUXCTRL); // Auxiliary control
+
+ reg [8:0] rx_shift_reg;
+ wire [8:0] nxt_rx_shift;
+ reg [6:0] string_length;
+ reg [7:0] tube_string [127:0];
+ reg [7:0] text_char;
+ integer i;
+ reg nxt_end_simulation;
+ reg reg_end_simulation;
+ wire char_received;
+ reg reg_esc_code_mode; // Escape code mode
+ reg reg_aux_ctrl_mode; // Auxiliary control capture mode
+ reg [7:0] reg_aux_ctrl; // Registered Auxiliary control
+ reg reg_dbgtester_enable;
+
+ integer mcd; // channel descriptor for log file output
+ reg [40*8-1:0] log_file; // File name can't be > *40* characters
+
+
+assign RXD8_READY = rx_shift_reg[0]; // ready except for a cycle processing
+
+`define SimSTDOUT 32'h00000001
+ initial
+ begin
+ $timeformat(-9, 0, " ns", 14);
+ log_file = LOGFILENAME;
+ mcd = $fopen(log_file);
+ mcd = mcd | `SimSTDOUT; // always echo to console
+ if(mcd == 0) begin
+ $fwrite(mcd,"soclabs_axis8_capture: Error, zero returned in response to $fopen\n");
+ $finish(2);
+ end
+ $fwrite(mcd,"soclabs_axis8_capture: Generating output file %0s using MCD %x @ %m\n",
+ log_file, mcd);
+ end
+
+ // Receive shift register
+ assign nxt_rx_shift = {RXD,rx_shift_reg[8:1]};
+ assign char_received = (rx_shift_reg[0]==1'b0);
+/*
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ rx_shift_reg <= {9{1'b0}};
+ else
+ if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
+ rx_shift_reg <= {9{1'b1}};
+ else
+ rx_shift_reg <= nxt_rx_shift;
+ end
+*/
+
+// ARM design wants valid char in rx_shift_reg[9:1]
+// and a zero in rx_shift_reg[0] to indicate valid start bit (so preset back to 1 after a clock cycle)
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ rx_shift_reg <= {9{1'b1}};
+ else if (rx_shift_reg[0]== 1'b0) // if LSB zero, preset a clock cycle later
+ rx_shift_reg <= {9{1'b1}};
+ else if (rx_shift_reg[0] & RXD8_VALID) //ready and valid data capture
+ rx_shift_reg[8:0] <= {RXD8_DATA[7:0], 1'b0};
+ end
+
+
+ // Escape code mode register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_esc_code_mode <= 1'b0;
+ else // Set to escape mode if ESC code is detected
+ if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
+ reg_esc_code_mode <= 1'b1;
+ else if (char_received)
+ reg_esc_code_mode <= 1'b0;
+ end
+
+ // Aux Ctrl capture mode register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_aux_ctrl_mode <= 1'b0;
+ else // Set to Aux control capture mode if ESC-0x10 sequence is detected
+ if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
+ reg_aux_ctrl_mode <= 1'b1;
+ else if (char_received)
+ reg_aux_ctrl_mode <= 1'b0;
+ end
+
+ // Aux Ctrl capture data register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_aux_ctrl <= {8{1'b0}};
+ else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
+ if (char_received & (reg_aux_ctrl_mode==1'b1))
+ reg_aux_ctrl <= rx_shift_reg[8:1];
+ end
+
+ assign AUXCTRL = reg_aux_ctrl;
+
+ // Debug tester enable
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_dbgtester_enable <= 1'b0;
+ else // Enable debug tester if ESC-0x11 sequence is detected
+ if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
+ reg_dbgtester_enable <= 1'b1;
+ else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
+ // Disable debug tester if ESC-0x12 sequence is detected
+ reg_dbgtester_enable <= 1'b0;
+ end
+
+ assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
+
+ // Message display
+ always @ (posedge CLK or negedge RESETn)
+ begin: p_tube
+ if (~RESETn)
+ begin
+ string_length = 7'b0;
+ nxt_end_simulation <= 1'b0;
+ for (i=0; i<= 127; i=i+1) begin
+ tube_string [i] = 8'h00;
+ end
+ end
+ else
+ if (char_received)
+ begin
+ if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
+ begin
+ // Escape code, or in escape code mode
+ // Data receive can be command, aux ctrl data
+ // Ignore this data
+ end
+ else if (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
+ nxt_end_simulation <= 1'b1;
+ else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
+ // New line
+ begin
+ tube_string[string_length] = 8'h00;
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: ",$time);
+
+ for (i=0; i<= string_length; i=i+1)
+ begin
+ text_char = tube_string[i];
+ $fwrite(mcd,"%s",text_char);
+ end
+
+ $fwrite(mcd,"\n");
+ string_length = 7'b0;
+ end
+ else
+ begin
+ tube_string[string_length] = rx_shift_reg[8:1];
+ string_length = string_length + 1;
+ if (string_length >79) // line too long, display and clear buffer
+ begin
+ tube_string[string_length] = 8'h00;
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: ",$time);
+
+ for (i=0; i<= string_length; i=i+1)
+ begin
+ text_char = tube_string[i];
+ $fwrite(mcd,"%s",text_char);
+ end
+
+ $fwrite(mcd,"\n");
+ string_length = 7'b0;
+
+ end
+
+ end
+
+ end
+
+ end // p_TUBE
+
+ // Delay for simulation end
+ always @ (posedge CLK or negedge RESETn)
+ begin: p_sim_end
+ if (~RESETn)
+ begin
+ reg_end_simulation <= 1'b0;
+ end
+ else
+ begin
+ reg_end_simulation <= nxt_end_simulation;
+ if (reg_end_simulation==1'b1)
+ begin
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t stream_capture<%m>: Test Ended\n",$time);
+ else
+ $fwrite(mcd,"Test Ended\n");
+ $stop;
+ end
+ end
+ end
+
+ assign SIMULATIONEND = nxt_end_simulation & (~reg_end_simulation);
+
+endmodule
--
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