diff --git a/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cm0.h b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab31de0ee87f9cb566cef040364c80c1f09bbf86
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cm0.h
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cm0plus.h b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000000000000000000000000000000000..5cea74e9af368d558cb8fca0b537eb0061006d92
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cmFunc.h b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..0a18fafc301e003d348edf5cae39481d8e5fe7c3
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cmInstr.h b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab3a01097c12e33d4953a9af95f712864abd7930
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
new file mode 100644
index 0000000000000000000000000000000000000000..ed3df93e7cfe6df1066b78dbc93af48b4006c44a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
@@ -0,0 +1,1313 @@
+//-----------------------------------------------------------------------------
+// enhanced top-level example Cortex-M0 controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+/**************************************************************************//**
+ * @file CMSDK_CM0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * Device CMSDK
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef CMSDK_H
+#define CMSDK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup CMSDK_Definitions CMSDK Definitions
+ This file defines all structures and symbols for CMSDK:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - Peripheral definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup CMSDK_CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M0 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** CMSDK Specific Interrupt Numbers *********************************************************/
+ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
+ PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
+ /*!< IRQ11 - Unused */
+ UARTOVF0_IRQn = 12, /*!< UART 0 Overflow Interrupt */
+ UARTOVF1_IRQn = 13, /*!< UART 1 Overflow Interrupt */
+ UARTOVF2_IRQn = 14, /*!< UART 2 Overflow Interrupt */
+ DMA_IRQn = 15, /*!< PL230 DMA Done + Error Interrupt */
+ PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
+ PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
+ PORT0_2_IRQn = 18,
+ PORT0_3_IRQn = 19,
+ PORT0_4_IRQn = 20,
+ PORT0_5_IRQn = 21,
+ PORT0_6_IRQn = 22,
+ PORT0_7_IRQn = 23,
+ PORT0_8_IRQn = 24,
+ PORT0_9_IRQn = 25,
+ PORT0_10_IRQn = 26,
+ PORT0_11_IRQn = 27,
+ PORT0_12_IRQn = 28,
+ PORT0_13_IRQn = 29,
+ PORT0_14_IRQn = 30,
+ PORT0_15_IRQn = 31,
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+
+/*@}*/ /* end of group CMSDK_CMSIS */
+
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_CMSDK_CM0.h" /* CMSDK System include file */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+/** @addtogroup CMSDK_Peripherals CMSDK Peripherals
+ CMSDK Device Specific Peripheral registers structures
+ @{
+*/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup CMSDK_UART CMSDK Universal Asynchronous Receiver/Transmitter
+ memory mapped structure for CMSDK_UART
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
+ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
+ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
+ union {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ };
+ __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+
+#define CMSDK_UART_DATA_Pos 0 /*!< CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /*!< CMSDK_UART DATA: DATA Mask */
+
+#define CMSDK_UART_STATE_RXOR_Pos 3 /*!< CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /*!< CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /*!< CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /*!< CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /*!< CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /*!< CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /*!< CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /*!< CMSDK_UART STATE: TXBF Mask */
+
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /*!< CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /*!< CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /*!< CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /*!< CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /*!< CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /*!< CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /*!< CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /*!< CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /*!< CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /*!< CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /*!< CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /*!< CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /*!< CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /*!< CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /*!< CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /*!< CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /*!< CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /*!< CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /*!< CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /*!< CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /*!< CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /*!< CMSDK_UART CTRL: TXIRQ Mask */
+
+#define CMSDK_UART_BAUDDIV_Pos 0 /*!< CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /*!< CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+/*@}*/ /* end of group CMSDK_UART */
+
+
+/*----------------------------- Timer (TIMER) -------------------------------*/
+/** @addtogroup CMSDK_TIMER CMSDK Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
+ __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
+ __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
+ union {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ };
+
+} CMSDK_TIMER_TypeDef;
+
+/* CMSDK_TIMER CTRL Register Definitions */
+
+#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /*!< CMSDK_TIMER CTRL: IRQEN Position */
+#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /*!< CMSDK_TIMER CTRL: IRQEN Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /*!< CMSDK_TIMER CTRL: SELEXTCLK Position */
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /*!< CMSDK_TIMER CTRL: SELEXTCLK Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /*!< CMSDK_TIMER CTRL: SELEXTEN Position */
+#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /*!< CMSDK_TIMER CTRL: SELEXTEN Mask */
+
+#define CMSDK_TIMER_CTRL_EN_Pos 0 /*!< CMSDK_TIMER CTRL: EN Position */
+#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /*!< CMSDK_TIMER CTRL: EN Mask */
+
+#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /*!< CMSDK_TIMER VALUE: CURRENT Position */
+#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /*!< CMSDK_TIMER VALUE: CURRENT Mask */
+
+#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /*!< CMSDK_TIMER RELOAD: RELOAD Position */
+#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /*!< CMSDK_TIMER RELOAD: RELOAD Mask */
+
+#define CMSDK_TIMER_INTSTATUS_Pos 0 /*!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
+#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /*!< CMSDK_TIMER INTSTATUS: INTSTATUSMask */
+
+#define CMSDK_TIMER_INTCLEAR_Pos 0 /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Position */
+#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
+
+/*@}*/ /* end of group CMSDK_TIMER */
+
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+// <g> Timer (TIM)
+
+/** @addtogroup CMSDK_DualTIMER CMSDK Dual Timer
+ @{
+*/
+
+typedef struct
+{
+ __IO uint32_t Timer1Load; // <h> Timer 1 Load </h>
+ __I uint32_t Timer1Value; // <h> Timer 1 Counter Current Value <r></h>
+ __IO uint32_t Timer1Control;// <h> Timer 1 Control
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t Timer1IntClr; // <h> Timer 1 Interrupt Clear <w></h>
+ __I uint32_t Timer1RIS; // <h> Timer 1 Raw Interrupt Status <r></h>
+ __I uint32_t Timer1MIS; // <h> Timer 1 Masked Interrupt Status <r></h>
+ __IO uint32_t Timer1BGLoad; // <h> Background Load Register </h>
+ uint32_t RESERVED0;
+ __IO uint32_t Timer2Load; // <h> Timer 2 Load </h>
+ __I uint32_t Timer2Value; // <h> Timer 2 Counter Current Value <r></h>
+ __IO uint32_t Timer2Control;// <h> Timer 2 Control
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t Timer2IntClr; // <h> Timer 2 Interrupt Clear <w></h>
+ __I uint32_t Timer2RIS; // <h> Timer 2 Raw Interrupt Status <r></h>
+ __I uint32_t Timer2MIS; // <h> Timer 2 Masked Interrupt Status <r></h>
+ __IO uint32_t Timer2BGLoad; // <h> Background Load Register </h>
+ uint32_t RESERVED1[945];
+ __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
+ __O uint32_t ITOP; // <h> Integration Test Output Set Register </h>
+} CMSDK_DUALTIMER_BOTH_TypeDef;
+
+#define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /*!< CMSDK_DUALTIMER1 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER1_VALUE_Pos 0 /*!< CMSDK_DUALTIMER1 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /*!< CMSDK_DUALTIMER1 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
+
+#define CMSDK_DUALTIMER2_LOAD_Pos 0 /*!< CMSDK_DUALTIMER2 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /*!< CMSDK_DUALTIMER2 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER2_VALUE_Pos 0 /*!< CMSDK_DUALTIMER2 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /*!< CMSDK_DUALTIMER2 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
+
+
+typedef struct
+{
+ __IO uint32_t TimerLoad; // <h> Timer Load </h>
+ __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
+ __IO uint32_t TimerControl; // <h> Timer Control
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
+ __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
+ __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
+ __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
+} CMSDK_DUALTIMER_SINGLE_TypeDef;
+
+#define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */
+#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /*!< CMSDK_DUALTIMER LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER_VALUE_Pos 0 /*!< CMSDK_DUALTIMER VALUE: VALUE Position */
+#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /*!< CMSDK_DUALTIMER VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /*!< CMSDK_DUALTIMER INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /*!< CMSDK_DUALTIMER BGLOAD: Background Load Mask */
+
+/*@}*/ /* end of group CMSDK_DualTIMER */
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+
+/** @addtogroup CMSDK_GPIO CMSDK GPIO
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Offset: 0x000 DATA Register (R/W) */
+ __IO uint32_t DATAOUT; /*!< Offset: 0x004 Data Output Latch Register (R/W) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /*!< Offset: 0x010 Output Enable Set Register (R/W) */
+ __IO uint32_t OUTENABLECLR; /*!< Offset: 0x014 Output Enable Clear Register (R/W) */
+ __IO uint32_t ALTFUNCSET; /*!< Offset: 0x018 Alternate Function Set Register (R/W) */
+ __IO uint32_t ALTFUNCCLR; /*!< Offset: 0x01C Alternate Function Clear Register (R/W) */
+ __IO uint32_t INTENSET; /*!< Offset: 0x020 Interrupt Enable Set Register (R/W) */
+ __IO uint32_t INTENCLR; /*!< Offset: 0x024 Interrupt Enable Clear Register (R/W) */
+ __IO uint32_t INTTYPESET; /*!< Offset: 0x028 Interrupt Type Set Register (R/W) */
+ __IO uint32_t INTTYPECLR; /*!< Offset: 0x02C Interrupt Type Clear Register (R/W) */
+ __IO uint32_t INTPOLSET; /*!< Offset: 0x030 Interrupt Polarity Set Register (R/W) */
+ __IO uint32_t INTPOLCLR; /*!< Offset: 0x034 Interrupt Polarity Clear Register (R/W) */
+ union {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x038 Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x038 Interrupt Clear Register ( /W) */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /*!< Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /*!< Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+/*@}*/ /* end of group CMSDK_GPIO */
+
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup CMSDK_SYSCON CMSDK System Control
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t REMAP; /*!< Offset: 0x000 Remap Control Register (R/W) */
+ __IO uint32_t PMUCTRL; /*!< Offset: 0x004 PMU Control Register (R/W) */
+ __IO uint32_t RESETOP; /*!< Offset: 0x008 Reset Option Register (R/W) */
+ __IO uint32_t EMICTRL; /*!< Offset: 0x00C EMI Control Register (R/W) */
+ __IO uint32_t RSTINFO; /*!< Offset: 0x010 Reset Information Register (R/W) */
+} CMSDK_SYSCON_TypeDef;
+
+#define CMSDK_SYSCON_REMAP_Pos 0
+#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /*!< CMSDK_SYSCON MEME_CTRL: REMAP Mask */
+
+#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
+#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /*!< CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
+
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /*!< CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
+#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /*!< CMSDK_SYSCON EMICTRL: SIZE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
+#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /*!< CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
+#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
+#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: READCYCLE Mask */
+
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /*!< CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
+
+/*@}*/ /* end of group CMSDK_SYSCON */
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+/** @addtogroup CMSDK_PL230 CMSDK uDMA controller
+ @{
+*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /*!< Offset: 0x000 DMA status Register (R/W) */
+ __O uint32_t DMA_CFG; /*!< Offset: 0x004 DMA configuration Register ( /W) */
+ __IO uint32_t CTRL_BASE_PTR; /*!< Offset: 0x008 Channel Control Data Base Pointer Register (R/W) */
+ __I uint32_t ALT_CTRL_BASE_PTR; /*!< Offset: 0x00C Channel Alternate Control Data Base Pointer Register (R/ ) */
+ __I uint32_t DMA_WAITONREQ_STATUS; /*!< Offset: 0x010 Channel Wait On Request Status Register (R/ ) */
+ __O uint32_t CHNL_SW_REQUEST; /*!< Offset: 0x014 Channel Software Request Register ( /W) */
+ __IO uint32_t CHNL_USEBURST_SET; /*!< Offset: 0x018 Channel UseBurst Set Register (R/W) */
+ __O uint32_t CHNL_USEBURST_CLR; /*!< Offset: 0x01C Channel UseBurst Clear Register ( /W) */
+ __IO uint32_t CHNL_REQ_MASK_SET; /*!< Offset: 0x020 Channel Request Mask Set Register (R/W) */
+ __O uint32_t CHNL_REQ_MASK_CLR; /*!< Offset: 0x024 Channel Request Mask Clear Register ( /W) */
+ __IO uint32_t CHNL_ENABLE_SET; /*!< Offset: 0x028 Channel Enable Set Register (R/W) */
+ __O uint32_t CHNL_ENABLE_CLR; /*!< Offset: 0x02C Channel Enable Clear Register ( /W) */
+ __IO uint32_t CHNL_PRI_ALT_SET; /*!< Offset: 0x030 Channel Primary-Alterante Set Register (R/W) */
+ __O uint32_t CHNL_PRI_ALT_CLR; /*!< Offset: 0x034 Channel Primary-Alterante Clear Register ( /W) */
+ __IO uint32_t CHNL_PRIORITY_SET; /*!< Offset: 0x038 Channel Priority Set Register (R/W) */
+ __O uint32_t CHNL_PRIORITY_CLR; /*!< Offset: 0x03C Channel Priority Clear Register ( /W) */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /*!< Offset: 0x04C Bus Error Clear Register (R/W) */
+
+} CMSDK_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA STATUS: MSTREN Position */
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /*!< CMSDK_PL230 DMA STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /*!< CMSDK_PL230 DMA STATUS: STATE Position */
+#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /*!< CMSDK_PL230 DMA STATUS: STATE Mask */
+
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA CFG: MSTREN Position */
+#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /*!< CMSDK_PL230 DMA CFG: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< CMSDK_PL230 DMA CFG: CPCCACHE Position */
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /*!< CMSDK_PL230 DMA CFG: CPCCACHE Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< CMSDK_PL230 DMA CFG: CPCBUF Position */
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /*!< CMSDK_PL230 DMA CFG: CPCBUF Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< CMSDK_PL230 DMA CFG: CPCPRIV Position */
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /*!< CMSDK_PL230 DMA CFG: CPCPRIV Mask */
+
+#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< CMSDK_PL230 STATUS: BASE_PTR Position */
+#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: BASE_PTR Mask */
+
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< CMSDK_PL230 STATUS: MSTREN Position */
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: SET Position */
+#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: SET Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: CLR Position */
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: CLR Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: SET Position */
+#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: SET Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: CLR Position */
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: SET Position */
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Position */
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define CMSDK_PL230_ERR_CLR_Pos 0 /*!< CMSDK_PL230 ERR: CLR Position */
+#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /*!< CMSDK_PL230 ERR: CLR Mask */
+
+
+/*@}*/ /* end of group CMSDK_PL230 */
+
+
+/*------------- PrimeCell UART (PL110) --------------------------------------*/
+/** @addtogroup CMSDK_PL110 CMSDK PrimeCell UART
+ @{
+*/
+
+typedef struct
+{
+ __IO uint32_t UARTDR; // <h> Data
+ // <o.11> OE: Overrun error <r>
+ // <o.10> BE: Break error <r>
+ // <o.9> PE: Parity error <r>
+ // <o.8> FE: Framing error <r>
+ // <o.0..7> DATA: Received or Transmitting data (0..255)
+ // </h>
+ union {
+ __I uint32_t UARTRSR; // <h> Receive Status <r>
+ // <o.3> OE: Overrun error <r>
+ // <o.2> BE: Break error <r>
+ // <o.1> PE: Parity error <r>
+ // <o.0> FE: Framing error <r>
+ // </h>
+ __O uint32_t UARTECR; // <h> Error Clear <w>
+ // <o.3> OE: Overrun error <w>
+ // <o.2> BE: Break error <w>
+ // <o.1> PE: Parity error <w>
+ // <o.0> FE: Framing error <w>
+ // </h>
+ };
+ uint32_t RESERVED0[4];
+ __IO uint32_t UARTFR; // <h> Flags <r>
+ // <o.8> RI: Ring indicator <r>
+ // <o.7> TXFE: Transmit FIFO empty <r>
+ // <o.6> RXFF: Receive FIFO full <r>
+ // <o.5> TXFF: Transmit FIFO full <r>
+ // <o.4> RXFE: Receive FIFO empty <r>
+ // <o.3> BUSY: UART busy <r>
+ // <o.2> DCD: Data carrier detect <r>
+ // <o.1> DSR: Data set ready <r>
+ // <o.0> CTS: Clear to send <r>
+ // </h>
+ uint32_t RESERVED1;
+ __IO uint32_t UARTILPR; // <h> IrDA Low-power Counter
+ // <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255)
+ // </h>
+ __IO uint32_t UARTIBRD; // <h> Integer Baud Rate
+ // <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535)
+ // </h>
+ __IO uint32_t UARTFBRD; // <h> Fractional Baud Rate
+ // <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63)
+ // </h>
+ __IO uint32_t UARTLCR_H; // <h> Line Control
+ // <o.8> SPS: Stick parity select
+ // <o.5..6> WLEN: Word length
+ // <0=> 5 bits
+ // <1=> 6 bits
+ // <2=> 7 bits
+ // <3=> 8 bits
+ // <o.4> FEN: Enable FIFOs
+ // <o.3> STP2: Two stop bits select
+ // <o.2> EPS: Even parity select
+ // <o.1> PEN: Parity enable
+ // <o.0> BRK: Send break
+ // </h>
+ __IO uint32_t UARTCR; // <h> Control
+ // <o.15> CTSEn: CTS hardware flow control enable
+ // <o.14> RTSEn: RTS hardware flow control enable
+ // <o.13> Out2: Complement of Out2 modem status output
+ // <o.12> Out1: Complement of Out1 modem status output
+ // <o.11> RTS: Request to send
+ // <o.10> DTR: Data transmit ready
+ // <o.9> RXE: Receive enable
+ // <o.8> TXE: Transmit enable
+ // <o.7> LBE: Loop-back enable
+ // <o.2> SIRLP: IrDA SIR low power mode
+ // <o.1> SIREN: SIR enable
+ // <o.0> UARTEN: UART enable
+ // </h>
+ __IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select
+ // <o.3..5> RXIFLSEL: Receive interrupt FIFO level select
+ // <0=> >= 1/8 full
+ // <1=> >= 1/4 full
+ // <2=> >= 1/2 full
+ // <3=> >= 3/4 full
+ // <4=> >= 7/8 full
+ // <5=> reserved
+ // <6=> reserved
+ // <7=> reserved
+ // <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select
+ // <0=> <= 1/8 full
+ // <1=> <= 1/4 full
+ // <2=> <= 1/2 full
+ // <3=> <= 3/4 full
+ // <4=> <= 7/8 full
+ // <5=> reserved
+ // <6=> reserved
+ // <7=> reserved
+ // </h>
+ __IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear
+ // <o.10> OEIM: Overrun error interrupt mask
+ // <o.9> BEIM: Break error interrupt mask
+ // <o.8> PEIM: Parity error interrupt mask
+ // <o.7> FEIM: Framing error interrupt mask
+ // <o.6> RTIM: Receive interrupt mask
+ // <o.5> TXIM: Transmit interrupt mask
+ // <o.4> RXIM: Receive interrupt mask
+ // <o.3> DSRMIM: nUARTDSR modem interrupt mask
+ // <o.2> DCDMIM: nUARTDCD modem interrupt mask
+ // <o.1> CTSMIM: nUARTCTS modem interrupt mask
+ // <o.0> RIMIM: nUARTRI modem interrupt mask
+ // </h>
+ __IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r>
+ // <o.10> OERIS: Overrun error interrupt status <r>
+ // <o.9> BERIS: Break error interrupt status <r>
+ // <o.8> PERIS: Parity error interrupt status <r>
+ // <o.7> FERIS: Framing error interrupt status <r>
+ // <o.6> RTRIS: Receive timeout interrupt status <r>
+ // <o.5> TXRIS: Transmit interrupt status <r>
+ // <o.4> RXRIS: Receive interrupt status <r>
+ // <o.3> DSRRMIS: nUARTDSR modem interrupt status <r>
+ // <o.2> DCDRMIS: nUARTDCD modem interrupt status <r>
+ // <o.1> CTSRMIS: nUARTCTS modem interrupt status <r>
+ // <o.0> RIRMIS: nUARTRI modem interrupt status <r>
+ // </h>
+ __IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r>
+ // <o.10> OEMIS: Overrun error masked interrupt status <r>
+ // <o.9> BEMIS: Break error masked interrupt status <r>
+ // <o.8> PEMIS: Parity error masked interrupt status <r>
+ // <o.7> FEMIS: Framing error masked interrupt status <r>
+ // <o.6> RTMIS: Receive timeout masked interrupt status <r>
+ // <o.5> TXMIS: Transmit masked interrupt status <r>
+ // <o.4> RXMIS: Receive masked interrupt status <r>
+ // <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r>
+ // <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r>
+ // <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r>
+ // <o.0> RIMMIS: nUARTRI modem masked interrupt status <r>
+ // </h>
+ __O uint32_t UARTICR; // <h> Interrupt Clear <w>
+ // <o.10> OEIC: Overrun error interrupt clear <w>
+ // <o.9> BEIC: Break error interrupt clear <w>
+ // <o.8> PEIC: Parity error interrupt clear <w>
+ // <o.7> FEIC: Framing error interrupt clear <w>
+ // <o.6> RTIC: Receive timeout interrupt clear <w>
+ // <o.5> TXIC: Transmit interrupt clear <w>
+ // <o.4> RXIC: Receive interrupt clear <w>
+ // <o.3> DSRMIC: nUARTDSR modem interrupt clear <w>
+ // <o.2> DCDMIC: nUARTDCD modem interrupt clear <w>
+ // <o.1> CTSMIC: nUARTCTS modem interrupt clear <w>
+ // <o.0> RIMIC: nUARTRI modem interrupt clear <w>
+ // </h>
+ __IO uint32_t UARTDMACR; // <h> DMA Control
+ // <o.2> DMAONERR: DMA on error
+ // <o.1> TXDMAE: Transmit DMA enable
+ // <o.0> RXDMAE: Receive DMA enable
+ // </h>
+} PL110_UART_TypeDef;
+
+#define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */
+#define CMSDK_PL110_DATAOVRRUN_Msk (0x1ul << CMSDK_PL110_DATAOVRRUN_Pos) /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Mask */
+
+#define CMSDK_PL110_DATABREAKERR_Pos 10 /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Position */
+#define CMSDK_PL110_DATABREAKERR_Msk (0x1ul << CMSDK_PL110_DATABREAKERR_Pos) /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Mask */
+
+#define CMSDK_PL110_DATAPARITYERR_Pos 9 /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Position */
+#define CMSDK_PL110_DATAPARITYERR_Msk (0x1ul << CMSDK_PL110_DATAPARITYERR_Pos) /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Mask */
+
+#define CMSDK_PL110_DATAFRAMEERR_Pos 8 /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Position */
+#define CMSDK_PL110_DATAFRAMEERR_Msk (0x1ul << CMSDK_PL110_DATAFRAMEERR_Pos) /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Mask */
+
+#define CMSDK_PL110_RECOVRRUN_Pos 3 /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Position */
+#define CMSDK_PL110_RECOVRRUN_Msk (0x1ul << CMSDK_PL110_RECOVRRUN_Pos) /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Mask */
+
+#define CMSDK_PL110_RECBREAKERR_Pos 2 /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Position */
+#define CMSDK_PL110_RECBREAKERR_Msk (0x1ul << CMSDK_PL110_RECBREAKERR_Pos) /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Mask */
+
+#define CMSDK_PL110_RECPARITYERR_Pos 1 /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Position */
+#define CMSDK_PL110_RECPARITYERR_Msk (0x1ul << CMSDK_PL110_RECPARITYERR_Pos) /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Mask */
+
+#define CMSDK_PL110_RECFRAMEERR_Pos 0 /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Position */
+#define CMSDK_PL110_RECFRAMEERR_Msk (0x1ul << CMSDK_PL110_RECFRAMEERR_Pos) /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Mask */
+
+#define CMSDK_PL110_ERRCLROVRRUN_Pos 3 /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Position */
+#define CMSDK_PL110_ERRCLROVRRUN_Msk (0x1ul << CMSDK_PL110_ERRCLROVRRUN_Pos) /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Mask */
+
+#define CMSDK_PL110_ERRCLRBREAKERR_Pos 2 /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Position */
+#define CMSDK_PL110_ERRCLRBREAKERR_Msk (0x1ul << CMSDK_PL110_ERRCLRBREAKERR_Pos) /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Mask */
+
+#define CMSDK_PL110_ERRCLRPARITYERR_Pos 1 /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Position */
+#define CMSDK_PL110_ERRCLRPARITYERR_Msk (0x1ul << CMSDK_PL110_ERRCLRPARITYERR_Pos) /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Mask */
+
+#define CMSDK_PL110_ERRCLRFRAMEERR_Pos 0 /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Position */
+#define CMSDK_PL110_ERRCLRFRAMEERR_Msk (0x1ul << CMSDK_PL110_ERRCLRFRAMEERR_Pos) /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Mask */
+
+#define CMSDK_PL110_FLAG_RINGIND_Pos 8 /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Position */
+#define CMSDK_PL110_FLAG_RINGIND_Msk (0x1ul << CMSDK_PL110_FLAG_RINGIND_Pos) /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Mask */
+
+#define CMSDK_PL110_FLAG_TXFEMPTY_Pos 7 /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Position */
+#define CMSDK_PL110_FLAG_TXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_TXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Mask */
+
+#define CMSDK_PL110_FLAG_RXFFULL_Pos 6 /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Position */
+#define CMSDK_PL110_FLAG_RXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_RXFFULL_Pos) /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Mask */
+
+#define CMSDK_PL110_FLAG_TXFFULL_Pos 5 /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Position */
+#define CMSDK_PL110_FLAG_TXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_TXFFULL_Pos) /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Mask */
+
+#define CMSDK_PL110_FLAG_RXFEMPTY_Pos 4 /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Position */
+#define CMSDK_PL110_FLAG_RXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_RXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Mask */
+
+#define CMSDK_PL110_FLAG_UARTBUSY_Pos 3 /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Position */
+#define CMSDK_PL110_FLAG_UARTBUSY_Msk (0x1ul << CMSDK_PL110_FLAG_UARTBUSY_Pos) /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Mask */
+
+#define CMSDK_PL110_FLAG_CARRIERDETECT_Pos 2 /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Position */
+#define CMSDK_PL110_FLAG_CARRIERDETECT_Msk (0x1ul << CMSDK_PL110_FLAG_CARRIERDETECT_Pos) /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Mask */
+
+#define CMSDK_PL110_FLAG_DATASETREADY_Pos 1 /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Position */
+#define CMSDK_PL110_FLAG_DATASETREADY_Msk (0x1ul << CMSDK_PL110_FLAG_DATASETREADY_Pos) /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Mask */
+
+#define CMSDK_PL110_FLAG_CLR2SEND_Pos 0 /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Position */
+#define CMSDK_PL110_FLAG_CLR2SEND_Msk (0x1ul << CMSDK_PL110_FLAG_CLR2SEND_Pos) /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Mask */
+
+#define CMSDK_PL110_IRDALOWPOWERCOUNT_Pos 0 /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Position */
+#define CMSDK_PL110_IRDALOWPOWERCOUNT_Msk (0xFFul << CMSDK_PL110_IRDALOWPOWERCOUNT_Pos) /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Mask */
+
+#define CMSDK_PL110_INTDIVIDER_Pos 0 /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Position */
+#define CMSDK_PL110_INTDIVIDER_Msk (0xFFFFul << CMSDK_PL110_INTDIVIDER_Pos) /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Mask */
+
+#define CMSDK_PL110_FRACTDIVIDER_Pos 0 /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Position */
+#define CMSDK_PL110_FRACTDIVIDER_Msk (0x3Ful << CMSDK_PL110_FRACTDIVIDER_Pos) /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Mask */
+
+#define CMSDK_PL110_STICKPARITYSEL_Pos 8 /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Position */
+#define CMSDK_PL110_STICKPARITYSEL_Msk (0x1ul << CMSDK_PL110_STICKPARITYSEL_Pos) /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Mask */
+
+#define CMSDK_PL110_WORDLEN_Pos 5 /*!< CMSDK_PL110 WORDLEN: Word Length Select Position */
+#define CMSDK_PL110_WORDLEN_Msk (0x3ul << CMSDK_PL110_WORDLEN_Pos) /*!< CMSDK_PL110 WORDLEN: Word Length Select Mask */
+
+#define CMSDK_PL110_ENFIFOS_Pos 4 /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Position */
+#define CMSDK_PL110_ENFIFOS_Msk (0x1ul << CMSDK_PL110_ENFIFOS_Pos) /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Mask */
+
+#define CMSDK_PL110_2STOPBITS_Pos 3 /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Position */
+#define CMSDK_PL110_2STOPBITS_Msk (0x1ul << CMSDK_PL110_2STOPBITS_Pos) /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Mask */
+
+#define CMSDK_PL110_EVENPARITY_Pos 2 /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Position */
+#define CMSDK_PL110_EVENPARITY_Msk (0x1ul << CMSDK_PL110_EVENPARITY_Pos) /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Mask */
+
+#define CMSDK_PL110_PARITYEN_Pos 1 /*!< CMSDK_PL110 PARITYEN: Parity Enable Position */
+#define CMSDK_PL110_PARITYEN_Msk (0x1ul << CMSDK_PL110_PARITYEN_Pos) /*!< CMSDK_PL110 PARITYEN: Parity Enable Mask */
+
+#define CMSDK_PL110_SENDBREAK_Pos 0 /*!< CMSDK_PL110 SENDBREAK: Send Break Position */
+#define CMSDK_PL110_SENDBREAK_Msk (0x1ul << CMSDK_PL110_SENDBREAK_Pos) /*!< CMSDK_PL110 SENDBREAK: Send Break Mask */
+
+#define CMSDK_PL110_CTS_FLOWCTRL_Pos 15 /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Position */
+#define CMSDK_PL110_CTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_CTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Mask */
+
+#define CMSDK_PL110_RTS_FLOWCTRL_Pos 14 /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Position */
+#define CMSDK_PL110_RTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_RTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Mask */
+
+#define CMSDK_PL110_OUT2_Pos 13 /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Position */
+#define CMSDK_PL110_OUT2_Msk (0x1ul << CMSDK_PL110_OUT2_Pos) /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Mask */
+
+#define CMSDK_PL110_OUT1_Pos 12 /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Position */
+#define CMSDK_PL110_OUT1_Msk (0x1ul << CMSDK_PL110_OUT1_Pos) /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Mask */
+
+#define CMSDK_PL110_REQ2SEND_Pos 11 /*!< CMSDK_PL110 REQ2SEND: Request To Send Position */
+#define CMSDK_PL110_REQ2SEND_Msk (0x1ul << CMSDK_PL110_REQ2SEND_Pos) /*!< CMSDK_PL110 REQ2SEND: Request To Send Mask */
+
+#define CMSDK_PL110_DATATRANSREADY_Pos 10 /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Position */
+#define CMSDK_PL110_DATATRANSREADY_Msk (0x1ul << CMSDK_PL110_DATATRANSREADY_Pos) /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Mask */
+
+#define CMSDK_PL110_RXEN_Pos 9 /*!< CMSDK_PL110 RXEN: Receive Enable Position */
+#define CMSDK_PL110_RXEN_Msk (0x1ul << CMSDK_PL110_RXEN_Pos) /*!< CMSDK_PL110 RXEN: Receive Enable Mask */
+
+#define CMSDK_PL110_TXEN_Pos 8 /*!< CMSDK_PL110 TXEN: Transmit Enable Position */
+#define CMSDK_PL110_TXEN_Msk (0x1ul << CMSDK_PL110_TXEN_Pos) /*!< CMSDK_PL110 TXEN: Transmit Enable Mask */
+
+#define CMSDK_PL110_LOOPBACKEN_Pos 7 /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Position */
+#define CMSDK_PL110_LOOPBACKEN_Msk (0x1ul << CMSDK_PL110_LOOPBACKEN_Pos) /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Mask */
+
+#define CMSDK_PL110_IRDASIRLPM_Pos 2 /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Position */
+#define CMSDK_PL110_IRDASIRLPM_Msk (0x1ul << CMSDK_PL110_IRDASIRLPM_Pos) /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Mask */
+
+#define CMSDK_PL110_SIREN_Pos 1 /*!< CMSDK_PL110 SIREN: SIR Enable Position */
+#define CMSDK_PL110_SIREN_Msk (0x1ul << CMSDK_PL110_SIREN_Pos) /*!< CMSDK_PL110 SIREN: SIR Enable Mask */
+
+#define CMSDK_PL110_UARTEN_Pos 0 /*!< CMSDK_PL110 UARTEN: UART Enable Position */
+#define CMSDK_PL110_UARTEN_Msk (0x1ul << CMSDK_PL110_UARTEN_Pos) /*!< CMSDK_PL110 UARTEN: UART Enable Mask */
+
+#define CMSDK_PL110_RECINTFIFOLEVEL_Pos 3 /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Position */
+#define CMSDK_PL110_RECINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_RECINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Mask */
+
+#define CMSDK_PL110_TRANSINTFIFOLEVEL_Pos 0 /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Position */
+#define CMSDK_PL110_TRANSINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_TRANSINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Mask */
+
+#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_BREAKERRINT_Pos) /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_PARITYERRINT_Pos) /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_FRAMEERRINT_Pos) /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Position */
+#define CMSDK_PL110_SETMASK_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECTRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_TRANSINT_Pos 5 /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Position */
+#define CMSDK_PL110_SETMASK_TRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_TRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_RECINT_Pos 4 /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Position */
+#define CMSDK_PL110_SETMASK_RECINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECINT_Pos) /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_RIMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 RAWINTSTAT_UART_DSRMODINT: Raw Data Set Ready Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UARTD_SRMODINT: Raw Data Set Ready Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Mask */
+
+#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Position */
+#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Position */
+#define CMSDK_PL110_INTCLR_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_BREAKERRINT_Pos) /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Position */
+#define CMSDK_PL110_INTCLR_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_PARITYERRINT_Pos) /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Position */
+#define CMSDK_PL110_INTCLR_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_FRAMEERRINT_Pos) /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Position */
+#define CMSDK_PL110_INTCLR_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECTRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Mask */
+
+#define CMSDK_PL110_INTCLR_TRANSINT_Pos 5 /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Position */
+#define CMSDK_PL110_INTCLR_TRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_TRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Mask */
+
+#define CMSDK_PL110_INTCLR_RECINT_Pos 4 /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Position */
+#define CMSDK_PL110_INTCLR_RECINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECINT_Pos) /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 INTCLR_UART_DSRMODINT: Clear Data Carrier Detect Int Position */
+#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UARTD_SRMODINT: Clear Data Carrier Detect Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Position */
+#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Position */
+#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Position */
+#define CMSDK_PL110_INTCLR_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_RIMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Mask */
+
+#define CMSDK_PL110_DMA_ERR_Pos 2 /*!< CMSDK_PL110 DMA_ERR: DMA Error Position */
+#define CMSDK_PL110_DMA_ERR_Msk (0x1ul << CMSDK_PL110_DMA_ERR_Pos) /*!< CMSDK_PL110 DMA_ERR: DMA Error Mask */
+
+#define CMSDK_PL110_DMA_TRANS_EN_Pos 1 /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Position */
+#define CMSDK_PL110_DMA_TRANS_EN_Msk (0x1ul << CMSDK_PL110_DMA_TRANS_EN_Pos) /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Mask */
+
+#define CMSDK_PL110_DMA_REC_EN_Pos 0 /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Position */
+#define CMSDK_PL110_DMA_REC_EN_Msk (0x1ul << CMSDK_PL110_DMA_REC_EN_Pos) /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Mask */
+
+
+/*@}*/ /* end of group CMSDK_PL110 */
+
+/*------------------- Watchdog ----------------------------------------------*/
+/** @addtogroup CMSDK_Watchdog CMSDK Watchdog
+ @{
+*/
+typedef struct
+{
+
+ __IO uint32_t LOAD; // <h> Watchdog Load Register </h>
+ __I uint32_t VALUE; // <h> Watchdog Value Register </h>
+ __IO uint32_t CTRL; // <h> Watchdog Control Register
+ // <o.1> RESEN: Reset enable
+ // <o.0> INTEN: Interrupt enable
+ // </h>
+ __O uint32_t INTCLR; // <h> Watchdog Clear Interrupt Register </h>
+ __I uint32_t RAWINTSTAT; // <h> Watchdog Raw Interrupt Status Register </h>
+ __I uint32_t MASKINTSTAT; // <h> Watchdog Interrupt Status Register </h>
+ uint32_t RESERVED0[762];
+ __IO uint32_t LOCK; // <h> Watchdog Lock Register </h>
+ uint32_t RESERVED1[191];
+ __IO uint32_t ITCR; // <h> Watchdog Integration Test Control Register </h>
+ __O uint32_t ITOP; // <h> Watchdog Integration Test Output Set Register </h>
+
+}CMSDK_WATCHDOG_TypeDef;
+
+#define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */
+#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */
+
+#define CMSDK_Watchdog_VALUE_Pos 0 /*!< CMSDK_Watchdog VALUE: VALUE Position */
+#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /*!< CMSDK_Watchdog VALUE: VALUE Mask */
+
+#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
+#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
+
+#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
+#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
+
+#define CMSDK_Watchdog_INTCLR_Pos 0 /*!< CMSDK_Watchdog INTCLR: Int Clear Position */
+#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /*!< CMSDK_Watchdog INTCLR: Int Clear Mask */
+
+#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_Watchdog_LOCK_Pos 0 /*!< CMSDK_Watchdog LOCK: LOCK Position */
+#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /*!< CMSDK_Watchdog LOCK: LOCK Mask */
+
+#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
+#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
+
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
+
+/*@}*/ /* end of group CMSDK_Watchdog */
+
+/*------------------- PrimeCell APB GPIO --------------------------------------*/
+/** @addtogroup CMSDK_PL061 CMSDK APB GPIO
+ @{
+*/
+typedef struct
+{
+
+__IO uint32_t DATA[256];
+__IO uint32_t DIR;
+__IO uint32_t INTSENSE;
+__IO uint32_t INTBOTHEDGE;
+__IO uint32_t INTEVENT;
+__IO uint32_t INTMASK;
+__O uint32_t RAWINTSTAT;
+__O uint32_t MASKINTSTAT;
+__I uint32_t INTCLR;
+__IO uint32_t MODECTRL;
+
+}APBGPIO_TypeDef;
+
+#define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */
+#define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */
+
+#define CMSDK_PL061_DIR_Pos 0 /*!< CMSDK_PL061 DIR: Data Direction Position */
+#define CMSDK_PL061_DIR_Msk (0x1ul << CMSDK_PL061_DIR_Pos) /*!< CMSDK_PL061 DIR: Data Direction Mask */
+
+#define CMSDK_PL061_INTSENSE_Pos 0 /*!< CMSDK_PL061 INTSENSE: INT SENSE Position */
+#define CMSDK_PL061_INTSENSE_Msk (0x1ul << CMSDK_PL061_INTSENSE_Pos) /*!< CMSDK_PL061 INTSENSE: INT SENSE Mask */
+
+#define CMSDK_PL061_INTBOTHEDGE_Pos 0 /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Position */
+#define CMSDK_PL061_INTBOTHEDGE_Msk (0x1ul << CMSDK_PL061_INTBOTHEDGE_Pos) /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Mask */
+
+#define CMSDK_PL061_INTEVENT_Pos 0 /*!< CMSDK_PL061 INTEVENT: INT EVENT Position */
+#define CMSDK_PL061_INTEVENT_Msk (0x1ul << CMSDK_PL061_INTEVENT_Pos) /*!< CMSDK_PL061 INTEVENT: INT EVENT Mask */
+
+#define CMSDK_PL061_INTMASK_Pos 0 /*!< CMSDK_PL061 INTMASK: INT MASK Position */
+#define CMSDK_PL061_INTMASK_Msk (0x1ul << CMSDK_PL061_INTMASK_Pos) /*!< CMSDK_PL061 INTMASK: INT MASK Mask */
+
+#define CMSDK_PL061_RAWINTSTAT_Pos 0 /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_PL061_RAWINTSTAT_Msk (0x1ul << CMSDK_PL061_RAWINTSTAT_Pos) /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_PL061_MASKINTSTAT_Pos 0 /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_PL061_MASKINTSTAT_Msk (0x1ul << CMSDK_PL061_MASKINTSTAT_Pos) /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_PL061_INTCLR_Pos 0 /*!< CMSDK_PL061 INTCLR: Int Clear Position */
+#define CMSDK_PL061_INTCLR_Msk (0x1ul << CMSDK_PL061_INTCLR_Pos) /*!< CMSDK_PL061 INTCLR: Int Clear Mask */
+
+#define CMSDK_PL061_MODECTRL_HWEN_Pos 0 /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Position */
+#define CMSDK_PL061_MODECTRL_HWEN_Msk (0x1ul << CMSDK_PL061_MODECTRL_HWEN_Pos) /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Mask */
+
+
+/*@}*/ /* end of group CMSDK_PL061 */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group CMSDK_Peripherals */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/** @addtogroup CMSDK_MemoryMap CMSDK Memory Mapping
+ @{
+*/
+
+/* Peripheral and SRAM base address */
+#define CMSDK_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
+#define CMSDK_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
+#define CMSDK_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
+
+#define CMSDK_RAM_BASE (0x20000000UL)
+#define CMSDK_APB_BASE (0x40000000UL)
+#define CMSDK_AHB_BASE (0x40010000UL)
+
+/* APB peripherals */
+#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
+#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
+#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
+#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
+#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
+#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_USRT2_BASE (CMSDK_APB_BASE + 0xE000UL) //0x6000UL)
+#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+/* AHB peripherals */
+#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
+#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
+#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
+/*@}*/ /* end of group CMSDK_MemoryMap */
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+/** @addtogroup CMSDK_PeripheralDecl CMSDK Peripheral Declaration
+ @{
+*/
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
+#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
+#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
+#define CMSDK_USRT2 ((CMSDK_UART_TypeDef *) CMSDK_USRT2_BASE )
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
+#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
+#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
+#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
+#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
+#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
+#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
+#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
+/*@}*/ /* end of group CMSDK_PeripheralDecl */
+
+/*@}*/ /* end of group CMSDK_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CMSDK_H */
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_driver.h b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_driver.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b7b49a5def62517e1e926302fce6c8af6e3e394
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_driver.h
@@ -0,0 +1,293 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/*************************************************************************//**
+ * @file CMSDK_driver.h
+ * @brief CMSDK Example Device Driver Header File
+ * @version $State:$
+ * @date $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ ******************************************************************************/
+
+
+/** @addtogroup CMSIS_CM0_CMSDK_Driver_definitions CMSDK Driver definitions
+ This file defines all CMSDK Driver functions for CMSIS core for the following modules:
+ - Timer
+ - UART
+ - GPIO
+ @{
+ */
+
+ #include "CMSDK_CM0.h"
+
+
+ /*UART Driver Declarations*/
+
+ /**
+ * @brief Initializes UART module.
+ */
+
+ extern uint32_t CMSDK_uart_init(CMSDK_UART_TypeDef *CMSDK_UART, uint32_t divider, uint32_t tx_en,
+ uint32_t rx_en, uint32_t tx_irq_en, uint32_t rx_irq_en, uint32_t tx_ovrirq_en, uint32_t rx_ovrirq_en);
+
+ /**
+ * @brief Returns whether the UART RX Buffer is Full.
+ */
+
+ extern uint32_t CMSDK_uart_GetRxBufferFull(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Returns whether the UART TX Buffer is Full.
+ */
+
+ extern uint32_t CMSDK_uart_GetTxBufferFull(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Sends a character to the UART TX Buffer.
+ */
+
+
+ extern void CMSDK_uart_SendChar(CMSDK_UART_TypeDef *CMSDK_UART, char txchar);
+
+ /**
+ * @brief Receives a character from the UART RX Buffer.
+ */
+
+ extern char CMSDK_uart_ReceiveChar(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Returns UART Overrun status.
+ */
+
+ extern uint32_t CMSDK_uart_GetOverrunStatus(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Clears UART Overrun status Returns new UART Overrun status.
+ */
+
+ extern uint32_t CMSDK_uart_ClearOverrunStatus(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Returns UART Baud rate Divider value.
+ */
+
+ extern uint32_t CMSDK_uart_GetBaudDivider(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Return UART TX Interrupt Status.
+ */
+
+ extern uint32_t CMSDK_uart_GetTxIRQStatus(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Return UART RX Interrupt Status.
+ */
+
+ extern uint32_t CMSDK_uart_GetRxIRQStatus(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Clear UART TX Interrupt request.
+ */
+
+ extern void CMSDK_uart_ClearTxIRQ(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Clear UART RX Interrupt request.
+ */
+
+ extern void CMSDK_uart_ClearRxIRQ(CMSDK_UART_TypeDef *CMSDK_UART);
+
+ /**
+ * @brief Set CMSDK Timer for multi-shoot mode with internal clock
+ */
+
+ /*Timer Driver Declarations*/
+
+ extern void CMSDK_timer_Init_IntClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,
+ uint32_t irq_en);
+
+ /**
+ * @brief Set CMSDK Timer for multi-shoot mode with external enable
+ */
+
+ extern void CMSDK_timer_Init_ExtClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,
+ uint32_t irq_en);
+
+
+ /**
+ * @brief Set CMSDK Timer for multi-shoot mode with external clock
+ */
+
+ extern void CMSDK_timer_Init_ExtEnable(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,
+ uint32_t irq_en);
+
+ /**
+ * @brief CMSDK Timer interrupt clear
+ */
+
+
+ extern void CMSDK_timer_ClearIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Returns timer IRQ status
+ */
+
+ uint32_t CMSDK_timer_StatusIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Returns Timer Reload value.
+ */
+
+ extern uint32_t CMSDK_timer_GetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Sets Timer Reload value.
+ */
+
+ extern void CMSDK_timer_SetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value);
+
+ /**
+ * @brief Returns Timer current value.
+ */
+
+ uint32_t CMSDK_timer_GetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Sets Timer current value.
+ */
+
+ extern void CMSDK_timer_SetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value);
+
+ /**
+ * @brief Stops CMSDK Timer.
+ */
+
+ extern void CMSDK_timer_StopTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Starts CMSDK Timer.
+ */
+
+ extern void CMSDK_timer_StartTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Enables CMSDK Timer Interrupt requests.
+ */
+
+ extern void CMSDK_timer_EnableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Disables CMSDK Timer Interrupt requests.
+ */
+
+ extern void CMSDK_timer_DisableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+
+ /**
+ * @brief Set CMSDK GPIO Output Enable.
+ */
+
+ /*GPIO Driver Declarations*/
+
+ extern void CMSDK_gpio_SetOutEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t outenableset);
+
+ /**
+ * @brief Clear CMSDK GPIO Output Enable.
+ */
+
+ extern void CMSDK_gpio_ClrOutEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t outenableclr);
+
+ /**
+ * @brief Returns CMSDK GPIO Output Enable.
+ */
+
+ extern uint32_t CMSDK_gpio_GetOutEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO);
+
+ /**
+ * @brief Set CMSDK GPIO Alternate function Enable.
+ */
+
+ extern void CMSDK_gpio_SetAltFunc(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t AltFuncset);
+
+ /**
+ * @brief Clear CMSDK GPIO Alternate function Enable.
+ */
+
+ extern void CMSDK_gpio_ClrAltFunc(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t AltFuncclr);
+
+ /**
+ * @brief Returns CMSDK GPIO Alternate function Enable.
+ */
+
+ extern uint32_t CMSDK_gpio_GetAltFunc(CMSDK_GPIO_TypeDef *CMSDK_GPIO);
+
+ /**
+ * @brief Clear CMSDK GPIO Interrupt request.
+ */
+
+ extern uint32_t CMSDK_gpio_IntClear(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Enable CMSDK GPIO Interrupt request.
+ */
+
+ extern uint32_t CMSDK_gpio_SetIntEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Disable CMSDK GPIO Interrupt request.
+ */
+
+ extern uint32_t CMSDK_gpio_ClrIntEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Setup CMSDK GPIO Interrupt as high level.
+ */
+
+ extern void CMSDK_gpio_SetIntHighLevel(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Setup CMSDK GPIO Interrupt as rising edge.
+ */
+
+ extern void CMSDK_gpio_SetIntRisingEdge(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Setup CMSDK GPIO Interrupt as low level.
+ */
+
+ extern void CMSDK_gpio_SetIntLowLevel(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Setup CMSDK GPIO Interrupt as falling edge.
+ */
+
+ extern void CMSDK_gpio_SetIntFallingEdge(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num);
+
+ /**
+ * @brief Setup CMSDK GPIO output value using Masked access.
+ */
+
+ extern void CMSDK_gpio_MaskedWrite(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t value, uint32_t mask);
+
+ /*@}*/ /* end of group CMSIS_CM0_CMSDK_Driver_definitions CMSDK Driver definitions */
+
+
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/system_CMSDK_CM0.h b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/system_CMSDK_CM0.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e74cf38acba2b90e5f923a5389c3d84b2a58821
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/system_CMSDK_CM0.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_CMSDK_CM0.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
+ * Device <Device>
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_CM0_H
+#define SYSTEM_CMSDK_CM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_CM0_H */
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
new file mode 100644
index 0000000000000000000000000000000000000000..29bc88adfc2f1833ab75bc6b546bc6fa71690d66
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
@@ -0,0 +1,250 @@
+;/**************************************************************************//**
+; * @file startup_CMSDK_CM0.s
+; * @brief CMSIS Cortex-M0 Core Device Startup File for
+; * Device CMSDK_CM0
+; * @version V3.01
+; * @date 06. March 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000100
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ DCD UARTRX0_Handler ; UART 0 RX Handler
+ DCD UARTTX0_Handler ; UART 0 TX Handler
+ DCD UARTRX1_Handler ; UART 1 RX Handler
+ DCD UARTTX1_Handler ; UART 1 TX Handler
+ DCD UARTRX2_Handler ; UART 2 RX Handler
+ DCD UARTTX2_Handler ; UART 2 TX Handler
+ DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
+ DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
+ DCD TIMER0_Handler ; TIMER 0 handler
+ DCD TIMER1_Handler ; TIMER 1 handler
+ DCD DUALTIMER_HANDLER ; Dual timer handler
+ DCD 0 ; Reserved
+ DCD UARTOVF0_Handler ; UART 0 Overflow Handler
+ DCD UARTOVF1_Handler ; UART 1 Overflow Handler
+ DCD UARTOVF2_Handler ; UART 2 Overflow Handler
+ DCD DMA_Handler ; DMA handler
+ DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
+ DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
+ DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
+ DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
+ DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
+ DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
+ DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
+ DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
+ DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
+ DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
+ DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
+ DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
+ DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
+ DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
+ DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
+ DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Default_Handler PROC
+ EXPORT UARTRX0_Handler [WEAK]
+ EXPORT UARTTX0_Handler [WEAK]
+ EXPORT UARTRX1_Handler [WEAK]
+ EXPORT UARTTX1_Handler [WEAK]
+ EXPORT UARTRX2_Handler [WEAK]
+ EXPORT UARTTX2_Handler [WEAK]
+ EXPORT PORT0_COMB_Handler [WEAK]
+ EXPORT PORT1_COMB_Handler [WEAK]
+ EXPORT TIMER0_Handler [WEAK]
+ EXPORT TIMER1_Handler [WEAK]
+ EXPORT DUALTIMER_HANDLER [WEAK]
+ EXPORT UARTOVF0_Handler [WEAK]
+ EXPORT UARTOVF1_Handler [WEAK]
+ EXPORT UARTOVF2_Handler [WEAK]
+ EXPORT DMA_Handler [WEAK]
+ EXPORT PORT0_0_Handler [WEAK]
+ EXPORT PORT0_1_Handler [WEAK]
+ EXPORT PORT0_2_Handler [WEAK]
+ EXPORT PORT0_3_Handler [WEAK]
+ EXPORT PORT0_4_Handler [WEAK]
+ EXPORT PORT0_5_Handler [WEAK]
+ EXPORT PORT0_6_Handler [WEAK]
+ EXPORT PORT0_7_Handler [WEAK]
+ EXPORT PORT0_8_Handler [WEAK]
+ EXPORT PORT0_9_Handler [WEAK]
+ EXPORT PORT0_10_Handler [WEAK]
+ EXPORT PORT0_11_Handler [WEAK]
+ EXPORT PORT0_12_Handler [WEAK]
+ EXPORT PORT0_13_Handler [WEAK]
+ EXPORT PORT0_14_Handler [WEAK]
+ EXPORT PORT0_15_Handler [WEAK]
+UARTRX0_Handler
+UARTTX0_Handler
+UARTRX1_Handler
+UARTTX1_Handler
+UARTRX2_Handler
+UARTTX2_Handler
+PORT0_COMB_Handler
+PORT1_COMB_Handler
+TIMER0_Handler
+TIMER1_Handler
+DUALTIMER_HANDLER
+UARTOVF0_Handler
+UARTOVF1_Handler
+UARTOVF2_Handler
+DMA_Handler
+PORT0_0_Handler
+PORT0_1_Handler
+PORT0_2_Handler
+PORT0_3_Handler
+PORT0_4_Handler
+PORT0_5_Handler
+PORT0_6_Handler
+PORT0_7_Handler
+PORT0_8_Handler
+PORT0_9_Handler
+PORT0_10_Handler
+PORT0_11_Handler
+PORT0_12_Handler
+PORT0_13_Handler
+PORT0_14_Handler
+PORT0_15_Handler
+ B .
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/CMSDK_driver.c b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/CMSDK_driver.c
new file mode 100644
index 0000000000000000000000000000000000000000..27b0f44a82df6f8f4cca4beb039393b608bab0fc
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/CMSDK_driver.c
@@ -0,0 +1,659 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/*********************************************************************//******
+ * @file CMSDK_driver.c
+ * @brief CMSDK Example Device Driver C File
+ * @version $State:$
+ * @date $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ ******************************************************************************/
+
+#include "CMSDK_CM0.h"
+
+
+
+/** \mainpage ARM CMSDK LIBRARY
+ *
+ *
+ * This user manual describes the ARM Corex M Series CMSDK Library which utilises the
+ * Cortex Microcontroller Software Interface Standard (CMSIS). it also includes drivers
+ * for the following modules:
+ *
+ * - UART
+ * - Timer
+ * - GPIO
+ *
+ * The library contains C and assembly functions that have been ported and tested on the MDK
+ * toolchain.
+ */
+
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return none
+ *
+ * @brief Enable the microcontroller timer interrupts.
+ */
+
+ void CMSDK_timer_EnableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ CMSDK_TIMER->CTRL |= CMSDK_TIMER_CTRL_IRQEN_Msk;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return none
+ *
+ * @brief Disable the microcontroller timer interrutps.
+ */
+
+ void CMSDK_timer_DisableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ CMSDK_TIMER->CTRL &= ~CMSDK_TIMER_CTRL_IRQEN_Msk;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return none
+ *
+ * @brief Start the Timer.
+ */
+
+ void CMSDK_timer_StartTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ CMSDK_TIMER->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return none
+ *
+ * @brief Stop the Timer.
+ */
+
+ void CMSDK_timer_StopTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ CMSDK_TIMER->CTRL &= ~CMSDK_TIMER_CTRL_EN_Msk;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return TimerValue
+ *
+ * @brief Returns the current value of the timer.
+ */
+
+ uint32_t CMSDK_timer_GetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ return CMSDK_TIMER->VALUE;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @param value the value to which the timer is to be set
+ * @return TimerValue
+ *
+ * @brief Sets the timer to the specified value.
+ */
+
+ void CMSDK_timer_SetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value)
+ {
+ CMSDK_TIMER->VALUE = value;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return TimerReload
+ *
+ * @brief Returns the reload value of the timer. The reload value is the value which the timer is set to after an underflow occurs.
+ */
+
+ uint32_t CMSDK_timer_GetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ return CMSDK_TIMER->RELOAD;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @param value Value to be loaded
+ * @return none
+ *
+ * @brief Sets the reload value of the timer to the specified value. The reload value is the value which the timer is set to after an underflow occurs.
+ */
+
+ void CMSDK_timer_SetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value)
+ {
+ CMSDK_TIMER->RELOAD = value;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return none
+ *
+ * @brief Clears the timer IRQ if set.
+ */
+
+ void CMSDK_timer_ClearIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ CMSDK_TIMER->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @return none
+ *
+ * @brief Returns the IRQ status of the timer in question.
+ */
+
+ uint32_t CMSDK_timer_StatusIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
+ {
+ return CMSDK_TIMER->INTSTATUS;
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @param reload The value to which the timer is to be set after an underflow has occurred
+ * @param irq_en Defines whether the timer IRQ is to be enabled
+ * @return none
+ *
+ * @brief Initialises the timer to use the internal clock and specifies the timer reload value and whether IRQ is enabled or not.
+ */
+
+ void CMSDK_timer_Init_IntClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,
+ uint32_t irq_en)
+ {
+ CMSDK_TIMER->CTRL = 0;
+ CMSDK_TIMER->VALUE = reload;
+ CMSDK_TIMER->RELOAD = reload;
+ if (irq_en!=0) /* non zero - enable IRQ */
+ CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk | CMSDK_TIMER_CTRL_EN_Msk);
+ else{ /* zero - do not enable IRQ */
+ CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk); /* enable timer */
+ }
+ }
+
+/**
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @param reload The value to which the timer is to be set after an underflow has occurred
+ * @param irq_en Defines whether the timer IRQ is to be enabled
+ * @return none
+ *
+ * @brief Initialises the timer to use the external clock and specifies the timer reload value and whether IRQ is enabled or not.
+ */
+
+ void CMSDK_timer_Init_ExtClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,
+ uint32_t irq_en)
+ {
+ CMSDK_TIMER->CTRL = 0;
+ CMSDK_TIMER->VALUE = reload;
+ CMSDK_TIMER->RELOAD = reload;
+ if (irq_en!=0) /* non zero - enable IRQ */
+ CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk |
+ CMSDK_TIMER_CTRL_SELEXTCLK_Msk |CMSDK_TIMER_CTRL_EN_Msk);
+ else { /* zero - do not enable IRQ */
+ CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk |
+ CMSDK_TIMER_CTRL_SELEXTCLK_Msk); /* enable timer */
+ }
+ }
+
+/**
+ *
+ * @brief Initialises the timer to use the internal clock but with an external enable. It also specifies the timer reload value and whether IRQ is enabled or not.
+ *
+ * @param *CMSDK_TIMER Timer Pointer
+ * @param reload The value to which the timer is to be set after an underflow has occurred
+ * @param irq_en Defines whether the timer IRQ is to be enabled
+ * @return none
+ *
+ *
+ */
+
+ void CMSDK_timer_Init_ExtEnable(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,
+ uint32_t irq_en)
+ {
+ CMSDK_TIMER->CTRL = 0;
+ CMSDK_TIMER->VALUE = reload;
+ CMSDK_TIMER->RELOAD = reload;
+ if (irq_en!=0) /* non zero - enable IRQ */
+ CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk |
+ CMSDK_TIMER_CTRL_SELEXTEN_Msk | CMSDK_TIMER_CTRL_EN_Msk);
+ else { /* zero - do not enable IRQ */
+ CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk |
+ CMSDK_TIMER_CTRL_SELEXTEN_Msk); /* enable timer */
+ }
+ }
+
+
+ /*UART driver functions*/
+
+/**
+ *
+ * @brief Initialises the UART specifying the UART Baud rate divider value and whether the send and recieve functionality is enabled. It also specifies which of the various interrupts are enabled.
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @param divider The value to which the UART baud rate divider is to be set
+ * @param tx_en Defines whether the UART transmit is to be enabled
+ * @param rx_en Defines whether the UART receive is to be enabled
+ * @param tx_irq_en Defines whether the UART transmit buffer full interrupt is to be enabled
+ * @param rx_irq_en Defines whether the UART receive buffer full interrupt is to be enabled
+ * @param tx_ovrirq_en Defines whether the UART transmit buffer overrun interrupt is to be enabled
+ * @param rx_ovrirq_en Defines whether the UART receive buffer overrun interrupt is to be enabled
+ * @return 1 if initialisation failed, 0 if successful.
+ */
+
+ uint32_t CMSDK_uart_init(CMSDK_UART_TypeDef *CMSDK_UART, uint32_t divider, uint32_t tx_en,
+ uint32_t rx_en, uint32_t tx_irq_en, uint32_t rx_irq_en, uint32_t tx_ovrirq_en, uint32_t rx_ovrirq_en)
+ {
+ uint32_t new_ctrl=0;
+
+ if (tx_en!=0) new_ctrl |= CMSDK_UART_CTRL_TXEN_Msk;
+ if (rx_en!=0) new_ctrl |= CMSDK_UART_CTRL_RXEN_Msk;
+ if (tx_irq_en!=0) new_ctrl |= CMSDK_UART_CTRL_TXIRQEN_Msk;
+ if (rx_irq_en!=0) new_ctrl |= CMSDK_UART_CTRL_RXIRQEN_Msk;
+ if (tx_ovrirq_en!=0) new_ctrl |= CMSDK_UART_CTRL_TXORIRQEN_Msk;
+ if (rx_ovrirq_en!=0) new_ctrl |= CMSDK_UART_CTRL_RXORIRQEN_Msk;
+
+ CMSDK_UART->CTRL = 0; /* Disable UART when changing configuration */
+ CMSDK_UART->BAUDDIV = divider;
+ CMSDK_UART->CTRL = new_ctrl; /* Update CTRL register to new value */
+
+ if((CMSDK_UART->STATE & (CMSDK_UART_STATE_RXOR_Msk | CMSDK_UART_STATE_TXOR_Msk))) return 1;
+ else return 0;
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return RxBufferFull
+ *
+ * @brief Returns whether the RX buffer is full.
+ */
+
+ uint32_t CMSDK_uart_GetRxBufferFull(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ return ((CMSDK_UART->STATE & CMSDK_UART_STATE_RXBF_Msk)>> CMSDK_UART_STATE_RXBF_Pos);
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return TxBufferFull
+ *
+ * @brief Returns whether the TX buffer is full.
+ */
+
+ uint32_t CMSDK_uart_GetTxBufferFull(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ return ((CMSDK_UART->STATE & CMSDK_UART_STATE_TXBF_Msk)>> CMSDK_UART_STATE_TXBF_Pos);
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @param txchar Character to be sent
+ * @return none
+ *
+ * @brief Sends a character to the TX buffer for transmission.
+ */
+
+ void CMSDK_uart_SendChar(CMSDK_UART_TypeDef *CMSDK_UART, char txchar)
+ {
+ while(CMSDK_UART->STATE & CMSDK_UART_STATE_TXBF_Msk);
+ CMSDK_UART->DATA = (uint32_t)txchar;
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return rxchar
+ *
+ * @brief returns the character from the RX buffer which has been received.
+ */
+
+ char CMSDK_uart_ReceiveChar(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ while(!(CMSDK_UART->STATE & CMSDK_UART_STATE_RXBF_Msk));
+ return (char)(CMSDK_UART->DATA);
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return 0 - No overrun
+ * @return 1 - TX overrun
+ * @return 2 - RX overrun
+ * @return 3 - TX & RX overrun
+ *
+ * @brief returns the current overrun status of both the RX & TX buffers.
+ */
+
+
+ uint32_t CMSDK_uart_GetOverrunStatus(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ return ((CMSDK_UART->STATE & (CMSDK_UART_STATE_RXOR_Msk | CMSDK_UART_STATE_TXOR_Msk))>>CMSDK_UART_STATE_TXOR_Pos);
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return 0 - No overrun
+ * @return 1 - TX overrun
+ * @return 2 - RX overrun
+ * @return 3 - TX & RX overrun
+ *
+ * @brief Clears the overrun status of both the RX & TX buffers and then returns the current overrun status.
+ */
+
+ uint32_t CMSDK_uart_ClearOverrunStatus(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ CMSDK_UART->STATE = (CMSDK_UART_STATE_RXOR_Msk | CMSDK_UART_STATE_TXOR_Msk);
+ return ((CMSDK_UART->STATE & (CMSDK_UART_STATE_RXOR_Msk | CMSDK_UART_STATE_TXOR_Msk))>>CMSDK_UART_STATE_TXOR_Pos);
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return BaudDiv
+ *
+ * @brief Returns the current UART Baud rate divider. Note that the Baud rate divider is the difference between the clock frequency and the Baud frequency.
+ */
+
+ uint32_t CMSDK_uart_GetBaudDivider(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ return CMSDK_UART->BAUDDIV;
+ }
+
+ /**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return TXStatus
+ *
+ * @brief Returns the TX interrupt status.
+ */
+
+ uint32_t CMSDK_uart_GetTxIRQStatus(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ return ((CMSDK_UART->INTSTATUS & CMSDK_UART_CTRL_TXIRQ_Msk)>>CMSDK_UART_CTRL_TXIRQ_Pos);
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return RXStatus
+ *
+ * @brief Returns the RX interrupt status.
+ */
+
+ uint32_t CMSDK_uart_GetRxIRQStatus(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ return ((CMSDK_UART->INTSTATUS & CMSDK_UART_CTRL_RXIRQ_Msk)>>CMSDK_UART_CTRL_RXIRQ_Pos);
+ }
+
+ /**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return none
+ *
+ * @brief Clears the TX buffer full interrupt status.
+ */
+
+ void CMSDK_uart_ClearTxIRQ(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ CMSDK_UART->INTCLEAR = CMSDK_UART_CTRL_TXIRQ_Msk;
+ }
+
+/**
+ *
+ * @param *CMSDK_UART UART Pointer
+ * @return none
+ *
+ * @brief Clears the RX interrupt status.
+ */
+
+ void CMSDK_uart_ClearRxIRQ(CMSDK_UART_TypeDef *CMSDK_UART)
+ {
+ CMSDK_UART->INTCLEAR = CMSDK_UART_CTRL_RXIRQ_Msk;
+ }
+
+
+ /*GPIO driver functions*/
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param outenable Bit pattern to be used to set output enable register
+ * @return none
+ *
+ * @brief Sets pins on a port as an output. Set the bit corresponding to the pin number to 1 for output i.e. Set bit 1 of outenable to 1 to set pin 1 as an output. This function is thread safe.
+ */
+
+ void CMSDK_gpio_SetOutEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t outenableset)
+ {
+ CMSDK_GPIO->OUTENABLESET = outenableset;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param outenable Bit pattern to be used to set output enable register
+ * @return none
+ *
+ * @brief Sets pins on a port as an input. Set the bit corresponding to the pin number to 1 for input i.e. Set bit 1 of outenable to 1 to set pin 1 as an input. This function is thread safe.
+ */
+
+ void CMSDK_gpio_ClrOutEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t outenableclr)
+ {
+ CMSDK_GPIO->OUTENABLECLR = outenableclr;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @return outputstatus
+ *
+ * @brief returns a uint32_t which defines the whether pins on a port are set as inputs or outputs i.e. if bit 1 of the returned uint32_t is set to 1 then this means that pin 1 is an output.
+ */
+
+ uint32_t CMSDK_gpio_GetOutEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO)
+ {
+ return CMSDK_GPIO->OUTENABLESET;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param AltFunc uint32_t to specify whether the alternate function for the pins on the port is enabled
+ * @return none
+ *
+ * @brief enables the alternative function for pins. Set the bit corresponding to the pin number to 1 for alternate function i.e. Set bit 1 of ALtFunc to 1 to set pin 1 to its alternative function. This function is thread safe.
+ */
+
+ void CMSDK_gpio_SetAltFunc(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t AltFuncset)
+ {
+ CMSDK_GPIO->ALTFUNCSET = AltFuncset;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param AltFunc uint32_t to specify whether the alternate function for the pins on the port is enabled
+ * @return none
+ *
+ * @brief disables the alternative function for pins. Set the bit corresponding to the pin number to 1 to disable alternate function i.e. Set bit 1 of ALtFunc to 1 to set pin 1 to the orignal output function. This function is thread safe.
+ */
+
+ void CMSDK_gpio_ClrAltFunc(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t AltFuncclr)
+ {
+ CMSDK_GPIO->ALTFUNCCLR = AltFuncclr;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @return AltFuncStatus
+ *
+ * @brief returns a uint32_t which defines the whether pins on a port are set to their alternative or their original output functionality i.e. if bit 1 of the returned uint32_t is set to 1 then this means that pin 1 is set to its alternative function.
+ */
+
+ uint32_t CMSDK_gpio_GetAltFunc(CMSDK_GPIO_TypeDef *CMSDK_GPIO)
+ {
+ return CMSDK_GPIO->ALTFUNCSET;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to clear the Interrupt
+ * @return NewIntStatus
+ *
+ * @brief Clears the interrupt flag for the specified pin and then returns the new interrupt status of the pin. This function is thread safe.
+ */
+
+ uint32_t CMSDK_gpio_IntClear(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTCLEAR = (1 << Num);
+
+ return CMSDK_GPIO->INTSTATUS;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to enable the Interrupt
+ * @return NewIntEnStatus
+ *
+ * @brief Enables interrupts for the specified pin and then returns the new interrupt enable status of the pin. This function is thread safe.
+ */
+
+ uint32_t CMSDK_gpio_SetIntEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTENSET = (1 << Num);
+
+ return CMSDK_GPIO->INTENSET;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to disable the Interrupt
+ * @return NewIntEnStatus
+ *
+ * @brief Disables interrupts for the specified pin and then returns the new interrupt enable status of the pin. This function is thread safe.
+ */
+
+ uint32_t CMSDK_gpio_ClrIntEnable(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTENCLR = (1 << Num);
+
+ return CMSDK_GPIO->INTENCLR;
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to set the Interrupt type
+ * @return none
+ *
+ * @brief Changes the interrupt type for the specified pin to a high level interrupt. This function is thread safe.
+ */
+
+ void CMSDK_gpio_SetIntHighLevel(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTTYPECLR = (1 << Num); /* Clear INT TYPE bit */
+ CMSDK_GPIO->INTPOLSET = (1 << Num); /* Set INT POLarity bit */
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to set the Interrupt type
+ * @return none
+ *
+ * @brief Changes the interrupt type for the specified pin to a rising edge interrupt. This function is thread safe.
+ */
+
+ void CMSDK_gpio_SetIntRisingEdge(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTTYPESET = (1 << Num); /* Set INT TYPE bit */
+ CMSDK_GPIO->INTPOLSET = (1 << Num); /* Set INT POLarity bit */
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to set the Interrupt type
+ * @return none
+ *
+ * @brief Changes the interrupt type for the specified pin to a low level interrupt. This function is thread safe.
+ */
+
+ void CMSDK_gpio_SetIntLowLevel(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTTYPECLR = (1 << Num); /* Clear INT TYPE bit */
+ CMSDK_GPIO->INTPOLCLR = (1 << Num); /* Clear INT POLarity bit */
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param Num The pin number for which to set the Interrupt type
+ * @return none
+ *
+ * @brief Changes the interrupt type for the specified pin to a falling edge interrupt. This function is thread safe.
+ */
+
+ void CMSDK_gpio_SetIntFallingEdge(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t Num)
+ {
+ CMSDK_GPIO->INTTYPESET = (1 << Num); /* Set INT TYPE bit */
+ CMSDK_GPIO->INTPOLCLR = (1 << Num); /* Clear INT POLarity bit */
+ }
+
+/**
+ *
+ * @param *CMSDK_GPIO GPIO Pointer
+ * @param mask The output port mask
+ * @param value The value to output to the specified port
+ * @return none
+ *
+ * @brief Outputs the specified value on the desired port using the user defined mask to perform Masked access.
+ */
+
+ void CMSDK_gpio_MaskedWrite(CMSDK_GPIO_TypeDef *CMSDK_GPIO, uint32_t value, uint32_t mask)
+ {
+ CMSDK_GPIO->LB_MASKED[0x00FF & mask] = value;
+ CMSDK_GPIO->UB_MASKED[((0xFF00 & mask) >> 8)] = value;
+ }
+
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/GCC/startup_CMSDK_CM0.s b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/GCC/startup_CMSDK_CM0.s
new file mode 100644
index 0000000000000000000000000000000000000000..b67683a6b858e8feec012d4c6a566323c8dadce9
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/GCC/startup_CMSDK_CM0.s
@@ -0,0 +1,270 @@
+/**************************************************************************//**
+ * @file startup_CMSDK_CM0.s
+ * @brief CMSIS Cortex-M0 Core Device Startup File for
+ * Device CMSDK_CM0
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note Should use with GCC for ARM Embedded Processors
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/* startup_CMSDK_CM3.s: Startup file for CMSDK device series */
+/*****************************************************************************/
+/* Version: GNU Tools for ARM Embedded Processors */
+/*****************************************************************************/
+
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+
+/*
+// <h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x200
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+
+/*
+// <h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+
+/* Vector Table */
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long UARTRX0_Handler /* 16+ 0: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 16+ 1: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 16+ 2: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 16+ 3: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 16+ 4: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 16+ 5: UART 2 TX Handler */
+ .long PORT0_COMB_Handler /* 16+ 6: GPIO Port 0 Combined Handler */
+ .long PORT1_COMB_Handler /* 16+ 7: GPIO Port 1 Combined Handler */
+ .long TIMER0_Handler /* 16+ 8: TIMER 0 handler */
+ .long TIMER1_Handler /* 16+ 9: TIMER 1 handler */
+ .long DUALTIMER_HANDLER /* 16+10: Dual timer 2 handler */
+ .long 0 /* 16+11: Reserved */
+ .long UARTOVF0_Handler /* 16+12: UART 0 Overflow Handler */
+ .long UARTOVF1_Handler /* 16+13: UART 1 Overflow Handler */
+ .long UARTOVF2_Handler /* 16+14: UART 2 Overflow Handler */
+ .long DMA_Handler /* 16+15: DMA done + error Handler */
+ .long PORT0_0_Handler /* 16+16: GPIO Port 0 pin 0 Handler */
+ .long PORT0_1_Handler /* 16+17: GPIO Port 0 pin 1 Handler */
+ .long PORT0_2_Handler /* 16+18: GPIO Port 0 pin 2 Handler */
+ .long PORT0_3_Handler /* 16+19: GPIO Port 0 pin 3 Handler */
+ .long PORT0_4_Handler /* 16+20: GPIO Port 0 pin 4 Handler */
+ .long PORT0_5_Handler /* 16+21: GPIO Port 0 pin 5 Handler */
+ .long PORT0_6_Handler /* 16+22: GPIO Port 0 pin 6 Handler */
+ .long PORT0_7_Handler /* 16+23: GPIO Port 0 pin 7 Handler */
+ .long PORT0_8_Handler /* 16+24: GPIO Port 0 pin 8 Handler */
+ .long PORT0_9_Handler /* 16+25: GPIO Port 0 pin 9 Handler */
+ .long PORT0_10_Handler /* 16+26: GPIO Port 0 pin 10 Handler */
+ .long PORT0_11_Handler /* 16+27: GPIO Port 0 pin 11 Handler */
+ .long PORT0_12_Handler /* 16+28: GPIO Port 0 pin 12 Handler */
+ .long PORT0_13_Handler /* 16+29: GPIO Port 0 pin 13 Handler */
+ .long PORT0_14_Handler /* 16+30: GPIO Port 0 pin 14 Handler */
+ .long PORT0_15_Handler /* 16+31: GPIO Port 0 pin 15 Handler */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC1
+.LC0:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .LC0
+.LC1:
+
+#ifdef __STARTUP_CLEAR_BSS
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * Loop to zero out BSS section, which uses following symbols
+ * in linker script:
+ * __bss_start__: start of BSS section. Must align to 4
+ * __bss_end__: end of BSS section. Must align to 4
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ subs r2, r1
+ ble .LC3
+
+ movs r0, 0
+.LC2:
+ str r0, [r1, r2]
+ subs r2, 4
+ bge .LC2
+.LC3:
+#endif /* __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ /* bl SystemInit */
+ ldr r0,=SystemInit
+ blx r0
+#endif
+
+ bl _start
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+/* System Exception Handlers */
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+
+/* IRQ Handlers */
+
+ def_default_handler UARTRX0_Handler
+ def_default_handler UARTTX0_Handler
+ def_default_handler UARTRX1_Handler
+ def_default_handler UARTTX1_Handler
+ def_default_handler UARTRX2_Handler
+ def_default_handler UARTTX2_Handler
+ def_default_handler PORT0_COMB_Handler
+ def_default_handler PORT1_COMB_Handler
+ def_default_handler TIMER0_Handler
+ def_default_handler TIMER1_Handler
+ def_default_handler DUALTIMER_HANDLER
+ def_default_handler UARTOVF0_Handler
+ def_default_handler UARTOVF1_Handler
+ def_default_handler UARTOVF2_Handler
+ def_default_handler DMA_Handler
+ def_default_handler PORT0_0_Handler
+ def_default_handler PORT0_1_Handler
+ def_default_handler PORT0_2_Handler
+ def_default_handler PORT0_3_Handler
+ def_default_handler PORT0_4_Handler
+ def_default_handler PORT0_5_Handler
+ def_default_handler PORT0_6_Handler
+ def_default_handler PORT0_7_Handler
+ def_default_handler PORT0_8_Handler
+ def_default_handler PORT0_9_Handler
+ def_default_handler PORT0_10_Handler
+ def_default_handler PORT0_11_Handler
+ def_default_handler PORT0_12_Handler
+ def_default_handler PORT0_13_Handler
+ def_default_handler PORT0_14_Handler
+ def_default_handler PORT0_15_Handler
+
+
+ /*
+ def_default_handler Default_Handler
+ .weak DEF_IRQHandler
+ .set DEF_IRQHandler, Default_Handler
+ */
+ .end
+
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/system_CMSDK_CM0.c b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/system_CMSDK_CM0.c
new file mode 100644
index 0000000000000000000000000000000000000000..9056bf4c95d26ee29235e0964306dac220315f69
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/system_CMSDK_CM0.c
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file system_CMSDK_CM0.c
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
+ * Device CMSDK
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "CMSDK_CM0.h"
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define XTAL (100000000UL) /* Oscillator frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemFrequency = XTAL; /*!< System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock = XTAL; /*!< Processor Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ SystemCoreClock = XTAL;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ SystemCoreClock = XTAL;
+}
diff --git a/Cortex-M0/nanosoc/software/common/bootloader/bootloader.c b/Cortex-M0/nanosoc/software/common/bootloader/bootloader.c
new file mode 100644
index 0000000000000000000000000000000000000000..fcebe2cac733404a2ddbd9607c2914cf5fc2620c
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/bootloader/bootloader.c
@@ -0,0 +1,142 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+//
+// Simple boot loader
+// - display a message that the boot loader is running
+// - clear remap control (user flash accessible from address 0x0)
+// - execute program from user flash
+//
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+void UartStdOutInit(void)
+{
+// CMSDK_UART2->BAUDDIV = 16;
+// CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only
+ CMSDK_UART2->BAUDDIV = 2080; //(20MHz/9600)
+ CMSDK_UART2->CTRL = 0x01; //TX only, standard UART
+ CMSDK_USRT2->CTRL = 0x01; //TX only, FT1248 USRT
+ CMSDK_GPIO1->ALTFUNCSET = (1<<5);
+ return;
+}
+// Output a character
+unsigned char UartPutc(unsigned char my_ch)
+{
+/// while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
+/// CMSDK_UART2->DATA = my_ch; // write to transmit holding register
+/// if ((CMSDK_USRT2->STATE & 1) == 0)
+ while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
+ if ((CMSDK_USRT2->STATE & 1) == 0)
+ CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
+ return (my_ch);
+}
+// Uart string output
+void UartPuts(unsigned char * mytext)
+{
+ unsigned char CurrChar;
+ do {
+ CurrChar = *mytext;
+ if (CurrChar != (char) 0x0) {
+ UartPutc(CurrChar); // Normal data
+ }
+ *mytext++;
+ } while (CurrChar != 0);
+ return;
+}
+#if defined ( __CC_ARM )
+/* ARM RVDS or Keil MDK */
+__asm void FlashLoader_ASM(void)
+{
+ MOVS R0,#0
+ LDR R1,[R0] ; Get initial MSP value
+ MOV SP, R1
+ LDR R1,[R0, #4] ; Get initial PC value
+ BX R1
+}
+
+#else
+/* ARM GCC */
+void FlashLoader_ASM(void) __attribute__((naked));
+void FlashLoader_ASM(void)
+{
+ __asm(" movs r0,#0\n"
+ " ldr r1,[r0]\n" /* Get initial MSP value */
+ " mov sp, r1\n"
+ " ldr r1,[r0, #4]\n" /* Get initial PC value */
+ " bx r1\n");
+}
+
+#endif
+
+void FlashLoader(void)
+{
+ if (CMSDK_SYSCON->REMAP==0) {
+ /* Remap is already cleared. Something has gone wrong.
+ Likely that the user is trying to run bootloader as a test,
+ which is not what this program is for.
+ */
+ UartPuts("@Error: REMAP cleared\n");
+ UartPutc(0x4); // Terminate simulation
+ while (1);
+ }
+ UartPuts("** Remap->RAM2\n"); // CMSDK boot loader\n");
+ CMSDK_SYSCON->REMAP = 0; // Clear remap
+ __DSB();
+ __ISB();
+
+ FlashLoader_ASM();
+};
+
+int main (void)
+{
+ // UART init
+ UartStdOutInit();
+
+ UartPuts("\n\n\nSOCLABS: ARM Cortex-M0 nanosoc\n");
+ FlashLoader();
+ return 0;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.c b/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..88fc02e92ac1053c7db303f7a2ec6987810c6e3a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.c
@@ -0,0 +1,508 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+//==============================================================================
+//
+// CORTEX-M System Design Kit Debug Test
+//
+//==============================================================================
+
+
+// If DBG is present, this test checks:
+//
+// ID value check
+//
+// - Check some ID registers like CPUID, BASEADDRESS,
+//
+// WFI SLEEPDEEP, Debugger Wakeup
+//
+// - Check when processor in deep sleep mode, the debugger can wakeup
+// the processor
+//
+// DAP Access
+//
+// - The test uses the debug tester to read and write to memory using
+// Word, Halfword and Byte accesses.
+//
+//
+// LOCKUP
+//
+// - The test enters the architected lock-up state by accessing faulting
+// memory from within the HardFault handler. The debug tester checks
+// that lockup has been entered and checks that the LOCKUP pin has been
+// driven by reading the example MCU internal debug register.
+//
+//
+
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#include "core_cm0.h"
+
+#else
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#include "core_cm0plus.h"
+
+#else
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#include "core_cm3.h"
+
+#else
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#include "core_cm4.h"
+
+#endif
+#endif
+#endif
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+#include "mcu_debugtester_interface.h" // For definition of interface to the debug tester
+#include "CMSDK_driver.h"
+
+
+#include "config_id.h"
+#include "debug_tests.h"
+#include "debugtester_functions.h"
+
+
+///////////////////////////////////////////////////////////////////////
+// Global Variables to track test progress
+///////////////////////////////////////////////////////////////////////
+
+uint32_t Errors = 0;
+volatile uint32_t ExpectHardFault = 0;
+uint32_t HardFaultTaken = 0;
+
+typedef void (* FuncPtr)(void);
+
+
+///////////////////////////////////////////////////////////////////////
+//Function prototype
+///////////////////////////////////////////////////////////////////////
+void HardFault_Handler(void);
+
+
+///////////////////////////////////////////////////////////////////////
+//Main code
+///////////////////////////////////////////////////////////////////////
+
+int main (void)
+{
+
+ // UART init
+ UartStdOutInit();
+
+ // This test requires DBG to be present.
+ // If EXPECTED_DBG indicates that DBG is not present, this test will
+ // PASS to allow a clean test run.
+
+ printf("%s - Debug Test\n", MCU_CPU_NAME);
+
+ if(EXPECTED_DBG != 1)
+ {
+ puts("EXPECTED_DBG parameter set to 0\n** TEST SKIPPED **\n");
+ UartEndSimulation(); // stop simulation
+ return 1;
+ }
+ else
+ {
+
+ EnableDebugTester();
+
+ puts("Debug Test is now enabled\n");
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Initialise debug tester to correct protocol
+ /////////////////////////////////////////////////////////////////////////////
+ //DAP must be power down when setting the interface mode
+
+ puts("Setting debug interface mode\n");
+ if(EXPECTED_JTAGnSW)
+ {
+ CallDebugTester(FnSetInterfaceJTAG);
+ }
+ else
+ {
+ CallDebugTester(FnSetInterfaceSW);
+ }
+
+ puts("Debug Test interface set successfully\n");
+
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Check DAP powerup
+ /////////////////////////////////////////////////////////////////////////////
+ puts("Checking DAP powerup:\n");
+ if (CallDebugTester (FnDAPPowerUp) == TEST_PASS )
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Check CPU ID
+ /////////////////////////////////////////////////////////////////////////////
+ puts("Checking CPU ID:\n");
+
+ // Write CPUID address to stacktop
+ DEBUGTESTERDATA[0] = 0xE000ED00;
+
+ // Call GetAPMem()
+ if( CallDebugTester(FnGetAPMem) == TEST_PASS )
+ {
+ // Check returned value matches expected CPU ID
+
+ if(DEBUGTESTERDATA[0] == MCU_CPU_ID_VALUE)
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ printf("\tFAIL - Expected %x, got %x\n", MCU_CPU_ID_VALUE, DEBUGTESTERDATA[0]);
+ }
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+
+ if (EXPECTED_SIMPLE_CHECK)
+ {
+ //Above check is enough
+ }
+ else
+ {
+ //Complex check start here
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Check DP ID
+ /////////////////////////////////////////////////////////////////////////////
+ puts("Checking DP ID:\n");
+
+ DEBUGTESTERDATA[0] = 0x0; //DPIDR
+
+ if (CallDebugTester (FnGetDPReg) == TEST_PASS )
+ {
+ if(DEBUGTESTERDATA[0] == MCU_DP_IDR_VALUE)
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ printf("\tFAIL - Expected %x, got %x\n", MCU_DP_IDR_VALUE, DEBUGTESTERDATA[0]);
+ }
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Check AP ID
+ /////////////////////////////////////////////////////////////////////////////
+
+ puts("Checking AP ID:\n");
+
+ DEBUGTESTERDATA[0] = 0xFC; //APIDR
+
+ if (CallDebugTester (FnGetAPReg) == TEST_PASS )
+ {
+ if(DEBUGTESTERDATA[0] == MCU_AP_IDR_VALUE)
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ printf("\tFAIL - Expected %x, got %x\n", MCU_AP_IDR_VALUE, DEBUGTESTERDATA[0]);
+ }
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Check BASE
+ /////////////////////////////////////////////////////////////////////////////
+ puts("Checking BASE:\n");
+
+ DEBUGTESTERDATA[0] = 0xF8; //APBASE
+
+ if (CallDebugTester (FnGetAPReg) == TEST_PASS )
+ {
+ if(DEBUGTESTERDATA[0] == MCU_AP_BASE_VALUE)
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ printf("\tFAIL - Expected %x, got %x\n", MCU_AP_BASE_VALUE, DEBUGTESTERDATA[0]);
+ }
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+
+ /////////////////////////////////////////////////////////////////////////////
+ // WFI SLEEPDEEP, Debugger Wakeup
+ /////////////////////////////////////////////////////////////////////////////
+ puts("WFI SLEEPDEEP, Debugger Wakeup:\n");
+ // Clear data value
+ DEBUGTESTERDATA[0] = 0;
+ // Ensure we SLEEPDEEP - SLEEPDEEP should be set
+ SET_SLEEP_DEEP();
+
+ // Wakeup will be due to the debugger
+ StartDebugTester(FnConnectWakeUnhalt);
+
+ // Wait For Interrupt loop
+ while(DEBUGTESTERDATA[0] == 0)
+ {
+ __WFI();
+ __ISB();
+ }
+
+ if(CheckDebugTester() == TEST_PASS)
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+
+ /////////////////////////////////////////////////////////////////////////////
+ // DAP Access
+ //
+ // Check Word, Halfword and Byte accesses to memory
+ // via the DAP, using the debug tester.
+ /////////////////////////////////////////////////////////////////////////////
+
+ puts("DAP Access:\n");
+
+ DEBUGTESTERDATA[0] = 0;
+
+ if( CallDebugTester(FnDAPAccess) == TEST_PASS )
+ {
+ // Check returned value from debug tester
+ puts("DAP Access: Test pass, checking returned values ....\n");
+ printf("After testing: DEBUGTESTERDATA[0] == %x :\n",DEBUGTESTERDATA[0] );
+ puts("\tWORD: ");
+
+ if( (DEBUGTESTERDATA[0]) & 0x1 )
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+ puts("\tHALFWORD: ");
+
+ if( (DEBUGTESTERDATA[0]) & 0x2 )
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+ puts("\tBYTE: ");
+
+ if( (DEBUGTESTERDATA[0]) & 0x4 )
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+ // Clear data value
+ DEBUGTESTERDATA[0] = 0;
+
+
+ /////////////////////////////////////////////////////////////////////////////
+ // LOCKUP
+ //
+ // Create LOCKUP scenario by accessing faulting instruction within the HardFault Handler
+ // We enter the HardFault Handler by accessing faulting instruction
+ // The debugger will check for lockup before allowing execution to resume.
+ /////////////////////////////////////////////////////////////////////////////
+
+ // Set up memory locations pointed to by FaultFunction
+ // to contain instruction code that will cause a hardware fault
+ //
+
+ // HardwareFault is generated by accessing the undefined instruction
+ // so we can generate a fault like this:
+ // xxxxx (0xf123) // non-exist instruction like 0xf123
+ // BX LR (0x4770) //
+
+ //
+ // Set up a faulting version and a non faulting version.
+ // The debugger will copy the non-faulting version over the
+ // faulting version to enable the MCU to return to the function
+ // without incurring further faults.
+ //
+
+ // Little Endian Encodings:
+ // FAULTLOAD 0xf123 //Non-exist instruction 0xf123
+ // NONFAULT 0x0000 //NOP
+ // RETURN 0x4770 //BX LR
+
+ if(EXPECTED_BE)
+ {
+ // Non Faulting
+ DEBUGTESTERDATA[2] = 0x00007047;
+ // Faulting
+ DEBUGTESTERDATA[3] = 0x23f17047;
+ }
+ else
+ {
+ // Non Faulting
+ DEBUGTESTERDATA[2] = 0x47700000;
+ // Faulting
+ DEBUGTESTERDATA[3] = 0x4770f123;
+ }
+
+
+ puts("LOCKUP:\n");
+
+ ExpectHardFault = 1;
+
+
+ // Start Debug Tester function that will get us out of Lockup
+ StartDebugTester(FnConnectCheckUnlockup);
+
+ while(HardFaultTaken == 0)
+ {
+ ((FuncPtr) ( 1+(uint32_t)(&(DEBUGTESTERDATA[3]))) ) ();
+ }
+
+ printf("HardFaultTaken = %x\n", HardFaultTaken);
+
+ // Get here if we took HardFault -> LOCKUP -> Debugger returned us
+
+ if( (CheckDebugTester() == TEST_PASS) && HardFaultTaken)
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+ //Complex check end here
+ }
+
+ /////////////////////////////////////////////////////////////////////////////
+ // Check DAP powerdown
+ /////////////////////////////////////////////////////////////////////////////
+ puts("Checking DAP power down:\n");
+ if (CallDebugTester (FnDAPPowerDown) == TEST_PASS )
+ {
+ puts("\tPASS\n");
+ }
+ else
+ {
+ Errors++;
+ puts("\tFAIL\n");
+ }
+
+
+ //Print final test result
+ if (Errors == 0) {
+ puts("** TEST PASSED **\n");
+ } else {
+ printf("** TEST FAILED ** with Error code:%d\n", Errors);
+ }
+
+ DisableDebugTester();
+
+ return Errors;
+ }
+}
+
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Hardware Fault Handlers
+/////////////////////////////////////////////////////////////////////////////
+void HardFault_Handler(void)
+{
+ // The HardFault Handler is used for testing LOCKUP in this test
+
+ if(ExpectHardFault == 1)
+ {
+ // Tell main() that we took the HardFault
+ HardFaultTaken = 1;
+
+ // Access the undefined instruction to take core into LOCKUP
+ ((FuncPtr) (1+(uint32_t)(&(DEBUGTESTERDATA[3])))) (); //Branch to the undefined instruction address
+ //with the LSB of the instruction to be 1
+ }
+ else
+ {
+ // Not expecting a fault
+ puts("Unexpected HardFault - FAIL\n");
+ }
+}
diff --git a/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h b/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h
new file mode 100644
index 0000000000000000000000000000000000000000..3c4602ea2f713c9b6a6e99e5e3bc0303e9c386b1
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h
@@ -0,0 +1,83 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+//==============================================================================
+// Cortex-M0/M0+ Debug test header File
+//==============================================================================
+
+#define TEST_PASS 0
+#define TEST_FAIL 1
+
+//Test command sequence definition
+#define DBG_ESCAPE 0x1B
+#define DBG_CONNECT_ENABLE 0x11
+#define DBG_CONNECT_DISABLE 0x12
+#define DBG_SIM_STOP 0x4
+
+
+// GPIO0 bit allocation
+//
+// CM0_MCU GPIO0 -------------------------------------- Debug Tester
+//
+// GPIO[15] 7 <----------------------------------------< Running
+// GPIO[14] 6 <----------------------------------------< Error
+// GPIO[13] 5 >----------------------------------------> Function Strobe
+// GPIO[12] 4 >----------------------------------------> Function Select bit 4
+// GPIO[11] 3 >----------------------------------------> Function Select bit 3
+// GPIO[10] 2 >----------------------------------------> Function Select bit 2
+// GPIO[9] 1 >----------------------------------------> Function Select bit 1
+// GPIO[8] 0 >----------------------------------------> Function Select bit 0
+//
+#define DEBUG_BIT_LOC 8 //GPIO[8] is the least bit of Function Select
+#define DEBUG_CMD 0x3f<<8 //GPIO [13:8]
+#define DEBUG_STROBE 0x00002000 //GPIO [13]
+#define DEBUG_ERROR 0x00004000 //GPIO [14]
+#define DEBUG_RUNNING 0x00008000 //GPIO [15]
+
+// GPIO1[7] 7
+// GPIO1[6] 6
+// GPIO1[5] 5
+// GPIO1[4] 4
+// GPIO1[3] 3
+// GPIO1[2] 2
+// GPIO1[1] 1
+// GPIO1[0] 0
+
+
+// CM0 MCU's view of the memory shared with the debugtester
+// (4 words above stack top)
+// This macro uses the SP value from the vector table as stacktop
+// The stacktop can not be set to the top of the memory.
+#define DEBUGTESTERDATA ((volatile uint32_t *) *((uint32_t *) 0x0))
+
+
+// A convenient way to access the AHB Default Slave
+// (1st word above top of RAM)
+#define AHBDEFAULTSLAVE ((volatile uint32_t *) ((uint32_t) 0x20010000))
+
+
+//Function definition
+// Ensure we SLEEPDEEP - SLEEPDEEP should be set
+// SCR[2] = SLEEPDEEP
+#define SET_SLEEP_DEEP() SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk
+
diff --git a/Cortex-M0/nanosoc/software/common/demos/dualtimer_demo.c b/Cortex-M0/nanosoc/software/common/demos/dualtimer_demo.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a69f5a51e54c7a3b01ee14640aeecb05279ccb6
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/demos/dualtimer_demo.c
@@ -0,0 +1,877 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/*
+ Dual timer demonstration
+
+ This test demonstrate setting the dual timer in different modes/
+ Since the execution speed of the program can be affected by memory speed
+ and hence result can change, the only checks in this program is the
+ occurrence of interrupts.
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#define PRESCALE_1_1 0
+#define PRESCALE_1_16 1
+#define PRESCALE_1_256 2
+#define NO_IRQ 0
+#define USE_IRQ 1
+
+/* Software variables for interrupt detection */
+volatile int dtimer_irq_expected;
+volatile int dtimer1_irq_occurred;
+volatile int dtimer2_irq_occurred;
+volatile int dtimer_integration_test=0;
+
+/* Demonstration functions */
+void dualtimer_16_free_running_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+void dualtimer_32_free_running_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+void dualtimer_16_periodic_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+void dualtimer_32_periodic_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+void dualtimer_16_one_shot_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+void dualtimer_32_one_shot_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+int dualtimer_integration_test(void);
+int dualtimer_id_check(void);
+
+/* Functions for setting up the dual timer */
+ /* 16-bit free running mode */
+void dualtimer_setup_freerunning16(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt);
+ /* 16-bit periodic mode */
+void dualtimer_setup_periodic16(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt);
+ /* 16-bit free one shot mode */
+void dualtimer_setup_oneshot16(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt);
+ /* 32-bit free running mode */
+void dualtimer_setup_freerunning32(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt);
+ /* 32-bit periodic mode */
+void dualtimer_setup_periodic32(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt);
+ /* 32-bit free one shot mode */
+void dualtimer_setup_oneshot32(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt);
+
+ /* Start a timer */
+void dualtimer_start(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+ /* Stop a timer */
+void dualtimer_stop(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+ /* Clear a timer interrupt request */
+void dualtimer_irq_clear(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx);
+
+ /* Text buffer for displaying value */
+char text_buf[20];
+void int_to_hex(unsigned int value, char text[]);
+
+/* ----------------------------------------------------------------- */
+int main(void)
+{
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Dual Timer Demo - revision $Revision: 371321 $\n");
+
+ if (dualtimer_id_check()!=0) {
+ puts ("** TEST SKIPPED ** Dual timer not present.\n");
+ UartEndSimulation();
+ return 0;}
+
+ puts ("\n--------------------------------");
+ puts ("Timer 1");
+ puts ("--------------------------------\n");
+
+ dualtimer_16_free_running_demo(CMSDK_DUALTIMER1);
+ dualtimer_16_periodic_demo(CMSDK_DUALTIMER1);
+ dualtimer_16_one_shot_demo(CMSDK_DUALTIMER1);
+ dualtimer_32_free_running_demo(CMSDK_DUALTIMER1);
+ dualtimer_32_periodic_demo(CMSDK_DUALTIMER1);
+ dualtimer_32_one_shot_demo(CMSDK_DUALTIMER1);
+
+ puts ("\n--------------------------------");
+ puts ("Timer 2");
+ puts ("--------------------------------\n");
+
+ dualtimer_16_free_running_demo(CMSDK_DUALTIMER2);
+ dualtimer_16_periodic_demo(CMSDK_DUALTIMER2);
+ dualtimer_16_one_shot_demo(CMSDK_DUALTIMER2);
+ dualtimer_32_free_running_demo(CMSDK_DUALTIMER2);
+ dualtimer_32_periodic_demo(CMSDK_DUALTIMER2);
+ dualtimer_32_one_shot_demo(CMSDK_DUALTIMER2);
+
+ puts ("\n--------------------------------");
+ puts ("Integration test");
+ puts ("--------------------------------\n");
+ dualtimer_integration_test();
+
+ puts ("** TEST PASSED ** \n");
+ UartEndSimulation();
+ /* Simulation stops in UartEndSimulation */
+
+}
+/* ----------------------------------------------------------------- */
+/* Detect the ARM ID and part number to see if device is present */
+int dualtimer_id_check(void)
+{
+unsigned char dualtimer_id;
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+ dualtimer_id = HW8_REG(CMSDK_DUALTIMER_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_DUALTIMER_BASE + 0xFE0) != 0x23) ||
+ (HW32_REG(CMSDK_DUALTIMER_BASE + 0xFE4) != 0xB8) ||
+ (dualtimer_id != 0x03))
+ return 1; /* part ID & ARM ID does not match dual timer */
+ else
+ return 0;
+}
+/* ----------------------------------------------------------------- */
+void dualtimer_16_free_running_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ unsigned int read_value;
+ unsigned int i;
+
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+ /* ------------------------------------------------------------- */
+ puts ("16-bit free running mode, prescale = 1:1, no interrupt");
+ /* 16-bit Free running timer, 5000 cycles, prescale = 1:1, no interrupt */
+ dualtimer_setup_freerunning16(CMSDK_DUALTIMERx, 5000, PRESCALE_1_1, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit free running mode, prescale = 1:16, no interrupt");
+ /* 16-bit Free running timer, 200 cycles, prescale = 1:16, no interrupt */
+ dualtimer_setup_freerunning16(CMSDK_DUALTIMERx, 200, PRESCALE_1_16, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit free running mode, prescale = 1:256, no interrupt");
+ /* 16-bit Free running timer, 20 cycles, prescale = 1:256, no interrupt */
+ dualtimer_setup_freerunning16(CMSDK_DUALTIMERx, 20, PRESCALE_1_256, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit free running mode, prescale = 1:1, with interrupt");
+ /* 16-bit Free running timer, 5000 cycles, prescale = 1:1, with interrupt */
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ dualtimer_setup_freerunning16(CMSDK_DUALTIMERx, 5000, PRESCALE_1_1, USE_IRQ);
+ i=0;
+ while (i<1){
+ /* Wait until timer interrupt take place */
+ while ((dtimer1_irq_occurred + dtimer2_irq_occurred)==0);
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ puts (" IRQ");
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+}
+/* ----------------------------------------------------------------- */
+void dualtimer_32_free_running_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ unsigned int read_value;
+ unsigned int i;
+
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+ /* ------------------------------------------------------------- */
+ puts ("32-bit free running mode, prescale = 1:1, no interrupt");
+ /* 32-bit Free running timer, 5000 cycles, prescale = 1:1, no interrupt */
+ dualtimer_setup_freerunning32(CMSDK_DUALTIMERx, 5000, PRESCALE_1_1, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit free running mode, prescale = 1:16, no interrupt");
+ /* 32-bit Free running timer, 200 cycles, prescale = 1:16, no interrupt */
+ dualtimer_setup_freerunning32(CMSDK_DUALTIMERx, 200, PRESCALE_1_16, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit free running mode, prescale = 1:256, no interrupt");
+ /* 32-bit Free running timer, 20 cycles, prescale = 1:256, no interrupt */
+ dualtimer_setup_freerunning32(CMSDK_DUALTIMERx, 20, PRESCALE_1_256, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit free running mode, prescale = 1:1, with interrupt");
+ /* 32-bit Free running timer, 5000 cycles, prescale = 1:1, with interrupt */
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ dualtimer_setup_freerunning32(CMSDK_DUALTIMERx, 5000, PRESCALE_1_1, USE_IRQ);
+ i=0;
+ while (i<1){
+ /* Wait until timer interrupt take place */
+ while ((dtimer1_irq_occurred + dtimer2_irq_occurred)==0);
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ puts (" IRQ");
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+}
+/* ----------------------------------------------------------------- */
+void dualtimer_16_periodic_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ unsigned int read_value;
+ unsigned int i;
+
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+ /* ------------------------------------------------------------- */
+ puts ("16-bit periodic mode, prescale = 1:1, no interrupt");
+ /* 16-bit periodic timer, 1000 cycles, prescale = 1:1, no interrupt */
+ dualtimer_setup_periodic16(CMSDK_DUALTIMERx, 1000, PRESCALE_1_1, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit periodic mode, prescale = 1:16, no interrupt");
+ /* 16-bit periodic timer, 200 cycles, prescale = 1:16, no interrupt */
+ dualtimer_setup_periodic16(CMSDK_DUALTIMERx, 200, PRESCALE_1_16, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit periodic mode, prescale = 1:256, no interrupt");
+ /* 16-bit periodic timer, 20 cycles, prescale = 1:256, no interrupt */
+ dualtimer_setup_periodic16(CMSDK_DUALTIMERx, 20, PRESCALE_1_256, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit periodic mode, prescale = 1:1, with interrupt x4");
+ /* 16-bit periodic timer, 3000 cycles, prescale = 1:1, with interrupt */
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ dualtimer_setup_periodic16(CMSDK_DUALTIMERx, 3000, PRESCALE_1_1, USE_IRQ);
+ i=0;
+ while (i<4){
+ /* Wait until timer interrupt take place */
+ while ((dtimer1_irq_occurred + dtimer2_irq_occurred)==0);
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ puts (" IRQ");
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+}
+/* ----------------------------------------------------------------- */
+void dualtimer_32_periodic_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ unsigned int read_value;
+ unsigned int i;
+
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+ /* ------------------------------------------------------------- */
+ puts ("32-bit periodic mode, prescale = 1:1, no interrupt");
+ /* 32-bit periodic timer, 1000 cycles, prescale = 1:1, no interrupt */
+ dualtimer_setup_periodic32(CMSDK_DUALTIMERx, 1000, PRESCALE_1_1, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit periodic mode, prescale = 1:16, no interrupt");
+ /* 32-bit periodic timer, 200 cycles, prescale = 1:16, no interrupt */
+ dualtimer_setup_periodic32(CMSDK_DUALTIMERx, 200, PRESCALE_1_16, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit periodic mode, prescale = 1:256, no interrupt");
+ /* 32-bit periodic timer, 20 cycles, prescale = 1:256, no interrupt */
+ dualtimer_setup_periodic32(CMSDK_DUALTIMERx, 20, PRESCALE_1_256, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit periodic mode, prescale = 1:1, with interrupt x4");
+ /* 16-bit periodic timer, 3000 cycles, prescale = 1:1, with interrupt */
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ dualtimer_setup_periodic32(CMSDK_DUALTIMERx, 3000, PRESCALE_1_1, USE_IRQ);
+ i=0;
+ while (i<4){
+ /* Wait until timer interrupt take place */
+ while ((dtimer1_irq_occurred + dtimer2_irq_occurred)==0);
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ puts (" IRQ");
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+}
+/* ----------------------------------------------------------------- */
+void dualtimer_16_one_shot_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ unsigned int read_value;
+ unsigned int i;
+
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+ /* ------------------------------------------------------------- */
+ puts ("16-bit one shot mode, prescale = 1:1, no interrupt");
+ /* 16-bit one shot timer, 2000 cycles, prescale = 1:1, no interrupt */
+ dualtimer_setup_oneshot16(CMSDK_DUALTIMERx, 2000, PRESCALE_1_1, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit one shot mode, prescale = 1:16, no interrupt");
+ /* 16-bit one shot timer, 100 cycles, prescale = 1:16, no interrupt */
+ dualtimer_setup_oneshot16(CMSDK_DUALTIMERx, 100, PRESCALE_1_16, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("16-bit one shot mode, prescale = 1:1, with interrupt");
+ /* 16-bit one shot timer, 3000 cycles, prescale = 1:1, with interrupt */
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ dualtimer_setup_oneshot16(CMSDK_DUALTIMERx, 3000, PRESCALE_1_1, USE_IRQ);
+ i=0;
+ while (i<1){
+ /* Wait until timer interrupt take place */
+ while ((dtimer1_irq_occurred + dtimer2_irq_occurred)==0);
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ puts (" IRQ");
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+}
+/* ----------------------------------------------------------------- */
+void dualtimer_32_one_shot_demo(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ unsigned int read_value;
+ unsigned int i;
+
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+ /* ------------------------------------------------------------- */
+ puts ("32-bit one shot mode, prescale = 1:1, no interrupt");
+ /* 32-bit one shot timer, 2000 cycles, prescale = 1:1, no interrupt */
+ dualtimer_setup_oneshot32(CMSDK_DUALTIMERx, 2000, PRESCALE_1_1, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit one shot mode, prescale = 1:16, no interrupt");
+ /* 32-bit one shot timer, 100 cycles, prescale = 1:16, no interrupt */
+ dualtimer_setup_oneshot32(CMSDK_DUALTIMERx, 100, PRESCALE_1_16, NO_IRQ);
+ i=0;
+ while (i<10){
+ read_value = CMSDK_DUALTIMERx->TimerValue;
+ /* Display value of timer */
+ /* timing of printf can be very different between different toolchain.
+ Use puts instead */
+ int_to_hex(read_value, &text_buf[0]);
+ puts(text_buf);
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ /* ------------------------------------------------------------- */
+ puts ("32-bit one shot mode, prescale = 1:1, with interrupt");
+ /* 32-bit one shot timer, 3000 cycles, prescale = 1:1, with interrupt */
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ dualtimer_setup_oneshot32(CMSDK_DUALTIMERx, 3000, PRESCALE_1_1, USE_IRQ);
+ i=0;
+ while (i<1){
+ /* Wait until timer interrupt take place */
+ while ((dtimer1_irq_occurred + dtimer2_irq_occurred)==0);
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ puts (" IRQ");
+ i++;
+ }
+ dualtimer_stop(CMSDK_DUALTIMERx);
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+ /* Clear software variables for interrupt tests */
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+
+}
+
+
+/* ----------------------------------------------------------------- */
+/* Interrupt handler for dual timer */
+void DUALTIMER_HANDLER(void)
+{
+if (dtimer_integration_test==0) { /* Normal operation mode */
+ /* The Dual Timer interrupt handler are shared by the two timers */
+ if (CMSDK_DUALTIMER1->TimerMIS != 0){
+ dualtimer_irq_clear(CMSDK_DUALTIMER1);
+ dtimer1_irq_occurred++;
+ if (dtimer_irq_expected==0) {
+ puts("ERROR: Unexpected dual timer 1 IRQ");
+ UartEndSimulation(); /* Simulation stops in UartEndSimulation */
+ } /* end if (dtimer1_irq_expected==0) */
+ } /* end if (CMSDK_DUALTIMER1->TimerMIS != 0) */
+ if (CMSDK_DUALTIMER2->TimerMIS != 0){
+ dualtimer_irq_clear(CMSDK_DUALTIMER2);
+ dtimer2_irq_occurred++;
+ if (dtimer_irq_expected==0) {
+ puts("ERROR: Unexpected dual timer 2 IRQ");
+ UartEndSimulation(); /* Simulation stops in UartEndSimulation */
+ } /* end if (dtimer2_irq_expected==0) */
+ } /* end if (CMSDK_DUALTIMER2->TimerMIS != 0) */
+ }
+else { /* Integration test mode */
+ /* Cannot tell which timer interrupt is asserted because
+ ITOP is write only and both timer shared the same interrupt.
+ So increment both variables. */
+ CMSDK_DUALTIMER->ITOP=0;
+ dtimer1_irq_occurred++;
+ dtimer2_irq_occurred++;
+ puts (" [Dualtimer interrupt triggered]");
+ }
+}
+
+/* ----------------------------------------------------------------- */
+/* Functions for setting up the dual timer */
+
+
+/* 16-bit Free running timer mode */
+void dualtimer_setup_freerunning16(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt)
+{
+ int ctrl_val;
+ CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
+ /* Previous timer activities might have trigger interrupt flag,
+ so need to clear it */
+ dualtimer_irq_clear(CMSDK_DUALTIMERx);
+ CMSDK_DUALTIMERx->TimerLoad = cycle;
+
+ ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
+ (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
+ CMSDK_DUALTIMER_CTRL_EN_Msk;
+
+ CMSDK_DUALTIMERx->TimerControl = ctrl_val;
+}
+
+/* 32-bit Free running timer mode */
+void dualtimer_setup_freerunning32(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt)
+{
+ int ctrl_val;
+ CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
+ /* Previous timer activities might have trigger interrupt flag,
+ so need to clear it */
+ dualtimer_irq_clear(CMSDK_DUALTIMERx);
+ CMSDK_DUALTIMERx->TimerLoad = cycle;
+
+ ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
+ (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
+ CMSDK_DUALTIMER_CTRL_EN_Msk |
+ CMSDK_DUALTIMER_CTRL_SIZE_Msk;
+
+ CMSDK_DUALTIMERx->TimerControl = ctrl_val;
+}
+
+/* 16-bit Periodic timer mode */
+void dualtimer_setup_periodic16(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt)
+{
+ int ctrl_val;
+ CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
+ /* Previous timer activities might have trigger interrupt flag,
+ so need to clear it */
+ dualtimer_irq_clear(CMSDK_DUALTIMERx);
+ CMSDK_DUALTIMERx->TimerLoad = cycle;
+
+ ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
+ (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
+ CMSDK_DUALTIMER_CTRL_EN_Msk |
+ CMSDK_DUALTIMER_CTRL_MODE_Msk;
+
+ CMSDK_DUALTIMERx->TimerControl = ctrl_val;
+}
+
+/* 32-bit Periodic timer mode */
+void dualtimer_setup_periodic32(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt)
+{
+ int ctrl_val;
+ CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
+ /* Previous timer activities might have trigger interrupt flag,
+ so need to clear it */
+ dualtimer_irq_clear(CMSDK_DUALTIMERx);
+ CMSDK_DUALTIMERx->TimerLoad = cycle;
+
+ ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
+ (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
+ CMSDK_DUALTIMER_CTRL_EN_Msk |
+ CMSDK_DUALTIMER_CTRL_MODE_Msk|
+ CMSDK_DUALTIMER_CTRL_SIZE_Msk;
+
+ CMSDK_DUALTIMERx->TimerControl = ctrl_val;
+}
+
+/* 16-bit One shot timer mode */
+void dualtimer_setup_oneshot16(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt)
+{
+ int ctrl_val;
+ CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
+ /* Previous timer activities might have trigger interrupt flag,
+ so need to clear it */
+ dualtimer_irq_clear(CMSDK_DUALTIMERx);
+ CMSDK_DUALTIMERx->TimerLoad = cycle;
+
+ ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
+ (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
+ CMSDK_DUALTIMER_CTRL_EN_Msk |
+ CMSDK_DUALTIMER_CTRL_MODE_Msk |
+ CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk;
+
+ CMSDK_DUALTIMERx->TimerControl = ctrl_val;
+}
+
+/* 32-bit One shot timer mode */
+void dualtimer_setup_oneshot32(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx,
+ unsigned int cycle, unsigned int prescale, unsigned int interrupt)
+{
+ int ctrl_val;
+ CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
+ /* Previous timer activities might have trigger interrupt flag,
+ so need to clear it */
+ dualtimer_irq_clear(CMSDK_DUALTIMERx);
+ CMSDK_DUALTIMERx->TimerLoad = cycle;
+
+ ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
+ (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
+ CMSDK_DUALTIMER_CTRL_EN_Msk |
+ CMSDK_DUALTIMER_CTRL_MODE_Msk |
+ CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk|
+ CMSDK_DUALTIMER_CTRL_SIZE_Msk;
+
+ CMSDK_DUALTIMERx->TimerControl = ctrl_val;
+}
+
+/* Demonstrate integration test feature in the dual timer */
+int dualtimer_integration_test(void)
+{
+ int result = 0;
+ /* Instead of triggering timer interrupt using normal timer operation, you can also
+ test the watchdog connection using integration test register.
+ ITCR - bit 0 enable integration test mode
+ ITOP - bit 0 enable timer 1 irq when integration test mode is enabled
+ bit 1 enable timer 2 irq when integration test mode is enabled
+ */
+
+ puts ("Integration test demo");
+ dtimer_integration_test = 1;
+
+ dtimer_irq_expected = 0;
+ dtimer1_irq_occurred = 0;
+ dtimer2_irq_occurred = 0;
+ CMSDK_DUALTIMER->ITOP=0; // Ensure interrupts are not asserted before start
+ CMSDK_DUALTIMER->ITCR=1; // Enable integration test mode
+ if (CMSDK_DUALTIMER->ITCR == 0) {
+ puts (" - Integration Test Control Register read error");
+ result++;
+ }
+ else {
+ dtimer_integration_test = 1;
+ dtimer_irq_expected = 1;
+ NVIC_EnableIRQ(DUALTIMER_IRQn);
+ CMSDK_DUALTIMER->ITOP=1; // Set timer 1 interrupt
+ CMSDK_DUALTIMER->ITOP=0; // Deassert timer 1 interrupt
+
+ if (dtimer1_irq_occurred == 0) {
+ puts (" - Integration Test operation 1 failed");
+ result++;
+ }
+ dtimer1_irq_occurred = 0; /* clear variables */
+ dtimer2_irq_occurred = 0;
+
+ CMSDK_DUALTIMER->ITOP=2; // Set timer 2 interrupt
+ CMSDK_DUALTIMER->ITOP=0; // Deassert timer 2 interrupt
+
+ if (dtimer2_irq_occurred == 0) {
+ puts (" - Integration Test operation 2 failed");
+ result++;
+ }
+ CMSDK_DUALTIMER->ITCR = 0; // Disable integration test mode
+ if (CMSDK_DUALTIMER->ITCR != 0) {
+ puts (" - Integration Control clear error");
+ result++;
+ }
+ }
+ dtimer_integration_test = 0;
+ NVIC_DisableIRQ(DUALTIMER_IRQn);
+
+ if (result != 0) {
+ puts ("ERROR: Integration test failed\n");
+ return (1);
+ } else {
+ puts ("Integration test completed successfully\n");
+ return (0);
+ }
+
+}
+
+
+
+/* Start the timer */
+void dualtimer_start(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ CMSDK_DUALTIMERx->TimerControl |= CMSDK_DUALTIMER_CTRL_EN_Msk;
+}
+/* Stop the timer */
+void dualtimer_stop(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ CMSDK_DUALTIMERx->TimerControl &= ~CMSDK_DUALTIMER_CTRL_EN_Msk;
+}
+/* Clear the interrupt request */
+void dualtimer_irq_clear(CMSDK_DUALTIMER_SINGLE_TypeDef *CMSDK_DUALTIMERx)
+{
+ CMSDK_DUALTIMERx->TimerIntClr = 0;
+}
+/* Convert hex value into text in text buffer */
+void int_to_hex(unsigned int value, char text[])
+{
+ int i=0;
+ int length=0;
+ unsigned int mask = 0xF0000000UL;
+ int nibble;
+
+ /* extra space in front for indent */
+ for (length=0;length<2; length++){
+ text[length] =' '; /* space */
+ }
+ length = 2;
+ /* Remove leading zero */
+ while (((mask & value)==0) & (i!=7)) {
+ i ++;
+ mask = mask >> 4;
+ }
+ while (i!=8) {
+ nibble = (mask & value) >> ((7-i)*4); /* shift to LSB */
+ if (nibble>9) text[length] = (char) (nibble+87); // Convert to ASCII a to f
+ else text[length] = (char) (nibble+48); // Convert to ASCII 0 to 9
+ i++;
+ length++;
+ mask = mask>> 4;
+ }
+ text[length]=(char) 0; /* null termination */
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/demos/interrupt_demo.c b/Cortex-M0/nanosoc/software/common/demos/interrupt_demo.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0598c09fc5db10a6b7ce0af61fa61dea77f7066
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/demos/interrupt_demo.c
@@ -0,0 +1,494 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/*
+ Interrupt demonstration
+
+ This test demonstrate interrupt generation using various peripherals.
+ - using simple timer
+ - using gpio with various configurations
+ - using uart
+
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include "uart_stdout.h"
+#include "CMSDK_driver.h"
+#include <stdio.h>
+
+//
+// Global Variables to track test progress
+//
+
+volatile uint32_t tx_count = 0; /*transmit counter */
+volatile uint32_t rx_count = 0; /*receive counter */
+const char str_tx[12] = "hello world"; /*transmission string*/
+const int uart_str_length = 11;
+volatile char str_rx[12] ; /*string that is received*/
+
+volatile int irq_triggered; /* Detected interrupt operation from GPIO IRQ handler */
+volatile uint32_t timer_stopped = 0; /* timer irq executed and stopped */
+
+//
+// Demonstrations
+//
+
+int TimerExample(void); // Timer interrupt
+int GPIOIntExample(void); // GPIO interrupt
+void UartExample(void); // UART interrupt
+int gpio0_id_check(void); // Detect GPIO 0 present
+int timer0_id_check(void); // Detect Timer 0 present
+int uart0_id_check(void); // Detect UART 0 present
+int uart1_id_check(void); // Detect UART 1 present
+
+// ----------------------------------------------------------
+// Main program
+// ----------------------------------------------------------
+
+int main (void)
+{
+ // UART init
+ UartStdOutInit(); // Initialize UART2 for printf (retargeting)
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Interrupt Demo - revision $Revision: 371321 $\n");
+
+ if (timer0_id_check()!=0) puts ("Timer 0 not present. TimerExample skipped.");
+ else TimerExample(); // Timer 0 interrupt example
+
+ if (gpio0_id_check()!=0) puts ("GPIO 0 not present. GPIOIntExample skipped.");
+ else GPIOIntExample(); // GPIO PORT0 interrupt example
+
+ if ((uart0_id_check()!=0)||(uart1_id_check()!=0))
+ puts ("UART 0 or UART 1 not present. UartExample skipped.");
+ else UartExample(); // Uart interrupt example
+
+ puts ("** TEST PASSED ** \n");
+ UartEndSimulation(); // send test end character to finish test
+ /* Simulation stops in UartEndSimulation */
+
+ return 0;
+}
+
+// ----------------------------------------------------------
+// Timer demo
+// ----------------------------------------------------------
+int TimerExample(void)
+{
+ puts("\n\n\n");
+ puts("+*************************+");
+ puts("* *");
+ puts("* Timer0 Interrupt demo *");
+ puts("* *");
+ puts("+*************************+\n\n");
+
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ // initialise Timer0 with internal clock, with interrupt generation
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0x100, 1);
+
+ while (timer_stopped==0) {
+ __WFE(); // enter sleep
+ }
+ puts(" Timer test done"); // Banner
+
+ return 0;
+}
+// ----------------------------------------------------------
+// UART demo
+// ----------------------------------------------------------
+
+/* Timer IRQ Driven UART Transmission of "hello world"
+
+ - Program UART 0 to operate as transmit only, with transmit IRQ enabled
+ - Program UART 1 to operate as receive only, with receive IRQ enabled
+ - The first character of the "hello world" message is transmit
+ - The rest of the message transmission is handled by UART transmit IRQ, until
+ all characters are transmitted.
+ - The receive process is also handled by UART receive IRQ.
+ - A while loop is used to wait until both transmit and receive has completed the test
+ - When finished then print string received
+ */
+
+
+// ----------------------------------------------------------
+// UART interrupt test
+// ----------------------------------------------------------
+
+void UartExample(void)
+{
+ uint32_t transmission_complete = 0; /*transmission complete bool*/
+
+ puts("+*************************+");
+ puts("* *");
+ puts("* UART Interrupt demo *");
+ puts("* *");
+ puts("+*************************+\n\n");
+
+ CMSDK_gpio_SetAltFunc(CMSDK_GPIO1, 0x000F); //enable alt functions for UART transmission
+
+ // Ensure Interrupt is not pending
+
+ NVIC_ClearPendingIRQ(UARTTX0_IRQn);
+ NVIC_ClearPendingIRQ(UARTRX1_IRQn);
+
+ // Enable Interrupts
+
+ NVIC_EnableIRQ(UARTTX0_IRQn);
+ NVIC_EnableIRQ(UARTRX1_IRQn);
+
+ /* Initialize UART in cross over configuration
+ uint32_t CMSDK_uart_init(CMSDK_UART_TypeDef *CMSDK_UART,
+ uint32_t divider,
+ uint32_t tx_en,
+ uint32_t rx_en,
+ uint32_t tx_irq_en,
+ uint32_t rx_irq_en,
+ uint32_t tx_ovrirq_en,
+ uint32_t rx_ovrirq_en)
+ */
+ /* enable UARTs with selected baud rate
+ UART #0 - transmit
+ UART #1 - receive
+ */
+ CMSDK_uart_init(CMSDK_UART0, 0x200, 1, 0, 1, 0, 0, 0);
+ CMSDK_uart_init(CMSDK_UART1, 0x200, 0, 1, 0, 1, 0, 0);
+
+ rx_count = 0;
+ tx_count = 0;
+
+ printf ("Transmit message : %s\n", str_tx);
+
+ /* Start first character transfer */
+ tx_count++;
+ CMSDK_uart_SendChar(CMSDK_UART0, str_tx[0]); // send the character
+ /* The rest of the transfers are handled by interrupts */
+
+ while(transmission_complete==0) // loop until transmission completed
+ {
+
+ if ((tx_count==uart_str_length) && (rx_count==uart_str_length)) transmission_complete = 1;
+ }
+
+ printf ("Received message : %s\n", str_rx);
+
+
+ NVIC_DisableIRQ(UARTTX0_IRQn); //disable both UART0 TX and UART1 RX IRQs
+ NVIC_DisableIRQ(UARTRX1_IRQn);
+
+ return;
+}
+
+// ----------------------------------------------------------
+// GPIO interrupt test
+// ----------------------------------------------------------
+/*
+ GPIO interrupt example
+
+ - Enable all pins as output
+ - Set DataOut to 0xA ready for a test of all IRQs
+ - Set pin0 as a High Level, pin1 as a Low Level, pin2 as a Rising Edge and pin3 as a Falling Edge,
+ then clear all pending IRQs
+ - enable the CMSDK GPIO interrupt for pins 0, 1, 2, 3.
+ - set Dataout to 0xB to test the high level interrupt on pin 0
+ - if irq_triggered != 0 (set in ISR) then print message saying IRQ occurred and set irq_triggered = 0
+ - else amend err_code
+ - set Dataout to 0x9 to test the low level interrupt on pin 1
+ - if irq_triggered != 0 (set in ISR) then print message saying IRQ occurred and set irq_triggered = 0
+ - else amend err_code
+ - set Dataout to 0xD to test the rising edge interrupt on pin 2
+ - if irq_triggered != 0 (set in ISR) then print message saying IRQ occurred and set irq_triggered = 0
+ - else amend err_code
+ - set Dataout to 0x5 to test the falling edge interrupt on pin 3
+ - if irq_triggered != 0 (set in ISR) then print message saying IRQ occurred and set irq_triggered = 0
+ - else amend err_code
+ - if test on all pins pass the test as a whole passes and return 0 to main
+ - else return an error and print error message
+*/
+int GPIOIntExample(void)
+{
+
+ int i = 0;
+ int irq_counter = 0;
+ int err_code = 0;
+
+ puts("\n\n\n");
+ puts("+*************************+");
+ puts("* *");
+ puts("* GPIO PORT0: Interrupt *");
+ puts("* Example *");
+ puts("* *");
+ puts("+*************************+\n\n");
+
+ CMSDK_gpio_SetOutEnable(CMSDK_GPIO0, 0xFFFF); //set output enable to output on all ports of GPIO 0
+ // By setting the port to output the pins are controllable by software
+
+ CMSDK_GPIO0->DATAOUT = 0xA; // set current I/O port value
+
+ CMSDK_gpio_SetIntHighLevel(CMSDK_GPIO0, 0); //set pin 0 to high level interrupts
+ CMSDK_gpio_SetIntLowLevel(CMSDK_GPIO0, 1); //set pin 1 to low level interrupts
+ CMSDK_gpio_SetIntRisingEdge(CMSDK_GPIO0, 2); //set pin 2 to rising edge interrupts
+ CMSDK_gpio_SetIntFallingEdge(CMSDK_GPIO0, 3); //set pin 3 to falling edge interrupts
+
+ NVIC_ClearPendingIRQ(PORT0_0_IRQn); //clear all global NVIC PORT0 pending interrupts
+ NVIC_ClearPendingIRQ(PORT0_1_IRQn);
+ NVIC_ClearPendingIRQ(PORT0_2_IRQn);
+ NVIC_ClearPendingIRQ(PORT0_3_IRQn);
+
+ NVIC_EnableIRQ(PORT0_0_IRQn); //enable NVIC interrupts on PORT0
+ NVIC_EnableIRQ(PORT0_1_IRQn);
+ NVIC_EnableIRQ(PORT0_2_IRQn);
+ NVIC_EnableIRQ(PORT0_3_IRQn);
+
+ if ((NVIC->ISER[0]>>PORT0_0_IRQn)!=0x0F) { // Cortex-M0 DesignStart only has 16 IRQ
+ printf("Not all of IRQ[%d to %d] are available.\nUse combined GPIO interrupt for test\n\n",
+ PORT0_0_IRQn,PORT0_3_IRQn);
+ NVIC_EnableIRQ(PORT0_ALL_IRQn); //enable combined NVIC interrupts on PORT0
+ }
+
+
+ for(i = 0; i < 4; i++) CMSDK_gpio_SetIntEnable(CMSDK_GPIO0, i); //enable interrupts on pins 0 -3
+
+ CMSDK_GPIO0->DATAOUT = 0xB; // emulating high level input on pin 0.
+
+ puts(" ...Test GPIO0[0]...\n");
+
+ if(irq_triggered){ //if irq flag set then print message else amend error code
+ puts(" High Level IRQ:\n Detected On Pin 0\n\n");
+ irq_triggered = 0;
+ irq_counter++;
+ }
+ else err_code |= (1 << irq_counter);
+
+ CMSDK_GPIO0->DATAOUT = 0x9; // emulating low level input on pin 1.
+
+ puts(" ...Test GPIO0[1]...\n");
+
+ if(irq_triggered){ //if irq flag set then print message else amend error code
+ puts(" Low Level IRQ\n Detected On Pin 0\n\n");
+ irq_triggered = 0;
+ irq_counter++;
+ }
+ else err_code |= (1 << 1);
+
+ CMSDK_GPIO0->DATAOUT = 0xD; // emulating rising edge input on pin 2.
+
+ puts(" ...Test GPIO0[2]...\n");
+
+ if(irq_triggered){ //if irq flag set then print message else amend error code
+ puts(" Rising Edge IRQ\n Detected On Pin 0\n\n");
+ irq_triggered = 0;
+ irq_counter++;
+ }
+ else err_code |= (1 << 2);
+
+ CMSDK_GPIO0->DATAOUT = 0x5; // emulating falling edge input on pin 3.
+
+ puts(" ...Test GPIO0[3]...\n");
+
+ if(irq_triggered){ //if irq flag set then print message else amend error code
+ puts(" Falling Edge IRQ:\n Detected On Pin 0\n\n");
+ irq_triggered = 0;
+ irq_counter++;
+ }
+ else err_code |= (1 << 3);
+
+ /* check to see whether intstatus, for the specified pin, is 1, which corresponds to a rising edge interrupt */
+
+ if(irq_counter == 4){
+ printf(" All %d IRQs Detected\n\n", i);
+ }
+
+
+ // print pass or fail message depending on the status of the test
+
+ if(err_code == 0){
+ puts("\n");
+ puts(" +***********************+");
+ puts(" * *");
+ puts(" * GPIO 0 IRQ Tests *");
+ puts(" * Passed Successfully *");
+ puts(" * *");
+ puts(" +***********************+\n");
+ }
+ else{
+
+ /*if the port did not have 1 of each IRQs as expected then display error*/
+
+ printf("\n** TEST FAILED ** IRQ Tests Error Code: (0x%x\n", err_code);
+ }
+
+ NVIC_DisableIRQ(PORT0_0_IRQn); //disable GPIO0 IRQ
+ NVIC_DisableIRQ(PORT0_1_IRQn);
+ NVIC_DisableIRQ(PORT0_2_IRQn);
+ NVIC_DisableIRQ(PORT0_3_IRQn);
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ return err_code;
+}
+
+// ----------------------------------------------------------
+// Peripheral detection
+// ----------------------------------------------------------
+/* Detect the part number to see if device is present */
+
+int gpio0_id_check(void)
+{
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+if ((HW32_REG(CMSDK_GPIO0_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO0_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+int timer0_id_check(void)
+{
+if ((HW32_REG(CMSDK_TIMER0_BASE + 0xFE0) != 0x22) ||
+ (HW32_REG(CMSDK_TIMER0_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+int uart0_id_check(void)
+{
+if ((HW32_REG(CMSDK_UART0_BASE + 0xFE0) != 0x21) ||
+ (HW32_REG(CMSDK_UART0_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+int uart1_id_check(void)
+{
+if ((HW32_REG(CMSDK_UART1_BASE + 0xFE0) != 0x21) ||
+ (HW32_REG(CMSDK_UART1_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+// ----------------------------------------------------------
+// Handlers
+// ----------------------------------------------------------
+// ---------------------------------
+// UART 0 Interrupt service routines
+// ---------------------------------
+//
+
+void UARTTX0_Handler(void)
+{
+ CMSDK_uart_ClearTxIRQ(CMSDK_UART0); // clear TX IRQ
+ // If the message output is not finished, output next character
+ if (tx_count < uart_str_length) {
+ CMSDK_uart_SendChar(CMSDK_UART0,str_tx[tx_count]);
+ tx_count++;
+ }
+
+}
+
+// ---------------------------------
+// UART 1 Interrupt service routines
+// ---------------------------------
+
+void UARTRX1_Handler(void)
+{
+ CMSDK_uart_ClearRxIRQ(CMSDK_UART1); //clear RX IRQ
+ str_rx[rx_count]=CMSDK_uart_ReceiveChar(CMSDK_UART1); // Read data
+ rx_count++;
+}
+
+// ---------------------------------
+// Timer 0 Interrupt service routines
+// ---------------------------------
+
+void TIMER0_Handler(void)
+{
+ timer_stopped = 1; // set timer stopped bool, so that
+ // system does not wait for another interrupt
+ CMSDK_timer_StopTimer(CMSDK_TIMER0); // stop timer
+ CMSDK_timer_ClearIRQ(CMSDK_TIMER0); // clear timer 0 IRQ
+ puts(" [Timer 0 IRQ]");
+}
+
+// ---------------------------------
+// GPIO Port 0 Interrupt service routines
+// ---------------------------------
+//
+void PORT0_0_Handler(void)
+{
+ irq_triggered = 1; /* high level */
+ CMSDK_GPIO0->DATAOUT = 0xA; /* Deassert Port 0 pin 0 to 0 */
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 0); //clear GPIO interrupt on pin N
+}
+
+void PORT0_1_Handler(void)
+{
+ irq_triggered = 1; /*low level*/
+ CMSDK_GPIO0->DATAOUT = 0xB; /* Deassert Port 0 pin 1 to 1 */
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 1); //clear GPIO interrupt on pin N
+}
+
+void PORT0_2_Handler(void)
+{
+ irq_triggered = 1; /*rising edge*/
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 2); //clear GPIO interrupt on pin N
+}
+
+void PORT0_3_Handler(void)
+{
+ irq_triggered = 1; /*falling edge*/
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 3); //clear GPIO interrupt on pin N
+}
+
+void PORT0_COMB_Handler(void) /* Combined handler */
+{
+ irq_triggered = 1;
+ if (CMSDK_GPIO0->INTSTATUS & 0x01){ /* high level */
+ CMSDK_GPIO0->DATAOUT = 0xA; /* Deassert Port 0 pin 0 to 0 */
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 0); //clear GPIO interrupt on pin N
+ }
+ if (CMSDK_GPIO0->INTSTATUS & 0x02){ /* low level*/
+ CMSDK_GPIO0->DATAOUT = 0xB; /* Deassert Port 0 pin 1 to 1 */
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 1); //clear GPIO interrupt on pin N
+ }
+ if (CMSDK_GPIO0->INTSTATUS & 0x04){ /* rising edge*/
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 2); //clear GPIO interrupt on pin N
+ }
+ if (CMSDK_GPIO0->INTSTATUS & 0x08){ /* falling edge*/
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, 3); //clear GPIO interrupt on pin N
+ }
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/demos/self_reset_demo.c b/Cortex-M0/nanosoc/software/common/demos/self_reset_demo.c
new file mode 100644
index 0000000000000000000000000000000000000000..697b3ec6c28cd60911c6fab5527efb8042c8742c
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/demos/self_reset_demo.c
@@ -0,0 +1,234 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+ /* Check self reset using SYSRESETREQ and LOCKUP reset */
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define BAD_ADDRESS 0xC0000001
+
+void main_prog_part_1(void); /* Carry out SYSRESETREQ */
+void main_prog_part_2(void); /* Check reset info, carry out lockup reset */
+void main_prog_part_3(void); /* Check reset info */
+int sysctrl_id_check(void);
+
+/*
+ Test process:
+ - if system controller is not available, skip test
+ - check reset status, which should be 0 in the beginning of test, goto execute part 1
+ - part 1 : Use System Reset Request function from CMSIS
+ - <system reset>
+ - Restarted, if system controller is not available, skip test
+ - check reset status, which should be 1 (SYSRESETREQ), goto execute part 2
+ - clear reset status, and check reset status is cleared.
+ - enable automatic reset for lockup
+ - check the reset option register read back value is correct
+ - trigger hardfault by reading BAD_ADDRESS
+ - enter hardfault handler, and then trigger lock up by reading BAD_ADDRESS again
+ - <lockup -> system reset>
+ - Restarted, if system controller is not available, skip test
+ - check reset status, which should be 4 (Lockup reset), goto execute part 3
+ - clear reset status, and check reset status is cleared.
+ - test completed , end test
+
+*/
+
+/* ----------------------------------------------------------------- */
+/* Start of main code */
+int main (void)
+{
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Self Reset Demo - revision $Revision: 371321 $\n");
+
+ if (sysctrl_id_check()!=0) {
+ puts ("** TEST SKIPPED ** SysCtrl not present.");
+ UartEndSimulation();
+ return 0;}
+
+ puts("[System started]\n");
+ /* Check CMSDK_SYSCON->RSTINFO Reset Information register */
+ /* 0 = cold reset */
+ /* 1 (bit 0) = reset from SYSRESETREQ */
+ /* 2 (bit 1) = reset from Watchdog */
+ /* 4 (bit 2) = reset from Lockup auto reset */
+ if ((CMSDK_SYSCON->RSTINFO & CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk) !=0) {
+ puts ("Restarted by SYSRESETREQ reset");
+ main_prog_part_2(); /* Check result from part 1 and trigger reset using lockup reset */
+ UartEndSimulation(); /* Should not get here. */
+ }
+ else if ((CMSDK_SYSCON->RSTINFO & CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk) !=0) {
+ puts ("Restarted by Lockup reset");
+ main_prog_part_3(); /* Check result */
+ UartEndSimulation(); /* Should not get here. Simulation stops in UartEndSimulation */
+ while(1);
+ }
+ else if ((CMSDK_SYSCON->RSTINFO & CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk) !=0) {
+ puts ("Restarted by Watchdog reset");
+ puts ("ERROR: Watchdog was not used in this test. Reset info register value incorrect.\n");
+ UartEndSimulation(); /* Should not get here. Simulation stops in UartEndSimulation */
+ }
+ else {
+ puts("Self Reset demo test\n");
+ main_prog_part_1(); /* Trigger self reset */
+ }
+ UartEndSimulation(); /* Should not get here. */
+ /* Simulation stops in UartEndSimulation */
+}
+
+/* ----------------------------------------------------------------- */
+/* Use ID value to detect if the system controller is present */
+int sysctrl_id_check(void)
+{ /* CMSDK SysCtrl part ID range from 826 to 829 */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+if ((HW32_REG(CMSDK_SYSCTRL_BASE + 0xFE0) < 0x26) ||
+ (HW32_REG(CMSDK_SYSCTRL_BASE + 0xFE0) > 0x29) ||
+ (HW32_REG(CMSDK_SYSCTRL_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+/* ----------------------------------------------------------------- */
+/* First part of the test program */
+void main_prog_part_1(void)
+{
+ puts("Using CMSIS function to generate self reset...\n");
+
+ NVIC_SystemReset();
+ while(1);
+
+}
+
+/* ----------------------------------------------------------------- */
+/* Second part of the main test program - execute after SYSRESETREQ reset */
+void main_prog_part_2(void)
+{
+ int result=0;
+ unsigned int read_data;
+
+ puts("- Self reset completed");
+ read_data = CMSDK_SYSCON->RSTINFO;
+ printf (" SYSCON->RSTINFO = %x\n", read_data);
+ if (read_data != CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk) result++;
+ puts("- Clear reset info");
+ CMSDK_SYSCON->RSTINFO = CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk;
+ read_data = CMSDK_SYSCON->RSTINFO;
+ printf (" SYSCON->RSTINFO = %x\n", read_data);
+ if (read_data != 0) result++;
+ if (result != 0) {
+ puts ("ERROR: reset info register value incorrect.\n");
+ } else {
+ puts ("SYSRESETREQ test done\nNow test reset caused by lockup\n");
+ }
+
+ /* Test Lockup reset */
+ CMSDK_SYSCON->RESETOP = CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk;
+ read_data = CMSDK_SYSCON->RESETOP;
+ if (read_data != CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk) {
+ puts ("ERROR: reset option register value incorrect.\n");
+ UartEndSimulation();
+ }
+ read_data = CMSDK_SYSCON->RSTINFO;
+ if (read_data != 0) {
+ puts ("ERROR: reset info register value incorrect.\n");
+ UartEndSimulation();
+ }
+
+ /* Trigger hard fault */
+ read_data=HW32_REG(BAD_ADDRESS);
+
+ puts ("ERROR: Hard fault not triggered");
+
+ UartEndSimulation();
+ /* Simulation stops in UartEndSimulation */
+
+ return;
+}
+
+/* ----------------------------------------------------------------- */
+/* Get to here after lockup auto-reset */
+void main_prog_part_3(void)
+{
+ int result=0;
+ unsigned int read_data;
+
+ puts("- Self reset completed");
+ /* Check reset info register value */
+ read_data = CMSDK_SYSCON->RSTINFO;
+ printf (" SYSCON->RSTINFO = %x\n", read_data);
+ if (read_data != CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk) result++;
+ puts("- Clear reset info");
+ CMSDK_SYSCON->RSTINFO = CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk;
+ read_data = CMSDK_SYSCON->RSTINFO;
+ printf (" SYSCON->RSTINFO = %x\n", read_data);
+ if (read_data != 0) result++;
+ if (result != 0) {
+ puts ("ERROR: reset info register value incorrect.\n");
+ } else {
+ puts ("Lockup reset test completed successfully\n");
+ puts ("** TEST PASSED ** \n");
+ }
+ UartEndSimulation();
+ /* Simulation stops in UartEndSimulation */
+
+ return;
+}
+
+/* ----------------------------------------------------------------- */
+void HardFault_Handler(void)
+{
+ unsigned int dummy; /* dummy variable for read that trigger hardfault */
+
+ puts("[Hard fault handler]");
+ puts("- trigger fault again to enter lockup");
+
+ /* Trigger lockup */
+ dummy=HW32_REG(BAD_ADDRESS);
+ puts ("ERROR: Lockup not triggered");
+
+ UartEndSimulation();
+ /* Simulation stops in UartEndSimulation */
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/demos/sleep_demo.c b/Cortex-M0/nanosoc/software/common/demos/sleep_demo.c
new file mode 100644
index 0000000000000000000000000000000000000000..9e99d3dc34b027be62b1cfbd927b28a78818bc99
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/demos/sleep_demo.c
@@ -0,0 +1,543 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+//==============================================================================
+//
+// Sleep Demonstration
+//
+//==============================================================================
+//
+// This test demonstrates various sleep modes and different ways to enter sleeps.
+// A timer is programmed before entering sleep and interrupt is generated to
+// wake up the processor.
+//
+// SLEEPING
+//
+// - The test enters normal sleep mode using WFI and WFE.
+//
+//
+// SLEEPDEEP
+//
+// - The test checks that the SLEEPDEEP output is asserted when the core enters
+// sleep mode, by using the CM0IKMCU internal GPIO to cause a wake-up interrupt
+// when the SLEEPDEEP signal is asserted.
+//
+//
+// WIC mode SLEEPDEEP
+//
+//
+//
+//
+
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include "uart_stdout.h"
+#include "CMSDK_driver.h"
+#include <stdio.h>
+
+//
+// Global Variables to track test progress
+//
+
+volatile uint32_t IntTaken = 0;
+volatile uint32_t SleepOnExitTest = 0;
+
+int timer0_id_check(void); // Detect Timer 0 present
+
+
+int main (void)
+{
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Sleep Demo - revision $Revision: 371321 $\n");
+
+ if (timer0_id_check()!=0) {
+ puts ("** TEST SKIPPED ** Timer 0 not present.");
+ UartEndSimulation();
+ return 0;}
+
+
+ // --------------------------------------------
+ // WFI Normal SLEEP
+ // --------------------------------------------
+ puts("\n- WFI SLEEP:");
+
+ // Ensure we use normal SLEEP - SLEEPDEEP should be clear
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR &= ~(1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ // Wait For Interrupt
+ __WFI(); // Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Check result
+ if (IntTaken) puts(" TIMER IRQ.\n");
+
+ // Disable Interrupt and Interrupt Source
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ IntTaken = 0; // Reset software variable
+
+
+ // --------------------------------------------
+ // WFE Normal SLEEP
+ // --------------------------------------------
+ puts("\n- WFE SLEEP:");
+
+ // Ensure we use normal SLEEP - SLEEPDEEP should be clear
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR &= ~(1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ IntTaken = 0; // Reset software variable
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ while (IntTaken==0) { /* Loop for sleep :
+ (first WFE could be woken up immediately due to event from the past)
+ */
+ // Wait For Event
+ __WFE();// Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+ }
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Show message (no need to test variable because of the loop)
+ puts(" TIMER IRQ.\n");
+ IntTaken = 0; // Reset software variable
+
+ // --------------------------------------------
+ // SLEEP-ON-EXIT
+ // --------------------------------------------
+ puts("\n- SLEEP-ON-EXIT:");
+
+ // Ensure we use normal SLEEP - SLEEPDEEP should be clear
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR &= ~(1UL << 2);
+
+ // Enable sleep on exit feature
+ SCB->SCR |= (1UL << 1);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ IntTaken = 0; // Reset software variable
+ SleepOnExitTest = 1;
+
+ // Set timer 0 to decrement from 0x2000 with internal clock,
+ // interrupt enabled
+ // Duration is longer than other test due to message display
+ // inside interrupt handler
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0x2000, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ while (IntTaken==0) {
+ /* Wait for first interrupt */
+ /* Then the processor will enter sleep after Timer IRQ handler */
+ /* Sleep on exit is disabled by timer IRQ handler in second occurrence */
+ }
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Show message (no need to test variable because of the loop)
+ IntTaken = 0; // Reset software variable
+ SleepOnExitTest = 0;
+ // Disable sleep on exit feature
+ SCB->SCR &= ~(1UL << 1);
+
+
+
+ // --------------------------------------------
+ // WFI Deep SLEEP
+ // --------------------------------------------
+ puts("\n- WFI DEEP SLEEP:");
+
+ // Ensure we use deep SLEEP - SLEEPDEEP should be set
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR |= (1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ // Wait For Interrupt
+ __WFI(); // Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Check result
+ if (IntTaken) puts(" TIMER IRQ.\n");
+
+ // Disable Interrupt and Interrupt Source
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ IntTaken = 0; // Reset software variable
+
+
+ // --------------------------------------------
+ // WFE Deep SLEEP
+ // --------------------------------------------
+ puts("\n- WFE DEEP SLEEP:");
+
+ // Ensure we use deep SLEEP - SLEEPDEEP should be set
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR |= (1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ IntTaken = 0; // Reset software variable
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ while (IntTaken==0) { /* Loop for sleep :
+ (first WFE could be woken up immediately due to event from the past)
+ */
+ // Wait For Event
+ __WFE();// Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+ }
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Show message (no need to test variable because of the loop)
+ puts(" TIMER IRQ.\n");
+ IntTaken = 0; // Reset software variable
+
+ // --------------------------------------------
+ // SLEEP-ON-EXIT
+ // --------------------------------------------
+ puts("\n- SLEEP-ON-EXIT deep sleep:");
+
+ // Ensure we use deep SLEEP - SLEEPDEEP should be set
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR |= (1UL << 2);
+
+ // Enable sleep on exit feature
+ SCB->SCR |= (1UL << 1);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ IntTaken = 0; // Reset software variable
+ SleepOnExitTest = 1;
+
+ // Set timer 0 to decrement from 0x2000 with internal clock,
+ // interrupt enabled
+ // Duration is longer than other test due to message display
+ // inside interrupt handler
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0x2000, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ while (IntTaken==0) {
+ /* Wait for first interrupt */
+ /* Then the processor will enter sleep after Timer IRQ handler */
+ /* Sleep on exit is disabled by timer IRQ handler in second occurrence */
+ }
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Show message (no need to test variable because of the loop)
+ IntTaken = 0; // Reset software variable
+ SleepOnExitTest = 0;
+ // Disable sleep on exit feature
+ SCB->SCR &= ~(1UL << 1);
+
+ // --------------------------------------------
+ // WFI Deep SLEEP with PMU enabled
+ // --------------------------------------------
+
+ puts("\n- Detecting PMU control");
+ CMSDK_SYSCON->PMUCTRL = CMSDK_SYSCON_PMUCTRL_EN_Msk; // set bit
+ if ((CMSDK_SYSCON->PMUCTRL & CMSDK_SYSCON_PMUCTRL_EN_Msk)==0) {
+ puts ("PMU not available\n");
+ }
+ else {
+
+ puts("\n- WFI DEEP SLEEP with WIC");
+
+ // Ensure we use deep SLEEP - SLEEPDEEP should be set
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR |= (1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ // Wait For Interrupt
+ __WFI(); // Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Check result
+ if (IntTaken) puts(" TIMER IRQ.\n");
+
+ // Disable Interrupt and Interrupt Source
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ IntTaken = 0; // Reset software variable
+
+
+ // --------------------------------------------
+ // WFE Deep SLEEP with PMU enabled
+ // --------------------------------------------
+ puts("\n- WFE DEEP SLEEP with WIC");
+
+ // Ensure we use deep SLEEP - SLEEPDEEP should be set
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR |= (1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ IntTaken = 0; // Reset software variable
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ while (IntTaken==0) { /* Loop for sleep :
+ (first WFE could be woken up immediately due to event from the past)
+ */
+ // Wait For Event
+ __WFE();// Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+ }
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Check result
+ // Show message (no need to test variable because of the loop)
+ puts(" TIMER IRQ.\n");
+ IntTaken = 0; // Reset software variable
+
+ // --------------------------------------------
+ // SLEEP-ON-EXIT
+ // --------------------------------------------
+ puts("\n- SLEEP-ON-EXIT with WIC:");
+
+ // Enable sleep on exit feature
+ SCB->SCR |= (1UL << 1);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ IntTaken = 0; // Reset software variable
+ SleepOnExitTest = 1;
+
+ // Set timer 0 to decrement from 0x2000 with internal clock,
+ // interrupt enabled
+ // Duration is longer than other test due to message display
+ // inside interrupt handler
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0x2000, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ while (IntTaken==0) {
+ /* Wait for first interrupt */
+ /* Then the processor will enter sleep after Timer IRQ handler */
+ /* Sleep on exit is disabled by timer IRQ handler in second occurrence */
+ }
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Show message (no need to test variable because of the loop)
+ IntTaken = 0; // Reset software variable
+ SleepOnExitTest = 0;
+ // Disable sleep on exit feature
+ SCB->SCR &= ~(1UL << 1);
+
+ }
+
+ // --------------------------------------------
+ // Disable PMU
+ // --------------------------------------------
+ CMSDK_SYSCON->PMUCTRL = 0; // Clear bit
+ if ((CMSDK_SYSCON->PMUCTRL & CMSDK_SYSCON_PMUCTRL_EN_Msk)!=0) {
+ puts ("ERROR:PMU control cannot be cleared\n");
+ }
+
+ puts("\n- WFI DEEP SLEEP with WIC switched off");
+
+ // Ensure we use deep SLEEP - SLEEPDEEP should be set
+ // SCR[2] = SLEEPDEEP
+ SCB->SCR |= (1UL << 2);
+
+ // Ensure timer interrupt is not pending before the test
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+
+ // Set timer 0 to decrement from 0xF0 with internal clock,
+ // interrupt enabled
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF0, 1);
+
+ // Enable Interrupts
+ NVIC_EnableIRQ(TIMER0_IRQn);
+
+ // Wait For Interrupt
+ __WFI(); // Enter sleep mode
+ // Wakeup when timer interrupt is triggered
+
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ // Check result
+ if (IntTaken) puts(" TIMER IRQ.\n");
+
+ // Disable Interrupt and Interrupt Source
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ IntTaken = 0;
+
+ printf("** TEST PASSED ** \n");
+
+ UartEndSimulation();
+ /* Simulation stops in UartEndSimulation */
+
+ return 0;
+}
+
+//
+// Timer 0 detection
+//
+/* Macros for word access to address */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+int timer0_id_check(void)
+{
+if ((HW32_REG(CMSDK_TIMER0_BASE + 0xFE0) != 0x22) ||
+ (HW32_REG(CMSDK_TIMER0_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+
+//
+// Timer interrupt handler
+//
+
+void TIMER0_Handler(void)
+{
+ CMSDK_timer_ClearIRQ(CMSDK_TIMER0);
+ // Signal to main code that the INT was taken
+ IntTaken++;
+ if (SleepOnExitTest==1){
+ puts(" TIMER IRQ.");
+ if (IntTaken==1){
+ puts(" Enter sleep...");
+ }
+
+ if (IntTaken==2){
+ // Disable sleep on exit feature
+ SCB->SCR &= ~(1UL << 1);
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+ }
+ } else {
+ // Stop the timer and disable interrupt generation
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+ }
+
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/demos/watchdog_demo.c b/Cortex-M0/nanosoc/software/common/demos/watchdog_demo.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c574f5535f5279479ce287b3fa15eef54086ca8
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/demos/watchdog_demo.c
@@ -0,0 +1,355 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+ /* Check demonstrate watchdog functionality */
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+/* Macros for word access to address */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+void main_prog_part_1(void);
+void main_prog_part_2(void);
+int watchdog_id_check(void);
+int sysctrl_id_check(void);
+void watchdog_init(unsigned int cycle, int type);
+ /* Program watchdog: */
+ /* type = 0 : No action */
+ /* type = 1 : Interrupt */
+ /* type = 2 : Reset */
+void watchdog_set(unsigned int cycle); /* update watchdog counter */
+void watchdog_unlock(void); /* unlock watchdog */
+void watchdog_lock(void); /* lock watchdog */
+void watchdog_irq_clear(void); /* clear watchdog interrupt */
+
+/* Software variables for testing */
+volatile int nmi_occurred;
+volatile int nmi_expected;
+volatile int reset_test; /* set to 1 during watchdog reset test so that NMI
+ handler will not clear the watchdog */
+volatile int integration_test=0; /* set to 1 during watchdog integration test so that NMI
+ handler will clear integration test output */
+
+/* Start of main code */
+int main (void)
+{
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Watchdog Demo - revision $Revision: 371321 $\n");
+
+ if (sysctrl_id_check()!=0) {
+ puts ("** TEST SKIPPED ** SysCtrl not present.");
+ UartEndSimulation();
+ return 0;}
+
+ /* Check CMSDK_SYSCON->RSTINFO Reset Information register */
+ /* 0 = cold reset */
+ /* 1 = reset from SYSRESETREQ */
+ /* 2 = reset from Watchdog */
+ if ((CMSDK_SYSCON->RSTINFO & CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk) !=0) {
+ puts ("Restarted by Watchdog reset");
+ main_prog_part_2();
+ UartEndSimulation(); /* Simulation stop */
+ }
+ else if ((CMSDK_SYSCON->RSTINFO & CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk) !=0) {
+ puts ("Restarted by SYSRESETREQ reset");
+ puts ("ERROR: reset info register value incorrect.\n");
+ UartEndSimulation(); /* Simulation stop */
+ }
+ else {
+ puts("Watchdog demo test\n");
+
+ if (watchdog_id_check()!=0) {
+ puts ("** TEST SKIPPED ** Watchdog not present.");
+ UartEndSimulation();
+ return 0;}
+
+ main_prog_part_1();
+ }
+ puts ("** TEST PASSED ** \n");
+ UartEndSimulation(); /* Simulation stop */
+}
+/* ----------------------------------------------------------------- */
+/* Detect the ARM ID and part number to see if device is present */
+int watchdog_id_check(void)
+{
+unsigned char wdog_id;
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+wdog_id = HW8_REG(CMSDK_WATCHDOG_BASE + 0xFE8) & 0x07;
+
+if ((HW32_REG(CMSDK_WATCHDOG_BASE + 0xFE0) != 0x24) ||
+ (HW32_REG(CMSDK_WATCHDOG_BASE + 0xFE4) != 0xB8) ||
+ (wdog_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+else
+ return 0;
+}
+int sysctrl_id_check(void)
+{ /* CMSDK SysCtrl part ID range from 826 to 829 */
+if ((HW32_REG(CMSDK_SYSCTRL_BASE + 0xFE0) < 0x26) ||
+ (HW32_REG(CMSDK_SYSCTRL_BASE + 0xFE0) > 0x29) ||
+ (HW32_REG(CMSDK_SYSCTRL_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+/* ----------------------------------------------------------------- */
+/* First part of the test program */
+void main_prog_part_1(void)
+{
+ int i;
+ const char expected_id[8]={0x24, 0xB8, 0x1B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+ unsigned int read_data;
+ reset_test = 0;
+
+ puts("Main program part 1\n");
+ puts("- Detect ID registers\n");
+ // Check the IDs and not revision number
+ for (i=0; i<8; i++){
+ read_data = HW32_REG(CMSDK_WATCHDOG_BASE + 0xFE0 + i*4);
+ if (read_data==expected_id[i]){
+ printf ("Values[%x]=0x%x\n", i, read_data);
+ } else {
+ printf ("ERROR : Values[%x]=0x%x, expected 0x%x\n", i, read_data,expected_id[i]);
+ UartEndSimulation();
+ }
+ }
+ puts("\n- Program watchdog for 10000 cycles");
+ watchdog_init(10000, 1); /* Generate NMI */
+ nmi_occurred = 0;
+ nmi_expected = 0;
+ puts("- Run loop with watchdog set regularly 10 times\n");
+ i = 0;
+ while (i<10) {
+ read_data = CMSDK_WATCHDOG->VALUE;
+ if (read_data < 8000) //the threshold must be large enough so that the NMI interrupt
+ //won't be triggered before the watchdog value is set again
+ {
+ watchdog_set(10000);
+ i++;
+ puts (" Watchdog value set again");
+ }
+ }
+
+ watchdog_init(5000, 0); /* Set watchdog to no action */
+ if (nmi_occurred!=0) {
+ puts ("ERROR : NMI occurred unexpectedly\n");
+ UartEndSimulation(); /* Simulation stop */
+ }
+
+ puts("\n- Test NMI generation");
+ nmi_occurred = 0;
+ nmi_expected = 1;
+ watchdog_init(5000, 1); /* Generate NMI */
+
+ while (nmi_occurred==0) {
+ //Wait for the watchdog interrupt
+ }
+
+ watchdog_init(5000, 0); /* Set watchdog to no action */
+ puts("\n- Test reset generation");
+ nmi_occurred = 0;
+ nmi_expected = 1; /* NMI will be triggered first */
+ reset_test = 1; /* put NMI handler to reset test operation */
+ watchdog_init(5000, 2); /* Generate Reset */
+ while (1) {
+ // wait for NMI...
+ }
+}
+
+
+/* ----------------------------------------------------------------- */
+/* Second part of the main test program - execute after watchdog reset */
+void main_prog_part_2(void)
+{
+ int result=0;
+ unsigned int read_data;
+ puts("Main program part 2");
+ puts("- Watchdog reset completed");
+ read_data = CMSDK_SYSCON->RSTINFO;
+ printf (" SYSCON->RSTINFO = %x\n", read_data);
+
+ if (read_data != CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk) {
+ result++;
+ }
+ puts("- Clear reset info");
+ CMSDK_SYSCON->RSTINFO = CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk;
+ read_data = CMSDK_SYSCON->RSTINFO;
+ printf (" SYSCON->RSTINFO = %x\n", read_data);
+
+ if (read_data != 0)/* RSTINFO should be cleared */
+ {
+ result++;
+ }
+
+ if (result != 0) {
+ puts ("ERROR: reset info register value incorrect.\n");
+ } else {
+ puts ("Watchdog reset performed successfully\n");
+ }
+
+ /* */
+ /* A simple integration test for Watchdog using NMI */
+ /* */
+
+ /* Instead of trigger NMI using normal watchdog operation, you can also
+ test the watchdog connection using integration test register.
+ ITCR - bit 0 enable integration test mode
+ ITOP - bit 0 enable watchdog reset when integration test mode is enabled
+ bit 1 enable watchdog interrupt when integration test mode is enabled
+
+ Here we demonstrate the generation of interrupt (NMI) using integration test
+ registers. You can also use integration test register to generate reset
+ but this will cause this part of the test running again and again, so we
+ will not demonstrate it here.
+ */
+
+ puts("Testing generation of NMI using integration test register");
+ reset_test = 0;
+ integration_test = 1;
+ nmi_expected = 0;
+ nmi_occurred = 0;
+ watchdog_unlock();
+ CMSDK_WATCHDOG->ITOP = 0; // Ensure NMI and reset in integration test mode are 0
+ CMSDK_WATCHDOG->ITCR = 1; // Enable integration test mode
+ if (CMSDK_WATCHDOG->ITCR == 0) {
+ puts (" - Integration Control read error");
+ result++;
+ }
+ else {
+ nmi_expected = 1;
+ CMSDK_WATCHDOG->ITOP = 2; // Set NMI output to 1
+ CMSDK_WATCHDOG->ITOP = 0; // Set NMI output to 0
+ if (nmi_occurred==0) {
+ puts (" - Integration Test operation failed");
+ result++;
+ }
+ CMSDK_WATCHDOG->ITCR = 0; // Disable integration test mode
+ if (CMSDK_WATCHDOG->ITCR != 0) {
+ puts (" - Integration Control clear error");
+ result++;
+ }
+ }
+ if (result != 0) {
+ puts ("** TEST FAILED ** Errors in Watchdog test\n");
+ } else {
+ puts ("Watchdog demo completed successfully\n** TEST PASSED ** \n");
+ }
+
+ UartEndSimulation(); /* Simulation stops in UartEndSimulation */
+}
+
+/* ----------------------------------------------------------------- */
+void NMI_Handler(void)
+{
+
+ puts ("NMI Handler Entered! \n");
+ if (reset_test==1){ /* When testing watchdog reset, need to stay
+ in NMI handler until the watchdog overflows again */
+ while (1) {
+ // wait for reset...
+ }
+ }
+ watchdog_irq_clear(); /* Deassert Watchdog interrupt */
+ nmi_occurred++; /* Update software flag */
+ if (nmi_expected==0) { /* error check */
+ puts ("ERROR : NMI occurred unexpectedly\n");
+ UartEndSimulation(); /* Simulation stop */
+ }
+ if (integration_test!=0) {
+ watchdog_unlock();
+ CMSDK_WATCHDOG->ITOP = 0; // Set NMI output to 0
+ }
+}
+/* ----------------------------------------------------------------- */
+/* Watchdog initialization */
+void watchdog_init(unsigned int cycle, int type)
+{
+ puts (" Unlocking watchdog...");
+ watchdog_unlock();
+ CMSDK_WATCHDOG->LOAD = cycle;
+ if (type==0) {
+ puts (" Set to no action");
+ CMSDK_WATCHDOG->CTRL = 0;
+ } else if (type==1) {
+ puts (" Set to NMI generation");
+ CMSDK_WATCHDOG->CTRL = CMSDK_Watchdog_CTRL_INTEN_Msk;
+ } else {
+ puts (" Set to reset generation");
+ CMSDK_WATCHDOG->CTRL = CMSDK_Watchdog_CTRL_RESEN_Msk|CMSDK_Watchdog_CTRL_INTEN_Msk;
+ }
+ puts (" Locking watchdog...");
+ watchdog_lock();
+}
+/* ----------------------------------------------------------------- */
+/* Update watchdog counter */
+void watchdog_set(unsigned int cycle)
+{
+ watchdog_unlock();
+ CMSDK_WATCHDOG->CTRL = cycle;
+ watchdog_lock();
+}
+/* ----------------------------------------------------------------- */
+/* Unlock watchdog access */
+void watchdog_unlock(void)
+{
+ CMSDK_WATCHDOG->LOCK = 0x1ACCE551;
+}
+/* ----------------------------------------------------------------- */
+/* Lock watchdog access */
+void watchdog_lock(void)
+{
+ CMSDK_WATCHDOG->LOCK = 0;
+}
+/* ----------------------------------------------------------------- */
+/* Clear watchdog interrupt request */
+void watchdog_irq_clear(void)
+{
+ watchdog_unlock();
+ CMSDK_WATCHDOG->INTCLR = CMSDK_Watchdog_INTCLR_Msk;
+ watchdog_lock();
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/dhry/dhry.h b/Cortex-M0/nanosoc/software/common/dhry/dhry.h
new file mode 100644
index 0000000000000000000000000000000000000000..5845c123181bbb066ce8afb4bd9b01eb01456d4a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/dhry/dhry.h
@@ -0,0 +1,455 @@
+/*
+This is a MODIFIED version of the Dhrystone 2.1 Benchmark program.
+
+The only changes which have been made are:
+1) the 'old-style' K&R function declarations have been replaced with
+'ANSI-C-style' function declarations (in dhry_1.c and dhry_2,c), and
+2) function prototypes have been added (in dhry.h)
+3) dhry.h uses CLOCKS_PER_SEC instead of CLK_TCK (to build with -strict)
+
+These changes allow an ANSI-C compiler to produce more efficient code, with
+no warnings.
+*/
+
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry.h (part 1 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ * Siemens AG, E STE 35
+ * Postfach 3240
+ * 8520 Erlangen
+ * Germany (West)
+ * Phone: [xxx-49]-9131-7-20330
+ * (8-17 Central European Time)
+ * Usenet: ..!mcvax!unido!estevax!weicker
+ *
+ * Original Version (in Ada) published in
+ * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ * pp. 1013 - 1030, together with the statistics
+ * on which the distribution of statements etc. is based.
+ *
+ * In this C version, the following C library functions are used:
+ * - strcpy, strcmp (inside the measurement loop)
+ * - printf, scanf (outside the measurement loop)
+ * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ * are used for execution time measurement. For measurements
+ * on other systems, these calls have to be changed.
+ *
+ * Collection of Results:
+ * Reinhold Weicker (address see above) and
+ *
+ * Rick Richardson
+ * PC Research. Inc.
+ * 94 Apple Orchard Drive
+ * Tinton Falls, NJ 07724
+ * Phone: (201) 389-8963 (9-17 EST)
+ * Usenet: ...!uunet!pcrat!rick
+ *
+ * Please send results to Rick Richardson and/or Reinhold Weicker.
+ * Complete information should be given on hardware and software used.
+ * Hardware information includes: Machine type, CPU, type and size
+ * of caches; for microprocessors: clock frequency, memory speed
+ * (number of wait states).
+ * Software information includes: Compiler (and runtime library)
+ * manufacturer and version, compilation switches, OS version.
+ * The Operating System version may give an indication about the
+ * compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ * The complete output generated by the program should be mailed
+ * such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ * History: This version C/2.1 has been made for two reasons:
+ *
+ * 1) There is an obvious need for a common C version of
+ * Dhrystone, since C is at present the most popular system
+ * programming language for the class of processors
+ * (microcomputers, minicomputers) where Dhrystone is used most.
+ * There should be, as far as possible, only one C version of
+ * Dhrystone such that results can be compared without
+ * restrictions. In the past, the C versions distributed
+ * by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ * had small (though not significant) differences.
+ *
+ * 2) As far as it is possible without changes to the Dhrystone
+ * statistics, optimizing compilers should be prevented from
+ * removing significant statements.
+ *
+ * This C version has been developed in cooperation with
+ * Rick Richardson (Tinton Falls, NJ), it incorporates many
+ * ideas from the "Version 1.1" distributed previously by
+ * him over the UNIX network Usenet.
+ * I also thank Chaim Benedelac (National Semiconductor),
+ * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ * for their help with comments on earlier versions of the
+ * benchmark.
+ *
+ * Changes: In the initialization part, this version follows mostly
+ * Rick Richardson's version distributed via Usenet, not the
+ * version distributed earlier via floppy disk by Reinhold Weicker.
+ * As a concession to older compilers, names have been made
+ * unique within the first 8 characters.
+ * Inside the measurement loop, this version follows the
+ * version previously distributed by Reinhold Weicker.
+ *
+ * At several places in the benchmark, code has been added,
+ * but within the measurement loop only in branches that
+ * are not executed. The intention is that optimizing compilers
+ * should be prevented from moving code out of the measurement
+ * loop, or from removing code altogether. Since the statements
+ * that are executed within the measurement loop have NOT been
+ * changed, the numbers defining the "Dhrystone distribution"
+ * (distribution of statements, operand types and locality)
+ * still hold. Except for sophisticated optimizing compilers,
+ * execution times for this version should be the same as
+ * for previous versions.
+ *
+ * Since it has proven difficult to subtract the time for the
+ * measurement loop overhead in a correct way, the loop check
+ * has been made a part of the benchmark. This does have
+ * an impact - though a very minor one - on the distribution
+ * statistics which have been updated for this version.
+ *
+ * All changes within the measurement loop are described
+ * and discussed in the companion paper "Rationale for
+ * Dhrystone version 2".
+ *
+ * Because of the self-imposed limitation that the order and
+ * distribution of the executed statements should not be
+ * changed, there are still cases where optimizing compilers
+ * may not generate code for some statements. To a certain
+ * degree, this is unavoidable for small synthetic benchmarks.
+ * Users of the benchmark are advised to check code listings
+ * whether code is generated for all statements of Dhrystone.
+ *
+ * Version 2.1 is identical to version 2.0 distributed via
+ * the UNIX network Usenet in March 1988 except that it corrects
+ * some minor deficiencies that were found by users of version 2.0.
+ * The only change within the measurement loop is that a
+ * non-executed "else" part was added to the "if" statement in
+ * Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines: The following "Defines" are possible:
+ * -DREG=register (default: Not defined)
+ * As an approximation to what an average C programmer
+ * might do, the "register" storage class is applied
+ * (if enabled by -DREG=register)
+ * - for local variables, if they are used (dynamically)
+ * five or more times
+ * - for parameters if they are used (dynamically)
+ * six or more times
+ * Note that an optimal "register" strategy is
+ * compiler-dependent, and that "register" declarations
+ * do not necessarily lead to faster execution.
+ * -DNOSTRUCTASSIGN (default: Not defined)
+ * Define if the C compiler does not support
+ * assignment of structures.
+ * -DNOENUMS (default: Not defined)
+ * Define if the C compiler does not support
+ * enumeration types.
+ * -DTIMES (default)
+ * -DTIME
+ * The "times" function of UNIX (returning process times)
+ * or the "time" function (returning wallclock time)
+ * is used for measurement.
+ * For single user machines, "time ()" is adequate. For
+ * multi-user machines where you cannot get single-user
+ * access, use the "times ()" function. If you have
+ * neither, use a stopwatch in the dead of night.
+ * "printf"s are provided marking the points "Start Timer"
+ * and "Stop Timer". DO NOT use the UNIX "time(1)"
+ * command, as this will measure the total time to
+ * run this program, which will (erroneously) include
+ * the time to allocate storage (malloc) and to perform
+ * the initialization.
+ * -DHZ=nnn
+ * In Berkeley UNIX, the function "times" returns process
+ * time in 1/HZ seconds, with HZ = 60 for most systems.
+ * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ * A VALUE.
+ *
+ ***************************************************************************
+ *
+ * Compilation model and measurement (IMPORTANT):
+ *
+ * This C version of Dhrystone consists of three files:
+ * - dhry.h (this file, containing global definitions and comments)
+ * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ * The following "ground rules" apply for measurements:
+ * - Separate compilation
+ * - No procedure merging
+ * - Otherwise, compiler optimizations are allowed but should be indicated
+ * - Default results are those without register declarations
+ * See the companion paper "Rationale for Dhrystone Version 2" for a more
+ * detailed discussion of these ground rules.
+ *
+ * For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ * models ("small", "medium", "large" etc.) should be given if possible,
+ * together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ * Dhrystone (C version) statistics:
+ *
+ * [Comment from the first distribution, updated for version 2.
+ * Note that because of language differences, the numbers are slightly
+ * different from the Ada version.]
+ *
+ * The following program contains statements of a high level programming
+ * language (here: C) in a distribution considered representative:
+ *
+ * assignments 52 (51.0 %)
+ * control statements 33 (32.4 %)
+ * procedure, function calls 17 (16.7 %)
+ *
+ * 103 statements are dynamically executed. The program is balanced with
+ * respect to the three aspects:
+ *
+ * - statement type
+ * - operand type
+ * - operand locality
+ * operand global, local, parameter, or constant.
+ *
+ * The combination of these three aspects is balanced only approximately.
+ *
+ * 1. Statement Type:
+ * ----------------- number
+ *
+ * V1 = V2 9
+ * (incl. V1 = F(..)
+ * V = Constant 12
+ * Assignment, 7
+ * with array element
+ * Assignment, 6
+ * with record component
+ * --
+ * 34 34
+ *
+ * X = Y +|-|"&&"|"|" Z 5
+ * X = Y +|-|"==" Constant 6
+ * X = X +|- 1 3
+ * X = Y *|/ Z 2
+ * X = Expression, 1
+ * two operators
+ * X = Expression, 1
+ * three operators
+ * --
+ * 18 18
+ *
+ * if .... 14
+ * with "else" 7
+ * without "else" 7
+ * executed 3
+ * not executed 4
+ * for ... 7 | counted every time
+ * while ... 4 | the loop condition
+ * do ... while 1 | is evaluated
+ * switch ... 1
+ * break 1
+ * declaration with 1
+ * initialization
+ * --
+ * 34 34
+ *
+ * P (...) procedure call 11
+ * user procedure 10
+ * library procedure 1
+ * X = F (...)
+ * function call 6
+ * user function 5
+ * library function 1
+ * --
+ * 17 17
+ * ---
+ * 103
+ *
+ * The average number of parameters in procedure or function calls
+ * is 1.82 (not counting the function values aX *
+ *
+ * 2. Operators
+ * ------------
+ * number approximate
+ * percentage
+ *
+ * Arithmetic 32 50.8
+ *
+ * + 21 33.3
+ * - 7 11.1
+ * * 3 4.8
+ * / (int div) 1 1.6
+ *
+ * Comparison 27 42.8
+ *
+ * == 9 14.3
+ * /= 4 6.3
+ * > 1 1.6
+ * < 3 4.8
+ * >= 1 1.6
+ * <= 9 14.3
+ *
+ * Logic 4 6.3
+ *
+ * && (AND-THEN) 1 1.6
+ * | (OR) 1 1.6
+ * ! (NOT) 2 3.2
+ *
+ * -- -----
+ * 63 100.1
+ *
+ *
+ * 3. Operand Type (counted once per operand reference):
+ * ---------------
+ * number approximate
+ * percentage
+ *
+ * Integer 175 72.3 %
+ * Character 45 18.6 %
+ * Pointer 12 5.0 %
+ * String30 6 2.5 %
+ * Array 2 0.8 %
+ * Record 2 0.8 %
+ * --- -------
+ * 242 100.0 %
+ *
+ * When there is an access path leading to the final operand (e.g. a record
+ * component), only the final data type on the access path is counted.
+ *
+ *
+ * 4. Operand Locality:
+ * -------------------
+ * number approximate
+ * percentage
+ *
+ * local variable 114 47.1 %
+ * global variable 22 9.1 %
+ * parameter 45 18.6 %
+ * value 23 9.5 %
+ * reference 22 9.1 %
+ * function result 6 2.5 %
+ * constant 55 22.7 %
+ * --- -------
+ * 242 100.0 %
+ *
+ *
+ * The program does not compute anything meaningful, but it is syntactically
+ * and semantically correct. All variables have a value assigned to them
+ * before they are used as a source operand.
+ *
+ * There has been no explicit effort to account for the effects of a
+ * cache, or to balance the use of long or short displacements for code or
+ * data.
+ *
+ ***************************************************************************
+ */
+
+#include <string.h>
+#include <stdlib.h>
+
+/* Compiler and system dependent definitions: */
+
+ /* Use times(2) time function unless */
+ /* explicitly defined otherwise */
+
+#ifdef MSC_CLOCK
+#undef HZ
+#undef TIMES
+#include <time.h>
+#define HZ CLOCKS_PER_SEC
+#endif
+ /* Use Microsoft C hi-res clock */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+ /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second 1000000.0
+ /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef NOSTRUCTASSIGN
+#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s) (d = s)
+#endif
+
+#ifdef NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+ typedef int Enumeration;
+#else
+ typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+ Enumeration;
+#endif
+ /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+ /* for strcpy, strcmp */
+
+#define Null 0
+ /* Value of a Null pointer */
+#define true 1
+#define false 0
+
+typedef int One_Thirty;
+typedef int One_Fifty;
+typedef char Capital_Letter;
+typedef int Boolean;
+typedef char Str_30 [31];
+typedef int Arr_1_Dim [50];
+typedef int Arr_2_Dim [50] [50];
+
+typedef struct record
+ {
+ struct record *Ptr_Comp;
+ Enumeration Discr;
+ union {
+ struct {
+ Enumeration Enum_Comp;
+ int Int_Comp;
+ char Str_Comp [31];
+ } var_1;
+ struct {
+ Enumeration E_Comp_2;
+ char Str_2_Comp [31];
+ } var_2;
+ struct {
+ char Ch_1_Comp;
+ char Ch_2_Comp;
+ } var_3;
+ } variant;
+ } Rec_Type, *Rec_Pointer;
+
+
+void Proc_1 (Rec_Pointer Ptr_Val_Par);
+void Proc_2 (One_Fifty *Int_Par_Ref);
+void Proc_3 (Rec_Pointer *Ptr_Ref_Par);
+void Proc_4 (void);
+void Proc_5 (void);
+void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par);
+void Proc_7 (One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val, One_Fifty *Int_Par_Ref);
+void Proc_8 (Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref, int Int_1_Par_Val, int Int_2_Par_Val);
+Enumeration Func_1 (Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val);
+Boolean Func_2 (Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref);
+Boolean Func_3 (Enumeration Enum_Par_Val);
+
diff --git a/Cortex-M0/nanosoc/software/common/dhry/dhry_1.c b/Cortex-M0/nanosoc/software/common/dhry/dhry_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..090af8522306d9f2a127e48d3c53158b91187067
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/dhry/dhry_1.c
@@ -0,0 +1,465 @@
+/*
+This is a MODIFIED version of the Dhrystone 2.1 Benchmark program.
+
+The only changes which have been made are:
+1) the 'old-style' K&R function declarations have been replaced with
+'ANSI-C-style' function declarations (in dhry_1.c and dhry_2,c), and
+2) function prototypes have been added (in dhry.h)
+3) dhry.h uses CLOCKS_PER_SEC instead of CLK_TCK (to build with -strict)
+
+These changes allow an ANSI-C compiler to produce more efficient code, with
+no warnings.
+*/
+
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_1.c (part 2 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+#include "uart_stdout.h"
+#define EXPECTED_SYST
+#define MSC_CLOCK
+#include "dhry.h"
+
+/* Global Variables: */
+
+Rec_Pointer Ptr_Glob,
+ Next_Ptr_Glob;
+int Int_Glob;
+Boolean Bool_Glob;
+char Ch_1_Glob,
+ Ch_2_Glob;
+int Arr_1_Glob [50];
+int Arr_2_Glob [50] [50];
+
+#ifndef REG
+ Boolean Reg = false;
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#else
+ Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms time_info;
+extern int times (void);
+ /* see library function "times" */
+#define Too_Small_Time (2*HZ)
+ /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long time(long *);
+ /* see library function "time" */
+#define Too_Small_Time 2
+ /* Measurements should last at least 2 seconds */
+#endif
+#ifdef MSC_CLOCK
+extern clock_t clock(void);
+#define Too_Small_Time (2*HZ)
+#endif
+
+long Begin_Time,
+ End_Time,
+ User_Time;
+float Microseconds,
+ Dhrystones_Per_Second;
+
+#ifdef NOMSG
+/*extern void EarlyExit(void);*/
+#endif
+
+/* end of variables for time measurement */
+
+
+int main (void)
+/*****/
+
+ /* main program, corresponds to procedures */
+ /* Main and Proc_0 in the Ada version */
+{
+ One_Fifty Int_1_Loc;
+ REG One_Fifty Int_2_Loc;
+ One_Fifty Int_3_Loc;
+ REG char Ch_Index;
+ Enumeration Enum_Loc;
+ Str_30 Str_1_Loc;
+ Str_30 Str_2_Loc;
+ REG int Run_Index;
+ REG int Number_Of_Runs;
+
+ // UART init
+ UartStdOutInit();
+
+ /* Initializations */
+
+ Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+ Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+ Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;
+ Ptr_Glob->Discr = Ident_1;
+ Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;
+ Ptr_Glob->variant.var_1.Int_Comp = 40;
+ strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+ "DHRYSTONE PROGRAM, SOME STRING");
+ strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+ Arr_2_Glob [8][7] = 10;
+ /* Was missing in published program. Without this statement, */
+ /* Arr_2_Glob [8][7] would have an undefined value. */
+ /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+ /* overflow may occur for this array element. */
+
+#ifdef NOMSG
+ Number_Of_Runs = ITERATIONS;
+#else
+ printf ("\n");
+ printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+ printf ("\n");
+ if (Reg)
+ {
+ printf ("Program compiled with 'register' attribute\n");
+ printf ("\n");
+ }
+ else
+ {
+ printf ("Program compiled without 'register' attribute\n");
+ printf ("\n");
+ }
+ printf ("Please give the number of runs through the benchmark: ");
+ {
+ //int n;
+ // scanf ("%d", &n);
+ Number_Of_Runs = ITERATIONS;
+ }
+ printf ("\n");
+
+ printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+#endif
+
+ /***************/
+ /* Start timer */
+ /***************/
+
+#ifdef TIMES
+ times (&time_info);
+ Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ Begin_Time = time ( (long *) 0);
+#endif
+#ifdef MSC_CLOCK
+#ifdef EXPECTED_SYST
+ SysTick->LOAD = 0x00FFFFFF; /* Reload value : lots of time */
+ SysTick->VAL = 0x0; /* Current value clear to 0x0 */
+ SysTick->CTRL = 0x5; /* Enable systick, no interrupt */
+ while (SysTick->VAL == 0); /* wait until current value reloaded */
+ Begin_Time = SysTick->VAL;
+#else
+ Begin_Time = 0;
+#endif
+#endif
+ for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+ {
+
+ Proc_5();
+ Proc_4();
+ /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+ Int_1_Loc = 2;
+ Int_2_Loc = 3;
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+ Enum_Loc = Ident_2;
+ Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+ /* Bool_Glob == 1 */
+ while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
+ {
+ Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+ /* Int_3_Loc == 7 */
+ Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+ /* Int_3_Loc == 7 */
+ Int_1_Loc += 1;
+ } /* while */
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+ /* Int_Glob == 5 */
+ Proc_1 (Ptr_Glob);
+ for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+ /* loop body executed twice */
+ {
+ if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+ /* then, not executed */
+ {
+ Proc_6 (Ident_1, &Enum_Loc);
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+ Int_2_Loc = Run_Index;
+ Int_Glob = Run_Index;
+ }
+ }
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Int_2_Loc = Int_2_Loc * Int_1_Loc;
+ Int_1_Loc = Int_2_Loc / Int_3_Loc;
+ Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+ /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+ Proc_2 (&Int_1_Loc);
+ /* Int_1_Loc == 5 */
+
+ } /* loop "for Run_Index" */
+
+#ifdef EARLY_EXIT
+ exit(0);
+#endif
+ /**************/
+ /* Stop timer */
+ /**************/
+
+#ifdef TIMES
+ times (&time_info);
+ End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ End_Time = time ( (long *) 0);
+#endif
+#ifdef MSC_CLOCK
+#ifdef EXPECTED_SYST
+ End_Time = SysTick->VAL; // Get current value;
+#else
+ End_Time = 1;
+#endif
+#endif
+
+#ifdef NOMSG
+
+#ifdef ENABLE_THUMB
+ printf ("\n");
+ printf ("\n");
+ exit(1);
+#else
+ exit(0);
+ /*EarlyExit();*/
+#endif
+
+/* Uncomment these lines if compiling with tcc (thumb) */
+#endif
+
+ printf ("Execution ends\n");
+ printf ("\n");
+ printf ("Final values of the variables used in the benchmark:\n");
+ printf ("\n");
+ printf ("Int_Glob: %d\n", Int_Glob);
+ printf (" should be: %d\n", 5);
+ printf ("Bool_Glob: %d\n", Bool_Glob);
+ printf (" should be: %d\n", 1);
+ printf ("Ch_1_Glob: %c\n", Ch_1_Glob);
+ printf (" should be: %c\n", 'A');
+ printf ("Ch_2_Glob: %c\n", Ch_2_Glob);
+ printf (" should be: %c\n", 'B');
+ printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]);
+ printf (" should be: %d\n", 7);
+ printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
+ printf (" should be: Number_Of_Runs + 10\n");
+ printf ("Ptr_Glob->\n");
+ printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp);
+ printf (" should be: (implementation-dependent)\n");
+ printf (" Discr: %d\n", Ptr_Glob->Discr);
+ printf (" should be: %d\n", 0);
+ printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+ printf (" should be: %d\n", 2);
+ printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+ printf (" should be: %d\n", 17);
+ printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+ printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ printf ("Next_Ptr_Glob->\n");
+ printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+ printf (" should be: (implementation-dependent), same as above\n");
+ printf (" Discr: %d\n", Next_Ptr_Glob->Discr);
+ printf (" should be: %d\n", 0);
+ printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+ printf (" should be: %d\n", 1);
+ printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+ printf (" should be: %d\n", 18);
+ printf (" Str_Comp: %s\n",
+ Next_Ptr_Glob->variant.var_1.Str_Comp);
+ printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ printf ("Int_1_Loc: %d\n", Int_1_Loc);
+ printf (" should be: %d\n", 5);
+ printf ("Int_2_Loc: %d\n", Int_2_Loc);
+ printf (" should be: %d\n", 13);
+ printf ("Int_3_Loc: %d\n", Int_3_Loc);
+ printf (" should be: %d\n", 7);
+ printf ("Enum_Loc: %d\n", Enum_Loc);
+ printf (" should be: %d\n", 1);
+ printf ("Str_1_Loc: %s\n", Str_1_Loc);
+ printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
+ printf ("Str_2_Loc: %s\n", Str_2_Loc);
+ printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
+ printf ("\n");
+
+#ifdef EXPECTED_SYST
+ User_Time = Begin_Time - End_Time; // SysTick is a decrement counter
+#else
+ User_Time = End_Time - Begin_Time;
+#endif
+
+
+#ifdef EXPECTED_SYST
+ printf ("Number of cycles for %d iteration is %d\n",Number_Of_Runs,User_Time);
+
+#else
+ if (User_Time < Too_Small_Time)
+ {
+ printf ("Measured time too small to obtain meaningful results\n");
+ printf ("Please increase number of runs\n");
+ printf ("\n");
+ }
+ else
+ {
+#ifdef TIME
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / (float) Number_Of_Runs;
+ Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+#else
+
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / ((float) HZ * ((float) Number_Of_Runs));
+ Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+ / (float) User_Time;
+#endif
+ printf ("Microseconds for one run through Dhrystone: ");
+ printf ("%6.1f \n", Microseconds);
+ printf ("Dhrystones per Second: ");
+ printf ("%6.1f \n", Dhrystones_Per_Second);
+ printf ("\n");
+ }
+
+#endif
+ printf ("** TEST PASSED ** \n");
+ UartPutc((char) 0x4); /* end simulation */
+ return 0;
+}
+
+
+void Proc_1 (REG Rec_Pointer Ptr_Val_Par)
+/******************/
+ /* executed once */
+{
+ REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+ /* == Ptr_Glob_Next */
+ /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */
+ /* corresponds to "rename" in Ada, "with" in Pascal */
+
+ structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+ Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+ Next_Record->variant.var_1.Int_Comp
+ = Ptr_Val_Par->variant.var_1.Int_Comp;
+ Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+ Proc_3 (&Next_Record->Ptr_Comp);
+ /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+ == Ptr_Glob->Ptr_Comp */
+ if (Next_Record->Discr == Ident_1)
+ /* then, executed */
+ {
+ Next_Record->variant.var_1.Int_Comp = 6;
+ Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+ &Next_Record->variant.var_1.Enum_Comp);
+ Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+ Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+ &Next_Record->variant.var_1.Int_Comp);
+ }
+ else /* not executed */
+ structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+void Proc_2 (One_Fifty *Int_Par_Ref)
+/******************/
+ /* executed once */
+ /* *Int_Par_Ref == 1, becomes 4 */
+{
+ One_Fifty Int_Loc;
+ Enumeration Enum_Loc;
+
+ Int_Loc = *Int_Par_Ref + 10;
+ do /* executed once */
+ if (Ch_1_Glob == 'A')
+ /* then, executed */
+ {
+ Int_Loc -= 1;
+ *Int_Par_Ref = Int_Loc - Int_Glob;
+ Enum_Loc = Ident_1;
+ } /* if */
+ while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+void Proc_3 (Rec_Pointer *Ptr_Ref_Par)
+/******************/
+ /* executed once */
+ /* Ptr_Ref_Par becomes Ptr_Glob */
+{
+ if (Ptr_Glob != Null)
+ /* then, executed */
+ *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+ Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+void Proc_4 (void) /* without parameters */
+/*******/
+ /* executed once */
+{
+ Boolean Bool_Loc;
+
+ Bool_Loc = Ch_1_Glob == 'A';
+ Bool_Glob = Bool_Loc | Bool_Glob;
+ Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+void Proc_5 (void) /* without parameters */
+/*******/
+ /* executed once */
+{
+ Ch_1_Glob = 'A';
+ Bool_Glob = false;
+} /* Proc_5 */
+
+
+ /* Procedure for the assignment of structures, */
+ /* if the C compiler doesn't support this feature */
+#ifdef NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char *d;
+register char *s;
+register int l;
+{
+ while (l--) *d++ = *s++;
+}
+#endif
+
+
diff --git a/Cortex-M0/nanosoc/software/common/dhry/dhry_2.c b/Cortex-M0/nanosoc/software/common/dhry/dhry_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..b123ae9fc648a8410cbde01fcbb6f4702c910f26
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/dhry/dhry_2.c
@@ -0,0 +1,190 @@
+/*
+This is a MODIFIED version of the Dhrystone 2.1 Benchmark program.
+
+The only changes which have been made are:
+1) the 'old-style' K&R function declarations have been replaced with
+'ANSI-C-style' function declarations (in dhry_1.c and dhry_2,c), and
+2) function prototypes have been added (in dhry.h)
+3) dhry.h uses CLOCKS_PER_SEC instead of CLK_TCK (to build with -strict)
+
+These changes allow an ANSI-C compiler to produce more efficient code, with
+no warnings.
+*/
+
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_2.c (part 3 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#ifndef COMBINED
+#include "dhry.h"
+#endif
+
+#ifndef REG
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#endif
+
+extern int Int_Glob;
+extern char Ch_1_Glob;
+
+
+void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par)
+/*********************************/
+ /* executed once */
+ /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+{
+ *Enum_Ref_Par = Enum_Val_Par;
+ if (! Func_3 (Enum_Val_Par))
+ /* then, not executed */
+ *Enum_Ref_Par = Ident_4;
+ switch (Enum_Val_Par)
+ {
+ case Ident_1:
+ *Enum_Ref_Par = Ident_1;
+ break;
+ case Ident_2:
+ if (Int_Glob > 100)
+ /* then */
+ *Enum_Ref_Par = Ident_1;
+ else *Enum_Ref_Par = Ident_4;
+ break;
+ case Ident_3: /* executed */
+ *Enum_Ref_Par = Ident_2;
+ break;
+ case Ident_4: break;
+ case Ident_5:
+ *Enum_Ref_Par = Ident_3;
+ break;
+ } /* switch */
+} /* Proc_6 */
+
+
+void Proc_7 (One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val, One_Fifty *Int_Par_Ref)
+/**********************************************/
+ /* executed three times */
+ /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */
+ /* Int_Par_Ref becomes 7 */
+ /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+ /* Int_Par_Ref becomes 17 */
+ /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+ /* Int_Par_Ref becomes 18 */
+{
+ One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 2;
+ *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+void Proc_8 (Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref, int Int_1_Par_Val, int Int_2_Par_Val)
+/*********************************************************************/
+ /* executed once */
+ /* Int_Par_Val_1 == 3 */
+ /* Int_Par_Val_2 == 7 */
+{
+ REG One_Fifty Int_Index;
+ REG One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 5;
+ Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+ Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+ Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+ for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+ Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+ Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+ Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+ Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val)
+/*************************************************/
+ /* executed three times */
+ /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */
+ /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */
+ /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */
+{
+ Capital_Letter Ch_1_Loc;
+ Capital_Letter Ch_2_Loc;
+
+ Ch_1_Loc = Ch_1_Par_Val;
+ Ch_2_Loc = Ch_1_Loc;
+ if (Ch_2_Loc != Ch_2_Par_Val)
+ /* then, executed */
+ return (Ident_1);
+ else /* not executed */
+ {
+ Ch_1_Glob = Ch_1_Loc;
+ return (Ident_2);
+ }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref)
+/*************************************************/
+ /* executed once */
+ /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+ /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+{
+ REG One_Thirty Int_Loc;
+ Capital_Letter Ch_Loc;
+
+ Int_Loc = 2;
+ while (Int_Loc <= 2) /* loop body executed once */
+ if (Func_1 (Str_1_Par_Ref[Int_Loc],
+ Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+ /* then, executed */
+ {
+ Ch_Loc = 'A';
+ Int_Loc += 1;
+ } /* if, while */
+ if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+ /* then, not executed */
+ Int_Loc = 7;
+ if (Ch_Loc == 'R')
+ /* then, not executed */
+ return (true);
+ else /* executed */
+ {
+ if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+ /* then, not executed */
+ {
+ Int_Loc += 7;
+ Int_Glob = Int_Loc;
+ return (true);
+ }
+ else /* executed */
+ return (false);
+ } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enumeration Enum_Par_Val)
+/***************************/
+ /* executed once */
+ /* Enum_Par_Val == Ident_3 */
+{
+ Enumeration Enum_Loc;
+
+ Enum_Loc = Enum_Par_Val;
+ if (Enum_Loc == Ident_3)
+ /* then, executed */
+ return (true);
+ else /* not executed */
+ return (false);
+} /* Func_3 */
+
diff --git a/Cortex-M0/nanosoc/software/common/retarget/retarget.c b/Cortex-M0/nanosoc/software/common/retarget/retarget.c
new file mode 100644
index 0000000000000000000000000000000000000000..5a9ed20fc23809fcae9389d5e88c2cda3b773a62
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/retarget/retarget.c
@@ -0,0 +1,86 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+
+#if defined ( __CC_ARM )
+/******************************************************************************/
+/* Retarget functions for ARM DS-5 Professional / Keil MDK */
+/******************************************************************************/
+
+#include <stdio.h>
+#include <time.h>
+#include <rt_misc.h>
+#pragma import(__use_no_semihosting_swi)
+
+extern unsigned char UartGetc(void);
+extern unsigned char UartPutc(unsigned char my_ch);
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+int fputc(int ch, FILE *f) {
+ return (UartPutc(ch));
+}
+
+int fgetc(FILE *f) {
+ return (UartPutc(UartGetc()));
+}
+
+int ferror(FILE *f) {
+ /* Your implementation of ferror */
+ return EOF;
+}
+
+
+void _ttywrch(int ch) {
+ UartPutc (ch);
+}
+
+
+void _sys_exit(int return_code) {
+label: goto label; /* endless loop */
+}
+
+#else
+
+/******************************************************************************/
+/* Retarget functions for GNU Tools for ARM Embedded Processors */
+/******************************************************************************/
+#include <stdio.h>
+#include <sys/stat.h>
+
+extern unsigned char UartPutc(unsigned char my_ch);
+
+__attribute__ ((used)) int _write (int fd, char *ptr, int len)
+{
+ size_t i;
+ for (i=0; i<len;i++) {
+ UartPutc(ptr[i]); // call character output function
+ }
+ return len;
+}
+
+
+#endif
diff --git a/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c b/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c
new file mode 100644
index 0000000000000000000000000000000000000000..a962275f4b817ed533bdb1348ea12be27e0ce18f
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c
@@ -0,0 +1,78 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+ /*
+
+ UART functions for retargetting
+
+ */
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+void UartStdOutInit(void)
+{
+// CMSDK_UART2->BAUDDIV = 16;
+// CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only
+ CMSDK_UART2->BAUDDIV = 2080; //(1MHz/9600)
+ CMSDK_UART2->CTRL = 0x01; //TX only, standard UART
+ CMSDK_USRT2->BAUDDIV = 2080; //(1MHz/9600)
+ CMSDK_USRT2->CTRL = 0x01; //TX only, standard UART
+ CMSDK_GPIO1->ALTFUNCSET = (1<<5);
+ return;
+}
+// Output a character
+unsigned char UartPutc(unsigned char my_ch)
+{
+ while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
+ CMSDK_UART2->DATA = my_ch; // write to transmit holding register
+ while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
+ CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
+ return (my_ch);
+}
+// Get a character
+unsigned char UartGetc(void)
+{
+ while ((CMSDK_UART2->STATE & 2)==0); // Wait if Receive Holding register is empty
+ return (CMSDK_UART2->DATA);
+}
+
+void UartEndSimulation(void)
+{
+ UartPutc((char) 0x4); // End of simulation
+ while(1);
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.h b/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.h
new file mode 100644
index 0000000000000000000000000000000000000000..ec0f88b00d0aed9af600a954034af515dafa6ccd
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.h
@@ -0,0 +1,30 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* Functions for stdout during simulation */
+/* The functions are implemented in shared/software/common/uart_stdout.c */
+
+extern void UartStdOutInit(void);
+extern unsigned char UartPutc(unsigned char my_ch);
+extern unsigned char UartGetc(void);
+extern unsigned char UartEndSimulation(void);
diff --git a/Cortex-M0/nanosoc/software/common/romtable_tests/romtable_tests.c b/Cortex-M0/nanosoc/software/common/romtable_tests/romtable_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..f2ffb83dcb7229ba5bb72dc9fdcb12c712c5d2ed
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/romtable_tests/romtable_tests.c
@@ -0,0 +1,607 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2011-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+//==============================================================================
+//
+// CORTEX-M System Design Kit ROM Table Test
+//
+//==============================================================================
+//
+// This test checks that is it possible to locate the CORTEX-M0+ architected
+// ROM table by following the CoreSight Component pointer from the DAP.
+// The ID values found in any intermediate ROM tables are displayed.
+//
+// The test passes if it finds the CORTEX-M0+ ROM Table (and the CoreSight MTB-M0+
+// ROM Table if MTB is included)
+//
+// If DBG is not included, this test skips.
+//
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#include "core_cm0.h"
+
+#else
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#include "core_cm0plus.h"
+
+#else
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#include "core_cm3.h"
+
+#else
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#include "core_cm4.h"
+
+#endif
+#endif
+#endif
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h" // for stdout
+#include "mcu_debugtester_interface.h" // For definition of interface to the debug tester
+#include "CMSDK_driver.h" // For GPIO functions in debug tester communication
+
+#include "config_id.h" // Needed for ID and configuration values
+
+#include "debugtester_functions.h" // For communication between processor under test and the debug tester
+
+#include "romtable_tests.h" // Defines known CS parts
+
+
+//=====================================================================
+// Global Variables
+//=====================================================================
+
+// Structure to store Component Address, CID, PID, reference count
+typedef struct
+{
+ uint32_t address; // Component Base Address
+ uint32_t cid; // CoreSight Component ID CID3:0
+ uint32_t pid1; // CoreSight Peripheral ID PID3:0
+ uint32_t pid2; // CoreSight Peripheral ID PID7:4
+ uint8_t jepid; // Decoded PID: JEP Identity
+ uint8_t jepcont; // Decoded PID: JEP Continuation code count
+ uint16_t partnum; // Decoded PID: Part Number
+ uint8_t revision; // Decoded PID: Part Revision
+ uint8_t revand; // Decoded PID: Revision ECO
+ uint8_t custmod; // Decoded PID: Customer Modification
+ uint8_t isarm; // Part has ARM JEPID
+ uint8_t ciderror; // Error in the CID fields
+ uint8_t piderror; // Error in the PID fields
+ uint32_t refcount; // Number of times referenced
+ uint32_t romcount; // ROM Table Number
+} CS_Type;
+
+// Maximum number of components
+#define COMPMAX 10
+
+// Array to store all discovered CoreSight components
+CS_Type Components[COMPMAX];
+
+// Number of unique ROM tables found
+uint32_t NumRomTables = 0;
+
+// error count
+uint32_t Errors = 0;
+
+//=====================================================================
+// Function Prototypes
+//=====================================================================
+// Function to check CID, PID, part number of a component.
+// If it is a ROM table, also scan through ROM table entries
+void FollowCoreSightPointer (uint32_t cs_pointer);
+
+// Simple compare function and output error message if needed
+uint32_t CheckVal(char *name, uint32_t actual, uint32_t expected);
+void CheckHex(char *name, uint32_t actual, uint32_t expected);
+void CheckPresence(char *name, uint32_t actual, uint32_t expected);
+void InitComponentsList(void);
+void ReportResults(void);
+CS_Type * FindComponent(uint32_t base_address);
+
+// Compare the CID and PID based on Part Number
+void GetCoreSightIDs(CS_Type * comp_ptr);
+void CheckDisplayCID (CS_Type * comp_ptr);
+void CheckDisplayPID (CS_Type * comp_ptr);
+void DisplayDecodedPID (CS_Type * comp_ptr);
+uint32_t LookupARMCSPart(uint32_t);
+
+//=====================================================================
+// Main code
+//=====================================================================
+
+int main (void)
+{
+ // UART init
+ UartStdOutInit();
+
+ InitComponentsList();
+
+ // Banner
+ printf("%s - ROM Table Test\n\n", MCU_CPU_NAME);
+
+ if(EXPECTED_DBG != 1)
+ {
+ puts("** TEST SKIPPED ** Core does not include DBG, skipping test\n");
+ return 1;
+ }
+ else
+ {
+ EnableDebugTester();
+
+ puts("\tROM Test is now ready\n");
+
+ //
+ // Initialise Debug Driver to correct protocol
+ //
+ if(EXPECTED_JTAGnSW)
+ {
+ CallDebugTester(FnSetInterfaceJTAG);
+ }
+ else
+ {
+ if(CallDebugTester(FnSetInterfaceSW) != TEST_PASS)
+ {
+ puts("FAIL: Serial Wire Mode not set correctly\n");
+ Errors++;
+ }
+ }
+
+ // Turn on the DAP
+ if(CallDebugTester(FnDAPPowerUp) != TEST_PASS)
+ {
+ puts("Failed to power up the DAP\n");
+ Errors++;
+ }
+ else
+ {
+ // Find BASE
+ DEBUGTESTERDATA[0] = 0xf8; // BASE
+
+ CallDebugTester(FnGetAPReg);
+ printf("----------\nDAP BASE entry is : 0x%08x", DEBUGTESTERDATA[0]);
+
+#ifdef CORTEX_M3
+ // Enable Trace to make DWT, ITM and TPIU visible
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+#endif
+#ifdef CORTEX_M4
+ // Enable Trace to make DWT, ITM and TPIU visible
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+#endif
+
+ // Start decoding
+ FollowCoreSightPointer(DEBUGTESTERDATA[0]);
+
+ puts("----------\n\n");
+ }
+
+ // Turn off DAP
+ CallDebugTester(FnDAPPowerDown);
+
+ // Report results
+ ReportResults();
+ }
+ DisableDebugTester();
+}
+
+
+void FollowCoreSightPointer (uint32_t cs_pointer)
+{
+ //
+ // Enter with a pointer to a CoreSight component
+ //
+
+ uint32_t base_addr = cs_pointer & 0xFFFFF000;
+ uint32_t entry;
+ uint32_t i;
+ CS_Type * comp_ptr = NULL;
+
+
+ // Check if pointer points to anything
+
+ switch(cs_pointer & 0x3)
+ {
+ case 0x0:
+ puts(" - Non Zero Entry not present, not in 32bit format\n");
+ Errors++;
+ break;
+
+ case 0x1:
+ puts(" - Entry marked as present but not in 32 bit format\n");
+ Errors++;
+ break;
+
+ case 0x2:
+ puts(" - Component not present\n");
+ break;
+
+ case 0x3:
+ //
+ // Component is present
+ //
+ printf(" - Component present at 0x%08x\n\nCoreSight ID of component at 0x%08x :\n\n",base_addr, base_addr);
+
+ // Find or allocate space for this component in the Components array
+ comp_ptr = FindComponent(base_addr);
+
+ // Get CID and PID for the component
+ GetCoreSightIDs(comp_ptr);
+
+ // Detect duplicate entries here
+ if(comp_ptr->refcount > 1)
+ {
+ puts("** FAIL: This component is referenced more than once **\n");
+ }
+
+ // Check and Display CID
+ CheckDisplayCID(comp_ptr);
+
+ // Check and Display PID
+ CheckDisplayPID(comp_ptr);
+
+ //
+ // If component is a ROM Table, iterate over its entries
+ //
+ if(comp_ptr->romcount)
+ {
+ entry = 1; // Non zero initialisation value for loop
+ for(i = 0; entry > 0 ; i++)
+ {
+ // Get ROM Table Entry
+ DEBUGTESTERDATA[0] = base_addr + (i*4);
+ CallDebugTester(FnGetAPMem);
+ entry = DEBUGTESTERDATA[0];
+
+ printf("----------\nROM Table (%d) Entry %d at 0x%08x is : 0x%08x", comp_ptr->romcount, i, (base_addr + (i*4)), entry);
+
+ if(entry != 0)
+ {
+ FollowCoreSightPointer(base_addr + entry);
+ }
+ else
+ {
+ puts(" - End of Table\n");
+ }
+ }
+ }
+ }
+}
+
+
+void CheckDisplayCID (CS_Type * comp_ptr)
+{
+ // Display as raw byte values
+
+ printf(" CID0: 0x%02x CID1: 0x%02x CID2: 0x%02x CID3: 0x%02x",
+ ( comp_ptr->cid & 0xFF),
+ ((comp_ptr->cid >> 8) & 0xFF),
+ ((comp_ptr->cid >> 16) & 0xFF),
+ ((comp_ptr->cid >> 24) & 0xFF));
+
+ comp_ptr->ciderror = 0;
+
+ switch(comp_ptr->cid)
+ {
+ case 0xB105100D:
+ printf(" - ROM Table (%d)\n", comp_ptr->romcount);
+ break;
+
+ case 0xB105900D:
+ puts(" - CoreSight Debug Component\n");
+ break;
+
+ case 0xB105E00D:
+ puts(" - ARM Core Memory Component\n");
+ break;
+
+ case 0xB105F00D:
+ puts(" - ARM Primecell\n");
+ break;
+
+ default:
+ puts(" - Unknown\n** FAIL: Unknown Component ID **\n");
+ comp_ptr->ciderror = 1;
+ }
+}
+
+
+void CheckDisplayPID (CS_Type * comp_ptr)
+{
+ // Display as raw byte values
+
+ printf(" PID0: 0x%02x PID1: 0x%02x PID2: 0x%02x PID3: 0x%02x\n",
+ ( comp_ptr->pid1 & 0xFF),
+ ((comp_ptr->pid1 >> 8) & 0xFF),
+ ((comp_ptr->pid1 >> 16) & 0xFF),
+ ((comp_ptr->pid1 >> 24) & 0xFF));
+
+ printf(" PID4: 0x%02x PID5: 0x%02x PID6: 0x%02x PID7: 0x%02x",
+ ( comp_ptr->pid2 & 0xFF),
+ ((comp_ptr->pid2 >> 8) & 0xFF),
+ ((comp_ptr->pid2 >> 16) & 0xFF),
+ ((comp_ptr->pid2 >> 24) & 0xFF));
+
+ comp_ptr->piderror = 0;
+
+ //
+ // Display description for known components
+ //
+ if(comp_ptr->isarm)
+ {
+ // ARM JEP ID
+ LookupARMCSPart(comp_ptr->partnum);
+ }
+ else if((comp_ptr->jepid == EXPECTED_CUST_JEP_ID) &&
+ (comp_ptr->jepcont == EXPECTED_CUST_JEP_CONT))
+ {
+ // Customer JEP ID
+ puts(" - Customer Part\n");
+ DisplayDecodedPID(comp_ptr);
+ if (comp_ptr->jepid == 0)
+ {
+ puts("** FAIL: Customer JEP ID shouldn't be zeroes or ARM's JEP ID! Please modify **\n");
+ comp_ptr->piderror = 1;
+ }
+ }
+ else
+ {
+ // Unknown JEP ID
+ puts(" - Unknown JEP ID code\n");
+ DisplayDecodedPID(comp_ptr);
+ puts("** FAIL: Unknown JEP ID code **\n");
+ comp_ptr->piderror = 1;
+ }
+}
+
+
+void DisplayDecodedPID (CS_Type * comp_ptr)
+{
+ printf("\n JEP106 ID [6:0] = 0x%02x\n", comp_ptr->jepid);
+ printf( " JEP106 continuation = 0x%x\n", comp_ptr->jepcont);
+ printf( " part number [11:0] = 0x%03x\n", comp_ptr->partnum);
+ printf( " revision [3:0] = 0x%x\n", comp_ptr->revision);
+ printf( " revand [3:0] = 0x%x\n", comp_ptr->revand);
+ printf( " customer modified [3:0] = 0x%x\n\n", comp_ptr->custmod);
+}
+
+
+//===========================================================================
+// Generate error message if compare result does not match,
+// also update error counter
+//===========================================================================
+uint32_t CheckVal(char *name, uint32_t actual, uint32_t expected)
+{
+ // Quiet check - Only call CheckHex if there is a mismatch
+ if(actual != expected)
+ {
+ CheckHex(name, actual, expected);
+ return 1; // Error
+ }
+ return 0;
+}
+
+
+void InitComponentsList(void)
+{
+ uint32_t index;
+ for(index=0 ; index < COMPMAX ; index++)
+ {
+ Components[index].address = 0;
+ }
+}
+
+
+void ReportResults(void)
+{
+ // Iterate through the list
+ // Show errors where the same component is referenced by multiple paths
+ // Show error if we don't find the expected components - Core, MTB, CTI
+
+ uint32_t CIDErrors = 0;
+ uint32_t PIDErrors = 0;
+ uint32_t REFErrors = 0;
+
+ uint32_t index;
+
+ for(index=0 ; index < COMPMAX; index++)
+ {
+ if(Components[index].address)
+ {
+ // Accumulate errors
+ CIDErrors += Components[index].ciderror;
+ PIDErrors += Components[index].piderror;
+ REFErrors += (Components[index].refcount > 1) ? 1 : 0;
+ }
+ }
+
+
+ if(CIDErrors)
+ {
+ printf("** FAIL: There were %d errors found with Component ID values **\n", CIDErrors);
+ }
+
+ if(PIDErrors)
+ {
+ printf("** FAIL: There were %d errors found with Peripheral ID values **\n", PIDErrors);
+ }
+
+ if(REFErrors)
+ {
+ printf("** FAIL: %d components were referenced more than once **\n", REFErrors);
+ }
+
+
+ // Update global Errors count
+ Errors += CIDErrors + PIDErrors + REFErrors;
+
+ // Print final test result
+ if (Errors == 0) {
+ puts("** TEST PASSED **\n");
+ } else {
+ printf("** TEST FAILED ** with %d errors\n", Errors);
+ }
+}
+
+
+void CheckPresence (char *name, uint32_t expected, uint32_t actual)
+{
+ if(expected && !actual)
+ {
+ printf("** FAIL: Did not find %s **\n", name);
+ Errors++;
+ }
+
+ if(!expected && actual)
+ {
+ printf("** FAIL: Found unexpected %s **\n", name);
+ Errors++;
+ }
+}
+
+
+CS_Type * FindComponent (uint32_t base_address)
+{
+ uint32_t index = 0;
+ CS_Type * comp_ptr = NULL;
+
+ while((index < COMPMAX) && (comp_ptr == NULL))
+ {
+ if(Components[index].address == base_address)
+ {
+ Components[index].refcount++;
+ comp_ptr = &Components[index];
+ index = COMPMAX;
+ }
+ else if(Components[index].address == 0)
+ {
+ // New component
+ Components[index].address = base_address;
+ Components[index].refcount = 1;
+ comp_ptr = &Components[index];
+ index = COMPMAX;
+ }
+ else
+ {
+ index++;
+ }
+ }
+
+ if(comp_ptr == NULL)
+ {
+ puts("** ERROR - Found too many components, increase COMPMAX and try again **\n");
+ Errors++;
+ }
+
+ return comp_ptr;
+}
+
+
+void GetCoreSightIDs(CS_Type * comp_ptr)
+{
+ // Only update the IDs if this is a new component
+ if(comp_ptr->refcount == 1)
+ {
+ // Use DebugDriver to get CID and PID
+ DEBUGTESTERDATA[0] = comp_ptr->address;
+ CallDebugTester(FnGetAPMemCSIDs);
+ comp_ptr->cid = DEBUGTESTERDATA[0];
+ comp_ptr->pid1 = DEBUGTESTERDATA[1];
+ comp_ptr->pid2 = DEBUGTESTERDATA[2];
+
+
+ // Decode PID information
+ comp_ptr->jepid = (comp_ptr->pid1 >> 12) & 0x7F;
+ comp_ptr->jepcont = comp_ptr->pid2 & 0xF;
+ comp_ptr->partnum = comp_ptr->pid1 & 0xFFF;
+ comp_ptr->revision = (comp_ptr->pid1 >> 20) & 0xF;
+ comp_ptr->revand = (comp_ptr->pid1 >> 28) & 0xF;
+ comp_ptr->custmod = (comp_ptr->pid1 >> 24) & 0xF;
+
+ // Check if the component is an ARM component
+ comp_ptr->isarm = ((comp_ptr->jepid == ARM_JEP_ID) &&
+ (comp_ptr->jepcont == ARM_JEP_CONT) ) ? 1 : 0;
+
+ // If this is a ROM Table, update counter
+ if(comp_ptr->cid == 0xB105100D)
+ {
+ comp_ptr->romcount = ++NumRomTables;
+ }
+ else
+ {
+ comp_ptr->romcount = 0;
+ }
+ }
+}
+
+void CheckHex(char *name, uint32_t actual, uint32_t expected)
+{
+ if(actual == expected)
+ {
+ printf("%s: 0x%x\t-\tPASS\n",
+ name,
+ actual);
+ }
+ else
+ {
+ printf("%s: Actual 0x%x\t(Expected 0x%x)\t-\tFAIL\n",
+ name,
+ actual,
+ expected);
+ Errors++;
+ }
+}
+
+
+uint32_t LookupARMCSPart(uint32_t partnum)
+{
+
+ // Iterate over known parts, print string if found.
+ // Return error if not found.
+
+ uint32_t error, i;
+
+ error = 1;
+
+ for(i=0; i < NumARMCSParts; i++)
+ {
+ if(ARMCSParts[i].partnumber == partnum)
+ {
+ error = 0;
+ printf(" - ARM %s\n", ARMCSParts[i].partname);
+ break;
+ }
+ }
+
+ if(error)
+ {
+ puts(" - ARM, Unknown Partnumber\n");
+ }
+ return error;
+}
diff --git a/Cortex-M0/nanosoc/software/common/romtable_tests/romtable_tests.h b/Cortex-M0/nanosoc/software/common/romtable_tests/romtable_tests.h
new file mode 100644
index 0000000000000000000000000000000000000000..d45f41be9876fb48d240eb15999895875e924aae
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/romtable_tests/romtable_tests.h
@@ -0,0 +1,83 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2012-05-31 12:12:02 +0100 (Thu, 31 May 2012) $
+ *
+ * Revision : $Revision: 210765 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// CMSDK romtable tests header file
+//
+////////////////////////////////////////////////////////////////////////////////
+
+// Partnumber is {PID1[3:0], PID0[7:0]}
+
+
+struct CoreSightPart {
+ uint32_t partnumber;
+ char * partname;
+};
+
+struct CoreSightPart ARMCSParts[] = {
+
+ // v6M Architected Parts
+ {0x008, "v6M System Control Space (SCS)"},
+ {0x00A, "v6M Data Watchpoint and Trace (DWT)"},
+ {0x00B, "v6M Breakpoint Unit (BPU)"},
+
+ // Cortex-M0
+ {0x471, "Cortex-M0 Processor"},
+ {0x4C2, "Cortex-M0 CoreSight Integration Level"},
+
+ // Cortex-M0+
+ {0x4C0, "Cortex-M0+ Processor"},
+ {0x4C1, "Cortex-M0+ CoreSight Integration Level"},
+ {0x9A6, "Cortex-M0+ Cross Trigger Interface (CTI)"},
+ {0x932, "CoreSight MTB-M0+"},
+
+ // Cortex-M1
+ {0x470, "Cortex-M1 Processor"},
+
+ // v7M Architected Parts
+ {0x000, "v7M System Control Space (SCS)"},
+ {0x00C, "v7MF System Control Space (SCS)"},
+ {0x001, "v7M Instrumentation Trace Macrocell (ITM)"},
+ {0x002, "v7M Data Watchpoint and Trace (DWT)"},
+ {0x003, "v7M FlashPatch and Breakpoint (FPB)"},
+
+ // Cortex-M3
+ {0x4C3, "Cortex-M3 Processor"},
+ {0x4C5, "Cortex-M3 CoreSight Integration Level"},
+ {0x923, "Cortex-M3 TPIU"},
+ {0x924, "Cortex-M3 ETM"},
+
+ // Cortex-M4
+ {0x4C4, "Cortex-M4 Processor"},
+ {0x4C6, "Cortex-M4 CoreSight Integration Level"},
+ {0x925, "Cortex-M4 ETM"},
+ {0x9A1, "Cortex-M4 TPIU"},
+
+ // Generic CoreSight Parts
+ {0x906, "CoreSight Cross Trigger Interface (CTI)"},
+
+};
+
+#define NumARMCSParts (sizeof ARMCSParts / sizeof ARMCSParts[0])
diff --git a/Cortex-M0/nanosoc/software/common/scripts/cmsdk_bootloader.ld b/Cortex-M0/nanosoc/software/common/scripts/cmsdk_bootloader.ld
new file mode 100644
index 0000000000000000000000000000000000000000..bc1fd29cb8c7e487deb3b2b5e053a8e1084d6632
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/cmsdk_bootloader.ld
@@ -0,0 +1,40 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: $
+ *
+ * Revision : $Revision: $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ * FLASH.ORIGIN: starting address of boot loader
+ * FLASH.LENGTH: length of flash
+ * RAM.ORIGIN: starting address of RAM bank 0
+ * RAM.LENGTH: length of RAM bank 0
+ */
+
+INCLUDE "lib-nosys.ld"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x01000000, LENGTH = 0x1000 /* 4K */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 /* 64K */
+}
+
+INCLUDE "sections.ld"
diff --git a/Cortex-M0/nanosoc/software/common/scripts/cmsdk_cm0.ld b/Cortex-M0/nanosoc/software/common/scripts/cmsdk_cm0.ld
new file mode 100644
index 0000000000000000000000000000000000000000..2ac111b4c1e84f0ed56d09852a63a0d9bbe2e9b7
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/cmsdk_cm0.ld
@@ -0,0 +1,43 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: $
+ *
+ * Revision : $Revision: $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ * FLASH.ORIGIN: starting address of flash
+ * FLASH.LENGTH: length of flash
+ * RAM.ORIGIN: starting address of RAM bank 0
+ * RAM.LENGTH: length of RAM bank 0
+ */
+
+INCLUDE "lib-nosys.ld"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFC00 /* 63K */
+ /* 64K is available, but reserve some space for */
+ /* 1) debug tester communication for debug tests */
+ /* 2) DMA data structure for DMA tests */
+}
+
+INCLUDE "sections.ld"
diff --git a/Cortex-M0/nanosoc/software/common/scripts/debugtester.ld b/Cortex-M0/nanosoc/software/common/scripts/debugtester.ld
new file mode 100644
index 0000000000000000000000000000000000000000..0c7b958969079e814e832bc7b1a46c97d7a4087a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/debugtester.ld
@@ -0,0 +1,40 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: $
+ *
+ * Revision : $Revision: $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ * FLASH.ORIGIN: starting address of flash
+ * FLASH.LENGTH: length of flash
+ * RAM.ORIGIN: starting address of RAM bank 0
+ * RAM.LENGTH: length of RAM bank 0
+ */
+
+INCLUDE "lib-nosys.ld"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 64K */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */
+}
+
+INCLUDE "sections.ld"
diff --git a/Cortex-M0/nanosoc/software/common/scripts/lib-nosys.ld b/Cortex-M0/nanosoc/software/common/scripts/lib-nosys.ld
new file mode 100644
index 0000000000000000000000000000000000000000..64e5874b5075647f4566aa12c284572e08a52212
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/lib-nosys.ld
@@ -0,0 +1,2 @@
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
diff --git a/Cortex-M0/nanosoc/software/common/scripts/lib-rdimon.ld b/Cortex-M0/nanosoc/software/common/scripts/lib-rdimon.ld
new file mode 100644
index 0000000000000000000000000000000000000000..93bd10c416e63352700c076b44b77a1f2193756b
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/lib-rdimon.ld
@@ -0,0 +1,2 @@
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a librdimon.a)
diff --git a/Cortex-M0/nanosoc/software/common/scripts/sections-nokeep.ld b/Cortex-M0/nanosoc/software/common/scripts/sections-nokeep.ld
new file mode 100644
index 0000000000000000000000000000000000000000..f21022e689907aebb0e342769e16894ff7a3c378
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/sections-nokeep.ld
@@ -0,0 +1,162 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: $
+ *
+ * Revision : $Revision: $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ *(.init)
+ *(.fini)
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Cortex-M0/nanosoc/software/common/scripts/sections.ld b/Cortex-M0/nanosoc/software/common/scripts/sections.ld
new file mode 100644
index 0000000000000000000000000000000000000000..e1e7308f3846a476eba302a39a228ce6d2260bc0
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/scripts/sections.ld
@@ -0,0 +1,163 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: $
+ *
+ * Revision : $Revision: $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Cortex-M0/nanosoc/software/common/validation/apb_mux_tests.c b/Cortex-M0/nanosoc/software/common/validation/apb_mux_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..d8ae41d4c5980a6cd1243eb899406d124fddffcd
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/apb_mux_tests.c
@@ -0,0 +1,367 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the operation of APB slave multiplexer
+*/
+
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+
+#if defined ( __CC_ARM )
+__asm void address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ void address_test_write(unsigned int addr, unsigned int wdata);
+ unsigned int address_test_read(unsigned int addr);
+#endif
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+int ID_Check(const unsigned char id_array[], unsigned int offset);
+int APB_test_slave_Check(unsigned int offset);
+
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+ int hardfault_verbose=0; // 0:Not displaying anything in hardfault handler
+
+/* Predefined ID values for APB peripherals */
+const unsigned char ahb_gpio_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x20, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char apb_uart_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x21, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char apb_timer_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x22, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char apb_dualtimer_id[16]= {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x23, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char apb_watchdog_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x24, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char pl230_udma_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x30, 0xB2, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char blank_id[16] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+int main (void)
+{
+
+ int err_code = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit");
+ puts(" - APB slave mux test - revision $Revision: 371321 $\n");
+
+ puts(" - Detecting if default peripherals are present ...\n");
+ temp_data=0;
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ puts ("0: timer 0");
+ if ( ID_Check(&apb_timer_id[0], CMSDK_TIMER0_BASE ) == 1 ) err_code |= 1<<0;
+ puts ("1: timer 1");
+ if ( ID_Check(&apb_timer_id[0], CMSDK_TIMER1_BASE ) == 1 ) err_code |= 1<<1;
+ puts ("2: dual timer");
+ if ( ID_Check(&apb_dualtimer_id[0], CMSDK_DUALTIMER_BASE) == 1 ) err_code |= 1<<2;
+ puts ("3: blank");
+ if ( ID_Check(&blank_id[0], 0x40003000 ) == 1 ) err_code |= 1<<3;
+ puts ("4: UART 0");
+ if ( ID_Check(&apb_uart_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4;
+ puts ("5: UART 1");
+ if ( ID_Check(&apb_uart_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5;
+ puts ("6: UART 2");
+ if ( ID_Check(&apb_uart_id[0], CMSDK_UART2_BASE ) == 1 ) err_code |= 1<<6;
+ puts ("7: blank");
+ if ( ID_Check(&blank_id[0], 0x40007000 ) == 1 ) err_code |= 1<<7;
+ puts ("8: Watchdog");
+ if ( ID_Check(&apb_watchdog_id[0], CMSDK_WATCHDOG_BASE ) == 1 ) err_code |= 1<<8;
+ puts ("9: blank");
+ if ( ID_Check(&blank_id[0], 0x40009000 ) == 1 ) err_code |= 1<<9;
+ puts ("10: blank");
+ if ( ID_Check(&blank_id[0], 0x4000A000 ) == 1 ) err_code |= 1<<10;
+ puts ("11: APB test slave");
+ if ( APB_test_slave_Check( 0x4000B000 ) == 1 ) err_code |= 1<<11;
+ puts ("12: APB expansion port 12");
+ if ( ID_Check(&blank_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12;
+ puts ("13: APB expansion port 13");
+ if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13;
+ puts ("14: APB expansion port 14");
+ if ( ID_Check(&blank_id[0], 0x4000E000 ) == 1 ) err_code |= 1<<14;
+ puts ("15: APB expansion port 15 (optional DMA controller)");
+ if ( ID_Check(&pl230_udma_id[0], CMSDK_PL230_BASE ) == 1 ) err_code |= 1<<15;
+
+
+ /* Report error code */
+
+ if (err_code==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+/* Check the ID register value in offset 0xFC0 to 0xFFC (last 16 words, last 12 are IDs) */
+int ID_Check(const unsigned char id_array[], unsigned int offset)
+{
+ int i; /* loop counter */
+ unsigned long expected_val, actual_val;
+ unsigned long compare_mask;
+ int mismatch = 0;
+ int id_is_zero = 0;
+ unsigned long test_addr;
+
+ /* Check the peripheral ID and component ID */
+ for (i=0;i<16;i++) {
+ test_addr = offset + 4*i + 0xFC0;
+ expected_val = (int) id_array[i];
+ actual_val = HW32_REG(test_addr);
+
+ if (actual_val == 0) id_is_zero++; // Check if all ID are zero at the end
+
+ /* create mask to ignore version numbers */
+ if (i==10) { compare_mask = 0xF0;} // mask out version field
+ else if (i==11) { compare_mask = 0xFF;} // mask out ECO field and patch field
+ else { compare_mask = 0x00;} // compare whole value
+
+ if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
+ printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
+ mismatch++;
+ }
+ } // end_for
+
+ if (id_is_zero == 16) {
+ puts (" All ID values are 0 : device not present\n");
+ return 2; }
+ else if (mismatch> 0) {
+ puts (" ID value mismatch(es) : device unknown\n");
+ return 1; }
+ else {
+ puts (" All ID values matched : device present\n");
+ return 0;
+ }
+
+}
+
+/* Simple test for APB test slave */
+int APB_test_slave_Check(unsigned int offset)
+{
+ /*
+ The APB test slave has got only one 32-bit register in
+ the first four addresses. For each word, the wait state
+ increase based on PADDR[3:2].
+
+ The test slave is also able to generate error responses
+ at offset 0x0F0 to 0xFC.
+ */
+ int mismatch = 0;
+ int fault_err = 0;
+ int i;
+
+ // Read/Write test to data_register
+ HW32_REG(offset) = 0xFFFFFFFF;
+ if ((HW32_REG(offset)) !=0xFFFFFFFF) mismatch ++;
+ HW32_REG(offset) = 0x00000000;
+ if ((HW32_REG(offset)) !=0x00000000) mismatch ++;
+ HW32_REG(offset) = 0x12345678;
+ if ((HW32_REG(offset)) !=0x12345678) mismatch ++;
+ HW16_REG(offset) = 0x5678; /* Use consistent access size.
+ This is required to allow the test to run in big endian */
+ if ((HW16_REG(offset)) !=0x5678) mismatch ++;
+ HW16_REG(offset+2) = 0x1234; /* Use consistent access size.*/
+ if ((HW16_REG(offset+2)) !=0x1234) mismatch ++;
+ HW8_REG(offset) = 0x78; /* Use consistent access size between read and write.*/
+ HW8_REG(offset+1) = 0x56;
+ HW8_REG(offset+2) = 0x34;
+ HW8_REG(offset+3) = 0x12;
+ if ((HW8_REG(offset)) !=0x78) mismatch ++;
+ if ((HW8_REG(offset+1)) !=0x56) mismatch ++;
+ if ((HW8_REG(offset+2)) !=0x34) mismatch ++;
+ if ((HW8_REG(offset+3)) !=0x12) mismatch ++;
+ HW16_REG(offset+4) = 0xFFFF; // Value = 0x1234FFFF
+ if ((HW16_REG(offset+8)) !=0xFFFF) mismatch ++;
+ HW16_REG(offset+6) = 0x0000; // Value = 0x0000FFFF
+ if ((HW16_REG(offset+4)) !=0xFFFF) mismatch ++;
+ if ((HW16_REG(offset+6)) !=0x0000) mismatch ++;
+ HW8_REG(offset+8) = 0xA5; // Value = 0x0000FFA5
+ if ((HW8_REG(offset+8)) !=0xA5) mismatch ++;
+ HW8_REG(offset+0xD) = 0xC3; // Value = 0x0000C3A5
+ if ((HW8_REG(offset+0xD)) !=0xC3) mismatch ++;
+ HW16_REG(offset+0xE)= 0xC53A;// Value = 0xC53AC3A5
+ if ((HW16_REG(offset+0xE)) !=0xC53A) mismatch ++;
+
+ /* Testing of error response from APB test slave */
+ for (i=0; i<4; i++) {
+ temp_data=0;
+ hardfault_expected = 1;
+ hardfault_occurred = 0;
+ address_test_write((offset + 0xF0 + (i<<2)), 0x0);
+ if (hardfault_occurred==0) fault_err++;
+ hardfault_occurred = 0;
+ temp_data=address_test_read(offset + 0xF0 + (i<<2));
+ if (hardfault_occurred==0) fault_err++;
+ }
+
+ hardfault_expected = 0;
+ hardfault_occurred = 0;
+
+ if (mismatch>0) { puts (" Data mismatch in APB test slave\n");
+ return 1;}
+ if (fault_err>0){ puts (" Fault mismatch in APB test slave\n");
+ return 1;}
+ else puts (" APB test slave test passed\n");
+
+ return 0;
+}
+
+#if defined ( __CC_ARM )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ STR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ BX LR
+}
+
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ __asm(" str r1,[r0]\n"
+ " dsb \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+ ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ if (hardfault_verbose) puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ if (hardfault_verbose) printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ if (hardfault_verbose) printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
+
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/bitband_tests.c b/Cortex-M0/nanosoc/software/common/validation/bitband_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..1d1020980777f88c744f45e3b09b14b32fa01fd0
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/bitband_tests.c
@@ -0,0 +1,602 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/* A simple program to test the bitband wrapper for Cortex-M0 and
+ Cortex-M0+ */
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#include <stdio.h>
+
+#include "uart_stdout.h"
+
+/* Macros for word, half word and byte */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+#define SRAM_BITBAND_ADDR 0x20000000
+#define SRAM_BITBAND_ALIAS 0x22000000
+#define PERIPH_BITBAND_ADDR 0x40000000
+#define PERIPH_BITBAND_ALIAS 0x42000000
+
+volatile unsigned int sram_array[20];
+
+/* Tick to make sure variables are placed after test ram area */
+#define probing_state sram_array[16]
+#define hf_expected sram_array[17]
+#define hf_occurred sram_array[18]
+
+void ProbeBitBandAddr(void);
+int SRamBitBandTest(void);
+int PeripheralBitBandTest(void);
+int EndianCheck(void);
+int error_test(void);
+
+int main (void)
+{
+ int result=0;
+
+ probing_state = 0;
+ hf_expected = 0;
+ hf_occurred = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Bitband Test - revision $Revision: 371321 $\n");
+
+ /* Probe Bit band alias address to see if bitband has been implemented */
+ ProbeBitBandAddr();
+
+ /* Test bitband access to SRAM */
+ if (SRamBitBandTest()) result |= 1;
+
+ /* Test bitband access to peripheral */
+ if (PeripheralBitBandTest()) result |= 1;
+
+ if (error_test()) result |= 1;
+
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+void ProbeBitBandAddr(void)
+{
+ probing_state = 1;
+ /* Access first address in bit-band alias. If bus fault occurred
+ it means bitband feature is not available. */
+ HW32_REG(SRAM_BITBAND_ALIAS) = 0;
+ puts ("- no error in SRAM bitband alias access\n");
+ puts (" continue test...\n");
+ probing_state = 0;
+ sram_array[0] = 0; /* Dummy access to make sure sram_array won't get optimized away */
+ return;
+}
+
+
+int SRamBitBandTest(void)
+{
+const unsigned int testdata[4] = { 0x55AA33CC, 0xBADF00D, 0xC0FFEE, 0x12345678};
+ unsigned int readdata; /* read back value - packed */
+ unsigned int i,j; /* loop counters */
+ unsigned int t1, t2; /* temp value */
+ unsigned int err_code; /* error code */
+ unsigned int verbose_level = 0;
+
+ err_code = 0;
+
+ /* Store data in SRAM */
+ HW32_REG(SRAM_BITBAND_ADDR ) = testdata[0];
+ HW32_REG(SRAM_BITBAND_ADDR+0x4) = testdata[1];
+ HW32_REG(SRAM_BITBAND_ADDR+0x8) = testdata[2];
+ HW32_REG(SRAM_BITBAND_ADDR+0xC) = testdata[3];
+
+ puts ("SRAM bitband");
+ puts (" - Read bitband alias,");
+ for (i=0;i<4;i++) {
+ readdata=0;
+
+ /* Read each bit in the word via bit band alias and reconstruct the 32-bit value */
+ j=32;
+ while(j>0) {
+ j--;
+ readdata = readdata << 1; /* Shift */
+ t1 = HW32_REG(SRAM_BITBAND_ALIAS + 4*j + 0x80*i);
+ /* Check bit band read data should be 0 or 1 */
+ if ((t1|0x1)!=1) {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<1;
+ }
+ /* merge 32-bit word with previous read data */
+ if (t1!=0) readdata += 1; /* Set LSB */
+ } /* end while */
+
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=testdata[i]){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",testdata[i],readdata );
+ err_code |= 1<<2;
+ }
+ } /* end for */
+
+ puts (" - toggle each bit by write to bit band alias");
+ for (i=0;i<4;i++) {
+ readdata=0;
+
+ /* Toggle each bit in the words via bit band alias and read the 32-bit value afterwards*/
+ j=32;
+ while(j>0) {
+ j--;
+ t1 = HW32_REG(SRAM_BITBAND_ALIAS + 4*j + 0x80*i);
+ /* Toggle bit and check bit band read data should be 0 or 1 */
+ if (t1==1) HW32_REG(SRAM_BITBAND_ALIAS + 4*j + 0x80*i) = 0;
+ else if (t1==0) HW32_REG(SRAM_BITBAND_ALIAS + 4*j + 0x80*i) = 1;
+ else {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<3;
+ }
+ } /* end while */
+ /* read whole word */
+ readdata = HW32_REG(SRAM_BITBAND_ADDR + 4*i);
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=(~testdata[i])){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(~testdata[i]),readdata );
+ err_code |= 1<<4;
+ }
+ } /* end for */
+
+
+ puts (" - Read bitband alias by halfword size,");
+ for (i=0;i<8;i++) {
+ readdata=0;
+
+ /* Read each bit in the word via bit band alias and reconstruct the 32-bit value */
+ j=16;
+ while(j>0) {
+ j--;
+ readdata = readdata << 1; /* Shift */
+ t1 = HW16_REG(SRAM_BITBAND_ALIAS + 4*j + 0x40*i);
+ /* Check bit band read data should be 0 or 1 */
+ if ((t1|0x1)!=1) {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<5;
+ }
+ /* merge 32-bit word with previous read data */
+ if (t1!=0) readdata += 1; /* Set LSB */
+ } /* end while */
+
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+
+ if (readdata!=(HW16_REG(SRAM_BITBAND_ADDR+2*i))){ /* Note : data has been inverted */
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(~testdata[i]),readdata );
+ err_code |= 1<<6;
+ }
+ } /* end for */
+
+
+ puts (" - toggle each bit by write to bit band alias, halfword size");
+ for (i=0;i<8;i++) {
+ readdata=0;
+
+ /* Toggle each bit in the words via bit band alias and read the 32-bit value afterwards*/
+ t2 = HW16_REG(SRAM_BITBAND_ADDR+2*i); /* Current value */
+ j=16;
+ while(j>0) {
+ j--;
+ t1 = HW16_REG(SRAM_BITBAND_ALIAS + 4*j + 0x40*i);
+ /* Toggle bit and check bit band read data should be 0 or 1 */
+ if (t1==1) HW16_REG(SRAM_BITBAND_ALIAS + 4*j + 0x40*i) = 0;
+ else if (t1==0) HW16_REG(SRAM_BITBAND_ALIAS + 4*j + 0x40*i) = 1;
+ else {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<7;
+ }
+ } /* end while */
+
+ /* read halfword */
+ readdata = HW16_REG(SRAM_BITBAND_ADDR + 2*i);
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+
+ if (readdata!=((~t2) & 0xFFFF)){ /* Check data has been inverted */
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",((~t2) & 0xFFFF),readdata );
+ err_code |= 1<<8;
+ }
+ } /* end for */
+
+
+ puts (" - Read bitband alias by byte size,");
+ for (i=0;i<16;i++) {
+ readdata=0;
+
+ /* Read each bit in the word via bit band alias and reconstruct the 32-bit value */
+ j=8;
+ while(j>0) {
+ j--;
+ readdata = readdata << 1; /* Shift */
+ t1 = HW8_REG(SRAM_BITBAND_ALIAS + 4*j + 0x20*i);
+ /* Check bit band read data should be 0 or 1 */
+ if ((t1|0x1)!=1) {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<5;
+ }
+ /* merge 32-bit word with previous read data */
+ if (t1!=0) readdata += 1; /* Set LSB */
+ } /* end while */
+
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+
+ if (readdata!=(HW8_REG(SRAM_BITBAND_ADDR + i))){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(HW8_REG(SRAM_BITBAND_ADDR + i)),readdata );
+ err_code |= 1<<6;
+ }
+ } /* end for */
+
+
+ puts (" - toggle each bit by write to bit band alias, byte size");
+ for (i=0;i<16;i++) {
+ readdata=0;
+
+ /* Toggle each bit in the words via bit band alias and read the 32-bit value afterwards*/
+ t2 = HW8_REG(SRAM_BITBAND_ADDR+i); /* Current value */
+ j=8;
+ while(j>0) {
+ j--;
+ t1 = HW8_REG(SRAM_BITBAND_ALIAS + 4*j + 0x20*i);
+ /* Toggle bit and check bit band read data should be 0 or 1 */
+ if (t1==1) HW8_REG(SRAM_BITBAND_ALIAS + 4*j + 0x20*i) = 0;
+ else if (t1==0) HW8_REG(SRAM_BITBAND_ALIAS + 4*j + 0x20*i) = 1;
+ else {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<7;
+ }
+ } /* end while */
+ /* read whole word */
+ readdata = HW8_REG(SRAM_BITBAND_ADDR + i);
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=((~t2) & 0xFF)){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",((~t2) & 0xFF),readdata );
+ err_code |= 1<<8;
+ }
+ } /* end for */
+
+
+ puts (" Test done\n");
+ return err_code;
+}
+
+int PeripheralBitBandTest(void)
+{
+
+const unsigned int testdata[2] = { 0x31241456, 0x92745722};
+ unsigned int readdata; /* read back value - packed */
+ unsigned int i,j; /* loop counters */
+ unsigned int t1; /* temp value */
+ unsigned int err_code; /* error code */
+ unsigned int verbose_level = 0;
+
+ /* Note :
+ Timer 0 is located in 0x40000000, with ctrl, value, reload and ID registers
+ CTRL : 0x40000000 (not used here)
+ VALUE : 0x40000004 (use for bit toggle later)
+ RELOAD : 0x40000008 (use for bit toggle later)
+ ...
+ PID 4 to 7 : 0x40000FE0 to 0x40000FEC (not used here).
+ PID 0 to 3 : 0x40000FE0 to 0x40000FEC (not used here).
+ CID 0 to 3 : 0x40000FF0 to 0x40000FFC (use for read test).
+ */
+ err_code = 0;
+ puts ("Peripheral bitband");
+ puts (" - Read bitband alias, word");
+
+ /* Read timer 0 CID registers with bit band alias */
+ for (i=0;i<4;i++) {
+ readdata=0;
+
+ /* Read each bit in the word via bit band alias and reconstruct the 32-bit value */
+ j=32;
+ while(j>0) {
+ j--;
+ readdata = readdata << 1; /* Shift */
+ t1 = HW32_REG(PERIPH_BITBAND_ALIAS + (0xFF0*0x20) + 4*j + 0x80*i);
+ /* Check bit band read data should be 0 or 1 */
+ if ((t1|0x1)!=1) {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<1;
+ }
+ /* merge 32-bit word with previous read data */
+ if (t1!=0) readdata += 1; /* Set LSB */
+ } /* end while */
+
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=(HW32_REG(PERIPH_BITBAND_ADDR +0xFF0 + 4 * i))){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(HW32_REG(PERIPH_BITBAND_ADDR + 0xFF0 + 4 * i)),readdata );
+ err_code |= 1<<2;
+ }
+ } /* end for */
+
+ puts (" - Read bitband alias, half word");
+ /* Read timer 0 CID registers with bit band alias, half word */
+ for (i=0;i<8;i++) {
+ readdata=0;
+
+ /* Read each bit in the halfword via bit band alias and reconstruct the 16-bit value */
+ j=16;
+ while(j>0) {
+ j--;
+ readdata = readdata << 1; /* Shift */
+ t1 = HW16_REG(PERIPH_BITBAND_ALIAS + (0xFF0*0x20) + 4*j + 0x40*i);
+ /* Check bit band read data should be 0 or 1 */
+ if ((t1|0x1)!=1) {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<3;
+ }
+ /* merge 32-bit word with previous read data */
+ if (t1!=0) readdata += 1; /* Set LSB */
+ } /* end while */
+
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=(HW16_REG(PERIPH_BITBAND_ADDR + 0xFF0 + 2 * i))){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(HW16_REG(PERIPH_BITBAND_ADDR + 0xFF0 + 2 * i)),readdata );
+ err_code |= 1<<4;
+ }
+ } /* end for */
+
+ puts (" - Read bitband alias, byte");
+ /* Read timer 0 CID registers with bit band alias, half word */
+ for (i=0;i<16;i++) {
+ readdata=0;
+
+ /* Read each bit in the word via bit band alias and reconstruct the 8-bit value */
+ j=8;
+ while(j>0) {
+ j--;
+ readdata = readdata << 1; /* Shift */
+ t1 = HW8_REG(PERIPH_BITBAND_ALIAS + (0xFF0*0x20) + 4*j + 0x20*i);
+ /* Check bit band read data should be 0 or 1 */
+ if ((t1|0x1)!=1) {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<5;
+ }
+ /* merge 32-bit word with previous read data */
+ if (t1!=0) readdata += 1; /* Set LSB */
+ } /* end while */
+
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=(HW8_REG(PERIPH_BITBAND_ADDR+0xFF0 + i))){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(HW8_REG(PERIPH_BITBAND_ADDR+0xFF0 + i)),readdata );
+ err_code |= 1<<6;
+ }
+ } /* end for */
+
+ /* CMSDK_TIMER0->VALUE (0x40000004) and CMSDK_TIMER0->RELOAD (0x40000008)
+ registers are 32-bit read/write registers which we can use them
+ for bit-band tests */
+
+ CMSDK_TIMER0->VALUE = testdata[0];
+ CMSDK_TIMER0->RELOAD = testdata[1];
+
+ puts (" - toggle each bit by write to bit band alias, word size");
+ for (i=0;i<2;i++) {
+ readdata=0;
+
+ /* Toggle each bit in the words via bit band alias and read the 32-bit value afterwards*/
+ j=32;
+ while(j>0) {
+ j--;
+ t1 = HW32_REG(PERIPH_BITBAND_ALIAS + (0x004*0x20)+ 4*j + 0x80*i);
+ /* Toggle bit and check bit band read data should be 0 or 1 */
+ if (t1==1) HW32_REG(PERIPH_BITBAND_ALIAS + (0x004*0x20) + 4*j + 0x80*i) = 0;
+ else if (t1==0) HW32_REG(PERIPH_BITBAND_ALIAS + (0x004*0x20) + 4*j + 0x80*i) = 1;
+ else {
+ puts("ERROR: bitband read should only return 0 or 1");
+ printf ("Got %x, i=%d, j=%d\n", t1, i, j);
+ err_code |= 1<<7;
+ }
+ } /* end while */
+ /* read whole word */
+ readdata = HW32_REG(PERIPH_BITBAND_ADDR + 0x4 + 4*i);
+ if (verbose_level!=0) printf (" readdata %d = %x\n", i, readdata);
+ if (readdata!=(~testdata[i])){
+ puts("ERROR: Value mismatch");
+ printf ("Expect %x, actual = %x\n",(~testdata[i]),readdata );
+ err_code |= 1<<8;
+ }
+ } /* end for */
+
+
+ puts (" Test done\n");
+ return err_code;
+}
+
+int EndianCheck(void)
+{
+ unsigned int err_code = 0; /* error code */
+ unsigned int t1; /* temp value */
+const unsigned int testdata[2] = { 0x31241456, 0x92745722};
+ int i; /* loop counter */
+
+ puts ("Checking endian characteristic");
+ for (i = 0;i<2; i++){
+ HW32_REG(SRAM_BITBAND_ADDR) = testdata[i];
+ t1 = HW16_REG(SRAM_BITBAND_ADDR) | (HW16_REG(SRAM_BITBAND_ADDR + 0x2) << 16);
+ if (t1 != testdata[i]) {
+ err_code = 1;
+ printf ("Write 32-bit word %x, read 2x 16-bit halfword %x.\n",testdata[i], t1 );
+ }
+ }
+ for (i = 0;i<2; i++){
+ HW32_REG(SRAM_BITBAND_ADDR) = testdata[i];
+ t1 = HW8_REG(SRAM_BITBAND_ADDR ) | (HW8_REG(SRAM_BITBAND_ADDR + 0x1) << 8) |
+ (HW8_REG(SRAM_BITBAND_ADDR+0x2) << 16) | (HW8_REG(SRAM_BITBAND_ADDR + 0x3) << 24);
+ if (t1 != testdata[i]) {
+ err_code = 1;
+ printf ("Write 32-bit word %x, read 4x 8-bit byte %x.\n", testdata[i], t1);
+ }
+ }
+ if (err_code != 0) {
+ puts ("The memory system does not fully compliant to endianess,");
+ puts ("some tests procedures will be skipped.\n");
+ }
+ return err_code;
+}
+
+int error_test(void)
+{
+
+ unsigned int err_code; /* error code */
+ unsigned int t1; /* temp value for bus fault test */
+ unsigned int testaddr; /* temp value */
+
+ err_code = 0;
+ puts ("Bus fault test");
+ puts (" - read error");
+ hf_expected = 1;
+ hf_occurred = 0;
+ testaddr = SRAM_BITBAND_ALIAS + (0x100000 - 1)*32; // Address to be tested
+ printf (" test address = %x\n", testaddr);
+ t1 = HW32_REG(testaddr);
+
+ /* Bus fault should be triggered */
+ __ISB(); /* delay */
+ __ISB(); /* delay */
+ __ISB(); /* delay */
+
+ if (hf_occurred!=1) {
+ printf ("Expect 1 fault, actual %d\n", hf_occurred);
+ err_code = 1;
+ }
+
+ puts (" - write error");
+ hf_expected = 1;
+ hf_occurred = 0;
+
+ HW32_REG(testaddr)=0;
+
+ /* Bus fault should be triggered */
+ __ISB(); /* delay */
+ __ISB(); /* delay */
+ __ISB(); /* delay */
+
+ if (hf_occurred!=1) {
+ printf ("Expect 1 fault, actual %d\n", hf_occurred);
+ err_code = 1;
+ }
+
+ /* End of test, clear hf_expected */
+ hf_expected = 0;
+
+ puts (" Test done\n");
+ return err_code;
+
+}
+
+/* Hard fault handler - would be triggered in probing state if
+ bitband feature is not implemented */
+
+void HF_Handler_main(unsigned int * hf_args)
+{
+ if (probing_state==1) {
+ /* Bus fault while probing */
+ puts ("Bus fault while probing bitband alias\n");
+ puts ("** TEST SKIPPED ** Bitband feature not available\n");
+ UartEndSimulation();
+ }
+ if (hf_expected==1) {
+ puts ("Expected Bus fault\n");
+ hf_occurred ++;
+ /* Increment stacked PC */
+ hf_args[6] = hf_args[6] + 2;
+ }
+ else {
+ puts ("Unexpected Bus fault\n");
+ UartEndSimulation();
+ }
+ return;
+}
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; first parameter - stacking was using PSP
+ LDR R1,=__cpp(HF_Handler_main)
+ BX R1
+stacking_used_MSP
+ MRS R0, MSP ; first parameter - stacking was using MSP
+ LDR R1,=__cpp(HF_Handler_main)
+ BX R1
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HF_Handler_main \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HF_Handler_main \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+#endif
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/default_slaves_tests.c b/Cortex-M0/nanosoc/software/common/validation/default_slaves_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..065dab96797f2d2e8690c631274d9e1af87c8634
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/default_slaves_tests.c
@@ -0,0 +1,240 @@
+/*-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+*/
+
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the operation of default slave and the handling of
+ error response in the AHB interconnection.
+*/
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#if defined ( __CC_ARM )
+__asm void address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ void address_test_write(unsigned int addr, unsigned int wdata);
+ unsigned int address_test_read(unsigned int addr);
+#endif
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+
+int main (void)
+{
+ int err_code = 0;
+ int rdata; /* dummy variable for read data in bus fault testing */
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Default Slave Test - revision $Revision: 371321 $\n");
+
+
+ puts("Default slave tests - hard faults expected\n");
+ temp_data=0;
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ address_test_write(0x40020000, 0x3456789A);
+ if (hardfault_occurred==0) {err_code |= (1<<0);}
+ hardfault_occurred = 0;
+
+ rdata = address_test_read(0x40020000);
+ if (hardfault_occurred==0) {err_code |= (1<<1);}
+ hardfault_occurred = 0;
+
+ address_test_write(0x50000000, 0x3456789A);
+ if (hardfault_occurred==0) {err_code |= (1<<2);}
+ hardfault_occurred = 0;
+
+ rdata = address_test_read(0x50000000);
+ if (hardfault_occurred==0) {err_code |= (1<<3);}
+ hardfault_occurred = 0;
+
+ puts("\nAPB test slave - hard faults expected\n");
+ rdata = address_test_read(0x40003000);
+ if (hardfault_occurred==0) {err_code |= (1<<4);}
+ hardfault_occurred = 0;
+
+ rdata = address_test_read(0x40007000);
+ if (hardfault_occurred==0) {err_code |= (1<<5);}
+ hardfault_occurred = 0;
+
+ rdata = address_test_read(0x40009000);
+ if (hardfault_occurred==0) {err_code |= (1<<6);}
+ hardfault_occurred = 0;
+
+ rdata = address_test_read(0x4000A000);
+ if (hardfault_occurred==0) {err_code |= (1<<7);}
+ hardfault_occurred = 0;
+
+ /* clean up */
+ hardfault_expected = 0;
+
+ /* Generate test pass/fail and return value */
+ if (err_code==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+#if defined ( __CC_ARM )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ STR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ BX LR
+}
+
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ __asm(" str r1,[r0]\n"
+ " dsb \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+ ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/dma_tests.c b/Cortex-M0/nanosoc/software/common/validation/dma_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..5c06eb900e6e3f15bc9771e4516bdb168076874a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/dma_tests.c
@@ -0,0 +1,543 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the connectivity of the DMA-230 including
+ interrupt and done signals
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#include "config_id.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+
+int pl230_dma_detect(void);
+int ID_Check(const unsigned int id_array[], unsigned int offset);
+void dma_memory_copy (unsigned int src, unsigned int dest, unsigned int size, unsigned int num);
+void dma_data_struct_init(void);
+void dma_pl230_init(void);
+int dma_simple_test(void);
+int dma_interrupt_test(void);
+int dma_event_test(void);
+void delay(void);
+
+ /* Maximum to 32 DMA channel */
+#define MAX_NUM_OF_DMA_CHANNELS 32
+ /* SRAM in example system is 64K bytes */
+#define RAM_ADDRESS_MAX 0x3000FFFF
+
+typedef struct /* 4 words */
+{
+ volatile unsigned long SrcEndPointer;
+ volatile unsigned long DestEndPointer;
+ volatile unsigned long Control;
+ volatile unsigned long unused;
+} pl230_dma_channel_data;
+
+
+typedef struct /* 8 words per channel */
+{ /* only one channel in the example uDMA setup */
+ volatile pl230_dma_channel_data Primary[MAX_NUM_OF_DMA_CHANNELS];
+ volatile pl230_dma_channel_data Alternate[MAX_NUM_OF_DMA_CHANNELS];
+} pl230_dma_data_structure;
+
+pl230_dma_data_structure *dma_data;
+
+volatile unsigned int source_data_array[4]; /* Data array for memory DMA test */
+volatile unsigned int dest_data_array[4]; /* Data array for memory DMA test */
+
+int main (void)
+{
+ int result=0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - DMA Test - revision $Revision: 371321 $\n");
+
+
+ if (pl230_dma_detect()!=0) {
+ return 0; /* Quit test if DMA is not present */
+ }
+
+ dma_done_irq_expected = 0;
+ dma_done_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ dma_data_struct_init();
+ dma_pl230_init();
+
+ result += dma_simple_test();
+ result += dma_interrupt_test();
+ result += dma_event_test();
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+/* --------------------------------------------------------------- */
+/* Detect if DMA controller is present or not */
+/* --------------------------------------------------------------- */
+
+int pl230_dma_detect(void)
+{
+ int result;
+
+ unsigned const int pl230_id[12] = {
+ 0x30, 0xB2, 0x0B, 0x00,
+ 0x0D, 0xF0, 0x05, 0xB1};
+ puts("Detect if DMA controller is present...");
+ result = ID_Check(&pl230_id[0] , CMSDK_PL230_BASE);
+ if (result!=0) {
+ puts("** TEST SKIPPED ** DMA controller is not present.\n");
+ UartEndSimulation();
+ }
+ return(result);
+}
+
+int ID_Check(const unsigned int id_array[], unsigned int offset)
+{
+int i;
+unsigned long expected_val, actual_val;
+unsigned long compare_mask;
+int mismatch = 0;
+unsigned long test_addr;
+
+ /* Check the peripheral ID and component ID */
+ for (i=0;i<8;i++) {
+ test_addr = offset + 4*i + 0xFE0;
+ expected_val = id_array[i];
+ actual_val = HW32_REG(test_addr);
+
+ /* create mask to ignore version numbers */
+ if (i==2) { compare_mask = 0xF0;} // mask out version field
+ else { compare_mask = 0x00;} // compare whole value
+
+ if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
+ printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
+ mismatch++;
+ }
+
+ } // end_for
+return (mismatch);
+}
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA data structure */
+/* --------------------------------------------------------------- */
+void dma_data_struct_init(void)
+{
+ int i; /* loop counter */
+ unsigned int ptr;
+
+ int ch_num; /* number of channels */
+ unsigned int blksize; /* Size of DMA data structure in bytes */
+ unsigned int blkmask; /* address mask */
+
+
+ ch_num = (((CMSDK_DMA->DMA_STATUS) >> 16) & 0x1F)+1;
+ blksize = ch_num * 32;
+ if (ch_num > 16) blkmask = 0x3FF; /* 17 to 32 */
+ else if (ch_num > 8) blkmask = 0x1FF; /* 9 to 16 */
+ else if (ch_num > 4) blkmask = 0x0FF; /* 5 to 8 */
+ else if (ch_num > 2) blkmask = 0x07F; /* 3 to 4 */
+ else if (ch_num > 1) blkmask = 0x07F; /* 2 */
+ else blkmask = 0x03F; /* 1 */
+
+ /* Create DMA data structure in RAM after stack
+ In the linker script, a 1KB memory stack above stack is reserved
+ so we can use this space for putting the DMA data structure.
+ */
+
+ ptr = HW32_REG(0); /* Read Top of Stack */
+
+ /* the DMA data structure must be aligned to the size of the data structure */
+ if ((ptr & blkmask) != 0x0)
+ ptr = (ptr + blksize) & ~blkmask;
+
+ if ((ptr + blksize) > (RAM_ADDRESS_MAX + 1)) {
+ puts ("ERROR : Not enough RAM space for DMA data structure.");
+ UartEndSimulation();
+ }
+
+ /* Set pointer to the reserved space */
+ dma_data = (pl230_dma_data_structure *) ptr;
+ ptr = (unsigned int) &dma_data->Primary->SrcEndPointer;
+
+ printf ("dma structure block address = %x\n", ptr);
+
+ for (i=0; i<1; i++) {
+ dma_data->Primary->SrcEndPointer = 0;
+ dma_data->Primary->DestEndPointer = 0;
+ dma_data->Primary->Control = 0;
+ dma_data->Alternate->SrcEndPointer = 0;
+ dma_data->Alternate->DestEndPointer = 0;
+ dma_data->Alternate->Control = 0;
+ }
+
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA PL230 */
+/* --------------------------------------------------------------- */
+void dma_pl230_init(void)
+{
+ unsigned int current_state;
+ puts ("Initialize PL230");
+ current_state = CMSDK_DMA->DMA_STATUS;
+ printf ("- # of channels allowed : %d\n",(((current_state) >> 16) & 0x1F)+1);
+ /* Debugging printfs: */
+ /*printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));*/
+ /*printf ("- Current master enable : %x\n",(((current_state) >> 0) & 0x1));*/
+
+ /* Wait until current DMA complete */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ if (!((current_state==0) || (current_state==0x8) || (current_state==0x9))) {
+ puts ("- wait for DMA IDLE/STALLED/DONE");
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+
+ }
+ while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
+ /* Wait if not IDLE/STALLED/DONE */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+ }
+ CMSDK_DMA->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ CMSDK_DMA->CTRL_BASE_PTR = (unsigned int) &dma_data->Primary->SrcEndPointer;
+ /* Set DMA data structure address */
+ CMSDK_DMA->CHNL_ENABLE_CLR = 0xFFFFFFFF; /* Disable all channels */
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+ CMSDK_DMA->DMA_CFG = 1; /* Enable DMA controller */
+
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* DMA memory copy */
+/* --------------------------------------------------------------- */
+void dma_memory_copy (unsigned int src, unsigned int dest, unsigned int size, unsigned int num)
+{
+ unsigned long src_end_pointer = src + ((1<<size)*(num-1));
+ unsigned long dst_end_pointer = dest + ((1<<size)*(num-1));
+ unsigned long control = (size << 30) | /* dst_inc */
+ (size << 28) | /* dst_size */
+ (size << 26) | /* src_inc */
+ (size << 24) | /* src_size */
+ (size << 21) | /* dst_prot_ctrl - HPROT[3:1] */
+ (size << 18) | /* src_prot_ctrl - HPROT[3:1] */
+ (0 << 14) | /* R_power */
+ ((num-1)<< 4) | /* n_minus_1 */
+ (0 << 3) | /* next_useburst */
+ (2 << 0) ; /* cycle_ctrl - auto */
+
+ /* By default the PL230 is little-endian; if the processor is configured
+ * big-endian then the configuration data that is written to memory must be
+ * byte-swapped before being written. This is also true if the processor is
+ * little-endian and the PL230 is big-endian.
+ * Remove the __REV usage if the processor and PL230 are configured with the
+ * same endianness
+ * */
+ dma_data->Primary->SrcEndPointer = (EXPECTED_BE) ? __REV(src_end_pointer) : (src_end_pointer);
+ dma_data->Primary->DestEndPointer = (EXPECTED_BE) ? __REV(dst_end_pointer) : (dst_end_pointer);
+ dma_data->Primary->Control = (EXPECTED_BE) ? __REV(control ) : (control );
+ /* Debugging printfs: */
+ /*printf ("SrcEndPointer = %x\n", dma_data->Primary->SrcEndPointer);*/
+ /*printf ("DestEndPointer = %x\n", dma_data->Primary->DestEndPointer);*/
+
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+ CMSDK_DMA->CHNL_SW_REQUEST = (1<<0); /* request channel 0 DMA */
+
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* Simple software DMA test */
+/* --------------------------------------------------------------- */
+int dma_simple_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ unsigned int current_state;
+
+
+ puts("uDMA simple test");
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 2, 4);
+ do { /* Wait until PL230 DMA controller return to idle state */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ } while (current_state!=0);
+
+ for (i=0;i<4;i++) {
+ /* Debugging printf: */
+ /*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
+ if (dest_data_array[i]!= i){
+ printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
+ err_code |= (1<<i);
+ }
+ }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : simple DMA failed (0x%x)\n", err_code);
+ return_val=1;
+ } else {
+ puts ("-Passed");
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* Simple DMA interrupt test */
+/* --------------------------------------------------------------- */
+int dma_interrupt_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ unsigned int current_state;
+
+
+ puts("DMA interrupt test");
+ puts("- DMA done");
+
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 2, 4);
+ delay();
+ /* Can't guarantee that there is sleep support, so use a polling loop */
+ do { /* Wait until PL230 DMA controller return to idle state */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ } while (current_state!=0);
+
+ for (i=0;i<4;i++) {
+ /* Debugging printf: */
+ /*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
+ if (dest_data_array[i]!= i){
+ printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
+ err_code |= (1<<i);
+ }
+ }
+
+ if (dma_done_irq_occurred==0){
+ puts ("ERROR: DMA done IRQ missing");
+ err_code |= (1<<4);
+ }
+
+ puts("- DMA err");
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_error_irq_expected = 1;
+ dma_error_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ /* Generate DMA transfer to invalid memory location */
+ dma_memory_copy ((unsigned int) &source_data_array[0],0x1F000000, 2, 4);
+ delay();
+ /* Can't guarantee that there is sleep support, so use a polling loop */
+ do { /* Wait until PL230 DMA controller return to idle state */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ } while (current_state!=0);
+
+ if (dma_error_irq_occurred==0){
+ puts ("ERROR: DMA err IRQ missing");
+ err_code |= (1<<5);
+ }
+
+
+ /* Clear up */
+ dma_done_irq_expected = 0;
+ dma_done_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ NVIC_DisableIRQ(DMA_IRQn);
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : DMA done interrupt failed (0x%x)\n", err_code);
+ return_val=1;
+ } else {
+ puts ("-Passed");
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* DMA event test */
+/* --------------------------------------------------------------- */
+int dma_event_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ unsigned int current_state;
+
+
+ puts("DMA event test");
+ puts("- DMA done event to RXEV");
+
+ CMSDK_DMA->CHNL_ENABLE_SET = (1<<0); /* Enable channel 0 */
+
+ /* setup data for DMA */
+ for (i=0;i<4;i++) {
+ source_data_array[i] = i;
+ dest_data_array[i] = 0;
+ }
+
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_DisableIRQ(DMA_IRQn);
+
+ /* Clear event register - by setting event with SEV and then clear it with WFE */
+ __SEV();
+ __WFE(); /* First WFE will not enter sleep because of previous event */
+
+ dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 2, 4);
+ __WFE(); /* This will cause the processor to enter sleep */
+
+ /* Processor woken up */
+ current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
+ if (current_state!=0) {
+ puts ("ERROR: DMA status should be IDLE after wake up");
+ err_code |= (1<<5);
+ }
+
+ for (i=0;i<4;i++) {
+ /*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
+ if (dest_data_array[i]!= i){
+ printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
+ err_code |= (1<<i);
+ }
+ }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : DMA event failed (0x%x)\n", err_code);
+ return_val=1;
+ } else {
+ puts ("-Passed");
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* DMA interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void DMA_Handler(void)
+{
+if ((CMSDK_DMA->ERR_CLR & 1) != 0) {
+ /* DMA interrupt is caused by DMA error */
+ dma_error_irq_occurred ++;
+ CMSDK_DMA->ERR_CLR = 1; /* Clear dma_err */
+ if (dma_error_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+else {
+ // DMA interrupt is caused by DMA done
+ dma_done_irq_occurred ++;
+ if (dma_done_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA done interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+}
+
+void HardFault_Handler(void)
+{
+ puts ("[Hard fault]\n");
+ UartEndSimulation();
+ while (1);
+}
+
+void delay(void)
+{
+ int i;
+ for (i=0;i<5;i++){
+ __ISB();
+ }
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/ext_sys_tests.c b/Cortex-M0/nanosoc/software/common/validation/ext_sys_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..f0ffe1f4f500a37ef5284486d9a87a03e6b75f4a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/ext_sys_tests.c
@@ -0,0 +1,677 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the operation of components instantiated in the
+ extended example subsystem.
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#if defined ( __CC_ARM )
+__asm void address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ void address_test_write(unsigned int addr, unsigned int wdata);
+ unsigned int address_test_read(unsigned int addr);
+#endif
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+
+/* Macros for word, half word and byte */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+#define ADDR_BASE_APB4_EG_SLAVE_1 0x50000000
+#define ADDR_BASE_APB4_EG_SLAVE_2 0x52000000
+#define ADDR_BASE_APB3_EG_SLAVE 0x50001000
+#define ADDR_BASE_AHB_EG_SLAVE 0x50020000
+#define ADDR_BASE_AHB_TB_SLAVE_1 0x50002000
+#define ADDR_BASE_AHB_TB_SLAVE_2 0x51010000
+#define ADDR_BASE_AHB_TB_SLAVE_3 0x52002000
+
+/* Function definition */
+int check_apb4_eg_slave(unsigned long base_addr);
+int check_apb3_eg_slave(unsigned long base_addr);
+int check_ahb_eg_slave(unsigned long base_addr);
+int check_ahb_tb_slave(unsigned long base_addr);
+int check_default_slave(unsigned long base_addr);
+
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+volatile int probe_ext_eg_sys=0; /* Set to 1 for memory map probing */
+
+// -----------------------------------------------------------
+// Start of main program
+// -----------------------------------------------------------
+
+int main (void)
+{
+ int result=0;
+ unsigned int dummy; /* dummy variable for memory probing */
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Extended Subsystem Test - revision $Revision: 371321 $\n");
+
+ probe_ext_eg_sys = 1; /* Probe to see if extended subsystem is included */
+ /* If extended subsystem is included, the following read will be carried out,
+ otherwise an error response will be received and enter hard fault */
+ dummy = HW32_REG(ADDR_BASE_APB4_EG_SLAVE_1 + 0xFE0);
+
+ probe_ext_eg_sys = 0; /* Example system exist, continue operation */
+
+ temp_data=0;
+
+ // Test access to APB4 Example Slave
+ result |= check_apb4_eg_slave(ADDR_BASE_APB4_EG_SLAVE_1);
+ result |= check_apb4_eg_slave(ADDR_BASE_APB4_EG_SLAVE_2);
+
+ // Test access to APB3 Example Slave
+ result |= check_apb3_eg_slave(ADDR_BASE_APB3_EG_SLAVE);
+
+ // Test access to AHB Example Slave
+ result |= check_ahb_eg_slave(ADDR_BASE_AHB_EG_SLAVE);
+
+ // Test access to AHB Trickbox Slave
+ result |= check_ahb_tb_slave(ADDR_BASE_AHB_TB_SLAVE_1);
+ result |= check_ahb_tb_slave(ADDR_BASE_AHB_TB_SLAVE_3);
+
+ // Test access to Default slave
+ puts ("Checking AHB Default slave");
+ result |= check_default_slave(0x52020000);
+ result |= check_default_slave(0x68000000);
+
+ /* clean up */
+ hardfault_expected = 0;
+
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+// -----------------------------------------------------------
+// Check the access to APB4 example slave
+// -----------------------------------------------------------
+int check_apb4_eg_slave(unsigned long base_addr)
+{
+ const char apb4_id[12] = {0x04, 0x00, 0x00, 0x00,
+ 0x19, 0xB8, 0x1B, 0x00,
+ 0x0D, 0xF0, 0x05, 0xB1};
+ int return_val=0;
+ int err_code=0;
+ int i;
+
+ puts ("Checking APB4 Example slave");
+ // -------------------------
+ puts ("- check ID values");
+ for (i=0; i<12; i++) {
+ if (HW32_REG(base_addr + 0xFD0 + 4*i) != apb4_id[i]) {
+ printf (" ID [%d] ERROR : expected %x, actual %x\n", i, apb4_id[i], HW32_REG(base_addr + 0xFD0 + 4*i));
+ err_code = err_code | 0x1;
+ }
+ }
+ // -------------------------
+ puts ("- initial data values");
+ for (i=0; i<4; i++) {
+ printf (" Data[%d] = %x\n", i, HW32_REG(base_addr + 4*i));
+ }
+
+ puts ("- check R/W in word size");
+
+ HW32_REG(base_addr ) = 0x12345678;
+ HW32_REG(base_addr +0x04) = 0x55CC33AA;
+ HW32_REG(base_addr +0x08) = 0xFF008765;
+ HW32_REG(base_addr +0x0C) = 0x99AABCDE;
+
+ if (HW32_REG(base_addr ) != 0x12345678) {err_code |= (1<<2); puts(" ERROR @ Data0");}
+ if (HW32_REG(base_addr +0x04) != 0x55CC33AA) {err_code |= (1<<2); puts(" ERROR @ Data1");}
+ if (HW32_REG(base_addr +0x08) != 0xFF008765) {err_code |= (1<<2); puts(" ERROR @ Data2");}
+ if (HW32_REG(base_addr +0x0C) != 0x99AABCDE) {err_code |= (1<<2); puts(" ERROR @ Data3");}
+
+
+ puts ("- check R/W in halfword size");
+
+ HW16_REG(base_addr ) = 0xA987;
+ HW16_REG(base_addr +0x02) = 0xEDCB;
+ HW16_REG(base_addr +0x04) = 0xCC55;
+ HW16_REG(base_addr +0x06) = 0xAA33;
+ HW16_REG(base_addr +0x08) = 0x789A;
+ HW16_REG(base_addr +0x0A) = 0x00FF;
+ HW16_REG(base_addr +0x0C) = 0x4321;
+ HW16_REG(base_addr +0x0E) = 0x6655;
+
+ if (HW16_REG(base_addr ) != 0xA987) {err_code |= (1<<3); puts(" ERROR @ Data0");}
+ if (HW16_REG(base_addr +0x02) != 0xEDCB) {err_code |= (1<<3); puts(" ERROR @ Data1");}
+ if (HW16_REG(base_addr +0x04) != 0xCC55) {err_code |= (1<<3); puts(" ERROR @ Data2");}
+ if (HW16_REG(base_addr +0x06) != 0xAA33) {err_code |= (1<<3); puts(" ERROR @ Data3");}
+ if (HW16_REG(base_addr +0x08) != 0x789A) {err_code |= (1<<3); puts(" ERROR @ Data4");}
+ if (HW16_REG(base_addr +0x0A) != 0x00FF) {err_code |= (1<<3); puts(" ERROR @ Data5");}
+ if (HW16_REG(base_addr +0x0C) != 0x4321) {err_code |= (1<<3); puts(" ERROR @ Data6");}
+ if (HW16_REG(base_addr +0x0E) != 0x6655) {err_code |= (1<<3); puts(" ERROR @ Data7");}
+
+ puts ("- check R/W in byte size");
+
+ HW8_REG(base_addr ) = 0xA9; // swap upper and lower byte
+ HW8_REG(base_addr +0x01) = 0x87;
+ HW8_REG(base_addr +0x02) = 0xED;
+ HW8_REG(base_addr +0x03) = 0xCB;
+ HW8_REG(base_addr +0x04) = 0xCC;
+ HW8_REG(base_addr +0x05) = 0x55;
+ HW8_REG(base_addr +0x06) = 0xAA;
+ HW8_REG(base_addr +0x07) = 0x33;
+ HW8_REG(base_addr +0x08) = 0x78;
+ HW8_REG(base_addr +0x09) = 0x9A;
+ HW8_REG(base_addr +0x0A) = 0x00;
+ HW8_REG(base_addr +0x0B) = 0xFF;
+ HW8_REG(base_addr +0x0C) = 0x43;
+ HW8_REG(base_addr +0x0D) = 0x21;
+ HW8_REG(base_addr +0x0E) = 0x66;
+ HW8_REG(base_addr +0x0F) = 0x55;
+
+ if (HW8_REG(base_addr ) != 0xA9) {err_code |= (1<<4); puts(" ERROR @ Data0");}
+ if (HW8_REG(base_addr +0x01) != 0x87) {err_code |= (1<<4); puts(" ERROR @ Data1");}
+ if (HW8_REG(base_addr +0x02) != 0xED) {err_code |= (1<<4); puts(" ERROR @ Data2");}
+ if (HW8_REG(base_addr +0x03) != 0xCB) {err_code |= (1<<4); puts(" ERROR @ Data3");}
+ if (HW8_REG(base_addr +0x04) != 0xCC) {err_code |= (1<<4); puts(" ERROR @ Data4");}
+ if (HW8_REG(base_addr +0x05) != 0x55) {err_code |= (1<<4); puts(" ERROR @ Data5");}
+ if (HW8_REG(base_addr +0x06) != 0xAA) {err_code |= (1<<4); puts(" ERROR @ Data6");}
+ if (HW8_REG(base_addr +0x07) != 0x33) {err_code |= (1<<4); puts(" ERROR @ Data7");}
+ if (HW8_REG(base_addr +0x08) != 0x78) {err_code |= (1<<4); puts(" ERROR @ Data8");}
+ if (HW8_REG(base_addr +0x09) != 0x9A) {err_code |= (1<<4); puts(" ERROR @ Data9");}
+ if (HW8_REG(base_addr +0x0A) != 0x00) {err_code |= (1<<4); puts(" ERROR @ DataA");}
+ if (HW8_REG(base_addr +0x0B) != 0xFF) {err_code |= (1<<4); puts(" ERROR @ DataB");}
+ if (HW8_REG(base_addr +0x0C) != 0x43) {err_code |= (1<<4); puts(" ERROR @ DataC");}
+ if (HW8_REG(base_addr +0x0D) != 0x21) {err_code |= (1<<4); puts(" ERROR @ DataD");}
+ if (HW8_REG(base_addr +0x0E) != 0x66) {err_code |= (1<<4); puts(" ERROR @ DataE");}
+ if (HW8_REG(base_addr +0x0F) != 0x55) {err_code |= (1<<4); puts(" ERROR @ DataF");}
+
+ if (err_code != 0) {
+ printf ("ERROR : APB4 eg slave access failed (0x%x)\n", err_code);
+ return_val=1;
+
+ err_code = 0;
+ }
+ return(return_val);
+
+}
+// -----------------------------------------------------------
+// Check the access to APB3 example slave
+// -----------------------------------------------------------
+int check_apb3_eg_slave(unsigned long base_addr)
+{
+ const char apb3_id[12] = {0x04, 0x00, 0x00, 0x00,
+ 0x18, 0xB8, 0x1B, 0x00,
+ 0x0D, 0xF0, 0x05, 0xB1};
+ int return_val=0;
+ int err_code=0;
+ int i;
+
+ puts ("Checking APB3 Example slave");
+ // -------------------------
+ puts ("- check ID values");
+ for (i=0; i<12; i++) {
+ if (HW32_REG(base_addr + 0xFD0 + 4*i) != apb3_id[i]) {
+ printf (" ID [%d] ERROR : expected %x, actual %x\n", i, apb3_id[i], HW32_REG(base_addr + 0xFD0 + 4*i));
+ err_code = err_code | 0x1;
+ }
+ }
+ // -------------------------
+ puts ("- initial data values");
+ for (i=0; i<4; i++) {
+ printf (" Data[%d] = %x\n", i, HW32_REG(ADDR_BASE_APB3_EG_SLAVE + 4*i));
+ }
+
+ puts ("- check R/W in word size");
+
+ HW32_REG(base_addr ) = 0x12345678;
+ HW32_REG(base_addr +0x04) = 0x55CC33AA;
+ HW32_REG(base_addr +0x08) = 0xFF008765;
+ HW32_REG(base_addr +0x0C) = 0x99AABCDE;
+
+ if (HW32_REG(base_addr ) != 0x12345678) {err_code |= (1<<2); puts(" ERROR @ Data0");}
+ if (HW32_REG(base_addr +0x04) != 0x55CC33AA) {err_code |= (1<<2); puts(" ERROR @ Data1");}
+ if (HW32_REG(base_addr +0x08) != 0xFF008765) {err_code |= (1<<2); puts(" ERROR @ Data2");}
+ if (HW32_REG(base_addr +0x0C) != 0x99AABCDE) {err_code |= (1<<2); puts(" ERROR @ Data3");}
+
+
+
+ if (err_code != 0) {
+ printf ("ERROR : APB3 eg slave access failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+ return(return_val);
+
+}
+// -----------------------------------------------------------
+// Check the access to AHB example slave
+// -----------------------------------------------------------
+int check_ahb_eg_slave(unsigned long base_addr)
+{
+ const char ahb_id[12] = {0x04, 0x00, 0x00, 0x00,
+ 0x17, 0xB8, 0x1B, 0x00,
+ 0x0D, 0xF0, 0x05, 0xB1};
+ int return_val=0;
+ int err_code=0;
+ int i;
+
+ puts ("Checking AHB Example slave");
+ // -------------------------
+ puts ("- check ID values");
+ for (i=0; i<12; i++) {
+ if (HW32_REG(base_addr + 0xFD0 + 4*i) != ahb_id[i]) {
+ printf (" ID [%d] ERROR : expected %x, actual %x\n", i, ahb_id[i], HW32_REG(base_addr + 0xFD0 + 4*i));
+ err_code = err_code | 0x1;
+ }
+ }
+ // -------------------------
+ puts ("- initial data values");
+ for (i=0; i<4; i++) {
+ printf (" Data[%d] = %x\n", i, HW32_REG(ADDR_BASE_AHB_EG_SLAVE + 4*i));
+ }
+
+ puts ("- check R/W in word size");
+
+ HW32_REG(base_addr ) = 0x12345678;
+ HW32_REG(base_addr +0x04) = 0x55CC33AA;
+ HW32_REG(base_addr +0x08) = 0xFF008765;
+ HW32_REG(base_addr +0x0C) = 0x99AABCDE;
+
+ if (HW32_REG(base_addr ) != 0x12345678) {err_code |= (1<<2); puts(" ERROR @ Data0");}
+ if (HW32_REG(base_addr +0x04) != 0x55CC33AA) {err_code |= (1<<2); puts(" ERROR @ Data1");}
+ if (HW32_REG(base_addr +0x08) != 0xFF008765) {err_code |= (1<<2); puts(" ERROR @ Data2");}
+ if (HW32_REG(base_addr +0x0C) != 0x99AABCDE) {err_code |= (1<<2); puts(" ERROR @ Data3");}
+
+
+ puts ("- check R/W in halfword size");
+
+ HW16_REG(base_addr ) = 0xA987;
+ HW16_REG(base_addr +0x02) = 0xEDCB;
+ HW16_REG(base_addr +0x04) = 0xCC55;
+ HW16_REG(base_addr +0x06) = 0xAA33;
+ HW16_REG(base_addr +0x08) = 0x789A;
+ HW16_REG(base_addr +0x0A) = 0x00FF;
+ HW16_REG(base_addr +0x0C) = 0x4321;
+ HW16_REG(base_addr +0x0E) = 0x6655;
+
+ if (HW16_REG(base_addr ) != 0xA987) {err_code |= (1<<3); puts(" ERROR @ Data0");}
+ if (HW16_REG(base_addr +0x02) != 0xEDCB) {err_code |= (1<<3); puts(" ERROR @ Data1");}
+ if (HW16_REG(base_addr +0x04) != 0xCC55) {err_code |= (1<<3); puts(" ERROR @ Data2");}
+ if (HW16_REG(base_addr +0x06) != 0xAA33) {err_code |= (1<<3); puts(" ERROR @ Data3");}
+ if (HW16_REG(base_addr +0x08) != 0x789A) {err_code |= (1<<3); puts(" ERROR @ Data4");}
+ if (HW16_REG(base_addr +0x0A) != 0x00FF) {err_code |= (1<<3); puts(" ERROR @ Data5");}
+ if (HW16_REG(base_addr +0x0C) != 0x4321) {err_code |= (1<<3); puts(" ERROR @ Data6");}
+ if (HW16_REG(base_addr +0x0E) != 0x6655) {err_code |= (1<<3); puts(" ERROR @ Data7");}
+
+ puts ("- check R/W in byte size");
+
+ HW8_REG(base_addr ) = 0xA9; // swap upper and lower byte
+ HW8_REG(base_addr +0x01) = 0x87;
+ HW8_REG(base_addr +0x02) = 0xED;
+ HW8_REG(base_addr +0x03) = 0xCB;
+ HW8_REG(base_addr +0x04) = 0xCC;
+ HW8_REG(base_addr +0x05) = 0x55;
+ HW8_REG(base_addr +0x06) = 0xAA;
+ HW8_REG(base_addr +0x07) = 0x33;
+ HW8_REG(base_addr +0x08) = 0x78;
+ HW8_REG(base_addr +0x09) = 0x9A;
+ HW8_REG(base_addr +0x0A) = 0x00;
+ HW8_REG(base_addr +0x0B) = 0xFF;
+ HW8_REG(base_addr +0x0C) = 0x43;
+ HW8_REG(base_addr +0x0D) = 0x21;
+ HW8_REG(base_addr +0x0E) = 0x66;
+ HW8_REG(base_addr +0x0F) = 0x55;
+
+ if (HW8_REG(base_addr ) != 0xA9) {err_code |= (1<<4); puts(" ERROR @ Data0");}
+ if (HW8_REG(base_addr +0x01) != 0x87) {err_code |= (1<<4); puts(" ERROR @ Data1");}
+ if (HW8_REG(base_addr +0x02) != 0xED) {err_code |= (1<<4); puts(" ERROR @ Data2");}
+ if (HW8_REG(base_addr +0x03) != 0xCB) {err_code |= (1<<4); puts(" ERROR @ Data3");}
+ if (HW8_REG(base_addr +0x04) != 0xCC) {err_code |= (1<<4); puts(" ERROR @ Data4");}
+ if (HW8_REG(base_addr +0x05) != 0x55) {err_code |= (1<<4); puts(" ERROR @ Data5");}
+ if (HW8_REG(base_addr +0x06) != 0xAA) {err_code |= (1<<4); puts(" ERROR @ Data6");}
+ if (HW8_REG(base_addr +0x07) != 0x33) {err_code |= (1<<4); puts(" ERROR @ Data7");}
+ if (HW8_REG(base_addr +0x08) != 0x78) {err_code |= (1<<4); puts(" ERROR @ Data8");}
+ if (HW8_REG(base_addr +0x09) != 0x9A) {err_code |= (1<<4); puts(" ERROR @ Data9");}
+ if (HW8_REG(base_addr +0x0A) != 0x00) {err_code |= (1<<4); puts(" ERROR @ DataA");}
+ if (HW8_REG(base_addr +0x0B) != 0xFF) {err_code |= (1<<4); puts(" ERROR @ DataB");}
+ if (HW8_REG(base_addr +0x0C) != 0x43) {err_code |= (1<<4); puts(" ERROR @ DataC");}
+ if (HW8_REG(base_addr +0x0D) != 0x21) {err_code |= (1<<4); puts(" ERROR @ DataD");}
+ if (HW8_REG(base_addr +0x0E) != 0x66) {err_code |= (1<<4); puts(" ERROR @ DataE");}
+ if (HW8_REG(base_addr +0x0F) != 0x55) {err_code |= (1<<4); puts(" ERROR @ DataF");}
+
+ if (err_code != 0) {
+ printf ("ERROR : AHB eg slave access failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+ return(return_val);
+
+}
+
+// -----------------------------------------------------------
+// Check the access to AHB trickbox slave
+// -----------------------------------------------------------
+int check_ahb_tb_slave(unsigned long base_addr)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+
+ puts ("Checking AHB Trickbox slave");
+
+ // First four words are the same data registers with different wait states
+ puts ("- check R/W in word size");
+ HW32_REG(base_addr ) = 0x12345678;
+ if (HW32_REG(base_addr ) != 0x12345678) {err_code |= (1<<0); puts(" ERROR @ Data0");}
+ HW32_REG(base_addr +0x04) = 0x55CC33AA;
+ if (HW32_REG(base_addr +0x04) != 0x55CC33AA) {err_code |= (1<<0); puts(" ERROR @ Data1");}
+ HW32_REG(base_addr +0x08) = 0xFF008765;
+ if (HW32_REG(base_addr +0x08) != 0xFF008765) {err_code |= (1<<0); puts(" ERROR @ Data2");}
+ HW32_REG(base_addr +0x0C) = 0x99AABCDE;
+ if (HW32_REG(base_addr +0x0C) != 0x99AABCDE) {err_code |= (1<<0); puts(" ERROR @ Data3");}
+
+ puts ("- check R/W in half word size");
+ HW16_REG(base_addr ) = 0xA987;
+ if (HW16_REG(base_addr ) != 0xA987) {err_code |= (1<<1); puts(" ERROR @ Data0");}
+ HW16_REG(base_addr +0x02) = 0xEDCB;
+ if (HW16_REG(base_addr +0x02) != 0xEDCB) {err_code |= (1<<1); puts(" ERROR @ Data1");}
+ HW16_REG(base_addr +0x04) = 0xCC55;
+ if (HW16_REG(base_addr +0x04) != 0xCC55) {err_code |= (1<<1); puts(" ERROR @ Data2");}
+ HW16_REG(base_addr +0x06) = 0xAA33;
+ if (HW16_REG(base_addr +0x06) != 0xAA33) {err_code |= (1<<1); puts(" ERROR @ Data3");}
+ HW16_REG(base_addr +0x08) = 0x789A;
+ if (HW16_REG(base_addr +0x08) != 0x789A) {err_code |= (1<<1); puts(" ERROR @ Data4");}
+ HW16_REG(base_addr +0x0A) = 0x00FF;
+ if (HW16_REG(base_addr +0x0A) != 0x00FF) {err_code |= (1<<1); puts(" ERROR @ Data5");}
+ HW16_REG(base_addr +0x0C) = 0x4321;
+ if (HW16_REG(base_addr +0x0C) != 0x4321) {err_code |= (1<<1); puts(" ERROR @ Data6");}
+ HW16_REG(base_addr +0x0E) = 0x6655;
+ if (HW16_REG(base_addr +0x0E) != 0x6655) {err_code |= (1<<1); puts(" ERROR @ Data7");}
+
+ puts ("- check R/W in byte size");
+ HW8_REG(base_addr ) = 0xA9; // swap upper and lower byte
+ if (HW8_REG(base_addr ) != 0xA9) {err_code |= (1<<2); puts(" ERROR @ Data0");}
+ HW8_REG(base_addr +0x01) = 0x87;
+ if (HW8_REG(base_addr +0x01) != 0x87) {err_code |= (1<<2); puts(" ERROR @ Data1");}
+ HW8_REG(base_addr +0x02) = 0xED;
+ if (HW8_REG(base_addr +0x02) != 0xED) {err_code |= (1<<2); puts(" ERROR @ Data2");}
+ HW8_REG(base_addr +0x03) = 0xCB;
+ if (HW8_REG(base_addr +0x03) != 0xCB) {err_code |= (1<<2); puts(" ERROR @ Data3");}
+ HW8_REG(base_addr +0x04) = 0xCC;
+ if (HW8_REG(base_addr +0x04) != 0xCC) {err_code |= (1<<2); puts(" ERROR @ Data4");}
+ HW8_REG(base_addr +0x05) = 0x55;
+ if (HW8_REG(base_addr +0x05) != 0x55) {err_code |= (1<<2); puts(" ERROR @ Data5");}
+ HW8_REG(base_addr +0x06) = 0xAA;
+ if (HW8_REG(base_addr +0x06) != 0xAA) {err_code |= (1<<2); puts(" ERROR @ Data6");}
+ HW8_REG(base_addr +0x07) = 0x33;
+ if (HW8_REG(base_addr +0x07) != 0x33) {err_code |= (1<<2); puts(" ERROR @ Data7");}
+ HW8_REG(base_addr +0x08) = 0x78;
+ if (HW8_REG(base_addr +0x08) != 0x78) {err_code |= (1<<2); puts(" ERROR @ Data8");}
+ HW8_REG(base_addr +0x09) = 0x9A;
+ if (HW8_REG(base_addr +0x09) != 0x9A) {err_code |= (1<<2); puts(" ERROR @ Data9");}
+ HW8_REG(base_addr +0x0A) = 0x00;
+ if (HW8_REG(base_addr +0x0A) != 0x00) {err_code |= (1<<2); puts(" ERROR @ DataA");}
+ HW8_REG(base_addr +0x0B) = 0xFF;
+ if (HW8_REG(base_addr +0x0B) != 0xFF) {err_code |= (1<<2); puts(" ERROR @ DataB");}
+ HW8_REG(base_addr +0x0C) = 0x43;
+ if (HW8_REG(base_addr +0x0C) != 0x43) {err_code |= (1<<2); puts(" ERROR @ DataC");}
+ HW8_REG(base_addr +0x0D) = 0x21;
+ if (HW8_REG(base_addr +0x0D) != 0x21) {err_code |= (1<<2); puts(" ERROR @ DataD");}
+ HW8_REG(base_addr +0x0E) = 0x66;
+ if (HW8_REG(base_addr +0x0E) != 0x66) {err_code |= (1<<2); puts(" ERROR @ DataE");}
+ HW8_REG(base_addr +0x0F) = 0x55;
+ if (HW8_REG(base_addr +0x0F) != 0x55) {err_code |= (1<<2); puts(" ERROR @ DataF");}
+
+
+ puts ("- check read to 0x010 to 0x0FF");
+ // address 0x010 to 0x0FF returns HADDR[7:0]
+ //
+ for (i=0x10;i<0x40;i=i+4){ // Higher address values will result in time out
+ if (HW32_REG(base_addr + i) != i) {
+ err_code |= (1<<3);
+ printf (" ERROR: %x, return %x\n", i, HW32_REG(base_addr + i));
+ }
+ }
+
+ // address 0x040 and above results in timeout
+ // Note:to reduce simulation time not all addresses are tested
+ puts ("- offset 0x040 and above results in timeout");
+ for (i=0x40;i<0xFF;i=i+28){ // Higher address values will result in time out
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(base_addr + i);
+
+ if (hardfault_occurred ==0) {
+ err_code |= (1<<4);
+ puts ("ERROR: Expected timeout did not take place");
+ }
+ }
+
+ puts ("- offset 0x100 and above results in error response/timeout");
+
+ // address 0x104 to 0x1FF results in error response
+ // Note:to reduce simulation time not all addresses are tested
+ for (i=0x104;i<0x180;i=i+20){ // Higher address values will result in time out
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(base_addr + i);
+
+ if (hardfault_occurred ==0) {
+ err_code |= (1<<5);
+ puts ("ERROR: Expected timeout did not take place");
+ }
+ }
+
+ hardfault_occurred = 0; // reset variables
+ hardfault_expected = 0;
+
+
+ if (err_code != 0) {
+ printf ("ERROR : AHB trickbox slave access failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+ return(return_val);
+
+}
+// -----------------------------------------------------------
+// Check the access to AHB default slave
+// -----------------------------------------------------------
+int check_default_slave(unsigned long base_addr)
+{
+ int return_val=0;
+ int err_code=0;
+
+ temp_data=0;
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+
+ printf ("- test R/W to %x\n",base_addr);
+ address_test_write(base_addr, 0x3456789A);
+ if (hardfault_occurred==0) {err_code |= (1<<2);}
+ hardfault_occurred = 0;
+
+ temp_data = address_test_read(base_addr);
+ if (hardfault_occurred==0) {err_code |= (1<<3);}
+ hardfault_occurred = 0;
+
+ hardfault_occurred = 0; // reset variables
+ hardfault_expected = 0;
+
+
+ if (err_code != 0) {
+ puts ("ERROR : AHB default slave access failed");
+ return_val=1;
+ err_code = 0;
+ }
+ return(return_val);
+
+}
+
+// -----------------------------------------------------------
+// Functions to handle read/write test with 16-bit memory
+// access instruction for bus fault testing.
+// -----------------------------------------------------------
+
+#if defined ( __CC_ARM )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ STR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ BX LR
+}
+
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ __asm(" str r1,[r0]\n"
+ " dsb \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+// -----------------------------------------------------------
+// Hard fault handler
+// Divided into two halves:
+// - assembly part to extract stack frame starting location
+// - C handler part to carry out processing and checks
+// -----------------------------------------------------------
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ if (probe_ext_eg_sys==1) {
+ puts (" - Extended Example System not available.\n - INCLUDE_EXT_SUBSYSTEM variable in rtl_sim/makefile is set to 0\nTest skipped.");
+ UartEndSimulation();
+ return;
+ }
+ puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ return;
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/gpio_driver_tests.c b/Cortex-M0/nanosoc/software/common/validation/gpio_driver_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..6374c0c69e7eff39ef3ebf402f57c7eb76fab707
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/gpio_driver_tests.c
@@ -0,0 +1,705 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the functionalities of gpio functions in the example device driver.
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#define ALTMASK 0x2A
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#define ALTMASK 0x2A
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#define ALTMASK 0xF82A
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#define ALTMASK 0xF82A
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "uart_stdout.h"
+#include "CMSDK_driver.h"
+
+/* Random seed used by GPIO_Mask_OP function */
+#define RANDOM_NUMBER 47563745
+
+/* Using ISB instruction to create a three cycles delay */
+#define small_delay __ISB
+
+volatile int intstatus[16] = { 0 }; /* Detected interrupt operation from GPIO IRQ handler */
+volatile int N = 0; /* Bit number being test - Data shared between GPIO_IRQ and PORT0_COMB_Handler */
+volatile uint32_t data = 0; /* Previous data in GPIO - Data shared between GPIO_IRQ and PORT0_COMB_Handler */
+
+/* Declare test functions */
+int GPIO_OPEN(void); /* tests the CMSDK GPIO output enable driver functions */
+int GPIO_AltFuncEN(void); /* tests the CMSDK GPIO Alternate Function driver functions */
+int GPIO_IRQ(void); /* tests the CMSDK GPIO IRQ driver functions */
+int GPIO_Mask_OP(void); /* tests the CMSDK GPIO Masked Accesses driver functions */
+
+int gpio0_id_check(void);
+int gpio1_id_check(void);
+
+int main (void)
+{
+ int result = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("Cortex Microcontroller System Design Kit - GPIO Driver Test - revision $Revision: 371321 $\n");
+
+ if (gpio0_id_check()!=0) {
+ puts ("GPIO 0 not present. Test skipped.");
+ UartEndSimulation();
+ return 0;}
+ if (gpio1_id_check()!=0) {
+ puts ("GPIO 1 not present. Test skipped.");
+ UartEndSimulation();
+ return 0;}
+
+ result |= GPIO_OPEN();
+ result |= GPIO_AltFuncEN();
+ result |= GPIO_IRQ();
+ result |= GPIO_Mask_OP();
+
+ if(result == 0) {
+ puts("** TEST PASSED **\n");
+ } else {
+ printf("** TEST FAILED **, Error code: (0x%x)\n", result);
+ }
+
+ UartEndSimulation();
+ return result;
+}
+
+/* GPIO ID check functions - detect if part number match expected value.
+ If not, the GPIO might not be available and therefore the test should be skipped.
+*/
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+int gpio0_id_check(void)
+{
+unsigned char gpio_id;
+
+ gpio_id = HW8_REG(CMSDK_GPIO0_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_GPIO0_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO0_BASE + 0xFE4) != 0xB8) ||
+ (gpio_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+int gpio1_id_check(void)
+{
+unsigned char gpio_id;
+
+ gpio_id = HW8_REG(CMSDK_GPIO1_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_GPIO1_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO1_BASE + 0xFE4) != 0xB8) ||
+ (gpio_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+
+/* GPIO_OPEN - This function tests the CMSDK GPIO output enable driver functions
+ - Set Output enable (OUTENABLESET)
+ - set Dataout to 0x0, due to the simulation pull up resistors,
+ read back value is 0xFFFF when all the Output Enable control bits
+ are not set.
+ - for each pin on the port set the OUTENABLE, each in turn and check the status of the register
+ - if the OUTENABLE for the specified pin is incorrect then change err_code
+ - this will set the value of the specified pin to 0, keep 0 value for subsequent pin tests
+ - if the Data-in for the port is incorrect then change err_code
+ - else test passed for specified pin
+ - if all pins pass, test passes
+
+ - Clear Alternate Function (OUTENABLECLR)
+ - using the current value of the Outen register all Outens will be cleared
+ - for each pin on the port clear the OUTENABLE, each in turn and check the status of the register
+ - if the OUTENABLE for the specified pin is incorrect then change err_code
+ - if the Data-in for the port is incorrect then change err_code i.e != pins enabled and 0xFFFF
+ - else test passed for specified pin
+ - if the OUTENABLE register is cleared then the test is classed as passed
+ */
+
+int GPIO_OPEN(void) /*output enable function*/
+{
+ int err_code = 0;
+ uint32_t i = 0;
+ uint32_t mask = 0;
+
+ puts("Stage 1 - GPIO Output Enable Test\n");
+
+ puts("- Stage 1a - Set GPIO Output Enable\n");
+
+ /* Test sequence :
+ Data output is set to 0x0000. Since output enable is 0x0000 by default,
+ the actual I/O port status is determined by external pull up so it is
+ 0xFFFF at starting. By enabling output enable bit by bit,
+ the read back value of I/O port data become 0xFFFE, 0xFFFC, 0xFFF8, etc.
+ */
+
+ CMSDK_GPIO0->DATAOUT = 0x0000; /* set data on all pins to logic 0 for the pull up resistor*/
+
+ for(i = 1; i < 65536; i <<= 1){
+
+ /* enable every pin starting at pin0 to pin15 while keeping the previous ones enabled */
+ /* so that the transition of the output enable register is as follows: 0000 -> 0001 -> 0011 -> 0111 -> 1111 */
+
+ mask |= i; /* mask is the expected value of OUTENABLE */
+ CMSDK_gpio_SetOutEnable(CMSDK_GPIO0, i); /* set specified bit in out enable register */
+
+ if(CMSDK_gpio_GetOutEnable(CMSDK_GPIO0) != mask) err_code += 1; /*check if the output enable register is not the*/
+ if(CMSDK_GPIO0->DATA != (0xFFFF & (~mask))) err_code += 1; /*same as the mask i.e. set up to and including*/
+ } /*the bit being set then increment error code */
+
+ /* OUTENABLE should be 0xFFFF */
+ printf("Output Enable Status: 0x%x\n\n", CMSDK_gpio_GetOutEnable(CMSDK_GPIO0));
+ mask = 0;
+
+ if(err_code) printf("Set Enable Test Failed, Error code: (0x%x\n)", err_code);
+ else puts("Set Enable Test Passed\n");
+
+ puts("- Stage 1b - Clear GPIO Output Enable\n");
+
+ for(i = 1; i < 65536; i <<= 1){
+
+ /* disable every pin starting at pin0 to pin15 while keeping the previously disabled ones disabled */
+ /* and previously enabled ones enabled starting at all enabled so that the transition of the output*/
+ /* enable register is as follows: 1111 -> 1110 -> 1100 -> 1000 -> 0000 */
+
+ mask |= i;
+ CMSDK_gpio_ClrOutEnable(CMSDK_GPIO0, i); /*clear specified bit in out enable register*/
+
+ if(~(CMSDK_gpio_GetOutEnable(CMSDK_GPIO0) | 0xFFFF0000) != mask) /*check if the output enable register is not the*/
+ err_code += 1; /*same as the mask i.e. clear up to and including*/
+ if(CMSDK_GPIO0->DATA != (0xFFFF & mask)) /*the bit being set then increment error code */
+ err_code += 1;
+ }
+
+ printf("Output Enable Status: 0x%x\n\n", CMSDK_gpio_GetOutEnable(CMSDK_GPIO0));
+
+ if(err_code) printf("Clear Output Enable Test Failed, Error code: (0x%x)\n", err_code);
+ else puts("Clear Output Enable Test Passed\n");
+
+ if(!err_code) return 0;
+ else return 1;
+}
+
+/* GPIO_AltFuncEN - This function tests the CMSDK GPIO Alternate Function driver functions
+ GPIO Port 1 is used for this test because GPIO pins in port 0 are not shared (AltFunc not implemented).
+ - Set Alternate Function (AltFunc)
+ - clear the alternate function register for all pins including TX2 (TUBE for puts)
+ - for each pin on the port set the AltFunc, each in turn and check the status of the register
+ - if the AltFunc for the specified pin is incorrect then change err_code
+ - else test passed for specified pin
+ - if the AltFunc register is set to 0x2A (M0) or 0xF82A (M3) then the test is classed as passed
+ - NOTE: it is these exact combinations as only AltFunc outputs can be set in the AltFunc register
+ as inputs have no effect as they are just routed to two places and pins without an AltFunc
+ the value is not affected so is zero constantly
+ - Clear Alternate Function (AltFunc)
+ - using the current vale of the AltFunc register all AltFuncs will be cleared apart for vital ones
+ - for each pin on the port clear the AltFunc, each in turn and check the status of the register
+ - if the AltFunc for the specified pin is incorrect then change err_code unless it is TX2 as this
+ is used for stdout so must remain set
+ - else test passed for specified pin
+ - if the AltFunc register is set to 0x20 (TX2 - pin 5) then the test is classed as passed
+ */
+
+int GPIO_AltFuncEN(void)
+{
+ int err_code = 0;
+ uint32_t i = 0;
+ uint32_t mask = 0;
+
+ puts("Stage 2 - GPIO Alternative Function Enable Test\n");
+
+ puts("- Stage 2a - Set GPIO Alternative Function Enable\n");
+
+ CMSDK_gpio_ClrAltFunc(CMSDK_GPIO1, 0xFFFF); /* Clear alternate function on all GPIO Port 1 pins to zero */
+
+ for(i = 1; i < 65536; i <<= 1){
+
+ //Set alternate function on all GPIO Port 1 pins which have an alternate function output port
+ //will not affect those with either no alternate function or those which the pin is an input for
+ //the alternate function so when read back the value with all alternate function is 0x2A for M0
+ //and 0xf82A for M3, because the only pins that the alternate function affects is the UART
+ //TX0 (pin 1), TX1 (pin 3), TX2 (pin 5)
+
+ mask |= i;
+ CMSDK_gpio_SetAltFunc(CMSDK_GPIO1, i); //set alternate function register for the specified bit
+ if(CMSDK_gpio_GetAltFunc(CMSDK_GPIO1) != (ALTMASK & mask)) /*check if the AltFunc register is not the same as the*/
+ err_code += i; /*AltFunc mask i.e. all pins which have one, up to and including*/
+ } /*the bit being set then if not increment error code */
+
+ printf("\nAlternate Function Enable Status: 0x%x\n\n", CMSDK_gpio_GetAltFunc(CMSDK_GPIO1));
+
+ if(err_code) printf("Set Enable Test Failed, Error code: (0x%x\n)", err_code);
+ else puts("Set Enable Test Passed\n"); //if the port did not set the AltFunc as expected display error*/
+
+ puts("- Stage 2b - Clear GPIO Alternative Function Enable\n");
+
+ mask = 0;
+
+ for(i = 1; i < 65536; i <<= 1){
+
+ /* Clear AltFunc bit by bit apart from bit 5 for stdout */
+
+ //Clear alternate function on all GPIO Port 1 pins which have an alternate function output port
+ //will not affect those with either no alternate function or those which the pin is an input for
+ //the alternate function so when read back the value with all alternate function is 0x20 for M0
+ //and M3 because must leave the TX2 enabled for the TUBE
+
+ mask |= i;
+
+ /*clear alternate function register for the specified bit except for UART2 TX for tube*/
+
+ CMSDK_gpio_ClrAltFunc(CMSDK_GPIO1, i & (~0x20));
+
+ if(CMSDK_gpio_GetAltFunc(CMSDK_GPIO1) != ((ALTMASK & (~mask )) | 0x20)) /*check if the AltFunc register is not the same as the*/
+ err_code += i; /*AltFunc mask i.e. all pins which have one, up to and including*/
+ /*the bit being set then if not increment error code */
+ }
+
+ printf("Alternate Function Enable Status: 0x%x\n\n", CMSDK_gpio_GetAltFunc(CMSDK_GPIO1)); /*display Port's AltFunc Setting*/
+
+ if(err_code) printf("Clear Enable Test Failed, Error code: (0x%x)\n", err_code);
+ else puts("Clear Enable Test Passed\n"); /*if the port did not clear the AltFunc as expected display error*/
+
+ if(!err_code) return 0;
+ else return 2;
+}
+
+/* GPIO_IRQ - This function tests the CMSDK GPIO IRQ driver functions
+
+ - Test High level IRQ
+ - Set DataOut to 0x0000 ready for high level test
+ - Enable all pins as output
+ - Set all pins as a high level interrupt and clear all pending IRQs
+ - Global enable (NVIC) the interrupts on the port
+ - for each pin on the port enable the CMSDK GPIO interrupt for that pin then set the Dataout on the specified pin high
+ - Check the inten register for the specified pin to check that it's set
+ - in ISR, record what type of interrupt it's meant to be according to the intpol and inttype registers
+ - if either the inten, intpol or inttype are incorrect then change err_code
+ - else test passed for specified pin
+ - if test on each pin passes the test as a whole passes and return 0 to main
+ - else return an error
+
+ - Test Rising Edge IRQ
+ - Set DataOut to 0x0000 ready for rising edge test
+ - Set all pins as a Rising Edge interrupt and clear all pending IRQs
+ - for each pin on the port enable the CMSDK GPIO interrupt for that pin
+ - set the Dataout on the specified pin high and keep high for subsequent pin tests (so can move on to falling edge tests)
+ - Check the inten register for the specified pin to check that it's set
+ - in ISR, record what type of interrupt it's meant to be according to the intpol and inttype registers
+ - if either the inten, intpol or inttype are incorrect then change err_code
+ - else test passed for specified pin
+ - if test on each pin passes the test as a whole passes and return 0 to main
+ - else return an error
+
+ - Test Falling Edge IRQ
+ - DataOut is already set to 0xFFFF from rising edge test
+ - Set all pins as a Falling Edge interrupt and clear all pending IRQs
+ - for each pin on the port enable the CMSDK GPIO interrupt for that pin
+ - set the Dataout on the specified pin low and keep low for subsequent pin tests
+ - Check the inten register for the specified pin to check that it's set
+ - in ISR, record what type of interrupt it's meant to be according to the intpol and inttype registers
+ - if either the inten, intpol or inttype are incorrect then change err_code
+ - else test passed for specified pin
+ - if test on each pin passes the test as a whole passes and return 0 to main
+ - else return an error
+
+ - Test Low level IRQ
+ - Set DataOut to 0xFFFF ready for low level test
+ - Enable all pins as output
+ - Set all pins as a low level interrupt and clear all pending IRQs
+ - for each pin, in turn, on the port enable the CMSDK GPIO interrupt for that pin
+ - set the Dataout on the specified pin low whilst the interrupts are enabled then back high before clearing it
+ - Check the inten register for the specified pin to check that it's set
+ - in ISR, record what type of interrupt it's meant to be according to the intpol and inttype registers
+ - if either the inten, intpol or inttype are incorrect then change err_code
+ - else test passed for specified pin
+ - if test on each pin passes the test as a whole passes and return 0 to main
+ - else return an error
+ */
+
+int GPIO_IRQ(void)
+{
+ uint32_t err_code = 0, return_val = 0;
+ int i = 0;
+ int irq_counter = 0;
+
+ puts("Stage 3 - GPIO Pin IRQ Test\n");
+
+ puts("- Stage 3a - GPIO High Level IRQ Test\n");
+
+ CMSDK_GPIO0->DATAOUT = 0x0000; //set data out to 0 to test high level IRQ
+ CMSDK_gpio_SetOutEnable(CMSDK_GPIO0, 0xFFFF); //set output enable to output on all ports of GPIO 0
+
+ for(i = 0; i < 16; i++)
+ {
+ CMSDK_gpio_SetIntHighLevel(CMSDK_GPIO0, i); //set all pins to high level interrupt and clear any
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, i); //outstanding set interrupts
+ }
+
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn); //clear all global NVIC PORT0 pending interrupts
+
+ NVIC_EnableIRQ(PORT0_ALL_IRQn); //enable NVIC interrupts on PORT0
+
+ for(i = 0; i < 16; i++){
+
+ CMSDK_gpio_SetIntEnable(CMSDK_GPIO0, i); //enable interrupt for the pin to be tested
+
+ if(!((CMSDK_GPIO0->INTENSET) & (1 << i))) err_code = (1 << (2*i));//check to see if the interrupt enable register is
+ //set for the pin which it should have just been
+ N = i;
+
+ CMSDK_GPIO0->DATAOUT = (0x0001 << i); //set data out on pin0 high to cause a high level interrupt
+ //repeat for all other pins 0001 -> 0010 -> 0100 -> 1000
+ CMSDK_gpio_ClrIntEnable(CMSDK_GPIO0, i ); /*clear interrupt enable*/
+
+ if((CMSDK_GPIO0->INTENSET) & ~(1 << i)) err_code = (1 << (2*i +1));//check to see if the interrupt enable register is
+ //clear for the pin which it should have just been
+
+ /* check to see whether intstatus, for the specified pin, is 2, which corresponds to a high level interrupt */
+
+ if(intstatus[i] == 2) irq_counter++;
+ else err_code |= (1 << i);
+ }
+
+ if((irq_counter == 16) && (err_code == 0)) puts("High Level IRQ Tests Passed Successfully\n");
+ else{
+ printf("\nHigh Level IRQ Tests Failed, Error Code: (0x%x)\n", err_code);
+ err_code = 0; /*if the port did not have 1 HL IRQ for each pin as expected then display error*/
+ return_val = 8;
+ }
+
+ puts("- Stage 3b - GPIO Rising Edge IRQ Test\n");
+
+ irq_counter = 0;
+
+ CMSDK_GPIO0->DATAOUT = 0x0000; //set data out to 0 to test rising edge IRQ
+
+ for(i = 0; i < 16; i++) CMSDK_gpio_SetIntRisingEdge(CMSDK_GPIO0, i); //set all pins to rising edge interrupts
+
+ for(i = 0; i < 16; i++){
+
+ CMSDK_gpio_SetIntEnable(CMSDK_GPIO0, i); //enable interrupts on specified pin then set data out to 1
+ //for pin 0 then repeat for all subsequent pins whilst still
+
+ if(!((CMSDK_GPIO0->INTENSET) & (1 << i))) err_code = (1 <<(2*i));//check to see if the interrupt enable register is
+ //set for the pin which it should have just been
+ N = i;
+
+ CMSDK_GPIO0->DATAOUT = (0x0001 << i) | CMSDK_GPIO0->DATA; //keeping all other pins high 0000->0001->0011->0111->1111
+
+ CMSDK_gpio_ClrIntEnable(CMSDK_GPIO0, i); //clear interrupt enable for specified pin
+
+ if((CMSDK_GPIO0->INTENSET) & ~(1 << i)) err_code = (1 <<(2*i + 1));//check to see if the interrupt enable register is
+ //clear for the pin which it should have just been
+
+ /* check to see whether intstatus, for the specified pin, is 1, which corresponds to a rising edge interrupt */
+
+ if(intstatus[i] == 1) irq_counter++;
+ else err_code |= (1 << i);
+ }
+
+ if((irq_counter == 16) && (err_code == 0)) puts("Rising Edge IRQ Tests Passed Successfully\n");
+ else{
+ printf("\nRising Edge IRQ Tests Failed, Error Code: (0x%x\n", err_code);
+ err_code = 0; /*if the port did not have 1 RE IRQ for each pin as expected then display error*/
+ return_val = 16;
+ }
+
+ puts("- Stage 3c - GPIO Falling Edge IRQ Test\n");
+
+ irq_counter = 0;
+
+ CMSDK_GPIO0->DATAOUT = 0xFFFF;
+
+ for(i = 0; i < 16; i++) CMSDK_gpio_SetIntFallingEdge(CMSDK_GPIO0, i); //set all pins to falling edge interrupts
+
+ for(i = 0; i < 16; i++){
+
+ /* Counter change from 0->1->2 ...15 */
+
+ CMSDK_gpio_SetIntEnable(CMSDK_GPIO0, i); //enable interrupts on specified pin then set data out to
+ //0xFFFF and shiftright to cause a falling edge on
+ //pin 15 and then shift each time to cause a falling
+ // edge on pins 14 -> 0 1111 >> 0111 >> 0011 >> 0001 >> 0000
+
+ if(!((CMSDK_GPIO0->INTENSET) & (1 << i))) //check to see if the interrupt enable register is
+ err_code = (1 << 2*i); //set for the pin which it should have just been
+
+ N = i;
+
+ CMSDK_GPIO0->DATAOUT = (CMSDK_GPIO0->DATA & ~(1 << i));
+
+ CMSDK_gpio_ClrIntEnable(CMSDK_GPIO0, i); //disable interrupts on specified pin
+
+ if((CMSDK_GPIO0->INTENSET) & ~(1 << i)) //check to see if the interrupt enable register is
+ err_code = (1 << (2*i + 1)); //clear for the pin which it should have just been
+
+ /* check to see whether intstatus, for the specified pin, is 3, which corresponds to a falling edge interrupt */
+
+ if(intstatus[i] == 3) irq_counter++;
+ else err_code |= (1 << i);
+ }
+
+ if((irq_counter == 16) && (err_code == 0)) puts("Falling Edge IRQ Tests Passed Successfully\n");
+ else{
+ printf("\nFalling Edge IRQ Tests Failed, Error Code: (0x%x)\n", err_code);
+ err_code = 0; /*if the port did not have 1 FE IRQ for each pin as expected then display error*/
+ return_val = 32;
+ }
+
+ puts("- Stage 3d - GPIO Low Level IRQ Test\n");
+
+ irq_counter = 0;
+ data = 0xFFFE;
+
+ CMSDK_GPIO0->DATAOUT = 0xFFFF; //set dataout to all ones ready to test low level interrupts
+
+ for(i = 0; i < 16; i++) CMSDK_gpio_SetIntLowLevel(CMSDK_GPIO0, i); //set all pins to low level interrupts
+
+ for(i = 0; i < 16; i++){
+
+ CMSDK_gpio_SetIntEnable(CMSDK_GPIO0, i); //enable interrupts on specified pin and set the
+ //data output to 0xFFFF XOR with 1 shifted to the
+ if(!((CMSDK_GPIO0->INTENSET) & (1 << i))) err_code = (1 << (2*i)); //pins position so that just the desired pin is
+ //set to 0 1111 -> 1110 -> 1101 -> 1011 -> 1111
+ N = i;
+
+ CMSDK_GPIO0->DATAOUT = (0x0001 << i) ^ 0xFFFF;
+
+ CMSDK_gpio_ClrIntEnable(CMSDK_GPIO0, i); //disable interrupts on specified pin
+
+ if((CMSDK_GPIO0->INTENSET) & ~(1 << i)) //check to see if the interrupt enable register is
+ err_code = (1 << (2*i + 1)); //clear for the pin which it should have just been
+
+ /* check to see whether intstatus, for the specified pin, is 4, which corresponds to a low level interrupt */
+
+ if(intstatus[i] == 4) irq_counter++;
+ else err_code |= (1 << i);
+ }
+
+ if((irq_counter == 16) && (err_code == 0)) puts("Low Level IRQ Tests Passed Successfully\n");
+ else{
+ printf("\nLow Level IRQ Tests Failed, Error Code: (0x%x)\n\n", err_code);
+ /*if the port did not have 1 LL IRQ for each pin as expected then display error*/
+ return_val = 64;
+ }
+
+ irq_counter = 0;
+
+ NVIC_DisableIRQ(PORT0_ALL_IRQn); //disable all GPIO interrupts on PORT 0
+
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn); //clear any outstanding GPIO interrupts
+
+ for(i = 0; i < 16; i++) CMSDK_gpio_IntClear(CMSDK_GPIO0, i); //clear any outstanding GPIO interrupts
+
+ return return_val;
+}
+
+/* GPIO_Mask_OP - This function tests the CMSDK GPIO Masked Accesses driver functions
+ - Normal test of all 16 pins
+ - Firstly the data output is set to 0x0000 so as to ensure all comparisons are evaluated correctly
+ - write 0xFFFF using masked access with the mask transitioning through the combinations
+ 0001->0010->0100->1000
+ - evaluate whether the data outputted are correct i.e. is same as 0xFFFF and mask
+ - if not amend err_code else test passed
+ - clear the current array element corresponding to the mask else the data on the output port will accumulate
+ i.e. mask of 0x0001 and mask of 0x0002 will give a mask of 0x0003.
+
+ - Test of 16 random combinations
+ - seed the random function with the #define RANDOM_NUMBER
+ - use rand to get a number between 0 and 65535
+ - perform masked access using the value 0xFFFF and the random number as the mask
+ - evaluate whether the data outputted is correct i.e. is same as 0xFFFF and random mask
+ - if not amend err_code else test passed
+ - clear the current array element corresponding to the mask else the data on the output port will accumulate
+ i.e. mask of 0x0001 and mask of 0x0002 will give a mask of 0x0003.
+
+ - Test accumulation of masks
+ - write 0xFFFF using masked access with the mask transitioning through the combinations
+ 0001->0010->0100->1000 but do not clear after evaluating so that the masked values accumulate
+ - evaluate whether the data outputted is correct i.e. is same as 0xFFFF and the accumulated mask
+ - if not amend err_code else test passed
+
+ - Test accumulation of random masks and random values
+ - gather both a random value and random mask using the rand function
+ - store the random mask so that it can be cleared later
+ - write value using masked access
+ - amend expected value to be seen when the GPIO is read back condition gained from verilog RTL
+ ((DATA[15:8] & mask[9:2])|(existing_data[15:8] & ~mask[9:2]));
+ - repeat with a second random value and mask after the test has been evaluated
+ clear the output port for the previous masks and reset both the previous masks and the expected value
+ - repeat process again until it has occurred 8 times
+*/
+
+int GPIO_Mask_OP(void)
+{
+ int err_code = 0, err_code_all = 0;
+ uint32_t i = 0, random_mask = 0, exp_value = 0, random_value, prev_masks[2] = { 0 }, mask = 0;
+
+
+ CMSDK_gpio_SetOutEnable(CMSDK_GPIO0, 0xFFFF);
+
+ CMSDK_GPIO0->DATAOUT = 0x0000;
+
+ puts("Stage 4 - GPIO Masked Output Test\n");
+
+ puts("- Stage 4a - GPIO Masked Output - Deterministic Test\n");
+
+ for(i = 0; i < 16; i++){
+
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0xFFFF, (1 << i)); //test each pin on the GPIO to check that masked
+ small_delay(); //access works for each pin individually
+ if(CMSDK_GPIO0->DATA != (0xFFFF & (1 << i)))
+ err_code |= (1 << i);
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0x0000, (1 << i)); //clear value back to zero
+ small_delay();
+ }
+
+ CMSDK_GPIO0->DATAOUT = 0;
+
+ for(i = 0; i < 16; i++){
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0xFFFF, (1 << i)); //test each pin on the GPIO to check that masked
+ small_delay(); //access works for each pin individually
+ mask |= (1 << i);
+ if(CMSDK_GPIO0->DATA != (0xFFFF & mask)) //test do not reset to ensure that the masked output
+ err_code |= (1 << (i + 16)); //goes through the transition 0001->0011->0111->1111
+ small_delay();
+ }
+
+ if(!err_code) puts("Stage 4a Deterministic Masked Output Tests Passed Successfully\n");
+ else {
+ printf("\nStage 4a Deterministic Masked Output Tests Failed, Error Code: (0x%x)\n", err_code);
+ err_code_all |= 1;
+ }
+
+ puts("- Stage 4b - GPIO Masked Output - Random Test\n");
+
+ err_code = 0;
+
+ CMSDK_GPIO0->DATAOUT = 0;
+
+ srand(RANDOM_NUMBER);
+
+ for(i = 0; i < 16; i++){ //repeat same process but with 16 random mask
+ random_mask = (rand() % 65536); //values, the random function is seeded with a
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0xFFFF, random_mask); //#define at the top of the program called RANDOM_NUMBER
+ if(CMSDK_GPIO0->DATA != (0xFFFF & random_mask)) //can be easily changed to perform tests on 16
+ err_code |= (1 << i); // more different random numbers
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0x0000, random_mask);
+ }
+
+ CMSDK_GPIO0->DATAOUT = 0;
+
+ mask = 0;
+
+ for(i = 0; i < 16; i++){
+ //repeat same process but with 16 random mask values,
+ random_mask = (rand() % 65536); //which are only cleared every other iteration so that
+ random_value = (rand() % 65536); //they accumulate, the first value is outputted using
+ //masked access and then not cleared then a second value
+ if(prev_masks[0] == 0) prev_masks[0] = random_mask; //is outputted using another mask and then the resulting
+ else prev_masks[1] = random_mask; //output is then checked against the expected output
+
+ exp_value = ((random_mask & random_value) | (exp_value & ~random_mask));
+
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, random_value, random_mask);
+
+ if(CMSDK_GPIO0->DATA != exp_value)
+ err_code |= (1 << (i + 16));
+
+ /* For every two non-zero mask writes taken place,
+ reset the data using the stored mask value and
+ clear the exp_value back to 0 */
+ if((prev_masks[0] != 0) && (prev_masks[1] != 0)){
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0x0000, prev_masks[0]);
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0x0000, prev_masks[1]);
+ prev_masks[0] = 0;
+ prev_masks[1] = 0;
+ exp_value = 0;
+ }
+ }
+
+ if(!err_code) puts("Stage 4b Random Masked Output Tests Passed Successfully\n");
+ else {
+ printf("\nStage 4b Random Masked Output Tests Failed, Error Code: (0x%x)\n", err_code);
+ err_code_all |= 2;
+ }
+
+
+ if(!err_code_all) puts("\nAll Masked Output Tests Passed Successfully\n");
+
+ if(!err_code_all) return 0;
+ else return 4;
+}
+
+//PORT 0 ISR - sets what type of interrupt it is according to the int polarity and type and
+//if the result when checked is the one expected then function will pass the test or fail it, if it's not
+//0 = undefined, 1 = rising edge, 2 = high level, 3 = falling edge, 4 = low level
+
+void PORT0_COMB_Handler(void)
+{
+
+ if((CMSDK_GPIO0->INTPOLSET)){
+ if((CMSDK_GPIO0->INTTYPESET)){
+ if(CMSDK_GPIO0->DATA == ( data |= (1 << N) ))
+ intstatus[N] = 1; /*rising edge*/
+ }else{
+ if(CMSDK_GPIO0->DATA == (1 << N)){
+ intstatus[N] = 2; /*high level*/
+ CMSDK_GPIO0->DATAOUT = 0x0000;
+ }
+ }
+ }else{
+ if((CMSDK_GPIO0->INTTYPESET)){
+ if(CMSDK_GPIO0->DATA == (data &= ~(1 << N))) intstatus[N] = 3; /*falling edge*/
+ }else{
+ if(CMSDK_GPIO0->DATA == 0xFFFF ^ (1 << N)){
+ intstatus[N] = 4; /*low level*/
+ CMSDK_GPIO0->DATAOUT = 0xFFFF;
+ }
+ }
+ }
+ CMSDK_gpio_IntClear(CMSDK_GPIO0, N);
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/gpio_tests.c b/Cortex-M0/nanosoc/software/common/validation/gpio_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..ef3c48a8e57a449300e0badbd0fb8c5338098d0c
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/gpio_tests.c
@@ -0,0 +1,2004 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A test to check the functionality of the AHB GPIO.
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#define GPIO1_ALTERNATE_FUNC_MASK 0x002A /* Implemented bits */
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#define GPIO1_ALTERNATE_FUNC_MASK 0x002A /* Implemented bits */
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#define GPIO1_ALTERNATE_FUNC_MASK 0xF82A /* Implemented bits */
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#define GPIO1_ALTERNATE_FUNC_MASK 0xF82A /* Implemented bits */
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+/* Alternate function control register mask */
+ /* Implemented bits */
+#define GPIO0_ALTERNATE_FUNC_MASK 0x0000
+ /* Default value */
+#define GPIO0_ALTERNATE_FUNC_DEFAULT 0x0000
+
+ /* Default value */
+#define GPIO1_ALTERNATE_FUNC_DEFAULT 0x0000
+
+/* Macros for word, half word and byte */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+/* A trick to add a small delay in program */
+/* small_delay() is the same as __ISB() */
+#define small_delay __ISB
+
+/* peripheral and component ID values */
+#define AHB_GPIO_PID4 0x04
+#define AHB_GPIO_PID5 0x00
+#define AHB_GPIO_PID6 0x00
+#define AHB_GPIO_PID7 0x00
+#define AHB_GPIO_PID0 0x20
+#define AHB_GPIO_PID1 0xB8
+#define AHB_GPIO_PID2 0x1B
+#define AHB_GPIO_PID3 0x00
+#define AHB_GPIO_CID0 0x0D
+#define AHB_GPIO_CID1 0xF0
+#define AHB_GPIO_CID2 0x05
+#define AHB_GPIO_CID3 0xB1
+
+
+/* Declare test functions */
+int gpio_register_rw_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO);
+int gpio_interrupt_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO);
+int gpio_masked_access_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO);
+int gpio_unused_addresses_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO);
+void medium_delay(void);
+int gpio0_id_check(void);
+int gpio1_id_check(void);
+
+/* Global variables */
+volatile int gpio0_irq_occurred;
+volatile int gpio1_irq_occurred;
+volatile int gpio0_irq_expected;
+volatile int gpio1_irq_expected;
+volatile int gpio0_irq_level_irq; // indicate it is a level IRQ test
+ // Need to toggle interrupt source
+volatile int gpio1_irq_level_irq; // indicate it is a level IRQ test
+ // Need to toggle interrupt source
+volatile int multi_irq_test; // indicate continuous level trigger IRQ test
+
+volatile int counter;
+volatile char gpio0_irq_flags[16];
+
+int main (void)
+{
+ int result=0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("Cortex Microcontroller System Design Kit - GPIO Test - revision $Revision: 371321 $\n");
+
+ gpio0_irq_occurred = 0;
+ gpio1_irq_occurred = 0;
+ gpio0_irq_expected = 0;
+ gpio1_irq_expected = 0;
+
+ puts("1) GPIO 0");
+
+ if (gpio0_id_check()==0) {
+ /* GPIO 0 present */
+ result += gpio_register_rw_test(CMSDK_GPIO0);
+ result += gpio_interrupt_test(CMSDK_GPIO0);
+ result += gpio_masked_access_test(CMSDK_GPIO0);
+ result += gpio_unused_addresses_test(CMSDK_GPIO0);
+ } else {
+ puts ("- GPIO #0 not present. Tests skipped.");
+ }
+
+ puts("\n2) GPIO 1");
+
+ if (gpio1_id_check()==0) {
+ /* GPIO 1 present */
+ result += gpio_register_rw_test(CMSDK_GPIO1);
+ result += gpio_interrupt_test(CMSDK_GPIO1);
+ result += gpio_masked_access_test(CMSDK_GPIO1);
+ result += gpio_unused_addresses_test(CMSDK_GPIO1);
+ } else {
+ puts ("- GPIO #1 not present. Tests skipped.");
+ }
+
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+int gpio0_id_check(void)
+{
+unsigned char gpio_id;
+
+ gpio_id = HW8_REG(CMSDK_GPIO0_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_GPIO0_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO0_BASE + 0xFE4) != 0xB8) ||
+ (gpio_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+int gpio1_id_check(void)
+{
+unsigned char gpio_id;
+
+ gpio_id = HW8_REG(CMSDK_GPIO1_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_GPIO1_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO1_BASE + 0xFE4) != 0xB8) ||
+ (gpio_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+
+void medium_delay(void)
+{
+ int i;
+ for (i=0;i<3;i++){
+ small_delay();
+ }
+ return;
+}
+/* --------------------------------------------------------------- */
+/* GPIO masked access tests */
+/* --------------------------------------------------------------- */
+int gpio_masked_access_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO){
+ int return_val=0;
+ unsigned int err_code=0;
+ int i;
+
+ unsigned int gpio_datamask; /* Data compare mask */
+ unsigned int gpio_byte_base; /* Base address of GPIO masked access*/
+ unsigned int current_value; /* */
+ unsigned int read_value; /* */
+ unsigned int expected_value; /* */
+ unsigned int write_value;
+ int test_counter = 0;
+ int ul_err = 0;
+
+
+ puts("GPIO mask access test");
+ puts("- lower byte");
+
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio_datamask = 0xFFFFFFFF;
+ gpio_byte_base = CMSDK_GPIO0_BASE + 0x400;
+ }
+ else if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio_datamask = ~((1<<5)|(1<<4)|(1<<2)|(1<<0)); /* Bits that cannot be tested */
+ gpio_byte_base = CMSDK_GPIO1_BASE + 0x400;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'gpio_masked_access_test'.");
+ return 1;
+ }
+
+ CMSDK_GPIO->INTENCLR = 0xFFFF;
+ CMSDK_GPIO->OUTENABLESET = gpio_datamask;
+ CMSDK_GPIO->DATAOUT = 0;
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+ current_value = CMSDK_GPIO->DATA;
+
+ for (i=0;i<256;i++){
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->LB_MASKED[i];
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<0);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<1);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<2);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<3);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<4);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<5);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 3);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<6);}
+
+ /* Use masked access to toggle current value, check it with word access */
+ write_value = ~CMSDK_GPIO->LB_MASKED[i];
+ CMSDK_GPIO->LB_MASKED[i] = write_value;
+ current_value = (current_value & (~i)) | (write_value & i);
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->LB_MASKED[i];
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<7);}
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<8);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<9);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<10);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<11);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<12);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<13);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 3);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<14);}
+
+ /* Use half word masked access to toggle current value, check it with word access */
+ write_value = ~CMSDK_GPIO->LB_MASKED[i];
+ HW16_REG(gpio_byte_base + 4 * i) = write_value;
+ current_value = (current_value & (~i)) | (write_value & i);
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->LB_MASKED[i];
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<15);}
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<16);}
+
+ /* Use half word access to write to upper 16-bit, should have no change in result */
+ write_value = ~CMSDK_GPIO->LB_MASKED[i];
+ HW16_REG(gpio_byte_base + 4 * i + 2) = write_value;
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<17);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<18);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<19);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<20);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<21);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<22);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 3);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<23);}
+
+ /* Use byte masked access to toggle current value, check it with word access */
+ write_value = ~CMSDK_GPIO->LB_MASKED[i];
+ HW8_REG(gpio_byte_base + 4 * i) = write_value;
+ current_value = (current_value & (~i)) | (write_value & i);
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<24);}
+
+ /* Write to second byte, should have no effect */
+ write_value = ~CMSDK_GPIO->LB_MASKED[i];
+ HW8_REG(gpio_byte_base + 4 * i + 1) = write_value;
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<25);}
+
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->LB_MASKED[i];
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<26);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<27);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<28);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<29);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<30);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= 0x80000000UL;}
+
+ if (err_code != 0) {
+ printf ("ERROR : LB masked access failed (0x%x) at mask = %d\n", err_code, i);
+ return_val =1;
+ err_code = 0;
+ }else test_counter++;
+ }
+
+ if(test_counter == 256){
+ puts("Lower Byte Mask Access Tests Passed\n");
+ }
+ else{
+ puts("Lower Byte Mask Access Tests Failed\n");
+ ul_err = 1;
+ }
+
+ test_counter = 0;
+
+ puts("- upper byte");
+ gpio_byte_base = gpio_byte_base + 0x400;
+
+ for (i=0;i<256;i++){
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->UB_MASKED[i];
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<0);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<1);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<2);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<4);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = (current_value>>8) & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<3);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<5);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 3);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<6);}
+
+ /* Use masked access to toggle current value, check it with word access */
+ write_value = ~CMSDK_GPIO->UB_MASKED[i];
+ CMSDK_GPIO->UB_MASKED[i] = write_value;
+ current_value = (current_value & (~(i<<8))) | (write_value & (i<<8));
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->UB_MASKED[i];
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<7);}
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<8);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<9);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<10);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<11);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = (current_value>>8) & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<12);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<13);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 3);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<14);}
+
+ /* Use half word masked access to toggle current value, check it with word access */
+ write_value = ~CMSDK_GPIO->UB_MASKED[i];
+ HW16_REG(gpio_byte_base + 4 * i) = write_value;
+ current_value = (current_value & (~(i<<8))) | (write_value & (i<<8));
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->UB_MASKED[i];
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<15);}
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<16);}
+
+ /* Use half word access to write to upper 16-bit, should have no change in result */
+ write_value = ~HW16_REG(gpio_byte_base + 4 * i + 2);
+ HW16_REG(gpio_byte_base + 4 * i + 2) = write_value;
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<17);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<18);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<19);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<20);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = (current_value>>8) & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<21);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<22);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 3);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<23);}
+
+ /* Use byte masked access to toggle current value, check it with word access */
+ write_value = ~CMSDK_GPIO->UB_MASKED[i];
+ HW8_REG(gpio_byte_base + 4 * i + 1) = (write_value>>8) & 0xFF;
+ current_value = (current_value & (~(i<<8))) | (write_value & (i<<8));
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<24);}
+
+ /* Write to lower byte, should have no effect */
+ write_value = ~CMSDK_GPIO->UB_MASKED[i];
+ HW8_REG(gpio_byte_base + 4 * i ) = (write_value) & 0xFF;
+ small_delay(); /* DATA read back take time to get updated due to synchronisation registers*/
+
+ /* Use normal access to read current value */
+ read_value = CMSDK_GPIO->DATA;
+ expected_value = current_value;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<25);}
+
+ /* Use masked access to read current value */
+ read_value = CMSDK_GPIO->UB_MASKED[i];
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<26);}
+
+ /* Use half word read access to carry out mask access */
+ read_value = HW16_REG(gpio_byte_base + 4 * i);
+ expected_value = current_value & (i<<8);
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<27);}
+
+ read_value = HW16_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<28);}
+
+ /* Use byte read access to carry out mask access */
+ read_value = HW8_REG(gpio_byte_base + 4 * i);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (1<<29);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 1);
+ expected_value = (current_value>>8) & i;
+ if ((read_value & gpio_datamask) != (expected_value & gpio_datamask)) { err_code |= (1<<30);}
+
+ read_value = HW8_REG(gpio_byte_base + 4 * i + 2);
+ expected_value = 0;
+ if ((read_value ) != (expected_value )) { err_code |= (0x80000000UL);}
+
+
+
+ if (err_code != 0) {
+ printf ("ERROR : UB masked access failed (0x%x) at mask = %d\n", err_code, i);
+ return_val =1;
+ err_code = 0;
+ UartEndSimulation();
+ }
+ else test_counter++;
+ }
+
+ if(test_counter == 256){
+ puts("Upper Byte Mask Access Tests Passed\n");
+ }
+ else{
+ puts("Upper Byte Mask Access Tests Failed\n");
+ ul_err |= 2;
+ }
+
+ if(ul_err) printf("Mask Access Tests Failed, Error Code: (0x%x)\n", ul_err);
+ else puts("Mask Access Tests Passed\n");
+
+ /* Clean up */
+ CMSDK_GPIO->OUTENABLECLR = 0xFFFFFFFF;
+ CMSDK_GPIO->DATAOUT = 0;
+
+ return(return_val);
+}
+
+
+
+/* --------------------------------------------------------------- */
+/* GPIO register read/write tests */
+/* --------------------------------------------------------------- */
+
+int gpio_register_rw_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO){
+ int return_val=0;
+ unsigned int err_code=0;
+ int i;
+ int test_individual_irq = 1; /* Test individual IRQ in GPIO #0 by default */
+
+ unsigned int gpio_datamask; /* Data compare mask */
+ unsigned int gpio_outen_mask; /* Output enable mask */
+ unsigned int gpio_altfunc_initval;
+ unsigned int gpio_altfunc_mask;
+ unsigned int gpio_altfunc_usedmask;
+ unsigned int gpio_base;
+ unsigned int saved_altfunc;
+
+
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ saved_altfunc = CMSDK_GPIO0->ALTFUNCSET; /* Keep a copy of current ALTFUNC */
+ /* GPIO #0 is not shared in example system */
+ gpio_datamask = 0xFFFFFFFF;
+ gpio_outen_mask = 0xFFFFFFFF;
+ gpio_altfunc_mask = GPIO0_ALTERNATE_FUNC_MASK; /* Mask bits that are not implemented */
+ gpio_altfunc_initval = GPIO0_ALTERNATE_FUNC_DEFAULT;
+ gpio_altfunc_usedmask = 0xFFFFFFFF;
+ gpio_base = CMSDK_GPIO0_BASE;
+ }
+ else if (CMSDK_GPIO==CMSDK_GPIO1) {
+ saved_altfunc = CMSDK_GPIO1->ALTFUNCSET; /* Keep a copy of current ALTFUNC */
+ /* GPIO #1 is shared with peripherals in example system */
+ /* bit 5 is used by stdout */
+ gpio_datamask = ~((1<<5)|(1<<2)|(1<<0)); /* Ignore return values for these bits */
+ gpio_outen_mask = ~((1<<2)|(1<<0)); /* Do not set output enable for these bits */
+ gpio_altfunc_mask = GPIO1_ALTERNATE_FUNC_MASK; /* Mask bits that are not implemented */
+ gpio_altfunc_initval = GPIO1_ALTERNATE_FUNC_DEFAULT;
+ gpio_altfunc_usedmask = ~(1<<5); /* This bit is use by stdout */
+ gpio_base = CMSDK_GPIO1_BASE;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'gpio_register_rw_test'.");
+ return 1;
+ }
+
+ puts("GPIO R/W test");
+ puts("- initial values");
+
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ NVIC_DisableIRQ(PORT1_ALL_IRQn);
+ for (i=0;i<16;i++){
+ NVIC_DisableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + i)));
+ }
+
+ /* Test initial values. */
+ /* Current data value could be affected by external signal */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ /* By default GPIO #0 signals are pulled up */
+ if (CMSDK_GPIO->DATA != 0x0000FFFF) {err_code |= (1<<0); }
+ }
+
+ if (CMSDK_GPIO->DATAOUT != 0x00000000) {err_code |= (1<<1); }
+ if (CMSDK_GPIO->OUTENABLESET != 0x00000000) {err_code |= (1<<2); }
+
+ /* Alternate function initial value can be affected by
+ 1) Verilog parameter
+ 2) Retargeting initialization code */
+ /* GPIO #1 is shared with peripherals in example system */
+ /* bit 5 is used by stdout */
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_usedmask) != (gpio_altfunc_initval & gpio_altfunc_usedmask))
+ {err_code |= (1<<3); }
+
+ if (CMSDK_GPIO->INTENSET != 0x00000000) {err_code |= (1<<4); }
+ if (CMSDK_GPIO->INTTYPESET != 0x00000000) {err_code |= (1<<5); }
+ if (CMSDK_GPIO->INTPOLSET != 0x00000000) {err_code |= (1<<6); }
+ if (CMSDK_GPIO->INTSTATUS != 0x00000000) {err_code |= (1<<7); }
+ puts ("- check ID values (WORD accesses)");
+ if (HW32_REG(gpio_base + 0xFD0) != AHB_GPIO_PID4) {err_code |= (1<<8); }
+ if (HW32_REG(gpio_base + 0xFD4) != AHB_GPIO_PID5) {err_code |= (1<<9); }
+ if (HW32_REG(gpio_base + 0xFD8) != AHB_GPIO_PID6) {err_code |= (1<<10); }
+ if (HW32_REG(gpio_base + 0xFDC) != AHB_GPIO_PID7) {err_code |= (1<<11); }
+ if (HW32_REG(gpio_base + 0xFE0) != AHB_GPIO_PID0) {err_code |= (1<<12); }
+ if (HW32_REG(gpio_base + 0xFE4) != AHB_GPIO_PID1) {err_code |= (1<<13); }
+ if (HW32_REG(gpio_base + 0xFE8) != AHB_GPIO_PID2) {err_code |= (1<<14); }
+ if (HW32_REG(gpio_base + 0xFEC) != AHB_GPIO_PID3) {err_code |= (1<<15); }
+ if (HW32_REG(gpio_base + 0xFF0) != AHB_GPIO_CID0) {err_code |= (1<<16); }
+ if (HW32_REG(gpio_base + 0xFF4) != AHB_GPIO_CID1) {err_code |= (1<<17); }
+ if (HW32_REG(gpio_base + 0xFF8) != AHB_GPIO_CID2) {err_code |= (1<<18); }
+ if (HW32_REG(gpio_base + 0xFFC) != AHB_GPIO_CID3) {err_code |= (1<<19); }
+
+ /* test write to PIDs and CIDs - should be ignored */
+ for (i=0; i <12; i++) {
+ HW8_REG(gpio_base + 0xFD0 + (i<<2)) = ~HW32_REG(gpio_base + 0xFD0 + (i<<2));
+ }
+
+ /* Check read back values again, should not be changed */
+ if (HW16_REG(gpio_base + 0xFD0) != AHB_GPIO_PID4) {err_code |= (1<<8); }
+ if (HW16_REG(gpio_base + 0xFD4) != AHB_GPIO_PID5) {err_code |= (1<<9); }
+ if (HW16_REG(gpio_base + 0xFD8) != AHB_GPIO_PID6) {err_code |= (1<<10); }
+ if (HW16_REG(gpio_base + 0xFDC) != AHB_GPIO_PID7) {err_code |= (1<<11); }
+ if (HW16_REG(gpio_base + 0xFE0) != AHB_GPIO_PID0) {err_code |= (1<<12); }
+ if (HW16_REG(gpio_base + 0xFE4) != AHB_GPIO_PID1) {err_code |= (1<<13); }
+ if (HW16_REG(gpio_base + 0xFE8) != AHB_GPIO_PID2) {err_code |= (1<<14); }
+ if (HW16_REG(gpio_base + 0xFEC) != AHB_GPIO_PID3) {err_code |= (1<<15); }
+ if (HW16_REG(gpio_base + 0xFF0) != AHB_GPIO_CID0) {err_code |= (1<<16); }
+ if (HW16_REG(gpio_base + 0xFF4) != AHB_GPIO_CID1) {err_code |= (1<<17); }
+ if (HW16_REG(gpio_base + 0xFF8) != AHB_GPIO_CID2) {err_code |= (1<<18); }
+ if (HW16_REG(gpio_base + 0xFFC) != AHB_GPIO_CID3) {err_code |= (1<<19); }
+
+ if (err_code != 0) {
+ printf ("ERROR : initial value failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+
+ puts ("- write ID values (HALF WORD accesses, lower) - should have no effect");
+ HW16_REG(gpio_base + 0xFD0) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFD4) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFD8) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFDC) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFE0) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFE4) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFE8) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFEC) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFF0) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFF4) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFF8) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFFC) = 0xFFFF;
+
+
+ puts ("- check ID values (HALF WORD accesses, lower)");
+ if (HW16_REG(gpio_base + 0xFD0) != AHB_GPIO_PID4) {err_code |= (1<<0); }
+ if (HW16_REG(gpio_base + 0xFD4) != AHB_GPIO_PID5) {err_code |= (1<<1); }
+ if (HW16_REG(gpio_base + 0xFD8) != AHB_GPIO_PID6) {err_code |= (1<<2); }
+ if (HW16_REG(gpio_base + 0xFDC) != AHB_GPIO_PID7) {err_code |= (1<<3); }
+ if (HW16_REG(gpio_base + 0xFE0) != AHB_GPIO_PID0) {err_code |= (1<<4); }
+ if (HW16_REG(gpio_base + 0xFE4) != AHB_GPIO_PID1) {err_code |= (1<<5); }
+ if (HW16_REG(gpio_base + 0xFE8) != AHB_GPIO_PID2) {err_code |= (1<<6); }
+ if (HW16_REG(gpio_base + 0xFEC) != AHB_GPIO_PID3) {err_code |= (1<<7); }
+ if (HW16_REG(gpio_base + 0xFF0) != AHB_GPIO_CID0) {err_code |= (1<<8); }
+ if (HW16_REG(gpio_base + 0xFF4) != AHB_GPIO_CID1) {err_code |= (1<<9); }
+ if (HW16_REG(gpio_base + 0xFF8) != AHB_GPIO_CID2) {err_code |= (1<<10); }
+ if (HW16_REG(gpio_base + 0xFFC) != AHB_GPIO_CID3) {err_code |= (1<<11); }
+
+
+ puts ("- write ID values (HALF WORD accesses, upper) - should have no effect");
+ HW16_REG(gpio_base + 0xFD2) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFD6) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFDA) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFDE) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFE2) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFE6) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFEA) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFEE) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFF2) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFF6) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFFA) = 0xFFFF;
+ HW16_REG(gpio_base + 0xFFE) = 0xFFFF;
+
+ puts ("- check ID values (HALF WORD accesses, upper)");
+ if (HW16_REG(gpio_base + 0xFD2) != 0x00) {err_code |= (1<<12); }
+ if (HW16_REG(gpio_base + 0xFD6) != 0x00) {err_code |= (1<<13); }
+ if (HW16_REG(gpio_base + 0xFDA) != 0x00) {err_code |= (1<<14); }
+ if (HW16_REG(gpio_base + 0xFDE) != 0x00) {err_code |= (1<<15); }
+ if (HW16_REG(gpio_base + 0xFE2) != 0x00) {err_code |= (1<<16); }
+ if (HW16_REG(gpio_base + 0xFE6) != 0x00) {err_code |= (1<<17); }
+ if (HW16_REG(gpio_base + 0xFEA) != 0x00) {err_code |= (1<<18); }
+ if (HW16_REG(gpio_base + 0xFEE) != 0x00) {err_code |= (1<<19); }
+ if (HW16_REG(gpio_base + 0xFF2) != 0x00) {err_code |= (1<<20); }
+ if (HW16_REG(gpio_base + 0xFF6) != 0x00) {err_code |= (1<<21); }
+ if (HW16_REG(gpio_base + 0xFFA) != 0x00) {err_code |= (1<<22); }
+ if (HW16_REG(gpio_base + 0xFFE) != 0x00) {err_code |= (1<<23); }
+
+ if (err_code != 0) {
+ printf ("ERROR : initial value failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ puts ("- write ID values (BYTE accesses, byte 0) - should have no effect");
+ HW8_REG(gpio_base + 0xFD0) = 0xFF;
+ HW8_REG(gpio_base + 0xFD4) = 0xFF;
+ HW8_REG(gpio_base + 0xFD8) = 0xFF;
+ HW8_REG(gpio_base + 0xFDC) = 0xFF;
+ HW8_REG(gpio_base + 0xFE0) = 0xFF;
+ HW8_REG(gpio_base + 0xFE4) = 0xFF;
+ HW8_REG(gpio_base + 0xFE8) = 0xFF;
+ HW8_REG(gpio_base + 0xFEC) = 0xFF;
+ HW8_REG(gpio_base + 0xFF0) = 0xFF;
+ HW8_REG(gpio_base + 0xFF4) = 0xFF;
+ HW8_REG(gpio_base + 0xFF8) = 0xFF;
+ HW8_REG(gpio_base + 0xFFC) = 0xFF;
+
+ puts ("- check ID values (BYTE accesses, byte 0)");
+ if (HW8_REG(gpio_base + 0xFD0) != AHB_GPIO_PID4) {err_code |= (1<<0); }
+ if (HW8_REG(gpio_base + 0xFD4) != AHB_GPIO_PID5) {err_code |= (1<<1); }
+ if (HW8_REG(gpio_base + 0xFD8) != AHB_GPIO_PID6) {err_code |= (1<<2); }
+ if (HW8_REG(gpio_base + 0xFDC) != AHB_GPIO_PID7) {err_code |= (1<<3); }
+ if (HW8_REG(gpio_base + 0xFE0) != AHB_GPIO_PID0) {err_code |= (1<<4); }
+ if (HW8_REG(gpio_base + 0xFE4) != AHB_GPIO_PID1) {err_code |= (1<<5); }
+ if (HW8_REG(gpio_base + 0xFE8) != AHB_GPIO_PID2) {err_code |= (1<<6); }
+ if (HW8_REG(gpio_base + 0xFEC) != AHB_GPIO_PID3) {err_code |= (1<<7); }
+ if (HW8_REG(gpio_base + 0xFF0) != AHB_GPIO_CID0) {err_code |= (1<<8); }
+ if (HW8_REG(gpio_base + 0xFF4) != AHB_GPIO_CID1) {err_code |= (1<<9); }
+ if (HW8_REG(gpio_base + 0xFF8) != AHB_GPIO_CID2) {err_code |= (1<<10); }
+ if (HW8_REG(gpio_base + 0xFFC) != AHB_GPIO_CID3) {err_code |= (1<<11); }
+
+ puts ("- write ID values (BYTE accesses, byte 1) - should have no effect");
+ HW8_REG(gpio_base + 0xFD1) = 0xFF;
+ HW8_REG(gpio_base + 0xFD5) = 0xFF;
+ HW8_REG(gpio_base + 0xFD9) = 0xFF;
+ HW8_REG(gpio_base + 0xFDD) = 0xFF;
+ HW8_REG(gpio_base + 0xFE1) = 0xFF;
+ HW8_REG(gpio_base + 0xFE5) = 0xFF;
+ HW8_REG(gpio_base + 0xFE9) = 0xFF;
+ HW8_REG(gpio_base + 0xFED) = 0xFF;
+ HW8_REG(gpio_base + 0xFF1) = 0xFF;
+ HW8_REG(gpio_base + 0xFF5) = 0xFF;
+ HW8_REG(gpio_base + 0xFF9) = 0xFF;
+ HW8_REG(gpio_base + 0xFFD) = 0xFF;
+
+ puts ("- check ID values (BYTE accesses, byte 1)");
+ if (HW8_REG(gpio_base + 0xFD1) != 0x00) {err_code |= (1<<12); }
+ if (HW8_REG(gpio_base + 0xFD5) != 0x00) {err_code |= (1<<13); }
+ if (HW8_REG(gpio_base + 0xFD9) != 0x00) {err_code |= (1<<14); }
+ if (HW8_REG(gpio_base + 0xFDD) != 0x00) {err_code |= (1<<15); }
+ if (HW8_REG(gpio_base + 0xFE1) != 0x00) {err_code |= (1<<16); }
+ if (HW8_REG(gpio_base + 0xFE5) != 0x00) {err_code |= (1<<17); }
+ if (HW8_REG(gpio_base + 0xFE9) != 0x00) {err_code |= (1<<18); }
+ if (HW8_REG(gpio_base + 0xFED) != 0x00) {err_code |= (1<<19); }
+ if (HW8_REG(gpio_base + 0xFF1) != 0x00) {err_code |= (1<<20); }
+ if (HW8_REG(gpio_base + 0xFF5) != 0x00) {err_code |= (1<<21); }
+ if (HW8_REG(gpio_base + 0xFF9) != 0x00) {err_code |= (1<<22); }
+ if (HW8_REG(gpio_base + 0xFFD) != 0x00) {err_code |= (1<<23); }
+
+ if (err_code != 0) {
+ printf ("ERROR : initial value failed on byte 0 and 1 accesses (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ puts ("- write ID values (BYTE accesses, byte 2) - should have no effect");
+ HW8_REG(gpio_base + 0xFD2) = 0xFF;
+ HW8_REG(gpio_base + 0xFD6) = 0xFF;
+ HW8_REG(gpio_base + 0xFDA) = 0xFF;
+ HW8_REG(gpio_base + 0xFDE) = 0xFF;
+ HW8_REG(gpio_base + 0xFE2) = 0xFF;
+ HW8_REG(gpio_base + 0xFE6) = 0xFF;
+ HW8_REG(gpio_base + 0xFEA) = 0xFF;
+ HW8_REG(gpio_base + 0xFEE) = 0xFF;
+ HW8_REG(gpio_base + 0xFF2) = 0xFF;
+ HW8_REG(gpio_base + 0xFF6) = 0xFF;
+ HW8_REG(gpio_base + 0xFFA) = 0xFF;
+ HW8_REG(gpio_base + 0xFFE) = 0xFF;
+
+ puts ("- check ID values (BYTE accesses, byte 2)");
+ if (HW8_REG(gpio_base + 0xFD2) != 0x00) {err_code |= (1<<0); }
+ if (HW8_REG(gpio_base + 0xFD6) != 0x00) {err_code |= (1<<1); }
+ if (HW8_REG(gpio_base + 0xFDA) != 0x00) {err_code |= (1<<2); }
+ if (HW8_REG(gpio_base + 0xFDE) != 0x00) {err_code |= (1<<3); }
+ if (HW8_REG(gpio_base + 0xFE2) != 0x00) {err_code |= (1<<4); }
+ if (HW8_REG(gpio_base + 0xFE6) != 0x00) {err_code |= (1<<5); }
+ if (HW8_REG(gpio_base + 0xFEA) != 0x00) {err_code |= (1<<6); }
+ if (HW8_REG(gpio_base + 0xFEE) != 0x00) {err_code |= (1<<7); }
+ if (HW8_REG(gpio_base + 0xFF2) != 0x00) {err_code |= (1<<8); }
+ if (HW8_REG(gpio_base + 0xFF6) != 0x00) {err_code |= (1<<9); }
+ if (HW8_REG(gpio_base + 0xFFA) != 0x00) {err_code |= (1<<10); }
+ if (HW8_REG(gpio_base + 0xFFE) != 0x00) {err_code |= (1<<11); }
+
+ puts ("- write ID values (BYTE accesses, byte 3) - should have no effect");
+ /* test write to PIDs and CIDs - should be ignored */
+ HW8_REG(gpio_base + 0xFD3) = 0xFF;
+ HW8_REG(gpio_base + 0xFD7) = 0xFF;
+ HW8_REG(gpio_base + 0xFDB) = 0xFF;
+ HW8_REG(gpio_base + 0xFDF) = 0xFF;
+ HW8_REG(gpio_base + 0xFE3) = 0xFF;
+ HW8_REG(gpio_base + 0xFE7) = 0xFF;
+ HW8_REG(gpio_base + 0xFEB) = 0xFF;
+ HW8_REG(gpio_base + 0xFEF) = 0xFF;
+ HW8_REG(gpio_base + 0xFF3) = 0xFF;
+ HW8_REG(gpio_base + 0xFF7) = 0xFF;
+ HW8_REG(gpio_base + 0xFFB) = 0xFF;
+ HW8_REG(gpio_base + 0xFFF) = 0xFF;
+
+ puts ("- check ID values (BYTE accesses, byte 3)");
+ if (HW8_REG(gpio_base + 0xFD3) != 0x00) {err_code |= (1<<12); }
+ if (HW8_REG(gpio_base + 0xFD7) != 0x00) {err_code |= (1<<13); }
+ if (HW8_REG(gpio_base + 0xFDB) != 0x00) {err_code |= (1<<14); }
+ if (HW8_REG(gpio_base + 0xFDF) != 0x00) {err_code |= (1<<15); }
+ if (HW8_REG(gpio_base + 0xFE3) != 0x00) {err_code |= (1<<16); }
+ if (HW8_REG(gpio_base + 0xFE7) != 0x00) {err_code |= (1<<17); }
+ if (HW8_REG(gpio_base + 0xFEB) != 0x00) {err_code |= (1<<18); }
+ if (HW8_REG(gpio_base + 0xFEF) != 0x00) {err_code |= (1<<19); }
+ if (HW8_REG(gpio_base + 0xFF3) != 0x00) {err_code |= (1<<20); }
+ if (HW8_REG(gpio_base + 0xFF7) != 0x00) {err_code |= (1<<21); }
+ if (HW8_REG(gpio_base + 0xFFB) != 0x00) {err_code |= (1<<22); }
+ if (HW8_REG(gpio_base + 0xFFF) != 0x00) {err_code |= (1<<23); }
+
+ if (err_code != 0) {
+ printf ("ERROR : initial value failed on byte 2 and 3 accesses (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ puts("- read/write");
+
+ /* Test output enable read/write */
+ /* word size */
+ CMSDK_GPIO->OUTENABLESET = 0xFFFFFFFF & gpio_outen_mask;
+ if (CMSDK_GPIO->OUTENABLESET != (0x0000FFFF & gpio_outen_mask)) { err_code |= (1<<0); }
+ CMSDK_GPIO->OUTENABLECLR = 0xCCAA5500 & gpio_outen_mask;
+ if (CMSDK_GPIO->OUTENABLESET != (0x0000AAFF & gpio_outen_mask)) { err_code |= (1<<1); }
+ CMSDK_GPIO->OUTENABLECLR = 0xFFFFFFFF & gpio_outen_mask;
+ if (CMSDK_GPIO->OUTENABLESET != (0x00000000 & gpio_outen_mask)) { err_code |= (1<<2); }
+
+ /* half word size and byte size */
+ HW16_REG(gpio_base + 0x14) = 0xFFFF & gpio_outen_mask;
+ HW16_REG(gpio_base + 0x10) = 0x3366 & gpio_outen_mask;
+ if (CMSDK_GPIO->OUTENABLESET != (0x00003366 & gpio_outen_mask)) { err_code |= (1<<3); }
+
+ HW16_REG(gpio_base + 0x12) = 0x9988 & gpio_outen_mask; /* This transfer is ignored */
+ if (CMSDK_GPIO->OUTENABLESET != (0x00003366 & gpio_outen_mask)) { err_code |= (1<<4); }
+ HW16_REG(gpio_base + 0x14) = 0xFFFF & gpio_outen_mask;
+ HW8_REG( gpio_base + 0x10) = 0x44 & gpio_outen_mask;
+ HW8_REG( gpio_base + 0x11) = 0x33;
+ if (HW16_REG(gpio_base + 0x10) != (0x00003344 & gpio_outen_mask)) { err_code |= (1<<5); }
+ HW16_REG(gpio_base + 0x10) = 0x77EE & gpio_outen_mask;
+ if (HW8_REG( gpio_base + 0x10) != (0x000000EE & gpio_outen_mask)) { err_code |= (1<<6); }
+ if (HW8_REG( gpio_base + 0x11) != (0x00000077 & (gpio_outen_mask>>8))) { err_code |= (1<<7); }
+
+ CMSDK_GPIO->OUTENABLESET = 0x0000FFFF & gpio_outen_mask; /* Set all output enabled */
+ if (CMSDK_GPIO->OUTENABLESET != (0x0000FFFF & gpio_outen_mask)) { err_code |= (1<<8); }
+
+ /* Now we can test read back data */
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0x0000 & gpio_datamask)) {err_code |= (1<<9); }
+ if ((HW16_REG( gpio_base + 0x0) & gpio_datamask) != (0x0000 & gpio_datamask)) {err_code |= (1<<10); }
+
+ /* Test byte size write to data register, which in effect change dataout register */
+ HW8_REG( gpio_base + 0x0) = 0xFF;
+ if (CMSDK_GPIO->DATAOUT != 0x00FF) {err_code |= (1<<11); }
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0x00FF & gpio_datamask)) {err_code |= (1<<12); }
+ HW8_REG( gpio_base + 0x1) = 0xFF;
+ if (CMSDK_GPIO->DATAOUT != 0xFFFF) {err_code |= (1<<13); }
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0xFFFF & gpio_datamask)) {err_code |= (1<<14); }
+ HW8_REG( gpio_base + 0x2) = 0xFF;
+ if (CMSDK_GPIO->DATAOUT != 0xFFFF) {err_code |= (1<<13); }
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0xFFFF & gpio_datamask)) {err_code |= (1<<15); }
+ HW8_REG( gpio_base + 0x3) = 0xFF;
+ if (CMSDK_GPIO->DATAOUT != 0xFFFF) {err_code |= (1<<14); }
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0xFFFF & gpio_datamask)) {err_code |= (1<<16); }
+
+ CMSDK_GPIO->DATAOUT = 0x1234;
+ if (CMSDK_GPIO->DATAOUT != 0x1234) {err_code |= (1<<17); }
+ if (HW8_REG( gpio_base + 0x4) != 0x34) {err_code |= (1<<18); }
+ if (HW8_REG( gpio_base + 0x5) != 0x12) {err_code |= (1<<19); }
+ if (HW16_REG(gpio_base + 0x4) != 0x1234) {err_code |= (1<<20); }
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0x1234 & gpio_datamask)) {err_code |= (1<<21); }
+ if ((HW8_REG( gpio_base + 0x0) & gpio_datamask) != (0x34 & gpio_datamask)) {err_code |= (1<<22); }
+ if ((HW8_REG( gpio_base + 0x1) & (gpio_datamask>>8)) != (0x12 & (gpio_datamask>>8))) {err_code |= (1<<23); }
+ if ( HW8_REG( gpio_base + 0x2) != 0x00) {err_code |= (1<<24); }
+ if ( HW8_REG( gpio_base + 0x3) != 0x00) {err_code |= (1<<25); }
+ if (HW16_REG( gpio_base + 0x6) != 0x0000) {err_code |= (1<<26); }
+
+ HW16_REG( gpio_base + 0x0) = 0xFFFF;
+ if (CMSDK_GPIO->DATAOUT != 0xFFFF) {err_code |= (1<<27); }
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0xFFFF & gpio_datamask)) {err_code |= (1<<28); }
+
+ HW16_REG( gpio_base + 0x4) = 0x0000;
+ if (CMSDK_GPIO->DATAOUT != 0x0000) {err_code |= (1<<29); }
+ small_delay(); /* required because the DATA readback is delay by double-flop-flop synchronisation */
+ if ((CMSDK_GPIO->DATA & gpio_datamask) != (0x0000 & gpio_datamask)) {err_code |= (1<<30); }
+
+ CMSDK_GPIO->OUTENABLECLR = 0xFFFFFFFF; /* Disable output */
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Read/write #1 failed(0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ small_delay();
+
+ /* Test ALTFUNC register */
+ CMSDK_GPIO->ALTFUNCCLR = 0xFFFF;
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_mask) != (0x0000 & gpio_altfunc_mask)) {err_code |= (1<<0); }
+ if ((HW16_REG(gpio_base + 0x18) & gpio_altfunc_mask) != (0x0000 & gpio_altfunc_mask)) {err_code |= (1<<1); }
+ if ((HW16_REG(gpio_base + 0x1A) ) != (0x0000 )) {err_code |= (1<<2); }
+
+ CMSDK_GPIO->ALTFUNCSET = 0xFFFF;
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_mask) != (0xFFFF & gpio_altfunc_mask)) {err_code |= (1<<3); }
+ if ((HW16_REG(gpio_base + 0x18) & gpio_altfunc_mask) != (0xFFFF & gpio_altfunc_mask)) {err_code |= (1<<4); }
+ if ((HW16_REG(gpio_base + 0x1A) ) != (0x0000 )) {err_code |= (1<<5); }
+ if ((HW8_REG( gpio_base + 0x18) & gpio_altfunc_mask) != (0xFF & gpio_altfunc_mask)) {err_code |= (1<<6); }
+ if ((HW8_REG( gpio_base + 0x19) & (gpio_altfunc_mask>>8)) != (0xFF & (gpio_altfunc_mask>>8))) {err_code |= (1<<7); }
+
+ HW16_REG(gpio_base + 0x1C) = 0x996E;
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_mask) != (0x6691 & gpio_altfunc_mask)) {err_code |= (1<<8); }
+ HW16_REG(gpio_base + 0x1A) = 0xFFFF; /* ignored */
+ if ((HW16_REG(gpio_base + 0x18) & gpio_altfunc_mask) != (0x6691 & gpio_altfunc_mask)) {err_code |= (1<<9); }
+ if ((HW16_REG(gpio_base + 0x1A) ) != (0x0000 )) {err_code |= (1<<10); }
+ if ((HW8_REG( gpio_base + 0x18) & gpio_altfunc_mask) != (0x91 & gpio_altfunc_mask)) {err_code |= (1<<11); }
+ if ((HW8_REG( gpio_base + 0x19) & (gpio_altfunc_mask>>8)) != (0x66 & (gpio_altfunc_mask>>8))) {err_code |= (1<<12); }
+ HW16_REG(gpio_base + 0x1C) = 0xFFFF;
+ HW8_REG(gpio_base + 0x18) = 0x45;
+ HW8_REG(gpio_base + 0x19) = 0x23;
+ HW8_REG(gpio_base + 0x1A) = 0x77;
+ HW8_REG(gpio_base + 0x1B) = 0x77;
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_mask) != (0x2345 & gpio_altfunc_mask)) {err_code |= (1<<13); }
+ if ((HW8_REG( gpio_base + 0x18) & gpio_altfunc_mask) != (0x45 & gpio_altfunc_mask)) {err_code |= (1<<14); }
+ if ((HW8_REG( gpio_base + 0x19) & (gpio_altfunc_mask>>8)) != (0x23 & (gpio_altfunc_mask>>8))) {err_code |= (1<<15); }
+
+ CMSDK_GPIO->ALTFUNCSET = 0x5488;
+ CMSDK_GPIO->ALTFUNCCLR = 0x2201;
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_mask) != (0x55CC & gpio_altfunc_mask)) {err_code |= (1<<16); }
+ CMSDK_GPIO->ALTFUNCCLR = 0x00CC;
+ CMSDK_GPIO->ALTFUNCSET = 0xAA33;
+ if ((CMSDK_GPIO->ALTFUNCSET & gpio_altfunc_mask) != (0xFF33 & gpio_altfunc_mask)) {err_code |= (1<<17); }
+ CMSDK_GPIO->ALTFUNCCLR = 0xFFFF;
+ CMSDK_GPIO->ALTFUNCSET = saved_altfunc; /* Restore ALTFUNC */
+
+ if (err_code != 0) {
+ printf ("ERROR : Read/write #2 failed(0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ // Write to every location
+
+ /* Test INTEN register read/write - offset 0x20 */
+ CMSDK_GPIO->INTENSET = 0x00FF;
+ if ((CMSDK_GPIO->INTENSET) != 0x00FF){err_code |= (1<<0); }
+ if ( HW8_REG(gpio_base + 0x20)!= 0xFF ){err_code |= (1<<1); }
+ if ( HW8_REG(gpio_base + 0x21)!= 0x00 ){err_code |= (1<<2); }
+ if (HW16_REG(gpio_base + 0x22)!= 0x0000){err_code |= (1<<3); }
+ CMSDK_GPIO->INTENSET = 0xFF00;
+ CMSDK_GPIO->INTENCLR = 0x00FF;
+ if ((CMSDK_GPIO->INTENSET) != 0xFF00){err_code |= (1<<4); }
+ if (HW16_REG(gpio_base + 0x20)!= 0xFF00){err_code |= (1<<5); }
+ if ( HW8_REG(gpio_base + 0x20)!= 0x00 ){err_code |= (1<<6); }
+ if ( HW8_REG(gpio_base + 0x21)!= 0xFF ){err_code |= (1<<7); }
+
+ CMSDK_GPIO->INTENCLR = 0x5500;
+ CMSDK_GPIO->INTENSET = 0x0055;
+ if ((CMSDK_GPIO->INTENSET) != 0xAA55) {err_code |= (1<<8); }
+ CMSDK_GPIO->INTENCLR = 0xFFFF;
+ CMSDK_GPIO->INTENSET = 0x33BB;
+ if ((CMSDK_GPIO->INTENSET) != 0x33BB) {err_code |= (1<<9); }
+ HW8_REG(gpio_base + 0x20) = 0x44;
+ HW8_REG(gpio_base + 0x24) = 0xBA;
+ HW8_REG(gpio_base + 0x25) = 0x10;
+ HW8_REG(gpio_base + 0x26) = 0x99;
+ HW8_REG(gpio_base + 0x27) = 0x99;
+ if ((CMSDK_GPIO->INTENSET) != 0x2345) {err_code |= (1<<10); }
+ HW16_REG(gpio_base + 0x20) = 0x5892;
+ HW16_REG(gpio_base + 0x22) = 0x1111;
+ HW16_REG(gpio_base + 0x24) = 0x0240;
+ if ((CMSDK_GPIO->INTENSET) != 0x7997) {err_code |= (1<<11); }
+
+ CMSDK_GPIO->INTENCLR = 0xFFFF;
+ if ((CMSDK_GPIO->INTENSET) != 0x0000) {err_code |= (1<<12); }
+
+ /* Test INTTYPE register read/write - offset 0x14 */
+ CMSDK_GPIO->INTTYPESET = 0x3A6B;
+ if ((CMSDK_GPIO->INTTYPESET) != 0x3A6B) {err_code |= (1<<19); }
+ if ( HW8_REG(gpio_base + 0x28)!= 0x6B ){err_code |= (1<<20); }
+ if ( HW8_REG(gpio_base + 0x29)!= 0x3A ){err_code |= (1<<21); }
+ if ( HW8_REG(gpio_base + 0x2A)!= 0x00 ){err_code |= (1<<22); }
+ if ( HW8_REG(gpio_base + 0x2B)!= 0x00 ){err_code |= (1<<23); }
+
+ HW16_REG(gpio_base + 0x2C) = 0xFFFF;
+ HW8_REG(gpio_base + 0x28) = 0x7C;
+ HW8_REG(gpio_base + 0x29) = 0x4B;
+ if ((CMSDK_GPIO->INTTYPESET) != 0x4B7C) {err_code |= (1<<24); }
+ if (HW16_REG(gpio_base + 0x28)!= 0x4B7C ){err_code |= (1<<25); }
+
+ HW16_REG(gpio_base + 0x2C) = 0x4964;
+ HW16_REG(gpio_base + 0x28) = 0x8001;
+ HW16_REG(gpio_base + 0x2A) = 0xFFFF;
+ if ((CMSDK_GPIO->INTTYPESET) != 0x8219) {err_code |= (1<<26); }
+ CMSDK_GPIO->INTTYPESET = 0xFFFF;
+ if ((CMSDK_GPIO->INTTYPESET) != 0xFFFF) {err_code |= (1<<27); }
+ CMSDK_GPIO->INTTYPECLR = 0xFFFF;
+ if ((CMSDK_GPIO->INTTYPESET) != 0x0000) {err_code |= (1<<28); }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Read/write #3 failed(0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+
+ /* Test INTPOL register read/write - offset 0x18 */
+ CMSDK_GPIO->INTPOLSET = 0x3B6A;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x3B6A) {err_code |= (1<<0); }
+ if ( HW8_REG(gpio_base + 0x30)!= 0x6A ){err_code |= (1<<1); }
+ if ( HW8_REG(gpio_base + 0x31)!= 0x3B ){err_code |= (1<<2); }
+ if ( HW8_REG(gpio_base + 0x32)!= 0x00 ){err_code |= (1<<3); }
+ if ( HW8_REG(gpio_base + 0x33)!= 0x00 ){err_code |= (1<<4); }
+ if (HW16_REG(gpio_base + 0x30)!= 0x3B6A){err_code |= (1<<5); }
+ HW16_REG(gpio_base + 0x34) = 0xFFFF;
+ HW16_REG(gpio_base + 0x30) = 0x4B7C;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x4B7C) {err_code |= (1<<6); }
+ HW16_REG(gpio_base + 0x32)= 0x3333;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x4B7C) {err_code |= (1<<7); }
+ HW8_REG( gpio_base + 0x34) = 0xFF;
+ HW8_REG( gpio_base + 0x30) = 0x95;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x4B95) {err_code |= (1<<8); }
+ HW8_REG( gpio_base + 0x35) = 0xFF;
+ HW8_REG( gpio_base + 0x31) = 0x32;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x3295) {err_code |= (1<<9); }
+ HW16_REG(gpio_base + 0x36)= 0xFFFF;
+ HW8_REG( gpio_base + 0x32) = 0x66;
+ HW8_REG( gpio_base + 0x33) = 0x66;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x3295) {err_code |= (1<<10); }
+ HW16_REG(gpio_base + 0x34)= 0xFFFF;
+ CMSDK_GPIO->INTPOLSET = 0x8219;
+ if (HW16_REG(gpio_base + 0x30) != 0x8219) {err_code |= (1<<11); }
+ CMSDK_GPIO->INTPOLSET = 0xFFFF;
+ if ((CMSDK_GPIO->INTPOLSET) != 0xFFFF) {err_code |= (1<<12); }
+ CMSDK_GPIO->INTPOLCLR = 0xFFFF;
+ if ((CMSDK_GPIO->INTPOLSET) != 0x0000) {err_code |= (1<<13); }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Read/write #4 failed(0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+ puts("- INTSTATUS/INTCLEAR r/w");
+
+ /* Test INTSTATUS/INTCLEAR register read/write - offset 0x1C */
+ /* It was not set because when INTEN was high, input was high, but INTPOL was low (low level trigger) */
+ if ((CMSDK_GPIO->INTSTATUS) != 0x0000) {err_code |= (1<<0); }
+ if ( HW8_REG(gpio_base + 0x38)!= 0x00 ){err_code |= (1<<1); }
+ if ( HW8_REG(gpio_base + 0x39)!= 0x00 ){err_code |= (1<<2); }
+ if ( HW8_REG(gpio_base + 0x3A)!= 0x00 ){err_code |= (1<<3); }
+ if ( HW8_REG(gpio_base + 0x3B)!= 0x00 ){err_code |= (1<<4); }
+ if (HW16_REG(gpio_base + 0x38)!= 0x0000){err_code |= (1<<5); }
+
+ /* Now we need to force INTSTATUS to 0xFFFF */
+ CMSDK_GPIO->INTENSET = 0xFFFF;
+ CMSDK_GPIO->INTPOLSET= 0xFFFF;
+ /* It set INTSTATUS to 0xFFFF because INTEN was set, DATA input was pulled up and INTPOL was 0xFFFF */
+
+ /* Disable interrupt from generating continuously */
+ CMSDK_GPIO->INTENCLR = 0xFFFF;
+ CMSDK_GPIO->INTPOLCLR= 0xFFFF;
+
+ /* Test clearing of INTSTATUS */
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFFFF & gpio_datamask)) {err_code |= (1<<6); }
+ if (( HW8_REG(gpio_base + 0x38) & gpio_datamask )!= (0xFF & gpio_datamask) ) {err_code |= (1<<7); }
+ if (( HW8_REG(gpio_base + 0x39) & gpio_datamask )!= (0xFF & gpio_datamask) ) {err_code |= (1<<8); }
+ if (( HW8_REG(gpio_base + 0x3A) & gpio_datamask )!= (0x00 & gpio_datamask) ) {err_code |= (1<<9); }
+ if (( HW8_REG(gpio_base + 0x3B) & gpio_datamask )!= (0x00 & gpio_datamask) ) {err_code |= (1<<10); }
+ if ((HW16_REG(gpio_base + 0x38) & gpio_datamask )!= (0xFFFF & gpio_datamask) ) {err_code |= (1<<11); }
+ if ((HW16_REG(gpio_base + 0x3A) & gpio_datamask )!= (0x0000 & gpio_datamask) ) {err_code |= (1<<12); }
+
+ CMSDK_GPIO->INTCLEAR = 0x0000;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFFFF & gpio_datamask)) {err_code |= (1<<13); }
+
+ CMSDK_GPIO->INTCLEAR = 0x0001;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFFFE & gpio_datamask)) {err_code |= (1<<14); }
+ if (( HW8_REG(gpio_base + 0x38) & gpio_datamask )!= (0xFE & gpio_datamask) ) {err_code |= (1<<15); }
+ if (( HW8_REG(gpio_base + 0x39) & gpio_datamask )!= (0xFF & gpio_datamask) ) {err_code |= (1<<16); }
+
+ HW16_REG(gpio_base + 0x38) = 0x0002;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFFFC & gpio_datamask)) {err_code |= (1<<17); }
+ HW16_REG(gpio_base + 0x38) = 0x0004;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFFF8 & gpio_datamask)) {err_code |= (1<<18); }
+ HW8_REG(gpio_base + 0x38) = 0x0008;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFFF0 & gpio_datamask)) {err_code |= (1<<19); }
+ HW8_REG(gpio_base + 0x39) = 0x0001;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFEF0 & gpio_datamask)) {err_code |= (1<<20); }
+ if ((HW16_REG(gpio_base + 0x38) & gpio_datamask )!= (0xFEF0 & gpio_datamask) ) {err_code |= (1<<21); }
+ CMSDK_GPIO->INTCLEAR = 0x000E; /* Clear a bit that is already cleared has no effect */
+ if ((HW16_REG(gpio_base + 0x38) & gpio_datamask )!= (0xFEF0 & gpio_datamask) ) {err_code |= (1<<22); }
+ HW8_REG(gpio_base + 0x3A) = 0x000F; /* ignored */
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFEF0 & gpio_datamask)) {err_code |= (1<<23); }
+ HW16_REG(gpio_base + 0x3A) = 0xFFFF; /* ignored */
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xFEF0 & gpio_datamask)) {err_code |= (1<<24); }
+ CMSDK_GPIO->INTCLEAR = 0x3330;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0xCCC0 & gpio_datamask)) {err_code |= (1<<25); }
+ CMSDK_GPIO->INTCLEAR = 0xCCC0;
+ if ((CMSDK_GPIO->INTSTATUS & gpio_datamask) != (0x0000 & gpio_datamask)) {err_code |= (1<<26); }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : INTSTATUS/INTCLEAR r/w failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ /* Clean up */
+ CMSDK_GPIO->OUTENABLECLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTPOLCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTCLEAR = 0x0000FFFF;
+ gpio0_irq_occurred = 0;
+ gpio1_irq_occurred = 0;
+ gpio0_irq_expected = 0;
+ gpio1_irq_expected = 0;
+
+ /* Test whether the PORT0_0_IRQn is available */
+ /* Note : GPIO Interrupt is pended in previous test stage */
+ __disable_irq(); /* Use setting of Interrupt enable to detect if
+ we have 32 interrupts, but we don't want the exact interrupt to
+ take place, so we disable interrupt using PRIMASK during this checking */
+ NVIC_EnableIRQ(PORT0_15_IRQn);
+ if ((NVIC->ISER[0] & 0x80000000U)==0) {
+ /* Number of IRQ less than 32, skip individual IRQ test */
+ puts("Less then 32 IRQ in design\n");
+ test_individual_irq = 0;
+ }
+ NVIC_DisableIRQ(PORT0_15_IRQn);
+ __enable_irq();
+
+
+ /* Check and Clear interrupt pending status in NVIC */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+
+ if (test_individual_irq == 1) {
+ for (i=0;i<16;i++){
+ if (NVIC_GetPendingIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + i))) == 0) { /* Should have been set */
+ err_code = err_code | (1<<i);
+ }
+ NVIC_ClearPendingIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + i)));
+ }
+ }
+ if (NVIC_GetPendingIRQ(PORT0_ALL_IRQn) == 0) {/* Should have been set */
+ err_code = err_code | (1<<16);
+ }
+ }
+
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ if (NVIC_GetPendingIRQ(PORT1_ALL_IRQn) == 0) {/* Should have been set */
+ err_code = err_code | (1<<17);
+ }
+ }
+
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+ NVIC_ClearPendingIRQ(PORT1_ALL_IRQn);
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : IRQ pending failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+ else puts("Register Read/Write Test Passed");
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* GPIO Unused Addresses access tests */
+/* --------------------------------------------------------------- */
+/* Test just one address - should read 0, write should be ignored */
+int gpio_unused_addresses_test_single(unsigned int address)
+{
+ if (HW32_REG(address) != 0) return (1);
+ HW32_REG(address) = 0xFFFFFFFF;
+ if (HW32_REG(address) != 0) return (1);
+ else return (0);
+}
+
+/* Test unused address in GPIO */
+int gpio_unused_addresses_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO){
+ int return_val=0;
+ unsigned int err_code=0;
+
+ unsigned int gpio_base;
+
+ puts("GPIO Unused address test");
+
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio_base = CMSDK_GPIO0_BASE;
+ }
+ else if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio_base = CMSDK_GPIO1_BASE;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'gpio_unused_addresses_test'.");
+ return 1;
+ }
+
+ if (gpio_unused_addresses_test_single(gpio_base + 0x008)) err_code |= 1 << 0;
+ if (gpio_unused_addresses_test_single(gpio_base + 0x00C)) err_code |= 1 << 1;
+ if (gpio_unused_addresses_test_single(gpio_base + 0x03C)) err_code |= 1 << 2;
+ if (gpio_unused_addresses_test_single(gpio_base + 0x040)) err_code |= 1 << 3;
+ if (gpio_unused_addresses_test_single(gpio_base + 0x3FC)) err_code |= 1 << 4;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xC00)) err_code |= 1 << 5;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xD00)) err_code |= 1 << 6;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xE00)) err_code |= 1 << 7;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xF00)) err_code |= 1 << 8;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xFC0)) err_code |= 1 << 9;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xFC4)) err_code |= 1 << 10;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xFC8)) err_code |= 1 << 11;
+ if (gpio_unused_addresses_test_single(gpio_base + 0xFCC)) err_code |= 1 << 12;
+
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Unused addresses failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+ else puts("- Unused addresses Test Passed");
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* GPIO interrupt tests */
+/* --------------------------------------------------------------- */
+
+int gpio_interrupt_test(CMSDK_GPIO_TypeDef *CMSDK_GPIO){
+ int return_val=0;
+ int err_code=0;
+ int i; /* loop variable */
+ int irq_num; /* loop variable */
+ unsigned int irq_mask; /* one hot bit mask for IRQ being tested in the loop */
+
+ unsigned int gpio_datamask; /* Data bit mask */
+ int test_individual_irq = 1; /* Test individual IRQ in GPIO #0 by default */
+
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ /* GPIO #0 is not shared in example system */
+ gpio_datamask = 0xFFFFFFFF; /* All bit can be tested */
+ }
+ else if (CMSDK_GPIO==CMSDK_GPIO1) {
+ /* GPIO #1 is shared with peripherals in example system */
+ /* bit 5 is used by stdout */
+ gpio_datamask = ~((1<<5)|(1<<4)|(1<<2)|(1<<0)); /* skip testing for these bits */
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'gpio_interrupt_test'.");
+ return 1;
+ }
+
+ for (i=0;i<16;i++){
+ gpio0_irq_flags[i]=0;
+ }
+ puts("GPIO interrupt test");
+
+ /* Check interrupt configurations */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ NVIC_EnableIRQ(PORT0_ALL_IRQn);
+ if ((NVIC->ISER[0] & (1<<(PORT0_ALL_IRQn)))==0) {
+ puts("Interrupt PORT0_ALL_IRQn not available.");
+ return_val =1;
+ }
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ NVIC_EnableIRQ(PORT1_ALL_IRQn);
+ if ((NVIC->ISER[0] & (1<<(PORT1_ALL_IRQn)))==0) {
+ puts("Interrupt PORT1_ALL_IRQn not available.");
+ return_val =1;
+ }
+ NVIC_DisableIRQ(PORT1_ALL_IRQn);
+ }
+ NVIC_EnableIRQ(PORT0_15_IRQn);
+ if ((NVIC->ISER[0] & 0x80000000U)==0) {
+ /* Number of IRQ less than 32, skip individual IRQ test */
+ puts("Less then 32 IRQ in design\n");
+ test_individual_irq = 0;
+ }
+ NVIC_DisableIRQ(PORT0_15_IRQn);
+
+ /* Start test loop */
+ for (irq_num = 0 ; irq_num <16; irq_num ++) {
+ if (((gpio_datamask>>irq_num) & 0x1)!=0) {
+ /* test required */
+
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTPOLCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTTYPECLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTCLEAR = 0x0000FFFF;
+ CMSDK_GPIO->OUTENABLECLR = 0xFFFFFFFF;
+ gpio0_irq_occurred = 0;
+ gpio1_irq_occurred = 0;
+ gpio0_irq_expected = 0;
+ gpio1_irq_expected = 0;
+ gpio0_irq_level_irq = 1;
+ gpio1_irq_level_irq = 1;
+ multi_irq_test = 0;
+ /* ------------------------------ */
+ /* Active low interrupt */
+ /* ------------------------------ */
+ CMSDK_GPIO->DATAOUT = 0xFFFFFFFF; /* Inactive */
+ CMSDK_GPIO->INTTYPECLR = 0xFFFFFFFF; /* Low level */
+ CMSDK_GPIO->INTPOLCLR = 0xFFFFFFFF; /* Low level */
+ irq_mask = 1<<irq_num;
+ CMSDK_GPIO->OUTENABLESET = irq_mask;
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_expected = irq_mask;
+ NVIC_EnableIRQ(PORT0_ALL_IRQn);
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_expected = irq_mask;
+ NVIC_EnableIRQ(PORT1_ALL_IRQn);
+ }
+ /* -- interrupt enable -- */
+ gpio0_irq_level_irq = 1;
+ CMSDK_GPIO->INTENSET = irq_mask;
+ //medium_delay();
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ /* Should not trigger IRQ yet because signal is high */
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<0);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = ~irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<1);}
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ /* Should not trigger IRQ yet because signal is high */
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<0);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = ~irq_mask; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred==0) { err_code |= (1<<1);}
+ }
+ /* -- interrupt disable -- */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ gpio0_irq_expected = 0;
+ gpio1_irq_expected = 0;
+ gpio0_irq_occurred = 0;
+ gpio1_irq_occurred = 0;
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ CMSDK_GPIO->DATAOUT = ~irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<2);}
+ CMSDK_GPIO->DATAOUT = 0xFFFFFFFF; /* Inactive */
+ medium_delay();
+ if (CMSDK_GPIO->INTSTATUS!=0){ err_code |= (1<<3);}
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ CMSDK_GPIO->DATAOUT = ~irq_mask; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<2);}
+ CMSDK_GPIO->DATAOUT = 0xFFFFFFFF; /* Inactive */
+ medium_delay();
+ if (CMSDK_GPIO->INTSTATUS!=0){ err_code |= (1<<3);}
+ }
+
+ /* -- separated irq -- */
+ if ((CMSDK_GPIO==CMSDK_GPIO0) && (test_individual_irq!=0)) {
+ gpio0_irq_flags[irq_num]=0;
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ NVIC_ClearPendingIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ NVIC_EnableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_level_irq = 1;
+ CMSDK_GPIO->INTENSET = irq_mask;
+ CMSDK_GPIO->DATAOUT = ~irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<4);}
+ if (gpio0_irq_flags[irq_num]==0) { err_code |= (1<<5);}
+ CMSDK_GPIO->DATAOUT = 0xFFFFFFFF; /* Inactive */
+
+ /* Clean up */
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+
+ NVIC_DisableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_flags[irq_num]= 0;
+ gpio0_irq_expected = 0;
+ gpio0_irq_occurred = 0;
+ }
+
+ /* -- multiple irq -- */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_occurred = 0;
+ NVIC_EnableIRQ(PORT0_ALL_IRQn);
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_expected = irq_mask;
+ gpio1_irq_occurred = 0;
+ NVIC_EnableIRQ(PORT1_ALL_IRQn);
+ }
+ multi_irq_test = 3; /* IRQ trigger 3 times */
+ CMSDK_GPIO->INTENSET = irq_mask;
+ CMSDK_GPIO->DATAOUT = ~irq_mask; /* active */
+ medium_delay();
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ if (gpio0_irq_occurred!=3) { err_code |= (1<<6);}
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ if (gpio1_irq_occurred!=3) { err_code |= (1<<6);}
+ }
+ CMSDK_GPIO->DATAOUT = 0xFFFFFFFF; /* Inactive */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF; /* Disable */
+ multi_irq_test = 0; /* Disable multiple IRQ test */
+ /* ------------------------------ */
+ /* Active high interrupt */
+ /* ------------------------------ */
+ CMSDK_GPIO->INTPOLSET = irq_mask; /* High level */
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* Inactive */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_occurred = 0;
+ }
+
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_expected = irq_mask;
+ gpio1_irq_occurred = 0;
+ }
+ /* -- interrupt enable -- */
+ CMSDK_GPIO->INTENSET = irq_mask; /* Enable */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<7);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<8);}
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<7);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred==0) { err_code |= (1<<8);}
+ }
+
+ /* -- interrupt disable -- */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ gpio0_irq_expected = 0;
+ gpio1_irq_expected = 0;
+ gpio0_irq_occurred = 0;
+ gpio1_irq_occurred = 0;
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<9);}
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* Inactive */
+ medium_delay();
+ if (CMSDK_GPIO->INTSTATUS!=0){ err_code |= (1<<10);}
+ }
+
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<9);}
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* Inactive */
+ medium_delay();
+ if (CMSDK_GPIO->INTSTATUS!=0){ err_code |= (1<<10);}
+ }
+
+ /* -- separated irq -- */
+ if ((CMSDK_GPIO==CMSDK_GPIO0) && (test_individual_irq!=0)) {
+ gpio0_irq_flags[irq_num]=0;
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ NVIC_ClearPendingIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ NVIC_EnableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_level_irq = 1;
+ CMSDK_GPIO->INTENSET = irq_mask;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<11);}
+ if (gpio0_irq_flags[irq_num]==0) { err_code |= (1<<12);}
+ CMSDK_GPIO->DATAOUT = 0x0; /* Inactive */
+ /* Clean up */
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+ NVIC_DisableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_flags[irq_num]= 0;
+ gpio0_irq_expected = 0;
+ gpio0_irq_occurred = 0;
+ }
+ /* -- multiple irq -- */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_occurred = 0;
+ NVIC_EnableIRQ(PORT0_ALL_IRQn);
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_expected = irq_mask;
+ gpio1_irq_occurred = 0;
+ NVIC_EnableIRQ(PORT1_ALL_IRQn);
+ }
+ multi_irq_test = 3; /* IRQ trigger 3 times */
+ CMSDK_GPIO->INTENSET = irq_mask;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ if (gpio0_irq_occurred!=3) { err_code |= (1<<13);}
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ if (gpio1_irq_occurred!=3) { err_code |= (1<<13);}
+ }
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* Inactive */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF; /* Disable */
+ multi_irq_test = 0; /* Disable multiple IRQ test */
+ /* ------------------------------ */
+ /* Active rising edge interrupt */
+ /* ------------------------------ */
+
+ CMSDK_GPIO->INTPOLSET = irq_mask; /* Rising edge */
+ CMSDK_GPIO->INTTYPESET = irq_mask; /* Rising edge */
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* Inactive */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_occurred = 0;
+ gpio0_irq_level_irq = 0;
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_expected = irq_mask;
+ gpio1_irq_occurred = 0;
+ gpio1_irq_level_irq = 0;
+ }
+ /* -- interrupt enable -- */
+ CMSDK_GPIO->INTENSET = irq_mask; /* Enable */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<14);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<15);}
+ gpio0_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* falling edge, should not trigger */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<16);}
+
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<14);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred==0) { err_code |= (1<<15);}
+ gpio1_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* falling edge, should not trigger */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<16);}
+ }
+ /* -- interrupt disable -- */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF; /* Disable */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_occurred = 0;
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<17);}
+ /* Rising edge - but IRQ is disabled */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<18);}
+ gpio0_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* falling edge, should not trigger */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<19);}
+
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_occurred = 0;
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<17);}
+ /* Rising edge - but IRQ is disabled */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<18);}
+ gpio1_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* falling edge, should not trigger */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<19);}
+ }
+ /* -- separated irq -- */
+ if ((CMSDK_GPIO==CMSDK_GPIO0) && (test_individual_irq!=0)) {
+ gpio0_irq_flags[irq_num]=0;
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ NVIC_ClearPendingIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ NVIC_EnableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_expected = irq_mask;
+ CMSDK_GPIO->INTENSET = irq_mask;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<20);}
+ if (gpio0_irq_flags[irq_num]==0) { err_code |= (1<<21);}
+ gpio0_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = 0x0; /* Inactive */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<22);}
+
+ /* Clean up */
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+ NVIC_DisableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_flags[irq_num]= 0;
+ gpio0_irq_expected = 0;
+ gpio0_irq_occurred = 0;
+ }
+ /* ------------------------------ */
+ /* Active falling edge interrupt */
+ /* ------------------------------ */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTPOLCLR = 0xFFFFFFFF; /* Falling edge */
+ CMSDK_GPIO->INTTYPESET = irq_mask; /* Falling edge */
+ CMSDK_GPIO->DATAOUT = irq_mask; /* Inactive */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_expected = irq_mask;
+ gpio0_irq_occurred = 0;
+ gpio0_irq_level_irq = 0;
+ NVIC_EnableIRQ(PORT0_ALL_IRQn);
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_expected = irq_mask;
+ gpio1_irq_occurred = 0;
+ gpio1_irq_level_irq = 0;
+ NVIC_EnableIRQ(PORT1_ALL_IRQn);
+ }
+ /* -- interrupt enable -- */
+ CMSDK_GPIO->INTENSET = irq_mask; /* Enable */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ /* Should not trigger IRQ yet because signal is high */
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<23);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<24);}
+ gpio0_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* rising edge, should not trigger */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<25);}
+
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<23);}
+ /* Trigger combined IRQ now */
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred==0) { err_code |= (1<<24);}
+ gpio1_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* rising edge, should not trigger */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<25);}
+ }
+ /* -- interrupt disable -- */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF; /* Disable */
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ gpio0_irq_occurred = 0;
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<26);}
+ /* falling edge - but IRQ is disabled */
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<27);}
+ gpio0_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* rising edge, should not trigger */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= (1<<28);}
+
+ }
+ if (CMSDK_GPIO==CMSDK_GPIO1) {
+ gpio1_irq_occurred = 0;
+ /* Should not trigger IRQ yet because signal is low */
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<26);}
+ /* falling edge - but IRQ is disabled */
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* active */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<27);}
+ gpio1_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* rising edge, should not trigger */
+ medium_delay();
+ if (gpio1_irq_occurred!=0) { err_code |= (1<<28);}
+ }
+ /* -- separated irq -- */
+ if ((CMSDK_GPIO==CMSDK_GPIO0) && (test_individual_irq!=0)) {
+ gpio0_irq_flags[irq_num]=0;
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ NVIC_ClearPendingIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ NVIC_EnableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_expected = irq_mask;
+ CMSDK_GPIO->INTENSET = irq_mask;
+ CMSDK_GPIO->DATAOUT = 0x00000000; /* active */
+ medium_delay();
+ if (gpio0_irq_occurred==0) { err_code |= (1<<29);}
+ if (gpio0_irq_flags[irq_num]==0) { err_code |= (1<<30);}
+ gpio0_irq_occurred = 0;
+ CMSDK_GPIO->DATAOUT = irq_mask; /* Inactive */
+ medium_delay();
+ if (gpio0_irq_occurred!=0) { err_code |= 0x80000000UL;}
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ /* Clean up */
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+ NVIC_DisableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + irq_num)));
+ gpio0_irq_flags[irq_num]= 0;
+ gpio0_irq_expected = 0;
+ gpio0_irq_occurred = 0;
+ }
+
+ if (err_code != 0) {
+ printf ("ERROR : Interrupt failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ /* Cleaning up */
+ CMSDK_GPIO->INTENCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTTYPECLR = 0xFFFFFFFF;
+ CMSDK_GPIO->INTPOLCLR = 0xFFFFFFFF;
+ CMSDK_GPIO->OUTENABLECLR = 0xFFFFFFFF;
+ CMSDK_GPIO->DATAOUT = 0x00000000;
+ CMSDK_GPIO->INTCLEAR = 0x0000FFFF;
+
+ } /* end if test required */
+ } /* end for irq_num */
+
+
+ /* Clean up */
+ gpio0_irq_occurred = 0;
+ gpio1_irq_occurred = 0;
+ gpio0_irq_expected = 0;
+ gpio1_irq_expected = 0;
+
+ NVIC_DisableIRQ(PORT0_ALL_IRQn);
+ NVIC_DisableIRQ(PORT1_ALL_IRQn);
+ if (CMSDK_GPIO==CMSDK_GPIO0) {
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+ for (i=0;i<16;i++){
+ NVIC_DisableIRQ(((IRQn_Type)(((int)PORT0_0_IRQn) + i)));
+ NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
+ }
+ } else {
+ NVIC_ClearPendingIRQ(PORT1_ALL_IRQn);
+ }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Interrupt failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+ else puts("Interrupt Test Passed");
+
+ return(return_val);
+}
+/* --------------------------------------- */
+/* Combined interrupt handler for GPIO #0 */
+/* */
+void PORT0_COMB_Handler(void)
+{
+ if (gpio0_irq_expected==0) {
+ puts ("ERROR : Unexpected GPIO 0 interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ else if (gpio0_irq_level_irq!=0) {
+ if (multi_irq_test > 1) {
+ multi_irq_test--; /* twice here : 3->2, 2->1 */
+ } else { /* once here */
+ /* Deassert interrupt source */
+ CMSDK_GPIO0->DATAOUT = CMSDK_GPIO0->DATAOUT ^ gpio0_irq_expected;
+ medium_delay();
+ }
+ }
+ CMSDK_GPIO0->INTCLEAR = gpio0_irq_expected;
+ gpio0_irq_occurred++;
+ return;
+}
+
+/* --------------------------------------- */
+/* Combined interrupt handler for GPIO #1 */
+/* */
+void PORT1_COMB_Handler(void)
+{
+ if (gpio1_irq_expected==0) {
+ puts ("ERROR : Unexpected GPIO 1 interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ else if (gpio1_irq_level_irq!=0) {
+ if (multi_irq_test > 1) {
+ multi_irq_test--; /* twice here : 3->2, 2->1 */
+ } else { /* once here */
+ /* Deassert interrupt source */
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT ^ gpio1_irq_expected;
+ medium_delay();
+ }
+ }
+ CMSDK_GPIO1->INTCLEAR = gpio1_irq_expected;
+ gpio1_irq_occurred++;
+ return;
+}
+
+/* ----------------------------------------- */
+/* Individual interrupt handler for GPIO #0 */
+/* */
+void PORT0_0_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[0]++;
+ return;
+}
+void PORT0_1_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[1]++;
+ return;
+}
+void PORT0_2_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[2]++;
+ return;
+}
+void PORT0_3_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[3]++;
+ return;
+}
+void PORT0_4_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[4]++;
+ return;
+}
+void PORT0_5_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[5]++;
+ return;
+}
+void PORT0_6_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[6]++;
+ return;
+}
+void PORT0_7_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[7]++;
+ return;
+}
+void PORT0_8_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[8]++;
+ return;
+}
+void PORT0_9_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[9]++;
+ return;
+}
+void PORT0_10_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[10]++;
+ return;
+}
+void PORT0_11_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[11]++;
+ return;
+}
+void PORT0_12_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[12]++;
+ return;
+}
+void PORT0_13_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[13]++;
+ return;
+}
+void PORT0_14_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[14]++;
+ return;
+}
+void PORT0_15_Handler(void){
+ PORT0_COMB_Handler();
+ gpio0_irq_flags[15]++;
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/memory_tests.c b/Cortex-M0/nanosoc/software/common/validation/memory_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..392854afb16e601b2d3ace72cfd58aa1f5bbaa67
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/memory_tests.c
@@ -0,0 +1,645 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check accesses to different memory locations
+*/
+
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#define SRAM_BASE_ADDR 0x20000000
+#define SRAM_SIZE 0x10000
+
+#define ROM_BASE_ADDR 0x00000000
+#define ROM_SIZE 0x10000
+
+#define BOOT_BASE_ADDR 0x01000000
+#define BOOT_SIZE 0x4000
+#define BOOT_ALIAS_SIZE 0x10000
+
+#define APB_IO_BASE_ADDR 0x40000000
+#define APB_IO_SIZE 0x10000
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+#if defined ( __CC_ARM )
+__asm void address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ void address_test_write(unsigned int addr, unsigned int wdata);
+ unsigned int address_test_read(unsigned int addr);
+#endif
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+int sram_test(void);
+int sram_test_word(unsigned int test_addr);
+int rom_test(void);
+int boot_rom_test(void);
+int apb_io_test(void);
+int ahb_io_test(void);
+int ID_Check(const unsigned char id_array[], unsigned int offset);
+int SysCtrl_ID_Check(const unsigned char id_array[], unsigned int offset);
+int SysCtrl_unused_addr_test(void);
+
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+ int hardfault_verbose=0; // 0:Not displaying anything in hardfault handler
+
+const unsigned char ahb_gpio_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x20, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+const unsigned char sysctrl_id[16] = {0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0x26, 0xB8, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1};
+
+int main (void)
+{
+ int err_code = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit");
+ puts(" - Simple memory test - revision $Revision: 371321 $\n");
+
+ temp_data=0;
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+
+ if (sram_test() !=0) err_code |= 1<< 0;
+ if (rom_test() !=0) err_code |= 1<< 1;
+ if (boot_rom_test() !=0) err_code |= 1<< 2;
+ if (apb_io_test() !=0) err_code |= 1<< 3;
+ if (ahb_io_test() !=0) err_code |= 1<< 4;
+
+
+ /* Generate test pass/fail and return value */
+ if (err_code==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+/* -------------------------------------------------------------------- */
+/* ROM test */
+/* -------------------------------------------------------------------- */
+int rom_test(void)
+{
+ int err_code = 0;
+
+ puts ("Checking ROM");
+
+ /* Test max and min addresses in ROM boundary */
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ temp_data = address_test_read(ROM_BASE_ADDR);
+ if (hardfault_occurred!=0) err_code |= 1<<0;
+ address_test_write(ROM_BASE_ADDR+ROM_SIZE-4, 0);
+ temp_data = address_test_read(ROM_BASE_ADDR+ROM_SIZE-4);
+ if (hardfault_occurred!=0) err_code |= 1<<1;
+
+ /* Test addresses beyond ROM boundary */
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(((unsigned)(ROM_BASE_ADDR-4)));
+ if (hardfault_occurred==0) err_code |= 1<<2;
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(ROM_BASE_ADDR+ROM_SIZE);
+ if (hardfault_occurred==0) err_code |= 1<<3;
+
+ if (err_code> 0) {
+ puts (" Failed\n");
+ printf ("Error code : %x\n", err_code);
+ return 1;
+ } else {
+ puts (" Passed\n");
+ return 0;
+ }
+}
+/* -------------------------------------------------------------------- */
+/* Boot loader ROM test */
+/* -------------------------------------------------------------------- */
+int boot_rom_test(void)
+{
+ int err_code = 0;
+
+ puts ("Checking Boot loader ROM");
+
+ /* Detect if boot loader present */
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(BOOT_BASE_ADDR);
+ if (hardfault_occurred!=0) {
+ puts (" Boot loader not present");
+ return 0;
+ }
+
+ /* Test max addresses in Boot loader ROM boundary */
+ hardfault_expected = 0;
+ hardfault_occurred = 0;
+ address_test_write(BOOT_BASE_ADDR+BOOT_SIZE-4, 0);
+ temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_SIZE-4);
+ if (hardfault_occurred!=0) err_code |= 1<<0;
+
+ /* Test addresses beyond Boot loader ROM boundary */
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(BOOT_BASE_ADDR-4);
+ if (hardfault_occurred==0) err_code |= 1<<1;
+
+ hardfault_occurred = 0;
+ hardfault_expected = 0; /* 64KB range is allocated for boot ROM,
+ but only 4K is used. Access over 4KB range wraps round */
+ temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_SIZE);
+ if (hardfault_occurred!=0) err_code |= 1<<2;
+
+ hardfault_occurred = 0;
+ hardfault_expected = 1; /* Check beyond alias range */
+ temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_ALIAS_SIZE);
+ if (hardfault_occurred==0) err_code |= 1<<3;
+
+ if (err_code> 0) {
+ puts (" Failed\n");
+ printf ("Error code : %x\n", err_code);
+ return 1;
+ } else {
+ puts (" Passed\n");
+ return 0;
+ }
+}
+/* -------------------------------------------------------------------- */
+/* SRAM test */
+/* -------------------------------------------------------------------- */
+int sram_test(void)
+{
+ int err_code = 0;
+
+ puts ("Checking SRAM");
+
+ /* Test max and min addresses in SRAM boundary */
+
+ // Starting location
+ if (sram_test_word(SRAM_BASE_ADDR )!=0) err_code |= 1<<0;
+ // Ending location
+ if (sram_test_word(SRAM_BASE_ADDR+SRAM_SIZE-4)!=0) err_code |= 1<<1;
+
+ /* Test addresses beyond SRAM boundary */
+
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(SRAM_BASE_ADDR-4);
+ if (hardfault_occurred==0) err_code |= 1<<2;
+
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(SRAM_BASE_ADDR+SRAM_SIZE);
+ if (hardfault_occurred==0) err_code |= 1<<3;
+
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+
+ if (err_code> 0) {
+ puts (" Failed\n");
+ printf ("Error code : %x\n", err_code);
+ return 1;
+ } else {
+ puts (" Passed\n");
+ return 0;
+ }
+}
+
+int sram_test_word(unsigned int test_addr)
+{
+ int result=0; // This will only work if result and temp are not store in address being tested
+ int temp;
+
+ __disable_irq(); // Make sure interrupt will not affect the result of the test
+
+ temp = HW32_REG(test_addr); // save data
+
+ /* Use consistence memory access size in checking so that it work with
+ both little endian and big endian configs */
+ HW32_REG(test_addr)=0x00000000;
+ if (HW32_REG(test_addr)!=0x00000000) result++;
+ HW16_REG(test_addr)=0xFFFF;
+ if (HW16_REG(test_addr)!=0xFFFF) result++;
+ HW8_REG(test_addr+3)=0x12;
+ HW8_REG(test_addr+2)=0xFF;
+ if (HW8_REG(test_addr+3)!=0x12) result++;
+ if (HW8_REG(test_addr+2)!=0xFF) result++;
+ HW8_REG(test_addr )=0x00;
+ HW8_REG(test_addr+1)=0x00;
+ if (HW8_REG(test_addr )!=0x00) result++;
+ if (HW8_REG(test_addr+1)!=0x00) result++;
+ HW16_REG(test_addr+2)=0xFE00;
+ if (HW16_REG(test_addr+2)!=0xFE00) result++;
+ HW32_REG(test_addr)=0x00000000;
+ if (HW32_REG(test_addr)!=0x00000000) result++;
+
+ HW32_REG(test_addr) = temp; // restore data
+ __enable_irq(); // re-enable IRQ
+ if (result !=0) printf ("ERROR: Memory location test failed at %x\n", test_addr);
+ return result;
+}
+
+
+/* -------------------------------------------------------------------- */
+/* APB test */
+/* -------------------------------------------------------------------- */
+int apb_io_test(void)
+{
+ int err_code = 0;
+
+ puts ("Checking APB space");
+
+ /* Test max and min addresses in IO boundary */
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ temp_data = address_test_read(APB_IO_BASE_ADDR);
+ if (hardfault_occurred!=0) err_code |= 1<<0;
+ temp_data = address_test_read(APB_IO_BASE_ADDR+APB_IO_SIZE-4);
+ if (hardfault_occurred!=0) err_code |= 1<<1;
+
+ /* Test addresses beyond IO boundary */
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(APB_IO_BASE_ADDR-4);
+ if (hardfault_occurred==0) err_code |= 1<<2;
+
+ /* Address above APB IO space is AHB GPIO, not test here */
+
+ if (err_code> 0) {
+ puts (" Failed\n");
+ printf ("Error code : %x\n", err_code);
+ return 1;
+ } else {
+ puts (" Passed\n");
+ return 0;
+ }
+}
+/* -------------------------------------------------------------------- */
+/* AHB test */
+/* -------------------------------------------------------------------- */
+int ahb_io_test(void)
+{
+ int err_code = 0;
+ unsigned int test_addr;
+ int i; /* loop counter */
+
+ puts ("Checking AHB I/O space");
+
+ /* Check ID for AHB peripheral */
+ puts (" - GPIO #0 ID values");
+ if (ID_Check(&ahb_gpio_id[0], CMSDK_GPIO0_BASE ) == 1 ) err_code |= 1<<0;
+ puts (" - GPIO #1 ID values");
+ if (ID_Check(&ahb_gpio_id[0], CMSDK_GPIO1_BASE ) == 1 ) err_code |= 1<<1;
+ puts (" - System Controller ID values");
+ if (SysCtrl_ID_Check(&sysctrl_id[0], CMSDK_SYSCTRL_BASE ) == 1 ) err_code |= 1<<2;
+ puts (" - System Controller unused addresses");
+ if (SysCtrl_unused_addr_test() == 1) err_code |= 1<<3;
+
+ /* Check limits of memory maps */
+ puts (" - Address range check");
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ temp_data = address_test_read(CMSDK_GPIO0_BASE); /* Should have no hard fault */
+ if (hardfault_occurred!=0) err_code |= 1<<4;
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ temp_data = address_test_read(CMSDK_GPIO1_BASE); /* Should have no hard fault */
+ if (hardfault_occurred!=0) err_code |= 1<<5;
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ temp_data = address_test_read(CMSDK_SYSCTRL_BASE); /* Should have no hard fault */
+ if (hardfault_occurred!=0) err_code |= 1<<6;
+
+ /* Unused AHB I/O space - should have hard fault */
+ for (i=0;i<13;i++) { // From 0x40010000 to 0x4001FFFF are AHB I/O space
+ hardfault_occurred = 0; // 0x40012000 to 0x4001EFFF are unused (13 slots)
+ hardfault_expected = 1;
+ test_addr = CMSDK_AHB_BASE+0x2000UL+(i*0x1000UL);
+ temp_data = address_test_read(test_addr); // Starting address of each slot
+ if (hardfault_occurred==0) {
+ err_code |= 1<<7;
+ printf("ERROR:Expected bus fault at %x did not take place\n", test_addr);
+ }
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ test_addr = test_addr + 0xFFC;
+ temp_data = address_test_read(test_addr); // Ending address of each slot
+ if (hardfault_occurred==0) {
+ err_code |= 1<<8;
+ printf("ERROR:Expected bus fault at %x did not take place\n", test_addr);
+ }
+ } // end_for
+
+ /* Test end of AHB I/O address range */
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ temp_data = address_test_read(0x40020000); // address beyond AHB I/O space
+ if (hardfault_occurred==0) {
+ err_code |= 1<<9;
+ puts("ERROR:Expected bus fault at 0x40020000 did not take place");
+ }
+
+ if (err_code> 0) {
+ puts (" Failed\n");
+ printf ("Error code : %x\n", err_code);
+ return 1;
+ } else {
+ puts (" Passed\n");
+ return 0;
+ }
+}
+
+/* -------------------------------------------------------------------- */
+/* ID value check */
+/* -------------------------------------------------------------------- */
+
+/* Check the ID register value in offset 0xFC0 to 0xFFC (last 16 words, last 12 are IDs) */
+int ID_Check(const unsigned char id_array[], unsigned int offset)
+{
+ int i; /* loop counter */
+ unsigned long expected_val, actual_val;
+ unsigned long compare_mask;
+ int mismatch = 0;
+ int id_is_zero = 0;
+ unsigned long test_addr;
+
+ /* Check the peripheral ID and component ID */
+ for (i=0;i<16;i++) {
+ test_addr = offset + 4*i + 0xFC0;
+ expected_val = (int) id_array[i];
+ actual_val = HW32_REG(test_addr);
+
+ if (actual_val == 0) id_is_zero++; // Check if all ID are zero at the end
+
+ /* create mask to ignore version numbers */
+ if (i==10) { compare_mask = 0xF0;} // mask out version field
+ else if (i==11) { compare_mask = 0xFF;} // mask out ECO field and patch field
+ else { compare_mask = 0x00;} // compare whole value
+
+ if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
+ printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
+ mismatch++;
+ }
+ } // end_for
+
+ if (id_is_zero == 16) {
+ puts (" All ID values are 0 : device not present\n");
+ return 2;
+ } else if (mismatch> 0) {
+ puts (" ID value mismatch(es) : device unknown\n");
+ return 1;
+ } else {
+ puts (" All ID values matched : device present\n");
+ return 0;
+ }
+}
+/* Check the ID register value in offset 0xFC0 to 0xFFC (last 16 words, last 12 are IDs) */
+int SysCtrl_ID_Check(const unsigned char id_array[], unsigned int offset)
+{
+ int i; /* loop counter */
+ unsigned long expected_val, actual_val;
+ unsigned long compare_mask;
+ int mismatch = 0;
+ int id_is_zero = 0;
+ unsigned long test_addr;
+
+ /* Check the peripheral ID and component ID */
+ for (i=0;i<16;i++) {
+ test_addr = offset + 4*i + 0xFC0;
+ expected_val = (int) id_array[i];
+ actual_val = HW32_REG(test_addr);
+
+ if (actual_val == 0) id_is_zero++; // Check if all ID are zero at the end
+
+ /* create mask to ignore version numbers */
+ if (i==10) { compare_mask = 0xF0;} // mask out version field
+ else if (i==11) { compare_mask = 0xFF;} // mask out ECO field and patch field
+ else { compare_mask = 0x00;} // compare whole value
+
+ if (i==8) {
+ /* The part number of the example system controller in CMSDK can be
+ 26 to 29 */
+ if ((actual_val<0x26)||(actual_val>0x29)) {
+ printf ("Difference found: %x, expected 0x26 to 0x29, actual %x\n", test_addr, actual_val);
+ mismatch++;
+ }
+ }
+ else {
+ if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
+ printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
+ mismatch++;
+ }
+ } // end_if_i_eq_8
+ } // end_for
+
+ if (id_is_zero == 16) {
+ puts (" All ID values are 0 : device not present\n");
+ return 2;
+ } else if (mismatch> 0) {
+ puts (" ID value mismatch(es) : device unknown\n");
+ return 1;
+ } else {
+ puts (" All ID values matched : device present\n");
+ return 0;
+ }
+}
+/* --------------------------------------------------------------- */
+/* SysCtrl Unused Addresses access tests */
+/* --------------------------------------------------------------- */
+
+int unused_addresses_test_single(unsigned int address)
+{
+ if (HW32_REG(address) != 0) return (1);
+ HW32_REG(address) = 0xFFFFFFFF;
+ if (HW32_REG(address) != 0) return (1);
+ else return (0);
+}
+
+/* Test unused address in SysCtrl */
+int SysCtrl_unused_addr_test(void)
+{
+ int return_val=0;
+ unsigned int err_code=0;
+
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0x00C)) err_code |= 1 << 0;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0x014)) err_code |= 1 << 1;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0x018)) err_code |= 1 << 2;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0x01C)) err_code |= 1 << 3;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0x020)) err_code |= 1 << 4;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xC00)) err_code |= 1 << 5;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xD00)) err_code |= 1 << 6;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xE00)) err_code |= 1 << 7;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xF00)) err_code |= 1 << 8;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xFC0)) err_code |= 1 << 9;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xFC4)) err_code |= 1 << 10;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xFC8)) err_code |= 1 << 11;
+ if (unused_addresses_test_single(CMSDK_SYSCTRL_BASE + 0xFCC)) err_code |= 1 << 12;
+
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("Error : Unused addresses failed (0x%x)\n", err_code);
+ return_val =1;
+ }
+ else puts(" Unused addresses Test Passed\n");
+
+ return(return_val);
+}
+/* -------------------------------------------------------------------- */
+/* Helper functions for testing bus fault */
+/* -------------------------------------------------------------------- */
+
+#if defined ( __CC_ARM )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ STR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ BX LR
+}
+
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ __asm(" str r1,[r0]\n"
+ " dsb \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+ ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ if (hardfault_verbose) puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ if (hardfault_verbose) printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ if (hardfault_verbose) printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/timer_driver_tests.c b/Cortex-M0/nanosoc/software/common/validation/timer_driver_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..db888a988eea9fd7c20df6fc9c34585d11bf6d5c
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/timer_driver_tests.c
@@ -0,0 +1,548 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the functionalities of timer functions in the example device driver.
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+#include "CMSDK_driver.h"
+
+int volatile timer_irq_counter;
+int volatile timer_irq_executed;
+uint32_t temp_test;
+
+/* Declare test functions */
+int Timer_Init(void);
+int Timer_IRQ(void);
+int Timer_Poll(void);
+int Timer_Ext(void);
+
+int timer0_id_check(void); // Detect Timer 0 present
+int gpio1_id_check(void); // Detect GPIO 1 present
+
+int main (void)
+{
+ int result = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Timer Driver Test - revision $Revision: 371321 $\n");
+
+ if (timer0_id_check()!=0) {
+ puts ("** TEST SKIPPED ** Timer 0 not present.");
+ UartEndSimulation();
+ return 0;}
+
+ /* Run tests */
+ result |= Timer_Init();
+ result |= Timer_IRQ();
+ result |= Timer_Poll();
+
+ if (gpio1_id_check()==0) {
+ /* GPIO #1 is require for creating test input */
+ result |= Timer_Ext(); /* Run external input test */
+ }
+ else {
+ if(result != 0) {
+ printf("** TEST FAILED **, Error code: (0x%x)\n\n", result);
+ }
+ puts ("** TEST SKIPPED ** GPIO 1 not present.");
+ UartEndSimulation();
+ return 0;
+ }
+
+ if(result == 0) {
+ puts("** TEST PASSED **\n");
+ } else {
+ printf("** TEST FAILED **, Error code: (0x%x)\n\n", result);
+ }
+
+ UartEndSimulation();
+
+ return result;
+}
+
+
+
+/* Initialisation test - set timer reload to 0xF00 with interrupt enabled */
+/* The test also check read back values of the control register and reload register */
+int Timer_Init(void)
+{
+ int err_code = 0;
+ uint32_t CTRL = 0;
+
+ puts("\nStage 1 - Timer Initialisation\n");
+
+ /* Stage 1 Test sequence
+ After CMSDK_timer_Init_IntClock is executed,
+ - read back timer #0 control register and save it to a variable
+ - stop timer (to stop interrupt for the moment to improve speed of the checking)
+ - check timer control register is set with correct value
+ - check timer reload register is set with correct value
+ - write back the previous control register value to resume timer operations
+ */
+
+ CMSDK_timer_Init_IntClock(CMSDK_TIMER0, 0xF00, 1); /*test timer interrupt using internal clock*/
+ CTRL = CMSDK_TIMER0->CTRL;
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+
+ if((CTRL & CMSDK_TIMER_CTRL_EN_Msk) != 0) {
+ puts("Timer Enabled");
+ }
+ else{
+ err_code |= (1 << 0);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+ if((CTRL & CMSDK_TIMER_CTRL_SELEXTEN_Msk) == 0){
+ puts("Ext Enable Not Selected");
+ }
+ else{
+ err_code |= (1 << 1);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+ if((CTRL & CMSDK_TIMER_CTRL_SELEXTCLK_Msk) == 0){
+ puts("Ext Clock Not Selected");
+ }
+ else{
+ err_code |= (1 << 2);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+ if((CTRL & CMSDK_TIMER_CTRL_IRQEN_Msk) != 0) {
+ puts("Timer IRQ Enabled");
+ }
+ else{
+ err_code |= (1 << 3);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+ if((CMSDK_TIMER0->RELOAD == 0xF00) != 0){
+ puts("Reload Value of 0xF00");
+ }
+ else{
+ err_code |= (1 << 4);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+ if((CTRL & 0x9)){
+ CMSDK_TIMER0->CTRL = CTRL;
+ puts("\nTimer Initialisation Successful\n");
+ }
+ else{
+ printf("\n** TEST FAILED ** Timer Initialisation Failed Program Will Now Quit, Error code: (0x%x)\n", err_code);
+ return err_code;
+ }
+
+ if(!err_code) return 0;
+ else return 1;
+}
+/* Interrupt test */
+int Timer_IRQ(void)
+{
+ int counter = 0; /* Loop counter */
+ int err_code = 0; /* Variable to record errors */
+ uint32_t CTRL = 0; /* Variable to hold read back CTRL value */
+ uint32_t RELOAD = 0; /* Variable to hold updated RELOAD value */
+
+ timer_irq_counter = 0; /* Set timer interrupt variables to 0 */
+ timer_irq_executed = 0;
+
+ puts("Stage 2 - interrupt\n");
+
+ // For robustness, disable the timer, clear the IRQ in case it's set, then
+ // clear the current value to zero, and then enable again; this should ensure
+ // that operation of this test part starts from a stable point
+ //
+ // Also set the reload value to 0x1f00 to allow the test more time to execute
+ // the test loop, and increment the loop counter sufficiently quickly in
+ // relation to the timer to allow all aspects of this test part to be
+ // executed
+ CMSDK_timer_StopTimer (CMSDK_TIMER0);
+ CMSDK_timer_ClearIRQ (CMSDK_TIMER0);
+ CMSDK_timer_SetValue (CMSDK_TIMER0, 0x0);
+ CMSDK_timer_SetReload (CMSDK_TIMER0, 0x1f00);
+ // Now start the timer before the test sequence
+ CMSDK_timer_StartTimer(CMSDK_TIMER0);
+
+ /* Stage 2 Test sequence
+ - timer enabled by CMSDK_timer_Init_IntClock, with interrupt enabled
+ - first interrupt triggered
+ - after first IRQ, timer interrupt is disabled
+ - after loop executed 5 times, reload value is reprogrammed to double the value
+ - after a while, second interrupt taken place
+ - after second IRQ, timer interrupt is disabled
+ - the loop is executed to 10th time (or multiple of 10), timer interrupt is re-enabled
+ (multiple of 10 is used to prevent the test from getting stuck.
+ Due to timing dependency nature of this test, the test sequence could be different
+ from expected when there are wait states in the memory system.)
+ - after a while, third interrupt taken place
+ - the timer is stopped inside the timer interrupt handler
+ - the loop is exited
+ */
+
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_EnableIRQ(TIMER0_IRQn);
+ while (timer_irq_counter < 3) /* Wait until IRQ take place 3 times*/
+ {
+ if (timer_irq_executed!=0) /* This part is executed each time a timer interrupt is detected */
+ {
+ puts ("Timer IRQ\n");
+ printf("Timer Status: %u\n", timer_irq_executed);
+ CMSDK_timer_DisableIRQ(CMSDK_TIMER0);
+ puts("Timer IRQ Disabled");
+ timer_irq_executed=0; /* clear variable so that this part is not executed until next timer interrupt */
+ }
+
+ printf("Timer Status: %u\n", CMSDK_timer_StatusIRQ(CMSDK_TIMER0));
+
+ counter++; /* loop counter increment */
+
+ if (counter == 5) /* after loop executed 5 times, reload value is reprogrammed to double the value */
+ {
+ printf("Timer Value: %u\n", CMSDK_timer_GetValue(CMSDK_TIMER0));
+ printf("Timer Reload Value: %u\n",CMSDK_timer_GetReload(CMSDK_TIMER0));
+ CMSDK_timer_SetReload(CMSDK_TIMER0, (RELOAD = 2*CMSDK_timer_GetReload(CMSDK_TIMER0)));
+ /*test other timer functions including set reload and set value*/
+ printf("Timer Reload Value now set to: %u\n",CMSDK_timer_GetReload(CMSDK_TIMER0));
+
+ if(RELOAD == CMSDK_timer_GetReload(CMSDK_TIMER0)) {
+ puts("Timer Reload Value Is Correct"); /*check for reload value */
+ }
+ else{
+ err_code = (1 << 0);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ break;
+ }
+
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_SetValue(CMSDK_TIMER0, 0x12C); /*set to 300 to test instant underflow*/
+
+ if(0x12C == CMSDK_timer_GetValue(CMSDK_TIMER0)) {
+ puts("Timer Value Set to 300"); /*check for reload value */
+ }
+ else{
+ err_code = (1 << 1);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ break;
+ }
+ CMSDK_timer_StartTimer(CMSDK_TIMER0);
+ CMSDK_timer_EnableIRQ(CMSDK_TIMER0);
+ }
+ if ((counter % 10) == 0) /* the loop is executed to 10th time (or multiple of 10), timer interrupt is re-enabled */
+ {
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ CMSDK_timer_EnableIRQ(CMSDK_TIMER0);
+ CTRL = CMSDK_TIMER0->CTRL; /* Check timer interrupt is enabled */
+ if((CTRL & CMSDK_TIMER_CTRL_IRQEN_Msk) != 0) {
+ puts("Timer IRQ enabled");
+ }
+ else{
+ err_code |= (1 << 2);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ break;
+ }
+ CMSDK_timer_StartTimer(CMSDK_TIMER0);
+ }
+ }
+
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ /*read back of control register to make sure value is expected */
+
+ if((CMSDK_TIMER0->CTRL & CMSDK_TIMER_CTRL_EN_Msk) == 0) {
+ puts("\nTimer Stopped");
+ }
+ else{
+ err_code = (1 << 3);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+
+ if(!err_code) {
+ puts("** Timer IRQ Test Passed **\n");
+ }
+ else printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+
+ if(!err_code) return 0;
+ else return 2;
+}
+/* Timer polling test */
+int Timer_Poll(void)
+{
+ int err_code = 0; /* Variable to record errors */
+ int Reload = 0; /* Read back value of reload */
+
+ /* Stage 3 Test sequence
+ - timer interrupt is disabled at NVIC
+ - timer is started
+ - each time the timer interrupt status register is set (timer overflow),
+ the counter variable (timer_irq_counter) increments and the interrupt status is cleared.
+ - the loop is executed three times
+ */
+ printf ("\nStage 3 - Polling\n\n");
+
+ NVIC_DisableIRQ(TIMER0_IRQn); /*disable IRQ ready to test polling*/
+ // Also enable the Timer IRQ since the test relies on reading the IRQ status
+ // as non-zero to progress - should be enabled by the previous part, but the
+ // behaviour of that part could be different if there are wait-states in the
+ // memory system, and hence it could leave the Timer IRQ disabled
+ CMSDK_timer_EnableIRQ(CMSDK_TIMER0);
+ CMSDK_timer_SetReload(CMSDK_TIMER0,0xF00); /*reload timer and start it*/
+
+ Reload = CMSDK_timer_GetReload(CMSDK_TIMER0);
+
+ if(Reload == 0xF00) {
+ puts("Timer Reload Initialised as 0xF00"); /*check for reload value */
+ }
+ else{
+ err_code = (1 << 0);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+
+ CMSDK_timer_StartTimer(CMSDK_TIMER0);
+
+ timer_irq_counter = 0; /* irq counter is re-used for this test although polling is used */
+
+ do {
+ printf("Timer Status: %u\n", CMSDK_timer_StatusIRQ(CMSDK_TIMER0));
+
+ while (CMSDK_timer_StatusIRQ(CMSDK_TIMER0) == 0); /*wait until timer underflow*/
+ printf("Timer Status: %u\n", CMSDK_timer_StatusIRQ(CMSDK_TIMER0));
+
+ CMSDK_timer_ClearIRQ(CMSDK_TIMER0); /*Test Timer status function 3 times by polling for interrupt*/
+ timer_irq_counter ++; /*status then clearing the IRQ and repeating until 3
+ interrupt requests have occurred*/
+
+ } while (timer_irq_counter<3);
+
+ CMSDK_timer_StopTimer(CMSDK_TIMER0); /*read back of control register to make sure value is expected */
+
+ if((CMSDK_TIMER0->CTRL & CMSDK_TIMER_CTRL_EN_Msk) == 0) {
+ puts("\nTimer Stopped");
+ }
+ else{
+ err_code = (1 << 1);
+ printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+ }
+
+ if(!err_code) puts("** Timer Polling Test Passed\n");
+ else printf("** TEST FAILED **, Error code: (0x%x)\n", err_code);
+
+ if(!err_code) return 0;
+ else return 4;
+}
+
+int Timer_Ext(void){
+
+ int test_disabled = 0; /* variable for stage 4b:to count tests carried out when timer is disabled by external input*/
+ int test_enabled = 0; /* variable for stage 4b:to count tests carried out when timer is enabled by external input*/
+ int test_error = 0; /* variable for stage 4b:to check the test error result */
+ int enabled = 0; /* variable for stage 4b:to handle test_disabled and test_enabled variable */
+ int counter = 0; /* loop counter */
+
+ puts ("\nStage 4 - Ext Stimuli\n");
+
+ /* Stage 4a Test sequence
+ - timer is configured to running with external clock
+ - timer is started
+ - each time the timer interrupt status register is set (timer overflow),
+ the counter variable (timer_irq_counter) increments and the interrupt status is cleared.
+ - the loop is executed to toggle the external clock input until timer interrupt triggers three times
+ */
+
+ puts ("\n -Stage 4a - Ext Clock\n");
+
+ timer_irq_counter = 0;
+
+ NVIC_ClearPendingIRQ(TIMER0_IRQn); /*Clear pending IRQs before test started*/
+ NVIC_EnableIRQ(TIMER0_IRQn); /*enable IRQs*/
+ CMSDK_GPIO1->DATAOUT = 0x000; /*Set external clock input to 0 at start of test*/
+ CMSDK_gpio_SetOutEnable(CMSDK_GPIO1, 0x100); /*set pin 8 as output so that it can be used as an external clock*/
+ CMSDK_timer_Init_ExtClock(CMSDK_TIMER0, 0x100, 1);/*setup timer to use external clock*/
+
+
+ while(timer_irq_counter < 3)
+ {
+ CMSDK_GPIO1->DATAOUT = 0x100; /*creates square wave on pin 8 to be used as the external clock*/
+ __ISB();
+ CMSDK_GPIO1->DATAOUT = 0x000;
+ if (timer_irq_executed != 0)
+ {
+ puts ("Timer IRQ");
+ timer_irq_executed = 0;
+ }
+ }
+
+ puts ("\n -Stage 4b - Ext Enable\n");
+
+ /* Stage 4b Test sequence
+ - Timer is configured to running with external enable
+ - Timer is enabled using ext input
+ - The external enable input is toggled for every iteration of the loop
+ to disable/enable the timer for the next iterations
+ - if the timer is enabled and the value of the timer is not the same as the previous value,
+ enable timer test is classed as passed.
+ - if the timer is disabled and the value of the timer is the same as the previous value
+ then the disable timer test is classed as passed.
+ - this process is repeated within one timer overflow and if neither any of the enable timer or disable timer
+ tests ever fail then the test as a whole (Stage 4b) passes.
+ */
+
+ timer_irq_executed = 0;
+ timer_irq_counter = 0;
+ counter = 0; /*counter used to count the external enable input toggle times*/
+
+ enabled = 1; /* used to indicate whether the timer is enabled or disabled (if enabled is even,
+ timer disabled, if enabled is odd, timer enabled) */
+
+ CMSDK_timer_Init_ExtEnable(CMSDK_TIMER0, 0xF00, 1); /*setup timer so that it uses an external enable*/
+ CMSDK_GPIO1->DATAOUT = 0x100; /*set pin 8 (external enable) high so as to enable the timer*/
+
+ puts ("Timer 0 Enabled\n");
+
+ while(timer_irq_counter < 1) /* this test only execute within one timer overflow so that when timer is enabled
+ the sampled timer values are always different*/
+ {
+ CMSDK_GPIO1->DATAOUT ^= 0x100;
+ /* XOR output port with 0x100 so as to invert the external enable signal*/
+ enabled++;
+ temp_test = CMSDK_timer_GetValue(CMSDK_TIMER0);
+ /*record the timer value so that it can be tested whether or not the timer has actually been disabled or not*/
+
+ if((enabled % 2) == 0) //if timer is disabled i.e. enabled is even, increment the test_disabled counter
+ {
+ test_disabled = 1;
+ }
+ else //
+ {
+ test_enabled = 1;
+ }
+
+ if((test_disabled == 1) && (test_enabled == 0))
+ /*Disable pass condition - only pass if value doesn't change*/
+ {
+ test_disabled = 0;
+ if(temp_test == CMSDK_timer_GetValue(CMSDK_TIMER0))
+ /*if the value of the sampled value is the same as the current timer value,
+ then it can be inferred that the timer is disabled*/
+ {
+ puts("Disable Test Passed");
+ }
+ else
+ {
+ puts("** TEST FAILED ** Disable Test");
+ test_error++;
+ }
+ }
+ else if((test_enabled ==1) && (test_disabled == 0))
+ /*Enable pass condition - only pass if value is different*/
+ {
+ test_enabled = 0;
+ if (temp_test != CMSDK_timer_GetValue(CMSDK_TIMER0))
+ /*if the value of the sampled value is different from the current then
+ it can be inferred that the timer is enabled*/
+ {
+ puts("Enable Test Passed");
+ }
+ else
+ {
+ puts("** TEST FAILED ** Enable Test");
+ test_error++;
+ }
+ }
+
+ counter++; //Enable Toggle counter
+
+ }
+
+ printf("\nTimer enable/disable toggled %d times\n", counter);
+ if(test_error == 0)
+ {
+ puts("\nExt Stimuli Tests Completed Successfully\n");
+ return 0;
+ }
+ else
+ {
+ printf("\n** TEST FAILED **, Error code: (0x%x)", test_error);
+ return 8;
+ }
+}
+
+void TIMER0_Handler(void) /*Timer ISR*/
+{
+ timer_irq_counter++;
+ timer_irq_executed=1;
+ if (timer_irq_counter>=3) {
+ CMSDK_timer_StopTimer(CMSDK_TIMER0);
+ }
+ CMSDK_timer_ClearIRQ(CMSDK_TIMER0);
+ return;
+}
+
+// ----------------------------------------------------------
+// Peripheral detection
+// ----------------------------------------------------------
+/* Detect the ARM ID and the part number to see if device is present */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+int timer0_id_check(void)
+{
+unsigned char timer_id;
+ timer_id = HW8_REG(CMSDK_TIMER0_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_TIMER0_BASE + 0xFE0) != 0x22) ||
+ (HW32_REG(CMSDK_TIMER0_BASE + 0xFE4) != 0xB8) ||
+ (timer_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+
+int gpio1_id_check(void)
+{
+unsigned char gpio_id;
+ gpio_id = HW8_REG(CMSDK_GPIO1_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_GPIO1_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO1_BASE + 0xFE4) != 0xB8) ||
+ (gpio_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
diff --git a/Cortex-M0/nanosoc/software/common/validation/timer_tests.c b/Cortex-M0/nanosoc/software/common/validation/timer_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0aa90250263fda449d68501ccc48e4dc2d8819e
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/timer_tests.c
@@ -0,0 +1,824 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the functionalities of APB timer
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+int timer_register_rw_test(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+int timer_start_stop_test(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+int timer_interrupt_test_1(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+int timer_external_input(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
+int timer0_id_check(void); // Detect Timer 0 present
+int timer1_id_check(void); // Detect Timer 1 present
+int gpio1_id_check(void); // Detect GPIO 1 present
+
+/* Global variables */
+volatile int timer0_irq_occurred;
+volatile int timer1_irq_occurred;
+volatile int timer0_irq_expected;
+volatile int timer1_irq_expected;
+volatile int counter;
+
+/* peripheral and component ID values */
+#define APB_TIMER_PID4 0x04
+#define APB_TIMER_PID5 0x00
+#define APB_TIMER_PID6 0x00
+#define APB_TIMER_PID7 0x00
+#define APB_TIMER_PID0 0x22
+#define APB_TIMER_PID1 0xB8
+#define APB_TIMER_PID2 0x1B
+#define APB_TIMER_PID3 0x00
+#define APB_TIMER_CID0 0x0D
+#define APB_TIMER_CID1 0xF0
+#define APB_TIMER_CID2 0x05
+#define APB_TIMER_CID3 0xB1
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+int main (void)
+{
+ int result=0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - Timer Test - revision $Revision: 371321 $\n");
+
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+ timer0_irq_expected = 0;
+ timer1_irq_expected = 0;
+
+ puts("1) Timer 0");
+
+ if (timer0_id_check()==0) { /* Detect if timer is available */
+ /* Timer 0 present */
+ result += timer_register_rw_test(CMSDK_TIMER0);
+ result += timer_start_stop_test(CMSDK_TIMER0);
+ result += timer_interrupt_test_1(CMSDK_TIMER0);
+
+ if (gpio1_id_check()==0) {
+ /* External input test need GPIO 1 to generate input */
+ result += timer_external_input(CMSDK_TIMER0);
+ } else {
+ puts ("- GPIO #1 not present. Test skipped.");
+ }
+
+ } else {
+ puts ("- Timer #0 not present. Tests skipped.");
+ }
+
+
+ puts("\n2) Timer 1");
+
+ if (timer1_id_check()==0) { /* Detect if timer is available */
+ /* Timer 1 present */
+ result += timer_register_rw_test(CMSDK_TIMER1);
+ result += timer_start_stop_test(CMSDK_TIMER1);
+ result += timer_interrupt_test_1(CMSDK_TIMER1);
+ if (gpio1_id_check()==0) {
+ /* External input test need GPIO 1 to generate input */
+ result += timer_external_input(CMSDK_TIMER1);
+ } else {
+ puts ("- GPIO #1 not present. Test skipped.");
+ }
+ } else {
+ puts ("- Timer #1 not present. Tests skipped.");
+ }
+
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **\n, Error code = (0x%x)", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+/* --------------------------------------------------------------- */
+/* Timer register read/write tests */
+/* --------------------------------------------------------------- */
+
+int timer_register_rw_test(CMSDK_TIMER_TypeDef *CMSDK_TIMER){
+ int return_val=0;
+ int err_code=0;
+ unsigned int timer_base;
+ puts("Timer R/W test");
+ puts("- initial values");
+
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ NVIC_DisableIRQ(TIMER1_IRQn);
+
+ if (CMSDK_TIMER->CTRL != 0) { err_code += (1<<0); }
+ if (CMSDK_TIMER->VALUE != 0) { err_code += (1<<1); }
+ if (CMSDK_TIMER->RELOAD != 0) { err_code += (1<<2); }
+ if (CMSDK_TIMER->INTSTATUS != 0) { err_code += (1<<3); }
+
+ timer_base = CMSDK_TIMER0_BASE;
+ if (CMSDK_TIMER==CMSDK_TIMER1) {timer_base = CMSDK_TIMER1_BASE;}
+
+ // Perform a write access to all PIDs
+ HW32_REG(timer_base + 0xFD0) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFD4) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFD8) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFDC) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFE0) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFE4) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFE8) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFEC) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFF0) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFF4) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFF8) = 0xFFFFFFFF;
+ HW32_REG(timer_base + 0xFFC) = 0xFFFFFFFF;
+
+ if (HW32_REG(timer_base + 0xFD0) != APB_TIMER_PID4) {err_code += (1<<4); }
+ if (HW32_REG(timer_base + 0xFD4) != APB_TIMER_PID5) {err_code += (1<<5); }
+ if (HW32_REG(timer_base + 0xFD8) != APB_TIMER_PID6) {err_code += (1<<6); }
+ if (HW32_REG(timer_base + 0xFDC) != APB_TIMER_PID7) {err_code += (1<<7); }
+ if (HW32_REG(timer_base + 0xFE0) != APB_TIMER_PID0) {err_code += (1<<8); }
+ if (HW32_REG(timer_base + 0xFE4) != APB_TIMER_PID1) {err_code += (1<<9); }
+ if (HW32_REG(timer_base + 0xFE8) != APB_TIMER_PID2) {err_code += (1<<10); }
+ if (HW32_REG(timer_base + 0xFEC) != APB_TIMER_PID3) {err_code += (1<<11); }
+ if (HW32_REG(timer_base + 0xFF0) != APB_TIMER_CID0) {err_code += (1<<12); }
+ if (HW32_REG(timer_base + 0xFF4) != APB_TIMER_CID1) {err_code += (1<<13); }
+ if (HW32_REG(timer_base + 0xFF8) != APB_TIMER_CID2) {err_code += (1<<14); }
+ if (HW32_REG(timer_base + 0xFFC) != APB_TIMER_CID3) {err_code += (1<<15); }
+
+
+ if (err_code != 0) {
+ printf ("ERROR : initial value failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+ puts("- read/write");
+
+ CMSDK_TIMER->VALUE = 0x3355AAFF;
+ if (CMSDK_TIMER->VALUE != 0x3355AAFF) { err_code += (1<<0); }
+ CMSDK_TIMER->VALUE = 0xCCAA5500;
+ if (CMSDK_TIMER->VALUE != 0xCCAA5500) { err_code += (1<<1); }
+ CMSDK_TIMER->VALUE = 0x00000000;
+ if (CMSDK_TIMER->VALUE != 0x00000000) { err_code += (1<<2); }
+
+ CMSDK_TIMER->RELOAD = 0x3355AAFF;
+ if (CMSDK_TIMER->RELOAD != 0x3355AAFF) { err_code += (1<<3); }
+ CMSDK_TIMER->RELOAD = 0xCCAA5500;
+ if (CMSDK_TIMER->RELOAD != 0xCCAA5500) { err_code += (1<<4); }
+ CMSDK_TIMER->RELOAD = 0x00000000;
+ if (CMSDK_TIMER->RELOAD != 0x00000000) { err_code += (1<<5); }
+
+ CMSDK_TIMER->CTRL = 0x01; /* Set enable */
+ if (CMSDK_TIMER->CTRL != 0x01) { err_code += (1<<6); }
+ CMSDK_TIMER->CTRL = 0x02; /* external select */
+ if (CMSDK_TIMER->CTRL != 0x02) { err_code += (1<<7); }
+ CMSDK_TIMER->CTRL = 0x04; /* external clock select */
+ if (CMSDK_TIMER->CTRL != 0x04) { err_code += (1<<8); }
+ CMSDK_TIMER->CTRL = 0x08; /* external clock select */
+ if (CMSDK_TIMER->CTRL != 0x08) { err_code += (1<<9); }
+ CMSDK_TIMER->CTRL = 0x00; /* all clear */
+ if (CMSDK_TIMER->CTRL != 0x00) { err_code += (1<<10); }
+
+ /* Trigger timer interrupt status */
+ CMSDK_TIMER->RELOAD = 0x3;
+ CMSDK_TIMER->VALUE = 0x3;
+ CMSDK_TIMER->CTRL = 0x9; /* enable with internal clock as source */
+ while ( CMSDK_TIMER->INTSTATUS == 0);
+ CMSDK_TIMER->CTRL = 0x0; /* disable timer */
+ if (CMSDK_TIMER->INTSTATUS != 0x01) { err_code += (1<<11); }
+ CMSDK_TIMER->INTCLEAR = 0x1; /* clear timer interrupt */
+ if (CMSDK_TIMER->INTSTATUS != 0x00) { err_code += (1<<12); }
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Read/write failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_ClearPendingIRQ(TIMER1_IRQn);
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* Timer start/stop tests */
+/* --------------------------------------------------------------- */
+/*
+ Timer value set to 0x1000, and enabled.
+ A polling loop is then use to check that timer had decremented to 0x900
+ within a certain period of time. A software variable called counter to
+ used to detect timeout, which make sure that the test report fail
+ if the timer does not decrement.
+
+ The timer is then stopped, and the value is sampled twice and checked
+ that the timer is really stopped.
+
+ The timer value is then set to 0x10, and then enabled, with interrupt feature
+ enabled (Note : NVIC is not enabled for this test so interrupt doesn't get
+ triggered).
+ A polling loop is then use to wait until timer reach zero and reloaded
+ (by checking interrupt status register). The current value of the timer
+ is then checked to make sure it is in the expected value range.
+
+*/
+int timer_start_stop_test(CMSDK_TIMER_TypeDef *CMSDK_TIMER){
+ int return_val=0;
+ int err_code=0;
+ unsigned long tvalue;
+ puts("Timer start/stop test");
+ puts("- timer enable");
+
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ NVIC_DisableIRQ(TIMER1_IRQn);
+
+ CMSDK_TIMER->RELOAD = 0x1000;
+ CMSDK_TIMER->VALUE = 0x1000;
+ CMSDK_TIMER->CTRL = 0x01; /* Set enable */
+ counter = 0x100; /* Time out counter */
+ while ((CMSDK_TIMER->VALUE > 0x900) && (counter>= 0)){
+ counter --;
+ }
+ CMSDK_TIMER->CTRL = 0x00; /* stop timer for now */
+ if (CMSDK_TIMER->VALUE > 0x900) {
+ puts("ERROR : Timer not decrementing.");
+ err_code += (1<<0);
+ }
+
+ tvalue = CMSDK_TIMER->VALUE;
+ puts("- timer disable");
+ __NOP();
+ __NOP();
+ if (CMSDK_TIMER->VALUE != tvalue) {
+ puts("ERROR : Timer not stopping.");
+ err_code += (1<<1);
+ }
+
+ /* Check reload operation */
+ puts("- timer reload");
+ CMSDK_TIMER->VALUE = 0x10;
+ CMSDK_TIMER->CTRL = 0x09; /* Set enable, and interrupt generation */
+ while ( CMSDK_TIMER->INTSTATUS == 0);
+ CMSDK_TIMER->CTRL = 0x00; /* Stop timer */
+ if (CMSDK_TIMER->VALUE > CMSDK_TIMER->RELOAD) {
+ puts("ERROR : Timer reload fail 1.");
+ err_code += (1<<2);
+ }
+ if ( (CMSDK_TIMER->RELOAD - CMSDK_TIMER->VALUE) > 0x100 ) {
+ puts("ERROR : Timer reload fail 2.");
+ err_code += (1<<3);
+ }
+
+ // Need to lower the interrupt in the timer before clearing in the NVIC
+ CMSDK_TIMER->INTCLEAR = 1;
+ // Clear the NVIC interrupts related to both timers to save working out which
+ // timer is currently being tested
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_ClearPendingIRQ(TIMER1_IRQn);
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : start/stop failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* Timer interrupt test 1 */
+/* --------------------------------------------------------------- */
+/*
+ Interrupt enable:
+ Timer is enabled, with reload value set to 0x7F (128 cycles),
+ and timer interrupt is enabled.
+ check that timer interrupt has take place as least twice
+ when counter (software variable) is increased from 0 to 0x300.
+ If counter is > 0x300 but less than two timer interrupt is received
+ (timerx_irq_occurred < 2), then flag it as time out error.
+
+ Interrupt disable:
+ Timer is enabled, with reload value set to 0x1F (32 cycles),
+ and timer interrupt is disabled.
+ The counter (software variable) is increased from 0 to 0x100.
+ Check that timer interrupt did not take place.
+ (timer0_irq_occurred and timer1_irq_occurred are 0).
+
+*/
+int timer_interrupt_test_1(CMSDK_TIMER_TypeDef *CMSDK_TIMER){
+ int return_val=0;
+ int err_code=0;
+
+ puts ("Timer interrupt test");
+ puts ("- Test interrupt generation enabled.");
+ CMSDK_TIMER->VALUE = 0; /* Disable timer */
+
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ NVIC_DisableIRQ(TIMER1_IRQn);
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_ClearPendingIRQ(TIMER1_IRQn);
+
+ /* Check which timer is being tested and setup software flags */
+ if (CMSDK_TIMER==CMSDK_TIMER0) {
+ timer0_irq_expected = 1;
+ timer1_irq_expected = 0;
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+
+ NVIC_EnableIRQ(TIMER0_IRQn); /* Enable Timer Interrupt */
+
+ }
+
+ if (CMSDK_TIMER==CMSDK_TIMER1) {
+ timer0_irq_expected = 0;
+ timer1_irq_expected = 1;
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+
+ NVIC_EnableIRQ(TIMER1_IRQn); /* Enable Timer Interrupt */
+
+ }
+
+
+ CMSDK_TIMER->RELOAD = 0x01FF;
+ CMSDK_TIMER->VALUE = 0x01FF;
+ CMSDK_TIMER->CTRL = 0x0009; /* Timer enabled */
+ counter = 0;
+ if (CMSDK_TIMER==CMSDK_TIMER0) {
+ while (( timer0_irq_occurred < 2) && (counter < 0x300)){
+ counter ++;
+ };
+ CMSDK_TIMER->CTRL = 0x0000; /* Stop Timer */
+ }
+
+ if (CMSDK_TIMER==CMSDK_TIMER1) {
+ while (( timer1_irq_occurred < 2) && (counter < 0x300)){
+ counter ++;
+ };
+ CMSDK_TIMER->CTRL = 0x0000; /* Stop Timer */
+ }
+ /* Check timeout has not occurred */
+ if (counter >= 0x300) {
+ puts("ERROR : Timer interrupt enable fail.");
+ err_code += (1<<0);
+ }
+ counter = 0;
+
+ puts ("- Test interrupt generation disabled.");
+ timer0_irq_expected = 0;
+ timer1_irq_expected = 0;
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+
+ CMSDK_TIMER->RELOAD = 0x001F;
+ CMSDK_TIMER->VALUE = 0x001F;
+ CMSDK_TIMER->CTRL = 0x0001; /* Timer enabled, with interrupt generation disabled */
+ counter = 0;
+ while ((counter<0x100) && (timer0_irq_occurred==0) && (timer1_irq_occurred==0)) {
+ counter++;
+ }
+ CMSDK_TIMER->CTRL = 0x0000; /* Stop Timer */
+ if ((timer0_irq_occurred!=0) || (timer1_irq_occurred!=0)) {
+ puts("ERROR : Timer interrupt disable fail.");
+ err_code += (1<<1);
+ }
+ counter = 0;
+
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ NVIC_DisableIRQ(TIMER1_IRQn);
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Interrupt test failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* Timer extin test 1 */
+/* --------------------------------------------------------------- */
+/* External input :
+ TIMER 0 - GPIO #1 [bit 8]
+ TIMER 1 - GPIO #1 [bit 9]
+
+ Checking of external input as enable:
+ Timer is programmed so that it use external input as enable.
+ The external input is set to 0 (disabled), and the timer value is sample twice
+ to make sure it is not decrementing.
+
+ The program then set the timer current value to 99, and then use the
+ SysTick timer to generate a pulse of 100 cycles on the timer
+ external input. This is done by
+ - setting up the SysTick to be triggered at every 100 cycles,
+ - the first timer SysTick interrupt is triggered, set ext input to 1
+ - the second timer SysTick interrupt is triggered, set ext input to 0, and disable SysTick
+ After the SysTick exception is entered twice, it then check if the timer has underflowed.
+ (check current value range between 0xFF to 0xA0).
+
+ Since the timer could be running at a divided APB clock speed which is half of the AHB,
+ the value check might fail in such configuration. If the current counter value is between
+ 30 and 60, generate another pulse of 100 clocks cycle to the external input and do the
+ check again.
+
+ It then check the timer interrupt status, and the clearing of the interrupt status.
+
+ ------------------------------------
+ Checking of external input as clock:
+ The test then program the timer to use external input as "clock" (rising edge detection).
+ Timer starting value is set to 0xC0.
+ It first keep the external input as 0, and check that the timer current value hasn't been
+ changed.
+
+ It then change the external input to 1, and check if the timer has decrement. (value = 0xBF)
+
+ It then wait for a short period (counter variable decrement from 10 to 0),
+ then check that the timer has not been decremented further.(value = 0xBF)
+
+ It then set external input to 0, again, wait for short period of time,
+ and check that the timer has not been decremented further.(value = 0xBF)
+
+ It then generate 15 pulses on the external input, and check the timer has decrement
+ 15 times. (value = 0xB0) It also check that at this stage the timer interrupt status
+ should still be 0.
+
+ It then set the timer value to 2, with interrupt generation enabled, use external input
+ as clock. The external input is then switched from 0 to 1, (value changed from 2 to 1)
+ and the timer interrupt shouldn't be triggered. (it should only trigger at 1 to 0 value
+ change).
+
+ It then generate another pulse at the external input, and wait for a short period.
+ This time the timer interrupt should be triggered.
+
+ it then clear up the interrupt settings and report test status.
+
+*/
+int timer_external_input(CMSDK_TIMER_TypeDef *CMSDK_TIMER){
+ int return_val=0;
+ int err_code=0;
+ unsigned long tvalue;
+ uint32_t timer_value;
+
+ puts ("Timer external input test");
+ /* Set external inputs low */
+ CMSDK_GPIO1->OUTENABLESET = (1<<8) | (1<<9);
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000;
+
+ CMSDK_TIMER->RELOAD = 0x00FF;
+ CMSDK_TIMER->VALUE = 0x00FF;
+ CMSDK_TIMER->CTRL = 0x000B; /* Timer enabled, use external input, interrupt enabled */
+
+ tvalue = CMSDK_TIMER->VALUE;
+ puts("- timer use ext. input");
+ __NOP(); /* Some delay is needed due to double flip-flop synchronization logic */
+ __NOP();
+ if (CMSDK_TIMER->VALUE != tvalue) {
+ puts("ERROR : Timer not stopping when external input is low.");
+ err_code += (1<<0);
+ }
+
+ puts("- use SysTick to generate ext. input pulse");
+ CMSDK_TIMER->VALUE = 0xFE; /* Use 0xFE so that it count to 0 */
+ counter = 0;
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ NVIC_DisableIRQ(TIMER1_IRQn);
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_ClearPendingIRQ(TIMER1_IRQn);
+
+ /* Create a pulse of approximately four times the length of the expected
+ * duration that the system timer will be counting down.
+ * APB is possibly running at half speed, but this should be allowed for by
+ * the fact that the SysTick reload value is set to a larger value than the
+ * system timer start value. This therefore should allow the system timer to
+ * count round multiple times, and should have the expected outcome
+ * regardless of whether APB is running at full speed or half speed
+ */
+ SysTick->LOAD = (0x100<<2)-1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = 0x7; /* Enable, use internal clock, interrupt enable */
+
+ while (counter < 2); /* SysTick handler trigger twice */
+
+ /* Timer should be reloaded, expected value between 0xA0 to 0xFF (reload value) */
+ timer_value = CMSDK_TIMER->VALUE;
+ if ((timer_value > 0xFF) || (timer_value < 0xA0)) {
+ printf("ERROR : Timer not running when external input is high (0x%x).\n", timer_value);
+ err_code += (1<<1);
+ }
+
+ /* Timer interrupt should be pending */
+ if (((NVIC_GetPendingIRQ(TIMER0_IRQn)==0)&&(CMSDK_TIMER==CMSDK_TIMER0))||
+ ((NVIC_GetPendingIRQ(TIMER1_IRQn)==0)&&(CMSDK_TIMER==CMSDK_TIMER1)))
+ {
+ puts("ERROR : Timer not trigger #1.");
+ err_code += (1<<2);
+ }
+
+ if (CMSDK_TIMER->INTSTATUS==0) {
+ puts("ERROR : Timer not trigger #2.");
+ err_code += (1<<3);
+ }
+ else {
+ CMSDK_TIMER->INTCLEAR=1; /* Clear interrupt status */
+ if (CMSDK_TIMER->INTSTATUS!=0) {
+ puts("ERROR : Timer not clear.");
+ err_code += (1<<4);
+ }
+ }
+
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_ClearPendingIRQ(TIMER1_IRQn);
+
+
+ puts("- use EXTIN as clock");
+ CMSDK_TIMER->VALUE = 0xC0;
+ CMSDK_TIMER->CTRL = 0x0007; /* Timer enabled, use external input as clock, interrupt disabled */
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000;
+ counter = 10; /* delay */
+ while (counter > 0) {
+ counter --;
+ }
+ if (CMSDK_TIMER->VALUE != 0xC0) {
+ puts("ERROR : Timer change unexpectedly 1.");
+ err_code += (1<<5);
+ }
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0300; /* Timer should decrement */
+ __ISB();
+ __ISB();
+
+ if (CMSDK_TIMER->VALUE != 0xBF) {
+ puts("ERROR : Timer decrement failed.");
+ err_code += (1<<6);
+ }
+ counter = 10; /* delay */
+ while (counter > 0) {
+ counter --;
+ }
+ if (CMSDK_TIMER->VALUE != 0xBF) {
+ puts("ERROR : Timer change unexpectedly 2.");
+ err_code += (1<<7);
+ }
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000; /* Timer should NOT decrement */
+ counter = 10; /* delay */
+ while (counter > 0) {
+ counter --;
+ }
+ if (CMSDK_TIMER->VALUE != 0xBF) {
+ puts("ERROR : Timer change unexpectedly 3.");
+ err_code += (1<<8);
+ }
+ counter = 15;
+ while (counter > 0) {
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0300; /* Timer should decrement */
+ __ISB();
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000; /* Timer should not decrement */
+ counter --;
+ }
+ if (CMSDK_TIMER->VALUE != 0xB0) {
+ puts("ERROR : Timer counting failed");
+ err_code += (1<<9);
+ }
+
+ /* Check interrupt should not be trigger */
+ if ((NVIC_GetPendingIRQ(TIMER0_IRQn)!=0)||(NVIC_GetPendingIRQ(TIMER1_IRQn)!=0)||
+ (CMSDK_TIMER->INTSTATUS!=0))
+ {
+ puts("ERROR : Timer IRQ set unexpectedly.");
+ err_code += (1<<10);
+ }
+
+ puts("- IRQ at 1->0 transition");
+ CMSDK_TIMER->VALUE = 0x02;
+ CMSDK_TIMER->CTRL = 0x000F; /* Timer enabled, use external input as clock, interrupt enabled */
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000;
+
+ timer0_irq_expected = 0;
+ timer1_irq_expected = 0;
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+
+ if (CMSDK_TIMER==CMSDK_TIMER0) {
+ NVIC_EnableIRQ(TIMER0_IRQn);
+ }
+
+ if (CMSDK_TIMER==CMSDK_TIMER1) {
+ NVIC_EnableIRQ(TIMER1_IRQn);
+ }
+
+ /* Test no IRQ generation for 2 to 1 transition */
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0300; /* Timer should decrement */
+ __ISB();
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000; /* Timer should not decrement */
+
+ counter = 10; /* delay */
+ while (counter > 0) {
+ counter --;
+ }
+
+ if (CMSDK_TIMER==CMSDK_TIMER0) {
+ timer0_irq_expected=1;
+ }
+
+ if (CMSDK_TIMER==CMSDK_TIMER1) {
+ timer1_irq_expected=1;
+ }
+
+ /* Test IRQ generation for 1 to 0 transition */
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0300; /* Timer should decrement */
+ __ISB();
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000; /* Timer should not decrement */
+
+ counter = 10; /* delay */
+ while (counter > 0) {
+ counter --;
+ }
+ if (((CMSDK_TIMER==CMSDK_TIMER0)&&(timer0_irq_occurred==0))||
+ ((CMSDK_TIMER==CMSDK_TIMER1)&&(timer1_irq_occurred==0))) {
+ puts("ERROR : Timer not trigger.");
+ err_code += (1<<11);
+ }
+
+ timer0_irq_expected = 0;
+ timer1_irq_expected = 0;
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+
+ /* Test IRQ generation for 0 to RELOAD transition */
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0300; /* Timer should decrement */
+ __ISB();
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000; /* Timer should not decrement */
+
+ counter = 10; /* delay */
+ while (counter > 0) {
+ counter --;
+ }
+ if ((timer0_irq_occurred!=0)||(timer1_irq_occurred!=0)) {
+ puts("ERROR : Timer triggered unexpectedly.");
+ err_code += (1<<12);
+ }
+
+ NVIC_DisableIRQ(TIMER0_IRQn);
+ NVIC_DisableIRQ(TIMER1_IRQn);
+ NVIC_ClearPendingIRQ(TIMER0_IRQn);
+ NVIC_ClearPendingIRQ(TIMER1_IRQn);
+
+ /* Clearing up */
+ SysTick->CTRL = 0x0;
+ CMSDK_TIMER->CTRL = 0x00;/* Disable, use internal clock, interrupt enable */
+ CMSDK_TIMER->RELOAD = 0x0000;
+ CMSDK_TIMER->VALUE = 0x0000;
+ CMSDK_GPIO1->OUTENABLECLR = 0xFFFF;
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000;
+
+ timer0_irq_expected = 0;
+ timer1_irq_expected = 0;
+ timer0_irq_occurred = 0;
+ timer1_irq_occurred = 0;
+
+ /* Generate return value */
+ if (err_code != 0) {
+ printf ("ERROR : Interrupt test failed (0x%x)\n", err_code);
+ return_val=1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* Peripheral detection */
+/* --------------------------------------------------------------- */
+/* Detect the part number to see if device is present */
+int timer0_id_check(void)
+{
+unsigned char timer_id;
+ timer_id = HW8_REG(CMSDK_TIMER0_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_TIMER0_BASE + 0xFE0) != 0x22) ||
+ (HW32_REG(CMSDK_TIMER0_BASE + 0xFE4) != 0xB8) ||
+ (timer_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+
+int timer1_id_check(void)
+{
+unsigned char timer_id;
+ timer_id = HW8_REG(CMSDK_TIMER1_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_TIMER1_BASE + 0xFE0) != 0x22) ||
+ (HW32_REG(CMSDK_TIMER1_BASE + 0xFE4) != 0xB8) ||
+ (timer_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+
+int gpio1_id_check(void)
+{
+unsigned char gpio_id;
+ gpio_id = HW8_REG(CMSDK_GPIO1_BASE + 0xFE8) & 0x07;
+
+ if ((HW32_REG(CMSDK_GPIO1_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO1_BASE + 0xFE4) != 0xB8) ||
+ (gpio_id != 0x03))
+ return 1; /* part ID & ARM ID does not match */
+ else
+ return 0;
+}
+
+/* --------------------------------------------------------------- */
+/* Timer exception handlers */
+/* --------------------------------------------------------------- */
+
+void TIMER0_Handler(void)
+{
+ timer0_irq_occurred ++;
+ CMSDK_TIMER0->INTCLEAR = 1;
+ if (timer0_irq_expected ==0) {
+ puts ("ERROR : Unexpected Timer 0 interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ return;
+}
+
+void TIMER1_Handler(void)
+{
+ timer1_irq_occurred ++;
+ CMSDK_TIMER1->INTCLEAR = 1;
+ if (timer1_irq_expected ==0) {
+ puts ("ERROR : Unexpected Timer 1 interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ return;
+}
+/* --------------------------------------------------------------- */
+/* SysTick exception handlers */
+/* --------------------------------------------------------------- */
+void SysTick_Handler(void)
+{
+ switch (counter) {
+ case 0 :
+ /* Assert the EXTIN to the system timer */
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0300;
+ counter ++;
+ break;
+ case 1 :
+ CMSDK_GPIO1->UB_MASKED[3] = 0x0000;
+ SysTick->CTRL = 0;
+ SCB->ICSR = SCB->ICSR & 0xFDFFFFFF; /* Clear SysTick pending bit */
+ counter ++;
+ break;
+ default:
+ SysTick->CTRL = 0;
+ SCB->ICSR = SCB->ICSR & 0xFDFFFFFF; /* Clear SysTick pending bit */
+ break;
+ }
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/common/validation/uart_driver_tests.c b/Cortex-M0/nanosoc/software/common/validation/uart_driver_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..544f45c28e2021929d2202fb620e38263f26e7b6
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/uart_driver_tests.c
@@ -0,0 +1,408 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the functionalities of UART functions in the example device driver.
+*/
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "string.h"
+#include "uart_stdout.h"
+#include "CMSDK_driver.h"
+
+/* variables shared between interrupt handlers and test program code */
+int volatile uart_txorirq_executed = 0; /* set to 1 if UARTOVF0_Handler (tx overflow) executed */
+int volatile uart_txorirq_counter = 0; /* number of time UARTOVF0_Handler executed */
+int volatile uart_data_received = 0; /* set to 1 if UARTRX1_Handler executed */
+int volatile uart_data_sent = 0; /* set to 1 if UARTTX0_Handler executed */
+int volatile uart_rxorirq_executed = 0; /* set to 1 if UARTOVF1_Handler (rx overflow) executed */
+int volatile uart_rxorirq_counter = 0; /* number of time UARTOVF1_Handler executed */
+
+/* Test Functions declarations */
+int Uart_Init(void); /* Function to test UART initialization */
+int Uart_Buffull(void); /* Function to test UART buffer full */
+int Uart_OR(void); /* Function to test UART overrun */
+int Uart_IRQ(void); /* Function to test UART interrupt */
+int uart0_id_check(void); /* Detect UART 0 present */
+int uart1_id_check(void); /* Detect UART 1 present */
+int gpio1_id_check(void); /* Detect GPIO 1 present */
+
+int main (void)
+{
+ int result = 0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - UART Driver Test - revision $Revision: 371321 $\n");
+
+ if ((uart0_id_check()!=0)||(uart1_id_check()!=0)||(gpio1_id_check()!=0)) {
+ puts("** TEST SKIPPED ** UART 0 / UART 1 / GPIO 1 not available");
+ UartEndSimulation();
+ return 0;}
+
+
+ result |= Uart_Init();
+ result |= Uart_Buffull();
+ result |= Uart_OR();
+ result |= Uart_IRQ();
+
+ if (result == 0) {
+ puts("** TEST PASSED **\n");
+ } else {
+ printf("** TEST FAILED **, Error code: (0x%x)\n", result);
+ }
+
+ UartEndSimulation();
+ return 0;
+}
+
+
+void UARTOVF0_Handler(void) /*UART0 Overrun ISR*/
+{
+if(CMSDK_uart_GetOverrunStatus(CMSDK_UART0) == 1){
+ uart_txorirq_executed = 1; /*set TX Overrun flag*/
+ uart_txorirq_counter++; /*increment TX Overrun counter*/
+ CMSDK_uart_ClearOverrunStatus(CMSDK_UART0); /*clear UART0 Overrun IRQ*/
+ }
+}
+
+void UARTOVF1_Handler(void) /*UART1 Overrun ISR*/
+{
+if(CMSDK_uart_GetOverrunStatus(CMSDK_UART1) == 2){
+ uart_rxorirq_executed = 1; /*set RX Overrun flag*/
+ uart_rxorirq_counter++; /*increment RX Overrun counter*/
+ CMSDK_uart_ClearOverrunStatus(CMSDK_UART1); /*clear UART1 Overrun IRQ*/
+ }
+}
+
+void UARTTX0_Handler(void) /*UART0 TX ISR*/
+{
+ uart_data_sent = 1; /*set data sent flag*/
+ CMSDK_uart_ClearTxIRQ(CMSDK_UART0); /*clear UART0 TX IRQ*/
+}
+
+void UARTRX1_Handler(void) /*UART1 RX ISR*/
+{
+ uart_data_received = 1; /*set data received flag*/
+ CMSDK_uart_ClearRxIRQ(CMSDK_UART1); /*clear UART1 RX IRQ*/
+}
+
+/* Initialize UART and check return status */
+int Uart_Init(void)
+{
+ int err_code = 0;
+
+ puts("\nStage 1 UART Initialization\n"); //initialise UART0 and UART1 with Baud divider of 32
+ //and all interrupts enabled and also tx and rx enabled
+ CMSDK_gpio_SetAltFunc(CMSDK_GPIO1, 0x000F);
+ if(CMSDK_uart_init(CMSDK_UART0, 0x20, 1, 1, 1, 1, 1, 1) == 0)
+ printf("UART0 Initialised Successfully (Baud Divider of: %d)\n", CMSDK_uart_GetBaudDivider(CMSDK_UART0));
+ /* CMSDK_uart_init() returns 1 if the overflow status is non-zero */
+ else
+ {
+ puts("UART0 Initialization Failed\n");
+ err_code = 1;
+ }
+ if(CMSDK_uart_init(CMSDK_UART1, 0x20, 1, 1, 1, 1, 1, 1) == 0)
+ printf("UART1 Initialised Successfully (Baud Divider of: %d)\n", CMSDK_uart_GetBaudDivider(CMSDK_UART1));
+ /* CMSDK_uart_init() returns 1 if the overflow status is non-zero */
+ else
+ {
+ puts("UART1 Initialization Failed\n");
+ err_code |= 2;
+ }
+
+ if(!err_code) return 0;
+ else return 1;
+ }
+
+
+int Uart_Buffull(void) //function for testing the Buffer full functions and simple transmission
+{
+ int err_code = 0;
+ int i, k;
+ char received[12] = {0,0,0,0, 0,0,0,0, 0,0,0,0};
+ char transmit[12] = "hello world";
+
+ puts("\nStage 2 Simple Transmission - TX and RX Test\n");
+
+ i = 0; /* transmit character counter */
+ k = 0; /* receive character counter */
+
+ while((CMSDK_uart_GetTxBufferFull(CMSDK_UART0) == 0)){ //while the TX buffer is not full send it data to transmit
+ CMSDK_UART0->DATA = (uint32_t)transmit[i];
+ i++;
+ }
+
+ if(CMSDK_uart_GetTxBufferFull(CMSDK_UART0)) puts("TX Buffer Full ...restarting transmission");
+ else{
+ err_code = (1 << 0);
+ printf("** TEST FAILED **, Error Code: (0x%x)", err_code);
+ }
+
+ /*receive data from transmission and dispose of it*/
+
+ if(CMSDK_uart_GetRxBufferFull(CMSDK_UART1) == 1) CMSDK_uart_ReceiveChar(CMSDK_UART1);
+ else{
+ err_code = (1 << 1);
+ printf("** TEST FAILED **, Error Code: (0x%x)", err_code);
+ }
+
+ i = 0;
+
+ while(k < 12){ //while received string is not the length of the original string
+
+ if(CMSDK_uart_GetRxBufferFull(CMSDK_UART1) == 1){ //receive data from RX buffer when full
+ received[k] = CMSDK_uart_ReceiveChar(CMSDK_UART1);
+ printf("RX Buffer Full ...receiving data... %c\n", received[k]);
+ k++;
+ }
+
+ /*Send data to TX buffer if the TX buffer is not
+ full and the RX buffer of UART1 is also not full.
+ The receive buffer status is checked because the
+ printf statement in the receive polling takes
+ long time so this code cannot handle maximum
+ throughput */
+
+ if((CMSDK_uart_GetTxBufferFull(CMSDK_UART0) == 0) && (CMSDK_uart_GetRxBufferFull(CMSDK_UART1) != 1)){
+ if(i < 12){
+ CMSDK_UART0->DATA = (uint32_t)transmit[i];
+ i++;
+ }
+ }
+ }
+ printf("\nCharacters received: %s\n", received); //when all characters received print the received string
+
+ if(strcmp(received, transmit)){
+ err_code = 4;
+ puts("** TEST FAILED **, Error : Strings DO Not Match!");
+ }
+
+ if(!err_code) return 0;
+ else return 2;
+}
+
+int Uart_OR(void) /*function to test driver Overrun functions*/
+{
+ int i = 0, TX = 0, RX = 0, err_code = 0;
+ char transmit[12] = "hello world";
+
+ puts("\nStage 3 Polling");
+
+ puts("\n- Stage 3a Overrun Polling\n");
+
+ while(1)
+ {
+ if(i < 4) CMSDK_UART0->DATA = (uint32_t)'a'; //if the loop iteration, the value of i, is less
+ //that 4 then send the TX buffer data to cause a
+ while(i > 10){ //TX overrun if the loop iteration, i, is greater
+ CMSDK_UART0->DATA = (uint32_t)'a'; //than 10 then send the TX buffer to cause another
+ if(CMSDK_uart_GetOverrunStatus(CMSDK_UART0) == 1) break; //TX buffer overrun
+ }
+
+ if(CMSDK_uart_GetOverrunStatus(CMSDK_UART0) == 1){
+ puts("TX Buffer Overrun Occurred");
+ CMSDK_uart_ClearOverrunStatus(CMSDK_UART0);
+ TX = 1;
+ }else if(CMSDK_uart_GetOverrunStatus(CMSDK_UART1) == 2){
+ puts("RX Buffer Overrun Occurred"); //RX buffer overrun will occur as the data
+ CMSDK_uart_ClearOverrunStatus(CMSDK_UART1); //is never read from the RX buffer
+ RX = 1;
+ }
+
+ i++;
+ if(RX & TX) break;
+ }
+
+ puts("\n- Stage 3b TX & RX IRQ Polling\n");
+
+ //clear the TX IRQ status and then print the new status
+ CMSDK_uart_ClearTxIRQ(CMSDK_UART0);
+ printf("TX IRQ Status: %d\n", CMSDK_uart_GetTxIRQStatus(CMSDK_UART0));
+
+ if(CMSDK_uart_GetTxIRQStatus(CMSDK_UART0)) err_code = (1 << 0);
+
+ //clear the RX IRQ status and then print the new status
+ CMSDK_uart_ClearRxIRQ(CMSDK_UART1);
+ printf("RX IRQ Status: %d\n", CMSDK_uart_GetRxIRQStatus(CMSDK_UART1));
+
+ if(CMSDK_uart_GetRxIRQStatus(CMSDK_UART1)) err_code = (1 << 1);
+
+ CMSDK_uart_SendChar(CMSDK_UART0, transmit[1]);
+
+ while(!CMSDK_uart_GetTxIRQStatus(CMSDK_UART0));
+ printf("TX IRQ Status: %d\n", CMSDK_uart_GetTxIRQStatus(CMSDK_UART0)); //send data and wait until the TX IRQ status
+ if(!CMSDK_uart_GetTxIRQStatus(CMSDK_UART0)) err_code = (1 << 2); //is set and then print the new status
+ else CMSDK_uart_ClearTxIRQ(CMSDK_UART0);
+
+
+ while(!CMSDK_uart_GetRxIRQStatus(CMSDK_UART1));
+ printf("RX IRQ Status: %d\n", CMSDK_uart_GetRxIRQStatus(CMSDK_UART1)); //send data and wait until the RX IRQ status
+ if(!CMSDK_uart_GetRxIRQStatus(CMSDK_UART1)) err_code = (1 << 3); //is set and then print the new status
+ else CMSDK_uart_ClearRxIRQ(CMSDK_UART1);
+
+
+
+ if(err_code){
+ printf("** TEST FAILED **, Polling Test Error Code: (0x%x)", err_code);
+ }
+ else puts("Polling Test Passed");
+
+ if(!err_code) return 0;
+ else return 4;
+}
+
+int Uart_IRQ(void){
+
+/*function to test the TX & RX overrun IRQ functions and the TX and RX IRQ driver
+ functions using a simple interrupt orientated send and receive*/
+
+ int i = 0, j = 0; /* i=transmit character counter, j = receive character counter */
+ int err_code = 0;
+ char received[12] = {0,0,0,0, 0,0,0,0, 0,0,0,0};
+ char transmit[12] = "hello world";
+
+ puts("\nStage 4 IRQ\n");
+ puts("- Stage 4a Overrun IRQ\n");
+
+ NVIC_EnableIRQ(UARTOVF0_IRQn); //enable both UART0 and UART1 overflow IRQs
+ NVIC_EnableIRQ(UARTOVF1_IRQn);
+
+ while(uart_txorirq_counter <= 3) //repeat until 3 TX OR IRQs have occurred
+ {
+ if(uart_txorirq_executed){
+ puts("UART TX Overrun IRQ"); //if an TX OR IRQ is performed then this variable is set,
+ uart_txorirq_executed = 0; //uart_txorirq_executed, and this statement will be printed
+ }
+ CMSDK_UART0->DATA = (uint32_t)'a'; //always send data to the TX buffer to cause TX OR and do not
+ if(uart_rxorirq_executed){ //receive data to cause RX OR
+ puts("UART RX Overrun IRQ");
+ uart_rxorirq_executed = 0;
+ }
+ }
+
+ if(uart_rxorirq_counter < 3){
+ err_code = (1 << 0);
+ printf("** TEST FAILED ** UART RX Overrun Error, Error Code: (0x%x)", err_code);
+ }
+ else puts("UART RX Overrun Passed");
+
+ j = 0;
+ uart_data_received = 1; //set uart_data_received to one so that the first character is sent
+
+ puts("\n- Stage 4b TX/RX IRQ\n");
+
+ /*- Send a character from the transmit variable
+ - When its received by UART1 transfer it from RX buffer to the received variable
+ - set flag to say it's been received
+ - when received flag has been set send the next character from transmit variable
+ - repeat until all characters have been received*/
+
+ NVIC_EnableIRQ(UARTTX0_IRQn); //enable both UART0 TX and UART1 RX IRQs
+ NVIC_EnableIRQ(UARTRX1_IRQn);
+
+ while(j < 11) /*while j, the received character counter, is less than 11, the number of characters to be sent*/
+ { /* uart_data_received and uart_data_sent are updated by TX and RX handlers */
+ if(uart_data_received){
+ puts("UART TX IRQ ....data sent"); //if the data has been received (which is set in the
+ CMSDK_uart_SendChar(CMSDK_UART0, transmit[i]); //RX IRQ) then send the character corresponding to
+ i++; //the character counter, i, increment character counter
+ uart_data_received = 0;
+ }
+ if(uart_data_sent){ //if the data has been set (which is set in the
+ printf("UART RX IRQ ....data received.... "); //TX IRQ) then receive the character corresponding to
+ received[j] = CMSDK_uart_ReceiveChar(CMSDK_UART1); //the character counter, j, increment character counter
+ printf("%c\n", received[j]);
+ j++;
+ uart_data_sent = 0;
+ }
+ }
+
+ printf("\nString received: %s\n\n", received);
+
+ if(strcmp(received, transmit)){
+ err_code = 1;
+ puts("** TEST FAILED ** Strings Do Not Match!");
+ }
+
+ NVIC_DisableIRQ(UARTOVF0_IRQn);
+ NVIC_DisableIRQ(UARTOVF1_IRQn); //disable all the enabled IRQs
+ NVIC_DisableIRQ(UARTTX0_IRQn);
+ NVIC_DisableIRQ(UARTRX1_IRQn);
+
+ if(!err_code) return 0;
+ else return 8;
+}
+
+// ----------------------------------------------------------
+// Peripheral detection
+// ----------------------------------------------------------
+/* Detect the part number to see if device is present */
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+int uart0_id_check(void)
+{
+if ((HW32_REG(CMSDK_UART0_BASE + 0xFE0) != 0x21) ||
+ (HW32_REG(CMSDK_UART0_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+int uart1_id_check(void)
+{
+if ((HW32_REG(CMSDK_UART1_BASE + 0xFE0) != 0x21) ||
+ (HW32_REG(CMSDK_UART1_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+int gpio1_id_check(void)
+{
+if ((HW32_REG(CMSDK_GPIO1_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO1_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
diff --git a/Cortex-M0/nanosoc/software/common/validation/uart_tests.c b/Cortex-M0/nanosoc/software/common/validation/uart_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf3b331821ce37d279d4d63ac991beed580717e2
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/common/validation/uart_tests.c
@@ -0,0 +1,1241 @@
+//
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+// A simple test to check the functionalities of the APB UART
+
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include <string.h>
+#include "uart_stdout.h"
+
+#define UART_STATE_TXFULL CMSDK_UART_STATE_TXBF_Msk
+#define UART_STATE_RXFULL CMSDK_UART_STATE_RXBF_Msk
+#define UART_STATE_TXOVR CMSDK_UART_STATE_TXOR_Msk
+#define UART_STATE_RXOVR CMSDK_UART_STATE_RXOR_Msk
+
+#define UART_CTRL_TXEN CMSDK_UART_CTRL_TXEN_Msk
+#define UART_CTRL_RXEN CMSDK_UART_CTRL_RXEN_Msk
+#define UART_CTRL_TXIRQEN CMSDK_UART_CTRL_TXIRQEN_Msk
+#define UART_CTRL_RXIRQEN CMSDK_UART_CTRL_RXIRQEN_Msk
+#define UART_CTRL_TXOVRIRQEN CMSDK_UART_CTRL_TXORIRQEN_Msk
+#define UART_CTRL_RXOVRIRQEN CMSDK_UART_CTRL_RXORIRQEN_Msk
+#define UART_CTRL_HIGHSPEEDTX CMSDK_UART_CTRL_HSTM_Msk
+
+#define UART_INTSTATE_TX 1
+#define UART_INTSTATE_RX 2
+#define UART_INTSTATE_TXOVR 4
+#define UART_INTSTATE_RXOVR 8
+
+#define BAUDDIV_MASK 0x000FFFFF
+
+#define DISPLAY 1
+#define NO_DISPLAY 0
+
+/* peripheral and component ID values */
+#define APB_UART_PID4 0x04
+#define APB_UART_PID5 0x00
+#define APB_UART_PID6 0x00
+#define APB_UART_PID7 0x00
+#define APB_UART_PID0 0x21
+#define APB_UART_PID1 0xB8
+#define APB_UART_PID2 0x1B
+#define APB_UART_PID3 0x00
+#define APB_UART_CID0 0x0D
+#define APB_UART_CID1 0xF0
+#define APB_UART_CID2 0x05
+#define APB_UART_CID3 0xB1
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+/* Global variables */
+volatile int uart0_irq_occurred;
+volatile int uart1_irq_occurred;
+volatile int uart2_irq_occurred;
+volatile int uart0_irq_expected;
+volatile int uart1_irq_expected;
+volatile int uart2_irq_expected;
+
+/* Function definitions */
+void UartIOConfig(void);
+int uart_initial_value_check(CMSDK_UART_TypeDef *CMSDK_UART);
+int simple_uart_test(CMSDK_UART_TypeDef *CMSDK_UART, unsigned int bauddiv, int verbose);
+int simple_uart_baud_test(void);
+int simple_uart_baud_test_single(CMSDK_UART_TypeDef *CMSDK_UART,
+ unsigned int tx_bauddiv,unsigned int rx_bauddiv,int verbose);
+int uart_enable_ctrl_test(CMSDK_UART_TypeDef *CMSDK_UART);
+int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART);
+int uart_tx_rx_overflow_test(CMSDK_UART_TypeDef *CMSDK_UART);
+void delay_for_character(void);
+int uart2_interrupt_test(void);
+int uart0_id_check(void); /* Detect UART 0 present */
+int uart1_id_check(void); /* Detect UART 1 present */
+int gpio1_id_check(void); /* Detect GPIO 1 present */
+
+int main (void)
+{
+ int result=0;
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - UART Test - revision $Revision: 371321 $\n");
+
+ if ((uart0_id_check()!=0)||(uart1_id_check()!=0)||(gpio1_id_check()!=0)) {
+ puts("** TEST SKIPPED ** UART 0 / UART 1 / GPIO 1 not available");
+ UartEndSimulation();
+ return 0;}
+
+ uart0_irq_occurred = 0;
+ uart1_irq_occurred = 0;
+ uart0_irq_expected = 0;
+ uart1_irq_expected = 0;
+
+ uart2_irq_occurred = 0;
+ uart2_irq_expected = 0;
+
+ UartIOConfig();
+
+ result += uart_initial_value_check(CMSDK_UART0);
+ result += uart_initial_value_check(CMSDK_UART1);
+
+ puts("\nUART 0 for transmit, UART 1 for receive\n");
+
+ result += simple_uart_test(CMSDK_UART0, 32, DISPLAY);
+ result += simple_uart_baud_test();
+ result += uart_enable_ctrl_test(CMSDK_UART0);
+ result += uart_tx_rx_irq_test(CMSDK_UART0);
+ result += uart_tx_rx_overflow_test(CMSDK_UART0);
+
+ puts("\nUART 1 for transmit, UART 0 for receive\n");
+
+ result += simple_uart_test(CMSDK_UART1, 16, DISPLAY);
+ result += uart_enable_ctrl_test(CMSDK_UART1);
+ result += uart_tx_rx_irq_test(CMSDK_UART1);
+ result += uart_tx_rx_overflow_test(CMSDK_UART1);
+
+ puts("\nUART 2 interrupt connectivity test\n");
+ result += uart2_interrupt_test();
+
+ if (result==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED ** , Error code = (0x%x)\n", result);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+void UartIOConfig(void)
+{ /* UART0 and UART1 are arranged in cross over configuration. */
+ /* Enable UART TXD functions for these pins */
+ CMSDK_GPIO1->ALTFUNCSET = (1<<1) | (1<<3);
+ return;
+}
+
+/* --------------------------------------------------------------- */
+/* UART initial value tests */
+/* --------------------------------------------------------------- */
+int uart_initial_value_check(CMSDK_UART_TypeDef *CMSDK_UART){
+ int return_val=0;
+ int err_code=0;
+ unsigned int uart_base;
+ unsigned int i;
+
+ puts("- check initial values");
+ if (CMSDK_UART->DATA !=0) {err_code += (1<<0);}
+ if (CMSDK_UART->STATE !=0) {err_code += (1<<1);}
+ if (CMSDK_UART->CTRL !=0) {err_code += (1<<2);}
+ if (CMSDK_UART->INTSTATUS!=0) {err_code += (1<<3);}
+ if (CMSDK_UART->BAUDDIV !=0) {err_code += (1<<4);}
+
+ uart_base = CMSDK_UART0_BASE;
+ if (CMSDK_UART==CMSDK_UART1) {uart_base = CMSDK_UART1_BASE;}
+ if (CMSDK_UART==CMSDK_UART2) {uart_base = CMSDK_UART2_BASE;}
+
+ if (HW32_REG(uart_base + 0xFD0) != APB_UART_PID4) {err_code += (1<<5); }
+ if (HW32_REG(uart_base + 0xFD4) != APB_UART_PID5) {err_code += (1<<6); }
+ if (HW32_REG(uart_base + 0xFD8) != APB_UART_PID6) {err_code += (1<<7); }
+ if (HW32_REG(uart_base + 0xFDC) != APB_UART_PID7) {err_code += (1<<8); }
+ if (HW32_REG(uart_base + 0xFE0) != APB_UART_PID0) {err_code += (1<<9); }
+ if (HW32_REG(uart_base + 0xFE4) != APB_UART_PID1) {err_code += (1<<10); }
+ if (HW32_REG(uart_base + 0xFE8) != APB_UART_PID2) {err_code += (1<<11); }
+ if (HW32_REG(uart_base + 0xFEC) != APB_UART_PID3) {err_code += (1<<12); }
+ if (HW32_REG(uart_base + 0xFF0) != APB_UART_CID0) {err_code += (1<<13); }
+ if (HW32_REG(uart_base + 0xFF4) != APB_UART_CID1) {err_code += (1<<14); }
+ if (HW32_REG(uart_base + 0xFF8) != APB_UART_CID2) {err_code += (1<<15); }
+ if (HW32_REG(uart_base + 0xFFC) != APB_UART_CID3) {err_code += (1<<16); }
+
+ /* test write to PIDs and CIDs - should be ignored */
+ for (i=0; i <12; i++) {
+ HW32_REG(uart_base + 0xFD0 + (i<<2)) = ~HW32_REG(uart_base + 0xFD0 + (i<<2));
+ }
+
+ /* Check read back values again, should not be changed */
+ if (HW32_REG(uart_base + 0xFD0) != APB_UART_PID4) {err_code |= (1<<5); }
+ if (HW32_REG(uart_base + 0xFD4) != APB_UART_PID5) {err_code |= (1<<6); }
+ if (HW32_REG(uart_base + 0xFD8) != APB_UART_PID6) {err_code |= (1<<7); }
+ if (HW32_REG(uart_base + 0xFDC) != APB_UART_PID7) {err_code |= (1<<8); }
+ if (HW32_REG(uart_base + 0xFE0) != APB_UART_PID0) {err_code |= (1<<9); }
+ if (HW32_REG(uart_base + 0xFE4) != APB_UART_PID1) {err_code |= (1<<10); }
+ if (HW32_REG(uart_base + 0xFE8) != APB_UART_PID2) {err_code |= (1<<11); }
+ if (HW32_REG(uart_base + 0xFEC) != APB_UART_PID3) {err_code |= (1<<12); }
+ if (HW32_REG(uart_base + 0xFF0) != APB_UART_CID0) {err_code |= (1<<13); }
+ if (HW32_REG(uart_base + 0xFF4) != APB_UART_CID1) {err_code |= (1<<14); }
+ if (HW32_REG(uart_base + 0xFF8) != APB_UART_CID2) {err_code |= (1<<15); }
+ if (HW32_REG(uart_base + 0xFFC) != APB_UART_CID3) {err_code |= (1<<16); }
+
+ if (err_code != 0) {
+ printf ("ERROR : initial value failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* UART simple operation test */
+/* --------------------------------------------------------------- */
+int simple_uart_test(CMSDK_UART_TypeDef *CMSDK_UART, unsigned int bauddiv, int verbose)
+{
+ int return_val=0;
+ int err_code=0;
+ CMSDK_UART_TypeDef *TX_UART;
+ CMSDK_UART_TypeDef *RX_UART;
+ char received_text[20];
+ const char transmit_text[20] = "Hello world\n";
+ unsigned int tx_count;
+ unsigned int rx_count;
+ unsigned int str_size;
+
+ puts("Simple test");
+ UartPutc('-');
+ UartPutc(' ');
+
+ /* Determine which UART is the sender, and which UART is receiver */
+ if (CMSDK_UART==CMSDK_UART0){
+ TX_UART = CMSDK_UART0;
+ RX_UART = CMSDK_UART1;
+ }
+ else if (CMSDK_UART==CMSDK_UART1){
+ TX_UART = CMSDK_UART1;
+ RX_UART = CMSDK_UART0;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'simple_uart_test'.");
+ return 1;
+ }
+
+ /* Both UART are programmed with the same baud rate */
+ TX_UART->BAUDDIV = bauddiv;
+ if (TX_UART->BAUDDIV != bauddiv) { err_code += (1<<0);}
+ RX_UART->BAUDDIV = bauddiv;
+ if (RX_UART->BAUDDIV != bauddiv) { err_code += (1<<1);}
+
+ TX_UART->CTRL = TX_UART->CTRL | UART_CTRL_TXEN; /* Set TX enable */
+ if ((TX_UART->CTRL & UART_CTRL_TXEN)==0) { err_code += (1<<2);}
+ RX_UART->CTRL = RX_UART->CTRL | UART_CTRL_RXEN; /* Set RX enable */
+ if ((RX_UART->CTRL & UART_CTRL_RXEN)==0) { err_code += (1<<3);}
+
+ tx_count = 0;
+ rx_count = 0;
+ str_size = strlen(transmit_text);
+ do { /* test loop for both tx and rx process */
+ /* tx process */
+ if (((TX_UART->STATE & UART_STATE_TXFULL)==0)&&(tx_count<str_size)) {
+ TX_UART->DATA = transmit_text[tx_count];
+ tx_count++;
+ }
+ /* rx process */
+ if ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ received_text[rx_count] = RX_UART->DATA;
+ if (verbose) UartPutc((char) received_text[rx_count]);
+ rx_count++;
+ }
+ } while ( rx_count <str_size);
+ received_text[rx_count]=0; /* add NULL termination */
+
+ /* Added 3 additional null chars to overcome X-termination in test
+ when reads back X's beyond null char since a load 32-bit word
+ happens rather than a byte access. */
+ received_text[rx_count+1]=0; /* add NULL termination */
+ received_text[rx_count+2]=0; /* add NULL termination */
+ received_text[rx_count+3]=0; /* add NULL termination */
+ if (strcmp(transmit_text, received_text)!=0){ err_code += (1<<4);}
+
+ TX_UART->CTRL = 0; /* Clear TX enable */
+ RX_UART->CTRL = 0; /* Clear RX enable */
+
+ if (err_code != 0) {
+ printf ("ERROR : simple test failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* UART baud rate operation test */
+/* --------------------------------------------------------------- */
+int simple_uart_baud_test(void)
+{
+ int return_val=0;
+ int err_code=0;
+ int i;
+ short int tx_bauddiv[10] = {
+ 63, 64, 35, 38, 40, 46, 85, 49, 51, 37};
+ short int rx_bauddiv[10] = {
+ 63, 64, 35, 38, 40, 46, 85, 49, 51, 37};
+
+ puts("Data transfer test\n");
+
+ for (i=0; i<10; i++) {
+ /* Test TX and RX at same speed */
+ if (simple_uart_baud_test_single(CMSDK_UART0,
+ tx_bauddiv[i], rx_bauddiv[i] , NO_DISPLAY)!=0) {err_code |= 0x1;};
+ /* Test RX slower than TX */
+ if (simple_uart_baud_test_single(CMSDK_UART0,
+ tx_bauddiv[i], (rx_bauddiv[i]+1), NO_DISPLAY)!=0) {err_code |= 0x2;};
+ /* Test RX faster than TX */
+ if (simple_uart_baud_test_single(CMSDK_UART0,
+ tx_bauddiv[i], (rx_bauddiv[i]-1), NO_DISPLAY)!=0) {err_code |= 0x4;};
+ if (err_code != 0) {
+ printf ("ERROR : Baud rate test failed (0x%x) at loop %d\n", err_code, i);
+ return_val = 1;
+ err_code = 0;
+ }
+ else {
+ printf ("- bauddiv = %d done\n", tx_bauddiv[i]);
+ }
+ }
+ CMSDK_UART0->CTRL = 0;
+ CMSDK_UART1->CTRL = 0;
+ CMSDK_UART0->BAUDDIV = 0xFFFFFFFF;
+ if (CMSDK_UART0->BAUDDIV != (0xFFFFFFFF & BAUDDIV_MASK)) {err_code |= (1<<0);};
+ CMSDK_UART0->BAUDDIV = 0xFF55AAC3;
+ if (CMSDK_UART0->BAUDDIV != (0xFF55AAC3 & BAUDDIV_MASK)) {err_code |= (1<<1);};
+ CMSDK_UART0->BAUDDIV = 0x00000000;
+ if (CMSDK_UART0->BAUDDIV != (0x00000000 & BAUDDIV_MASK)) {err_code |= (1<<2);};
+ CMSDK_UART1->BAUDDIV = 0xFFFFFFFF;
+ if (CMSDK_UART1->BAUDDIV != (0xFFFFFFFF & BAUDDIV_MASK)) {err_code |= (1<<3);};
+ CMSDK_UART1->BAUDDIV = 0xAAFF6699;
+ if (CMSDK_UART1->BAUDDIV != (0xAAFF6699 & BAUDDIV_MASK)) {err_code |= (1<<4);};
+ CMSDK_UART1->BAUDDIV = 0x00000000;
+ if (CMSDK_UART1->BAUDDIV != (0x00000000 & BAUDDIV_MASK)) {err_code |= (1<<5);};
+ if (err_code != 0) {
+ printf ("ERROR : Baud rate r/w failed (0x%x)\n", err_code);
+ return_val = 1;
+ err_code = 0;
+ }
+
+
+ return(return_val);
+
+}
+/* --------------------- */
+int simple_uart_baud_test_single(CMSDK_UART_TypeDef *CMSDK_UART,
+ unsigned int tx_bauddiv,
+ unsigned int rx_bauddiv,
+ int verbose)
+{
+ int return_val=0;
+ int err_code=0;
+ CMSDK_UART_TypeDef *TX_UART;
+ CMSDK_UART_TypeDef *RX_UART;
+ char received_text[20];
+ const char transmit_text[20] = "Hello world\n";
+ unsigned int tx_count;
+ unsigned int rx_count;
+ unsigned int str_size;
+
+ /* Determine which UART is the sender, and which UART is receiver */
+ if (CMSDK_UART==CMSDK_UART0){
+ TX_UART = CMSDK_UART0;
+ RX_UART = CMSDK_UART1;
+ }
+ else if (CMSDK_UART==CMSDK_UART1){
+ TX_UART = CMSDK_UART1;
+ RX_UART = CMSDK_UART0;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'simple_uart_baud_test_single'.");
+ return 1;
+ }
+
+ /* UART can be programmed with different baud rate */
+ TX_UART->BAUDDIV = tx_bauddiv;
+ if (TX_UART->BAUDDIV != tx_bauddiv) { err_code += (1<<0);}
+ RX_UART->BAUDDIV = rx_bauddiv;
+ if (RX_UART->BAUDDIV != rx_bauddiv) { err_code += (1<<1);}
+
+ TX_UART->CTRL = TX_UART->CTRL | UART_CTRL_TXEN; /* Set TX enable */
+ if ((TX_UART->CTRL & UART_CTRL_TXEN)==0) { err_code += (1<<2);}
+ RX_UART->CTRL = RX_UART->CTRL | UART_CTRL_RXEN; /* Set RX enable */
+ if ((RX_UART->CTRL & UART_CTRL_RXEN)==0) { err_code += (1<<3);}
+
+ tx_count = 0;
+ rx_count = 0;
+ str_size = strlen(transmit_text);
+ do { /* test loop for both tx and rx process */
+ /* tx process */
+ if (((TX_UART->STATE & UART_STATE_TXFULL)==0)&&(tx_count<str_size)) {
+ TX_UART->DATA = transmit_text[tx_count];
+ tx_count++;
+ }
+ /* rx process */
+ if ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ received_text[rx_count] = RX_UART->DATA;
+ if (verbose) UartPutc((char) received_text[rx_count]);
+ rx_count++;
+ }
+ } while ( rx_count <str_size);
+ received_text[rx_count]=0; /* add NULL termination */
+
+ /* Added 3 additional null chars to overcome X-termination in test
+ when reads back X's beyond null char since a load 32-bit word
+ happens rather than a byte access. */
+ received_text[rx_count+1]=0; /* add NULL termination */
+ received_text[rx_count+2]=0; /* add NULL termination */
+ received_text[rx_count+3]=0; /* add NULL termination */
+ if (strcmp(transmit_text, received_text)!=0){ err_code += (1<<4);}
+
+ TX_UART->CTRL = 0; /* Clear TX enable */
+ RX_UART->CTRL = 0; /* Clear RX enable */
+
+ if (err_code != 0) {
+ printf ("ERROR : baud test failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* UART enable control test */
+/* --------------------------------------------------------------- */
+int uart_enable_ctrl_test(CMSDK_UART_TypeDef *CMSDK_UART)
+{
+ int return_val=0;
+ int err_code=0;
+ CMSDK_UART_TypeDef *TX_UART;
+ CMSDK_UART_TypeDef *RX_UART;
+ char ctmp;
+
+ /* Determine which UART is the sender, and which UART is receiver */
+ if (CMSDK_UART==CMSDK_UART0){
+ TX_UART = CMSDK_UART0;
+ RX_UART = CMSDK_UART1;
+ }
+ else if (CMSDK_UART==CMSDK_UART1){
+ TX_UART = CMSDK_UART1;
+ RX_UART = CMSDK_UART0;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'uart_enable_ctrl_test'.");
+ return 1;
+ }
+
+ puts ("UART enable test");
+ /* UART programmed with same baud rate */
+ TX_UART->BAUDDIV = 32;
+ if (TX_UART->BAUDDIV != 32) { err_code += (1<<0);}
+ RX_UART->BAUDDIV = 32;
+ if (RX_UART->BAUDDIV != 32) { err_code += (1<<1);}
+
+ puts ("- both TX and RX are enabled");
+ TX_UART->CTRL = TX_UART->CTRL | UART_CTRL_TXEN; /* Set TX enable */
+ if ((TX_UART->CTRL & UART_CTRL_TXEN)==0) { err_code += (1<<2);}
+ RX_UART->CTRL = RX_UART->CTRL | UART_CTRL_RXEN; /* Set RX enable */
+ if ((RX_UART->CTRL & UART_CTRL_RXEN)==0) { err_code += (1<<3);}
+
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* Starting state incorrect */
+ err_code += (1<<4);}
+ TX_UART->DATA = 'A'; /* transmit a character */
+ delay_for_character();
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)==0)) {
+ /* complete state incorrect */
+ err_code += (1<<5);}
+ ctmp = RX_UART->DATA; /* Read received data */
+ if ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ /* receive buffer should be empty now */
+ err_code += (1<<6);}
+ if ( ctmp != 'A') { /* received data incorrect */
+ err_code += (1<<7);}
+
+ puts ("- TX disabled");
+ TX_UART->CTRL = TX_UART->CTRL & ~UART_CTRL_TXEN; /* Clear TX enable */
+ if ((TX_UART->CTRL & UART_CTRL_TXEN)!=0) { err_code += (1<<8);}
+
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* Starting state incorrect */
+ err_code += (1<<9);}
+ TX_UART->DATA = 'B'; /* transmit a character */
+
+ /* When TX enable is low and a data is written to transmit buffer, the
+ data would be lost */
+ delay_for_character();
+ if ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ /* RX buffer should still be empty*/
+ err_code += (1<<10);}
+ TX_UART->CTRL = TX_UART->CTRL | UART_CTRL_TXEN; /* Set TX enable */
+ delay_for_character();
+
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* complete state incorrect */
+ err_code += (1<<11);}
+
+ puts ("- RX disabled");
+ RX_UART->CTRL = RX_UART->CTRL & ~UART_CTRL_RXEN; /* Clear RX enable */
+ if ((RX_UART->CTRL & UART_CTRL_RXEN)!=0) { err_code += (1<<12);}
+
+ TX_UART->DATA = 'C'; /* transmit a character */
+ delay_for_character();
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* No data should be received. complete state incorrect */
+ err_code += (1<<13);}
+ RX_UART->CTRL = RX_UART->CTRL | UART_CTRL_RXEN; /* Set RX enable */
+ delay_for_character();
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* No data should be received. complete state incorrect */
+ err_code += (1<<14);}
+
+ TX_UART->CTRL = 0;
+ RX_UART->CTRL = 0;
+ while ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ ctmp=RX_UART->DATA;
+ }
+
+ if (err_code != 0) {
+ printf ("ERROR : uart enable failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* UART tx & rx interrupt test */
+/* --------------------------------------------------------------- */
+
+int uart_tx_rx_irq_test(CMSDK_UART_TypeDef *CMSDK_UART)
+{
+ int return_val=0;
+ unsigned int err_code=0;
+ CMSDK_UART_TypeDef *TX_UART;
+ CMSDK_UART_TypeDef *RX_UART;
+ char ctmp;
+
+ /* Determine which UART is the sender, and which UART is receiver */
+ if (CMSDK_UART==CMSDK_UART0){
+ TX_UART = CMSDK_UART0;
+ RX_UART = CMSDK_UART1;
+ }
+ else if (CMSDK_UART==CMSDK_UART1){
+ TX_UART = CMSDK_UART1;
+ RX_UART = CMSDK_UART0;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'uart_tx_rx_irq_test'.");
+ return 1;
+ }
+
+ puts ("UART TX & RX IRQ test");
+ /* UART programmed with same baud rate */
+ TX_UART->BAUDDIV = 33;
+ if (TX_UART->BAUDDIV != 33) { err_code += (1<<0);}
+ RX_UART->BAUDDIV = 33;
+ if (RX_UART->BAUDDIV != 33) { err_code += (1<<1);}
+
+ puts ("- TX irq enable");
+ if (CMSDK_UART==CMSDK_UART0){
+ uart0_irq_expected=1;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTTX0_IRQn);
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ uart0_irq_expected=0;
+ uart1_irq_expected=1;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTTX1_IRQn);
+ }
+
+ TX_UART->CTRL = UART_CTRL_TXEN | UART_CTRL_TXIRQEN;
+ RX_UART->CTRL = UART_CTRL_RXEN;
+
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) |
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* Starting state incorrect */
+ err_code += (1<<2);}
+ TX_UART->DATA = 'A'; /* transmit a character */
+ delay_for_character();
+
+ if (CMSDK_UART==CMSDK_UART0){
+ if (uart0_irq_occurred==0){ err_code += (1<<3);}
+ if (uart1_irq_occurred!=0){ err_code += (1<<4);}
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ if (uart1_irq_occurred==0){ err_code += (1<<3);}
+ if (uart0_irq_occurred!=0){ err_code += (1<<4);}
+ }
+ /* Interrupt status should have been cleared */
+ if (TX_UART->INTSTATUS != 0) { err_code += (1<<5);}
+ if (RX_UART->INTSTATUS != 0) { err_code += (1<<6);}
+
+ /* Receive buffer should have been full */
+ if ((RX_UART->STATE & UART_STATE_RXFULL) == 0) { err_code += (1<<7);}
+ ctmp = RX_UART->DATA;
+ if (ctmp!='A') { err_code += (1<<8);}
+ if ((RX_UART->STATE & UART_STATE_RXFULL) != 0) { err_code += (1<<9);}
+
+ puts ("- TX irq disable");
+ if (CMSDK_UART==CMSDK_UART0){
+ uart0_irq_expected=0;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTTX0_IRQn);
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ uart0_irq_expected=0;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTTX1_IRQn);
+ }
+
+ TX_UART->CTRL = UART_CTRL_TXEN; /* No interrupt generation */
+ RX_UART->CTRL = UART_CTRL_RXEN; /* No interrupt generation */
+
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* Starting state incorrect */
+ err_code += (1<<10);}
+ TX_UART->DATA = 'B'; /* transmit a character */
+ delay_for_character();
+
+ if (uart0_irq_occurred!=0){ err_code += (1<<11);}
+ if (uart1_irq_occurred!=0){ err_code += (1<<12);}
+
+ /* Receive buffer should have been full */
+ if ((RX_UART->STATE & UART_STATE_RXFULL) == 0) { err_code += (1<<13);}
+ ctmp = RX_UART->DATA;
+ if (ctmp!='B') { err_code += (1<<14);}
+ if ((RX_UART->STATE & UART_STATE_RXFULL) != 0) { err_code += (1<<15);}
+
+ /* Interrupt status should have been cleared */
+ if (TX_UART->INTSTATUS != 0) { err_code += (1<<16);}
+ if (RX_UART->INTSTATUS != 0) { err_code += (1<<17);}
+
+ puts ("- RX irq enable");
+ if (CMSDK_UART==CMSDK_UART0){
+ uart0_irq_expected=0;
+ uart1_irq_expected=1;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTRX1_IRQn);
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ uart0_irq_expected=1;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTRX0_IRQn);
+ }
+
+ TX_UART->CTRL = UART_CTRL_TXEN ; /* No interrupt generation */
+ RX_UART->CTRL = UART_CTRL_RXEN | UART_CTRL_RXIRQEN;
+
+ TX_UART->DATA = 'C'; /* transmit a character */
+ delay_for_character();
+
+ if (CMSDK_UART==CMSDK_UART0){
+ if (uart0_irq_occurred!=0){ err_code += (1<<18);}
+ if (uart1_irq_occurred==0){ err_code += (1<<19);}
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ if (uart1_irq_occurred!=0){ err_code += (1<<18);}
+ if (uart0_irq_occurred==0){ err_code += (1<<19);}
+ }
+ /* Interrupt status should have been cleared */
+ if (TX_UART->INTSTATUS != 0) { err_code += (1<<20);}
+ if (RX_UART->INTSTATUS != 0) { err_code += (1<<21);}
+
+ /* Receive buffer should have been full */
+ if ((RX_UART->STATE & UART_STATE_RXFULL) == 0) { err_code += (1<<22);}
+ ctmp = RX_UART->DATA;
+ if (ctmp!='C') { err_code += (1<<23);}
+ if ((RX_UART->STATE & UART_STATE_RXFULL) != 0) { err_code += (1<<24);}
+
+ puts ("- RX irq disable");
+ uart0_irq_expected=0;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+
+ TX_UART->CTRL = UART_CTRL_TXEN; /* No interrupt generation */
+ RX_UART->CTRL = UART_CTRL_RXEN; /* No interrupt generation */
+
+ if (((TX_UART->STATE & UART_STATE_TXFULL)!=0) ||
+ ((RX_UART->STATE & UART_STATE_RXFULL)!=0)) {
+ /* Starting state incorrect */
+ err_code += (1<<25);}
+ TX_UART->DATA = 'D'; /* transmit a character */
+ delay_for_character();
+
+ if (uart0_irq_occurred!=0){ err_code += (1<<26);}
+ if (uart1_irq_occurred!=0){ err_code += (1<<27);}
+
+ /* Receive buffer should have been full */
+ if ((RX_UART->STATE & UART_STATE_RXFULL) == 0) { err_code += (1<<28);}
+ ctmp = RX_UART->DATA;
+ if (ctmp!='D') { err_code += (1<<29);}
+ if ((RX_UART->STATE & UART_STATE_RXFULL) != 0) { err_code += (1<<30);}
+
+ /* Interrupt status should have been cleared */
+ if ((TX_UART->INTSTATUS != 0)||(RX_UART->INTSTATUS != 0)) { err_code |= 0x80000000UL;}
+
+ /* clean up */
+
+ TX_UART->CTRL = 0;
+ RX_UART->CTRL = 0;
+ while ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ ctmp=RX_UART->DATA;
+ }
+ NVIC_DisableIRQ(UARTRX0_IRQn);
+ NVIC_DisableIRQ(UARTRX1_IRQn);
+ NVIC_DisableIRQ(UARTTX0_IRQn);
+ NVIC_DisableIRQ(UARTTX1_IRQn);
+
+ if (err_code != 0) {
+ printf ("ERROR : uart interrupt enable failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* UART tx & rx overflow test */
+/* --------------------------------------------------------------- */
+
+int uart_tx_rx_overflow_test(CMSDK_UART_TypeDef *CMSDK_UART)
+{
+ int return_val=0;
+ int err_code=0;
+ CMSDK_UART_TypeDef *TX_UART;
+ CMSDK_UART_TypeDef *RX_UART;
+ char ctmp;
+ int i;
+
+ /* Determine which UART is the sender, and which UART is receiver */
+ if (CMSDK_UART==CMSDK_UART0){
+ TX_UART = CMSDK_UART0;
+ RX_UART = CMSDK_UART1;
+ }
+ else if (CMSDK_UART==CMSDK_UART1){
+ TX_UART = CMSDK_UART1;
+ RX_UART = CMSDK_UART0;
+ }
+ else {
+ puts ("ERROR: Input parameter invalid in function 'uart_tx_rx_overflow_test'.");
+ return 1;
+ }
+
+ puts ("UART TX & RX overflow test");
+ /* UART programmed with same baud rate */
+ TX_UART->BAUDDIV = 34;
+ if (TX_UART->BAUDDIV != 34) { err_code += (1<<0);}
+ RX_UART->BAUDDIV = 34;
+ if (RX_UART->BAUDDIV != 34) { err_code += (1<<1);}
+
+ puts ("- TX without overflow");
+ uart0_irq_expected=0;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+
+ TX_UART->CTRL = UART_CTRL_TXEN ; /* No interrupt generation */
+ RX_UART->CTRL = UART_CTRL_RXEN ; /* No interrupt generation */
+
+ TX_UART->DATA = 'A';
+ TX_UART->DATA = 'B';
+ if ((TX_UART->STATE & UART_STATE_TXOVR)!=0) { err_code += (1<<2);}
+ for (i=0; i<2;i++) {
+ while ((RX_UART->STATE & UART_STATE_RXFULL)==0); /* wait for data */
+ ctmp= RX_UART->DATA;
+ if (i==0) {
+ if (ctmp!='A') { err_code += (1<<3);}
+ }
+ if (i==1) {
+ if (ctmp!='B') { err_code += (1<<4);}
+ }
+ }
+ if ((RX_UART->STATE != 0)||(TX_UART->STATE != 0)) { err_code += (1<<5);}
+
+ puts ("- TX with overflow");
+ TX_UART->DATA = 'A';
+ TX_UART->DATA = 'B';
+ TX_UART->DATA = 'C';
+ if ((TX_UART->STATE & UART_STATE_TXOVR)==0) { err_code += (1<<6);}
+ for (i=0; i<2;i++) {
+ while ((RX_UART->STATE & UART_STATE_RXFULL)==0); /* wait for data */
+ ctmp= RX_UART->DATA;
+ if (i==0) {
+ if (ctmp!='A') { err_code += (1<<7);}
+ }
+ /* if i=1, data unpredictable */
+ }
+ /* Overrun state should stay high */
+ if ((TX_UART->STATE & UART_STATE_TXOVR)==0) { err_code += (1<<8);}
+ /* Overrun interrupt status should be low because TX overrun interrupt is not set */
+ if ((TX_UART->INTSTATUS & UART_INTSTATE_TXOVR)!=0) { err_code += (1<<9);}
+
+ TX_UART->CTRL = UART_CTRL_TXEN | UART_CTRL_TXOVRIRQEN; /* Enable overflow interrupt generation */
+ /* Overrun interrupt status should be high now */
+ if ((TX_UART->INTSTATUS & UART_INTSTATE_TXOVR)==0) { err_code += (1<<10);}
+
+ /* enable the overflow interrupt in NVIC to trigger the overflow interrupt */
+ if (CMSDK_UART==CMSDK_UART0){
+ uart0_irq_expected=1;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTOVF0_IRQn);
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ uart0_irq_expected=0;
+ uart1_irq_expected=1;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTOVF1_IRQn);
+ }
+
+ __DSB();
+ __ISB();
+ /* The interrupt should be taken */
+
+ /* Overrun state should be cleared by interrupt handler */
+ if ((TX_UART->STATE & UART_STATE_TXOVR)!=0) { err_code += (1<<11);}
+ /* interrupt handler should be executed once */
+ if ((CMSDK_UART==CMSDK_UART0)&&(uart0_irq_occurred==0)) { err_code += (1<<12);}
+ if ((CMSDK_UART==CMSDK_UART1)&&(uart1_irq_occurred==0)) { err_code += (1<<12);}
+
+ TX_UART->CTRL = UART_CTRL_TXEN ; /* No interrupt generation */
+ RX_UART->CTRL = UART_CTRL_RXEN ; /* No interrupt generation */
+
+ NVIC_DisableIRQ(UARTOVF0_IRQn);
+ NVIC_DisableIRQ(UARTOVF1_IRQn);
+ uart0_irq_expected = 0;
+ uart1_irq_expected = 0;
+
+ puts ("- RX overflow");
+ TX_UART->DATA = 'A';
+ TX_UART->DATA = 'B';
+ /* TX overflow should not occur */
+ if ((TX_UART->STATE & UART_STATE_TXOVR)!=0) { err_code += (1<<13);}
+ /* wait until RX buffer full */
+ while ((RX_UART->STATE & UART_STATE_RXFULL)==0);
+ /* Should not overflow yet */
+ if ((RX_UART->STATE & UART_STATE_RXOVR)!=0) { err_code += (1<<14);}
+ /* wait until RX overflow */
+ while ((RX_UART->STATE & UART_STATE_RXOVR)==0);
+ /* RX overflow interrupt should be low because RX overflow interrupt enable is not set */
+ if ((RX_UART->INTSTATUS & UART_INTSTATE_RXOVR)!=0) { err_code += (1<<15);}
+
+ RX_UART->CTRL = UART_CTRL_RXEN | UART_CTRL_RXOVRIRQEN; /* Enable overflow interrupt generation */
+ /* Overrun interrupt status should be high now */
+ if ((RX_UART->INTSTATUS & UART_INTSTATE_RXOVR)==0) { err_code += (1<<16);}
+
+ /* enable the overflow interrupt in NVIC to trigger the overflow interrupt */
+ if (CMSDK_UART==CMSDK_UART0){
+ uart0_irq_expected=0;
+ uart1_irq_expected=1;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTOVF1_IRQn);
+ }
+ if (CMSDK_UART==CMSDK_UART1){
+ uart0_irq_expected=1;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+ NVIC_EnableIRQ(UARTOVF0_IRQn);
+ }
+
+ __DSB();
+ __ISB();
+ /* The interrupt should be taken */
+
+ /* Overrun state should be cleared by interrupt handler */
+ if ((RX_UART->STATE & UART_STATE_RXOVR)!=0) { err_code += (1<<17);}
+ /* interrupt handler should be executed once */
+ if ((CMSDK_UART==CMSDK_UART0)&&(uart1_irq_occurred==0)) { err_code += (1<<18);}
+ if ((CMSDK_UART==CMSDK_UART1)&&(uart0_irq_occurred==0)) { err_code += (1<<18);}
+
+
+ /* clean up */
+ uart0_irq_expected=0;
+ uart1_irq_expected=0;
+ uart0_irq_occurred=0;
+ uart1_irq_occurred=0;
+
+ TX_UART->CTRL = 0;
+ RX_UART->CTRL = 0;
+ while ((RX_UART->STATE & UART_STATE_RXFULL)!=0) {
+ ctmp=RX_UART->DATA;
+ }
+
+ NVIC_DisableIRQ(UARTOVF0_IRQn);
+ NVIC_DisableIRQ(UARTOVF1_IRQn);
+
+ if (err_code != 0) {
+ printf ("ERROR : uart overflow test failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+
+/* --------------------------------------------------------------- */
+/* UART 2 interrupt connectivity test */
+/* --------------------------------------------------------------- */
+int uart2_interrupt_test(void){
+ int return_val=0;
+ int err_code=0;
+ int i;
+ char ctmp; /* dummy variable for overflow test (data can be corrupted so it is not checked) */
+
+
+ puts ("UART 2 interrupt connectivity test");
+
+ puts ("- UART 2 TX IRQ");
+ CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_TXIRQEN | UART_CTRL_HIGHSPEEDTX;
+ NVIC_EnableIRQ(UARTTX2_IRQn);
+ uart2_irq_expected = 1;
+ UartPutc('.');
+ for (i=0; i<3;i++){ __ISB(); } /* small delay */
+ CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_HIGHSPEEDTX;
+ if (uart2_irq_occurred==0) { err_code += (1<<0);}
+ uart2_irq_occurred = 0;
+ NVIC_DisableIRQ(UARTTX2_IRQn);
+
+ puts ("\n- UART 2 TX overflow IRQ");
+ NVIC_EnableIRQ(UARTOVF2_IRQn);
+ CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_TXOVRIRQEN | UART_CTRL_HIGHSPEEDTX;
+ CMSDK_UART2->DATA = '.';
+ CMSDK_UART2->DATA = '.';
+ CMSDK_UART2->DATA = '.';
+ for (i=0; i<3;i++){ __ISB(); } /* small delay */
+ if (uart2_irq_occurred==0) { err_code += (1<<1);}
+ uart2_irq_occurred = 0;
+ NVIC_DisableIRQ(UARTOVF2_IRQn);
+
+ puts ("\n- UART 2 RX IRQ");
+ /* UART 2 RXD is shared with GPIO1[4] */
+ CMSDK_GPIO1->OUTENABLESET = (1<<4);
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
+ NVIC_EnableIRQ(UARTRX2_IRQn);
+ CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_RXEN | UART_CTRL_RXIRQEN | UART_CTRL_HIGHSPEEDTX;
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
+ for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
+ delay_for_character();
+ if (uart2_irq_occurred==0) { err_code += (1<<2);}
+ if ((CMSDK_UART2->STATE & UART_STATE_RXFULL)==0) { err_code += (1<<3);}
+ ctmp=CMSDK_UART2->DATA;
+ /*printf ("Receive data = 0x%x\n", ctmp);*/
+ uart2_irq_occurred = 0;
+ NVIC_DisableIRQ(UARTRX2_IRQn);
+
+ puts ("\n- UART 2 RX overflow IRQ");
+ NVIC_EnableIRQ(UARTOVF2_IRQn);
+ CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_RXEN | UART_CTRL_RXOVRIRQEN | UART_CTRL_HIGHSPEEDTX;
+ /* First character */
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
+ for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
+ delay_for_character();
+ /* Second character */
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
+ for (i=0; i<2;i++){ __ISB(); } /* small delay to create start bit */
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT | (1<<4);
+ delay_for_character();
+ if (uart2_irq_occurred==0) { err_code += (1<<4);}
+
+ /* Remove receive data in buffer */
+ while ((CMSDK_UART2->STATE & UART_STATE_RXFULL)!=0) {
+ ctmp=CMSDK_UART2->DATA;
+ }
+ /* clear up */
+ uart2_irq_occurred = 0;
+ NVIC_DisableIRQ(UARTOVF2_IRQn);
+ CMSDK_UART2->CTRL = UART_CTRL_TXEN | UART_CTRL_HIGHSPEEDTX;
+
+ CMSDK_GPIO1->OUTENABLECLR = (1<<4);
+ CMSDK_GPIO1->DATAOUT = CMSDK_GPIO1->DATAOUT & ~(1<<4);
+ uart2_irq_expected = 0;
+
+
+
+ if (err_code != 0) {
+ printf ("ERROR : uart overflow test failed (0x%x)\n", err_code);
+ return_val =1;
+ err_code = 0;
+ }
+
+ return(return_val);
+}
+/* --------------------------------------------------------------- */
+/* delay function to provide delay for one character */
+/* --------------------------------------------------------------- */
+
+void delay_for_character(void)
+{
+ int i;
+ for (i=0; i<120;i++){
+ __ISB();
+ }
+ return;
+}
+/* --------------------------------------------------------------- */
+/* Peripheral ID detection to check if device is present */
+/* --------------------------------------------------------------- */
+int uart0_id_check(void)
+{
+if ((HW32_REG(CMSDK_UART0_BASE + 0xFE0) != 0x21) ||
+ (HW32_REG(CMSDK_UART0_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+int uart1_id_check(void)
+{
+if ((HW32_REG(CMSDK_UART1_BASE + 0xFE0) != 0x21) ||
+ (HW32_REG(CMSDK_UART1_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+
+int gpio1_id_check(void)
+{
+if ((HW32_REG(CMSDK_GPIO1_BASE + 0xFE0) != 0x20) ||
+ (HW32_REG(CMSDK_GPIO1_BASE + 0xFE4) != 0xB8))
+ return 1; /* part ID does not match */
+else
+ return 0;
+}
+/* --------------------------------------------------------------- */
+/* UART interrupt handlers */
+/* --------------------------------------------------------------- */
+void UARTRX0_Handler(void)
+{
+ int err_code = 0;
+ if (uart0_irq_expected==0) {err_code += (1<<0);}
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_RX)==0) {err_code += (1<<1);}
+ CMSDK_UART0->INTCLEAR = UART_INTSTATE_RX; /* Clear interrupt status */
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_RX)!=0) {err_code += (1<<2);}
+ uart0_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 0 RX handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+
+void UARTTX0_Handler(void)
+{
+ int err_code = 0;
+ if (uart0_irq_expected==0) {err_code += (1<<0);}
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_TX)==0) {err_code += (1<<1);}
+ CMSDK_UART0->INTCLEAR = UART_INTSTATE_TX; /* Clear interrupt status */
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_TX)!=0) {err_code += (1<<2);}
+ uart0_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 0 TX handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+void UARTRX1_Handler(void)
+{
+ int err_code = 0;
+ if (uart1_irq_expected==0) {err_code += (1<<0);}
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_RX)==0) {err_code += (1<<1);}
+ CMSDK_UART1->INTCLEAR = UART_INTSTATE_RX; /* Clear interrupt status */
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_RX)!=0) {err_code += (1<<2);}
+ uart1_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 1 RX handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+
+void UARTTX1_Handler(void)
+{
+ int err_code = 0;
+ if (uart1_irq_expected==0) {err_code += (1<<0);}
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_TX)==0) {err_code += (1<<1);}
+ CMSDK_UART1->INTCLEAR = UART_INTSTATE_TX; /* Clear interrupt status */
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_TX)!=0) {err_code += (1<<2);}
+ uart1_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 1 TX handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+void UARTOVF0_Handler(void)
+{
+ int err_code = 0;
+ if (uart0_irq_expected==0) {err_code += (1<<0);}
+ if (((CMSDK_UART0->INTSTATUS & UART_INTSTATE_TXOVR)==0) &
+ ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_RXOVR)==0)) {err_code += (1<<1);}
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_TXOVR)!=0){
+ CMSDK_UART0->STATE = UART_STATE_TXOVR; /* Clear TX overrun status */
+ }
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_RXOVR)!=0){
+ CMSDK_UART0->STATE = UART_STATE_RXOVR; /* Clear RX overrun status */
+ }
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_TXOVR)!=0) {err_code += (1<<2);}
+ if ((CMSDK_UART0->INTSTATUS & UART_INTSTATE_RXOVR)!=0) {err_code += (1<<3);}
+ uart0_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 0 overrun handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ } return;
+}
+
+void UARTOVF1_Handler(void)
+{
+ int err_code = 0;
+ if (uart1_irq_expected==0) {err_code += (1<<0);}
+ if (((CMSDK_UART1->INTSTATUS & UART_INTSTATE_TXOVR)==0) &
+ ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_RXOVR)==0)) {err_code += (1<<1);}
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_TXOVR)!=0){
+ CMSDK_UART1->STATE = UART_STATE_TXOVR; /* Clear TX overrun status */
+ }
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_RXOVR)!=0){
+ CMSDK_UART1->STATE = UART_STATE_RXOVR; /* Clear RX overrun status */
+ }
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_TXOVR)!=0) {err_code += (1<<2);}
+ if ((CMSDK_UART1->INTSTATUS & UART_INTSTATE_RXOVR)!=0) {err_code += (1<<3);}
+ uart1_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 1 overrun handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+void UARTRX2_Handler(void)
+{
+ int err_code = 0;
+ if (uart2_irq_expected==0) {err_code += (1<<0);}
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_RX)==0) {err_code += (1<<1);}
+ CMSDK_UART2->INTCLEAR = UART_INTSTATE_RX; /* Clear interrupt status */
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_RX)!=0) {err_code += (1<<2);}
+ uart2_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 2 RX handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+
+void UARTTX2_Handler(void)
+{
+ int err_code = 0;
+ if (uart2_irq_expected==0) {err_code += (1<<0);}
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_TX)==0) {err_code += (1<<1);}
+ CMSDK_UART2->INTCLEAR = UART_INTSTATE_TX; /* Clear interrupt status */
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_TX)!=0) {err_code += (1<<2);}
+ uart2_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 2 TX handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+
+void UARTOVF2_Handler(void)
+{
+ int err_code = 0;
+ if (uart2_irq_expected==0) {err_code += (1<<0);}
+ if (((CMSDK_UART2->INTSTATUS & UART_INTSTATE_TXOVR)==0) &
+ ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_RXOVR)==0)) {err_code += (1<<1);}
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_TXOVR)!=0){
+ CMSDK_UART2->STATE = UART_STATE_TXOVR; /* Clear TX overrun status */
+ }
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_RXOVR)!=0){
+ CMSDK_UART2->STATE = UART_STATE_RXOVR; /* Clear RX overrun status */
+ }
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_TXOVR)!=0) {err_code += (1<<2);}
+ if ((CMSDK_UART2->INTSTATUS & UART_INTSTATE_RXOVR)!=0) {err_code += (1<<3);}
+ uart2_irq_occurred++;
+ if (err_code != 0) {
+ printf ("ERROR : UART 2 overrun handler failed (0x%x)\n", err_code);
+ UartEndSimulation();
+ while(1);
+ }
+ return;
+}
+
diff --git a/Cortex-M0/nanosoc/software/debug_tester/Makefile b/Cortex-M0/nanosoc/software/debug_tester/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..05ce772a70174163c1d07e20524e9e2f09fdfded
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/Makefile
@@ -0,0 +1,264 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# CMSDK Debug Tester Makefile
+#
+#-----------------------------------------------------------------------------
+# Remove any current implicit rules
+.IMPLICIT =
+
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+# - CORTEX_M3
+# - CORTEX_M4
+# - CORTEX_M4F
+# Note: if CORTEX_M4F is used, make sure:
+# 1. RTL is configured to enable FPU option (cmsdk_mcu_defs.v) and recompiled
+# 2. __FPU_PRESENT variable in header file (e.g. CMSDK_CM4.h) is set to 1
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = ../
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+GCC_LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0_DS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+ STARTUP_FILE = startup_CMSDK_CM0
+ USER_DEFINE = -DCORTEX_M0
+ ARM_CPU_TYPE = --cpu=Cortex-M0
+ GCC_CPU_TYPE = -mcpu=cortex-m0
+ GCC_LINKER_SCRIPT = $(GCC_LINKER_SCRIPT_PATH)/debugtester.ld
+endif
+ifeq ($(CPU_PRODUCT),CORTEX_M0)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+ STARTUP_FILE = startup_CMSDK_CM0
+ USER_DEFINE = -DCORTEX_M0
+ ARM_CPU_TYPE = --cpu=Cortex-M0
+ GCC_CPU_TYPE = -mcpu=cortex-m0
+ GCC_LINKER_SCRIPT = $(GCC_LINKER_SCRIPT_PATH)/debugtester.ld
+endif
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ USER_DEFINE = -DCORTEX_M0PLUS
+ ARM_CPU_TYPE = --cpu=Cortex-M0plus
+ GCC_CPU_TYPE = -mcpu=cortex-m0plus
+ GCC_LINKER_SCRIPT = $(GCC_LINKER_SCRIPT_PATH)/debugtester.ld
+endif
+ifeq ($(CPU_PRODUCT),CORTEX_M3)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM3
+ STARTUP_FILE = startup_CMSDK_CM3
+ USER_DEFINE = -DCORTEX_M3
+ ARM_CPU_TYPE = --cpu=Cortex-M3
+ GCC_CPU_TYPE = -mcpu=cortex-m3
+ GCC_LINKER_SCRIPT = $(GCC_LINKER_SCRIPT_PATH)/debugtester.ld
+endif
+ifeq ($(CPU_PRODUCT),CORTEX_M4)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM4
+ STARTUP_FILE = startup_CMSDK_CM4
+ USER_DEFINE = -DCORTEX_M4
+ ARM_CPU_TYPE = --cpu=Cortex-M4
+ GCC_CPU_TYPE = -mcpu=cortex-m4
+ GCC_LINKER_SCRIPT = $(GCC_LINKER_SCRIPT_PATH)/debugtester.ld
+endif
+ifeq ($(CPU_PRODUCT),CORTEX_M4F)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM4
+ STARTUP_FILE = startup_CMSDK_CM4
+ USER_DEFINE = -DCORTEX_M4
+ # The debug tester processor for M4F as the target is an M4, so the processor
+ # for compiling the debug tester code must be M4
+ ARM_CPU_TYPE = --cpu=Cortex-M4
+ GCC_CPU_TYPE = -mcpu=cortex-m4
+ GCC_LINKER_SCRIPT = $(GCC_LINKER_SCRIPT_PATH)/debugtester.ld
+endif
+
+# Program file
+DEBUGTESTER = debugtester
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+DEPS_LIST = Makefile debugtester.h cmsdk_debugtester.h
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option (DS-5)
+COMPILE_MICROLIB = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(CORE_DIR) -I $(DEVICE_DIR)/Include \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x20000000 --ro_base 0x00000000 --map
+
+# Big Endian
+ARM_CC_OPTIONS_BE = $(ARM_CC_OPTIONS) -DDEBUGTESTER_BE
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLib
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+# The optimisation level for the GCC compiler should be fixed at -01 or the results can
+# cause unpredictable results for the debugtester behaviour.
+GNU_CC_FLAGS = -g -O1 -mthumb $(GCC_CPU_TYPE)
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(DEBUGTESTER)_le.hex $(DEBUGTESTER)_be.hex $(DEBUGTESTER)_le.lst $(DEBUGTESTER)_be.lst
+
+debugtester_le.o : debugtester.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(ARM_CPU_TYPE) $< -o $@
+
+system_cmsdk_debugtester_le.o : system_cmsdk_debugtester.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(ARM_CPU_TYPE) $< -o $@
+
+retarget_cmsdk_debugtester_le.o : retarget_cmsdk_debugtester.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(ARM_CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(DEVICE_DIR)/Source/ARM/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(ARM_CPU_TYPE) $< -o $@
+
+$(DEBUGTESTER)_le.elf : $(DEBUGTESTER)_le.o $(STARTUP_FILE).o system_cmsdk_debugtester_le.o retarget_cmsdk_debugtester_le.o
+ armlink $(ARM_LINK_OPTIONS) $(DEBUGTESTER)_le.o $(STARTUP_FILE).o system_cmsdk_debugtester_le.o retarget_cmsdk_debugtester_le.o -o $@
+
+$(DEBUGTESTER)_le.hex : $(DEBUGTESTER)_le.elf
+ fromelf --vhx --8x1 $< --output $@
+
+$(DEBUGTESTER)_le.lst : $(DEBUGTESTER)_le.elf
+ fromelf -c -d -e -s $< --output $@
+
+debugtester_be.o : debugtester.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS_BE) $(ARM_CPU_TYPE) $< -o $@
+
+system_cmsdk_debugtester_be.o : system_cmsdk_debugtester.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS_BE) $(ARM_CPU_TYPE) $< -o $@
+
+retarget_cmsdk_debugtester_be.o : retarget_cmsdk_debugtester.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS_BE) $(ARM_CPU_TYPE) $< -o $@
+
+$(DEBUGTESTER)_be.elf : $(DEBUGTESTER)_be.o $(STARTUP_FILE).o system_cmsdk_debugtester_be.o retarget_cmsdk_debugtester_be.o
+ armlink $(ARM_LINK_OPTIONS) $(DEBUGTESTER)_be.o $(STARTUP_FILE).o system_cmsdk_debugtester_be.o retarget_cmsdk_debugtester_be.o -o $@
+
+$(DEBUGTESTER)_be.hex : $(DEBUGTESTER)_be.elf
+ fromelf --vhx --8x1 $< --output $@
+
+$(DEBUGTESTER)_be.lst : $(DEBUGTESTER)_be.elf
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# GCC
+all_gcc : $(DEBUGTESTER)_le $(DEBUGTESTER)_be
+
+$(DEBUGTESTER)_le :
+ $(GNG_CC) $(GNU_CC_FLAGS) $(DEVICE_DIR)/Source/GCC/$(STARTUP_FILE).s \
+ $(DEBUGTESTER).c \
+ system_cmsdk_debugtester.c \
+ retarget_cmsdk_debugtester.c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -L $(GCC_LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(GCC_LINKER_SCRIPT) -o $(DEBUGTESTER)_le.o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(DEBUGTESTER)_le.o > $(DEBUGTESTER)_le.lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(DEBUGTESTER)_le.o -O binary $(DEBUGTESTER)_le.bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(DEBUGTESTER)_le.o -O verilog $(DEBUGTESTER)_le.hex
+
+$(DEBUGTESTER)_be :
+ $(GNG_CC) $(GNU_CC_FLAGS) $(DEVICE_DIR)/Source/GCC/$(STARTUP_FILE).s \
+ $(DEBUGTESTER).c \
+ system_cmsdk_debugtester.c \
+ retarget_cmsdk_debugtester.c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -L $(GCC_LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -DDEBUGTESTER_BE -T $(GCC_LINKER_SCRIPT) -o $(DEBUGTESTER)_be.o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(DEBUGTESTER)_be.o > $(DEBUGTESTER)_be.lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(DEBUGTESTER)_be.o -O binary $(DEBUGTESTER)_be.bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(DEBUGTESTER)_be.o -O verilog $(DEBUGTESTER)_be.hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(DEBUGTESTER)_le.bin > $(DEBUGTESTER)_le.hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(DEBUGTESTER)_le.bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(DEBUGTESTER)_le.bin > $(DEBUGTESTER)_le.hex
+
+
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean:
+ @rm -f *.hex *.bin *.elf *.o *.lst
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/software/debug_tester/cmsdk_debugtester.h b/Cortex-M0/nanosoc/software/debug_tester/cmsdk_debugtester.h
new file mode 100644
index 0000000000000000000000000000000000000000..8e3b9eb112cfa53cacbd11b365f0cb233c8cb9e5
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/cmsdk_debugtester.h
@@ -0,0 +1,336 @@
+//
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+#ifndef __CMSDK_DEBUGTESTER_H__
+#define __CMSDK_DEBUGTESTER_H__
+
+//////////////////////////////////////////////////////////////////////////////////
+////
+//// CMSDK Debug Tester CMSIS Configuration File
+////
+//// This file corresponds to the device.h file in the CMSIS standard,
+//// and defines the peripherals for the Debug Tester device:
+//// IRQ number
+//// IO address mapping and data structures
+//// core configuration etc
+////
+//////////////////////////////////////////////////////////////////////////////////
+
+ //============================================================================
+ //---------- Interrupt Number Definition -------------------------------------
+ //============================================================================
+
+typedef enum IRQn
+{
+/////// Cortex-M Processor Exceptions Numbers /////////////////////////////////////////////////////
+ NonMaskableInt_IRQn = -14, //!< 2 Non Maskable Interrupt //
+ HardFault_IRQn = -13, //!< 3 Cortex-M Hard Fault Interrupt //
+ SVCall_IRQn = -5, //!< 11 Cortex-M SV Call Interrupt //
+ PendSV_IRQn = -2, //!< 14 Cortex-M Pend SV Interrupt //
+ SysTick_IRQn = -1, //!< 15 Cortex-M System Tick Interrupt //
+
+/////// Example MCU Cortex-M specific Interrupt Numbers ///////////////////////////////////////////
+ GPIO_IRQn = 0 //!< GPIO Interrupt //
+} IRQn_Type;
+
+
+//
+// ==========================================================================
+// ----------- Processor and Core Peripheral Section ------------------------
+// ==========================================================================
+//
+
+// Include the appropriate CMSIS core header file
+
+#ifdef CORTEX_M0
+#define __CM0_REV 0x0000 /*!< Core revision r0p0 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#include "core_cm0.h" // Cortex-M0 processor and core peripherals
+
+#else
+
+#ifdef CORTEX_M0PLUS
+#define __CM0_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#include "core_cm0plus.h" // Cortex-M0+ processor and core peripherals
+
+#else
+
+#ifdef CORTEX_M3
+#define __CM3_REV 0x0201 /*!< Core revision r2p1 */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#include "core_cm3.h" // Cortex-M3 processor and core peripherals
+
+#else
+
+#ifdef CORTEX_M4
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#include "core_cm4.h" // Cortex-M4 processor and core peripherals
+
+#endif
+#endif
+#endif
+#endif
+
+#include "system_cmsdk_debugtester.h"
+
+
+// =============================================================================
+// Device Specific Peripheral registers structures //
+// =============================================================================
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+
+/** @addtogroup CMSDK_GPIO CMSDK GPIO
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Offset: 0x000 DATA Register (R/W) */
+ __IO uint32_t DATAOUT; /*!< Offset: 0x004 Data Output Latch Register (R/W) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /*!< Offset: 0x010 Output Enable Set Register (R/W) */
+ __IO uint32_t OUTENABLECLR; /*!< Offset: 0x014 Output Enable Clear Register (R/W) */
+ __IO uint32_t ALTFUNCSET; /*!< Offset: 0x018 Alternate Function Set Register (R/W) */
+ __IO uint32_t ALTFUNCCLR; /*!< Offset: 0x01C Alternate Function Clear Register (R/W) */
+ __IO uint32_t INTENSET; /*!< Offset: 0x020 Interrupt Enable Set Register (R/W) */
+ __IO uint32_t INTENCLR; /*!< Offset: 0x024 Interrupt Enable Clear Register (R/W) */
+ __IO uint32_t INTTYPESET; /*!< Offset: 0x028 Interrupt Type Set Register (R/W) */
+ __IO uint32_t INTTYPECLR; /*!< Offset: 0x02C Interrupt Type Clear Register (R/W) */
+ __IO uint32_t INTPOLSET; /*!< Offset: 0x030 Interrupt Polarity Set Register (R/W) */
+ __IO uint32_t INTPOLCLR; /*!< Offset: 0x034 Interrupt Polarity Clear Register (R/W) */
+ union {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x038 Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x038 Interrupt Clear Register ( /W) */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /*!< Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /*!< Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+/*@}*/ /* end of group CMSDK_GPIO */
+
+
+/*-------------------- Trace Capture Buffer (TCB) -------------------*/
+
+typedef struct
+{
+ __IO uint32_t CONFIG;
+ __I uint32_t DATA;
+ __I uint32_t DEPTH;
+ __I uint32_t SYNCS;
+ __I uint32_t HSYNCS;
+ __I uint32_t STATUS;
+
+} TRACE_TypeDef;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+// =============================================================================
+// Peripheral memory map //
+// =============================================================================
+// Peripheral and SRAM base address //
+#define SRAM_BASE ((uint32_t)0x20000000)
+
+// Peripheral memory map //
+#define GPIO0_BASE ((uint32_t)0x40000000)
+#define GPIO1_BASE ((uint32_t)0x40001000)
+#define TRACE_BASE ((uint32_t)0x40002000)
+
+// =============================================================================
+// Peripheral declaration //
+// =============================================================================
+#define GPIO0 ((CMSDK_GPIO_TypeDef *) GPIO0_BASE)
+#define GPIO1 ((CMSDK_GPIO_TypeDef *) GPIO1_BASE)
+#define TRACE ((TRACE_TypeDef *) TRACE_BASE)
+
+// =============================================================================
+// GPIO 0 Pin Assignments
+// =============================================================================
+
+//
+// Debug tester Hardware Interface to the MCU
+//
+// Debug tester --------------------------------------- Example MCU
+//
+// GPIO[15] 7 >----------------------------------------> Running
+// GPIO[14] 6 >----------------------------------------> Error
+// GPIO[13] 5 <----------------------------------------< Function Strobe
+// GPIO[12] 4 <----------------------------------------< Function Select bit 4
+// GPIO[11] 3 <----------------------------------------< Function Select bit 3
+// GPIO[10] 2 <----------------------------------------< Function Select bit 2
+// GPIO[ 9] 1 <----------------------------------------< Function Select bit 1
+// GPIO[ 8] 0 <----------------------------------------< Function Select bit 0
+//
+//
+
+#define DD_IO_RUNNING (1 << 7)
+#define DD_IO_ERROR (1 << 6)
+#define DD_IO_STROBE (1 << 5)
+#define DD_IO_FUNCSEL 0x1f
+
+
+//
+// JTAG / SerialWire Connectivity
+//
+// Debug tester --------------------------------------- Example MCU
+//
+//
+// GPIO[ 6] 6 >----------------------+
+// |\|
+// GPIO[ 5] 5 >--------------------| >--------+-------<> SWDIOTMS
+// |/ |
+// GPIO[ 4] 4 <-------------------------------+
+// GPIO[ 3] 3 <----------------------------------------< TDO
+// GPIO[ 2] 2 >----------------------------------------> TDI
+// GPIO[ 1] 1 >----------------------------------------> SWCLKTCK
+// GPIO[ 0] 0 >----------------------------------------> nTRST
+//
+//
+
+#define DD_DBG_TMSEN (1 << 6)
+#define DD_DBG_TMS (1 << 5)
+#define DD_DBG_TMSIN (1 << 4)
+#define DD_DBG_TDO (1 << 3)
+#define DD_DBG_TDI (1 << 2)
+#define DD_DBG_SWCLKTCK (1 << 1)
+#define DD_DBG_nTRST (1 << 0)
+
+
+// =============================================================================
+// GPIO 1 Pin Assignments
+// =============================================================================
+
+//
+// Character device for printf and miscellaneous signals
+//
+//
+// GPIO[ 7] 7 >----------------------------------------> Character Strobe
+// GPIO[ 6] 6 >----------------------------------------> \
+// GPIO[ 5] 5 >----------------------------------------> \
+// GPIO[ 4] 4 >----------------------------------------> \ Character
+// GPIO[ 3] 3 >----------------------------------------> > Value
+// GPIO[ 2] 2 >----------------------------------------> /
+// GPIO[ 1] 1 >----------------------------------------> /
+// GPIO[ 0] 0 >----------------------------------------> /
+//
+//
+
+#define DD_PRINT_STROBE (1 << 7)
+#define DD_PRINT_CHAR 0x7F
+
+
+#endif
+
+
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester.c b/Cortex-M0/nanosoc/software/debug_tester/debugtester.c
new file mode 100644
index 0000000000000000000000000000000000000000..a77804361b3cf8f135dc7f47d2064bb2a5b9045e
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester.c
@@ -0,0 +1,2775 @@
+//
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// CMSDK Debug Tester Code
+//
+//////////////////////////////////////////////////////////////////////////////
+
+
+// This code always runs on the Cortex-M processor within the
+// cmsdk_debug_tester.v module in the example testbench.
+//
+// The Debug Tester uses the example components supplied with the CMSDK.
+// You must copy and rename the example components if you wish to
+// modify their behavior, otherwise the Debug Tester may break.
+//
+// This code provides access to various test routines that can use
+// either a SerialWire or JTAG interface to connect to the
+// example MCU.
+//
+// The functions available to the example MCU are enumerated in
+// debugtester_functions.h by the variable "Function". These correspond to
+// actual functions within this file beneath the comment "Functions Available
+// to MCU Core".
+//
+// Communication between the example MCU and the Debug Tester takes place
+// in two ways:
+//
+// [1]
+//
+// Function Calling, Function completion and Error status use a simple
+// handshake using GPIO0. Refer to the main() function in this file,
+// and the functions EnableDebugTester(), DisableDebugTester(),
+// CallDebugtester(), StartDebugtester() and CheckDebugtester() in
+// generic/mcu_debugtester_interface.c for details.
+//
+//
+// [2]
+//
+// Some tests and functions need to pass more complex data between the
+// example MCU and the Debug Tester. For these cases, an area of memory
+// in the example MCU SRAM is predefined as an area for passing values
+// between the Debug Tester and example MCU.
+//
+// The region used is the last 4 words above the stack pointer of the
+// example MCU. The debugtester code reads the example MCU vector table
+// to determine its SP, and therefore the location of these four words.
+//
+// The Debug Tester accesses this region using
+// Cortex_MCU.stacktop and suitable offsets, using the
+// ReadCommRegion() and WriteCommRegion() functions which also handle
+// changing the endianness of the data when required.
+// The example MCU accesses this region using the array
+// DEBUGTESTERDATA, defined in generic/mcu_debugtester_interface.h
+//
+//
+
+#include "cmsdk_debugtester.h" // CMSIS Support for the debugtester
+#include "system_cmsdk_debugtester.h" // CMSIS Support for the debugtester
+#include "debugtester.h" // Local header file
+#include <stdio.h> // Access to printf
+
+// EXPECTED_BE: Expected Endianness <0=> Little Endian <1=> Big Endian
+#ifdef DEBUGTESTER_BE
+#define EXPECTED_BE 1
+#else
+#define EXPECTED_BE 0
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Global Variables
+//////////////////////////////////////////////////////////////////////////////
+
+// Track information about the target
+
+struct {
+ uint32_t stacktop;
+ uint32_t traceconfigured;
+} Cortex_MCU;
+
+
+// Track state of the DAP
+
+struct {
+ uint32_t jtagnsw;
+ uint32_t jtagapndp;
+ uint32_t on;
+ uint32_t banksel;
+ uint32_t csw;
+ uint32_t error;
+ uint8_t ack;
+ uint8_t stkerrclr;
+} DAPSTATUS;
+
+// Trace decompression globals
+uint32_t trace_id = 0x71; // Init to reserved
+uint32_t trace_errors = 0;
+uint8_t etm_packet[6];
+uint32_t etm_bytes=0;
+uint32_t etm_current=0;
+uint32_t itm_current=0;
+uint8_t itm_header;
+uint32_t itm_payload=0;
+uint32_t itm_ts1=0;
+uint32_t itm_ts2=0;
+uint32_t itm_ts1_last=0;
+uint32_t itm_bytes=0;
+uint32_t itm_size=0;
+uint32_t itm_ts=0;
+uint32_t itm_sync=0;
+uint32_t itm_overflow=0;
+uint32_t itm_sw=0;
+uint32_t itm_event=0;
+uint32_t itm_periodic=0;
+uint32_t itm_exception=0;
+uint32_t itm_comp=0;
+uint32_t itm_glb1=0;
+uint32_t itm_glb2=0;
+
+uint32_t current_address = 0;
+uint32_t etm_ts1 = 0;
+uint32_t etm_ts1_last = 0;
+uint32_t etm_ts2 = 0;
+uint32_t etm_p_headers =0;
+uint32_t etm_i_sync =0;
+uint32_t etm_branches =0;
+uint32_t etm_exceptions =0;
+uint32_t etm_rfe =0;
+uint32_t etm_timestamps =0;
+uint32_t etm_triggers =0;
+uint32_t etm_ignore =0; // Expect 0
+uint32_t fmt_triggers =0;
+uint32_t fmt_frames =0;
+uint32_t fmt_etm =0;
+uint32_t fmt_itm =0;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Prototypes
+//////////////////////////////////////////////////////////////////////////////
+
+// SerialWire
+
+uint32_t SWConnect(void);
+uint32_t SWHeader(uint8_t);
+uint32_t SWDataRead(void);
+void SWDataWrite(uint32_t);
+void SerialWireClockOut (uint32_t, uint32_t);
+uint32_t SerialWireClockIn (uint32_t);
+void SWLineReset(uint8_t);
+void SWExitDormantState(void);
+
+
+// JTAG
+
+void JTAGTransition(uint32_t, uint8_t);
+uint64_t JTAGShift(uint64_t, uint8_t);
+uint64_t JTAGScanIDCODE(void);
+void JTAGScanIR(uint32_t);
+uint64_t JTAGScanDR(uint64_t);
+
+
+// Trace
+
+uint32_t ParseTrace(uint8_t);
+
+
+// Wire Protocol Agnostic functions
+
+void pulse_clock(uint8_t);
+void InitDAPSTATUS(void);
+void InitCommRegion(void);
+uint32_t SwapEndian(uint32_t);
+uint32_t ReadCommRegion(uint32_t);
+void WriteCommRegion(uint32_t, uint32_t);
+uint32_t ReadMem(uint32_t);
+uint32_t ReadMemH(uint32_t);
+uint32_t ReadMemB(uint32_t);
+void ReadMemBlock(uint32_t, uint32_t, uint32_t *);
+uint32_t ReadMemSpecial(uint32_t, uint8_t, uint32_t);
+void WriteMem(uint32_t, uint32_t);
+void WriteMemBlock(uint32_t, uint32_t, uint32_t *);
+void WriteMemH(uint32_t, uint32_t);
+void WriteMemB(uint32_t, uint32_t);
+void JtagAPnDP(uint32_t);
+void DPWriteBANKSEL(uint32_t);
+void DPWriteCTRLSTAT(uint32_t);
+uint32_t DPReadCTRLSTAT(void);
+uint32_t APReadCSW(void);
+void APWriteCSW(uint32_t);
+void APWriteTAR(uint32_t);
+uint32_t APReadDRW(void);
+void APWriteDRW(uint32_t);
+uint32_t DPReadRDBUFF(void);
+uint32_t DPReadIDR(void);
+uint32_t APReadIDR(void);
+uint32_t APReadBASE(void);
+uint32_t DPReadHALTEV(void);
+void DPClearSTICKYERR(void);
+uint32_t CheckDAPSTATUS(void);
+
+
+// Prototypes for MCU exposed functions
+uint32_t SetInterfaceJTAG(void);
+uint32_t SetInterfaceSW(void);
+uint32_t DAPPowerUp(void);
+uint32_t DAPPowerDown(void);
+uint32_t GetTAPID(void);
+uint32_t GetDPReg(void);
+uint32_t GetAPReg(void);
+uint32_t GetAPMem(void);
+uint32_t SetAPMem(void);
+uint32_t GetAPMemCSIDs(void);
+uint32_t GetAPMemPID(void);
+uint32_t ConnectWakeUnhalt(void);
+uint32_t ConnectCheckUnlockup(void);
+uint32_t EnableHaltingDebug(void);
+uint32_t DAPAccess(void);
+uint32_t ConfigTrace(void);
+uint32_t CheckTrace(void);
+uint32_t EmptyFunction(void);
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Func points to the functions that will be used by the MCU
+//////////////////////////////////////////////////////////////////////////////
+
+uint32_t (*Func[]) (void) = { SetInterfaceJTAG,
+ SetInterfaceSW,
+ DAPPowerUp,
+ DAPPowerDown,
+ GetTAPID,
+ GetDPReg,
+ GetAPReg,
+ GetAPMem,
+ SetAPMem,
+ GetAPMemCSIDs,
+ ConnectWakeUnhalt,
+ ConnectCheckUnlockup,
+ EnableHaltingDebug,
+ DAPAccess,
+ ConfigTrace,
+ CheckTrace,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction,
+ EmptyFunction
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Main code
+//////////////////////////////////////////////////////////////////////////////
+
+int main (void)
+{
+ uint32_t SelectedFunction;
+
+ //
+ // Initialisation
+ //
+ // GPIO0
+ GPIO0->DATAOUT = 0;
+ GPIO0->OUTENABLESET = ( ((DD_IO_RUNNING | DD_IO_ERROR) << 8) |
+ (DD_DBG_TMSEN | DD_DBG_TMS | DD_DBG_TDI | DD_DBG_SWCLKTCK | DD_DBG_nTRST) );
+ // GPIO1
+ GPIO1->DATAOUT = 0;
+ GPIO1->OUTENABLESET = ( DD_PRINT_STROBE | DD_PRINT_CHAR );
+
+ // Raise nTRST to bring JTAG DAP out of reset
+ GPIO0->DATAOUT = DD_DBG_nTRST;
+
+ // Initialise DAPSTATUS struct
+ InitDAPSTATUS();
+
+ // Initialise example MCU information
+ Cortex_MCU.stacktop = 0;
+ Cortex_MCU.traceconfigured = 0;
+
+ //
+ // Sit in loop waiting to service requests from the MCU cpu core
+ //
+ while(1)
+ {
+ if(GPIO0->UB_MASKED[DD_IO_STROBE])
+ {
+ // Clear any error flag
+ GPIO0->UB_MASKED[DD_IO_ERROR] = 0;
+
+ // Work out which routine to execute
+ SelectedFunction = (GPIO0->UB_MASKED[DD_IO_FUNCSEL]) >> 8;
+
+ // Indicate that we are running
+ GPIO0->UB_MASKED[DD_IO_RUNNING] = DD_IO_RUNNING << 8;
+
+ // Wait for deassertion of strobe
+ while(GPIO0->UB_MASKED[DD_IO_STROBE]);
+
+ // Run it
+ if( (*Func[SelectedFunction])() != 0 )
+ {
+ // Flag an error
+ GPIO0->UB_MASKED[DD_IO_ERROR] = DD_IO_ERROR << 8;
+ };
+
+ // Indicate that we are finished
+ GPIO0->UB_MASKED[DD_IO_RUNNING] = 0;
+ DBG_MSG(("Selected function run finished, wait for new function\n"));
+ }
+ }
+}
+
+
+//============================================================================
+//
+// Functions Available to MCU Core
+//
+//============================================================================
+
+uint32_t SetInterfaceJTAG()
+{
+ // Switch to JTAG mode
+ DBG_MSG(("SetInterfaceJTAG()\n"));
+ if(DAPSTATUS.on)
+ {
+ DBG_MSG(("SetInterfaceJTAG() TEST FAILED: DAP power on\n"));
+ return TEST_FAIL;
+ }
+ else
+ {
+ // Update struct
+ DAPSTATUS.jtagnsw = 1;
+
+ // JTAG - We'll always be driving TMS
+ GPIO0->LB_MASKED[DD_DBG_TMSEN] = DD_DBG_TMSEN;
+
+ // Ensure we are in TLR by clocking in 5 TMS high cycles
+ JTAGTransition(0xff, 5);
+
+ // Get into RTI as our default initial state
+ JTAGTransition(0, 1);
+
+ return TEST_PASS;
+ }
+}
+
+
+uint32_t SetInterfaceSW()
+{
+ // Switch to SerialWire mode
+ DBG_MSG(("SetInterfaceSW()\n"));
+ if(DAPSTATUS.on)
+ {
+ DBG_MSG(("SetInterfaceSW() TEST FAIL: DAP power on\n"));
+ return TEST_FAIL;
+ }
+ else
+ {
+ // Initialise
+ DAPSTATUS.jtagnsw = 0;
+ return SWConnect();
+ }
+}
+
+
+uint32_t DAPPowerUp()
+{
+ DBG_MSG(("DAPPowerUp()\n"));
+ if(DAPSTATUS.on == 0)
+ {
+ DPWriteCTRLSTAT( 0x50000000 );
+
+ // Wait for the effect of write
+ while((DPReadCTRLSTAT() & 0xF0000000UL) != 0xF0000000UL);
+
+ DAPSTATUS.on=1;
+ return CheckDAPSTATUS();
+ }
+ DBG_MSG(("DAPPowerUp() FAIL\n"));
+ return TEST_FAIL;
+}
+
+
+uint32_t DAPPowerDown()
+{
+ uint32_t jtagnsw;
+ uint32_t error;
+
+ DBG_MSG(("DAPPowerDown()\n"));
+ if(DAPSTATUS.on == 1)
+ {
+ DPWriteCTRLSTAT( 0x0 );
+
+ // Wait for the effect of write
+ while((DPReadCTRLSTAT() & 0xF0000000UL) != 0 );
+
+ // Re-Initialise DAPSTATUS, but preserve jtagnsw and error
+ jtagnsw = DAPSTATUS.jtagnsw;
+ error = DAPSTATUS.error;
+ InitDAPSTATUS();
+ DAPSTATUS.jtagnsw = jtagnsw;
+ DAPSTATUS.error = error;
+ return CheckDAPSTATUS();
+ }
+ DBG_MSG(("DAPPowerDown(): FAIL\n"));
+ return TEST_FAIL;
+}
+
+
+// Following functions all use the Comms Region
+
+uint32_t GetTAPID()
+{
+ DBG_MSG(("GetTAPID()\n"));
+ InitCommRegion();
+ if(DAPSTATUS.jtagnsw == 1)
+ {
+ WriteCommRegion(0, (JTAGScanIDCODE() & 0xFFFFFFFFUL) );
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t GetDPReg()
+{
+ uint32_t dpreg;
+ uint32_t value;
+
+ DBG_MSG(("GetDPReg()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+
+ dpreg = ReadCommRegion(0);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(DP);
+ JTAGScanDR(JTAG_SCAN(dpreg,READ));
+ value = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader(SW_HEADER(DP, READ, dpreg));
+ value = SWDataRead();
+ }
+
+ WriteCommRegion(0, value);
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t GetAPReg()
+{
+ uint32_t apreg;
+ uint32_t value;
+
+ DBG_MSG(("GetAPReg()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+ apreg = ReadCommRegion(0);
+
+ DPWriteBANKSEL( (apreg >> 4) & 0xF );
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(AP);
+ JTAGScanDR(JTAG_SCAN(apreg,READ));
+ value = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, READ, apreg) );
+ SWDataRead();
+ value = DPReadRDBUFF();
+ }
+ WriteCommRegion(0, value);
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t GetAPMem()
+{
+ uint32_t addr;
+ uint32_t value;
+
+ DBG_MSG(("GetAPMem()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+ addr = ReadCommRegion(0);
+ DBG_MSG(("GetAPMem(%x)\n",addr));
+
+ value = ReadMem(addr);
+ DBG_MSG(("GetAPMem(%x) returned %x\n", addr, value));
+
+ WriteCommRegion(0, value);
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t SetAPMem()
+{
+ uint32_t addr;
+ uint32_t value;
+
+ DBG_MSG(("SetAPMem()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+ addr = ReadCommRegion(0);
+ value = ReadCommRegion(1);
+
+ if(addr&0x3 == 0)
+ {
+ WriteMem(addr, value);
+ return CheckDAPSTATUS();
+ }
+
+ DBG_MSG(("Only WORD writes are supported\n"));
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t GetAPMemCSIDs()
+{
+ //
+ // Use the Comm Region to return the CoreSight PID and CID values
+ //
+ // Pack the four byte values CID0-CID3 into one word
+ // Pack the four byte values PID0-PID3 into one word
+ // Pack the four byte values PID4-PID7 into one word
+ //
+
+ uint32_t component_base;
+
+ uint32_t csids[12];
+
+ uint32_t cid;
+ uint32_t pid_lo;
+ uint32_t pid_hi;
+
+ DBG_MSG(("GetAPMemCSIDs()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+ component_base = ReadCommRegion(0);
+
+ // Read all 12 ID locations in one operation
+ ReadMemBlock((component_base + PID4_OFFSET), 12, csids);
+
+ // Pack CID and PID information into 3 words
+
+ // PID4 (0xFD0)
+ pid_hi = (csids[0] & 0xFF);
+
+ // PID5 (0xFD4)
+ pid_hi |= ((csids[1] & 0xFF) << 8);
+
+ // PID6 (0xFD8)
+ pid_hi |= ((csids[2] & 0xFF) << 16);
+
+ // PID7 (0xFDC)
+ pid_hi |= ((csids[3] & 0xFF) << 24);
+
+ // PID0 (0xFE0)
+ pid_lo = (csids[4] & 0xFF);
+
+ // PID1 (0xFE4)
+ pid_lo |= ((csids[5] & 0xFF) << 8);
+
+ // PID2 (0xFE8)
+ pid_lo |= ((csids[6] & 0xFF) << 16);
+
+ // PID3 (0xFEC)
+ pid_lo |= ((csids[7] & 0xFF) << 24);
+
+ // CID0 (0xFF0)
+ cid = (csids[8] & 0xFF);
+
+ // CID1 (0xFF4)
+ cid |= ((csids[9] & 0xFF) << 8);
+
+ // CID2 (0xFF8)
+ cid |= ((csids[10] & 0xFF) << 16);
+
+ // CID3 (0xFFC)
+ cid |= ((csids[11] & 0xFF) << 24);
+
+ WriteCommRegion(0, cid);
+ WriteCommRegion(1, pid_lo);
+ WriteCommRegion(2, pid_hi);
+
+ return CheckDAPSTATUS();
+ }
+
+ return TEST_FAIL;
+}
+
+
+uint32_t ConnectWakeUnhalt()
+{
+ //
+ // Used to wake core up when sleeping
+ //
+
+ uint32_t data;
+
+ // Connect - Done by SetMode*
+ DBG_MSG(("ConnectWakeUnhalt()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+
+ // Check S_SLEEP
+ data=ReadMem(DHCSR_ADDR);
+
+ if(data & S_SLEEP)
+ {
+ DBG_MSG(("Seen S_SLEEP\n"));
+
+ // Core is sleeping, so set halting debug enable
+ WriteMem(DHCSR_ADDR, (DBGKEY | C_HALT | C_DEBUGEN) );
+ DBG_MSG(("Written C_HALT\n"));
+
+ // Wait for core to be halted
+ while((ReadMem(DHCSR_ADDR) & S_HALT) == 0);
+ DBG_MSG(("Seen S_HALT\n"));
+
+ // Write flag into DATA[0] to allow example MCU code to escape its loop
+ WriteCommRegion(0, 1);
+ DBG_MSG(("Written flag\n"));
+
+ // Clear Halt and debug enables
+ WriteMem(DHCSR_ADDR, DBGKEY);
+ DBG_MSG(("Cleared halt\n"));
+
+ return CheckDAPSTATUS();
+ }
+
+ DBG_MSG(("Core not sleeping\n"));
+ return TEST_FAIL;
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t EnableHaltingDebug()
+{
+ DBG_MSG(("EnableHaltingDebug()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ // Set C_DEBUGEN bit
+ DBG_MSG(("EnableHaltingDebug()\n"));
+
+ // Set Debug enable
+ WriteMem(DHCSR_ADDR, (DBGKEY | C_DEBUGEN) );
+ DBG_MSG(("Written C_DEBUGEN\n"));
+
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t ConnectCheckUnlockup()
+{
+ uint32_t value;
+
+ DBG_MSG(("ConnectCheckUnlockup()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+
+ // Check for S_LOCKUP
+ if(ReadMem(DHCSR_ADDR) & S_LOCKUP)
+ {
+ DBG_MSG(("Seen S_LOCKUP\n"));
+
+ // Halt the core
+ WriteMem(DHCSR_ADDR, (DBGKEY | C_HALT | C_DEBUGEN) );
+ DBG_MSG(("Written C_HALT\n"));
+
+ // Wait for core to be halted
+ while((ReadMem(DHCSR_ADDR) & S_HALT) == 0);
+ DBG_MSG(("Seen S_HALT\n"));
+
+
+ // Replace faulting code sequence with a non-faulting
+ // sequence at the same address, to allow the core to
+ // exit HardFault and continue the main() code.
+
+ // Get non-faulting value
+ value = ReadCommRegion(2); // Reads from (Cortex_MCU.stacktop + 0x8)
+
+ // Write to execution location
+ WriteCommRegion(3, value); // Writes to (Cortex_MCU.stacktop + 0xC)
+
+ //Get the RETURN register value
+ WriteMem(DCRSR_ADDR, (DebugReturnAddress));
+ while( (ReadMem(DHCSR_ADDR) & S_REGRDY) == 0 );
+ value = ReadMem(DCRDR_ADDR);
+ DBG_MSG(("Current DebugReturnAddress= %x\n", value));
+
+
+ // Write address of the (now non-faulting) function
+ // as the DebugReturnAddress
+ value = (Cortex_MCU.stacktop + 0xC);
+ WriteMem(DCRDR_ADDR, value);
+ WriteMem(DCRSR_ADDR, (REGWnR | DebugReturnAddress));
+ while( (ReadMem(DHCSR_ADDR) & S_REGRDY) == 0 );
+ DBG_MSG(("Wrote return address= %x\n", value));
+
+ // Unhalt
+ WriteMem(DHCSR_ADDR, DBGKEY);
+ DBG_MSG(("Cleared C_HALT\n"));
+
+ return CheckDAPSTATUS();
+ }
+ DBG_MSG(("Core not in lockup\n"));
+ return TEST_FAIL;
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t DAPAccess()
+{
+ //
+ // Perform WORD, HALFWORD, and BYTE accesses
+ //
+
+ uint32_t retval = 0;
+
+ DBG_MSG(("DAPAccess()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+
+ // Zero a WORD
+ WriteMem(Cortex_MCU.stacktop, 0);
+
+ // Check WORD reads as zero
+ if(ReadMem(Cortex_MCU.stacktop) == 0)
+ {
+ retval |= 0x1;
+ DBG_MSG(("Word was clear\n"));
+ }
+
+ // Write a HALFWORD
+ WriteMemH((Cortex_MCU.stacktop + 2), 0x3456);
+
+ // Read a WORD, check for expected value
+ if(ReadMem(Cortex_MCU.stacktop) == 0x34560000)
+ {
+ retval |= 0x2;
+ DBG_MSG(("Read back correct value\n"));
+ }
+ else
+ {
+ DBG_MSG(("Incorrect value - FAIL\n"));
+ }
+
+ // Write a BYTE
+ WriteMemB((Cortex_MCU.stacktop + 1), 0x12);
+
+ // Read a WORD, check for expected value
+ if(ReadMem(Cortex_MCU.stacktop) == 0x34561200)
+ {
+ retval |= 0x4;
+ DBG_MSG(("Read back correct value\n"));
+ }
+ else
+ {
+ DBG_MSG(("Incorrect value - FAIL\n"));
+ }
+
+ WriteCommRegion(0, retval);
+ DBG_MSG(("Written retval: %x\n", retval));
+
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t ConfigTrace(void)
+{
+ //
+ // Function to provide support for trace testing.
+ // Initialise the trace capture, and should be after
+ // trace port has been set-up.
+ //
+
+ DBG_MSG(("ConfigTrace()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ InitCommRegion();
+ // Get config to use from test core.
+ TRACE->CONFIG = ReadCommRegion(0); // Reads from (Cortex_MCU.stacktop);
+ DBG_MSG(("TRACE->CONFIG= %x\n",TRACE->CONFIG));
+ Cortex_MCU.traceconfigured = 1;
+ return CheckDAPSTATUS();
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t CheckTrace(void)
+{
+ //
+ // Function to provide support for trace testing.
+ // Read formatted data from buffer and
+ // decompress individual streams
+ //
+ // Trace is printed, and also counted to allow tests to check
+ // the relevant packets were generated
+ //
+
+ uint32_t i = 7;
+ uint32_t frame_buffer[4];
+ uint32_t lsb_bits;
+
+ DBG_MSG(("CheckTrace()\n"));
+
+ if(DAPSTATUS.on)
+ {
+ if(Cortex_MCU.traceconfigured == 0)
+ {
+ DBG_MSG(("ERROR : ConfigTrace has not been ran before CheckTrace, or CheckTrace executed again without rerunning ConfigTrace\n"));
+ return TEST_FAIL;
+ }
+ else
+ {
+ InitCommRegion();
+
+ // Set Cortex_MCU.traceconfigured = 0 again to reconfigure trace next time when
+ // it is called. This make it possible for testing ITM/ITMSW/DTM/DTMSW
+ // in one main file.
+ Cortex_MCU.traceconfigured = 0;
+
+ DBG_MSG(("Trace Decompress\n"));
+ DBG_MSG(("initial i= %x, trace_errors=%x\n", i, trace_errors));
+ DBG_MSG(("initial TRACE->DEPTH = %x\n", TRACE->DEPTH));
+ DBG_MSG(("initial TRACE->STATUS = %x\n", TRACE->STATUS));
+ if ((TRACE->DEPTH ==0) &((TRACE->STATUS & 0x8)==0)) { //Trace depth is zero and no overflow
+ DBG_MSG(("No trace captured\n"));
+
+ return TEST_FAIL;
+ }
+
+ if ((TRACE->STATUS & 0x8)==0x8) { //Trace capture buffer overflow
+ DBG_MSG(("Trace capture buffer overflow\n"));
+ return TEST_FAIL;
+ }
+ DBG_MSG(("initial i= %x, trace_errors=%x\n", i, trace_errors));
+ // Grab frame of data
+ while((i==7) && (trace_errors == 0))
+ {
+ DBG_MSG(("."));
+ for(i=0;i<4;i++)
+ {
+ frame_buffer[i] = TRACE->DATA;
+ if (frame_buffer[i] == 0x7FFFFFFFUL)
+ {
+ if (i==0)
+ {
+ DBG_MSG(("No more Frames\n"));
+ i=5;
+ }
+ else
+ {
+ DBG_MSG(("Incomplete Frame. At %d, %08x:%08x:%08x:%08x:\n",i,
+ frame_buffer[0],frame_buffer[1],frame_buffer[2],frame_buffer[3]));
+ i=5;
+ trace_errors++;
+ }
+ }
+ }
+ // Decompress frame
+ if(i==4)
+ {
+ fmt_frames++;;
+ lsb_bits = frame_buffer[3] >> 24;
+ for(i=0;i<7;i++)
+ {
+ if((frame_buffer[i/2] & 0x1) == 0x1)
+ {
+ if ((lsb_bits & 1) == 1)
+ {
+ ParseTrace(((frame_buffer[i/2]) >> 8) & 0xFF);
+ trace_id = (((frame_buffer[i/2]) >> 1) & 0x7F);
+ }
+ else
+ {
+ trace_id = (((frame_buffer[i/2]) >> 1) & 0x7F);
+ ParseTrace(((frame_buffer[i/2]) >> 8) & 0xFF);
+ }
+ }
+ else
+ {
+ ParseTrace((frame_buffer[i/2] & 0xFE) |
+ (lsb_bits & 1));
+ ParseTrace(((frame_buffer[i/2]) >> 8) & 0xFF);
+ }
+ frame_buffer[i/2] = ((frame_buffer[i/2]) >> 16);
+ lsb_bits = lsb_bits >> 1;
+ }
+ // Byte 14 handled outside of loop Should not be early ID
+ if((frame_buffer[3] & 0x1) == 1)
+ {
+ if(lsb_bits != 0 )
+ {
+ trace_errors ++;
+ DBG_MSG(("\nByte 14 is ID with LSB set, should be data\n"));
+ }
+ else
+ {
+ trace_id = ((frame_buffer[3] >> 1) & 0x7F);
+ }
+ }
+ else
+ {
+ ParseTrace((frame_buffer[3] & 0xFE) | lsb_bits);
+ }
+ }
+ }
+ DBG_MSG(("\nTrace extraction done, %d\n",trace_errors));
+ // Write trace statistics into MCU memmory. May be some corruption if counts are too large
+ // Maximum of 256 frames, 3840 ETM bytes
+ // [0] fmt_trig[2], fmt_itm[10], fmt_etm[12], fmt_frames[8]
+ // [1] exceptions[4], branches[8], Isync[6], p_headers [14]
+ // [2] itm_sync[2] itm_overflow[2], itm_glb2[4], itm_glb1[8], triggers[2], ignore [2], timestamps[8], rfe[4]
+ // [3] itm_ts[5], itm_sw[5], itm_event[6], itm_periodic[5], itm_exception[5], itm_comp[6]
+ WriteCommRegion(0, ((fmt_triggers << 30) | (fmt_itm << 20) | (fmt_etm <<8) | fmt_frames) );
+ WriteCommRegion(1, (etm_p_headers | etm_i_sync <<14 | etm_branches<<20| etm_exceptions<<28));
+ WriteCommRegion(2, (etm_rfe | etm_timestamps<<4 | etm_ignore<<12 | etm_triggers <<14 |
+ itm_glb1 << 16 | itm_glb2 << 24 | itm_overflow <<28 | itm_sync << 2));
+ WriteCommRegion(3, (itm_ts<<27 | itm_sw<<22 | itm_event <<16 | itm_periodic <<11 | itm_exception <<6 | itm_comp));
+
+ return trace_errors;
+ }
+ }
+ return TEST_FAIL;
+}
+
+
+uint32_t ParseTrace(uint8_t new_byte)
+{
+ // ID 0 is null, used for padding. Although not architected, expect to only see data=0
+ //
+ switch (trace_id)
+ {
+ case 0:
+ if(new_byte != 0)
+ {
+ DBG_MSG(("NULL ID (0) with non-zero data byte:%02x\n",new_byte));
+ trace_errors++;
+ }
+ break;
+
+ case MCU_ETM_ID:
+
+ fmt_etm++;
+ TRC_MSG(("%02x ",new_byte));
+ switch (etm_current)
+ {
+ case 00:
+ if(new_byte==0) // Sync Packet
+ {
+ etm_current = 1;
+ etm_bytes++;
+ }
+ else if((new_byte & 1) ==1) // Branch Packet
+ {
+ current_address = (current_address & 0xFFFFFF80UL) |
+ (new_byte & 0x7E);
+ if((new_byte & 0x80)==0x80)
+ {
+ etm_current = 2;
+ etm_packet[0] = new_byte;
+ etm_bytes++;
+ }
+ else
+ {
+ TRC_MSG(("Branch to %08x\n",current_address));
+ etm_branches++;
+ }
+ }
+ else if(new_byte ==0x08) // I-Sync packet
+ {
+ etm_current = 4;
+ }
+ else if(new_byte ==0x0C) // Trigger, single byte
+ {
+ TRC_MSG(("ETM Trigger\n"));
+ etm_triggers++;
+ }
+ else if(new_byte ==0x66) // Ignore, single byte
+ {
+ TRC_MSG(("ETM Ignore byte\n"));
+ etm_ignore++;
+ }
+ else if(new_byte ==0x76) // RFE, single byte
+ {
+ TRC_MSG(("ETM Exception Return\n"));
+ etm_rfe++;
+ }
+ else if((new_byte & 0x80 )== 0x80) // P-header, single byte
+ {
+ etm_p_headers++;
+ TRC_MSG(("P-header, "));
+ if((new_byte & 0x3) == 0) {
+ if((new_byte & 0x3C) !=0) {
+ TRC_MSG(("%d CC pass ",(new_byte & 0x3C)>>2));
+ }
+ if((new_byte & 0x40) !=0) {
+ TRC_MSG(("1 CC Fail "));
+ }
+ TRC_MSG(("\n"));
+ }
+ else
+ {
+ if((new_byte & 0xF0) != 0x80)
+ {
+ DBG_MSG(("Bad P-Header\n"));
+ trace_errors++;
+ }
+ etm_p_headers++;
+ if((new_byte & 0x8) == 0x0)
+ {
+ TRC_MSG(("CC-Pass,"));
+ }
+ else
+ {
+ TRC_MSG(("CC-Fail,"));
+ }
+ if((new_byte & 0x4) == 0x0)
+ {
+ TRC_MSG(("CC-Pass\n"));
+ }
+ else
+ {
+ TRC_MSG(("CC-Fail\n"));
+ }
+ }
+ }
+ else if((new_byte | 0x04 )== 0x46) // Timestamp
+ {
+ etm_current = 8;
+ etm_bytes=0;
+ TRC_MSG(("ETM Timestamp, R-bit%d\n",(new_byte>>2) & 1));
+ etm_timestamps++;
+ }
+ else
+ {
+ trace_errors++;
+ DBG_MSG(("Bad ETM Byte\n"));
+ TRC_MSG(("Header %02x Unknown\n",new_byte));
+ }
+ break;
+ case 0x01: // Sync packet. 0x00 or 0x80
+ if(new_byte==0)
+ {
+ etm_bytes++;
+ }
+ else if(new_byte==0x80)
+ {
+ etm_bytes=0;
+ etm_current = 0;
+ TRC_MSG(("Sync Packet\n"));
+ }
+ break;
+ case 0x02: // Branch Packet. Uses continuation bits
+ etm_packet[etm_bytes] = new_byte;
+ etm_bytes++;
+ if((new_byte >>7) == 0)
+ {
+ switch (etm_bytes)
+ {
+ case 2: // bits[12:7]
+ current_address = (current_address & 0xFFFFD07F) | ((new_byte & 0x3E) << 6);
+ break;
+ case 3: // bits[19:14]
+ current_address = (current_address & 0xFFF03FFF) | ((new_byte & 0x3E) << 13);
+ break;
+ case 4: // bits[26:21]
+ current_address = (current_address & 0xF81FFFFF) | ((new_byte & 0x3E) << 20);
+ break;
+ case 5: // bits[31:28]
+ trace_errors++;
+ DBG_MSG(("Branch Packet Too long\n"));
+ break;
+ }
+ TRC_MSG(("Branch Packet - Address %08x\n",current_address));
+ etm_branches++;
+ etm_bytes = 0;
+ // Check for exception bytes
+ if((new_byte >>6) == 0)
+ {
+ etm_current = 0;
+ }
+ else
+ {
+ etm_current = 0x10;
+ }
+ }
+ else
+ {
+ if(etm_bytes > 6) {
+ DBG_MSG(("Branch Packet too long\n"));
+ trace_errors++;
+ switch (etm_bytes)
+ {
+ case 2: // bits[13:7]
+ current_address = (current_address & 0xFFFFC07F) | ((new_byte & 0x7E) << 6);
+ break;
+ case 3: // bits[20:14]
+ current_address = (current_address & 0xFFE03FFF) | ((new_byte & 0x7E) << 13);
+ break;
+ case 4: // bits[27:21]
+ current_address = (current_address & 0xF01FFFFF) | ((new_byte & 0x7E) << 20);
+ break;
+ case 5: // bits[31:28]
+ current_address = (current_address & 0x0FFFFFFF) | ((new_byte & 0x7E) << 27);
+ break;
+ }
+ }
+ }
+ break;
+ case 0x04: // I-sync packet. Fixed length for CM3-ETM / CM4-ETM
+ etm_packet[etm_bytes] = new_byte;
+ etm_bytes++;
+ if(etm_bytes == 5)
+ {
+ current_address = (etm_packet[1] & 0xFE) |
+ (etm_packet[2] << 8) | (etm_packet[3] << 16) | (etm_packet[4] << 24) ;
+ if((etm_packet[0] & 0x9F) != 0x01)
+ {
+ trace_errors++;
+ DBG_MSG(("Bad Isync information byte %02x\n",etm_packet[0]));
+ }
+ TRC_MSG(("I-Sync Packet "));
+ switch(etm_packet[0]>>5 & 3)
+ {
+ case 0: TRC_MSG(("Periodic"));
+ break;
+ case 1: TRC_MSG(("Trc On"));
+ break;
+ case 2: TRC_MSG(("Overflow"));
+ break;
+ case 3: TRC_MSG(("Debug"));
+ }
+ TRC_MSG((", Address %08x\n",current_address));
+ etm_i_sync++;
+ etm_bytes = 0;
+ etm_current = 0;
+ }
+ break;
+ case 0x08: // Timestamp Packet
+ etm_bytes++;
+ switch (etm_bytes)
+ {
+ case 1:
+ etm_ts1 = (etm_ts1 & 0xFFFFFF80UL) | (new_byte & 0x7F);
+ break;
+ case 2:
+ etm_ts1 = (etm_ts1 & 0xFFFFC07FUL) | (new_byte & 0x7F)<<7;
+ break;
+ case 3:
+ etm_ts1 = (etm_ts1 & 0xFFE03FFFUL) | (new_byte & 0x7F)<<14;
+ break;
+ case 4:
+ etm_ts1 = (etm_ts1 & 0xF01FFFFFUL) | (new_byte & 0x7F)<<21;
+ break;
+ case 5:
+ etm_ts1 = (etm_ts1 & 0x0FFFFFFFUL) | (new_byte & 0x0F)<<28;
+ etm_ts2 = (etm_ts2 & 0xFFFFFFF8UL) | (new_byte & 0x70)>>4;
+ break;
+ case 6:
+ etm_ts2 = (etm_ts2 & 0xFFFFFC07UL) | (new_byte & 0x7F)<<3;
+ break;
+ case 7:
+ etm_ts2 = (etm_ts2 & 0xFFFF03FFUL) | (new_byte & 0x3F)<<10;
+ if(new_byte & 0xC0 !=0)
+ {
+ DBG_MSG(("Last timestamp byte should have [7:6]=00\n"));
+ trace_errors++;
+ etm_current = 0;
+ }
+ break;
+ }
+ if((new_byte >> 7) ==0)
+ {
+ if ((etm_ts1 < etm_ts1_last) & etm_bytes <5)
+ {
+ DBG_MSG(("Timestamp must increase\n"));
+ trace_errors++;
+ }
+ TRC_MSG(("ETM Timestamp %04x%08x\n",etm_ts2,etm_ts1));
+ etm_current = 0;
+ etm_bytes=0;
+ }
+ break;
+ case 0x10: // Exception packet
+ etm_bytes++;
+ if((new_byte>>7) == 0)
+ {
+ etm_bytes=0;
+ etm_current = 0;
+ TRC_MSG(("Exception Taken\n"));
+ etm_exceptions++;
+ }
+ else
+ {
+ if(etm_bytes > 2)
+ {
+ trace_errors++;
+ DBG_MSG(("Exception packet too long\n"));
+ }
+ }
+ break;
+ default:
+ DBG_MSG(("Trace parser crashed\n"));
+ trace_errors++;
+ break;
+ }
+ break;
+
+ case MCU_ITM_ID:
+
+ DBG_MSG(("ITM:%02x\n",new_byte));
+ fmt_itm++;
+ switch (itm_current)
+ {
+ case 0x00:
+ if(new_byte == 00)
+ {
+ itm_current = 1; // Sync
+ itm_bytes=1;
+ }
+ else if(new_byte == 0x70) // Overflow
+ {
+ itm_overflow++;
+ TRC_MSG(("ITM Overflow\n"));
+ }
+ else if((new_byte & 0x0F) == 0) // local timestamp
+ {
+ if ((new_byte & 0x80) == 0) // single byte TS
+ {
+ TRC_MSG(("ITM TS :%d\n",(new_byte & 0x70) >> 4));
+ itm_ts++;
+ }
+ else
+ {
+ itm_current = 2;
+ itm_header = new_byte;
+ itm_payload = 0;
+ itm_bytes=1;
+ }
+ }
+ else if(new_byte == 0x94) // ts1
+ {
+ itm_current = 4;
+ itm_header = new_byte;
+ itm_payload = 0;
+ itm_bytes=1;
+ }
+ else if(new_byte == 0xB4) // ts2
+ {
+ itm_current = 8;
+ itm_header = new_byte;
+ itm_payload = 0;
+ itm_bytes=1;
+ }
+ else if((new_byte & 0x3) != 0) // Stimulus packet
+ {
+ itm_current = 16;
+ itm_header = new_byte;
+ itm_payload = 0;
+ itm_bytes=0;
+ switch (new_byte & 0x3)
+ {
+ case 1: itm_size = 1;
+ break;
+ case 2: itm_size = 2;
+ break;
+ case 3: itm_size = 4;
+ break;
+ }
+ }
+ else
+ {
+ trace_errors++;
+ DBG_MSG(("Un-recognised ITM\n"));
+ TRC_MSG((" BAD Header %02x\n",new_byte));
+ }
+ break;
+ case 0x01:
+ itm_bytes ++;
+ if(new_byte == 0x80)
+ {
+ TRC_MSG(("ITM Sync\n"));
+ itm_sync++;
+ itm_current = 0;
+ itm_bytes = 0;
+ }
+ if((new_byte & 0x7F) != 0)
+ {
+ trace_errors++;
+ itm_current = 0;
+ itm_bytes = 0;
+ DBG_MSG(("ITM Bad sync byte %02x\n",new_byte));
+ }
+ break;
+ case 0x02:
+ itm_payload = (itm_payload <<7) | (new_byte & 0x7F);
+ if ((new_byte & 0x80) == 0)
+ {
+ switch (itm_header>>4 & 3)
+ {
+ case 0: TRC_MSG(("ITM TS delta:%d\n",itm_payload));
+ break;
+ case 1: TRC_MSG(("ITM Late TS :%d\n",itm_payload));
+ break;
+ case 2: TRC_MSG(("ITM TS for delayed packet :%d\n",itm_payload));
+ break;
+ case 3: TRC_MSG(("ITM late TS for delayed packet:%d\n",itm_payload));
+ break;
+ }
+ itm_ts++;
+ itm_current = 0;
+ itm_bytes =0;
+ }
+ else
+ {
+ itm_bytes++;
+ if (itm_bytes > 5)
+ {
+ trace_errors++;
+ DBG_MSG(("ITM timestamp packet too long\n"));
+ itm_current = 0;
+ itm_bytes =0;
+ }
+ }
+ break;
+ case 0x04:
+ switch (itm_bytes)
+ {
+ case 1:
+ itm_ts1 = (itm_ts1 & 0xFFFFFF10) | (new_byte & 0x7f);
+ break;
+ case 2:
+ itm_ts1 = (itm_ts1 & 0xFFFFC07F) | ((new_byte & 0x7f) <<7);
+ break;
+ case 3:
+ itm_ts1 = (itm_ts1 & 0xFFF03FFF) | ((new_byte & 0x7f) <<14);
+ break;
+ case 4:
+ itm_ts1 = (itm_ts1 & 0xFF10FFFF) | ((new_byte & 0x7f) <<21);
+ break;
+ }
+ itm_bytes++;
+ if((new_byte & 0x80) == 0x00)
+ {
+ TRC_MSG(("ITM Global TS1 :%d\n",itm_ts1 & 0x03FFFFFFUL));
+ itm_glb1 ++;
+ if(itm_ts1 > 0)
+ {
+ if((itm_ts1 < itm_ts1_last) & (new_byte & 0x40 == 0x00))
+ {
+ DBG_MSG(("Timestamp should increase"));
+ trace_errors++;
+ }
+ itm_ts1_last = itm_ts1;
+ }
+ if (itm_bytes == 5)
+ {
+ if((new_byte & 0x20) == 0x20)
+ {
+ TRC_MSG(("ITM Global Clock Change\n"));
+ }
+ if((new_byte & 0x40) == 0x40)
+ {
+ TRC_MSG(("ITM Global low count bits wrapped\n"));
+ }
+ }
+ itm_current = 0;
+ }
+ else
+ {
+ if (itm_bytes == 5)
+ {
+ DBG_MSG(("ITM TS1 too long\n"));
+ trace_errors++;
+ itm_current = 0;
+ itm_bytes =0;
+ }
+ }
+ break;
+ case 0x08:
+ switch (itm_bytes)
+ {
+ case 1:
+ itm_ts2 = (itm_ts2 & 0xFFFFFF10) | (new_byte & 0x7f);
+ break;
+ case 2:
+ itm_ts2 = (itm_ts2 & 0xFFFFC07F) | ((new_byte & 0x7f) <<7);
+ break;
+ case 3:
+ itm_ts2 = (itm_ts2 & 0xFFF03FFF) | ((new_byte & 0x7f) <<14);
+ break;
+ case 4:
+ itm_ts2 = (itm_ts2 & 0xFF10FFFF) | ((new_byte & 0x7f) <<21);
+ break;
+ }
+ itm_bytes++;
+ if((new_byte & 0x80) == 0x00)
+ {
+ TRC_MSG(("ITM Global TS2 :%d\n",itm_ts2 & 0x007FFFFFUL));
+ itm_glb2 ++;
+ if (itm_bytes == 5)
+ {
+ if(new_byte & 0xFE != 0x00)
+ {
+ DBG_MSG(("ITM TS2 byte 5 can only have bit[0] set\n"));
+ trace_errors++;
+ }
+ }
+ itm_current = 0;
+ }
+ else
+ {
+ if (itm_bytes == 5)
+ {
+ DBG_MSG(("ITM TS2 too long\n"));
+ trace_errors++;
+ itm_current = 0;
+ itm_bytes =0;
+ }
+ }
+ break;
+ case 0x10:
+ itm_payload = itm_payload | (new_byte << (itm_bytes * 8));
+ itm_bytes ++;
+ if(itm_bytes == itm_size)
+ {
+ if ((itm_header & 4) == 0)
+ {
+ TRC_MSG(("ITM s/w channel %d, %08x\n",itm_header>>3,itm_payload));
+ itm_sw++;
+ }
+ else
+ {
+ switch(itm_header>>3)
+ {
+ case 0://Event packet
+ TRC_MSG(("ITM #"));
+ if((itm_payload & 1) == 1) {
+ TRC_MSG((" CPI"));
+ itm_event++;
+ }
+ if((itm_payload & 2) == 2) {
+ TRC_MSG((" Exc"));
+ itm_event++;
+ }
+ if((itm_payload & 4) == 4) {
+ TRC_MSG((" Sleep"));
+ itm_event++;
+ }
+ if((itm_payload & 8) == 8) {
+ TRC_MSG((" LSU"));
+ itm_event++;
+ }
+ if((itm_payload & 16) == 16) {
+ TRC_MSG((" FOLD"));
+ itm_event++;
+ }
+ if((itm_payload & 32) == 32) {
+ TRC_MSG((" Cyc"));
+ itm_event++;
+ }
+ TRC_MSG((" Event\n"));
+ break;
+ case 1://Exception Packet
+ switch (itm_payload >> 12)
+ {
+ case 1:
+ TRC_MSG(("ITM Exception Entry %d\n",itm_payload & 0x1ff));
+ break;
+ case 2:
+ TRC_MSG(("ITM Exception Exit %d\n",itm_payload & 0x1ff));
+ break;
+ case 3:
+ TRC_MSG(("ITM Exception Return %d\n",itm_payload & 0x1ff));
+ break;
+ }
+ itm_exception++;
+ break;
+ case 2:
+ if(itm_size == 4) {
+ TRC_MSG(("ITM PC periodic %08x\n",itm_payload));
+ } else {
+ TRC_MSG(("ITM PC periodic, sleeping\n"));
+ }
+ itm_periodic++;
+ break;
+ default: // Other sources
+ if((itm_header & 0xC4) == 0x84){
+ TRC_MSG(("ITM Data Value %d:",(itm_header>> 4) & 3));
+ if ((itm_header & 8) == 0){
+ TRC_MSG(("Read "));
+ } else {
+ TRC_MSG(("Write "));
+ }
+ TRC_MSG((" %08x\n",itm_payload));
+ }
+ if((itm_header & 0xCF) == 0x47) {
+ TRC_MSG(("ITM Data PC %d:%08x\n",(itm_header>> 4) & 3,itm_payload));
+ }
+ if((itm_header & 0xCF) == 0x4E) {
+ TRC_MSG(("ITM Data Address offset %d:%08x\n",(itm_header>> 4) & 3,itm_payload));
+ }
+ if((itm_header >> 5) == 3) {
+ TRC_MSG(("ITM Unspecified HW source %d:%08x\n",(itm_header>> 3),itm_payload));
+ trace_errors++;
+ }
+ itm_comp++;
+ }
+ }
+ itm_current = 0;
+ itm_bytes =0;
+ }
+ break;
+ }
+ break;
+ case 0x7D:
+ if(new_byte != 0)
+ {
+ DBG_MSG(("Trigger with non-zero data byte:%02x\n",new_byte));
+ }
+ TRC_MSG(("Formatter Trigger\n"));
+ fmt_triggers++;
+ break;
+ default:
+ trace_errors ++;
+ DBG_MSG(("Unexpected ID:%02x\n",trace_id));
+ break;
+ }
+ return 0;
+}
+
+
+uint32_t EmptyFunction()
+{
+ DBG_MSG(("EmptyFunction()\n"));
+
+ return TEST_FAIL;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Internal Functions - Wire Protocol agnostic
+//
+////////////////////////////////////////////////////////////////////////////////
+
+void InitDAPSTATUS()
+{
+ //
+ // Initialise DAPSTATUS struct - use from reset, or if DAP powered down
+ //
+ DAPSTATUS.jtagnsw = 0; // Serial Wire
+ DAPSTATUS.jtagapndp = 2; // Invalid value
+ DAPSTATUS.on = 0; // DAP powered off
+ DAPSTATUS.banksel = 0xff; // Invalid banksel value
+ DAPSTATUS.csw = 0xffffffff;// Invalid CSW value - we haven't set up CSW
+ DAPSTATUS.error = 0; // No errors
+ DAPSTATUS.ack = 0; // Invalid value for ack
+ DAPSTATUS.stkerrclr = 0; // Not cleared
+}
+
+
+void InitCommRegion()
+{
+ //
+ // Get value for Cortex_MCU.stacktop by reading example MCU vector table
+ //
+ if(Cortex_MCU.stacktop == 0)
+ {
+ DBG_MSG(("InitCommRegion()\n"));
+ Cortex_MCU.stacktop = ReadMem(0);
+ Cortex_MCU.stacktop = SwapEndian(Cortex_MCU.stacktop);
+ DBG_MSG(("InitCommRegion() StackPointer = %x\n",Cortex_MCU.stacktop ));
+ }
+}
+
+
+uint32_t SwapEndian(uint32_t data)
+{
+ //
+ // Swap endianness of data values if CPUs are BigEndian, since
+ // the DAP routines are inherently LE
+ //
+
+ if(EXPECTED_BE)
+ {
+ // CPU under test is in BigEndian, so swap data endianness
+ return __REV(data);
+ }
+ else
+ {
+ return data;
+ }
+}
+
+
+uint32_t ReadCommRegion(uint32_t index)
+{
+ return SwapEndian( ReadMem( Cortex_MCU.stacktop + (4 * index)));
+}
+
+
+void WriteCommRegion(uint32_t index, uint32_t data)
+{
+ WriteMem( (Cortex_MCU.stacktop + (4 * index)), SwapEndian(data) );
+}
+
+
+uint32_t ReadMem(uint32_t address)
+{
+ //
+ // return the WORD value found at address
+ //
+
+ uint32_t value;
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_OFF | CSW_SIZE_WORD);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Read DRW
+ APReadDRW();
+
+ // Read RdBuff
+ value = DPReadRDBUFF();
+
+ DBG_MSG(("ReadMem(%x), returned: %x\n", address,value));
+
+ return value;
+}
+
+
+uint32_t ReadMemH(uint32_t address)
+{
+ //
+ // return the HALFWORD value found at address
+ //
+
+ uint32_t value;
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_OFF | CSW_SIZE_HALFWORD);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Read DRW
+ APReadDRW();
+
+ // Read RdBuff
+ value = DPReadRDBUFF();
+
+ DBG_MSG(("ReadMemH(%x), returned: %x\n", address,value));
+
+ return value;
+}
+
+
+uint32_t ReadMemB(uint32_t address)
+{
+ //
+ // return the BYTE value found at address
+ //
+
+ uint32_t value;
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_OFF | CSW_SIZE_BYTE);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Read DRW
+ APReadDRW();
+
+ // Read RdBuff
+ value = DPReadRDBUFF();
+
+ DBG_MSG(("ReadMemB(%x), returned: %x\n", address,value));
+
+ return value;
+}
+
+
+void ReadMemBlock(uint32_t address, uint32_t numwords, uint32_t * data)
+{
+ //
+ // Return numword WORDS from address into the data array
+ //
+
+ uint32_t tar;
+ uint32_t wordsread;
+
+ DBG_MSG(("ReadMemBlock(%x, %x)\n",address, numwords));
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_SINGLE | CSW_SIZE_WORD);
+
+ // Keep local copy of TAR
+ tar = address;
+
+ // Write TAR
+ APWriteTAR(tar);
+
+ for(wordsread = 0; wordsread < numwords; wordsread++)
+ {
+ // If the local copy of the TAR value increments beyond the bottom 10 bits,
+ // reload the DAP TAR. (ADIv5 Arch states that autoincrement beyond the
+ // bottom 10 bits is implementation defined.)
+ if(!(tar & 0x3FF))
+ {
+ APWriteTAR(tar);
+ }
+
+ if(wordsread)
+ {
+ data[wordsread-1] = APReadDRW();
+ }
+ else
+ {
+ // Discard data from initial Read
+ APReadDRW();
+ }
+ tar += 4;
+ }
+
+ // Read final word from the Read Buffer
+ data[wordsread-1] = DPReadRDBUFF();
+}
+
+
+uint32_t ReadMemSpecial(uint32_t address, uint8_t size, uint32_t user)
+{
+ //
+ // return the value found at address. if the DAPSTATUS error
+ // is set as a result of this read (assuming no prior errors),
+ // the CTRL/STAT register is read to check sticky ERR bit and
+ // then ABORT register written to clear the sticky ERR bit
+ //
+ uint32_t value;
+ uint32_t ctrlstat;
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_INCR_OFF | size | user);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Read DRW
+ APReadDRW();
+
+ // Read RdBuff
+ value = DPReadRDBUFF();
+
+ // For JTAG, CTRLSTAT needs to be read
+ // for faults. Ack doesn't indicate fault
+ if(DAPSTATUS.jtagnsw)
+ {
+ ctrlstat = DPReadCTRLSTAT();
+ if((ctrlstat >> 5) & 1UL)
+ DAPSTATUS.error++;
+ }
+
+ // Read CTRLSTAT to check STICKYERR
+ // if STICKYERR is set, clear it
+ if(DAPSTATUS.error == 1)
+ {
+ if(DAPSTATUS.jtagnsw)
+ {
+ // Already read earlier
+ DBG_MSG(("DAP access faulted, clearing sticky error bit\n"));
+ DPClearSTICKYERR();
+ DAPSTATUS.stkerrclr = 1;
+ }
+ else
+ {
+ ctrlstat = DPReadCTRLSTAT();
+
+ if((ctrlstat >> 5) & 1UL)
+ {
+ DBG_MSG(("DAP access faulted, clearing sticky error bit\n"));
+ DPClearSTICKYERR();
+ DAPSTATUS.stkerrclr = 1;
+ }
+ }
+
+ DAPSTATUS.error = 0;
+ }
+ else if(DAPSTATUS.error > 1)
+ DBG_MSG(("More than one DAP error seen! Unexpected so not clearing sticky error bit\n"));
+
+ DBG_MSG(("ReadMemSpecial(%x), returned: %x\n", address,value));
+
+ return value;
+}
+
+void WriteMem(uint32_t address, uint32_t data)
+{
+ //
+ // Write WORD value back to target memory
+ //
+
+ DBG_MSG(("WriteMem(%x, %x)\n",address, data));
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_OFF | CSW_SIZE_WORD);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Write DRW
+ APWriteDRW(data);
+
+ // Read RdBuff to flush the write
+ DPReadRDBUFF();
+}
+
+
+void WriteMemBlock(uint32_t address, uint32_t numwords, uint32_t * data)
+{
+ //
+ // Write numwords WORD values to target memory
+ //
+
+ uint32_t tar;
+ uint32_t wordswritten;
+
+ DBG_MSG(("WriteMemBlock(%x, %x, %x)\n",address, numwords, data));
+
+ // Write CSW : Word, incrementing address
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_SINGLE | CSW_SIZE_WORD);
+
+ // Keep local copy of TAR
+ tar = address;
+
+ // Write TAR
+ APWriteTAR(tar);
+ DBG_MSG(("Written 0x%x to TAR\n",tar));
+
+ for(wordswritten = 0; wordswritten < numwords; wordswritten++)
+ {
+ // If the local copy of the TAR value increments beyond the bottom 10 bits,
+ // reload the DAP TAR. (ADIv5 Arch states that autoincrement beyond the
+ // bottom 10 bits is implementation defined.)
+ if(!(tar & 0x3FF))
+ {
+ APWriteTAR(tar);
+ DBG_MSG(("Written 0x%x to TAR\n",tar));
+ }
+
+ // Write DRW
+ APWriteDRW(data[wordswritten]);
+ tar += 4;
+ }
+
+ // Read RdBuff to flush the last write
+ DPReadRDBUFF();
+}
+
+
+void WriteMemH(uint32_t address, uint32_t data)
+{
+ //
+ // Write HALFWORD value back to target memory
+ //
+
+ uint32_t ldata;
+
+ ldata = data | (data << 16);
+
+ DBG_MSG(("WriteMemH(%x, %x)\n",address, ldata));
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_OFF | CSW_SIZE_HALFWORD);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Write DRW
+ APWriteDRW(ldata);
+
+ // Read RdBuff to flush the write
+ DPReadRDBUFF();
+}
+
+
+void WriteMemB(uint32_t address, uint32_t data)
+{
+ //
+ // Write BYTE value back to target memory
+ //
+
+ uint32_t ldata;
+
+ ldata = data | (data << 8);
+ ldata = ldata | (ldata << 16);
+
+ DBG_MSG(("WriteMemB(%x, %x)\n",address, ldata));
+
+ // Ensure CSW is set up
+ APWriteCSW(CSW_PROT_MASTER_DBG | CSW_PROT_PRIV | CSW_INCR_OFF | CSW_SIZE_BYTE);
+
+ // Write TAR
+ APWriteTAR(address);
+
+ // Write DRW
+ APWriteDRW(ldata);
+
+ // Read RdBuff to flush the write
+ DPReadRDBUFF();
+}
+
+
+void JtagAPnDP(uint32_t apndp)
+{
+ //
+ // JTAG switch scanchains
+ //
+ if(DAPSTATUS.jtagapndp != apndp)
+ {
+ if(apndp)
+ {
+ // AP
+ JTAGScanIR(JTAG_APACC);
+ }
+ else
+ {
+ // DP
+ JTAGScanIR(JTAG_DPACC);
+ }
+ DAPSTATUS.jtagapndp = apndp;
+ }
+}
+
+
+void DPWriteBANKSEL(uint32_t banksel)
+{
+ //
+ // Set DP register BANKSEL
+ //
+
+ if(DAPSTATUS.banksel != banksel)
+ {
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(0);
+ JTAGScanDR( (banksel << 7) | JTAG_SCAN(SELECT,WRITE) );
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, WRITE, SELECT) );
+ SWDataWrite( banksel << 4 );
+ }
+ DAPSTATUS.banksel = banksel;
+ }
+}
+
+
+void DPWriteCTRLSTAT(uint32_t ctrlstat)
+{
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(0);
+ JTAGScanDR( (((uint64_t) ctrlstat) << 3) | JTAG_SCAN(CTRLSTAT,WRITE) );
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, WRITE, CTRLSTAT) );
+ SWDataWrite( ctrlstat );
+ }
+}
+
+
+uint32_t DPReadCTRLSTAT()
+{
+ uint32_t data;
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(0);
+ JTAGScanDR( JTAG_SCAN(CTRLSTAT,READ) );
+ data = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, READ, CTRLSTAT) );
+ data = SWDataRead();
+ }
+ return data;
+}
+
+uint32_t APReadCSW()
+{
+ uint32_t data;
+
+ // CSW is in bank 0 (APBANKSEL=0)
+ DPWriteBANKSEL(0UL << 4);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ JTAGScanDR( JTAG_SCAN(CSW, READ) );
+ data = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, READ, CSW) );
+ SWDataRead();
+ data =DPReadRDBUFF();
+ }
+ return data;
+}
+
+void APWriteCSW(uint32_t csw)
+{
+ // Set up CSW
+ if(DAPSTATUS.csw != csw)
+ {
+ // CSW is in bank 0
+ DPWriteBANKSEL(0UL << 4);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ JTAGScanDR( (((uint64_t) csw) << 3) | JTAG_SCAN(CSW,WRITE) );
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, WRITE, CSW) );
+ SWDataWrite( csw );
+ }
+ DAPSTATUS.csw = csw;
+ }
+}
+
+
+void APWriteTAR(uint32_t address)
+{
+ // TAR is in bank 0
+ DPWriteBANKSEL(0UL << 4);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ JTAGScanDR( (((uint64_t) address) << 3) | JTAG_SCAN(TAR,WRITE) );
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, WRITE, TAR) );
+ SWDataWrite( address );
+ }
+}
+
+
+uint32_t APReadDRW()
+{
+ uint32_t data;
+ // DRW is in bank 0
+ DPWriteBANKSEL(0UL << 4);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ data = (JTAGScanDR(JTAG_SCAN(DRW,READ)) >> 3);
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, READ, DRW) );
+ data = SWDataRead();
+ }
+ return data;
+}
+
+
+void APWriteDRW(uint32_t data)
+{
+ // DRW is in bank 0
+ DPWriteBANKSEL(0UL << 4);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ JTAGScanDR( (((uint64_t) data) << 3) | JTAG_SCAN(DRW,WRITE) );
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, WRITE, DRW) );
+ SWDataWrite(data);
+ }
+}
+
+
+uint32_t DPReadRDBUFF()
+{
+ uint32_t data;
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(0);
+ data = ( JTAGScanDR(JTAG_SCAN(RDBUFF,READ)) >> 3);
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, READ, RDBUFF) );
+ data = SWDataRead();
+ }
+ return data;
+}
+
+
+uint32_t DPReadIDR()
+{
+ uint32_t data;
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(0);
+
+ JTAGScanDR(JTAG_SCAN(DPIDR,READ));
+ data = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, READ, DPIDR) );
+ data = SWDataRead();
+ }
+ return data;
+}
+
+
+uint32_t APReadIDR()
+{
+ uint32_t data;
+
+ // IDR is in bank F
+ DPWriteBANKSEL(0xF);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ JTAGScanDR(JTAG_SCAN(IDR,READ));
+ data = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, READ, IDR) );
+ SWDataRead();
+ data = DPReadRDBUFF();
+ }
+ return data;
+}
+
+
+uint32_t APReadBASE()
+{
+ uint32_t data;
+
+ // BASE is in bank F
+ DPWriteBANKSEL(0xF);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(1);
+ JTAGScanDR(JTAG_SCAN(BASE,READ));
+ data = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(AP, READ, BASE) );
+ SWDataRead();
+ data =DPReadRDBUFF();
+ }
+ return data;
+}
+
+
+uint32_t DPReadHALTEV()
+{
+ uint32_t data;
+
+ // HALTEV is in bank 4 (DPBANKSEL=4)
+ DPWriteBANKSEL(0x4UL);
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ JtagAPnDP(0);
+ JTAGScanDR(JTAG_SCAN(HALTEV,READ));
+ data = DPReadRDBUFF();
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, READ, HALTEV));
+ data = SWDataRead();
+ }
+
+ // Switch DPBANKSEL back to 0
+ DPWriteBANKSEL(0x0UL);
+
+ return data;
+}
+
+
+void DPClearSTICKYERR()
+{
+ //
+ // Clear STICKYERR bit
+ //
+ uint32_t ctrlstat;
+
+ if(DAPSTATUS.jtagnsw)
+ {
+ // write 1 to STICKYERR to clear it, also keep power-up requests high
+#ifdef CORTEX_M0PLUS
+ ctrlstat = (1UL << 5) | (5UL << 28);
+#else
+ ctrlstat = (1UL << 5);
+#endif
+ JtagAPnDP(0);
+ JTAGScanDR( (((uint64_t) ctrlstat) << 3) | JTAG_SCAN(CTRLSTAT,WRITE) );
+ }
+ else
+ {
+ SWHeader( SW_HEADER(DP, WRITE, ABORT) );
+#ifdef CORTEX_M0PLUS
+ SWDataWrite( 1UL << 2 );
+#else
+ SWDataWrite( 1UL << 5 );
+#endif
+ }
+}
+
+
+uint32_t CheckDAPSTATUS()
+{
+ //
+ // Check for any debugger errors and return FAIL if any
+ //
+
+ // For JTAG, check CTRLSTAT for faults
+ if(DAPSTATUS.jtagnsw)
+ {
+ if((DPReadCTRLSTAT() >> 5) & 1UL)
+ DAPSTATUS.error++;
+ }
+
+ if(DAPSTATUS.error != 0)
+ {
+ DBG_MSG(("Errors found in Debugger accesses -\tFAIL\n"));
+ return TEST_FAIL;
+ }
+
+ return TEST_PASS;
+}
+
+
+void pulse_clock(uint8_t number_of_clock_ticks)
+{
+ uint8_t count;
+
+ for(count = number_of_clock_ticks; count > 0; count--)
+ {
+ // Pulse clock pin
+ GPIO0->LB_MASKED[DD_DBG_SWCLKTCK] = DD_DBG_SWCLKTCK;
+ GPIO0->LB_MASKED[DD_DBG_SWCLKTCK] = 0;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// JTAG Routines
+//
+////////////////////////////////////////////////////////////////////////////////
+
+uint64_t JTAGScanIDCODE()
+{
+ // Read the TAP ID code
+
+ uint64_t tmp;
+
+ JTAGScanIR(JTAG_IDCODE);
+
+ // RTI->SDR
+ // 001
+ JTAGTransition(0x1, 3);
+
+ // Shift
+ tmp = JTAGShift(0, 32);
+
+ // E1DR->RTI
+ // 01
+ JTAGTransition(0x1, 2);
+
+ return tmp;
+}
+
+
+void JTAGScanIR(uint32_t instruction)
+{
+ //
+ // Scan in the passed Instruction
+ //
+
+ // RTI->SIR
+ // 0011
+ JTAGTransition(0x3, 4);
+
+ // Shift Instruction
+ JTAGShift(instruction, 4);
+
+ // E1IR->RTI
+ // 01
+ JTAGTransition(0x1, 2);
+}
+
+
+uint64_t JTAGScanDR(uint64_t data)
+{
+ //
+ // Scan in/out values for the APACC/DPACC/ABORT Scan Chains
+ //
+ // Repeat scan chain for ack=WAIT
+ uint64_t tmp;
+ uint8_t ack;
+
+ do
+ {
+ // RTI->SDR
+ // 001
+ JTAGTransition(0x1, 3);
+
+ // Shift
+ tmp = JTAGShift(data, 35);
+
+ // E1DR->RTI
+ // 01
+ JTAGTransition(0x1, 2);
+
+ ack = (uint8_t)tmp & 7UL;
+
+ DAPSTATUS.ack = ack;
+
+ } while (ack == JTAG_DP_ACK_WAIT);
+
+ return tmp;
+}
+
+
+void JTAGTransition(uint32_t tms, uint8_t numbits)
+{
+ //
+ // JTAGTransition causes us to ENTER a new TAP state
+ //
+
+ uint8_t i;
+
+ for(i = numbits; i > 0; i--)
+ {
+ // Drive TMS
+ if(tms & 0x1)
+ {
+ GPIO0->LB_MASKED[DD_DBG_TMS] = DD_DBG_TMS;
+ }
+ else
+ {
+ GPIO0->LB_MASKED[DD_DBG_TMS] = 0;
+ }
+ tms = (tms >> 1);
+
+ pulse_clock(1);
+ }
+}
+
+
+uint64_t JTAGShift(uint64_t data, uint8_t numbits)
+{
+ //
+ // JTAGShift handles shifts into and out of the the SR
+ //
+
+ // Most of the shift state has TMS Low, however the final cycle
+ // which exits from the Shift to Exit1 also clocks out the final bit
+
+ // When we enter this function, JTAGTransition has already created the negedge,
+ // so here we want to drive the output and sample the input.
+
+ // On the final cycle, we'll drive TMS high to escape the SHIFT state
+
+
+ uint8_t i;
+ uint64_t captured_data = 0;
+
+ // Shifts require TMS == 0
+ GPIO0->LB_MASKED[DD_DBG_TMS] = 0;
+
+ for(i = numbits; i > 0; i--)
+ {
+ // Posedge of clock enters the state
+ // GPIO0->DATA[DD_SWCLKTCK].BYTE[DD_DBG_BYTE] = DD_SWCLKTCK;
+
+ // Drive signals to the DAP on negedge of clock
+ // Also sample signals from the DAP after negedge of clock
+
+ // Drive output
+ if(data & 0x1)
+ {
+ // Set
+ GPIO0->LB_MASKED[DD_DBG_TDI] = DD_DBG_TDI;
+ }
+ else
+ {
+ // Clear
+ GPIO0->LB_MASKED[DD_DBG_TDI] = 0;
+ }
+ data = (data >> 1);
+
+
+ // Capture Input
+ captured_data = captured_data >> 1;
+
+ if(GPIO0->LB_MASKED[DD_DBG_TDO])
+ {
+ // Set
+ captured_data |= (0x1ull << 63);
+ }
+
+
+ // Final cycle - drive TMS high to escape to Exit1
+ if(i == 1)
+ {
+ GPIO0->LB_MASKED[DD_DBG_TMS] = DD_DBG_TMS;
+ }
+
+ pulse_clock(1);
+
+ }
+
+ // fix up alignment of captured data before returning it
+ captured_data = captured_data >> (64-numbits);
+
+ return captured_data;
+
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// SerialWire routines
+//
+////////////////////////////////////////////////////////////////////////////////
+
+uint32_t SWConnect()
+{
+ uint32_t tmp;
+
+#ifdef SWJ_DEPRECATED_SWITCHING_SEQUENCE
+
+ // Note: This sequence is deprecated if dormant mode is supported.
+ // Switch from Jtag to SW (no effect if just SW present)
+
+ SWLineReset(0);
+
+ // : start
+ // Switching sequence (lsb first) = 0xE79E;
+ SerialWireClockOut(0xE79E,16);
+ // Should now be waiting in sw state
+
+#endif
+
+#ifdef SWMD_TARGET_SELECTION
+ // SWMD starts in dormant state so first exit dormant state
+ SWExitDormantState();
+
+ SWHeader( SW_HEADER(DP, WRITE, TARGETSEL));
+
+ // Ack for TARGETSEL access is not driven, so set it explicitly
+ DAPSTATUS.ack = SW_DP_ACK_OK;
+
+ SWDataWrite( MCU_TARGETSEL_VALUE );
+
+#endif
+
+ // Attempt a SerialWire connection sequence
+ SWLineReset(8);
+
+ // Attempt an ID code read
+ SWHeader( SW_HEADER(DP,READ,DPIDR) );
+ tmp = SWDataRead();
+
+ DBG_MSG(("SWConnect returned DPIDR: %x\n", tmp));
+
+ return CheckDAPSTATUS();
+}
+
+
+void SWDataWrite(uint32_t data)
+{
+ //
+ // Enter from SW header+Ack, we are not currently driving the line
+ //
+
+ uint32_t mask;
+ uint32_t parity;
+
+ // Send one turnaround cycle
+ pulse_clock(1);
+
+ // Only clock out bits if ACK was OK
+ if(DAPSTATUS.ack == SW_DP_ACK_OK)
+ {
+ // Clock data out
+ SerialWireClockOut(data,32);
+
+ // Calculate data parity
+ for(parity=0, mask=0x1; mask != 0; mask = mask << 1)
+ {
+ parity += (data & mask) ? 1 : 0;
+ }
+
+ // Clock parity out
+ SerialWireClockOut(parity,1);
+ }
+}
+
+
+uint32_t SWDataRead(void)
+{
+ uint32_t rdata;
+
+ // Only clock in bits if ACK was OK
+ if(DAPSTATUS.ack == SW_DP_ACK_OK)
+ {
+ // Reads do not need to flip the line at all.
+ // Clock out 32 data bits, + parity, + turnaround
+
+ // Clock in 32 bits of read data
+ rdata = SerialWireClockIn(32);
+
+ // Clock in (and ignore!) parity bit and turnround bit
+ SerialWireClockIn(2);
+ }
+ else
+ {
+ // Clock in 1 cycle to put SW state in correct state
+ pulse_clock(1);
+
+ // return bogus value
+ rdata = 0xDEADBEEFUL;
+ }
+
+ DBG_MSG(("SWDataRead() returned %x\n", rdata));
+
+ return rdata;
+}
+
+
+uint32_t SWHeader(uint8_t header)
+{
+ // Clock out the (precalculated) SW header
+ //
+ // Always clock out 8 bits.
+ // Drive ALL bits, including park (DE 618567)
+ //
+
+ uint32_t ack;
+
+ do {
+ // Clock out the header
+ SerialWireClockOut(header, 8);
+
+ // Clock in the first turnround bit and 3 ack bits
+ ack = SerialWireClockIn(4);
+
+ // LSB adjust Ack value and lose turnround bit
+ ack = (ack >> (32 - 3)) & 0x7;
+
+ if (ack == SW_DP_ACK_FAULT)
+ DAPSTATUS.error++;
+
+ // Insert turnaround bit if for WAITed ACK
+ if (ack == SW_DP_ACK_WAIT)
+ SerialWireClockOut(0UL,1);
+
+ DAPSTATUS.ack = ack;
+
+ } while (ack == SW_DP_ACK_WAIT);
+
+
+ if (ack != SW_DP_ACK_OK)
+ {
+ DBG_MSG(("ERROR - Maybe unhandled SW-DP response "));
+ switch(ack)
+ {
+ case SW_DP_ACK_WAIT:
+ DBG_MSG(("WAIT\n"));
+ break;
+ case SW_DP_ACK_FAULT:
+ DBG_MSG(("ERROR\n"));
+ break;
+ default:
+ DBG_MSG(("Unknown, %x\n",ack));
+ break;
+ }
+ }
+
+ return ack;
+}
+
+
+void SerialWireClockOut (uint32_t data, uint32_t numbits)
+{
+ // Ensure we are going to drive the line
+ GPIO0->LB_MASKED[DD_DBG_TMSEN] = DD_DBG_TMSEN;
+
+ for(; numbits > 0; numbits--)
+ {
+ if(data & 0x1)
+ {
+ // Bit set
+ GPIO0->LB_MASKED[DD_DBG_TMS] = DD_DBG_TMS;
+ }
+ else
+ {
+ // Bit clear
+ GPIO0->LB_MASKED[DD_DBG_TMS] = 0;
+ }
+
+ pulse_clock(1);
+
+ data = (data >> 1);
+ }
+}
+
+
+uint32_t SerialWireClockIn (uint32_t numbits)
+{
+ uint32_t data = 0;
+
+ // Don't drive the line while clocking data in
+ GPIO0->LB_MASKED[DD_DBG_TMSEN] = 0;
+
+ for(; numbits > 0; numbits--)
+ {
+ data = (data >> 1);
+
+ if(GPIO0->LB_MASKED[DD_DBG_TMSIN])
+ {
+ data |= (0x1UL << 31);
+ }
+
+ pulse_clock(1);
+ }
+
+ return data;
+}
+
+
+void SWLineReset(uint8_t num_of_idle_cycles)
+{
+ // Ensure Clock is low
+ GPIO0->LB_MASKED[DD_DBG_SWCLKTCK] = 0;
+
+ // Set SWDO and SWDOEN
+ GPIO0->LB_MASKED[(DD_DBG_TMS | DD_DBG_TMSEN)] = (DD_DBG_TMS | DD_DBG_TMSEN);
+
+ pulse_clock(50);
+
+ // Insert requested idle cycles
+ GPIO0->LB_MASKED[DD_DBG_TMS] = 0;
+
+ pulse_clock(num_of_idle_cycles);
+}
+
+
+void SWExitDormantState(void)
+{
+ // Leave Dormant state
+ DBG_MSG(("Leaving Dormant State\n"));
+
+ // 1. At least 8 SWCLKTCK cycles with SWDIOTMS high
+ SerialWireClockOut(0xFFUL,8);
+
+ // 2. 128-bit Selection Alert
+ SerialWireClockOut(DS_to_SWD_0,32);
+ SerialWireClockOut(DS_to_SWD_1,32);
+ SerialWireClockOut(DS_to_SWD_2,32);
+ SerialWireClockOut(DS_to_SWD_3,32);
+
+ // 3. 4 SWCLKTCK cycles with SWDIOTMS low
+ SerialWireClockOut(0UL,4);
+
+ // 4. Activation Sequence
+ SerialWireClockOut(SW_ACTV_CODE,8);
+
+ // 5. Line Reset
+ SWLineReset(2);
+}
+
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester.h b/Cortex-M0/nanosoc/software/debug_tester/debugtester.h
new file mode 100644
index 0000000000000000000000000000000000000000..fcaacd0fcfd72d8be188ba72c1c0454b02475b8a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester.h
@@ -0,0 +1,237 @@
+//
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+//============================================================================
+// Debug tester header file, contain debug related definition
+//============================================================================
+
+//============================================================================
+// Define pass/fail value
+//============================================================================
+#define TEST_PASS 0
+#define TEST_FAIL 1
+
+// Define whether the DebugTester code should display messages
+// using the character output device in the debugtester.
+//#define DEBUGTESTER_PRINTF
+//#define DEBUGTRACE_PRINTF
+
+
+//============================================================================
+// Print macro to allow conditional printing of messages
+//
+// Invoke like printf, but use double braces: DBG_MSG(("format %x", var));
+//============================================================================
+
+#ifdef DEBUGTESTER_PRINTF
+#define DBG_MSG(arg) { printf arg ; }
+#else
+#define DBG_MSG(arg) { (void) 0; }
+#endif
+
+#ifdef DEBUGTRACE_PRINTF
+#define TRC_MSG(arg) { printf arg ; }
+#else
+#define TRC_MSG(arg) { (void) 0; }
+#endif
+
+//============================================================================
+// SW responses
+//============================================================================
+#define SW_DP_ACK_OK 1
+#define SW_DP_ACK_WAIT 2
+#define SW_DP_ACK_FAULT 4
+
+// SW to Dormant state sequence
+#define SWD_to_DS 0xE3BCUL
+
+// Dormant state to SW sequence
+#define DS_to_SWD_0 0x6209F392UL
+#define DS_to_SWD_1 0x86852D95UL
+#define DS_to_SWD_2 0xE3DDAFE9UL
+#define DS_to_SWD_3 0x19BC0EA2UL
+
+#define SW_ACTV_CODE 0x1AUL
+
+//============================================================================
+// JTAG Definitions
+//============================================================================
+#define JTAG_ABORT 0x8
+#define JTAG_DPACC 0xa
+#define JTAG_APACC 0xb
+#define JTAG_IDCODE 0xe
+#define JTAG_BYPASS 0xf
+
+#define JTAG_SCAN(Address,RnW) (((Address & 0xC) >> 1) | RnW)
+
+#define JTAG_DP_ACK_OKFAULT 2
+#define JTAG_DP_ACK_WAIT 1
+
+
+//============================================================================
+// Macro definitions to generate SerialWire packet headers at compilation time
+//============================================================================
+
+// Header Bits
+
+#define AP 1
+#define DP 0
+
+#define READ 1
+#define WRITE 0
+
+// DP Register Addresses
+
+#define DPIDR 0x0
+#define ABORT 0x0
+#define CTRLSTAT 0x4
+#define DLCR 0x4
+#define TARGETID 0x4
+#define HALTEV 0x4
+#define RESEND 0x8
+#define SELECT 0x8
+#define RDBUFF 0xc
+#define TARGETSEL 0xc
+
+// DP control and state register bit definition
+
+#define CTRL_CSYSPWRUPACK (1UL << 31) //System power up ack, RO
+#define CTRL_CSYSPWRUPREQ (1UL << 30) //System power up req, RW
+#define CTRL_CDBGPWRUPACK (1UL << 29) //Debug power up ack, RO
+#define CTRL_CDBGPWRUPREQ (1UL << 28) //Debug power up req, RW
+#define CTRL_CDBGRSTACK (1UL << 27) //Debug reset ack, RO
+#define CTRL_CDBGRSTREQ (1UL << 26) //Debug reset req, RW
+
+// AP Register Addresses
+
+#define CSW 0x00
+#define TAR 0x04
+#define DRW 0x0c
+#define BD0 0x10
+#define BD1 0x14
+#define BD2 0x18
+#define BD3 0x1c
+#define CFG 0xf4
+#define BASE 0xf8
+#define IDR 0xfc
+
+// CSW Register Fields
+#define CSW_PROT_USER (0UL << 25)
+#define CSW_PROT_PRIV (1UL << 25)
+#define CSW_PROT_BUFF (1UL << 26)
+#define CSW_PROT_CACH (1UL << 27)
+#define CSW_PROT_MASTER_CORE (0UL << 29)
+#define CSW_PROT_MASTER_DBG (1UL << 29)
+
+#define CSW_INCR_OFF (0UL << 4)
+#define CSW_INCR_SINGLE (1UL << 4)
+
+#define CSW_SIZE_BYTE 0
+#define CSW_SIZE_HALFWORD 1
+#define CSW_SIZE_WORD 2
+
+// Serial Wire Header Macros
+
+#define SW_HEADER_PARITY(APnDP,RnW,Address) ( (APnDP & 0x1) ^ (RnW & 0x1) ^ ((Address & 0x4) >> 2) ^ ((Address & 0x8) >> 3) )
+
+// Start, APnDP, RnW, A[3:2], Parity, Stop, Park
+#define SW_HEADER(APnDP,RnW,Address) (1 | ((APnDP & 0x1) << 1) | ((RnW & 0x1) << 2) | ((Address & 0xC) << 1) | SW_HEADER_PARITY(APnDP,RnW,Address) << 5 | 0 << 6 | 1 << 7)
+
+
+//============================================================================
+// CoreSight ID Register Offset values
+//============================================================================
+
+// CID OFFSET define
+#define CID0_OFFSET 0xFF0
+#define CID1_OFFSET 0xFF4
+#define CID2_OFFSET 0xFF8
+#define CID3_OFFSET 0xFFC
+
+
+// PID OFFSET define
+#define PID0_OFFSET 0xFE0
+#define PID1_OFFSET 0xFE4
+#define PID2_OFFSET 0xFE8
+#define PID3_OFFSET 0xFEC
+#define PID4_OFFSET 0xFD0
+#define PID5_OFFSET 0xFD4
+#define PID6_OFFSET 0xFD8
+#define PID7_OFFSET 0xFDC
+
+
+//============================================================================
+// ARMv6M and ARMv7M Architectural Debug Register Definitions
+//============================================================================
+
+// DHCSR
+#define DHCSR_ADDR 0xE000EDF0
+
+#define DBGKEY 0xA05F0000
+#define S_LOCKUP (1UL << 19)
+#define S_SLEEP (1UL << 18)
+#define S_HALT (1UL << 17)
+#define S_REGRDY (1UL << 16)
+#define C_MASKINTS (1UL << 3)
+#define C_STEP (1UL << 2)
+#define C_HALT (1UL << 1)
+#define C_DEBUGEN (1UL << 0)
+
+
+// DCRSR
+#define DCRSR_ADDR 0xE000EDF4
+
+#define REGWnR (1UL << 16)
+#define R0 0x00
+#define R1 0x01
+#define R2 0x02
+#define R3 0x03
+#define R4 0x04
+#define R5 0x05
+#define R6 0x06
+#define R7 0x07
+#define R8 0x08
+#define R9 0x09
+#define R10 0x0A
+#define R11 0x0B
+#define R12 0x0C
+#define SP 0x0D
+#define LR 0x0E
+#define DebugReturnAddress 0x0F
+#define xPSR 0x10
+#define MSP 0x11
+#define PSP 0x12
+#define CONTROL 0x14
+
+
+// DCRDR
+#define DCRDR_ADDR 0xE000EDF8
+
+
+//============================================================================
+// Trace related defines
+//============================================================================
+
+#define MCU_ETM_ID 0x23 // CM_MCU_ETM_ID in trace_tests.h
+#define MCU_ITM_ID 0x59 // CM_MCU_ITM_ID in trace_tests.h
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0.sct b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0.sct
new file mode 100644
index 0000000000000000000000000000000000000000..948eaf903de1bf6fcd4db8f6e99f28555980d4a0
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0.sct
@@ -0,0 +1,38 @@
+;-----------------------------------------------------------------------------
+; The confidential and proprietary information contained in this file may
+; only be used by a person authorised under and to the extent permitted
+; by a subsisting licensing agreement from Arm Limited or its affiliates.
+;
+; (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+; ALL RIGHTS RESERVED
+;
+; This entire notice must be reproduced on all copies of this file
+; and copies of this file may only be made by a person if such person is
+; permitted to do so under the terms of a subsisting license agreement
+; from Arm Limited or its affiliates.
+;
+; SVN Information
+;
+; Checked In : $Date: 2011-02-22 16:53:27 +0000 (Tue, 22 Feb 2011) $
+;
+; Revision : $Revision: 162307 $
+;
+; Release Information : Cortex-M System Design Kit-r1p1-00rel0
+;
+;-----------------------------------------------------------------------------
+
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_ROM1 0x00000000 0x00020000 { ; load address = execution address
+ startup_CMSDK_CM0.o (RESET, +FIRST)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_RAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_be.uvopt b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_be.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..647d0307ee7800bf0bde7601226ebb984fc12a9a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_be.uvopt
@@ -0,0 +1,245 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
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new file mode 100644
index 0000000000000000000000000000000000000000..b20c84b626ba5985d0934b777c4df81a2c8bbc82
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_be.uvproj
@@ -0,0 +1,430 @@
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diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_le.uvopt b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_le.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..647d0307ee7800bf0bde7601226ebb984fc12a9a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_le.uvopt
@@ -0,0 +1,245 @@
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diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_le.uvproj b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_le.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..7973ddcc968fff5cc4d016d48abf9b7a53bb4a6a
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0_le.uvproj
@@ -0,0 +1,430 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
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+ <Flash3>"" ()</Flash3>
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+ <LinkerInputFile></LinkerInputFile>
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+ </File>
+ </Files>
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+ <GroupName>Application</GroupName>
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+ <File>
+ <FileName>cmsdk_debugtester.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\debugtester.c</FilePath>
+ </File>
+ </Files>
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+ <GroupName>System</GroupName>
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+ <File>
+ <FileName>system_cmsdk_debugtester.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_cmsdk_debugtester.c</FilePath>
+ </File>
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+ <FileName>retarget_cmsdk_debugtester.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\retarget_cmsdk_debugtester.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus.sct b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus.sct
new file mode 100644
index 0000000000000000000000000000000000000000..8068dfb28fe625e089f6b4d2adb94b65fa3583a5
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus.sct
@@ -0,0 +1,38 @@
+;-----------------------------------------------------------------------------
+; The confidential and proprietary information contained in this file may
+; only be used by a person authorised under and to the extent permitted
+; by a subsisting licensing agreement from Arm Limited or its affiliates.
+;
+; (C) COPYRIGHT 2013 Arm Limited or its affiliates.
+; ALL RIGHTS RESERVED
+;
+; This entire notice must be reproduced on all copies of this file
+; and copies of this file may only be made by a person if such person is
+; permitted to do so under the terms of a subsisting license agreement
+; from Arm Limited or its affiliates.
+;
+; SVN Information
+;
+; Checked In : $Date: 2011-02-22 16:53:27 +0000 (Tue, 22 Feb 2011) $
+;
+; Revision : $Revision: 162307 $
+;
+; Release Information : Cortex-M System Design Kit-r1p1-00rel0
+;
+;-----------------------------------------------------------------------------
+
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_ROM1 0x00000000 0x00020000 { ; load address = execution address
+ startup_CMSDK_CM0PLUS.o (RESET, +FIRST)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_RAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_be.uvopt b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_be.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..253e152828faa9a2542b996cf229b58d6c32b872
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_be.uvopt
@@ -0,0 +1,230 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
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+ <Target>
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diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_be.uvproj b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_be.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..7d4eeb1d87f7e2f7e31aae60bac02395a3b6bedb
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_be.uvproj
@@ -0,0 +1,427 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_le.uvopt b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_le.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..253e152828faa9a2542b996cf229b58d6c32b872
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_le.uvopt
@@ -0,0 +1,230 @@
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diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_le.uvproj b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_le.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..0fe273b1559bf558a13b117a848e87999ed425c5
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_cm0plus_le.uvproj
@@ -0,0 +1,427 @@
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+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile>debugtester_cm0plus.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0PLUS.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\cmsis\Device\ARM\CMSDK_CM0PLUS\Source\ARM\startup_CMSDK_CM0PLUS.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>debugtester.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\debugtester.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_cmsdk_debugtester.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_cmsdk_debugtester.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget_cmsdk_debugtester.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\retarget_cmsdk_debugtester.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/software/debug_tester/debugtester_functions.h b/Cortex-M0/nanosoc/software/debug_tester/debugtester_functions.h
new file mode 100644
index 0000000000000000000000000000000000000000..3aa1dfd53c689e094fc81a8f9408bcc2bd092fdf
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/debugtester_functions.h
@@ -0,0 +1,52 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2012-05-31 12:12:02 +0100 (Thu, 31 May 2012) $
+ *
+ * Revision : $Revision: 210765 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// CMSDK Debug Tester Functions header file
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function enumeration to allow access to debug tester functions
+//
+
+enum Function { FnSetInterfaceJTAG,
+ FnSetInterfaceSW,
+ FnDAPPowerUp,
+ FnDAPPowerDown,
+ FnGetTAPID,
+ FnGetDPReg,
+ FnGetAPReg,
+ FnGetAPMem,
+ FnSetAPMem,
+ FnGetAPMemCSIDs,
+ FnConnectWakeUnhalt,
+ FnConnectCheckUnlockup,
+ FnEnableHaltingDebug,
+ FnDAPAccess,
+ FnConfigTrace,
+ FnCheckTrace
+};
diff --git a/Cortex-M0/nanosoc/software/debug_tester/retarget_cmsdk_debugtester.c b/Cortex-M0/nanosoc/software/debug_tester/retarget_cmsdk_debugtester.c
new file mode 100644
index 0000000000000000000000000000000000000000..b2d677d6d055f14dfcf5c9cb461ab9c94ff19ec1
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/retarget_cmsdk_debugtester.c
@@ -0,0 +1,97 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+//
+// printf retargetting functions for Debug Tester
+//
+
+#include "cmsdk_debugtester.h"
+
+// Routine to write a char - specific to Cortex-M Core debug tester
+void debugtester_char_write(int ch)
+{
+ GPIO1->LB_MASKED[DD_PRINT_CHAR] = ch; // Write whole char to 2nd byte
+ GPIO1->LB_MASKED[DD_PRINT_STROBE] = DD_PRINT_STROBE; // Write strobe
+ GPIO1->LB_MASKED[DD_PRINT_STROBE] = 0; // Clear Strobe
+}
+
+
+#if defined ( __CC_ARM )
+/******************************************************************************/
+/* Retarget functions for ARM DS-5 Professional / Keil MDK */
+/******************************************************************************/
+
+#include <stdio.h>
+#include <time.h>
+#include <rt_misc.h>
+#pragma import(__use_no_semihosting_swi)
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+int fputc(int ch, FILE *f) {
+ debugtester_char_write(ch);
+ return 0;
+}
+
+int fgetc(FILE *f) {
+ return 0;
+}
+
+int ferror(FILE *f) {
+ /* Your implementation of ferror */
+ return EOF;
+}
+
+
+void _ttywrch(int ch) {
+ debugtester_char_write(ch);
+}
+
+
+void _sys_exit(int return_code) {
+label: goto label; /* endless loop */
+}
+
+#else
+
+/******************************************************************************/
+/* Retarget functions for GNU Tools for ARM Embedded Processors */
+/******************************************************************************/
+#include <stdio.h>
+#include <sys/stat.h>
+
+__attribute__ ((used)) int _write (int fd, char *ptr, int len)
+{
+ size_t i;
+ for (i=0; i<len;i++) {
+ debugtester_char_write(ptr[i]); // call character output function
+ }
+ return len;
+}
+
+
+#endif
diff --git a/Cortex-M0/nanosoc/software/debug_tester/system_cmsdk_debugtester.c b/Cortex-M0/nanosoc/software/debug_tester/system_cmsdk_debugtester.c
new file mode 100644
index 0000000000000000000000000000000000000000..5a33bfa1e34d3f7ab159f25e225196686213a940
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/system_cmsdk_debugtester.c
@@ -0,0 +1,61 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2012 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+ //Correspond to the system_device.c file in the CMSIS standard
+ //provide a minimum requirement for the SystemInit function
+
+
+#include <stdint.h>
+#include "system_cmsdk_debugtester.h"
+
+/*----------------------------------------------------------------------------
+ Define SYSCLK
+ *----------------------------------------------------------------------------*/
+#define __HSI (5000000UL)
+
+/*----------------------------------------------------------------------------
+ Clock Definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemFrequency = 50000000UL; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system
+ *
+ */
+void SystemInit (void)
+{
+ //
+ // SystemInit
+ //
+
+ // Empty function for example MCU, since there are no PLLs etc.
+
+}
+
diff --git a/Cortex-M0/nanosoc/software/debug_tester/system_cmsdk_debugtester.h b/Cortex-M0/nanosoc/software/debug_tester/system_cmsdk_debugtester.h
new file mode 100644
index 0000000000000000000000000000000000000000..ce0beb1ac1ba79227ef4f673b402db6c8a841d13
--- /dev/null
+++ b/Cortex-M0/nanosoc/software/debug_tester/system_cmsdk_debugtester.h
@@ -0,0 +1,41 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+#ifndef __SYSTEM_CMSDK_DEBUGTESTER_H
+#define __SYSTEM_CMSDK_DEBUGTESTER_H
+
+extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system
+ * Initialise GPIO directions and values
+ */
+extern void SystemInit (void);
+#endif
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/build_fpga_pynq_z2.scr b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/build_fpga_pynq_z2.scr
new file mode 100755
index 0000000000000000000000000000000000000000..781e2c3ccb10931953140379fc42320888a1cc29
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/build_fpga_pynq_z2.scr
@@ -0,0 +1 @@
+vivado -mode tcl -source scripts/build_mcu_fpga_pynq_z2.tcl
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/build_fpga_pynq_zcu104.scr b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/build_fpga_pynq_zcu104.scr
new file mode 100755
index 0000000000000000000000000000000000000000..8d883a1c515ecfb08bf1579c8e99052635457978
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/build_fpga_pynq_zcu104.scr
@@ -0,0 +1 @@
+vivado -mode batch -source scripts/build_mcu_fpga_pynq_zcu104.tcl
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/clean_fpga.scr b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/clean_fpga.scr
new file mode 100755
index 0000000000000000000000000000000000000000..cf4b0fa112dd2ffa1a1ffa37cdbbd9370d5a772b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/clean_fpga.scr
@@ -0,0 +1,8 @@
+rm -f ./pynq_export/pz2/pynq/overlays/soclabs/*
+rm -f ./pynq_export/pz104/pynq/overlays/soclabs/*
+rm -Rf ./project_pynq_z2
+rm -Rf ./project_pynq_zcu104
+rm -Rf ./vivado*
+rm -Rf ./.gen
+rm -Rf ./.srcs
+rm -Rf ./.Xil
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..690e4e124478e7a541fa5bd5469dc6447e9f893f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml
new file mode 100755
index 0000000000000000000000000000000000000000..afd116f0e666806de4d0ff0d7f50a99ebd8d756e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml
@@ -0,0 +1,1456 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>axi_stream_io</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWPROT</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARPROT</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WSTRB</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIZ_NUM_REG</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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+ <xilinx:tag xilinx:name="ui.data.coregen.df@38e9bfee_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
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+ <xilinx:tag xilinx:name="ui.data.coregen.df@348407d1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
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+ <xilinx:tag xilinx:name="ui.data.coregen.df@21bb058_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
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+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5562313f"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="d6592117"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="323cdeea"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="7c2aad6e"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cd9ec9b5"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="6cced3b9"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
new file mode 100755
index 0000000000000000000000000000000000000000..d7af75e2819376e5c2c39a5f2e0ae96d14f52b63
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER axi_stream_io
+ OPTION supported_peripherals = (axi_stream_io);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = axi_stream_io;
+END DRIVER
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..c3a9cd03e1863921dd4ab5cbc6e020d40ae2757b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "axi_stream_io" "NUM_INSTANCES" "DEVICE_ID" "C_axi_s_BASEADDR" "C_axi_s_HIGHADDR"
+}
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
new file mode 100755
index 0000000000000000000000000000000000000000..21453f41a1f9f82d13b20509b772556244d9f08d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling axi_stream_io..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
new file mode 100755
index 0000000000000000000000000000000000000000..c552cbf0e917a961b599672e2ffd4327293d004c
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "axi_stream_io.h"
+
+/************************** Function Definitions ***************************/
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
new file mode 100755
index 0000000000000000000000000000000000000000..294e8516087a45c4aa2229806fe30eb93e47c9b9
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
@@ -0,0 +1,79 @@
+
+#ifndef AXI_STREAM_IO_H
+#define AXI_STREAM_IO_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXI_STREAM_IO_axi_s_SLV_REG0_OFFSET 0
+#define AXI_STREAM_IO_axi_s_SLV_REG1_OFFSET 4
+#define AXI_STREAM_IO_axi_s_SLV_REG2_OFFSET 8
+#define AXI_STREAM_IO_axi_s_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXI_STREAM_IO register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the AXI_STREAM_IOdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void AXI_STREAM_IO_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXI_STREAM_IO_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXI_STREAM_IO register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the AXI_STREAM_IO device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 AXI_STREAM_IO_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXI_STREAM_IO_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the AXI_STREAM_IO instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXI_STREAM_IO_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXI_STREAM_IO_H
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
new file mode 100755
index 0000000000000000000000000000000000000000..26bea4d0c70f3d34776b08b13b6c877f2034dea1
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "axi_stream_io.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the AXI_STREAM_IOinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXI_STREAM_IO_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ AXI_STREAM_IO_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( AXI_STREAM_IO_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..2a22446f1995db34a975c88b9976e397a70995e4
Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip differ
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
new file mode 100755
index 0000000000000000000000000000000000000000..c6560f7d9f7273274985938b456c1f1479797a92
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
@@ -0,0 +1,424 @@
+
+`timescale 1 ns / 1 ps
+
+ module iostream_v1_0_axi #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXI data bus
+ parameter integer C_S_AXI_DATA_WIDTH = 32,
+ // Width of S_AXI address bus
+ parameter integer C_S_AXI_ADDR_WIDTH = 4
+ )
+ (
+ // Users to add ports here
+ output wire interrupt,
+
+ // Ports of Axi Master Bus Interface tx
+// input wire tx_aclk,
+// input wire tx_aresetn,
+ output wire tx_tvalid,
+ output wire [7 : 0] tx_tdata,
+// output wire [0 : 0] tx_tstrb,
+// output wire tx_tlast,
+ input wire tx_tready,
+
+ // Ports of Axi Slave Bus Interface rx
+// input wire rx_aclk,
+// input wire rx_aresetn,
+ output wire rx_tready,
+ input wire [7 : 0] rx_tdata,
+// input wire [0 : 0] rx_tstrb,
+// input wire rx_tlast,
+ input wire rx_tvalid,
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global Clock Signal
+ input wire S_AXI_ACLK,
+ // Global Reset Signal. This Signal is Active LOW
+ input wire S_AXI_ARESETN,
+ // Write address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+ // Write channel Protection type. This signal indicates the
+ // privilege and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_AWPROT,
+ // Write address valid. This signal indicates that the master signaling
+ // valid write address and control information.
+ input wire S_AXI_AWVALID,
+ // Write address ready. This signal indicates that the slave is ready
+ // to accept an address and associated control signals.
+ output wire S_AXI_AWREADY,
+ // Write data (issued by master, acceped by Slave)
+ input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+ // Write strobes. This signal indicates which byte lanes hold
+ // valid data. There is one write strobe bit for each eight
+ // bits of the write data bus.
+ input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available.
+ input wire S_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ output wire S_AXI_WREADY,
+ // Write response. This signal indicates the status
+ // of the write transaction.
+ output wire [1 : 0] S_AXI_BRESP,
+ // Write response valid. This signal indicates that the channel
+ // is signaling a valid write response.
+ output wire S_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ input wire S_AXI_BREADY,
+ // Read address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether the
+ // transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_ARPROT,
+ // Read address valid. This signal indicates that the channel
+ // is signaling valid read address and control information.
+ input wire S_AXI_ARVALID,
+ // Read address ready. This signal indicates that the slave is
+ // ready to accept an address and associated control signals.
+ output wire S_AXI_ARREADY,
+ // Read data (issued by slave)
+ output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+ // Read response. This signal indicates the status of the
+ // read transfer.
+ output wire [1 : 0] S_AXI_RRESP,
+ // Read valid. This signal indicates that the channel is
+ // signaling the required read data.
+ output wire S_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ input wire S_AXI_RREADY
+ );
+
+ // AXI4LITE signals
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awready;
+ reg axi_wready;
+ reg [1 : 0] axi_bresp;
+ reg axi_bvalid;
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arready;
+ reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
+ reg [1 : 0] axi_rresp;
+ reg axi_rvalid;
+
+ // Example-specific design signals
+ // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ // ADDR_LSB is used for addressing 32/64 bit registers/memories
+ // ADDR_LSB = 2 for 32 bits (n downto 2)
+ // ADDR_LSB = 3 for 64 bits (n downto 3)
+ localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+ localparam integer OPT_MEM_ADDR_BITS = 1;
+
+ //----------------------------------------------
+ //-- Signals for user logic register space example
+ //------------------------------------------------
+ //-- Number of Slave Registers 4
+ reg [8:0] tx_reg; // TX data
+ reg [8:0] rx_reg; // RX data
+ reg [7:0] ctrl_reg; // ctrl
+ wire slv_reg_rden;
+ wire slv_reg_wren;
+ reg [7:0] reg_data_out;
+ integer byte_index;
+ reg aw_en;
+
+ wire tx_req = tx_reg[8]; // request to transmit
+ wire tx_ack = tx_tready; // acknowledge when stream ready
+
+ wire rx_req = rx_tvalid; // request to receive
+ wire rx_ack = !rx_reg[8];
+ wire rx_val = rx_reg[8];
+
+ //assign rx_reg[7:0] <= rx_tdata;
+
+ // I/O Connections assignments
+
+ assign interrupt = ctrl_reg[4] & (!tx_req | rx_req);
+
+ // TX stream interface
+ assign tx_tdata = tx_reg[7:0];
+ assign tx_tvalid = tx_req;
+
+ // RX stream interface
+ assign rx_tready = rx_ack;
+
+ //AXI Slave
+ assign S_AXI_AWREADY = axi_awready;
+ assign S_AXI_WREADY = axi_wready;
+ assign S_AXI_BRESP = axi_bresp;
+ assign S_AXI_BVALID = axi_bvalid;
+ assign S_AXI_ARREADY = axi_arready;
+ assign S_AXI_RDATA = axi_rdata;
+ assign S_AXI_RRESP = axi_rresp;
+ assign S_AXI_RVALID = axi_rvalid;
+ // Implement axi_awready generation
+ // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awready <= 1'b0;
+ aw_en <= 1'b1;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // slave is ready to accept write address when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_awready <= 1'b1;
+ aw_en <= 1'b0;
+ end
+ else if (S_AXI_BREADY && axi_bvalid)
+ begin
+ aw_en <= 1'b1;
+ axi_awready <= 1'b0;
+ end
+ else
+ begin
+ axi_awready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_awaddr latching
+ // This process is used to latch the address when both
+ // S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awaddr <= 0;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end
+ end
+ end
+
+ // Implement axi_wready generation
+ // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_wready <= 1'b0;
+ end
+ else
+ begin
+ if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+ begin
+ // slave is ready to accept write data when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_wready <= 1'b1;
+ end
+ else
+ begin
+ axi_wready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and write logic generation
+ // The write data is accepted and written to memory mapped registers when
+ // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ // select byte enables of slave registers while writing.
+ // These registers are cleared when reset (active low) is applied.
+ // Slave register write enable is asserted when valid address and data are available
+ // and the slave is ready to accept the write address and write data.
+ assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ rx_reg <= 0;
+ else if ((ctrl_reg[1] == 1'b1))
+ rx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
+ rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
+ rx_reg[8] <= 1'b0;
+ else if (rx_req & rx_ack) // check precedence (rx_req)
+ rx_reg[8:0] <= {1'b1, rx_tdata[7:0]};
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ tx_reg <= 0;
+ else if ((ctrl_reg[0] == 1'b1))
+ tx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1))
+ tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (tx_req & tx_ack)
+ tx_reg[8] <= 1'b0;
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ ctrl_reg <= 8'b00000100;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h3))
+ ctrl_reg[7:0] <= S_AXI_WDATA[7:0];
+ end
+
+ // Implement write response logic generation
+ // The write response and response valid signals are asserted by the slave
+ // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ // This marks the acceptance of address and indicates the status of
+ // write transaction.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_bvalid <= 0;
+ axi_bresp <= 2'b0;
+ end
+ else
+ begin
+ if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+ begin
+ // indicates a valid write response is available
+ axi_bvalid <= 1'b1;
+ axi_bresp <= 2'b0; // 'OKAY' response
+ end // work error responses in future
+ else
+ begin
+ if (S_AXI_BREADY && axi_bvalid)
+ //check if bready is asserted while bvalid is high)
+ //(there is a possibility that bready is always asserted high)
+ begin
+ axi_bvalid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ // Implement axi_arready generation
+ // axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ // S_AXI_ARVALID is asserted. axi_awready is
+ // de-asserted when reset (active low) is asserted.
+ // The read address is also latched when S_AXI_ARVALID is
+ // asserted. axi_araddr is reset to zero on reset assertion.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_arready <= 1'b0;
+ axi_araddr <= 32'b0;
+ end
+ else
+ begin
+ if (~axi_arready && S_AXI_ARVALID)
+ begin
+ // indicates that the slave has acceped the valid read address
+ axi_arready <= 1'b1;
+ // Read address latching
+ axi_araddr <= S_AXI_ARADDR;
+ end
+ else
+ begin
+ axi_arready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_arvalid generation
+ // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ // data are available on the axi_rdata bus at this instance. The
+ // assertion of axi_rvalid marks the validity of read data on the
+ // bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ // is deasserted on reset (active low). axi_rresp and axi_rdata are
+ // cleared to zero on reset (active low).
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rvalid <= 0;
+ axi_rresp <= 0;
+ end
+ else
+ begin
+ if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+ begin
+ // Valid read data is available at the read data bus
+ axi_rvalid <= 1'b1;
+ axi_rresp <= 2'b0; // 'OKAY' response
+ end
+ else if (axi_rvalid && S_AXI_RREADY)
+ begin
+ // Read data is accepted by the master
+ axi_rvalid <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and read logic generation
+ // Slave register read enable is asserted when valid address is available
+ // and the slave is ready to accept the read address.
+ assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+ always @(*)
+ begin
+ // Address decoding for reading registers
+ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+ 2'h0 : reg_data_out <= rx_reg[7:0];
+ 2'h1 : reg_data_out <= tx_reg[7:0];
+ 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], tx_req, !tx_req, rx_val, rx_val};
+ 2'h3 : reg_data_out <= ctrl_reg;
+ default : reg_data_out <= 0;
+ endcase
+ end
+
+ // Output register or memory read data
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rdata <= 0;
+ end
+ else
+ begin
+ // When there is a valid read address (S_AXI_ARVALID) with
+ // acceptance of read address by the slave (axi_arready),
+ // output the read dada
+ if (slv_reg_rden)
+ begin
+ axi_rdata <= {24'h000000, reg_data_out}; // register read data
+ end
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..fcf8a063ad02ac8d5e1c0cefd2eaf6c6e8339a41
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
@@ -0,0 +1,58 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_axi_s_BASEADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_axi_s_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_S_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_S_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_axi_s_BASEADDR { PARAM_VALUE.C_axi_s_BASEADDR } {
+ # Procedure called to update C_axi_s_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_axi_s_BASEADDR { PARAM_VALUE.C_axi_s_BASEADDR } {
+ # Procedure called to validate C_axi_s_BASEADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_axi_s_HIGHADDR { PARAM_VALUE.C_axi_s_HIGHADDR } {
+ # Procedure called to update C_axi_s_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_axi_s_HIGHADDR { PARAM_VALUE.C_axi_s_HIGHADDR } {
+ # Procedure called to validate C_axi_s_HIGHADDR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
+}
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/bd/bd.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/bd/bd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c9d8d6e573fef4d3a7f1d643e634a02f82032d93
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml
@@ -0,0 +1,127 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix
new file mode 100644
index 0000000000000000000000000000000000000000..1b2410ad1ecde98574e898028f41ad55c1c8f3b1
Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix differ
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..822ab4cd47a344ec599d082d80384686bdb6360d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
@@ -0,0 +1,75 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Slave Bus Interface RXD8
+ parameter integer C_RXD8_TDATA_WIDTH = 32,
+
+ // Parameters of Axi Master Bus Interface TXD8
+ parameter integer C_TXD8_TDATA_WIDTH = 32,
+ parameter integer C_TXD8_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Slave Bus Interface RXD8
+ input wire rxd8_aclk,
+ input wire rxd8_aresetn,
+ output wire rxd8_tready,
+ input wire [C_RXD8_TDATA_WIDTH-1 : 0] rxd8_tdata,
+ input wire [(C_RXD8_TDATA_WIDTH/8)-1 : 0] rxd8_tstrb,
+ input wire rxd8_tlast,
+ input wire rxd8_tvalid,
+
+ // Ports of Axi Master Bus Interface TXD8
+ input wire txd8_aclk,
+ input wire txd8_aresetn,
+ output wire txd8_tvalid,
+ output wire [C_TXD8_TDATA_WIDTH-1 : 0] txd8_tdata,
+ output wire [(C_TXD8_TDATA_WIDTH/8)-1 : 0] txd8_tstrb,
+ output wire txd8_tlast,
+ input wire txd8_tready
+ );
+// Instantiation of Axi Bus Interface RXD8
+ ft1248x1_to_stream8_v1_0_RXD8 # (
+ .C_S_AXIS_TDATA_WIDTH(C_RXD8_TDATA_WIDTH)
+ ) ft1248x1_to_stream8_v1_0_RXD8_inst (
+ .S_AXIS_ACLK(rxd8_aclk),
+ .S_AXIS_ARESETN(rxd8_aresetn),
+ .S_AXIS_TREADY(rxd8_tready),
+ .S_AXIS_TDATA(rxd8_tdata),
+ .S_AXIS_TSTRB(rxd8_tstrb),
+ .S_AXIS_TLAST(rxd8_tlast),
+ .S_AXIS_TVALID(rxd8_tvalid)
+ );
+
+// Instantiation of Axi Bus Interface TXD8
+ ft1248x1_to_stream8_v1_0_TXD8 # (
+ .C_M_AXIS_TDATA_WIDTH(C_TXD8_TDATA_WIDTH),
+ .C_M_START_COUNT(C_TXD8_START_COUNT)
+ ) ft1248x1_to_stream8_v1_0_TXD8_inst (
+ .M_AXIS_ACLK(txd8_aclk),
+ .M_AXIS_ARESETN(txd8_aresetn),
+ .M_AXIS_TVALID(txd8_tvalid),
+ .M_AXIS_TDATA(txd8_tdata),
+ .M_AXIS_TSTRB(txd8_tstrb),
+ .M_AXIS_TLAST(txd8_tlast),
+ .M_AXIS_TREADY(txd8_tready)
+ );
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
new file mode 100644
index 0000000000000000000000000000000000000000..9b39ac62c1aa1246d5b566160b5bd7b5dd1d07ad
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0_RXD8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
new file mode 100644
index 0000000000000000000000000000000000000000..3abf9f8a3c52a9a6716e09c985c2a15faa383be5
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0_TXD8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/ip_project_archive.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/ip_project_archive.zip
new file mode 100755
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diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip
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Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip differ
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
new file mode 100755
index 0000000000000000000000000000000000000000..6c55abc8d956769a1ca142d910603d780445a4ca
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
@@ -0,0 +1,187 @@
+//-----------------------------------------------------------------------------
+// FT1248 1-bit-data to 8-bit AXI-Stream IO
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+//-----------------------------------------------------------------------------
+
+
+module ft1248x1_to_stream8
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+// inout wire ft_miosio_io, // MIOSIO tristate output control
+ input wire ft_miosio_i,
+ output wire ft_miosio_o,
+ output wire ft_miosio_z,
+// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO
+//
+// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
+
+ input wire clk, // external primary clock
+ input wire resetn, // external reset (active low)
+
+ // Ports of Axi stream Bus Interface TXD
+ output wire txd_tvalid_o,
+ output wire [7 : 0] txd_tdata8_o,
+ input wire txd_tready_i,
+
+ // Ports of Axi stream Bus Interface RXD
+ output wire rxd_tready_o,
+ input wire [7 : 0] rxd_tdata8_i,
+ input wire rxd_tvalid_i
+
+ );
+
+//wire ft_clk;
+wire ft_clk_rising;
+wire ft_clk_falling;
+
+wire ft_ssn;
+//wire ft_ssn_rising;
+//wire ft_ssn_falling;
+
+SYNCHRONIZER_EDGES u_xync_ft_clk (
+ .testmode_i(1'b0),
+ .clk_i(clk),
+ .reset_n_i(resetn),
+ .asyn_i(ft_clk_i),
+ .syn_o(),
+ .posedge_o(ft_clk_rising),
+ .negedge_o(ft_clk_falling)
+ );
+
+SYNCHRONIZER_EDGES u_xync_ft_ssn (
+ .testmode_i(1'b0),
+ .clk_i(clk),
+ .reset_n_i(resetn),
+ .asyn_i(ft_ssn_i),
+ .syn_o(ft_ssn),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+//----------------------------------------------
+//-- FT1248 1-bit protocol State Machine
+//----------------------------------------------
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [4:0] ft_nextstate = ft_state + 5'b00001;
+
+// advance state count on rising edge of ft_clk
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ft_state <= 5'b11111;
+ else if (ft_ssn) // sync reset
+ ft_state <= 5'b11111;
+ else if (ft_clk_rising) // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// capture 7-bit CMD on falling edge of clock (mid-data)
+reg [7:0] ft_cmd;
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ft_cmd <= 8'b00000001;
+ else if (ft_ssn) // sync reset
+ ft_cmd <= 8'b00000001;
+ else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
+ ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// capture (ft_cmd_txd) serial data out on falling edge of clock
+// bit [0] indicated byte valid
+reg [7:0] rxd_sr;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ rxd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ rxd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
+ rxd_sr <= {ft_miosio_i, rxd_sr[7:1]};
+
+// AXI STREAM handshake interfaces
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txstream;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ txstream <= 9'b000000000;
+ else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
+ txstream[8] <= 1'b0;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
+ txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]};
+
+assign txd_tvalid_o = txstream[8];
+assign txd_tdata8_o = txstream[7:0];
+
+
+// AXI STREAM handshake interfaces
+// RX stream accepts 8-bit data to transfer over FT1248 channel
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] rxstream;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ rxstream <= 9'b000000000;
+ else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
+ rxstream[8:0] <= {1'b1,rxd_tdata8_i};
+ else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
+ rxstream[8] <= 1'b0;
+assign rxd_tready_o = !rxstream[8]; // ready until loaded
+
+// shift TXD on rising edge of clock
+reg [7:0] txd_sr;
+// rewrite for clocked
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ txd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ txd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111))
+ txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000;
+ else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
+ txd_sr <= {1'b0,txd_sr[7:1]};
+
+
+//FT1248 FIFO status signals
+
+// ft_miso_o reflects TXF when deselected
+assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0];
+
+// ft_miso_o reflects RXE when deselected
+assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
+
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/src/synclib.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/src/synclib.v
new file mode 100755
index 0000000000000000000000000000000000000000..1daf61f27dffed42591278f8e46a4239a46554a2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/src/synclib.v
@@ -0,0 +1,139 @@
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
+
+module SYNCHRONIZER_RST_LO (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+module SYNCHRONIZER_RST_HI (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b1;
+ sync_stage2 <= 1'b1;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+
+module NRST_SYNCHRONIZER_LO (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,output wire synreset_n_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= 1'b1;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign synreset_n_o = (testmode_i) ? reset_n_i : sync_stage2;
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0db18e9a9d18f3e4b14481f7664b048781110ca3
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
new file mode 100755
index 0000000000000000000000000000000000000000..4da3b3396dff1710d66e943d7e91337483665b50
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
@@ -0,0 +1,88 @@
+from time import sleep, time
+from pynq import MMIO
+
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+
+#Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+OVERRUN_ERR = 5
+FRAME_ERR = 6
+PARITY_ERR =7
+
+#Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class UartLite:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address,0x10000, debug=False)
+ self.address = address
+
+ def getBit(self,num,pos):
+ return (num&1<<pos)>>pos
+
+ def setupCtrlReg(self):
+ # Reset FIFOs, disable interrupts
+ self.uart.write(CTRL_REG, 1<<RST_TX | 1<<RST_RX)
+ sleep(0.0)
+ self.uart.write(CTRL_REG,0)
+ sleep(0.0)
+
+ def currentStatus(self):
+ """Returns object that specifies current status of axi core"""
+ status = self.uart.read(STAT_REG)
+ return {'RX_VALID':self.getBit(status,RX_VALID),
+ 'RX_FULL':self.getBit(status, RX_FULL),
+ 'TX_EMPTY':self.getBit(status, TX_EMPTY),
+ 'TX_FULL':self.getBit(status, TX_FULL),
+ 'IS_INTR':self.getBit(status, IS_INTR),
+ 'OVERRUN_ERR':self.getBit(status, OVERRUN_ERR),
+ 'FRAME_ERR':self.getBit(status, FRAME_ERR),
+ 'PARITY_ERR':self.getBit(status, PARITY_ERR)}
+
+ def read(self, count, timeout = 1):
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, skip if timeout exceeded
+ while (not (self.uart.read(STAT_REG) & 1<<RX_VALID)) and (time()<stop_time):
+ pass
+ if time()>=stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout = 10):
+ """
+ buf: iterable
+
+ """
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ #Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1<<TX_FULL) and (time()<stop_time):
+ pass
+ # Check timeout
+ if time()>stop_time:
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+ def readLine(self):
+ buf = self.read(1)
+ if len(buf) ==0:
+ return ""
+ while '\n' not in buf:
+ buf += self.read(1)
+ return buf
\ No newline at end of file
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..cef03a2bdbda425ca0a6a5b6688d97da8b8cf2da
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
@@ -0,0 +1,372 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# SoCLabs cm0sdk mcu overlay\n",
+ "This notebook demonstrates how to download the FPGA overlay and communicate with programmable logic state. \n",
+ "\n",
+ "## 1. Instantiating an overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, a `soclabs` overlay called `design_1` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"soclabs/design_1.bit\")\n",
+ "```\n",
+ "A `drivers` directory is provided for device driver templates for comms channels. (uartlite example).\n",
+ "\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "from pynq import MMIO\n",
+ "\n",
+ "import sys\n",
+ "sys.path.insert(1, './driver')\n",
+ "from uartlite import *\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed.\n",
+ "\n",
+ "Next try relative path:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "ol = Overlay(\"soclabs/design_1.bit\")"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'/usr/local/lib/python3.6/dist-packages/pynq/overlays/soclabs/design_1.bit'"
+ ]
+ },
+ "execution_count": 4,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 5,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "True"
+ ]
+ },
+ "execution_count": 6,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Establishing communications \n",
+ "Next set up a serial channel (configured for 9600 baud clocking rate).\n",
+ "Re-download image which also resets the MCU design in PL.\n",
+ "(No explicit to reinitialize the UART after HW reset, as preconfigured baud rate).\n",
+ "Poll for start-up banner from MCU internal boot-ROM.\n",
+ "\n",
+ "Expect a message of the form (sometimes characters are lost as uartlite has no no flow-control support)\n",
+ "\n",
+ "```python\n",
+ " SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "```"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "# Address of the uart core\n",
+ "ADDRESS = 0x80030000\n",
+ "uart = UartLite(ADDRESS)\n",
+ "ol.download()\n",
+ "# Setup AXI UART register\n",
+ "#uart.setupCtrlReg()\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "print(uart.read(45,1))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "{'RX_VALID': 0, 'RX_FULL': 0, 'TX_EMPTY': 1, 'TX_FULL': 0, 'IS_INTR': 0, 'OVERRUN_ERR': 0, 'FRAME_ERR': 0, 'PARITY_ERR': 0}\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(uart.currentStatus())"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#ol.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "image/png": 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TuHeA/UuShqTvI4OqemNVLauqg4BTgKur6uXANcDLWrWVwGXt/uVtmbb+6qqqfvcvSRqe7fE9gzcAr0myhu6cwHmt/DxgcSt/DXDGdti3JKkPg0wT/UxVXQtc2+7fChy9lTo/An5vGPuTJA2X30CWJBkGkiTDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkYRhIkjAMJEkYBpIkDANJEoaBJAnDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSSJAcIgyQFJrklyc5Kbkryqle+d5Mokt7TbvVp5knwgyZok301y5LAehCRpMIMcGTwGvLaqDgeOAV6Z5HDgDOCqqjoUuKotAxwPHNp+Tgc+NMC+JUlD1HcYVNW6qvp2u/8wsBpYCqwAzm/VzgdOavdXABdU55vAoiT79d1zSdLQDOWcQZKDgGcC1wH7VtW6tuoeYN92fylwZ89md7Wyzds6Pcl4kvGNGzcOo3uSpCkMHAZJdgc+A7y6qh7qXVdVBdRM2quqc6tqrKrGlixZMmj3JEnTMFAYJNmJLgguqqrPtuL1E9M/7XZDK18LHNCz+bJWJkmaY4N8mijAecDqqnpfz6rLgZXt/krgsp7yU9unio4BHuyZTpIkzaGFA2z7HOCPgBuSfKeVvQl4F3BJktOA24GT27ovAScAa4AfAq8YYN+SpCHqOwyq6m+ATLL62K3UL+CV/e5PkrT9+A1kSZJhIEkyDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSYx6GKxaBQcdBBddNL36F13U1X/Sk2a2XT8m29co9KHf/vW7bpj9m82+j3p7O3LfR7292d7XZGbz9WIqVTWyP0dBFVTtumvVhRd2/zDzwgurli+vSrrb3vJdd+3qb77dZNtsq71+9vUnfzJ5HwbZVz+Pd6b966e9bY3tIO3NRt9Hvb0due+j3t6O8Bzp5zWhBzA+09fbGVWe7Z+jegdp4kFPNnjLl/98+cTP4sXD/+VOtq8FC7ZePlXf+/nDnKwPy5f3179+2tvW2PbT3mz2fdTb25H7Purt7QjPkX7fcA4QBum2G01jSY1PLCRw4IFw++1bVly+HO64oxua6Vq+vLudrL1trZvpvqbq+2T7WrAAHn98Zn1Iu6r4TPs32Tb9tNdv/0ah76PS3o7c91FvbxT6PtVzZLLXi229Jtx2W08TWVVVY9PvEDtQGPQ7eJMZ5A+pn1/UsF+8hx0uk22zrXXD7t9s9n3U29uR+z7q7e0Iz5F+3nA+8UTP4szDYEaHEXM2TTTIYdXixcM97Ov3EG7Yh6yjMB+6rbEd9bncUW9vR+77qLe3IzxH+nlNGHCaaEaV5yQMBj3hMuw/ln5P7gz7D3Nb++qnf/2s63eMRqHvO0J7O3LfR7292drXIK8js3zOYM5f8Lf1c9RRR9UWtvXLmMz2+EPqx7D/MEfBqPdPmmv9PkcGeE3oJwxG+5zB2FiNj49PXVGS9DP9nDMY7S+dSZJmhWEgSTIMJEmGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkMQdhkOS4JP+QZE2SM2Z7/5KkLc1qGCRZAPwP4HjgcOD3kxw+m32QJG1pto8MjgbWVNWtVfUT4JPAilnugyRpMwtneX9LgTt7lu8CntVbIcnpwOlt8cdJbpylvo26fYDvz3UnRoRjsYljsYljscnTZrrBbIfBlKrqXOBcgCTjM/0/nr+oHItNHItNHItNHItNksz4n8fP9jTRWuCAnuVlrUySNIdmOwy+BRya5OAkOwOnAJfPch8kSZuZ1WmiqnosyZ8CVwALgI9W1U3b2OTc2enZDsGx2MSx2MSx2MSx2GTGY5Gq2h4dkSTtQPwGsiTJMJAkjXAYzOfLViT5aJINvd+xSLJ3kiuT3NJu95rLPs6WJAckuSbJzUluSvKqVj7vxiPJLkn+Lsnft7F4eys/OMl17bnyqfbhjF94SRYkuT7JF9vyvBwHgCS3JbkhyXcmPlY60+fISIaBl63g48Bxm5WdAVxVVYcCV7Xl+eAx4LVVdThwDPDK9rcwH8fjx8CLquoZwBHAcUmOAd4NnF1VhwD3A6fNYR9n06uA1T3L83UcJrywqo7o+a7FjJ4jIxkGzPPLVlTV14H7NiteAZzf7p8PnDSrnZojVbWuqr7d7j9M9+Rfyjwcj+o80hZ3aj8FvAi4tJXPi7FIsgx4CfCRthzm4ThMYUbPkVENg61dtmLpHPVlVOxbVeva/XuAfeeyM3MhyUHAM4HrmKfj0aZGvgNsAK4E/h/wQFU91qrMl+fK+4HXA0+05cXMz3GYUMBXk6xql/SBGT5HRu5yFJpaVVWSefWZ4CS7A58BXl1VD3VvBDvzaTyq6nHgiCSLgM8Bh81xl2ZdkpcCG6pqVZIXzHV/RsRzq2ptkl8Crkzyvd6V03mOjOqRgZet2NL6JPsBtNsNc9yfWZNkJ7oguKiqPtuK5+14AFTVA8A1wLOBRUkm3tjNh+fKc4DfTXIb3RTyi4BzmH/j8DNVtbbdbqB7k3A0M3yOjGoYeNmKLV0OrGz3VwKXzWFfZk2bCz4PWF1V7+tZNe/GI8mSdkRAkqcAv0N3DuUa4GWt2i/8WFTVG6tqWVUdRPfacHVVvZx5Ng4TkuyW5KkT94EXAzcyw+fIyH4DOckJdPOCE5etOGuOuzRrklwMvIDukrzrgbcCnwcuAQ4EbgdOrqrNTzL/wknyXOAbwA1smh9+E915g3k1Hkn+Od2JwAV0b+Quqap3JPkVunfIewPXA39YVT+eu57OnjZN9Lqqeul8HYf2uD/XFhcCn6iqs5IsZgbPkZENA0nS7BnVaSJJ0iwyDCRJhoEkyTCQJGEYSJIwDCRJGAaSJOD/Az15XOWF/4x9AAAAAElFTkSuQmCC\n",
+ "text/plain": [
+ "<matplotlib.figure.Figure at 0xaefaa6b0>"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
new file mode 100755
index 0000000000000000000000000000000000000000..4da3b3396dff1710d66e943d7e91337483665b50
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
@@ -0,0 +1,88 @@
+from time import sleep, time
+from pynq import MMIO
+
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+
+#Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+OVERRUN_ERR = 5
+FRAME_ERR = 6
+PARITY_ERR =7
+
+#Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class UartLite:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address,0x10000, debug=False)
+ self.address = address
+
+ def getBit(self,num,pos):
+ return (num&1<<pos)>>pos
+
+ def setupCtrlReg(self):
+ # Reset FIFOs, disable interrupts
+ self.uart.write(CTRL_REG, 1<<RST_TX | 1<<RST_RX)
+ sleep(0.0)
+ self.uart.write(CTRL_REG,0)
+ sleep(0.0)
+
+ def currentStatus(self):
+ """Returns object that specifies current status of axi core"""
+ status = self.uart.read(STAT_REG)
+ return {'RX_VALID':self.getBit(status,RX_VALID),
+ 'RX_FULL':self.getBit(status, RX_FULL),
+ 'TX_EMPTY':self.getBit(status, TX_EMPTY),
+ 'TX_FULL':self.getBit(status, TX_FULL),
+ 'IS_INTR':self.getBit(status, IS_INTR),
+ 'OVERRUN_ERR':self.getBit(status, OVERRUN_ERR),
+ 'FRAME_ERR':self.getBit(status, FRAME_ERR),
+ 'PARITY_ERR':self.getBit(status, PARITY_ERR)}
+
+ def read(self, count, timeout = 1):
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, skip if timeout exceeded
+ while (not (self.uart.read(STAT_REG) & 1<<RX_VALID)) and (time()<stop_time):
+ pass
+ if time()>=stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout = 10):
+ """
+ buf: iterable
+
+ """
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ #Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1<<TX_FULL) and (time()<stop_time):
+ pass
+ # Check timeout
+ if time()>stop_time:
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+ def readLine(self):
+ buf = self.read(1)
+ if len(buf) ==0:
+ return ""
+ while '\n' not in buf:
+ buf += self.read(1)
+ return buf
\ No newline at end of file
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..4a2d262f56441d06113459a833653c72aaca475a
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
@@ -0,0 +1,372 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# SoCLabs cm0sdk mcu overlay\n",
+ "This notebook demonstrates how to download the FPGA overlay and communicate with programmable logic state. \n",
+ "\n",
+ "## 1. Instantiating an overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, a `soclabs` overlay called `design_1` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"soclabs/design_1.bit\")\n",
+ "```\n",
+ "A `drivers` directory is provided for device driver templates for comms channels. (uartlite example).\n",
+ "\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "from pynq import MMIO\n",
+ "\n",
+ "import sys\n",
+ "sys.path.insert(1, './driver')\n",
+ "from uartlite import *\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed.\n",
+ "\n",
+ "Next try relative path:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "ol = Overlay(\"soclabs/design_1.bit\")"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'/usr/local/lib/python3.6/dist-packages/pynq/overlays/soclabs/design_1.bit'"
+ ]
+ },
+ "execution_count": 4,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 5,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "True"
+ ]
+ },
+ "execution_count": 6,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Establishing communications \n",
+ "Next set up a serial channel (configured for 9600 baud clocking rate).\n",
+ "Re-download image which also resets the MCU design in PL.\n",
+ "(No explicit to reinitialize the UART after HW reset, as preconfigured baud rate).\n",
+ "Poll for start-up banner from MCU internal boot-ROM.\n",
+ "\n",
+ "Expect a message of the form (sometimes characters are lost as uartlite has no no flow-control support)\n",
+ "\n",
+ "```python\n",
+ " SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "```"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "# Address of the uart core\n",
+ "ADDRESS = 0x42C00000\n",
+ "uart = UartLite(ADDRESS)\n",
+ "ol.download()\n",
+ "# Setup AXI UART register\n",
+ "#uart.setupCtrlReg()\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "print(uart.read(45,1))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "{'RX_VALID': 0, 'RX_FULL': 0, 'TX_EMPTY': 1, 'TX_FULL': 0, 'IS_INTR': 0, 'OVERRUN_ERR': 0, 'FRAME_ERR': 0, 'PARITY_ERR': 0}\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(uart.currentStatus())"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#ol.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "image/png": 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TuHeA/UuShqTvI4OqemNVLauqg4BTgKur6uXANcDLWrWVwGXt/uVtmbb+6qqqfvcvSRqe7fE9gzcAr0myhu6cwHmt/DxgcSt/DXDGdti3JKkPg0wT/UxVXQtc2+7fChy9lTo/An5vGPuTJA2X30CWJBkGkiTDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkYRhIkjAMJEkYBpIkDANJEoaBJAnDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSSJAcIgyQFJrklyc5Kbkryqle+d5Mokt7TbvVp5knwgyZok301y5LAehCRpMIMcGTwGvLaqDgeOAV6Z5HDgDOCqqjoUuKotAxwPHNp+Tgc+NMC+JUlD1HcYVNW6qvp2u/8wsBpYCqwAzm/VzgdOavdXABdU55vAoiT79d1zSdLQDOWcQZKDgGcC1wH7VtW6tuoeYN92fylwZ89md7Wyzds6Pcl4kvGNGzcOo3uSpCkMHAZJdgc+A7y6qh7qXVdVBdRM2quqc6tqrKrGlixZMmj3JEnTMFAYJNmJLgguqqrPtuL1E9M/7XZDK18LHNCz+bJWJkmaY4N8mijAecDqqnpfz6rLgZXt/krgsp7yU9unio4BHuyZTpIkzaGFA2z7HOCPgBuSfKeVvQl4F3BJktOA24GT27ovAScAa4AfAq8YYN+SpCHqOwyq6m+ATLL62K3UL+CV/e5PkrT9+A1kSZJhIEkyDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSYx6GKxaBQcdBBddNL36F13U1X/Sk2a2XT8m29co9KHf/vW7bpj9m82+j3p7O3LfR7292d7XZGbz9WIqVTWyP0dBFVTtumvVhRd2/zDzwgurli+vSrrb3vJdd+3qb77dZNtsq71+9vUnfzJ5HwbZVz+Pd6b966e9bY3tIO3NRt9Hvb0due+j3t6O8Bzp5zWhBzA+09fbGVWe7Z+jegdp4kFPNnjLl/98+cTP4sXD/+VOtq8FC7ZePlXf+/nDnKwPy5f3179+2tvW2PbT3mz2fdTb25H7Purt7QjPkX7fcA4QBum2G01jSY1PLCRw4IFw++1bVly+HO64oxua6Vq+vLudrL1trZvpvqbq+2T7WrAAHn98Zn1Iu6r4TPs32Tb9tNdv/0ah76PS3o7c91FvbxT6PtVzZLLXi229Jtx2W08TWVVVY9PvEDtQGPQ7eJMZ5A+pn1/UsF+8hx0uk22zrXXD7t9s9n3U29uR+z7q7e0Iz5F+3nA+8UTP4szDYEaHEXM2TTTIYdXixcM97Ov3EG7Yh6yjMB+6rbEd9bncUW9vR+77qLe3IzxH+nlNGHCaaEaV5yQMBj3hMuw/ln5P7gz7D3Nb++qnf/2s63eMRqHvO0J7O3LfR7292drXIK8js3zOYM5f8Lf1c9RRR9UWtvXLmMz2+EPqx7D/MEfBqPdPmmv9PkcGeE3oJwxG+5zB2FiNj49PXVGS9DP9nDMY7S+dSZJmhWEgSTIMJEmGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkMQdhkOS4JP+QZE2SM2Z7/5KkLc1qGCRZAPwP4HjgcOD3kxw+m32QJG1pto8MjgbWVNWtVfUT4JPAilnugyRpMwtneX9LgTt7lu8CntVbIcnpwOlt8cdJbpylvo26fYDvz3UnRoRjsYljsYljscnTZrrBbIfBlKrqXOBcgCTjM/0/nr+oHItNHItNHItNHItNksz4n8fP9jTRWuCAnuVlrUySNIdmOwy+BRya5OAkOwOnAJfPch8kSZuZ1WmiqnosyZ8CVwALgI9W1U3b2OTc2enZDsGx2MSx2MSx2MSx2GTGY5Gq2h4dkSTtQPwGsiTJMJAkjXAYzOfLViT5aJINvd+xSLJ3kiuT3NJu95rLPs6WJAckuSbJzUluSvKqVj7vxiPJLkn+Lsnft7F4eys/OMl17bnyqfbhjF94SRYkuT7JF9vyvBwHgCS3JbkhyXcmPlY60+fISIaBl63g48Bxm5WdAVxVVYcCV7Xl+eAx4LVVdThwDPDK9rcwH8fjx8CLquoZwBHAcUmOAd4NnF1VhwD3A6fNYR9n06uA1T3L83UcJrywqo7o+a7FjJ4jIxkGzPPLVlTV14H7NiteAZzf7p8PnDSrnZojVbWuqr7d7j9M9+Rfyjwcj+o80hZ3aj8FvAi4tJXPi7FIsgx4CfCRthzm4ThMYUbPkVENg61dtmLpHPVlVOxbVeva/XuAfeeyM3MhyUHAM4HrmKfj0aZGvgNsAK4E/h/wQFU91qrMl+fK+4HXA0+05cXMz3GYUMBXk6xql/SBGT5HRu5yFJpaVVWSefWZ4CS7A58BXl1VD3VvBDvzaTyq6nHgiCSLgM8Bh81xl2ZdkpcCG6pqVZIXzHV/RsRzq2ptkl8Crkzyvd6V03mOjOqRgZet2NL6JPsBtNsNc9yfWZNkJ7oguKiqPtuK5+14AFTVA8A1wLOBRUkm3tjNh+fKc4DfTXIb3RTyi4BzmH/j8DNVtbbdbqB7k3A0M3yOjGoYeNmKLV0OrGz3VwKXzWFfZk2bCz4PWF1V7+tZNe/GI8mSdkRAkqcAv0N3DuUa4GWt2i/8WFTVG6tqWVUdRPfacHVVvZx5Ng4TkuyW5KkT94EXAzcyw+fIyH4DOckJdPOCE5etOGuOuzRrklwMvIDukrzrgbcCnwcuAQ4EbgdOrqrNTzL/wknyXOAbwA1smh9+E915g3k1Hkn+Od2JwAV0b+Quqap3JPkVunfIewPXA39YVT+eu57OnjZN9Lqqeul8HYf2uD/XFhcCn6iqs5IsZgbPkZENA0nS7BnVaSJJ0iwyDCRJhoEkyTCQJGEYSJIwDCRJGAaSJOD/Az15XOWF/4x9AAAAAElFTkSuQmCC\n",
+ "text/plain": [
+ "<matplotlib.figure.Figure at 0xaefaa6b0>"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..789b2768f6c87b947825adc38fc1c4d65a518fd3
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl
@@ -0,0 +1,122 @@
+# build_mcu_fpga_batch.tcl
+#
+# cmsdk_mcu sample design
+# A Vivado script that demonstrates a very simple RTL-to-bitstream non-project batch flow
+#
+# NOTE: typical usage would be "vivado -mode tcl -source build_mcu_fpga_batch.tcl"
+#
+# STEP#0: define output directory area.
+#
+
+##if {$argc < 1} {
+#puts "target_fpga arg must be \[ac701 \| arm_mps3 \| pynz_z2 \| zcu104\]"
+#}
+#set target [lindex $argv 0]
+#puts "target requested : $target"
+#set target_dir target_fpga
+#append target_dir $target
+#puts "target directory : $target_dir"
+
+set outputDir ./vivado/built_mcu_fpga
+file mkdir $outputDir
+#
+# STEP#1: setup design sources and constraints
+#
+
+# local search path for configurations
+set search_path ../verilog
+
+set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
+source scripts/rtl_source_cm0.tcl
+
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
+read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
+
+# Arm unmodified CMSDK RTL
+set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+source scripts/rtl_source_cmsdk.tcl
+
+set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
+###read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+###read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
+###read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
+
+# ADP, FT1248 and streamio IP
+source scripts/rtl_source_soclabs_ip.tcl
+
+# FPGA-specific pads
+source scripts/rtl_source_fpga_ip.tcl
+
+# soclabs modified mcu system
+set soc_vlog ../verilog
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
+read_verilog $soc_vlog/ahb_bootrom.v
+read_verilog $soc_vlog/bootrom.v
+read_verilog $soc_vlog/cmsdk_ahb_cs_rom_table.v
+read_verilog $soc_vlog/cmsdk_apb_usrt.v
+read_verilog $soc_vlog/cmsdk_clkreset.v
+read_verilog $soc_vlog/cmsdk_ft1248x1_adpio.v
+read_verilog $soc_vlog/cmsdk_mcu_clkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_pin_mux.v
+read_verilog $soc_vlog/cmsdk_mcu_stclkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v
+read_verilog $soc_vlog/cmsdk_uart_capture.v
+read_verilog $soc_vlog/nanosoc_ahb_sys_decode.v
+read_verilog $soc_vlog/nanosoc_chip_pads.v
+read_verilog $soc_vlog/nanosoc_chip.v
+read_verilog $soc_vlog/nanosoc_cpu.v
+read_verilog $soc_vlog/nanosoc_sys_ahb_decode.v
+read_verilog $soc_vlog/nanosoc_sysio.v
+
+
+# FPGA specific timing constraints
+read_xdc target_fpga/fpga_timing.xdc
+
+# FPGA board specific pin constraints
+read_xdc target_fpga/fpga_pinmap.xdc
+
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+source target_fpga/fpga_synth.tcl
+
+write_checkpoint -force $outputDir/post_synth
+report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
+report_power -file $outputDir/post_synth_power.rpt
+#
+# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
+#
+opt_design
+place_design
+phys_opt_design
+write_checkpoint -force $outputDir/post_place
+report_timing_summary -file $outputDir/post_place_timing_summary.rpt
+#
+# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
+#
+route_design
+write_checkpoint -force $outputDir/post_route
+report_timing_summary -file $outputDir/post_route_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
+report_clock_utilization -file $outputDir/clock_util.rpt
+report_utilization -file $outputDir/post_route_util.rpt
+report_power -file $outputDir/post_route_power.rpt
+report_drc -file $outputDir/post_imp_drc.rpt
+write_verilog -force $outputDir/cmsdk_mcu_impl_netlist.v
+write_xdc -no_fixed_only -force $outputDir/cmsdk_mcu_impl.xdc
+#
+# STEP#5: generate a bitstream
+#
+write_bitstream -force $outputDir/cmsdk_mcu.bit
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a1a6c43b84f099075b5f79214628984e8427a264
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -0,0 +1,127 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_ip.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright � 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#0: define output directory area.
+#
+
+set outputDir ./vivado/built_mcu_fpga
+file mkdir $outputDir
+#
+# STEP#1: setup design sources and constraints
+#
+
+# local search path for configurations
+set search_path ../verilog
+
+set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
+source scripts/rtl_source_cm0.tcl
+
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
+read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
+
+# Arm unmodified CMSDK RTL
+set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+source scripts/rtl_source_cmsdk.tcl
+
+set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
+
+# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
+set search_path [ concat $search_path ../verilog ]
+set dma230_vlog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+source scripts/rtl_source_dma230.tcl
+
+# ADP, FT1248 and streamio IP
+source scripts/rtl_source_soclabs_ip.tcl
+
+## FPGA-specific pads
+#source scripts/rtl_source_fpga_ip.tcl
+
+# soclabs modified mcu system
+set soc_vlog ../verilog
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
+read_verilog $soc_vlog/ahb_bootrom.v
+read_verilog $soc_vlog/bootrom.v
+read_verilog $soc_vlog/cmsdk_ahb_cs_rom_table.v
+read_verilog $soc_vlog/cmsdk_apb_usrt.v
+##read_verilog $soc_vlog/cmsdk_clkreset.v
+read_verilog $soc_vlog/cmsdk_ft1248x1_adpio.v
+read_verilog $soc_vlog/cmsdk_mcu_clkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_pin_mux.v
+read_verilog $soc_vlog/cmsdk_mcu_stclkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v
+##read_verilog $soc_vlog/cmsdk_uart_capture.v
+read_verilog $soc_vlog/nanosoc_cpu.v
+read_verilog $soc_vlog/nanosoc_sys_ahb_decode.v
+read_verilog $soc_vlog/nanosoc_sysio.v
+read_verilog $soc_vlog/nanosoc_chip.v
+read_verilog $soc_vlog/nanosoc_chip_pads.v
+
+set_property top nanosoc_chip [current_fileset]
+
+# FPGA specific timing constraints
+#read_xdc target_fpga/fpga_timing.xdc
+
+## FPGA board specific pin constraints
+#read_xdc target_fpga/fpga_pinmap.xdc
+
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+
+update_compile_order -fileset sources_1
+
+set mculib_ip $outputDir/MCULIB
+
+ipx::package_project -root_dir $mculib_ip -vendor soclabs.org -library user -taxonomy /UserIP -import_files -set_current false -force -force_update_compile_order
+
+ipx::unload_core $mculib_ip/component.xml
+ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $mculib_ip $mculib_ip/component.xml
+
+update_compile_order -fileset sources_1
+set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
+ipx::merge_project_changes files [ipx::current_core]
+
+set_property core_revision 2 [ipx::current_core]
+ipx::update_source_project_archive -component [ipx::current_core]
+ipx::create_xgui_files [ipx::current_core]
+ipx::update_checksums [ipx::current_core]
+ipx::check_integrity [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+ipx::check_integrity -quiet -xrt [ipx::current_core]
+ipx::archive_core $mculib_ip/soclabs.org_user_cmsdk_mcu_chip_1.0.zip [ipx::current_core]
+ipx::move_temp_component_back -component [ipx::current_core]
+close_project -delete
+
+set_property ip_repo_paths { ip_repo $mculib_ip} [current_project]
+update_ip_catalog
+close_project
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..28b5b35bc264f21990043a065a2b55d09c2ef43b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -0,0 +1,118 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_z2.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright � 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_pynq_z2.tcl
+# vivado -mode gui -source scripts/build_mcu_fpga_pynq_z2.tcl
+
+# for TUL PYNQ-Z2 as PYNQ target
+set xilinx_part xc7z020clg400-1
+set project project_pynq_z2
+set importDir target_fpga_pynq_z2
+set ipDir ./ip_repo
+set mcuDir ./vivado/built_mcu_fpga/MCULIB
+set pynqDir pynq_export/pz2/pynq/overlays/soclabs
+set exportDir /research/soclabs/pynq_export/pz2/pynq/overlays/soclabs
+#set_property BOARD_PART tul.com:pynq-z2:part0:1.1 [current_project]
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ $ipDir\
+ $mcuDir\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize $ipDir] [file normalize $mcuDir]" $obj
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $importDir/design_1_wrapper.v
+source $importDir/design_1.tcl
+create_root_design ""
+
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../verilog/pl230_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files ../verilog/pl230_defs.v]
+
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../verilog/pl230_defs.v]
+
+add_files $importDir/fpga_pinmap.xdc
+
+set_property top design_1_wrapper [current_fileset]
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+
+exec mkdir -p $pynqDir
+exec cp -p $project/export/design_1.bit $pynqDir
+exec cp -p $project/export/design_1.hwh $pynqDir
+#exec cp -p $project/export/design_1.bit $exportDir
+#exec cp -p $project/export/design_1.hwh $exportDir
+
+exec rm -Rf vivado/
+
+exit 1
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..87ae9c21ccbc94e23c06ccd881d73e19637f74ff
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -0,0 +1,115 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_zcu104.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright � 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_pynq_zcu104.tcl
+# vivado -mode gui -source scripts/build_mcu_fpga_pynq_zcu104.tcl
+
+# for Xilinx ZCU104 as PYNQ target
+set xilinx_part xczu7ev-ffvc1156-2-e
+set project project_pynq_zcu104
+set importDir target_fpga_zcu104
+set ipDir ./ip_repo
+set mcuDir ./vivado/built_mcu_fpga/MCULIB
+set pynqDir pynq_export/pz104/pynq/overlays/soclabs
+#set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ $ipDir\
+ $mcuDir\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize $ipDir] [file normalize $mcuDir]" $obj
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $importDir/design_1_wrapper.v
+source $importDir/design_1.tcl
+create_root_design ""
+
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../verilog/pl230_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files ../verilog/pl230_defs.v]
+
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../verilog/pl230_defs.v]
+
+add_files $importDir/fpga_pinmap.xdc
+
+set_property top design_1_wrapper [current_fileset]
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+exec mkdir -p $pynqDir
+exec cp -p $project/export/design_1.bit $pynqDir
+exec cp -p $project/export/design_1.hwh $pynqDir
+
+exec rm -Rf vivado/
+
+exit 1
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_cm0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_cm0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b76287f3995fc4ff1584a546bf0c82dc5d4c3217
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_cm0.tcl
@@ -0,0 +1,17 @@
+### Cortex-M0 rtl source build
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0/verilog/*.v ]
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_dap/verilog ]
+##read_verilog [ glob $cortexm0_vlog/cortexm0_dap/verilog/*.v ]
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_cdc.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_cdc.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_pwr.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/CORTEXM0DAP.v
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cd99c878a8278d9fa6b59166f4f0b2cc0e54d461
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl
@@ -0,0 +1,17 @@
+### CMSDK rtl source build
+###read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/*.v ]
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
+read_verilog $cmsdk_vlog/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_timer/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_dualtimers/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_watchdog/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_uart/verilog/*.v ]
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_slave_mux/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_to_apb/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_slave_mux/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_subsystem/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_master_mux/verilog/*.v ]
+read_verilog $cmsdk_vlog/logical/models/clkgate/cmsdk_clock_gate.v
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..356404ee9e0d2ee8a3e21d54b13fae19b9421c6d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl
@@ -0,0 +1,8 @@
+### DMA PL230 rtl source build
+read_verilog ../verilog/pl230_defs.v
+read_verilog $dma230_vlog/pl230_ahb_ctrl.v
+read_verilog $dma230_vlog/pl230_apb_regs.v
+read_verilog $dma230_vlog/pl230_dma_data.v
+read_verilog $dma230_vlog/pl230_udma.v
+read_verilog $dma230_vlog/pl230_undefs.v
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..376d757658bf7dc98669ac9c626075f3126f64c0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl
@@ -0,0 +1,9 @@
+# rtl_source_fpga_ip.tcl
+#
+
+set fpgalib_vlog ../../../../../FPGALIB
+read_verilog $fpgalib_vlog/pads/verilog/PAD_INOUT8MA_NOE.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VDDIO.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VSSIO.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VDDSOC.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VSS.v
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a661717b3f1593e6f4733a14831e72d568ffea3c
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl
@@ -0,0 +1,7 @@
+# rtl_source_soclabs_ip.tcl
+#
+
+set iplib_vlog ../../../../../IPLIB
+read_verilog $iplib_vlog/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
+read_verilog $iplib_vlog/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+read_verilog $iplib_vlog/ADPcontrol_v1_0/ADPmanager.v
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_pinmap.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..b8889af48409d7409031d5229f5949e72f9dc5ef
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_pinmap.xdc
@@ -0,0 +1,983 @@
+##################################################################################
+## ##
+## AC701 Master XDC ##
+## ##
+##################################################################################
+
+set_property CFGBVS VCCO [current_design]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+##set_property PACKAGE_PIN AB22 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN AE25 [get_ports FMC1_HPC_HA02_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA02_P]
+##set_property PACKAGE_PIN AE26 [get_ports FMC1_HPC_HA02_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA02_N]
+##set_property PACKAGE_PIN AC22 [get_ports FMC1_HPC_HA03_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA03_P]
+##set_property PACKAGE_PIN AC23 [get_ports FMC1_HPC_HA03_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA03_N]
+##set_property PACKAGE_PIN AF24 [get_ports FMC1_HPC_HA04_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA04_P]
+##set_property PACKAGE_PIN AF25 [get_ports FMC1_HPC_HA04_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA04_N]
+##set_property PACKAGE_PIN AD25 [get_ports FMC1_HPC_HA05_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA05_P]
+##set_property PACKAGE_PIN AD26 [get_ports FMC1_HPC_HA05_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA05_N]
+##set_property PACKAGE_PIN AE23 [get_ports FMC1_HPC_HA06_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA06_P]
+##set_property PACKAGE_PIN AF23 [get_ports FMC1_HPC_HA06_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA06_N]
+##set_property PACKAGE_PIN AD23 [get_ports FMC1_HPC_HA07_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA07_P]
+##set_property PACKAGE_PIN AD24 [get_ports FMC1_HPC_HA07_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA07_N]
+##set_property PACKAGE_PIN AD21 [get_ports FMC1_HPC_HA08_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA08_P]
+##set_property PACKAGE_PIN AE21 [get_ports FMC1_HPC_HA08_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA08_N]
+##set_property PACKAGE_PIN AF19 [get_ports FMC1_HPC_HA09_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA09_P]
+##set_property PACKAGE_PIN AF20 [get_ports FMC1_HPC_HA09_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA09_N]
+##set_property PACKAGE_PIN AE22 [get_ports FMC1_HPC_HA10_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_P]
+##set_property PACKAGE_PIN AF22 [get_ports FMC1_HPC_HA10_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_N]
+##set_property PACKAGE_PIN AD20 [get_ports FMC1_HPC_HA11_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_P]
+##set_property PACKAGE_PIN AE20 [get_ports FMC1_HPC_HA11_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_N]
+##set_property PACKAGE_PIN AB21 [get_ports FMC1_HPC_HA01_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA01_CC_P]
+##set_property PACKAGE_PIN AC21 [get_ports FMC1_HPC_HA01_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA01_CC_N]
+##set_property PACKAGE_PIN AA20 [get_ports FMC1_HPC_HA17_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA17_CC_P]
+##set_property PACKAGE_PIN AB20 [get_ports FMC1_HPC_HA17_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA17_CC_N]
+##set_property PACKAGE_PIN AA19 [get_ports FMC1_HPC_HA00_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA00_CC_P]
+##set_property PACKAGE_PIN AB19 [get_ports FMC1_HPC_HA00_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA00_CC_N]
+##set_property PACKAGE_PIN AC19 [get_ports FMC1_HPC_HA12_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_P]
+##set_property PACKAGE_PIN AD19 [get_ports FMC1_HPC_HA12_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_N]
+##set_property PACKAGE_PIN AC18 [get_ports FMC1_HPC_HA13_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_P]
+##set_property PACKAGE_PIN AD18 [get_ports FMC1_HPC_HA13_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_N]
+##set_property PACKAGE_PIN AE18 [get_ports FMC1_HPC_HA14_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA14_P]
+##set_property PACKAGE_PIN AF18 [get_ports FMC1_HPC_HA14_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA14_N]
+##set_property PACKAGE_PIN Y18 [get_ports FMC1_HPC_HA15_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA15_P]
+##set_property PACKAGE_PIN AA18 [get_ports FMC1_HPC_HA15_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA15_N]
+##set_property PACKAGE_PIN AE17 [get_ports FMC1_HPC_HA16_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA16_P]
+##set_property PACKAGE_PIN AF17 [get_ports FMC1_HPC_HA16_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA16_N]
+##set_property PACKAGE_PIN AA17 [get_ports FMC1_HPC_HA18_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA18_P]
+##set_property PACKAGE_PIN AB17 [get_ports FMC1_HPC_HA18_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA18_N]
+##set_property PACKAGE_PIN AC17 [get_ports FMC1_HPC_HA19_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA19_P]
+##set_property PACKAGE_PIN AD17 [get_ports FMC1_HPC_HA19_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA19_N]
+##set_property PACKAGE_PIN Y16 [get_ports FMC1_HPC_HA20_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA20_P]
+##set_property PACKAGE_PIN Y17 [get_ports FMC1_HPC_HA20_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA20_N]
+##set_property PACKAGE_PIN AB16 [get_ports FMC1_HPC_HA21_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA21_P]
+##set_property PACKAGE_PIN AC16 [get_ports FMC1_HPC_HA21_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA21_N]
+##set_property PACKAGE_PIN Y15 [get_ports FMC1_HPC_HA22_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_P]
+##set_property PACKAGE_PIN AA15 [get_ports FMC1_HPC_HA22_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_N]
+##set_property PACKAGE_PIN W14 [get_ports FMC1_HPC_HA23_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_P]
+##set_property PACKAGE_PIN W15 [get_ports FMC1_HPC_HA23_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_N]
+##set_property PACKAGE_PIN W16 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN U24 [get_ports HDMI_R_D21]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D21]
+##set_property PACKAGE_PIN U25 [get_ports HDMI_R_D16]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D16]
+##set_property PACKAGE_PIN U26 [get_ports HDMI_R_D11]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D11]
+##set_property PACKAGE_PIN V26 [get_ports HDMI_R_D7]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D7]
+##set_property PACKAGE_PIN W26 [get_ports HDMI_R_D8]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D8]
+##set_property PACKAGE_PIN AB26 [get_ports HDMI_R_DE]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_DE]
+##set_property PACKAGE_PIN AC26 [get_ports HDMI_R_VSYNC]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_VSYNC]
+##set_property PACKAGE_PIN W25 [get_ports HDMI_R_D9]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D9]
+##set_property PACKAGE_PIN Y26 [get_ports HDMI_R_D6]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D6]
+##set_property PACKAGE_PIN Y25 [get_ports HDMI_R_D5]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D5]
+##set_property PACKAGE_PIN AA25 [get_ports HDMI_R_D29]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D29]
+##set_property PACKAGE_PIN V24 [get_ports HDMI_R_D17]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D17]
+##set_property PACKAGE_PIN W24 [get_ports HDMI_R_D10]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D10]
+##set_property PACKAGE_PIN AA24 [get_ports HDMI_R_D4]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D4]
+##set_property PACKAGE_PIN AB25 [get_ports HDMI_R_D30]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D30]
+##set_property PACKAGE_PIN AA22 [get_ports HDMI_R_HSYNC]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_HSYNC]
+##set_property PACKAGE_PIN AA23 [get_ports HDMI_R_D28]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D28]
+##set_property PACKAGE_PIN AB24 [get_ports HDMI_R_D32]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D32]
+##set_property PACKAGE_PIN AC24 [get_ports HDMI_R_D31]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D31]
+##set_property PACKAGE_PIN V23 [get_ports HDMI_R_D23]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D23]
+##set_property PACKAGE_PIN W23 [get_ports HDMI_R_D19]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D19]
+##set_property PACKAGE_PIN Y22 [get_ports HDMI_R_D33]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D33]
+##set_property PACKAGE_PIN Y23 [get_ports HDMI_R_D34]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D34]
+##set_property INTERNAL_VREF 0.90 [get_iobanks 13]
+##set_property PACKAGE_PIN U22 [get_ports PHY_TX_CLK]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CLK]
+##set_property PACKAGE_PIN V22 [get_ports HDMI_R_D35]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D35]
+##set_property PACKAGE_PIN U21 [get_ports PHY_RX_CLK]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CLK]
+##set_property PACKAGE_PIN V21 [get_ports HDMI_R_CLK]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_CLK]
+##set_property PACKAGE_PIN W21 [get_ports HDMI_INT]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
+##set_property PACKAGE_PIN Y21 [get_ports HDMI_R_SPDIF]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_SPDIF]
+##set_property PACKAGE_PIN T20 [get_ports HDMI_SPDIF_OUT_LS]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_SPDIF_OUT_LS]
+##set_property PACKAGE_PIN U20 [get_ports HDMI_R_D18]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D18]
+##set_property PACKAGE_PIN W20 [get_ports HDMI_R_D20]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D20]
+##set_property PACKAGE_PIN Y20 [get_ports HDMI_R_D22]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D22]
+##set_property PACKAGE_PIN T19 [get_ports USB_UART_TX]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
+##set_property PACKAGE_PIN U19 [get_ports USB_UART_RX]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
+##set_property PACKAGE_PIN V19 [get_ports USB_UART_RTS]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
+##set_property PACKAGE_PIN W19 [get_ports USB_UART_CTS]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
+##set_property PACKAGE_PIN V18 [get_ports PHY_RESET_B]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_B]
+##set_property PACKAGE_PIN W18 [get_ports PHY_MDC]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC]
+##set_property PACKAGE_PIN T14 [get_ports PHY_MDIO]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO]
+##set_property PACKAGE_PIN T15 [get_ports PHY_TX_CTRL]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CTRL]
+##set_property PACKAGE_PIN T17 [get_ports PHY_TXD3]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD3]
+##set_property PACKAGE_PIN T18 [get_ports PHY_TXD2]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD2]
+##set_property PACKAGE_PIN U15 [get_ports PHY_TXD1]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD1]
+##set_property PACKAGE_PIN U16 [get_ports PHY_TXD0]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD0]
+##set_property PACKAGE_PIN U14 [get_ports PHY_RX_CTRL]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CTRL]
+##set_property PACKAGE_PIN V14 [get_ports PHY_RXD3]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD3]
+##set_property PACKAGE_PIN V16 [get_ports PHY_RXD2]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD2]
+##set_property PACKAGE_PIN V17 [get_ports PHY_RXD1]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD1]
+##set_property PACKAGE_PIN U17 [get_ports PHY_RXD0]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD0]
+##set_property PACKAGE_PIN M19 [get_ports SI5324_INT_ALM_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports SI5324_INT_ALM_B]
+##set_property PACKAGE_PIN R14 [get_ports FLASH_D0]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D0]
+##set_property PACKAGE_PIN R15 [get_ports FLASH_D1]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D1]
+##set_property PACKAGE_PIN P14 [get_ports FLASH_D2]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D2]
+##set_property PACKAGE_PIN N14 [get_ports FLASH_D3]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D3]
+##set_property PACKAGE_PIN P15 [get_ports CTRL2_PWRGOOD]
+##set_property IOSTANDARD LVCMOS33 [get_ports CTRL2_PWRGOOD]
+##set_property PACKAGE_PIN P16 [get_ports FPGA_EMCCLK]
+##set_property IOSTANDARD LVCMOS33 [get_ports FPGA_EMCCLK]
+##set_property PACKAGE_PIN N16 [get_ports FMC1_HPC_PRSNT_M2C_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC1_HPC_PRSNT_M2C_B]
+##set_property PACKAGE_PIN N17 [get_ports FMC1_HPC_PG_M2C]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC1_HPC_PG_M2C]
+##set_property PACKAGE_PIN R16 [get_ports FMC_VADJ_ON_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC_VADJ_ON_B]
+##set_property PACKAGE_PIN R17 [get_ports IIC_MUX_RESET_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_MUX_RESET_B]
+##set_property PACKAGE_PIN P18 [get_ports QSPI_IC_CS_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports QSPI_IC_CS_B]
+##set_property PACKAGE_PIN N18 [get_ports IIC_SCL_MAIN]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_SCL_MAIN]
+##set_property PACKAGE_PIN K25 [get_ports IIC_SDA_MAIN]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_SDA_MAIN]
+##set_property PACKAGE_PIN K26 [get_ports PCIE_WAKE_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports PCIE_WAKE_B]
+##set_property PACKAGE_PIN M20 [get_ports PCIE_PERST]
+##set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST]
+##set_property PACKAGE_PIN L20 [get_ports LCD_E_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_E_LS]
+##set_property PACKAGE_PIN L24 [get_ports LCD_RW_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_RW_LS]
+##set_property PACKAGE_PIN L25 [get_ports LCD_DB4_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB4_LS]
+##set_property PACKAGE_PIN M24 [get_ports LCD_DB5_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB5_LS]
+##set_property PACKAGE_PIN M25 [get_ports LCD_DB6_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB6_LS]
+##set_property PACKAGE_PIN L22 [get_ports LCD_DB7_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB7_LS]
+##set_property PACKAGE_PIN L23 [get_ports LCD_RS_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_RS_LS]
+##set_property PACKAGE_PIN M21 [get_ports USER_CLOCK_P]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
+##set_property PACKAGE_PIN M22 [get_ports USER_CLOCK_N]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
+##set_property PACKAGE_PIN N21 [get_ports ROTARY_PUSH]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_PUSH]
+##set_property PACKAGE_PIN N22 [get_ports ROTARY_INCA]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCA]
+##set_property PACKAGE_PIN P20 [get_ports ROTARY_INCB]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCB]
+##set_property PACKAGE_PIN P21 [get_ports SDIO_CD_DAT3]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CD_DAT3]
+##set_property PACKAGE_PIN N23 [get_ports SDIO_CMD]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CMD]
+##set_property PACKAGE_PIN N24 [get_ports SDIO_CLK]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CLK]
+##set_property PACKAGE_PIN P19 [get_ports SDIO_DAT0]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT0]
+##set_property PACKAGE_PIN N19 [get_ports SDIO_DAT1]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT1]
+##set_property PACKAGE_PIN P23 [get_ports SDIO_DAT2]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT2]
+##set_property PACKAGE_PIN P24 [get_ports SDIO_SDDET]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDDET]
+##set_property PACKAGE_PIN R20 [get_ports SDIO_SDWP]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDWP]
+##set_property PACKAGE_PIN R21 [get_ports PMBUS_CLK_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CLK_LS]
+##set_property PACKAGE_PIN R25 [get_ports PMBUS_DATA_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_DATA_LS]
+##set_property PACKAGE_PIN P25 [get_ports PMBUS_CTRL_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CTRL_LS]
+##set_property PACKAGE_PIN N26 [get_ports PMBUS_ALERT_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_ALERT_LS]
+##set_property PACKAGE_PIN M26 [get_ports GPIO_LED_0]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_0]
+##set_property PACKAGE_PIN T24 [get_ports GPIO_LED_1]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_1]
+##set_property PACKAGE_PIN T25 [get_ports GPIO_LED_2]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_2]
+##set_property PACKAGE_PIN R26 [get_ports GPIO_LED_3]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_3]
+##set_property PACKAGE_PIN P26 [get_ports PMOD_0]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_0]
+##set_property PACKAGE_PIN T22 [get_ports PMOD_1]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_1]
+##set_property PACKAGE_PIN R22 [get_ports PMOD_2]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_2]
+##set_property PACKAGE_PIN T23 [get_ports PMOD_3]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_3]
+##set_property PACKAGE_PIN R23 [get_ports SFP_LOS]
+##set_property IOSTANDARD LVCMOS33 [get_ports SFP_LOS]
+##set_property PACKAGE_PIN R18 [get_ports SFP_TX_DISABLE]
+##set_property IOSTANDARD LVCMOS33 [get_ports SFP_TX_DISABLE]
+##set_property PACKAGE_PIN K18 [get_ports XADC_GPIO_2]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]
+##set_property PACKAGE_PIN K15 [get_ports XADC_VAUX0_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_P]
+##set_property PACKAGE_PIN J16 [get_ports XADC_VAUX0_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_N]
+##set_property PACKAGE_PIN J14 [get_ports XADC_VAUX8_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_P]
+##set_property PACKAGE_PIN J15 [get_ports XADC_VAUX8_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_N]
+##set_property PACKAGE_PIN K16 [get_ports XADC_AD1_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_P]
+##set_property PACKAGE_PIN K17 [get_ports XADC_AD1_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_N]
+##set_property PACKAGE_PIN M14 [get_ports FMC1_HPC_LA19_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA19_P]
+##set_property PACKAGE_PIN L14 [get_ports FMC1_HPC_LA19_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA19_N]
+##set_property PACKAGE_PIN M15 [get_ports XADC_AD9_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_P]
+##set_property PACKAGE_PIN L15 [get_ports XADC_AD9_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_N]
+##set_property PACKAGE_PIN M16 [get_ports FMC1_HPC_LA20_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA20_P]
+##set_property PACKAGE_PIN M17 [get_ports FMC1_HPC_LA20_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA20_N]
+##set_property PACKAGE_PIN J19 [get_ports FMC1_HPC_LA21_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA21_P]
+##set_property PACKAGE_PIN H19 [get_ports FMC1_HPC_LA21_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA21_N]
+##set_property PACKAGE_PIN L17 [get_ports FMC1_HPC_LA22_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA22_P]
+##set_property PACKAGE_PIN L18 [get_ports FMC1_HPC_LA22_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA22_N]
+##set_property PACKAGE_PIN K20 [get_ports FMC1_HPC_LA23_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA23_P]
+##set_property PACKAGE_PIN J20 [get_ports FMC1_HPC_LA23_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA23_N]
+##set_property PACKAGE_PIN J18 [get_ports FMC1_HPC_LA24_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_P]
+##set_property PACKAGE_PIN H18 [get_ports FMC1_HPC_LA24_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_N]
+##set_property PACKAGE_PIN G20 [get_ports FMC1_HPC_LA18_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_P]
+##set_property PACKAGE_PIN G21 [get_ports FMC1_HPC_LA18_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_N]
+##set_property PACKAGE_PIN K21 [get_ports FMC1_HPC_LA17_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_P]
+##set_property PACKAGE_PIN J21 [get_ports FMC1_HPC_LA17_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_N]
+##set_property PACKAGE_PIN H21 [get_ports FMC1_HPC_CLK1_M2C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK1_M2C_P]
+##set_property PACKAGE_PIN H22 [get_ports FMC1_HPC_CLK1_M2C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK1_M2C_N]
+##set_property PACKAGE_PIN J23 [get_ports USER_SMA_CLOCK_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_P]
+##set_property PACKAGE_PIN H23 [get_ports USER_SMA_CLOCK_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_N]
+##set_property PACKAGE_PIN G22 [get_ports FMC1_HPC_LA25_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_P]
+##set_property PACKAGE_PIN F22 [get_ports FMC1_HPC_LA25_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_N]
+##set_property PACKAGE_PIN J24 [get_ports FMC1_HPC_LA26_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_P]
+##set_property PACKAGE_PIN H24 [get_ports FMC1_HPC_LA26_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_N]
+##set_property PACKAGE_PIN F23 [get_ports FMC1_HPC_LA27_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_P]
+##set_property PACKAGE_PIN E23 [get_ports FMC1_HPC_LA27_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_N]
+##set_property PACKAGE_PIN K22 [get_ports FMC1_HPC_LA28_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA28_P]
+##set_property PACKAGE_PIN K23 [get_ports FMC1_HPC_LA28_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA28_N]
+##set_property PACKAGE_PIN G24 [get_ports FMC1_HPC_LA29_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA29_P]
+##set_property PACKAGE_PIN F24 [get_ports FMC1_HPC_LA29_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA29_N]
+##set_property PACKAGE_PIN E25 [get_ports FMC1_HPC_LA30_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA30_P]
+##set_property PACKAGE_PIN D25 [get_ports FMC1_HPC_LA30_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA30_N]
+##set_property PACKAGE_PIN E26 [get_ports FMC1_HPC_LA31_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA31_P]
+##set_property PACKAGE_PIN D26 [get_ports FMC1_HPC_LA31_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA31_N]
+##set_property PACKAGE_PIN H26 [get_ports FMC1_HPC_LA32_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA32_P]
+##set_property PACKAGE_PIN G26 [get_ports FMC1_HPC_LA32_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA32_N]
+##set_property PACKAGE_PIN G25 [get_ports FMC1_HPC_LA33_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA33_P]
+##set_property PACKAGE_PIN F25 [get_ports FMC1_HPC_LA33_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA33_N]
+##set_property PACKAGE_PIN J25 [get_ports SM_FAN_TACH]
+##set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH]
+##set_property PACKAGE_PIN J26 [get_ports SM_FAN_PWM]
+##set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_PWM]
+##set_property PACKAGE_PIN L19 [get_ports XADC_GPIO_3]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]
+##set_property PACKAGE_PIN H17 [get_ports XADC_GPIO_0]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
+##set_property PACKAGE_PIN H14 [get_ports FMC1_HPC_LA02_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA02_P]
+##set_property PACKAGE_PIN H15 [get_ports FMC1_HPC_LA02_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA02_N]
+##set_property PACKAGE_PIN G17 [get_ports FMC1_HPC_LA03_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA03_P]
+##set_property PACKAGE_PIN F17 [get_ports FMC1_HPC_LA03_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA03_N]
+##set_property PACKAGE_PIN F18 [get_ports FMC1_HPC_LA04_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA04_P]
+##set_property PACKAGE_PIN F19 [get_ports FMC1_HPC_LA04_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA04_N]
+##set_property PACKAGE_PIN G15 [get_ports FMC1_HPC_LA05_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA05_P]
+##set_property PACKAGE_PIN F15 [get_ports FMC1_HPC_LA05_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA05_N]
+##set_property PACKAGE_PIN G19 [get_ports FMC1_HPC_LA06_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA06_P]
+##set_property PACKAGE_PIN F20 [get_ports FMC1_HPC_LA06_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA06_N]
+##set_property PACKAGE_PIN H16 [get_ports FMC1_HPC_LA07_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA07_P]
+##set_property PACKAGE_PIN G16 [get_ports FMC1_HPC_LA07_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA07_N]
+##set_property PACKAGE_PIN C17 [get_ports FMC1_HPC_LA08_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA08_P]
+##set_property PACKAGE_PIN B17 [get_ports FMC1_HPC_LA08_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA08_N]
+##set_property PACKAGE_PIN E16 [get_ports FMC1_HPC_LA09_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA09_P]
+##set_property PACKAGE_PIN D16 [get_ports FMC1_HPC_LA09_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA09_N]
+##set_property PACKAGE_PIN A17 [get_ports FMC1_HPC_LA10_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA10_P]
+##set_property PACKAGE_PIN A18 [get_ports FMC1_HPC_LA10_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA10_N]
+##set_property PACKAGE_PIN B19 [get_ports FMC1_HPC_LA11_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA11_P]
+##set_property PACKAGE_PIN A19 [get_ports FMC1_HPC_LA11_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA11_N]
+##set_property PACKAGE_PIN E17 [get_ports FMC1_HPC_LA01_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA01_CC_P]
+##set_property PACKAGE_PIN E18 [get_ports FMC1_HPC_LA01_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA01_CC_N]
+##set_property PACKAGE_PIN D18 [get_ports FMC1_HPC_LA00_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA00_CC_P]
+##set_property PACKAGE_PIN C18 [get_ports FMC1_HPC_LA00_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA00_CC_N]
+##set_property PACKAGE_PIN D19 [get_ports FMC1_HPC_CLK0_M2C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK0_M2C_P]
+##set_property PACKAGE_PIN C19 [get_ports FMC1_HPC_CLK0_M2C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK0_M2C_N]
+##set_property PACKAGE_PIN E20 [get_ports FMC1_HPC_LA12_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA12_P]
+##set_property PACKAGE_PIN D20 [get_ports FMC1_HPC_LA12_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA12_N]
+##set_property PACKAGE_PIN B20 [get_ports FMC1_HPC_LA13_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA13_P]
+##set_property PACKAGE_PIN A20 [get_ports FMC1_HPC_LA13_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA13_N]
+##set_property PACKAGE_PIN C21 [get_ports FMC1_HPC_LA14_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA14_P]
+##set_property PACKAGE_PIN B21 [get_ports FMC1_HPC_LA14_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA14_N]
+##set_property PACKAGE_PIN B22 [get_ports FMC1_HPC_LA15_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_P]
+##set_property PACKAGE_PIN A22 [get_ports FMC1_HPC_LA15_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_N]
+##set_property PACKAGE_PIN E21 [get_ports FMC1_HPC_LA16_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_P]
+##set_property PACKAGE_PIN D21 [get_ports FMC1_HPC_LA16_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_N]
+##set_property PACKAGE_PIN C22 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN C23 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN B25 [get_ports XADC_MUX_ADDR0_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR0_LS]
+##set_property PACKAGE_PIN A25 [get_ports XADC_MUX_ADDR1_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR1_LS]
+##set_property PACKAGE_PIN A23 [get_ports XADC_MUX_ADDR2_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR2_LS]
+##set_property PACKAGE_PIN A24 [get_ports PCIE_MGT_CLK_SEL0]
+##set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL0]
+##set_property PACKAGE_PIN C26 [get_ports PCIE_MGT_CLK_SEL1]
+##set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL1]
+##set_property PACKAGE_PIN B26 [get_ports SFP_MGT_CLK_SEL0]
+##set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL0]
+##set_property PACKAGE_PIN C24 [get_ports SFP_MGT_CLK_SEL1]
+##set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL1]
+##set_property PACKAGE_PIN B24 [get_ports SI5324_RST_LS_B]
+##set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_LS_B]
+##set_property PACKAGE_PIN D23 [get_ports REC_CLOCK_C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
+##set_property PACKAGE_PIN D24 [get_ports REC_CLOCK_C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
+##set_property PACKAGE_PIN E22 [get_ports XADC_GPIO_1]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
+##set_property PACKAGE_PIN V4 [get_ports No]
+##set_property IOSTANDARD LVCMOS15 [get_ports No]
+##set_property PACKAGE_PIN V1 [get_ports DDR3_D31]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
+##set_property PACKAGE_PIN W1 [get_ports DDR3_D30]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
+##set_property PACKAGE_PIN W5 [get_ports DDR3_D29]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
+##set_property PACKAGE_PIN W4 [get_ports DDR3_D28]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
+##set_property PACKAGE_PIN V3 [get_ports DDR3_DQS3_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P]
+##set_property PACKAGE_PIN V2 [get_ports DDR3_DQS3_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N]
+##set_property PACKAGE_PIN V6 [get_ports DDR3_D27]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
+##set_property PACKAGE_PIN W6 [get_ports DDR3_D26]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
+##set_property PACKAGE_PIN W3 [get_ports DDR3_D25]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
+##set_property PACKAGE_PIN Y3 [get_ports DDR3_D24]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
+##set_property PACKAGE_PIN U7 [get_ports DDR3_DM3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
+##set_property PACKAGE_PIN V7 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN AB1 [get_ports DDR3_D23]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
+##set_property PACKAGE_PIN AC1 [get_ports DDR3_D22]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
+##set_property PACKAGE_PIN Y2 [get_ports DDR3_D21]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
+##set_property PACKAGE_PIN Y1 [get_ports DDR3_D20]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
+##set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS2_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P]
+##set_property PACKAGE_PIN AE1 [get_ports DDR3_DQS2_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N]
+##set_property PACKAGE_PIN AE2 [get_ports DDR3_D19]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
+##set_property PACKAGE_PIN AF2 [get_ports DDR3_D18]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
+##set_property PACKAGE_PIN AB2 [get_ports DDR3_D17]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
+##set_property PACKAGE_PIN AC2 [get_ports DDR3_D16]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
+##set_property PACKAGE_PIN AA3 [get_ports DDR3_DM2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
+##set_property PACKAGE_PIN AA2 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN AA4 [get_ports DDR3_D15]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
+##set_property PACKAGE_PIN AB4 [get_ports DDR3_D14]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
+##set_property PACKAGE_PIN AC3 [get_ports DDR3_D13]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
+##set_property PACKAGE_PIN AD3 [get_ports DDR3_D12]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
+##set_property PACKAGE_PIN AD5 [get_ports DDR3_DQS1_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
+##set_property PACKAGE_PIN AE5 [get_ports DDR3_DQS1_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
+##set_property PACKAGE_PIN AE3 [get_ports DDR3_D11]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
+##set_property PACKAGE_PIN AF3 [get_ports DDR3_D10]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
+##set_property PACKAGE_PIN AF5 [get_ports DDR3_D9]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
+##set_property PACKAGE_PIN AF4 [get_ports DDR3_D8]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
+##set_property PACKAGE_PIN AC4 [get_ports DDR3_DM1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
+##set_property PACKAGE_PIN AD4 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN Y7 [get_ports DDR3_D7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
+##set_property PACKAGE_PIN AA7 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN Y6 [get_ports DDR3_D6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
+##set_property PACKAGE_PIN Y5 [get_ports DDR3_D5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
+##set_property PACKAGE_PIN V8 [get_ports DDR3_DQS0_P]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_P]
+##set_property PACKAGE_PIN W8 [get_ports DDR3_DQS0_N]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_N]
+##set_property PACKAGE_PIN AA5 [get_ports DDR3_D4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
+##set_property PACKAGE_PIN AB5 [get_ports DDR3_D3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
+##set_property PACKAGE_PIN Y8 [get_ports DDR3_D2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
+##set_property PACKAGE_PIN AA8 [get_ports DDR3_D1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
+##set_property PACKAGE_PIN AB6 [get_ports DDR3_D0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
+##set_property PACKAGE_PIN AC6 [get_ports DDR3_DM0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
+##set_property PACKAGE_PIN V9 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN N8 [get_ports DDR3_RESET_B]
+##set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
+##set_property PACKAGE_PIN K3 [get_ports DDR3_A9]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
+##set_property PACKAGE_PIN J3 [get_ports DDR3_A1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
+##set_property PACKAGE_PIN M7 [get_ports DDR3_A5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
+##set_property PACKAGE_PIN L7 [get_ports DDR3_A12]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
+##set_property PACKAGE_PIN M4 [get_ports DDR3_A0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
+##set_property PACKAGE_PIN L4 [get_ports DDR3_A3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
+##set_property PACKAGE_PIN L5 [get_ports DDR3_A11]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
+##set_property PACKAGE_PIN K5 [get_ports DDR3_A4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
+##set_property PACKAGE_PIN N7 [get_ports DDR3_A10]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
+##set_property PACKAGE_PIN N6 [get_ports DDR3_A13]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
+##set_property PACKAGE_PIN M6 [get_ports DDR3_A7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
+##set_property PACKAGE_PIN M5 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN K1 [get_ports DDR3_A6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
+##set_property PACKAGE_PIN J1 [get_ports DDR3_A2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
+##set_property PACKAGE_PIN L3 [get_ports DDR3_A14]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
+##set_property PACKAGE_PIN K2 [get_ports DDR3_A15]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
+##set_property PACKAGE_PIN N1 [get_ports DDR3_BA0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
+##set_property PACKAGE_PIN M1 [get_ports DDR3_BA1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
+##set_property PACKAGE_PIN H2 [get_ports DDR3_BA2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
+##set_property PACKAGE_PIN H1 [get_ports DDR3_A8]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
+##set_property PACKAGE_PIN M2 [get_ports DDR3_CLK0_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
+##set_property PACKAGE_PIN L2 [get_ports DDR3_CLK0_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
+##set_property PACKAGE_PIN N3 [get_ports DDR3_CLK1_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
+##set_property PACKAGE_PIN N2 [get_ports DDR3_CLK1_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
+##set_property PACKAGE_PIN R3 [get_ports SYSCLK_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]
+##set_property PACKAGE_PIN P3 [get_ports SYSCLK_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
+##set_property PACKAGE_PIN P4 [get_ports DDR3_CKE0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
+##set_property PACKAGE_PIN N4 [get_ports DDR3_CKE1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
+##set_property PACKAGE_PIN R1 [get_ports DDR3_WE_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
+##set_property PACKAGE_PIN P1 [get_ports DDR3_RAS_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
+##set_property PACKAGE_PIN T4 [get_ports DDR3_CAS_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
+##set_property PACKAGE_PIN T3 [get_ports DDR3_S0_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
+##set_property PACKAGE_PIN T2 [get_ports DDR3_S1_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
+##set_property PACKAGE_PIN R2 [get_ports DDR3_ODT0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
+##set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
+##set_property PACKAGE_PIN U1 [get_ports DDR3_TEMP_EVENT]
+##set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]
+##set_property PACKAGE_PIN P6 [get_ports GPIO_SW_N]
+##set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
+##set_property PACKAGE_PIN P5 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN T5 [get_ports GPIO_SW_S]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_S]
+##set_property PACKAGE_PIN R5 [get_ports GPIO_SW_W]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_W]
+##set_property PACKAGE_PIN U6 [get_ports GPIO_SW_C]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_C]
+##set_property PACKAGE_PIN U5 [get_ports GPIO_SW_E]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_E]
+##set_property PACKAGE_PIN R8 [get_ports GPIO_DIP_SW0]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW0]
+##set_property PACKAGE_PIN P8 [get_ports GPIO_DIP_SW1]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW1]
+##set_property PACKAGE_PIN R7 [get_ports GPIO_DIP_SW2]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW2]
+##set_property PACKAGE_PIN R6 [get_ports GPIO_DIP_SW3]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW3]
+##set_property PACKAGE_PIN T8 [get_ports USER_SMA_GPIO_P]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_P]
+##set_property PACKAGE_PIN T7 [get_ports USER_SMA_GPIO_N]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_N]
+##set_property PACKAGE_PIN U4 [get_ports CPU_RESET]
+##set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESET]
+##set_property PACKAGE_PIN J8 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN E6 [get_ports DDR3_D63]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
+##set_property PACKAGE_PIN D6 [get_ports DDR3_D62]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
+##set_property PACKAGE_PIN H8 [get_ports DDR3_D61]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
+##set_property PACKAGE_PIN G8 [get_ports DDR3_D60]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
+##set_property PACKAGE_PIN H7 [get_ports DDR3_DQS7_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
+##set_property PACKAGE_PIN G7 [get_ports DDR3_DQS7_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
+##set_property PACKAGE_PIN F8 [get_ports DDR3_D59]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
+##set_property PACKAGE_PIN F7 [get_ports DDR3_D58]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
+##set_property PACKAGE_PIN H6 [get_ports DDR3_D57]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
+##set_property PACKAGE_PIN G6 [get_ports DDR3_D56]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
+##set_property PACKAGE_PIN H9 [get_ports DDR3_DM7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
+##set_property PACKAGE_PIN G9 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN J6 [get_ports DDR3_D55]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
+##set_property PACKAGE_PIN J5 [get_ports DDR3_D54]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
+##set_property PACKAGE_PIN L8 [get_ports DDR3_D53]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
+##set_property PACKAGE_PIN K8 [get_ports DDR3_D52]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
+##set_property PACKAGE_PIN J4 [get_ports DDR3_DQS6_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
+##set_property PACKAGE_PIN H4 [get_ports DDR3_DQS6_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
+##set_property PACKAGE_PIN K7 [get_ports DDR3_D51]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
+##set_property PACKAGE_PIN K6 [get_ports DDR3_D50]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
+##set_property PACKAGE_PIN G4 [get_ports DDR3_D49]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
+##set_property PACKAGE_PIN F4 [get_ports DDR3_D48]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
+##set_property PACKAGE_PIN G5 [get_ports DDR3_DM6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
+##set_property PACKAGE_PIN F5 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN E5 [get_ports DDR3_D47]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
+##set_property PACKAGE_PIN D5 [get_ports DDR3_D46]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
+##set_property PACKAGE_PIN D4 [get_ports DDR3_D45]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
+##set_property PACKAGE_PIN C4 [get_ports DDR3_D44]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
+##set_property PACKAGE_PIN B5 [get_ports DDR3_DQS5_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
+##set_property PACKAGE_PIN A5 [get_ports DDR3_DQS5_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
+##set_property PACKAGE_PIN B4 [get_ports DDR3_D43]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
+##set_property PACKAGE_PIN A4 [get_ports DDR3_D42]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
+##set_property PACKAGE_PIN D3 [get_ports DDR3_D41]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
+##set_property PACKAGE_PIN C3 [get_ports DDR3_D40]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
+##set_property PACKAGE_PIN F3 [get_ports DDR3_DM5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
+##set_property PACKAGE_PIN E3 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN C2 [get_ports DDR3_D39]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
+##set_property PACKAGE_PIN B2 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN A3 [get_ports DDR3_D38]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
+##set_property PACKAGE_PIN A2 [get_ports DDR3_D37]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
+##set_property PACKAGE_PIN C1 [get_ports DDR3_DQS4_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
+##set_property PACKAGE_PIN B1 [get_ports DDR3_DQS4_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
+##set_property PACKAGE_PIN F2 [get_ports DDR3_D36]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
+##set_property PACKAGE_PIN E2 [get_ports DDR3_D35]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
+##set_property PACKAGE_PIN E1 [get_ports DDR3_D34]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
+##set_property PACKAGE_PIN D1 [get_ports DDR3_D33]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
+##set_property PACKAGE_PIN G2 [get_ports DDR3_D32]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
+##set_property PACKAGE_PIN G1 [get_ports DDR3_DM4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
+##set_property PACKAGE_PIN H3 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN AB13 [get_ports SFP_MGT_CLK0_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_N]
+##set_property PACKAGE_PIN AA13 [get_ports SFP_MGT_CLK0_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_P]
+##set_property PACKAGE_PIN AF15 [get_ports MGTRREF_213]
+##set_property IOSTANDARD LVDS_25 [get_ports MGTRREF_213]
+##set_property PACKAGE_PIN AA11 [get_ports SFP_MGT_CLK1_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_P]
+##set_property PACKAGE_PIN AB11 [get_ports SFP_MGT_CLK1_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_N]
+##set_property PACKAGE_PIN E11 [get_ports PCIE_CLK_QO_N]
+##set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_N]
+##set_property PACKAGE_PIN F11 [get_ports PCIE_CLK_QO_P]
+##set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_P]
+##set_property PACKAGE_PIN A15 [get_ports MGTRREF_216]
+##set_property IOSTANDARD LVDS_25 [get_ports MGTRREF_216]
+##set_property PACKAGE_PIN F13 [get_ports No]
+##set_property IOSTANDARD LVDS_25 [get_ports No]
+##set_property PACKAGE_PIN E13 [get_ports No]
+##set_property IOSTANDARD LVDS_25 [get_ports No]
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[15]} ]
+
+set_property PULLUP true [get_ports {P0[0]} ]
+set_property PULLUP true [get_ports {P0[1]} ]
+set_property PULLUP true [get_ports {P0[2]} ]
+set_property PULLUP true [get_ports {P0[3]} ]
+set_property PULLUP true [get_ports {P0[4]} ]
+set_property PULLUP true [get_ports {P0[5]} ]
+set_property PULLUP true [get_ports {P0[6]} ]
+set_property PULLUP true [get_ports {P0[7]} ]
+set_property PULLUP true [get_ports {P0[8]} ]
+set_property PULLUP true [get_ports {P0[9]} ]
+set_property PULLUP true [get_ports {P0[10]} ]
+set_property PULLUP true [get_ports {P0[11]} ]
+set_property PULLUP true [get_ports {P0[12]} ]
+set_property PULLUP true [get_ports {P0[13]} ]
+set_property PULLUP true [get_ports {P0[14]} ]
+set_property PULLUP true [get_ports {P0[15]} ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[15]} ]
+
+set_property PULLUP true [get_ports {P1[0]} ]
+set_property PULLUP true [get_ports {P1[1]} ]
+set_property PULLUP true [get_ports {P1[2]} ]
+set_property PULLUP true [get_ports {P1[3]} ]
+set_property PULLUP true [get_ports {P1[4]} ]
+set_property PULLUP true [get_ports {P1[5]} ]
+set_property PULLUP true [get_ports {P1[6]} ]
+set_property PULLUP true [get_ports {P1[7]} ]
+set_property PULLUP true [get_ports {P1[8]} ]
+set_property PULLUP true [get_ports {P1[9]} ]
+set_property PULLUP true [get_ports {P1[10]} ]
+set_property PULLUP true [get_ports {P1[11]} ]
+set_property PULLUP true [get_ports {P1[12]} ]
+set_property PULLUP true [get_ports {P1[13]} ]
+set_property PULLUP true [get_ports {P1[14]} ]
+set_property PULLUP true [get_ports {P1[15]} ]
+
+set_property PULLDOWN true [get_ports {SWDIOTMS} ]
+set_property PULLDOWN true [get_ports {SWCLKTCK} ]
+
+#PMODA pin0 to FTCLK
+set_property PACKAGE_PIN T22 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+set_property PACKAGE_PIN T23 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+set_property PACKAGE_PIN P26 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+set_property PACKAGE_PIN R22 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+##set_property PACKAGE_PIN G6 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+##set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+##set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+set_property PACKAGE_PIN M26 [get_ports {P0[0]}]
+# LED1 to P0[1]
+set_property PACKAGE_PIN T24 [get_ports {P0[1]}]
+# LED2 to P0[2]
+set_property PACKAGE_PIN T25 [get_ports {P0[2]}]
+# LED3 to P0[3]
+set_property PACKAGE_PIN R26 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+set_property PACKAGE_PIN R8 [get_ports NRST]
+
+# USR CLOCK P (need dvider)
+##set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN M21 [get_ports XTAL1]
+#set_property PACKAGE_PIN R17 [get_ports XTAL2]
+
+#Board ref clock - 200MHz (need dvider)
+#set_property PACKAGE_PIN R3 [get_ports XTAL1]
+#set_property PACKAGE_PIN P3 [get_ports XTAL2]
+#Board user clock - 200MHz (need dvider)
+set_property PACKAGE_PIN M21 [get_ports XTAL1]
+set_property PACKAGE_PIN M22 [get_ports XTAL2]
+
+
+## auto mapped - to remap
+set_property PACKAGE_PIN R20 [get_ports {P0[10]}]
+set_property PACKAGE_PIN P24 [get_ports {P0[11]}]
+set_property PACKAGE_PIN P23 [get_ports {P0[12]}]
+set_property PACKAGE_PIN N19 [get_ports {P0[13]}]
+set_property PACKAGE_PIN P19 [get_ports {P0[14]}]
+set_property PACKAGE_PIN N24 [get_ports {P0[15]}]
+set_property PACKAGE_PIN R18 [get_ports {P0[4]}]
+set_property PACKAGE_PIN R23 [get_ports {P0[5]}]
+set_property PACKAGE_PIN N26 [get_ports {P0[6]}]
+set_property PACKAGE_PIN P25 [get_ports {P0[7]}]
+set_property PACKAGE_PIN R25 [get_ports {P0[8]}]
+set_property PACKAGE_PIN R21 [get_ports {P0[9]}]
+set_property PACKAGE_PIN M25 [get_ports {P1[10]}]
+set_property PACKAGE_PIN M24 [get_ports {P1[11]}]
+set_property PACKAGE_PIN L25 [get_ports {P1[12]}]
+set_property PACKAGE_PIN L24 [get_ports {P1[13]}]
+set_property PACKAGE_PIN L20 [get_ports {P1[14]}]
+set_property PACKAGE_PIN M20 [get_ports {P1[15]}]
+set_property PACKAGE_PIN N23 [get_ports {P1[4]}]
+set_property PACKAGE_PIN P21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN P20 [get_ports {P1[6]}]
+set_property PACKAGE_PIN N22 [get_ports {P1[7]}]
+set_property PACKAGE_PIN N21 [get_ports {P1[8]}]
+set_property PACKAGE_PIN L23 [get_ports {P1[9]}]
+set_property PACKAGE_PIN L22 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN K26 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN K25 [get_ports VDD]
+set_property PACKAGE_PIN N18 [get_ports VDDIO]
+set_property PACKAGE_PIN P18 [get_ports VSS]
+set_property PACKAGE_PIN R17 [get_ports VSSIO]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a13e2b6e4b167fed62c60f4aa382e932b1b9593a
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl
@@ -0,0 +1,40 @@
+
+synth_design -top cmsdk_mcu_chip -part xc7a200tfbg676-2
+
+write_verilog -force $outputDir/cmsdk_mcu_synth_netlist.v
+
+# # Create interface ports
+#
+# disconnect_net -net XTAL1 -objects {uPAD_XTAL_I/XTAL1}
+# disconnect_net -net XTAL2 -objects {uPAD_XTAL_O/XTAL2}
+# #disconnect_net -net xtal_clk_in] [get_pins XTAL1 uPAD_XTAL1_PAD/IOBUF3V3/I]]
+
+# set sys_diff_clock [ create_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]
+# set_property -dict [ list \
+# CONFIG.FREQ_HZ {200000000} \
+# ] $sys_diff_clock
+
+# set reset [ create_bd_port -dir I -type rst reset ]
+# set_property -dict [ list \
+# CONFIG.POLARITY {ACTIVE_HIGH} \
+# ] $reset
+
+# # Create instance: clk_wiz_20M, and set properties
+# set clk_wiz_20M [ create_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_20M ]
+# set_property -dict [ list \
+# CONFIG.CLKOUT1_JITTER {155.788} \
+# CONFIG.CLKOUT1_PHASE_ERROR {94.329} \
+# CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \
+# CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \
+# CONFIG.MMCM_CLKFBOUT_MULT_F {4.250} \
+# CONFIG.MMCM_CLKOUT0_DIVIDE_F {42.500} \
+# CONFIG.RESET_BOARD_INTERFACE {reset} \
+# CONFIG.USE_BOARD_FLOW {false} \
+#] $clk_wiz_20M
+
+# # Create interface connections
+# connect_net -intf_net sys_diff_clock_1 [get_ports sys_diff_clock] [get_pins clk_wiz_20M/CLK_IN1_D]
+
+# # Create port connections
+# connect_net -net clk_wiz_0_clk_out1 [get_pins xtal_clk_in] [get_bd_pins clk_wiz_20M/clk_out1]
+# connect_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_20M/reset]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..cb4cef44a99ecc3e62b7c6d18c03ca623885f6a8
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]}]
+
+set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_pinmap.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5fbe61eb28f3d716824d54418909d555a4f29ad4
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_pinmap.xdc
@@ -0,0 +1,915 @@
+# -----------------------------------------------------------------------------
+# Purpose : Main timing constraints and pin list for MPS3
+# -----------------------------------------------------------------------------
+
+####################################################################################
+# Pin Assigment
+####################################################################################
+
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_* ETH_* USB_* CLCD_* USER_nLED* USER_SW* USER_nPB* HDMI_* CS_* SH_ADC* UART_*}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[23]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[22]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[21]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[20]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[18]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_DE]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_HS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_IDCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_VS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_WS]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CMD]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_DS]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_nRST]
+# not used
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[2]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[2]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_LRCK]
+set_property PACKAGE_PIN Y30 [get_ports AUD_LRCK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_MCLK]
+set_property PACKAGE_PIN AB29 [get_ports AUD_MCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_nRST]
+set_property PACKAGE_PIN AA27 [get_ports AUD_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCL]
+set_property PACKAGE_PIN AA28 [get_ports AUD_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCLK]
+set_property PACKAGE_PIN AB30 [get_ports AUD_SCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDA]
+set_property PACKAGE_PIN AA29 [get_ports AUD_SDA]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDIN]
+set_property PACKAGE_PIN AA30 [get_ports AUD_SDIN]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDOUT]
+set_property PACKAGE_PIN Y27 [get_ports AUD_SDOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nPOR]
+set_property PACKAGE_PIN AU22 [get_ports CB_nPOR]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nRST]
+set_property PACKAGE_PIN AV23 [get_ports CB_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_RUN]
+set_property PACKAGE_PIN AR25 [get_ports CB_RUN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_CLK]
+set_property PACKAGE_PIN AT20 [get_ports CFG_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAIN]
+set_property PACKAGE_PIN AT19 [get_ports CFG_DATAIN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAOUT]
+set_property PACKAGE_PIN AV18 [get_ports CFG_DATAOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_LOAD]
+set_property PACKAGE_PIN AW18 [get_ports CFG_LOAD]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_nRST]
+set_property PACKAGE_PIN AR20 [get_ports CFG_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AT18 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AJ16 [get_ports CLCD_BL]
+set_property PACKAGE_PIN AP15 [get_ports CLCD_CS]
+set_property PACKAGE_PIN AN17 [get_ports {CLCD_PD[10]}]
+set_property PACKAGE_PIN AP16 [get_ports {CLCD_PD[11]}]
+set_property PACKAGE_PIN AP18 [get_ports {CLCD_PD[12]}]
+set_property PACKAGE_PIN AR18 [get_ports {CLCD_PD[13]}]
+set_property PACKAGE_PIN AM16 [get_ports {CLCD_PD[14]}]
+set_property PACKAGE_PIN AN16 [get_ports {CLCD_PD[15]}]
+set_property PACKAGE_PIN AR17 [get_ports {CLCD_PD[16]}]
+set_property PACKAGE_PIN AR16 [get_ports {CLCD_PD[17]}]
+set_property PACKAGE_PIN AM15 [get_ports CLCD_RD]
+set_property PACKAGE_PIN AN14 [get_ports CLCD_RS]
+set_property PACKAGE_PIN AK18 [get_ports CLCD_RST]
+#set_property PACKAGE_PIN AN18 [get_ports CLCD_SDI]
+#set_property PACKAGE_PIN AH16 [get_ports CLCD_SDO]
+set_property PACKAGE_PIN AJ14 [get_ports CLCD_TINT]
+set_property PACKAGE_PIN AL17 [get_ports CLCD_TNC]
+set_property PACKAGE_PIN AL18 [get_ports CLCD_TSCL]
+set_property PACKAGE_PIN AJ15 [get_ports CLCD_TSDA]
+set_property PACKAGE_PIN AP14 [get_ports CLCD_WR_SCL]
+# not used
+# set_property PACKAGE_PIN N28 [get_ports {CLK_BIDIR_P[2]}]
+# set_property PACKAGE_PIN N29 [get_ports {CLK_BIDIR_N[2]}]
+# set_property PACKAGE_PIN E32 [get_ports {CLK_BIDIR_P[3]}]
+# set_property PACKAGE_PIN D33 [get_ports {CLK_BIDIR_N[3]}]
+# set_property PACKAGE_PIN G31 [get_ports {CLK_M2C_P[0]}]
+# set_property PACKAGE_PIN F32 [get_ports {CLK_M2C_N[0]}]
+# set_property PACKAGE_PIN E31 [get_ports {CLK_M2C_P[1]}]
+# set_property PACKAGE_PIN D31 [get_ports {CLK_M2C_N[1]}]
+set_property PACKAGE_PIN BB39 [get_ports CS_nDET]
+set_property PACKAGE_PIN BB36 [get_ports CS_nSRST]
+set_property PACKAGE_PIN BB37 [get_ports CS_nTRST]
+set_property PACKAGE_PIN AW33 [get_ports CS_T_CLK]
+set_property PACKAGE_PIN AY35 [get_ports CS_T_CTL]
+set_property PACKAGE_PIN AW34 [get_ports {CS_T_D[0]}]
+set_property PACKAGE_PIN AT34 [get_ports {CS_T_D[1]}]
+set_property PACKAGE_PIN AU34 [get_ports {CS_T_D[2]}]
+set_property PACKAGE_PIN AV36 [get_ports {CS_T_D[3]}]
+set_property PACKAGE_PIN AW36 [get_ports {CS_T_D[4]}]
+set_property PACKAGE_PIN AT35 [get_ports {CS_T_D[5]}]
+set_property PACKAGE_PIN AU35 [get_ports {CS_T_D[6]}]
+set_property PACKAGE_PIN AU36 [get_ports {CS_T_D[7]}]
+set_property PACKAGE_PIN AV37 [get_ports {CS_T_D[8]}]
+set_property PACKAGE_PIN AW35 [get_ports {CS_T_D[9]}]
+set_property PACKAGE_PIN AY36 [get_ports {CS_T_D[10]}]
+set_property PACKAGE_PIN AY37 [get_ports {CS_T_D[11]}]
+set_property PACKAGE_PIN BB34 [get_ports {CS_T_D[12]}]
+set_property PACKAGE_PIN BB35 [get_ports {CS_T_D[13]}]
+set_property PACKAGE_PIN BA37 [get_ports {CS_T_D[14]}]
+set_property PACKAGE_PIN BA38 [get_ports {CS_T_D[15]}]
+set_property PACKAGE_PIN AV33 [get_ports CS_TCK]
+set_property PACKAGE_PIN BA35 [get_ports CS_TDI]
+set_property PACKAGE_PIN AW38 [get_ports CS_TDO]
+set_property PACKAGE_PIN AY38 [get_ports CS_TMS]
+# not used
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[0]}]
+#set_property PACKAGE_PIN J19 [get_ports {DDR_CHIPID[0]}]
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[1]}]
+#set_property PACKAGE_PIN G20 [get_ports {DDR_CHIPID[1]}]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nALERT]
+#set_property PACKAGE_PIN P15 [get_ports DDR_nALERT]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nEVENT]
+#set_property PACKAGE_PIN C17 [get_ports DDR_nEVENT]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_PARITY]
+# set_property PACKAGE_PIN D18 [get_ports DDR_PARITY]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SCL]
+# set_property PACKAGE_PIN N21 [get_ports DDR_SCL]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SDA]
+# set_property PACKAGE_PIN P21 [get_ports DDR_SDA]
+# set_property PACKAGE_PIN AC42 [get_ports {DP_M2C_N[0]}]
+# set_property PACKAGE_PIN AJ42 [get_ports {DP_M2C_N[1]}]
+# set_property PACKAGE_PIN AE42 [get_ports {DP_M2C_N[2]}]
+# set_property PACKAGE_PIN W42 [get_ports {DP_M2C_N[3]}]
+# set_property PACKAGE_PIN R42 [get_ports {DP_M2C_N[4]}]
+# set_property PACKAGE_PIN L42 [get_ports {DP_M2C_N[5]}]
+# set_property PACKAGE_PIN N42 [get_ports {DP_M2C_N[6]}]
+# set_property PACKAGE_PIN U42 [get_ports {DP_M2C_N[7]}]
+# set_property PACKAGE_PIN AA42 [get_ports {DP_M2C_N[8]}]
+# set_property PACKAGE_PIN AG42 [get_ports {DP_M2C_N[9]}]
+# set_property PACKAGE_PIN AC41 [get_ports {DP_M2C_P[0]}]
+# set_property PACKAGE_PIN AJ41 [get_ports {DP_M2C_P[1]}]
+# set_property PACKAGE_PIN AE41 [get_ports {DP_M2C_P[2]}]
+# set_property PACKAGE_PIN W41 [get_ports {DP_M2C_P[3]}]
+# set_property PACKAGE_PIN R41 [get_ports {DP_M2C_P[4]}]
+# set_property PACKAGE_PIN L41 [get_ports {DP_M2C_P[5]}]
+# set_property PACKAGE_PIN N41 [get_ports {DP_M2C_P[6]}]
+# set_property PACKAGE_PIN U41 [get_ports {DP_M2C_P[7]}]
+# set_property PACKAGE_PIN AA41 [get_ports {DP_M2C_P[8]}]
+# set_property PACKAGE_PIN AG41 [get_ports {DP_M2C_P[9]}]
+set_property PACKAGE_PIN AG34 [get_ports HDMI_CSCL]
+set_property PACKAGE_PIN AE33 [get_ports HDMI_CSDA]
+set_property PACKAGE_PIN AF33 [get_ports HDMI_INT]
+set_property PACKAGE_PIN W29 [get_ports EMMC_CLK]
+set_property PACKAGE_PIN AC34 [get_ports EMMC_CMD]
+set_property PACKAGE_PIN Y32 [get_ports {EMMC_DAT[0]}]
+set_property PACKAGE_PIN Y33 [get_ports {EMMC_DAT[1]}]
+set_property PACKAGE_PIN W33 [get_ports {EMMC_DAT[2]}]
+set_property PACKAGE_PIN W34 [get_ports {EMMC_DAT[3]}]
+set_property PACKAGE_PIN AA34 [get_ports {EMMC_DAT[4]}]
+set_property PACKAGE_PIN AB34 [get_ports {EMMC_DAT[5]}]
+set_property PACKAGE_PIN W31 [get_ports {EMMC_DAT[6]}]
+set_property PACKAGE_PIN Y31 [get_ports {EMMC_DAT[7]}]
+set_property PACKAGE_PIN AE32 [get_ports EMMC_DS]
+set_property PACKAGE_PIN W30 [get_ports EMMC_nRST]
+set_property PACKAGE_PIN AK23 [get_ports ETH_INT]
+set_property PACKAGE_PIN AL24 [get_ports ETH_nCS]
+set_property PACKAGE_PIN AJ23 [get_ports ETH_nOE]
+# not used
+# set_property PACKAGE_PIN AV38 [get_ports FMC_CLK_DIR]
+# set_property PACKAGE_PIN AL42 [get_ports FMC_nPRSNT]
+# set_property PACKAGE_PIN BB40 [get_ports {HA_N[2]}]
+# set_property PACKAGE_PIN BA41 [get_ports {HA_N[3]}]
+# set_property PACKAGE_PIN AY40 [get_ports {HA_N[4]}]
+# set_property PACKAGE_PIN AU42 [get_ports {HA_N[5]}]
+# set_property PACKAGE_PIN AY42 [get_ports {HA_N[6]}]
+# set_property PACKAGE_PIN AW41 [get_ports {HA_N[7]}]
+# set_property PACKAGE_PIN AU37 [get_ports {HA_N[8]}]
+# set_property PACKAGE_PIN AT42 [get_ports {HA_N[9]}]
+# set_property PACKAGE_PIN AT38 [get_ports {HA_N[10]}]
+# set_property PACKAGE_PIN AV42 [get_ports {HA_N[11]}]
+# set_property PACKAGE_PIN AR37 [get_ports {HA_N[12]}]
+# set_property PACKAGE_PIN AN42 [get_ports {HA_N[13]}]
+# set_property PACKAGE_PIN AP38 [get_ports {HA_N[14]}]
+# set_property PACKAGE_PIN AN37 [get_ports {HA_N[15]}]
+# set_property PACKAGE_PIN AM42 [get_ports {HA_N[16]}]
+# set_property PACKAGE_PIN AR41 [get_ports {HA_N[18]}]
+# set_property PACKAGE_PIN AM39 [get_ports {HA_N[19]}]
+# set_property PACKAGE_PIN AR40 [get_ports {HA_N[20]}]
+# set_property PACKAGE_PIN AM40 [get_ports {HA_N[21]}]
+# set_property PACKAGE_PIN AK38 [get_ports {HA_N[22]}]
+# set_property PACKAGE_PIN AL38 [get_ports {HA_N[23]}]
+# set_property PACKAGE_PIN AT39 [get_ports {HA_P[0]}]
+# set_property PACKAGE_PIN AT40 [get_ports {HA_N[0]}]
+# set_property PACKAGE_PIN AU39 [get_ports {HA_P[1]}]
+# set_property PACKAGE_PIN AU40 [get_ports {HA_N[1]}]
+# set_property PACKAGE_PIN BA39 [get_ports {HA_P[2]}]
+# set_property PACKAGE_PIN BA40 [get_ports {HA_P[3]}]
+# set_property PACKAGE_PIN AW39 [get_ports {HA_P[4]}]
+# set_property PACKAGE_PIN AU41 [get_ports {HA_P[5]}]
+# set_property PACKAGE_PIN AY41 [get_ports {HA_P[6]}]
+# set_property PACKAGE_PIN AW40 [get_ports {HA_P[7]}]
+# set_property PACKAGE_PIN AT37 [get_ports {HA_P[8]}]
+# set_property PACKAGE_PIN AR42 [get_ports {HA_P[9]}]
+# set_property PACKAGE_PIN AR38 [get_ports {HA_P[10]}]
+# set_property PACKAGE_PIN AV41 [get_ports {HA_P[11]}]
+# set_property PACKAGE_PIN AR36 [get_ports {HA_P[12]}]
+# set_property PACKAGE_PIN AN41 [get_ports {HA_P[13]}]
+# set_property PACKAGE_PIN AN38 [get_ports {HA_P[14]}]
+# set_property PACKAGE_PIN AM37 [get_ports {HA_P[15]}]
+# set_property PACKAGE_PIN AM41 [get_ports {HA_P[16]}]
+# set_property PACKAGE_PIN AN39 [get_ports {HA_P[17]}]
+# set_property PACKAGE_PIN AP39 [get_ports {HA_N[17]}]
+# set_property PACKAGE_PIN AP41 [get_ports {HA_P[18]}]
+# set_property PACKAGE_PIN AL39 [get_ports {HA_P[19]}]
+# set_property PACKAGE_PIN AP40 [get_ports {HA_P[20]}]
+# set_property PACKAGE_PIN AL40 [get_ports {HA_P[21]}]
+# set_property PACKAGE_PIN AK37 [get_ports {HA_P[22]}]
+# set_property PACKAGE_PIN AL37 [get_ports {HA_P[23]}]
+# set_property PACKAGE_PIN T32 [get_ports {HB_N[1]}]
+# set_property PACKAGE_PIN V33 [get_ports {HB_N[2]}]
+# set_property PACKAGE_PIN V29 [get_ports {HB_N[3]}]
+# set_property PACKAGE_PIN T30 [get_ports {HB_N[4]}]
+# set_property PACKAGE_PIN T34 [get_ports {HB_N[5]}]
+# set_property PACKAGE_PIN R32 [get_ports {HB_N[7]}]
+# set_property PACKAGE_PIN P29 [get_ports {HB_N[8]}]
+# set_property PACKAGE_PIN P30 [get_ports {HB_N[9]}]
+# set_property PACKAGE_PIN K28 [get_ports {HB_N[10]}]
+# set_property PACKAGE_PIN L29 [get_ports {HB_N[11]}]
+# set_property PACKAGE_PIN K31 [get_ports {HB_N[12]}]
+# set_property PACKAGE_PIN L33 [get_ports {HB_N[13]}]
+# set_property PACKAGE_PIN U31 [get_ports {HB_N[14]}]
+# set_property PACKAGE_PIN N33 [get_ports {HB_N[15]}]
+# set_property PACKAGE_PIN L34 [get_ports {HB_N[16]}]
+# set_property PACKAGE_PIN R28 [get_ports {HB_N[18]}]
+# set_property PACKAGE_PIN N27 [get_ports {HB_N[19]}]
+# set_property PACKAGE_PIN U34 [get_ports {HB_N[20]}]
+# set_property PACKAGE_PIN N34 [get_ports {HB_N[21]}]
+# set_property PACKAGE_PIN N31 [get_ports {HB_P[0]}]
+# set_property PACKAGE_PIN M31 [get_ports {HB_N[0]}]
+# set_property PACKAGE_PIN U32 [get_ports {HB_P[1]}]
+# set_property PACKAGE_PIN V32 [get_ports {HB_P[2]}]
+# set_property PACKAGE_PIN V28 [get_ports {HB_P[3]}]
+# set_property PACKAGE_PIN U30 [get_ports {HB_P[4]}]
+# set_property PACKAGE_PIN T33 [get_ports {HB_P[5]}]
+# set_property PACKAGE_PIN M30 [get_ports {HB_P[6]}]
+# set_property PACKAGE_PIN L30 [get_ports {HB_N[6]}]
+# set_property PACKAGE_PIN R31 [get_ports {HB_P[7]}]
+# set_property PACKAGE_PIN P28 [get_ports {HB_P[8]}]
+# set_property PACKAGE_PIN R30 [get_ports {HB_P[9]}]
+# set_property PACKAGE_PIN L28 [get_ports {HB_P[10]}]
+# set_property PACKAGE_PIN M29 [get_ports {HB_P[11]}]
+# set_property PACKAGE_PIN K30 [get_ports {HB_P[12]}]
+# set_property PACKAGE_PIN L32 [get_ports {HB_P[13]}]
+# set_property PACKAGE_PIN V31 [get_ports {HB_P[14]}]
+# set_property PACKAGE_PIN P33 [get_ports {HB_P[15]}]
+# set_property PACKAGE_PIN M34 [get_ports {HB_P[16]}]
+# set_property PACKAGE_PIN N32 [get_ports {HB_P[17]}]
+# set_property PACKAGE_PIN M32 [get_ports {HB_N[17]}]
+# set_property PACKAGE_PIN T28 [get_ports {HB_P[18]}]
+# set_property PACKAGE_PIN N26 [get_ports {HB_P[19]}]
+# set_property PACKAGE_PIN V34 [get_ports {HB_P[20]}]
+# set_property PACKAGE_PIN P34 [get_ports {HB_P[21]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {CLK_CFG}]
+# set_property PACKAGE_PIN AT27 [get_ports {CLK_CFG}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_CSIB}]
+# set_property PACKAGE_PIN BA27 [get_ports {IOFPGA_CSIB}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[4]}]
+# set_property PACKAGE_PIN AV26 [get_ports {IOFPGA_D[4]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[5]}]
+# set_property PACKAGE_PIN AV27 [get_ports {IOFPGA_D[5]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[6]}]
+# set_property PACKAGE_PIN AU29 [get_ports {IOFPGA_D[6]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[7]}]
+# set_property PACKAGE_PIN AV29 [get_ports {IOFPGA_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NRST]
+set_property PACKAGE_PIN AV31 [get_ports IOFPGA_NRST]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NSPIR]
+set_property PACKAGE_PIN AV32 [get_ports IOFPGA_NSPIR]
+set_property IOSTANDARD LVCMOS33 [get_ports IOFPGA_SYSWDT]
+set_property PACKAGE_PIN AU20 [get_ports IOFPGA_SYSWDT]
+# not used
+# set_property PACKAGE_PIN AN27 [get_ports {LA_N[2]}]
+# set_property PACKAGE_PIN AP30 [get_ports {LA_N[3]}]
+# set_property PACKAGE_PIN AN29 [get_ports {LA_N[4]}]
+# set_property PACKAGE_PIN AR35 [get_ports {LA_N[5]}]
+# set_property PACKAGE_PIN AR33 [get_ports {LA_N[6]}]
+# set_property PACKAGE_PIN AN32 [get_ports {LA_N[7]}]
+# set_property PACKAGE_PIN AP31 [get_ports {LA_N[8]}]
+# set_property PACKAGE_PIN AN34 [get_ports {LA_N[9]}]
+# set_property PACKAGE_PIN AL35 [get_ports {LA_N[10]}]
+# set_property PACKAGE_PIN AM36 [get_ports {LA_N[11]}]
+# set_property PACKAGE_PIN AP34 [get_ports {LA_N[12]}]
+# set_property PACKAGE_PIN AL32 [get_ports {LA_N[13]}]
+# set_property PACKAGE_PIN AK36 [get_ports {LA_N[14]}]
+# set_property PACKAGE_PIN AJ34 [get_ports {LA_N[15]}]
+# set_property PACKAGE_PIN AL33 [get_ports {LA_N[16]}]
+# set_property PACKAGE_PIN AJ29 [get_ports {LA_N[19]}]
+# set_property PACKAGE_PIN AJ33 [get_ports {LA_N[20]}]
+# set_property PACKAGE_PIN AH29 [get_ports {LA_N[21]}]
+# set_property PACKAGE_PIN AH31 [get_ports {LA_N[22]}]
+# set_property PACKAGE_PIN AG30 [get_ports {LA_N[23]}]
+# set_property PACKAGE_PIN G32 [get_ports {LA_N[24]}]
+# set_property PACKAGE_PIN H34 [get_ports {LA_N[25]}]
+# set_property PACKAGE_PIN H31 [get_ports {LA_N[26]}]
+# set_property PACKAGE_PIN K33 [get_ports {LA_N[27]}]
+# set_property PACKAGE_PIN H29 [get_ports {LA_N[28]}]
+# set_property PACKAGE_PIN H33 [get_ports {LA_N[29]}]
+# set_property PACKAGE_PIN F34 [get_ports {LA_N[30]}]
+# set_property PACKAGE_PIN E33 [get_ports {LA_N[31]}]
+# set_property PACKAGE_PIN C34 [get_ports {LA_N[32]}]
+# set_property PACKAGE_PIN G30 [get_ports {LA_N[33]}]
+# set_property PACKAGE_PIN AM29 [get_ports {LA_P[0]}]
+# set_property PACKAGE_PIN AM30 [get_ports {LA_N[0]}]
+# set_property PACKAGE_PIN AL29 [get_ports {LA_P[1]}]
+# set_property PACKAGE_PIN AL30 [get_ports {LA_N[1]}]
+# set_property PACKAGE_PIN AM27 [get_ports {LA_P[2]}]
+# set_property PACKAGE_PIN AP29 [get_ports {LA_P[3]}]
+# set_property PACKAGE_PIN AN28 [get_ports {LA_P[4]}]
+# set_property PACKAGE_PIN AP35 [get_ports {LA_P[5]}]
+# set_property PACKAGE_PIN AP33 [get_ports {LA_P[6]}]
+# set_property PACKAGE_PIN AM32 [get_ports {LA_P[7]}]
+# set_property PACKAGE_PIN AN31 [get_ports {LA_P[8]}]
+# set_property PACKAGE_PIN AM34 [get_ports {LA_P[9]}]
+# set_property PACKAGE_PIN AL34 [get_ports {LA_P[10]}]
+# set_property PACKAGE_PIN AM35 [get_ports {LA_P[11]}]
+# set_property PACKAGE_PIN AN33 [get_ports {LA_P[12]}]
+# set_property PACKAGE_PIN AK32 [get_ports {LA_P[13]}]
+# set_property PACKAGE_PIN AK35 [get_ports {LA_P[14]}]
+# set_property PACKAGE_PIN AH34 [get_ports {LA_P[15]}]
+# set_property PACKAGE_PIN AK33 [get_ports {LA_P[16]}]
+# set_property PACKAGE_PIN AK30 [get_ports {LA_P[17]}]
+# set_property PACKAGE_PIN AK31 [get_ports {LA_N[17]}]
+# set_property PACKAGE_PIN AJ30 [get_ports {LA_P[18]}]
+# set_property PACKAGE_PIN AJ31 [get_ports {LA_N[18]}]
+# set_property PACKAGE_PIN AJ28 [get_ports {LA_P[19]}]
+# set_property PACKAGE_PIN AH33 [get_ports {LA_P[20]}]
+# set_property PACKAGE_PIN AH28 [get_ports {LA_P[21]}]
+# set_property PACKAGE_PIN AG31 [get_ports {LA_P[22]}]
+# set_property PACKAGE_PIN AG29 [get_ports {LA_P[23]}]
+# set_property PACKAGE_PIN H32 [get_ports {LA_P[24]}]
+# set_property PACKAGE_PIN J34 [get_ports {LA_P[25]}]
+# set_property PACKAGE_PIN J30 [get_ports {LA_P[26]}]
+# set_property PACKAGE_PIN K32 [get_ports {LA_P[27]}]
+# set_property PACKAGE_PIN J29 [get_ports {LA_P[28]}]
+# set_property PACKAGE_PIN J33 [get_ports {LA_P[29]}]
+# set_property PACKAGE_PIN G34 [get_ports {LA_P[30]}]
+# set_property PACKAGE_PIN F33 [get_ports {LA_P[31]}]
+# set_property PACKAGE_PIN D34 [get_ports {LA_P[32]}]
+# set_property PACKAGE_PIN G29 [get_ports {LA_P[33]}]
+set_property PACKAGE_PIN AM17 [get_ports {MMB_DATA[0]}]
+set_property PACKAGE_PIN AL14 [get_ports {MMB_DATA[1]}]
+set_property PACKAGE_PIN AK15 [get_ports {MMB_DATA[2]}]
+set_property PACKAGE_PIN AK17 [get_ports {MMB_DATA[3]}]
+set_property PACKAGE_PIN AM14 [get_ports {MMB_DATA[4]}]
+set_property PACKAGE_PIN AN13 [get_ports {MMB_DATA[5]}]
+set_property PACKAGE_PIN AM11 [get_ports {MMB_DATA[6]}]
+set_property PACKAGE_PIN AN11 [get_ports {MMB_DATA[7]}]
+set_property PACKAGE_PIN AR13 [get_ports {MMB_DATA[8]}]
+set_property PACKAGE_PIN AR12 [get_ports {MMB_DATA[9]}]
+set_property PACKAGE_PIN AL10 [get_ports {MMB_DATA[10]}]
+set_property PACKAGE_PIN AM10 [get_ports {MMB_DATA[11]}]
+set_property PACKAGE_PIN AM12 [get_ports {MMB_DATA[12]}]
+set_property PACKAGE_PIN AN12 [get_ports {MMB_DATA[13]}]
+set_property PACKAGE_PIN AP13 [get_ports {MMB_DATA[14]}]
+set_property PACKAGE_PIN AK13 [get_ports {MMB_DATA[15]}]
+set_property PACKAGE_PIN AK12 [get_ports {MMB_DATA[16]}]
+set_property PACKAGE_PIN AK11 [get_ports {MMB_DATA[17]}]
+set_property PACKAGE_PIN AK10 [get_ports {MMB_DATA[18]}]
+set_property PACKAGE_PIN AH13 [get_ports {MMB_DATA[19]}]
+set_property PACKAGE_PIN AJ13 [get_ports {MMB_DATA[20]}]
+set_property PACKAGE_PIN AJ11 [get_ports {MMB_DATA[21]}]
+set_property PACKAGE_PIN AJ10 [get_ports {MMB_DATA[22]}]
+set_property PACKAGE_PIN AH12 [get_ports {MMB_DATA[23]}]
+set_property PACKAGE_PIN AH11 [get_ports MMB_DE]
+set_property PACKAGE_PIN AG12 [get_ports MMB_HS]
+set_property PACKAGE_PIN AH14 [get_ports MMB_IDCLK]
+set_property PACKAGE_PIN AF29 [get_ports MMB_SCK]
+set_property PACKAGE_PIN AC28 [get_ports {MMB_SD[0]}]
+set_property PACKAGE_PIN AC29 [get_ports {MMB_SD[1]}]
+set_property PACKAGE_PIN AE27 [get_ports {MMB_SD[2]}]
+set_property PACKAGE_PIN AF34 [get_ports {MMB_SD[3]}]
+set_property PACKAGE_PIN AG11 [get_ports MMB_VS]
+set_property PACKAGE_PIN AF30 [get_ports MMB_WS]
+set_property PACKAGE_PIN AL15 [get_ports {OSCCLK[0]}]
+set_property PACKAGE_PIN AK16 [get_ports {OSCCLK[1]}]
+set_property PACKAGE_PIN AY32 [get_ports {OSCCLK[2]}]
+set_property PACKAGE_PIN AY30 [get_ports {OSCCLK[3]}]
+set_property PACKAGE_PIN AC31 [get_ports {OSCCLK[4]}]
+set_property PACKAGE_PIN AC32 [get_ports {OSCCLK[5]}]
+set_property PACKAGE_PIN AT29 [get_ports PB_IRQ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D0]
+set_property PACKAGE_PIN AU24 [get_ports QSPI_D0]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D1]
+set_property PACKAGE_PIN AV24 [get_ports QSPI_D1]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D2]
+set_property PACKAGE_PIN AV21 [get_ports QSPI_D2]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D3]
+set_property PACKAGE_PIN AV22 [get_ports QSPI_D3]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_nCS]
+set_property PACKAGE_PIN AT24 [get_ports QSPI_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_SCLK]
+set_property PACKAGE_PIN AT25 [get_ports QSPI_SCLK]
+# not used
+# set_property PACKAGE_PIN AL13 [get_ports SATA_CLK_P]
+# set_property PACKAGE_PIN AL12 [get_ports SATA_CLK_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[0]}]
+set_property PACKAGE_PIN AW14 [get_ports {SH0_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[1]}]
+set_property PACKAGE_PIN AW13 [get_ports {SH0_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[2]}]
+set_property PACKAGE_PIN AW15 [get_ports {SH0_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[3]}]
+set_property PACKAGE_PIN AY15 [get_ports {SH0_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[4]}]
+set_property PACKAGE_PIN AY13 [get_ports {SH0_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[5]}]
+set_property PACKAGE_PIN AY12 [get_ports {SH0_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[6]}]
+set_property PACKAGE_PIN BA15 [get_ports {SH0_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[7]}]
+set_property PACKAGE_PIN BB14 [get_ports {SH0_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[8]}]
+set_property PACKAGE_PIN BA12 [get_ports {SH0_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[9]}]
+set_property PACKAGE_PIN BB12 [get_ports {SH0_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[10]}]
+set_property PACKAGE_PIN BA14 [get_ports {SH0_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[11]}]
+set_property PACKAGE_PIN BA13 [get_ports {SH0_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[12]}]
+set_property PACKAGE_PIN BB15 [get_ports {SH0_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[13]}]
+set_property PACKAGE_PIN AU12 [get_ports {SH0_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[14]}]
+set_property PACKAGE_PIN AV12 [get_ports {SH0_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[15]}]
+set_property PACKAGE_PIN AV17 [get_ports {SH0_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[16]}]
+set_property PACKAGE_PIN AV16 [get_ports {SH0_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[17]}]
+set_property PACKAGE_PIN AT14 [get_ports {SH0_IO[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[0]}]
+set_property PACKAGE_PIN AT17 [get_ports {SH1_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[1]}]
+set_property PACKAGE_PIN AU17 [get_ports {SH1_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[2]}]
+set_property PACKAGE_PIN AV19 [get_ports {SH1_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[3]}]
+set_property PACKAGE_PIN AW19 [get_ports {SH1_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[4]}]
+set_property PACKAGE_PIN AW20 [get_ports {SH1_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[5]}]
+set_property PACKAGE_PIN BA19 [get_ports {SH1_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[6]}]
+set_property PACKAGE_PIN BA18 [get_ports {SH1_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[7]}]
+set_property PACKAGE_PIN AY20 [get_ports {SH1_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[8]}]
+set_property PACKAGE_PIN BA20 [get_ports {SH1_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[9]}]
+set_property PACKAGE_PIN BA17 [get_ports {SH1_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[10]}]
+set_property PACKAGE_PIN BB17 [get_ports {SH1_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[11]}]
+set_property PACKAGE_PIN BB20 [get_ports {SH1_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[12]}]
+set_property PACKAGE_PIN BB19 [get_ports {SH1_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[13]}]
+set_property PACKAGE_PIN AW16 [get_ports {SH1_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[14]}]
+set_property PACKAGE_PIN AY16 [get_ports {SH1_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[15]}]
+set_property PACKAGE_PIN AY18 [get_ports {SH1_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[16]}]
+set_property PACKAGE_PIN AY17 [get_ports {SH1_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN BB16 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN AL25 [get_ports SH_ADC_CK]
+set_property PACKAGE_PIN AM25 [get_ports SH_ADC_CS]
+set_property PACKAGE_PIN AP25 [get_ports SH_ADC_DI]
+set_property PACKAGE_PIN AP26 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS33 [get_ports SH_nRST]
+set_property PACKAGE_PIN AU14 [get_ports SH_nRST]
+set_property PACKAGE_PIN AK20 [get_ports {SMBF_ADDR[0]}]
+set_property PACKAGE_PIN AK21 [get_ports {SMBF_ADDR[1]}]
+set_property PACKAGE_PIN AJ18 [get_ports {SMBF_ADDR[2]}]
+set_property PACKAGE_PIN AJ19 [get_ports {SMBF_ADDR[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {SMBF_ADDR[4]}]
+set_property PACKAGE_PIN AJ21 [get_ports {SMBF_ADDR[5]}]
+set_property PACKAGE_PIN AH19 [get_ports {SMBF_ADDR[6]}]
+set_property PACKAGE_PIN AK22 [get_ports {SMBF_DATA[0]}]
+set_property PACKAGE_PIN AL22 [get_ports {SMBF_DATA[1]}]
+set_property PACKAGE_PIN AL19 [get_ports {SMBF_DATA[2]}]
+set_property PACKAGE_PIN AL20 [get_ports {SMBF_DATA[3]}]
+set_property PACKAGE_PIN AH18 [get_ports {SMBF_DATA[4]}]
+set_property PACKAGE_PIN AM19 [get_ports {SMBF_DATA[5]}]
+set_property PACKAGE_PIN AN19 [get_ports {SMBF_DATA[6]}]
+set_property PACKAGE_PIN AP19 [get_ports {SMBF_DATA[7]}]
+set_property PACKAGE_PIN AP20 [get_ports {SMBF_DATA[8]}]
+set_property PACKAGE_PIN AM20 [get_ports {SMBF_DATA[9]}]
+set_property PACKAGE_PIN AN21 [get_ports {SMBF_DATA[10]}]
+set_property PACKAGE_PIN AP21 [get_ports {SMBF_DATA[11]}]
+set_property PACKAGE_PIN AR22 [get_ports {SMBF_DATA[12]}]
+set_property PACKAGE_PIN AM21 [get_ports {SMBF_DATA[13]}]
+set_property PACKAGE_PIN AM22 [get_ports {SMBF_DATA[14]}]
+set_property PACKAGE_PIN AN22 [get_ports {SMBF_DATA[15]}]
+set_property PACKAGE_PIN AJ20 [get_ports SMBF_FIFOSEL]
+set_property PACKAGE_PIN AN23 [get_ports SMBF_nOE]
+set_property PACKAGE_PIN AL23 [get_ports SMBF_nRST]
+set_property PACKAGE_PIN AP23 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[16]}]
+set_property PACKAGE_PIN AR26 [get_ports {SMBM_A[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[17]}]
+set_property PACKAGE_PIN AT22 [get_ports {SMBM_A[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[18]}]
+set_property PACKAGE_PIN AT23 [get_ports {SMBM_A[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[19]}]
+set_property PACKAGE_PIN AU21 [get_ports {SMBM_A[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[20]}]
+set_property PACKAGE_PIN AY22 [get_ports {SMBM_A[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[21]}]
+set_property PACKAGE_PIN BA22 [get_ports {SMBM_A[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[22]}]
+set_property PACKAGE_PIN AW21 [get_ports {SMBM_A[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[23]}]
+set_property PACKAGE_PIN AY21 [get_ports {SMBM_A[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[24]}]
+set_property PACKAGE_PIN BA23 [get_ports {SMBM_A[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[25]}]
+set_property PACKAGE_PIN BA24 [get_ports {SMBM_A[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_CLK]
+set_property PACKAGE_PIN AY25 [get_ports SMBM_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[0]}]
+set_property PACKAGE_PIN BB21 [get_ports {SMBM_D[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[1]}]
+set_property PACKAGE_PIN BB22 [get_ports {SMBM_D[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[2]}]
+set_property PACKAGE_PIN AW24 [get_ports {SMBM_D[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {SMBM_D[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[4]}]
+set_property PACKAGE_PIN AW23 [get_ports {SMBM_D[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[5]}]
+set_property PACKAGE_PIN AY23 [get_ports {SMBM_D[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[6]}]
+set_property PACKAGE_PIN BB24 [get_ports {SMBM_D[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[7]}]
+set_property PACKAGE_PIN AY27 [get_ports {SMBM_D[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[8]}]
+set_property PACKAGE_PIN AY26 [get_ports {SMBM_D[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[9]}]
+set_property PACKAGE_PIN AY28 [get_ports {SMBM_D[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[10]}]
+set_property PACKAGE_PIN BA28 [get_ports {SMBM_D[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[11]}]
+set_property PACKAGE_PIN BA25 [get_ports {SMBM_D[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[12]}]
+set_property PACKAGE_PIN BB25 [get_ports {SMBM_D[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[13]}]
+set_property PACKAGE_PIN AW28 [get_ports {SMBM_D[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[14]}]
+set_property PACKAGE_PIN AW29 [get_ports {SMBM_D[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[15]}]
+set_property PACKAGE_PIN BB26 [get_ports {SMBM_D[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[0]}]
+set_property PACKAGE_PIN AU26 [get_ports {SMBM_nBL[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[1]}]
+set_property PACKAGE_PIN AR28 [get_ports {SMBM_nBL[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[1]}]
+set_property PACKAGE_PIN BB27 [get_ports {SMBM_nE[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[2]}]
+set_property PACKAGE_PIN AU27 [get_ports {SMBM_nE[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[3]}]
+set_property PACKAGE_PIN AV28 [get_ports {SMBM_nE[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[4]}]
+set_property PACKAGE_PIN AU25 [get_ports {SMBM_nE[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nOE]
+set_property PACKAGE_PIN AT28 [get_ports SMBM_nOE]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWAIT]
+set_property PACKAGE_PIN AP28 [get_ports SMBM_nWAIT]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AR27 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AF28 [get_ports {UART_RX_F[0]}]
+set_property PACKAGE_PIN AE31 [get_ports {UART_RX_F[1]}]
+set_property PACKAGE_PIN AE28 [get_ports {UART_RX_F[2]}]
+set_property PACKAGE_PIN AD30 [get_ports {UART_RX_F[3]}]
+set_property PACKAGE_PIN AF27 [get_ports {UART_TX_F[0]}]
+set_property PACKAGE_PIN AE30 [get_ports {UART_TX_F[1]}]
+set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
+set_property PACKAGE_PIN AD29 [get_ports {UART_TX_F[3]}]
+set_property PACKAGE_PIN AN26 [get_ports USB_DACK]
+set_property PACKAGE_PIN AN24 [get_ports USB_DREQ]
+set_property PACKAGE_PIN AP24 [get_ports USB_INT]
+set_property PACKAGE_PIN AM26 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CLK]
+set_property PACKAGE_PIN AU15 [get_ports USD_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CMD]
+set_property PACKAGE_PIN AU16 [get_ports USD_CMD]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[0]}]
+set_property PACKAGE_PIN AV14 [get_ports {USD_DAT[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[1]}]
+set_property PACKAGE_PIN AV13 [get_ports {USD_DAT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[2]}]
+set_property PACKAGE_PIN AT13 [get_ports {USD_DAT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[3]}]
+set_property PACKAGE_PIN AT12 [get_ports {USD_DAT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_NCD]
+set_property PACKAGE_PIN AT15 [get_ports USD_NCD]
+set_property PACKAGE_PIN AU32 [get_ports {USER_nLED[0]}]
+set_property PACKAGE_PIN AU30 [get_ports {USER_nLED[1]}]
+set_property PACKAGE_PIN AU31 [get_ports {USER_nLED[2]}]
+set_property PACKAGE_PIN AR32 [get_ports {USER_nLED[3]}]
+set_property PACKAGE_PIN AT33 [get_ports {USER_nLED[4]}]
+set_property PACKAGE_PIN AW30 [get_ports {USER_nLED[5]}]
+set_property PACKAGE_PIN AW31 [get_ports {USER_nLED[6]}]
+set_property PACKAGE_PIN AR30 [get_ports {USER_nLED[7]}]
+set_property PACKAGE_PIN BB31 [get_ports {USER_nLED[8]}]
+set_property PACKAGE_PIN BB32 [get_ports {USER_nLED[9]}]
+set_property PACKAGE_PIN AT30 [get_ports {USER_nPB[0]}]
+set_property PACKAGE_PIN AT32 [get_ports {USER_nPB[1]}]
+set_property PACKAGE_PIN BA29 [get_ports {USER_SW[0]}]
+set_property PACKAGE_PIN BB29 [get_ports {USER_SW[1]}]
+set_property PACKAGE_PIN BA32 [get_ports {USER_SW[2]}]
+set_property PACKAGE_PIN BA33 [get_ports {USER_SW[3]}]
+set_property PACKAGE_PIN BA30 [get_ports {USER_SW[4]}]
+set_property PACKAGE_PIN BB30 [get_ports {USER_SW[5]}]
+set_property PACKAGE_PIN AY33 [get_ports {USER_SW[6]}]
+set_property PACKAGE_PIN AY31 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports WDOG_RREQ]
+set_property PACKAGE_PIN AU19 [get_ports WDOG_RREQ]
+
+# native DDR pin names
+
+# set_property PACKAGE_PIN A17 [get_ports {c0_ddr4_dq[37]}]
+# set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[54]}]
+# set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[55]}]
+# set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_dq[28]}]
+# set_property PACKAGE_PIN D23 [get_ports {c0_ddr4_dq[52]}]
+# set_property PACKAGE_PIN D24 [get_ports {c0_ddr4_dq[53]}]
+# set_property PACKAGE_PIN C24 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+# set_property PACKAGE_PIN A22 [get_ports {c0_ddr4_dq[46]}]
+# set_property PACKAGE_PIN A23 [get_ports {c0_ddr4_dq[47]}]
+# set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_dq[29]}]
+# set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_dq[27]}]
+# set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dqs_t[6]}]
+# set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dqs_c[6]}]
+# set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dq[50]}]
+# set_property PACKAGE_PIN G21 [get_ports {c0_ddr4_dq[51]}]
+# set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+# set_property PACKAGE_PIN A24 [get_ports {c0_ddr4_dq[42]}]
+# set_property PACKAGE_PIN B22 [get_ports {c0_ddr4_dqs_t[5]}]
+# set_property PACKAGE_PIN B21 [get_ports {c0_ddr4_dqs_c[5]}]
+# set_property PACKAGE_PIN B17 [get_ports {c0_ddr4_dqs_t[4]}]
+# set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_dqs_c[4]}]
+# set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dq[38]}]
+# set_property PACKAGE_PIN A12 [get_ports {c0_ddr4_dq[31]}]
+# set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[48]}]
+# set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[49]}]
+# set_property PACKAGE_PIN C23 [get_ports {c0_ddr4_dq[40]}]
+# set_property PACKAGE_PIN A25 [get_ports {c0_ddr4_dq[43]}]
+# set_property PACKAGE_PIN C22 [get_ports {c0_ddr4_dq[44]}]
+# set_property PACKAGE_PIN B14 [get_ports {c0_ddr4_dq[24]}]
+# set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_adr[4]}]
+# set_property PACKAGE_PIN C21 [get_ports {c0_ddr4_dq[41]}]
+# set_property PACKAGE_PIN D21 [get_ports {c0_ddr4_dq[45]}]
+# set_property PACKAGE_PIN C16 [get_ports {c0_ddr4_dq[32]}]
+# set_property PACKAGE_PIN E12 [get_ports {c0_ddr4_dq[16]}]
+# set_property PACKAGE_PIN D13 [get_ports {c0_ddr4_dq[25]}]
+# set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_dqs_t[3]}]
+# set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_dqs_c[3]}]
+# set_property PACKAGE_PIN E15 [get_ports {c0_ddr4_dq[18]}]
+# #set_property PACKAGE_PIN P18 [get_ports {c0_ddr4_ck_t[1]}]
+# #set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_ck_c[1]}]
+# set_property PACKAGE_PIN L19 [get_ports {c0_ddr4_adr[0]}]
+# set_property PACKAGE_PIN J18 [get_ports {c0_ddr4_adr[5]}]
+# #set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke[0]}]
+# set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke}]
+# set_property PACKAGE_PIN D19 [get_ports c0_ddr4_act_n]
+# set_property PACKAGE_PIN F12 [get_ports {c0_ddr4_dq[17]}]
+# set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_dq[19]}]
+# set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_adr[2]}]
+# set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_adr[3]}]
+# set_property PACKAGE_PIN J16 [get_ports {c0_ddr4_adr[1]}]
+# #set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_cke[1]}]
+# set_property PACKAGE_PIN E18 [get_ports c0_ddr4_reset_n]
+# set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_dqs_t[2]}]
+# set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_dqs_c[2]}]
+# #set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t[0]}]
+# set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t}]
+# #set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c[0]}]
+# set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c}]
+# set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_bg[0]}]
+# #set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_bg[1]}]
+# #set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt[0]}]
+# set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt}]
+# #set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n[0]}]
+# set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n}]
+# #set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_cs_n[1]}]
+# #set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_odt[1]}]
+# set_property PACKAGE_PIN K13 [get_ports {c0_ddr4_dq[10]}]
+# set_property PACKAGE_PIN J14 [get_ports {c0_ddr4_dq[11]}]
+# set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_adr[16]}]
+# set_property PACKAGE_PIN G17 [get_ports {c0_ddr4_ba[0]}]
+# set_property PACKAGE_PIN H16 [get_ports {c0_ddr4_adr[14]}]
+# set_property PACKAGE_PIN G19 [get_ports {c0_ddr4_ba[1]}]
+# set_property PACKAGE_PIN N11 [get_ports {c0_ddr4_dqs_t[0]}]
+# set_property PACKAGE_PIN M11 [get_ports {c0_ddr4_dqs_c[0]}]
+# set_property PACKAGE_PIN J15 [get_ports {c0_ddr4_dq[8]}]
+# set_property PACKAGE_PIN K15 [get_ports {c0_ddr4_dq[9]}]
+# set_property PACKAGE_PIN G16 [get_ports {c0_ddr4_adr[15]}]
+# set_property PACKAGE_PIN M10 [get_ports {c0_ddr4_dq[6]}]
+# set_property PACKAGE_PIN L10 [get_ports {c0_ddr4_dq[7]}]
+# set_property PACKAGE_PIN J11 [get_ports {c0_ddr4_dqs_t[1]}]
+# set_property PACKAGE_PIN J10 [get_ports {c0_ddr4_dqs_c[1]}]
+# set_property PACKAGE_PIN L17 [get_ports {c0_ddr4_adr[6]}]
+# set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_adr[8]}]
+# set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_adr[9]}]
+# set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_adr[7]}]
+# set_property PACKAGE_PIN M19 [get_ports {c0_ddr4_adr[10]}]
+# set_property PACKAGE_PIN M15 [get_ports {c0_ddr4_adr[11]}]
+# set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_adr[12]}]
+# set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_adr[13]}]
+# set_property PACKAGE_PIN L22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+# set_property PACKAGE_PIN P11 [get_ports {c0_ddr4_dq[0]}]
+# set_property PACKAGE_PIN P10 [get_ports {c0_ddr4_dq[1]}]
+# set_property PACKAGE_PIN L12 [get_ports {c0_ddr4_dq[2]}]
+# set_property PACKAGE_PIN M12 [get_ports {c0_ddr4_dq[3]}]
+# set_property PACKAGE_PIN N13 [get_ports {c0_ddr4_dq[4]}]
+# set_property PACKAGE_PIN N12 [get_ports {c0_ddr4_dq[5]}]
+# set_property PACKAGE_PIN K11 [get_ports {c0_ddr4_dq[12]}]
+# set_property PACKAGE_PIN K10 [get_ports {c0_ddr4_dq[13]}]
+# set_property PACKAGE_PIN J13 [get_ports {c0_ddr4_dq[14]}]
+# set_property PACKAGE_PIN K12 [get_ports {c0_ddr4_dq[15]}]
+# set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[20]}]
+# set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[21]}]
+# set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_dq[22]}]
+# set_property PACKAGE_PIN G14 [get_ports {c0_ddr4_dq[23]}]
+# set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_dq[26]}]
+# set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_dq[30]}]
+# set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[33]}]
+# set_property PACKAGE_PIN B19 [get_ports {c0_ddr4_dq[34]}]
+# set_property PACKAGE_PIN A20 [get_ports {c0_ddr4_dq[35]}]
+# set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[36]}]
+# set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dq[39]}]
+# set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[56]}]
+# set_property PACKAGE_PIN J23 [get_ports {c0_ddr4_dq[57]}]
+# set_property PACKAGE_PIN K20 [get_ports {c0_ddr4_dq[58]}]
+# set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dq[59]}]
+# set_property PACKAGE_PIN H21 [get_ports {c0_ddr4_dq[60]}]
+# set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[61]}]
+# set_property PACKAGE_PIN K23 [get_ports {c0_ddr4_dq[62]}]
+# set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[63]}]
+# set_property PACKAGE_PIN N14 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+# set_property PACKAGE_PIN L14 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+# set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+# set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+# set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+# set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dqs_t[7]}]
+
+#set_property CFGBVS GND [current_design]
+#set_property CONFIG_VOLTAGE 1.8 [current_design]
+
+# set_property PACKAGE_PIN H19 [get_ports c0_sys_clk_p]
+# set_property PACKAGE_PIN H18 [get_ports c0_sys_clk_n]
+
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[1]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[0]}]
+
+# set_property PACKAGE_PIN AB31 [get_ports GTX_CLK_P]
+# set_property PACKAGE_PIN AB32 [get_ports GTX_CLK_N]
+
+# set_property PACKAGE_PIN AH39 [get_ports {DP_C2M_N[0]}]
+# set_property PACKAGE_PIN AF39 [get_ports {DP_C2M_N[1]}]
+# set_property PACKAGE_PIN AD39 [get_ports {DP_C2M_N[2]}]
+# set_property PACKAGE_PIN AB39 [get_ports {DP_C2M_N[3]}]
+# set_property PACKAGE_PIN Y39 [get_ports {DP_C2M_N[4]}]
+# set_property PACKAGE_PIN V39 [get_ports {DP_C2M_N[5]}]
+# set_property PACKAGE_PIN K39 [get_ports {DP_C2M_N[6]}]
+# set_property PACKAGE_PIN M39 [get_ports {DP_C2M_N[7]}]
+# set_property PACKAGE_PIN P39 [get_ports {DP_C2M_N[8]}]
+# set_property PACKAGE_PIN T39 [get_ports {DP_C2M_N[9]}]
+# set_property PACKAGE_PIN AH38 [get_ports {DP_C2M_P[0]}]
+# set_property PACKAGE_PIN AF38 [get_ports {DP_C2M_P[1]}]
+# set_property PACKAGE_PIN AD38 [get_ports {DP_C2M_P[2]}]
+# set_property PACKAGE_PIN AB38 [get_ports {DP_C2M_P[3]}]
+# set_property PACKAGE_PIN Y38 [get_ports {DP_C2M_P[4]}]
+# set_property PACKAGE_PIN V38 [get_ports {DP_C2M_P[5]}]
+# set_property PACKAGE_PIN K38 [get_ports {DP_C2M_P[6]}]
+# set_property PACKAGE_PIN M38 [get_ports {DP_C2M_P[7]}]
+# set_property PACKAGE_PIN P38 [get_ports {DP_C2M_P[8]}]
+# set_property PACKAGE_PIN T38 [get_ports {DP_C2M_P[9]}]
+# set_property PACKAGE_PIN AE36 [get_ports {GBTCLK_M2C_P[0]}]
+# set_property PACKAGE_PIN AE37 [get_ports {GBTCLK_M2C_N[0]}]
+# set_property PACKAGE_PIN AA36 [get_ports {GBTCLK_M2C_P[1]}]
+# set_property PACKAGE_PIN AA37 [get_ports {GBTCLK_M2C_N[1]}]
+
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y4_p [get_ports {GBTCLK_M2C_P[0]}]
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y7_p [get_ports {GBTCLK_M2C_P[1]}]
+
+# # False path constraints
+# # ----------------------------------------------------------------------------------------------------------------------
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]
+
+#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iACLK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CFG_CLK_IBUF_inst/O]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iGPUCLK]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iMCLK]
+
+set_property PULLUP true [get_ports QSPI_D0]
+set_property PULLUP true [get_ports QSPI_D1]
+set_property PULLUP true [get_ports QSPI_D2]
+set_property PULLUP true [get_ports QSPI_D3]
+
+# set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
+# set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports "c0_ddr4_bg[0]"]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
+set_property BITSTREAM.CONFIG.PERSIST Yes [current_design]
+set_property BITSTREAM.STARTUP.MATCH_CYCLE Auto [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
+set_property CONFIG_MODE S_SELECTMAP [current_design]
+
+set_property PACKAGE_PIN AR26 [get_ports NRST]
+set_property PACKAGE_PIN AR27 [get_ports {P0[0]}]
+set_property PACKAGE_PIN AW29 [get_ports {P0[10]}]
+set_property PACKAGE_PIN BA25 [get_ports {P0[11]}]
+set_property PACKAGE_PIN BB25 [get_ports {P0[12]}]
+set_property PACKAGE_PIN AY28 [get_ports {P0[13]}]
+set_property PACKAGE_PIN BA28 [get_ports {P0[14]}]
+set_property PACKAGE_PIN AY26 [get_ports {P0[15]}]
+set_property PACKAGE_PIN AR28 [get_ports {P0[1]}]
+set_property PACKAGE_PIN AT28 [get_ports {P0[2]}]
+set_property PACKAGE_PIN AU25 [get_ports {P0[3]}]
+set_property PACKAGE_PIN AU26 [get_ports {P0[4]}]
+set_property PACKAGE_PIN AU27 [get_ports {P0[5]}]
+set_property PACKAGE_PIN AV28 [get_ports {P0[6]}]
+set_property PACKAGE_PIN BB26 [get_ports {P0[7]}]
+set_property PACKAGE_PIN BB27 [get_ports {P0[8]}]
+set_property PACKAGE_PIN AW28 [get_ports {P0[9]}]
+set_property PACKAGE_PIN AW26 [get_ports {P1[0]}]
+set_property PACKAGE_PIN AY21 [get_ports {P1[10]}]
+set_property PACKAGE_PIN AY22 [get_ports {P1[11]}]
+set_property PACKAGE_PIN BA22 [get_ports {P1[12]}]
+set_property PACKAGE_PIN AT22 [get_ports {P1[13]}]
+set_property PACKAGE_PIN AT23 [get_ports {P1[14]}]
+set_property PACKAGE_PIN AR25 [get_ports {P1[15]}]
+set_property PACKAGE_PIN AY27 [get_ports {P1[1]}]
+set_property PACKAGE_PIN AW23 [get_ports {P1[2]}]
+set_property PACKAGE_PIN AY23 [get_ports {P1[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {P1[4]}]
+set_property PACKAGE_PIN BB21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN BB22 [get_ports {P1[6]}]
+set_property PACKAGE_PIN BA23 [get_ports {P1[7]}]
+set_property PACKAGE_PIN BA24 [get_ports {P1[8]}]
+set_property PACKAGE_PIN AW21 [get_ports {P1[9]}]
+set_property PACKAGE_PIN AW24 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN AU22 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN AV23 [get_ports VDD]
+set_property PACKAGE_PIN AT24 [get_ports VDDIO]
+set_property PACKAGE_PIN AT25 [get_ports VSS]
+set_property PACKAGE_PIN AV21 [get_ports VSSIO]
+set_property PACKAGE_PIN AY25 [get_ports XTAL1]
+set_property PACKAGE_PIN AV22 [get_ports XTAL2]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4b89d747c16fc5a7319b9e0a8f1e0f48df0fafd8
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xcku115-flvb1760-1-c
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..78ac5e66193d3180e0df08f400cc924f8f74e8be
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc
@@ -0,0 +1,99 @@
+##################################################################################
+## ##
+## Arm MPS3 Rev-C timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks SWCLK]
+
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
+set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
+set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..22a84dfa88d5b9ac56e2bb92024d0ebd2e24b01e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
@@ -0,0 +1,508 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o
+ create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z
+ create_bd_pin -dir O -from 15 -to 0 gpio_tri_i
+ create_bd_pin -dir I -from 15 -to 0 gpio_tri_o
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_gpio_2, and set properties
+ set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_2
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
+ ] $axi_uartlite_0
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o]
+ connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net nanosoc_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net nanosoc_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net nanosoc_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i]
+ connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din]
+ connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {20.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CLK0_FREQ {20000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {8} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ ] $processing_system7_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+
+ # Create port connections
+ connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o]
+ connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z]
+ connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins nanosoc_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o]
+ connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins nanosoc_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i]
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins nanosoc_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins nanosoc_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins nanosoc_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+
+ # Create address segments
+ assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce586c7af967a217fedd3c4fae7ef758794c7931
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5599cd2eec9ca0da4c7b57e21412e609fd7d41de
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
@@ -0,0 +1,33 @@
+##################################################################################
+## ##
+## PZ2 PMODA XDC ##
+## ##
+##################################################################################
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+
+set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
+set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
+set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
+set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
+set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
+set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
+set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
+set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
+
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1a9e44eff2f8e3cc3a24a1c5e1da88ae70f62c90
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xc7z020clg400-1
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..879aaadbadf756cabae24bf0f3f919d9951a8e5d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4859c7bf4bbd640cadb922491a7de25c57e547e4
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl
@@ -0,0 +1,1017 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o
+ create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z
+ create_bd_pin -dir O -from 15 -to 0 gpio_tri_i
+ create_bd_pin -dir I -from 15 -to 0 gpio_tri_o
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_gpio_2, and set properties
+ set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_2
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o]
+ connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net nanosoc_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net nanosoc_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net nanosoc_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i]
+ connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din]
+ connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+ set_property -dict [ list \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+ CONFIG.PSU_MIO_0_DIRECTION {out} \
+ CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_0_POLARITY {Default} \
+ CONFIG.PSU_MIO_16_DIRECTION {inout} \
+ CONFIG.PSU_MIO_16_POLARITY {Default} \
+ CONFIG.PSU_MIO_17_DIRECTION {inout} \
+ CONFIG.PSU_MIO_17_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_DIRECTION {in} \
+ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_18_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_SLEW {fast} \
+ CONFIG.PSU_MIO_19_DIRECTION {out} \
+ CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_19_POLARITY {Default} \
+ CONFIG.PSU_MIO_1_DIRECTION {inout} \
+ CONFIG.PSU_MIO_1_POLARITY {Default} \
+ CONFIG.PSU_MIO_20_DIRECTION {out} \
+ CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_20_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_DIRECTION {in} \
+ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_21_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DIRECTION {out} \
+ CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_24_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_DIRECTION {in} \
+ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_25_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DIRECTION {out} \
+ CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_27_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_DIRECTION {in} \
+ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_28_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_SLEW {fast} \
+ CONFIG.PSU_MIO_29_DIRECTION {out} \
+ CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_29_POLARITY {Default} \
+ CONFIG.PSU_MIO_2_DIRECTION {inout} \
+ CONFIG.PSU_MIO_2_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_DIRECTION {in} \
+ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_30_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DIRECTION {inout} \
+ CONFIG.PSU_MIO_3_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_DIRECTION {in} \
+ CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_45_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_SLEW {fast} \
+ CONFIG.PSU_MIO_46_DIRECTION {inout} \
+ CONFIG.PSU_MIO_46_POLARITY {Default} \
+ CONFIG.PSU_MIO_47_DIRECTION {inout} \
+ CONFIG.PSU_MIO_47_POLARITY {Default} \
+ CONFIG.PSU_MIO_48_DIRECTION {inout} \
+ CONFIG.PSU_MIO_48_POLARITY {Default} \
+ CONFIG.PSU_MIO_49_DIRECTION {inout} \
+ CONFIG.PSU_MIO_49_POLARITY {Default} \
+ CONFIG.PSU_MIO_4_DIRECTION {inout} \
+ CONFIG.PSU_MIO_4_POLARITY {Default} \
+ CONFIG.PSU_MIO_50_DIRECTION {inout} \
+ CONFIG.PSU_MIO_50_POLARITY {Default} \
+ CONFIG.PSU_MIO_51_DIRECTION {out} \
+ CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_51_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_DIRECTION {in} \
+ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_52_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_SLEW {fast} \
+ CONFIG.PSU_MIO_53_DIRECTION {in} \
+ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_53_POLARITY {Default} \
+ CONFIG.PSU_MIO_53_SLEW {fast} \
+ CONFIG.PSU_MIO_54_DIRECTION {inout} \
+ CONFIG.PSU_MIO_54_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_DIRECTION {in} \
+ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_55_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_SLEW {fast} \
+ CONFIG.PSU_MIO_56_DIRECTION {inout} \
+ CONFIG.PSU_MIO_56_POLARITY {Default} \
+ CONFIG.PSU_MIO_57_DIRECTION {inout} \
+ CONFIG.PSU_MIO_57_POLARITY {Default} \
+ CONFIG.PSU_MIO_58_DIRECTION {out} \
+ CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_58_POLARITY {Default} \
+ CONFIG.PSU_MIO_59_DIRECTION {inout} \
+ CONFIG.PSU_MIO_59_POLARITY {Default} \
+ CONFIG.PSU_MIO_5_DIRECTION {out} \
+ CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_5_POLARITY {Default} \
+ CONFIG.PSU_MIO_60_DIRECTION {inout} \
+ CONFIG.PSU_MIO_60_POLARITY {Default} \
+ CONFIG.PSU_MIO_61_DIRECTION {inout} \
+ CONFIG.PSU_MIO_61_POLARITY {Default} \
+ CONFIG.PSU_MIO_62_DIRECTION {inout} \
+ CONFIG.PSU_MIO_62_POLARITY {Default} \
+ CONFIG.PSU_MIO_63_DIRECTION {inout} \
+ CONFIG.PSU_MIO_63_POLARITY {Default} \
+ CONFIG.PSU_MIO_64_DIRECTION {out} \
+ CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_64_POLARITY {Default} \
+ CONFIG.PSU_MIO_65_DIRECTION {out} \
+ CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_65_POLARITY {Default} \
+ CONFIG.PSU_MIO_66_DIRECTION {out} \
+ CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_66_POLARITY {Default} \
+ CONFIG.PSU_MIO_67_DIRECTION {out} \
+ CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_67_POLARITY {Default} \
+ CONFIG.PSU_MIO_68_DIRECTION {out} \
+ CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_68_POLARITY {Default} \
+ CONFIG.PSU_MIO_69_DIRECTION {out} \
+ CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_69_POLARITY {Default} \
+ CONFIG.PSU_MIO_6_DIRECTION {out} \
+ CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_6_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_DIRECTION {in} \
+ CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_70_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_SLEW {fast} \
+ CONFIG.PSU_MIO_71_DIRECTION {in} \
+ CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_71_POLARITY {Default} \
+ CONFIG.PSU_MIO_71_SLEW {fast} \
+ CONFIG.PSU_MIO_72_DIRECTION {in} \
+ CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_72_POLARITY {Default} \
+ CONFIG.PSU_MIO_72_SLEW {fast} \
+ CONFIG.PSU_MIO_73_DIRECTION {in} \
+ CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_73_POLARITY {Default} \
+ CONFIG.PSU_MIO_73_SLEW {fast} \
+ CONFIG.PSU_MIO_74_DIRECTION {in} \
+ CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_74_POLARITY {Default} \
+ CONFIG.PSU_MIO_74_SLEW {fast} \
+ CONFIG.PSU_MIO_75_DIRECTION {in} \
+ CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_75_POLARITY {Default} \
+ CONFIG.PSU_MIO_75_SLEW {fast} \
+ CONFIG.PSU_MIO_76_DIRECTION {out} \
+ CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_76_POLARITY {Default} \
+ CONFIG.PSU_MIO_77_DIRECTION {inout} \
+ CONFIG.PSU_MIO_77_POLARITY {Default} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
+SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
+1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
+1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
+3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
+3}\
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+ CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+ CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+ CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+ CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+ CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+ CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+ CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+ CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+ CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+ CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+ CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+ CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+ CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+ CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+ CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+ CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+ CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB0__RESET__ENABLE {0} \
+ CONFIG.PSU__USB1__RESET__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ ] $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o]
+ connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z]
+ connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins nanosoc_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o]
+ connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins nanosoc_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i]
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins nanosoc_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins nanosoc_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins nanosoc_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce586c7af967a217fedd3c4fae7ef758794c7931
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..4a635dde3eeee4ba52cd771abdd9df48b7e59231
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
@@ -0,0 +1,1031 @@
+##################################################################################
+## ##
+## ZCU104 Rev1.0 Master XDC ##
+## ##
+##################################################################################
+
+#Other net PACKAGE_PIN V17 - SYSMON_DXN Bank 0 - DXN
+#Other net PACKAGE_PIN V18 - SYSMON_DXP Bank 0 - DXP
+#Other net PACKAGE_PIN R17 - SYSMON_AGND Bank 0 - GNDADC
+#Other net PACKAGE_PIN AA12 - 3N5824 Bank 0 - POR_OVERRIDE
+#Other net PACKAGE_PIN AA13 - 3N5822 Bank 0 - PUDC_B
+#Other net PACKAGE_PIN R18 - FPGA_SYSMON_AVCC Bank 0 - VCCADC
+#Other net PACKAGE_PIN U17 - SYSMON_VN_R Bank 0 - VN
+#Other net PACKAGE_PIN T18 - SYSMON_VP_R Bank 0 - VP
+#Other net PACKAGE_PIN T17 - SYSMON_AGND Bank 0 - VREFN
+#Other net PACKAGE_PIN U18 - SYSMON_AGND Bank 0 - VREFP
+#set_property PACKAGE_PIN B21 [get_ports "5N7582"] ;# Bank 28 VCCO - VCC1V8 - IO_L24N_T3U_N11_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7582"] ;# Bank 28 VCCO - VCC1V8 - IO_L24N_T3U_N11_28
+#set_property PACKAGE_PIN B20 [get_ports "5N7577"] ;# Bank 28 VCCO - VCC1V8 - IO_L24P_T3U_N10_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7577"] ;# Bank 28 VCCO - VCC1V8 - IO_L24P_T3U_N10_28
+#set_property PACKAGE_PIN A23 [get_ports "5N7578"] ;# Bank 28 VCCO - VCC1V8 - IO_L23N_T3U_N9_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7578"] ;# Bank 28 VCCO - VCC1V8 - IO_L23N_T3U_N9_28
+#set_property PACKAGE_PIN A22 [get_ports "5N7569"] ;# Bank 28 VCCO - VCC1V8 - IO_L23P_T3U_N8_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7569"] ;# Bank 28 VCCO - VCC1V8 - IO_L23P_T3U_N8_28
+#set_property PACKAGE_PIN B19 [get_ports "5N7570"] ;# Bank 28 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7570"] ;# Bank 28 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property PACKAGE_PIN B18 [get_ports "5N7565"] ;# Bank 28 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7565"] ;# Bank 28 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property PACKAGE_PIN A21 [get_ports "5N7709"] ;# Bank 28 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7709"] ;# Bank 28 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_28
+#set_property PACKAGE_PIN A18 [get_ports "5N7704"] ;# Bank 28 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7704"] ;# Bank 28 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property PACKAGE_PIN B23 [get_ports "5N7581"] ;# Bank 28 VCCO - VCC1V8 - IO_T3U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7581"] ;# Bank 28 VCCO - VCC1V8 - IO_T3U_N12_28
+#set_property PACKAGE_PIN F25 [get_ports "5N7703"] ;# Bank 28 VCCO - VCC1V8 - IO_T2U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7703"] ;# Bank 28 VCCO - VCC1V8 - IO_T2U_N12_28
+#set_property PACKAGE_PIN G26 [get_ports "5N7702"] ;# Bank 28 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7702"] ;# Bank 28 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_28
+#set_property PACKAGE_PIN G25 [get_ports "5N7694"] ;# Bank 28 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7694"] ;# Bank 28 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_28
+#set_property PACKAGE_PIN C23 [get_ports "5N7693"] ;# Bank 28 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7693"] ;# Bank 28 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_28
+#set_property PACKAGE_PIN D22 [get_ports "5N7690"] ;# Bank 28 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7690"] ;# Bank 28 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_28
+#set_property PACKAGE_PIN D24 [get_ports "5N7688"] ;# Bank 28 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7688"] ;# Bank 28 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property PACKAGE_PIN E24 [get_ports "5N7682"] ;# Bank 28 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7682"] ;# Bank 28 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property PACKAGE_PIN C22 [get_ports "5N7681"] ;# Bank 28 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7681"] ;# Bank 28 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_28
+#set_property PACKAGE_PIN C21 [get_ports "5N7678"] ;# Bank 28 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7678"] ;# Bank 28 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_28
+#set_property PACKAGE_PIN G24 [get_ports "5N7676"] ;# Bank 28 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7676"] ;# Bank 28 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_28
+#set_property PACKAGE_PIN G23 [get_ports "5N7672"] ;# Bank 28 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7672"] ;# Bank 28 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_28
+#set_property PACKAGE_PIN F20 [get_ports "5N7532"] ;# Bank 28 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7532"] ;# Bank 28 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property PACKAGE_PIN G20 [get_ports "5N7533"] ;# Bank 28 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7533"] ;# Bank 28 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property PACKAGE_PIN D21 [get_ports "5N7524"] ;# Bank 28 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7524"] ;# Bank 28 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_28
+#set_property PACKAGE_PIN D20 [get_ports "5N7525"] ;# Bank 28 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7525"] ;# Bank 28 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_28
+#set_property PACKAGE_PIN H22 [get_ports "5N7520"] ;# Bank 28 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7520"] ;# Bank 28 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_28
+#set_property PACKAGE_PIN H21 [get_ports "5N7521"] ;# Bank 28 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7521"] ;# Bank 28 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_28
+#set_property PACKAGE_PIN D19 [get_ports "5N7512"] ;# Bank 28 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7512"] ;# Bank 28 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property PACKAGE_PIN E19 [get_ports "5N7513"] ;# Bank 28 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7513"] ;# Bank 28 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property PACKAGE_PIN E20 [get_ports "5N7726"] ;# Bank 28 VCCO - VCC1V8 - IO_T1U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7726"] ;# Bank 28 VCCO - VCC1V8 - IO_T1U_N12_28
+#set_property PACKAGE_PIN H23 [get_ports "5N7508"] ;# Bank 28 VCCO - VCC1V8 - IO_T0U_N12_VRP_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7508"] ;# Bank 28 VCCO - VCC1V8 - IO_T0U_N12_VRP_28
+#set_property PACKAGE_PIN H24 [get_ports "5N7509"] ;# Bank 28 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7509"] ;# Bank 28 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_28
+#set_property PACKAGE_PIN J24 [get_ports "5N7500"] ;# Bank 28 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7500"] ;# Bank 28 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_28
+#set_property PACKAGE_PIN H26 [get_ports "5N7501"] ;# Bank 28 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7501"] ;# Bank 28 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_28
+#set_property PACKAGE_PIN J25 [get_ports "5N7496"] ;# Bank 28 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7496"] ;# Bank 28 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_28
+#set_property PACKAGE_PIN K23 [get_ports "5N7497"] ;# Bank 28 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7497"] ;# Bank 28 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property PACKAGE_PIN K22 [get_ports "5N7488"] ;# Bank 28 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7488"] ;# Bank 28 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property PACKAGE_PIN J22 [get_ports "5N7489"] ;# Bank 28 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7489"] ;# Bank 28 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_28
+#set_property PACKAGE_PIN J21 [get_ports "5N7484"] ;# Bank 28 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7484"] ;# Bank 28 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_28
+#set_property PACKAGE_PIN K24 [get_ports "5N7485"] ;# Bank 28 VCCO - VCC1V8 - IO_L2N_T0L_N3_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7485"] ;# Bank 28 VCCO - VCC1V8 - IO_L2N_T0L_N3_28
+#set_property PACKAGE_PIN L23 [get_ports "5N7476"] ;# Bank 28 VCCO - VCC1V8 - IO_L2P_T0L_N2_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7476"] ;# Bank 28 VCCO - VCC1V8 - IO_L2P_T0L_N2_28
+#set_property PACKAGE_PIN L22 [get_ports "5N7477"] ;# Bank 28 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7477"] ;# Bank 28 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_28
+#set_property PACKAGE_PIN L21 [get_ports "5N7472"] ;# Bank 28 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7472"] ;# Bank 28 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_28
+#Other net PACKAGE_PIN M23 - 5N7631 Bank 28 - VREF_28
+#set_property PACKAGE_PIN A9 [get_ports "4N9784"] ;# Bank 68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9784"] ;# Bank 68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property PACKAGE_PIN G13 [get_ports "4N9781"] ;# Bank 68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9781"] ;# Bank 68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property PACKAGE_PIN G11 [get_ports "4N9820"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9820"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property PACKAGE_PIN H11 [get_ports "4N9817"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9817"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property PACKAGE_PIN G9 [get_ports "4N9823"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9823"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property PACKAGE_PIN H9 [get_ports "4N9826"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9826"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property PACKAGE_PIN D7 [get_ports "4N9778"] ;# Bank 68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9778"] ;# Bank 68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property PACKAGE_PIN H14 [get_ports "VRP_68"] ;# Bank 68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_68"] ;# Bank 68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property PACKAGE_PIN K13 [get_ports "4N9759"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9759"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property PACKAGE_PIN L14 [get_ports "4N9760"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9760"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property PACKAGE_PIN J14 [get_ports "4N9755"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9755"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property PACKAGE_PIN K14 [get_ports "4N9756"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9756"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property PACKAGE_PIN J11 [get_ports "4N9771"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9771"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property PACKAGE_PIN K12 [get_ports "4N9772"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9772"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property PACKAGE_PIN L11 [get_ports "4N9767"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9767"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property PACKAGE_PIN L12 [get_ports "4N9768"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9768"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#Other net PACKAGE_PIN J12 - 4N9503 Bank 68 - VREF_68
+#set_property PACKAGE_PIN J20 [get_ports "7N10213"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10213"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property PACKAGE_PIN J19 [get_ports "7N10210"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10210"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property PACKAGE_PIN G16 [get_ports "FMC_LPC_LA09_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67
+#set_property PACKAGE_PIN D14 [get_ports "7N10403"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10403"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property PACKAGE_PIN D15 [get_ports "7N10406"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10406"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property PACKAGE_PIN F13 [get_ports "7N10612"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10612"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property PACKAGE_PIN G14 [get_ports "7N10614"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10614"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property PACKAGE_PIN E13 [get_ports "7N10207"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10207"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property PACKAGE_PIN C14 [get_ports "7N10204"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10204"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property PACKAGE_PIN C12 [get_ports "FMC_LPC_LA14_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67
+#set_property PACKAGE_PIN B13 [get_ports "7N10197"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10197"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property PACKAGE_PIN B14 [get_ports "7N10198"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10198"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property PACKAGE_PIN A14 [get_ports "7N10193"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10193"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property PACKAGE_PIN A15 [get_ports "7N10194"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10194"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property PACKAGE_PIN B15 [get_ports "7N10185"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10185"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property PACKAGE_PIN B16 [get_ports "7N10186"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10186"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property PACKAGE_PIN A16 [get_ports "7N10181"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10181"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property PACKAGE_PIN A17 [get_ports "7N10182"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10182"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#Other net PACKAGE_PIN L18 - 7N9719 Bank 67 - VREF_67
+#set_property PACKAGE_PIN AF10 [get_ports "7N10601"] ;# Bank 66 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10601"] ;# Bank 66 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property PACKAGE_PIN AC14 [get_ports "7N10603"] ;# Bank 66 VCCO - VCC1V2 - IO_T3U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10603"] ;# Bank 66 VCCO - VCC1V2 - IO_T3U_N12_66
+#set_property PACKAGE_PIN AH8 [get_ports "7N10599"] ;# Bank 66 VCCO - VCC1V2 - IO_T2U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10599"] ;# Bank 66 VCCO - VCC1V2 - IO_T2U_N12_66
+#set_property PACKAGE_PIN AJ12 [get_ports "7N10597"] ;# Bank 66 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10597"] ;# Bank 66 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_66
+#set_property PACKAGE_PIN AL13 [get_ports "7N10593"] ;# Bank 66 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10593"] ;# Bank 66 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property PACKAGE_PIN AM13 [get_ports "7N10595"] ;# Bank 66 VCCO - VCC1V2 - IO_T1U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10595"] ;# Bank 66 VCCO - VCC1V2 - IO_T1U_N12_66
+#set_property PACKAGE_PIN AP8 [get_ports "VRP_66"] ;# Bank 66 VCCO - VCC1V2 - IO_T0U_N12_VRP_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - VCC1V2 - IO_T0U_N12_VRP_66
+#set_property PACKAGE_PIN AP12 [get_ports "7N10591"] ;# Bank 66 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10591"] ;# Bank 66 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_66
+#Other net PACKAGE_PIN AB12 - 7N8282 Bank 66 - VREF_66
+#set_property PACKAGE_PIN AE19 [get_ports "6N12439"] ;# Bank 65 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12439"] ;# Bank 65 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property PACKAGE_PIN AE22 [get_ports "6N12442"] ;# Bank 65 VCCO - VCC1V2 - IO_T3U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12442"] ;# Bank 65 VCCO - VCC1V2 - IO_T3U_N12_65
+#set_property PACKAGE_PIN AF20 [get_ports "6N12436"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12436"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
+#set_property PACKAGE_PIN AH23 [get_ports "6N12433"] ;# Bank 65 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12433"] ;# Bank 65 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_65
+#set_property PACKAGE_PIN AL21 [get_ports "6N12427"] ;# Bank 65 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12427"] ;# Bank 65 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property PACKAGE_PIN AH19 [get_ports "6N12430"] ;# Bank 65 VCCO - VCC1V2 - IO_T1U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12430"] ;# Bank 65 VCCO - VCC1V2 - IO_T1U_N12_65
+#set_property PACKAGE_PIN AM20 [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V2 - IO_T0U_N12_VRP_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V2 - IO_T0U_N12_VRP_65
+#set_property PACKAGE_PIN AP20 [get_ports "6N12401"] ;# Bank 65 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12401"] ;# Bank 65 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_65
+#Other net PACKAGE_PIN AB20 - 6N11582 Bank 65 - VREF_65
+#set_property PACKAGE_PIN AA17 [get_ports "6N12707"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12707"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64
+#set_property PACKAGE_PIN AE17 [get_ports "6N12705"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12705"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64
+#set_property PACKAGE_PIN AP14 [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64
+#set_property PACKAGE_PIN AP15 [get_ports "6N12788"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12788"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64
+#set_property PACKAGE_PIN AP16 [get_ports "6N12789"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12789"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64
+#set_property PACKAGE_PIN AN14 [get_ports "6N12782"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12782"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property PACKAGE_PIN AM14 [get_ports "6N12783"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12783"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property PACKAGE_PIN AN18 [get_ports "6N12780"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12780"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64
+#set_property PACKAGE_PIN AM18 [get_ports "6N12781"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12781"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64
+#set_property PACKAGE_PIN AP13 [get_ports "6N12774"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12774"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64
+#set_property PACKAGE_PIN AN13 [get_ports "6N12775"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12775"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64
+#set_property PACKAGE_PIN AP17 [get_ports "6N12772"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12772"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64
+#set_property PACKAGE_PIN AP18 [get_ports "6N12773"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64
+#set_property IOSTANDARD LVCMOSxxn [get_ports "6N12773"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64
+#Other net PACKAGE_PIN AG16 - 6N11370 Bank 64 - VREF_64
+#Other net PACKAGE_PIN AD9 - MGT1V2 Bank 224 - MGTAVTTRCAL_R
+#Other net PACKAGE_PIN A24 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0
+#Other net PACKAGE_PIN C24 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1
+#Other net PACKAGE_PIN F26 - 53N7803 Bank 500 - PS_MIO10
+#Other net PACKAGE_PIN B26 - 53N7806 Bank 500 - PS_MIO11
+#Other net PACKAGE_PIN C27 - 53N7809 Bank 500 - PS_MIO12
+#Other net PACKAGE_PIN D27 - 53N7788 Bank 500 - PS_MIO13
+#Other net PACKAGE_PIN A27 - 53N7844 Bank 500 - PS_MIO14
+#Other net PACKAGE_PIN E27 - 53N7842 Bank 500 - PS_MIO15
+#Other net PACKAGE_PIN A28 - MIO16_I2C1_SCL Bank 500 - PS_MIO16
+#Other net PACKAGE_PIN C29 - MIO17_I2C1_SDA Bank 500 - PS_MIO17
+#Other net PACKAGE_PIN F27 - UART0_TXD_MIO18_RXD Bank 500 - PS_MIO18
+#Other net PACKAGE_PIN B28 - UART0_RXD_MIO19_TXD Bank 500 - PS_MIO19
+#Other net PACKAGE_PIN B24 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2
+#Other net PACKAGE_PIN E29 - UART1_RXD_MIO20_TXD Bank 500 - PS_MIO20
+#Other net PACKAGE_PIN C28 - UART1_TXD_MIO21_RXD Bank 500 - PS_MIO21
+#Other net PACKAGE_PIN F28 - 53N7824 Bank 500 - PS_MIO22
+#Other net PACKAGE_PIN B29 - 53N7822 Bank 500 - PS_MIO23
+#Other net PACKAGE_PIN E28 - MIO24_CAN_TX Bank 500 - PS_MIO24
+#Other net PACKAGE_PIN D29 - MIO25_CAN_RX Bank 500 - PS_MIO25
+#Other net PACKAGE_PIN E25 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3
+#Other net PACKAGE_PIN A25 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4
+#Other net PACKAGE_PIN D25 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5
+#Other net PACKAGE_PIN A26 - 53N6816 Bank 500 - PS_MIO6
+#Other net PACKAGE_PIN B25 - 53N7794 Bank 500 - PS_MIO7
+#Other net PACKAGE_PIN D26 - 53N7797 Bank 500 - PS_MIO8
+#Other net PACKAGE_PIN C26 - 53N7800 Bank 500 - PS_MIO9
+#Other net PACKAGE_PIN AA25 - PS_SYSMON_AVCC Bank 500 - VCC_PSADC
+#Other net PACKAGE_PIN AA24 - PS_SYSMON_AGND Bank 500 - GND_PSADC
+#Other net PACKAGE_PIN A29 - 53N7791 Bank 501 - PS_MIO26
+#Other net PACKAGE_PIN A30 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27
+#Other net PACKAGE_PIN A31 - MIO28_DP_HPD Bank 501 - PS_MIO28
+#Other net PACKAGE_PIN A32 - MIO29_DP_OE Bank 501 - PS_MIO29
+#Other net PACKAGE_PIN A33 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30
+#Other net PACKAGE_PIN B30 - 53N7736 Bank 501 - PS_MIO31
+#Other net PACKAGE_PIN B31 - 53N7739 Bank 501 - PS_MIO32
+#Other net PACKAGE_PIN B33 - 53N7742 Bank 501 - PS_MIO33
+#Other net PACKAGE_PIN B34 - 53N7745 Bank 501 - PS_MIO34
+#Other net PACKAGE_PIN C31 - 53N7748 Bank 501 - PS_MIO35
+#Other net PACKAGE_PIN C32 - 53N7751 Bank 501 - PS_MIO36
+#Other net PACKAGE_PIN C33 - 53N7754 Bank 501 - PS_MIO37
+#Other net PACKAGE_PIN C34 - 53N7768 Bank 501 - PS_MIO38
+#Other net PACKAGE_PIN D30 - 53N7771 Bank 501 - PS_MIO39
+#Other net PACKAGE_PIN D31 - 53N7773 Bank 501 - PS_MIO40
+#Other net PACKAGE_PIN D32 - 53N7775 Bank 501 - PS_MIO41
+#Other net PACKAGE_PIN D34 - 53N7777 Bank 501 - PS_MIO42
+#Other net PACKAGE_PIN E30 - 53N6798 Bank 501 - PS_MIO43
+#Other net PACKAGE_PIN E32 - 53N7783 Bank 501 - PS_MIO44
+#Other net PACKAGE_PIN E33 - MIO45_SDIO_DETECT Bank 501 - PS_MIO45
+#Other net PACKAGE_PIN E34 - MIO46_SDIO_DAT0_R Bank 501 - PS_MIO46
+#Other net PACKAGE_PIN F30 - MIO47_SDIO_DAT1_R Bank 501 - PS_MIO47
+#Other net PACKAGE_PIN F31 - MIO48_SDIO_DAT2_R Bank 501 - PS_MIO48
+#Other net PACKAGE_PIN F32 - MIO49_SDIO_DAT3_R Bank 501 - PS_MIO49
+#Other net PACKAGE_PIN F33 - MIO50_SDIO_CMD_R Bank 501 - PS_MIO50
+#Other net PACKAGE_PIN F34 - MIO51_SDIO_CLK_R Bank 501 - PS_MIO51
+#Other net PACKAGE_PIN G29 - MIO52_USB_CLK Bank 502 - PS_MIO52
+#Other net PACKAGE_PIN G30 - MIO53_USB_DIR Bank 502 - PS_MIO53
+#Other net PACKAGE_PIN G31 - MIO54_USB_DATA2_R Bank 502 - PS_MIO54
+#Other net PACKAGE_PIN G33 - MIO55_USB_NXT Bank 502 - PS_MIO55
+#Other net PACKAGE_PIN G34 - MIO56_USB_DATA0_R Bank 502 - PS_MIO56
+#Other net PACKAGE_PIN H29 - MIO57_USB_DATA1_R Bank 502 - PS_MIO57
+#Other net PACKAGE_PIN H31 - MIO58_USB_STP_R Bank 502 - PS_MIO58
+#Other net PACKAGE_PIN H32 - MIO59_USB_DATA3_R Bank 502 - PS_MIO59
+#Other net PACKAGE_PIN H33 - MIO60_USB_DATA4_R Bank 502 - PS_MIO60
+#Other net PACKAGE_PIN H34 - MIO61_USB_DATA5_R Bank 502 - PS_MIO61
+#Other net PACKAGE_PIN J29 - MIO62_USB_DATA6_R Bank 502 - PS_MIO62
+#Other net PACKAGE_PIN J30 - MIO63_USB_DATA7_R Bank 502 - PS_MIO63
+#Other net PACKAGE_PIN J31 - MIO64_ENET_TX_CLK Bank 502 - PS_MIO64
+#Other net PACKAGE_PIN J32 - MIO65_ENET_TX_D0 Bank 502 - PS_MIO65
+#Other net PACKAGE_PIN J34 - MIO66_ENET_TX_D1 Bank 502 - PS_MIO66
+#Other net PACKAGE_PIN K28 - MIO67_ENET_TX_D2 Bank 502 - PS_MIO67
+#Other net PACKAGE_PIN K29 - MIO68_ENET_TX_D3 Bank 502 - PS_MIO68
+#Other net PACKAGE_PIN K30 - MIO69_ENET_TX_CTRL Bank 502 - PS_MIO69
+#Other net PACKAGE_PIN K31 - MIO70_ENET_RX_CLK Bank 502 - PS_MIO70
+#Other net PACKAGE_PIN K32 - MIO71_ENET_RX_D0 Bank 502 - PS_MIO71
+#Other net PACKAGE_PIN K33 - MIO72_ENET_RX_D1 Bank 502 - PS_MIO72
+#Other net PACKAGE_PIN K34 - MIO73_ENET_RX_D2 Bank 502 - PS_MIO73
+#Other net PACKAGE_PIN L29 - MIO74_ENET_RX_D3 Bank 502 - PS_MIO74
+#Other net PACKAGE_PIN L30 - MIO75_ENET_RX_CTRL Bank 502 - PS_MIO75
+#Other net PACKAGE_PIN L33 - MIO76_ENET_MDC Bank 502 - PS_MIO76
+#Other net PACKAGE_PIN L34 - MIO77_ENET_MDIO Bank 502 - PS_MIO77
+#Other net PACKAGE_PIN N24 - PS_DONE Bank 503 - PS_DONE
+#Other net PACKAGE_PIN T25 - PS_ERR_OUT Bank 503 - PS_ERROR_OUT
+#Other net PACKAGE_PIN R25 - PS_ERR_STATUS Bank 503 - PS_ERROR_STATUS
+#Other net PACKAGE_PIN P24 - PS_INIT_B Bank 503 - PS_INIT_B
+#Other net PACKAGE_PIN K27 - FPGA_TCK Bank 503 - PS_JTAG_TCK
+#Other net PACKAGE_PIN J27 - FPGA_TDI Bank 503 - PS_JTAG_TDI
+#Other net PACKAGE_PIN G28 - FPGA_TDO_FMC_TDI Bank 503 - PS_JTAG_TDO
+#Other net PACKAGE_PIN H28 - FPGA_TMS Bank 503 - PS_JTAG_TMS
+#Other net PACKAGE_PIN H27 - PS_MODE0 Bank 503 - PS_MODE0
+#Other net PACKAGE_PIN J26 - PS_MODE1 Bank 503 - PS_MODE1
+#Other net PACKAGE_PIN K26 - PS_MODE2 Bank 503 - PS_MODE2
+#Other net PACKAGE_PIN K25 - PS_MODE3 Bank 503 - PS_MODE3
+#Other net PACKAGE_PIN M25 - PS_PADI Bank 503 - PS_PADI
+#Other net PACKAGE_PIN L25 - PS_PADO Bank 503 - PS_PADO
+#Other net PACKAGE_PIN M24 - PS_POR_B Bank 503 - PS_POR_B
+#Other net PACKAGE_PIN T24 - PS_PROG_B Bank 503 - PS_PROG_B
+#Other net PACKAGE_PIN R24 - PS_REF_CLK Bank 503 - PS_REF_CLK
+#Other net PACKAGE_PIN P25 - PS_SRST_B Bank 503 - PS_SRST_B
+#Other net PACKAGE_PIN AN34 - DDR4_A0 Bank 504 - PS_DDR_A0
+#Other net PACKAGE_PIN AM34 - DDR4_A1 Bank 504 - PS_DDR_A1
+#Other net PACKAGE_PIN AG31 - DDR4_A10 Bank 504 - PS_DDR_A10
+#Other net PACKAGE_PIN AF31 - DDR4_A11 Bank 504 - PS_DDR_A11
+#Other net PACKAGE_PIN AG30 - DDR4_A12 Bank 504 - PS_DDR_A12
+#Other net PACKAGE_PIN AF30 - DDR4_A13 Bank 504 - PS_DDR_A13
+#Other net PACKAGE_PIN AG29 - DDR4_A14_WE_B Bank 504 - PS_DDR_A14
+#Other net PACKAGE_PIN AG28 - DDR4_A15_CAS_B Bank 504 - PS_DDR_A15
+#Other net PACKAGE_PIN AF28 - DDR4_A16_RAS_B Bank 504 - PS_DDR_A16
+#Other net PACKAGE_PIN AF26 - 68N6692 Bank 504 - PS_DDR_A17
+#Other net PACKAGE_PIN AM33 - DDR4_A2 Bank 504 - PS_DDR_A2
+#Other net PACKAGE_PIN AL34 - DDR4_A3 Bank 504 - PS_DDR_A3
+#Other net PACKAGE_PIN AL33 - DDR4_A4 Bank 504 - PS_DDR_A4
+#Other net PACKAGE_PIN AK33 - DDR4_A5 Bank 504 - PS_DDR_A5
+#Other net PACKAGE_PIN AK30 - DDR4_A6 Bank 504 - PS_DDR_A6
+#Other net PACKAGE_PIN AJ30 - DDR4_A7 Bank 504 - PS_DDR_A7
+#Other net PACKAGE_PIN AJ31 - DDR4_A8 Bank 504 - PS_DDR_A8
+#Other net PACKAGE_PIN AH31 - DDR4_A9 Bank 504 - PS_DDR_A9
+#Other net PACKAGE_PIN AE25 - DDR4_ACT_B Bank 504 - PS_DDR_ACT_N
+#Other net PACKAGE_PIN AB26 - DDR4_ALERT_B Bank 504 - PS_DDR_ALERT_N
+#Other net PACKAGE_PIN AE27 - DDR4_BA0 Bank 504 - PS_DDR_BA0
+#Other net PACKAGE_PIN AE28 - DDR4_BA1 Bank 504 - PS_DDR_BA1
+#Other net PACKAGE_PIN AD27 - DDR4_BG0 Bank 504 - PS_DDR_BG0
+#Other net PACKAGE_PIN AF27 - 68N7393 Bank 504 - PS_DDR_BG1
+#Other net PACKAGE_PIN AL31 - DDR4_CK_T Bank 504 - PS_DDR_CK0
+#Other net PACKAGE_PIN AL30 - 68N7399 Bank 504 - PS_DDR_CK1
+#Other net PACKAGE_PIN AN33 - DDR4_CKE Bank 504 - PS_DDR_CKE0
+#Other net PACKAGE_PIN AH32 - 68N7405 Bank 504 - PS_DDR_CKE1
+#Other net PACKAGE_PIN AN32 - DDR4_CK_C Bank 504 - PS_DDR_CK_N0
+#Other net PACKAGE_PIN AL32 - 68N7402 Bank 504 - PS_DDR_CK_N1
+#Other net PACKAGE_PIN AP33 - DDR4_CS_B Bank 504 - PS_DDR_CS_N0
+#Other net PACKAGE_PIN AK32 - 68N7396 Bank 504 - PS_DDR_CS_N1
+#Other net PACKAGE_PIN AN24 - DDR4_DM0 Bank 504 - PS_DDR_DM0
+#Other net PACKAGE_PIN AM29 - DDR4_DM1 Bank 504 - PS_DDR_DM1
+#Other net PACKAGE_PIN AH24 - DDR4_DM2 Bank 504 - PS_DDR_DM2
+#Other net PACKAGE_PIN AJ29 - DDR4_DM3 Bank 504 - PS_DDR_DM3
+#Other net PACKAGE_PIN AD29 - DDR4_DM4 Bank 504 - PS_DDR_DM4
+#Other net PACKAGE_PIN Y29 - DDR4_DM5 Bank 504 - PS_DDR_DM5
+#Other net PACKAGE_PIN AC32 - DDR4_DM6 Bank 504 - PS_DDR_DM6
+#Other net PACKAGE_PIN Y32 - DDR4_DM7 Bank 504 - PS_DDR_DM7
+#Other net PACKAGE_PIN AF34 - 68N7353 Bank 504 - PS_DDR_DM8
+#Other net PACKAGE_PIN AP27 - DDR4_DQ0 Bank 504 - PS_DDR_DQ0
+#Other net PACKAGE_PIN AP25 - DDR4_DQ1 Bank 504 - PS_DDR_DQ1
+#Other net PACKAGE_PIN AP29 - DDR4_DQ10 Bank 504 - PS_DDR_DQ10
+#Other net PACKAGE_PIN AP28 - DDR4_DQ11 Bank 504 - PS_DDR_DQ11
+#Other net PACKAGE_PIN AM31 - DDR4_DQ12 Bank 504 - PS_DDR_DQ12
+#Other net PACKAGE_PIN AP31 - DDR4_DQ13 Bank 504 - PS_DDR_DQ13
+#Other net PACKAGE_PIN AN31 - DDR4_DQ14 Bank 504 - PS_DDR_DQ14
+#Other net PACKAGE_PIN AM30 - DDR4_DQ15 Bank 504 - PS_DDR_DQ15
+#Other net PACKAGE_PIN AF25 - DDR4_DQ16 Bank 504 - PS_DDR_DQ16
+#Other net PACKAGE_PIN AG25 - DDR4_DQ17 Bank 504 - PS_DDR_DQ17
+#Other net PACKAGE_PIN AG26 - DDR4_DQ18 Bank 504 - PS_DDR_DQ18
+#Other net PACKAGE_PIN AJ25 - DDR4_DQ19 Bank 504 - PS_DDR_DQ19
+#Other net PACKAGE_PIN AP26 - DDR4_DQ2 Bank 504 - PS_DDR_DQ2
+#Other net PACKAGE_PIN AG24 - DDR4_DQ20 Bank 504 - PS_DDR_DQ20
+#Other net PACKAGE_PIN AK25 - DDR4_DQ21 Bank 504 - PS_DDR_DQ21
+#Other net PACKAGE_PIN AJ24 - DDR4_DQ22 Bank 504 - PS_DDR_DQ22
+#Other net PACKAGE_PIN AK24 - DDR4_DQ23 Bank 504 - PS_DDR_DQ23
+#Other net PACKAGE_PIN AH28 - DDR4_DQ24 Bank 504 - PS_DDR_DQ24
+#Other net PACKAGE_PIN AH27 - DDR4_DQ25 Bank 504 - PS_DDR_DQ25
+#Other net PACKAGE_PIN AJ27 - DDR4_DQ26 Bank 504 - PS_DDR_DQ26
+#Other net PACKAGE_PIN AK27 - DDR4_DQ27 Bank 504 - PS_DDR_DQ27
+#Other net PACKAGE_PIN AL26 - DDR4_DQ28 Bank 504 - PS_DDR_DQ28
+#Other net PACKAGE_PIN AL27 - DDR4_DQ29 Bank 504 - PS_DDR_DQ29
+#Other net PACKAGE_PIN AM26 - DDR4_DQ3 Bank 504 - PS_DDR_DQ3
+#Other net PACKAGE_PIN AH29 - DDR4_DQ30 Bank 504 - PS_DDR_DQ30
+#Other net PACKAGE_PIN AL28 - DDR4_DQ31 Bank 504 - PS_DDR_DQ31
+#Other net PACKAGE_PIN AB29 - DDR4_DQ32 Bank 504 - PS_DDR_DQ32
+#Other net PACKAGE_PIN AB30 - DDR4_DQ33 Bank 504 - PS_DDR_DQ33
+#Other net PACKAGE_PIN AC29 - DDR4_DQ34 Bank 504 - PS_DDR_DQ34
+#Other net PACKAGE_PIN AD32 - DDR4_DQ35 Bank 504 - PS_DDR_DQ35
+#Other net PACKAGE_PIN AC31 - DDR4_DQ36 Bank 504 - PS_DDR_DQ36
+#Other net PACKAGE_PIN AE30 - DDR4_DQ37 Bank 504 - PS_DDR_DQ37
+#Other net PACKAGE_PIN AC28 - DDR4_DQ38 Bank 504 - PS_DDR_DQ38
+#Other net PACKAGE_PIN AE29 - DDR4_DQ39 Bank 504 - PS_DDR_DQ39
+#Other net PACKAGE_PIN AP24 - DDR4_DQ4 Bank 504 - PS_DDR_DQ4
+#Other net PACKAGE_PIN AC27 - DDR4_DQ40 Bank 504 - PS_DDR_DQ40
+#Other net PACKAGE_PIN AA27 - DDR4_DQ41 Bank 504 - PS_DDR_DQ41
+#Other net PACKAGE_PIN AA28 - DDR4_DQ42 Bank 504 - PS_DDR_DQ42
+#Other net PACKAGE_PIN AB28 - DDR4_DQ43 Bank 504 - PS_DDR_DQ43
+#Other net PACKAGE_PIN W27 - DDR4_DQ44 Bank 504 - PS_DDR_DQ44
+#Other net PACKAGE_PIN W29 - DDR4_DQ45 Bank 504 - PS_DDR_DQ45
+#Other net PACKAGE_PIN W28 - DDR4_DQ46 Bank 504 - PS_DDR_DQ46
+#Other net PACKAGE_PIN V27 - DDR4_DQ47 Bank 504 - PS_DDR_DQ47
+#Other net PACKAGE_PIN AA32 - DDR4_DQ48 Bank 504 - PS_DDR_DQ48
+#Other net PACKAGE_PIN AA33 - DDR4_DQ49 Bank 504 - PS_DDR_DQ49
+#Other net PACKAGE_PIN AL25 - DDR4_DQ5 Bank 504 - PS_DDR_DQ5
+#Other net PACKAGE_PIN AA34 - DDR4_DQ50 Bank 504 - PS_DDR_DQ50
+#Other net PACKAGE_PIN AE34 - DDR4_DQ51 Bank 504 - PS_DDR_DQ51
+#Other net PACKAGE_PIN AD34 - DDR4_DQ52 Bank 504 - PS_DDR_DQ52
+#Other net PACKAGE_PIN AB31 - DDR4_DQ53 Bank 504 - PS_DDR_DQ53
+#Other net PACKAGE_PIN AC34 - DDR4_DQ54 Bank 504 - PS_DDR_DQ54
+#Other net PACKAGE_PIN AC33 - DDR4_DQ55 Bank 504 - PS_DDR_DQ55
+#Other net PACKAGE_PIN AA30 - DDR4_DQ56 Bank 504 - PS_DDR_DQ56
+#Other net PACKAGE_PIN Y30 - DDR4_DQ57 Bank 504 - PS_DDR_DQ57
+#Other net PACKAGE_PIN AA31 - DDR4_DQ58 Bank 504 - PS_DDR_DQ58
+#Other net PACKAGE_PIN W30 - DDR4_DQ59 Bank 504 - PS_DDR_DQ59
+#Other net PACKAGE_PIN AM25 - DDR4_DQ6 Bank 504 - PS_DDR_DQ6
+#Other net PACKAGE_PIN Y33 - DDR4_DQ60 Bank 504 - PS_DDR_DQ60
+#Other net PACKAGE_PIN W33 - DDR4_DQ61 Bank 504 - PS_DDR_DQ61
+#Other net PACKAGE_PIN W34 - DDR4_DQ62 Bank 504 - PS_DDR_DQ62
+#Other net PACKAGE_PIN Y34 - DDR4_DQ63 Bank 504 - PS_DDR_DQ63
+#Other net PACKAGE_PIN AF32 - 68N7356 Bank 504 - PS_DDR_DQ64
+#Other net PACKAGE_PIN AE32 - 68N7359 Bank 504 - PS_DDR_DQ65
+#Other net PACKAGE_PIN AH33 - 68N7362 Bank 504 - PS_DDR_DQ66
+#Other net PACKAGE_PIN AE33 - 68N7364 Bank 504 - PS_DDR_DQ67
+#Other net PACKAGE_PIN AF33 - 68N7368 Bank 504 - PS_DDR_DQ68
+#Other net PACKAGE_PIN AH34 - 68N7370 Bank 504 - PS_DDR_DQ69
+#Other net PACKAGE_PIN AM24 - DDR4_DQ7 Bank 504 - PS_DDR_DQ7
+#Other net PACKAGE_PIN AJ34 - 68N7374 Bank 504 - PS_DDR_DQ70
+#Other net PACKAGE_PIN AK34 - 68N7376 Bank 504 - PS_DDR_DQ71
+#Other net PACKAGE_PIN AM28 - DDR4_DQ8 Bank 504 - PS_DDR_DQ8
+#Other net PACKAGE_PIN AN28 - DDR4_DQ9 Bank 504 - PS_DDR_DQ9
+#Other net PACKAGE_PIN AN27 - DDR4_DQS0_C Bank 504 - PS_DDR_DQS_N0
+#Other net PACKAGE_PIN AP30 - DDR4_DQS1_C Bank 504 - PS_DDR_DQS_N1
+#Other net PACKAGE_PIN AJ26 - DDR4_DQS2_C Bank 504 - PS_DDR_DQS_N2
+#Other net PACKAGE_PIN AK29 - DDR4_DQS3_C Bank 504 - PS_DDR_DQS_N3
+#Other net PACKAGE_PIN AD31 - DDR4_DQS4_C Bank 504 - PS_DDR_DQS_N4
+#Other net PACKAGE_PIN Y28 - DDR4_DQS5_C Bank 504 - PS_DDR_DQS_N5
+#Other net PACKAGE_PIN AB34 - DDR4_DQS6_C Bank 504 - PS_DDR_DQS_N6
+#Other net PACKAGE_PIN W32 - DDR4_DQS7_C Bank 504 - PS_DDR_DQS_N7
+#Other net PACKAGE_PIN AG34 - 68N7350 Bank 504 - PS_DDR_DQS_N8
+#Other net PACKAGE_PIN AN26 - DDR4_DQS0_T Bank 504 - PS_DDR_DQS_P0
+#Other net PACKAGE_PIN AN29 - DDR4_DQS1_T Bank 504 - PS_DDR_DQS_P1
+#Other net PACKAGE_PIN AH26 - DDR4_DQS2_T Bank 504 - PS_DDR_DQS_P2
+#Other net PACKAGE_PIN AK28 - DDR4_DQS3_T Bank 504 - PS_DDR_DQS_P3
+#Other net PACKAGE_PIN AD30 - DDR4_DQS4_T Bank 504 - PS_DDR_DQS_P4
+#Other net PACKAGE_PIN Y27 - DDR4_DQS5_T Bank 504 - PS_DDR_DQS_P5
+#Other net PACKAGE_PIN AB33 - DDR4_DQS6_T Bank 504 - PS_DDR_DQS_P6
+#Other net PACKAGE_PIN W31 - DDR4_DQS7_T Bank 504 - PS_DDR_DQS_P7
+#Other net PACKAGE_PIN AG33 - 68N7347 Bank 504 - PS_DDR_DQS_P8
+#Other net PACKAGE_PIN AP32 - DDR4_ODT Bank 504 - PS_DDR_ODT0
+#Other net PACKAGE_PIN AJ32 - 68N7408 Bank 504 - PS_DDR_ODT1
+#Other net PACKAGE_PIN AA26 - DDR4_PAR Bank 504 - PS_DDR_PARITY
+#Other net PACKAGE_PIN AD26 - DDR4_RESET_B Bank 504 - PS_DDR_RAM_RST_N
+#Other net PACKAGE_PIN AC26 - SODIMM_ZQ Bank 504 - PS_DDR_ZQ
+#Other net PACKAGE_PIN U34 - 69N6524 Bank 505 - PS_MGTRRXN0_505
+#Other net PACKAGE_PIN T32 - 69N6530 Bank 505 - PS_MGTRRXN1_505
+#Other net PACKAGE_PIN R34 - GT2_USB0_RX_N Bank 505 - PS_MGTRRXN2_505
+#Other net PACKAGE_PIN N34 - GT3_SATA1_RX_N Bank 505 - PS_MGTRRXN3_505
+#Other net PACKAGE_PIN U33 - 69N6521 Bank 505 - PS_MGTRRXP0_505
+#Other net PACKAGE_PIN T31 - 69N6527 Bank 505 - PS_MGTRRXP1_505
+#Other net PACKAGE_PIN R33 - GT2_USB0_RX_P Bank 505 - PS_MGTRRXP2_505
+#Other net PACKAGE_PIN N33 - GT3_SATA1_RX_P Bank 505 - PS_MGTRRXP3_505
+#Other net PACKAGE_PIN U30 - GT0_DP_TX_N Bank 505 - PS_MGTRTXN0_505
+#Other net PACKAGE_PIN R30 - GT1_DP_TX_N Bank 505 - PS_MGTRTXN1_505
+#Other net PACKAGE_PIN P32 - GT2_USB0_TX_N Bank 505 - PS_MGTRTXN2_505
+#Other net PACKAGE_PIN N30 - GT3_SATA1_TX_N Bank 505 - PS_MGTRTXN3_505
+#Other net PACKAGE_PIN U29 - GT0_DP_TX_P Bank 505 - PS_MGTRTXP0_505
+#Other net PACKAGE_PIN R29 - GT1_DP_TX_P Bank 505 - PS_MGTRTXP1_505
+#Other net PACKAGE_PIN P31 - GT2_USB0_TX_P Bank 505 - PS_MGTRTXP2_505
+#Other net PACKAGE_PIN N29 - GT3_SATA1_TX_P Bank 505 - PS_MGTRTXP3_505
+#Other net PACKAGE_PIN T28 - 69N6536 Bank 505 - PS_MGTREFCLK0N_505
+#Other net PACKAGE_PIN T27 - 69N6533 Bank 505 - PS_MGTREFCLK0P_505
+#Other net PACKAGE_PIN P28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505
+#Other net PACKAGE_PIN P27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505
+#Other net PACKAGE_PIN M28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505
+#Other net PACKAGE_PIN M27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505
+#Other net PACKAGE_PIN M32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505
+#Other net PACKAGE_PIN M31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505
+#Other net PACKAGE_PIN U31 - 69N5804 Bank 505 - PS_MGTRREF_505
+#Other net PACKAGE_PIN AE16 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AH15 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AJ18 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AF19 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AG22 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AK21 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AF9 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN AG12 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN AK11 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN E21 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN F24 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN H20 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN D13 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN E16 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN H15 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN F9 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN G12 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN K11 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN J8 - VCC3V3 Bank 87 - VCCO_87
+#Other net PACKAGE_PIN N10 - VCC3V3 Bank 87 - VCCO_87
+#Other net PACKAGE_PIN D3 - VCC3V3 Bank 88 - VCCO_88
+#Other net PACKAGE_PIN E6 - VCC3V3 Bank 88 - VCCO_88
+#Other net PACKAGE_PIN C25 - VCC1V8 Bank 500 - VCCO_PSIO0_500
+#Other net PACKAGE_PIN D28 - VCC1V8 Bank 500 - VCCO_PSIO0_500
+#Other net PACKAGE_PIN B32 - VCC1V8 Bank 501 - VCCO_PSIO1_501
+#Other net PACKAGE_PIN E31 - VCC1V8 Bank 501 - VCCO_PSIO1_501
+#Other net PACKAGE_PIN H30 - VCC1V8 Bank 502 - VCCO_PSIO2_502
+#Other net PACKAGE_PIN J33 - VCC1V8 Bank 502 - VCCO_PSIO2_502
+#Other net PACKAGE_PIN G27 - VCC1V8 Bank 503 - VCCO_PSIO3_503
+#Other net PACKAGE_PIN N25 - VCC1V8 Bank 503 - VCCO_PSIO3_503
+#Other net PACKAGE_PIN AE26 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AE31 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AG27 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AG32 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AJ28 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AJ33 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AL29 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN A1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN A34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN A4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN E11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN E26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K6 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AB10 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AC8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN R8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN T10 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN U8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN W8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AB6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AD6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AF6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AH6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AK6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AM6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AP6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN M6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN P6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN T6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN V6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN Y6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN V10 - MGT1V8 Bank 999 - MGTVCCAUX_R
+#Other net PACKAGE_PIN Y10 - MGT1V8 Bank 999 - MGTVCCAUX_R
+#Other net PACKAGE_PIN N27 - MGTRAVCC Bank 999 - PS_MGTRAVCC
+#Other net PACKAGE_PIN R27 - MGTRAVCC Bank 999 - PS_MGTRAVCC
+#Other net PACKAGE_PIN N31 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN P29 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN T29 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN P23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN R23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN U23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN V23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN N22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN R22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN T22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN U22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN R12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN T12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN V12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN W12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN M15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N18 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W18 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN T13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN U13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN V13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN Y13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN V26 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN W25 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN W26 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN Y25 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN Y23 - VCC_PSBATT Bank 999 - VCC_PSBATT
+#Other net PACKAGE_PIN U25 - VCCPSDDRPLL Bank 999 - VCC_PSDDR_PLL
+#Other net PACKAGE_PIN V25 - VCCPSDDRPLL Bank 999 - VCC_PSDDR_PLL
+#Other net PACKAGE_PIN AA23 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB21 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB22 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB23 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB24 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AC21 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AC22 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB25 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AC24 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AC25 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AA22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN V22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN W21 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN W22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN Y21 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN Y22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN V24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN W24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN Y24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN AD21 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD22 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD23 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD24 - VCCINT_VCU Bank 999 - VCCINT_VCU
+
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+set_property PACKAGE_PIN G8 [get_ports PMOD0_0]
+set_property PACKAGE_PIN H8 [get_ports PMOD0_1]
+set_property PACKAGE_PIN G7 [get_ports PMOD0_2]
+set_property PACKAGE_PIN H7 [get_ports PMOD0_3]
+set_property PACKAGE_PIN G6 [get_ports PMOD0_4]
+set_property PACKAGE_PIN H6 [get_ports PMOD0_5]
+set_property PACKAGE_PIN J6 [get_ports PMOD0_6]
+set_property PACKAGE_PIN J7 [get_ports PMOD0_7]
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
+#set_property PACKAGE_PIN J9 [get_ports PMOD1_0]
+#set_property PACKAGE_PIN K9 [get_ports PMOD1_1]
+#set_property PACKAGE_PIN K8 [get_ports PMOD1_2]
+#set_property PACKAGE_PIN L8 [get_ports PMOD1_3]
+#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
+#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
+#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
+#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
+
+#set_property PULLUP true [get_ports PMOD1_7]
+#set_property PULLUP true [get_ports PMOD1_6]
+#set_property PULLUP true [get_ports PMOD1_5]
+#set_property PULLUP true [get_ports PMOD1_4]
+#set_property PULLUP true [get_ports PMOD1_3]
+#set_property PULLUP true [get_ports PMOD1_2]
+#set_property PULLUP true [get_ports PMOD1_1]
+#set_property PULLUP true [get_ports PMOD1_0]
+
+
+#PMODA pin0 to FTCLK
+#set_property PACKAGE_PIN K9 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+#set_property PACKAGE_PIN L8 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+#set_property PACKAGE_PIN J9 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+#set_property PACKAGE_PIN K8 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+#set_property PACKAGE_PIN G8 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+#set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+#set_property PACKAGE_PIN D5 [get_ports {P0[0]}]
+# LED1 to P0[1]
+#set_property PACKAGE_PIN D6 [get_ports {P0[1]}]
+# LED2 to P0[2]
+#set_property PACKAGE_PIN A5 [get_ports {P0[2]}]
+# LED3 to P0[3]
+#set_property PACKAGE_PIN B5 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+#set_property PACKAGE_PIN B4 [get_ports NRST]
+
+# CLK125MHz (need dvider)
+#set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN F23 [get_ports XTAL1]
+
+
+## auto mapped - to remap
+#set_property PACKAGE_PIN C4 [get_ports {P0[10]}]
+#set_property PACKAGE_PIN C3 [get_ports {P0[11]}]
+#set_property PACKAGE_PIN B3 [get_ports {P0[12]}]
+#set_property PACKAGE_PIN D2 [get_ports {P0[13]}]
+#set_property PACKAGE_PIN C2 [get_ports {P0[14]}]
+#set_property PACKAGE_PIN E3 [get_ports {P0[15]}]
+#set_property PACKAGE_PIN F6 [get_ports {P0[4]}]
+#set_property PACKAGE_PIN E5 [get_ports {P0[5]}]
+#set_property PACKAGE_PIN F5 [get_ports {P0[6]}]
+#set_property PACKAGE_PIN F4 [get_ports {P0[7]}]
+#set_property PACKAGE_PIN E4 [get_ports {P0[8]}]
+#set_property PACKAGE_PIN D4 [get_ports {P0[9]}]
+#set_property PACKAGE_PIN M10 [get_ports {P1[10]}]
+#set_property PACKAGE_PIN L10 [get_ports {P1[11]}]
+#set_property PACKAGE_PIN M9 [get_ports {P1[12]}]
+#set_property PACKAGE_PIN M8 [get_ports {P1[13]}]
+#set_property PACKAGE_PIN N11 [get_ports {P1[14]}]
+#set_property PACKAGE_PIN M11 [get_ports {P1[15]}]
+#set_property PACKAGE_PIN H8 [get_ports {P1[4]}]
+#set_property PACKAGE_PIN G7 [get_ports {P1[5]}]
+#set_property PACKAGE_PIN H6 [get_ports {P1[6]}]
+#set_property PACKAGE_PIN G6 [get_ports {P1[7]}]
+#set_property PACKAGE_PIN J7 [get_ports {P1[8]}]
+#set_property PACKAGE_PIN J6 [get_ports {P1[9]}]
+#set_property PACKAGE_PIN E2 [get_ports VDD]
+#set_property PACKAGE_PIN A3 [get_ports VDDIO]
+#set_property PACKAGE_PIN A2 [get_ports VSS]
+#set_property PACKAGE_PIN C1 [get_ports VSSIO]
+#set_property PACKAGE_PIN B1 [get_ports XTAL2]
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7e6b0c29e7c2584df999ce9a0bc5b3cb502f4185
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top nanosoc_chip -part xczu7ev-ffvc1156-2-e
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..fe6eb50301a0e98b47f0d17b9ca18580479e66f7
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports xtal_clk_i]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports swdclk_i]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
new file mode 100644
index 0000000000000000000000000000000000000000..d0b75b39580ddb49af40fd737ded8ca4e2a32c1e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
@@ -0,0 +1,29 @@
+A
+A 0
+R
+R
+A
+A
+A
+a 10000000
+r
+r
+a 20000000
+r
+r
+a 30000000
+r
+r
+a 40006000
+r
+r
+r
+r
+a 30000200
+z 400
+A
+C 201
+
+ A
+X
+!
diff --git a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..9254704ac7aadf747555a32559438f5d205e1db2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
@@ -0,0 +1,555 @@
+#-----------------------------------------------------------------------------
+# customised simulation makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Flynn (d.w.flynn@soton.ac.uk)
+#
+# Copyright � 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M0/Cortex-M0+ System Design Kit simulation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Name of test directory (e.g. hello, dhry)
+# TESTNAME must be specified on the make command line
+TESTNAME =
+
+# List of all tests (this is used when running 'make all/clean')
+TEST_LIST = hello dhry sleep_demo interrupt_demo dualtimer_demo \
+ self_reset_demo watchdog_demo rtx_demo gpio_tests timer_tests \
+ uart_tests debug_tests default_slaves_tests dma_tests \
+ gpio_driver_tests uart_driver_tests timer_driver_tests apb_mux_tests \
+ memory_tests romtable_tests
+
+# Default to DS-5 tool-chain
+TOOL_CHAIN = ds5
+
+# Choose the core instantiated, can be either
+# - CORTEX_M0PLUS (Cortex-M0+)
+# - CORTEX_M0 (Cortex-M0)
+# - CORTEX_M0_DS (Cortex-M0 DesignStart version)
+# Note: for all processors, make sure that the __MPU_PRESENT variable in the header file agrees with the setting made in
+# the processor configuration (refer to Section 4.3.3 of the Example System Guide). The header file is either:
+# ../../../software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
+# or
+# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h
+# to match the CPU_PRODUCT selected
+# Note: for the M0+ processor, make sure that the __VTOR_PRESENT variable in the header file agrees with the setting made in
+# the processor configuration (refer to Section 4.3.3 of the Example System Guide). The header file is:
+# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h
+#DF#CPU_PRODUCT = CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Select Verilog Command File based on CPU type
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ # For Cortex-M0+ product users
+ TBENCH_VC = ../verilog/tbench_M0P.vc
+endif
+
+# Select Verilog Command File based on CPU type
+ifeq ($(CPU_PRODUCT),CORTEX_M0)
+ # For Cortex-M0 product users
+ TBENCH_VC = ../verilog/tbench_M0.vc
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0_DS)
+ # For Cortex-M0 DesignStart users
+ TBENCH_VC = ../verilog/tbench_M0_DS.vc
+endif
+
+
+
+# Simulator type (mti/vcs/nc)
+SIMULATOR = mti
+
+# MTI option
+#DF#MTI_OPTIONS = -novopt
+MTI_OPTIONS =
+MTI_VC_OPTIONS = -f $(TBENCH_VC)
+
+# VCS option
+VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug
+VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
+VCS_VC_OPTIONS = -f $(TBENCH_VC)
+
+# NC verilog option
+NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
+NC_VC_OPTIONS = -f $(TBENCH_VC)
+
+# Boot Loader image
+BOOTLOADER = bootloader
+# Debug Tester image
+DEBUGTESTER = debugtester
+
+
+# Software make options
+# - Pass onto the software makefile to define targetted CPU type
+# You can append additional make options for testcode here
+SW_MAKE_OPTIONS = CPU_PRODUCT=$(CPU_PRODUCT) TOOL_CHAIN=$(TOOL_CHAIN)
+
+# ------- Simulator redirect -----------
+
+compile : compile_$(SIMULATOR)
+
+
+run : run_$(SIMULATOR)
+
+
+sim : sim_$(SIMULATOR)
+
+
+all : all_$(SIMULATOR)
+
+# ------- VCS -----------
+
+# Compile RTL
+compile_vcs :
+ vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) | tee compile_vcs.log
+
+
+# Run simulation in batch mode
+run_vcs : code
+ @if [ ! -d logs ] ; then \
+ mkdir logs; \
+ fi
+ @echo quit > quit.do
+ ./simv $(VCS_SIM_OPTION) < quit.do | tee logs/run_$(TESTNAME).log ;
+
+# Run simulation in interactive mode
+sim_vcs : code
+ ./simv -gui +vcs+lic+wait +vcs+flush+log &
+
+# Compile RTL, and run all tests in batch mode
+all_vcs : compile_vcs bootrom debugtester
+ @if [ ! -d logs ] ; then \
+ mkdir logs; \
+ fi
+ @echo quit > quit.do
+ @echo Run tests ...
+ for thistest in $(TEST_LIST) ; do \
+ echo $$thistest ; \
+ make testcode TESTNAME=$$thistest ;\
+ if [ -e image.hex ] ; then \
+ ./simv +vcs+lic+wait +vcs+flush+log < quit.do | tee logs/run_$$thistest.log ;\
+ else \
+ echo Cannot read image.hex ;\
+ exit 1; \
+ fi ; \
+ done
+
+# ------- NC -----------
+
+# Compile RTL
+compile_nc :
+ ncprep +overwrite $(NC_VC_OPTIONS) +debug | tee compile_nc.log
+ ncvlog -work worklib -f ncvlog.args | tee -a compile_nc.log
+ ncelab -mess -f ncelab.args -access +r | tee -a compile_nc.log
+
+# Note : If coverage is required, you can add -coverage all to ncelab
+
+# Run simulation in batch mode
+run_nc : code
+ @if [ ! -d logs ] ; then \
+ mkdir logs; \
+ fi
+ @echo run > run.tcl.tmp
+ @echo exit >> run.tcl.tmp
+ @mv run.tcl.tmp run.tcl
+ ncsim $(NCSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
+
+# Run simulation in interactive mode
+sim_nc : code
+ ncsim -gui $(NCSIM_OPTIONS)
+
+# Compile RTL, and run all tests in batch mode
+all_nc : compile_nc bootrom debugtester
+ @if [ ! -d logs ] ; then \
+ mkdir logs; \
+ fi
+ @echo run > run.tcl.tmp
+ @echo exit >> run.tcl.tmp
+ @mv run.tcl.tmp run.tcl
+ @echo Run tests ...
+ for thistest in $(TEST_LIST) ; do \
+ echo $$thistest ; \
+ make testcode TESTNAME=$$thistest ;\
+ if [ -e image.hex ] ; then \
+ ncsim $(NCSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
+ else \
+ echo Cannot read image.hex ;\
+ exit 1; \
+ fi ; \
+ done
+
+# ------- MTI -----------
+
+# Compile RTL
+compile_mti :
+ @if [ -d work ] ; then \
+ true ; \
+ else \
+ vlib work; \
+ fi
+ vlog -incr -lint +v2k $(MTI_OPTIONS) $(MTI_VC_OPTIONS) | tee compile_mti.log
+
+# Run simulation in batch mode
+run_mti : code
+ @if [ ! -d logs ] ; then \
+ mkdir logs; \
+ fi
+ vsim $(MTI_OPTIONS) -c tb_cmsdk_mcu -do "radix hex;run -all;quit -f" | tee logs/run_$(TESTNAME).log ;
+
+# Run simulation in interactive mode
+sim_mti : code
+ vsim $(MTI_OPTIONS) -gui tb_cmsdk_mcu &
+
+# Create work directory
+lib_mti :
+ vlib work
+
+# Compile RTL, and run all tests in batch mode
+all_mti : compile_mti bootrom debugtester
+ @if [ ! -d logs ] ; then \
+ mkdir logs; \
+ fi
+ @echo Run tests ...
+ for thistest in $(TEST_LIST) ; do \
+ echo $$thistest ; \
+ make testcode TESTNAME=$$thistest ;\
+ if [ -e image.hex ] ; then \
+ vsim $(MTI_OPTIONS) -c tb_cmsdk_mcu -do "radix hex;run -all;quit -f" | tee logs/run_$$thistest.log ;\
+ else \
+ echo Cannot read image.hex ;\
+ exit 1; \
+ fi ; \
+ done
+
+# ------- Software -----------
+
+# code target is used by other simulation targets (e.g. run_mti, sim_mti)
+# Before simulation, bootrom and testcode need to be compiled.
+code : testcode bootrom debugtester
+
+# Compile bootloader
+# Note : The use of ls after compile allows the computing server to sync up
+bootrom:
+ @(cd ../testcodes/$(BOOTLOADER) ;\
+ make all $(SW_MAKE_OPTIONS) ;\
+ echo Compile done ;\
+ ls > /dev/null ;\
+ echo Copy $(BOOTLOADER).hex ;\
+ if [ -e $(BOOTLOADER).hex ] ; then \
+ cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\
+ else \
+ while [ ! -e $(BOOTLOADER).hex ] ; do \
+ echo Wait for hex file ...; \
+ ls > /dev/null; \
+ sleep 5; \
+ done; \
+ if [ -e $(BOOTLOADER).hex ] ; then \
+ cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\
+ else \
+ echo Problem reading hex file ;\
+ exit 1; \
+ fi ;\
+ fi ;\
+ cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\
+ cd ../../rtl_sim )
+
+# Compile test code
+# Note : The use of ls after compile allows the computing server to sync up
+testcode:
+ifeq ($(TESTNAME),)
+ $(error Please specify TESTNAME on the make command line)
+endif
+ @(if [ -d "../testcodes/$(TESTNAME)" ] ; then \
+ cd ../testcodes/$(TESTNAME) ;\
+ make all $(SW_MAKE_OPTIONS) ; \
+ echo Compile done ;\
+ ls > /dev/null ;\
+ echo Copy $(TESTNAME).hex ;\
+ if [ -e $(TESTNAME).hex ] ; then \
+ cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \
+ else \
+ while [ ! -e $(TESTNAME).hex ] ; do \
+ echo Wait for $(TESTNAME).hex file ...; \
+ ls > /dev/null ; \
+ sleep 5 ; \
+ done; \
+ if [ -e $(TESTNAME).hex ] ; then \
+ cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \
+ else \
+ echo Problem reading hex file ;\
+ exit 1; \
+ fi ;\
+ fi ;\
+ cd ../../rtl_sim ;\
+ else \
+ echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\
+ exit 1 ;\
+ fi ;\
+ )
+
+
+# Compile debugtester
+# Note : The use of ls after compile allows the computing server to sync up
+debugtester:
+ @(cd ../../../software/debug_tester ;\
+ make all $(SW_MAKE_OPTIONS) ;\
+ echo Compile done ;\
+ ls > /dev/null ;\
+ echo Copy $(DEBUGTESTER)_le.hex ;\
+ if [ -e $(DEBUGTESTER)_le.hex ] ; then \
+ cp $(DEBUGTESTER)_le.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_le.hex ;\
+ else \
+ while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \
+ echo Wait for hex file ...; \
+ ls > /dev/null ; \
+ sleep 5 ; \
+ done; \
+ if [ -e $(DEBUGTESTER)_le.hex ] ; then \
+ cp $(DEBUGTESTER)_le.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_le.hex ;\
+ fi ;\
+ fi ;\
+ echo Copy $(DEBUGTESTER)_be.hex ;\
+ if [ -e $(DEBUGTESTER)_be.hex ] ; then \
+ cp $(DEBUGTESTER)_be.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_be.hex ;\
+ else \
+ while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \
+ echo Wait for hex file ...;\
+ ls > /dev/null ;\
+ sleep 5 ; \
+ done; \
+ if [ -e $(DEBUGTESTER)_be.hex ] ; then \
+ cp $(DEBUGTESTER)_be.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_be.hex ;\
+ fi ;\
+ fi ;\
+ if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \
+ echo Problem reading hex file ;\
+ exit 1 ;\
+ fi ;\
+ cd ../../systems/mcu/rtl_sim )
+
+# Compile all software including boot ROM
+compile_all_code: bootrom debugtester
+ for thistest in $(TEST_LIST) ; do \
+ echo Compiling $$thistest ; \
+ echo Removing old image.hex ;\
+ rm -f image.hex ;\
+ make testcode TESTNAME=$$thistest;\
+ if [ -e image.hex ] ; then \
+ echo OK - image.hex created for test $$thistest ;\
+ else \
+ echo ERROR - image.hex NOT created for test $$thistest ;\
+ exit 1; \
+ fi ; \
+ done
+
+# ------- document with v2html -----------
+
+#
+# rm -Rf *
+# ../tools/v2html -f ../verilog/v2html_M0.vc -ht cmsdk_mcu_system
+# cp -p tb_cmsdk_mcu.v.html hierarchy.html
+
+v2html:
+ echo building HTML tree
+ @if [ ! -d ../v2html_doc ] ; then \
+ mkdir ../v2html_doc; \
+ fi
+ @(cd ../v2html_doc; \
+ rm *.html; rm *.gif; rm *.gz; \
+ ~/tools/v2html -f ../verilog/v2html_M0.vc -ht nanosoc_chip ; \
+ cp -p tb_nanosoc.v.html hierarchy.html ; \
+ cd ../rtl_sim ; )
+ gtar zcvf ../v2html_doc.tgz ../v2html_doc
+
+
+# Remove all software compilation results
+clean_all_code:
+ @(cd ../../../software/debug_tester ; make clean; cd ../../systems/mcu/rtl_sim; )
+ @(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; )
+ for thistest in $(TEST_LIST) ; do \
+ echo Cleaning $$thistest ... ; \
+ cd ../testcodes/$$thistest ; \
+ make clean; \
+ cd ../../rtl_sim; \
+ done
+
+# Remove only bootloader and default selected test
+clean_code:
+ @(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; )
+ @(cd ../testcodes/$(TESTNAME) ; make clean; cd ../../rtl_sim; )
+
+# ------- clean -----------
+
+# Remove RTL compile files, log files, software compile files
+clean : clean_all_code
+ @if [ -d work ] ; then \
+ rm -rf work ; \
+ fi
+ @if [ -e tarmac0.log ] ; then \
+ rm tarmac0.log ; \
+ fi
+ @if [ -e tarmac1.log ] ; then \
+ rm tarmac1.log ; \
+ fi
+ @if [ -e tarmac0track.log ] ; then \
+ rm tarmac0track.log ; \
+ fi
+ @if [ -e ft1248_ip.log ] ; then \
+ rm ft1248_ip.log ; \
+ fi
+ @if [ -e ft1248_op.log ] ; then \
+ rm ft1248_op.log ; \
+ fi
+ @if [ -e uart.log ] ; then \
+ rm uart.log ; \
+ fi
+ @if [ -e uart0.log ] ; then \
+ rm uart0.log ; \
+ fi
+ @if [ -e uart1.log ] ; then \
+ rm uart1.log ; \
+ fi
+ @if [ -e uart2.log ] ; then \
+ rm uart2.log ; \
+ fi
+ @if [ -e uart3.log ] ; then \
+ rm uart3.log ; \
+ fi
+ @if [ -e vsim.wlf ] ; then \
+ rm vsim.wlf ; \
+ fi
+ @if [ -e image.hex ] ; then \
+ rm image.hex ; \
+ fi
+ @if [ -e date_file ] ; then \
+ rm date_file ; \
+ fi
+ @if [ -e bootrom.v ] ; then \
+ rm bootrom.v ; \
+ fi
+ @if [ -e bootrom.bintxt ] ; then \
+ rm bootrom.bintxt ; \
+ fi
+ @if [ -e bootloader.hex ] ; then \
+ rm bootloader.hex ; \
+ fi
+ @if [ -e debugtester_le.hex ] ; then \
+ rm debugtester_le.hex ; \
+ fi
+ @if [ -e debugtester_be.hex ] ; then \
+ rm debugtester_be.hex ; \
+ fi
+ @if [ -e compile_mti.log ] ; then \
+ rm compile_mti.log ; \
+ fi
+ @if [ -e vish_stacktrace.vstf ] ; then \
+ rm vish_stacktrace.vstf ; \
+ fi
+ @if [ -e compile_vcs.log ] ; then \
+ rm compile_vcs.log ; \
+ fi
+ @if [ -e compile_nc.log ] ; then \
+ rm compile_nc.log ; \
+ fi
+ @if [ -e transcript ] ; then \
+ rm transcript ; \
+ fi
+ @if [ -e simv ] ; then \
+ rm simv ; \
+ fi
+ @if [ -d csrc ] ; then \
+ rm -rf csrc ; \
+ fi
+ @if [ -d simv.daidir ] ; then \
+ rm -rf simv.daidir ; \
+ fi
+ @if [ -e inter.vpd ] ; then \
+ rm -rf inter.vpd ; \
+ fi
+ @if [ -e quit.do ] ; then \
+ rm -rf quit.do ; \
+ fi
+ @if [ -e ucli.key ] ; then \
+ rm -rf ucli.key ; \
+ fi
+ @if [ -d DVEfiles ] ; then \
+ rm -rf DVEfiles ; \
+ fi
+ @if [ -d INCA_libs ] ; then \
+ rm -rf INCA_libs ; \
+ fi
+ @if [ -d cov_work ] ; then \
+ rm -rf cov_work ; \
+ fi
+ @if [ -e hdl.var ] ; then \
+ rm -rf hdl.var ; \
+ fi
+ @if [ -e ncelab.args ] ; then \
+ rm -rf ncelab.args ; \
+ fi
+ @if [ -e ncvlog.args ] ; then \
+ rm -rf ncvlog.args ; \
+ fi
+ @if [ -e ncsim.args ] ; then \
+ rm -rf ncsim.args ; \
+ fi
+ @if [ -e ncprep.log ] ; then \
+ rm -rf ncprep.log ; \
+ fi
+ @if [ -e ncelab.log ] ; then \
+ rm -rf ncelab.log ; \
+ fi
+ @if [ -e ncvlog.log ] ; then \
+ rm -rf ncvlog.log ; \
+ fi
+ @if [ -e ncsim.log ] ; then \
+ rm -rf ncsim.log ; \
+ fi
+ @if [ -e run.tcl ] ; then \
+ rm -rf run.tcl ; \
+ fi
+ @if [ -e RUN_NC ] ; then \
+ rm -rf RUN_NC ; \
+ fi
+ @if [ -e ncsim.key ] ; then \
+ rm -rf ncsim.key ; \
+ fi
+ @if [ -e cds.lib ] ; then \
+ rm -rf cds.lib ; \
+ fi
+ @if [ -e logs ] ; then \
+ rm -rf logs ; \
+ fi
+ @if [ -e ../v2html_doc ] ; then \
+ rm -rf ../v2html_doc ; \
+ fi
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..59bbba095a1b73916c36e685fe51895ac58e8235
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\validation\apb_mux_tests.c</PathWithFileName>
+ <FilenameWithoutPath>apb_mux_tests.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..9b96eadf819a84102252b2d8a3d7a82b349a4fb6
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>apb_mux_tests</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output apb_mux_tests.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..e735ca81de478ce51eda853cea43b253ba7e5ef2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt
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new file mode 100644
index 0000000000000000000000000000000000000000..f19bc04d1ffcfe5210466164b171e70956c51937
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvproj
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+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>apb_mux_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\apb_mux_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..3705c8b9a3f662ca6fb8808046c774ad70729a2d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/makefile
@@ -0,0 +1,251 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = apb_mux_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# D5-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x20000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..54e406f40f5c742eb90fb1b2ad2b53bc918f97e3
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0.uvopt
@@ -0,0 +1,229 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
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+ <sDll></sDll>
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+ <sDlgDll></sDlgDll>
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+ <tDll></tDll>
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+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
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+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
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+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
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+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
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+ <Group>
+ <GroupName>System</GroupName>
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+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..cadb326716275f988f95cccd627e175f8bdd4d35
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0.uvproj
@@ -0,0 +1,425 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
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+ <Linker></Linker>
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+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
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+ </TargetStatus>
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+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output bootloader.hex</UserProg1Name>
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+ <SVCSIdString></SVCSIdString>
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+ <UseCPPCompiler>0</UseCPPCompiler>
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+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
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+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
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+ </Simulator>
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+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
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+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
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+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
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+ <Utilities>
+ <Flash1>
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+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
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+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
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+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
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+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
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+ <LinkerInputFile></LinkerInputFile>
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+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
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+ <GroupName>Startup</GroupName>
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+ <File>
+ <FileName>startup_CMSDK_CM0.s</FileName>
+ <FileType>2</FileType>
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+ </File>
+ </Files>
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+ <Group>
+ <GroupName>Application</GroupName>
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+ <File>
+ <FileName>bootloader.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\bootloader\bootloader.c</FilePath>
+ </File>
+ </Files>
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+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..d7a2948a10923d4a24b048590174d7e606022f60
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0p.uvopt
@@ -0,0 +1,216 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
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+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
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+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
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+ <tIfile></tIfile>
+ <pMon></pMon>
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+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
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+ </Group>
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+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..ba95d12010442f63180c49d50256cdbc85fa14a7
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/bootloader_cm0p.uvproj
@@ -0,0 +1,422 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
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+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0+</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0+") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>6268</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
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+ <InfinionOptionDll></InfinionOptionDll>
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+ <SLE66AMisc></SLE66AMisc>
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+ </TargetStatus>
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+ <OutputName>bootloader</OutputName>
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+ <ListingPath>.\</ListingPath>
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+ <Merge32K>0</Merge32K>
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+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg2Name></UserProg2Name>
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+ <BeforeMake>
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+ <UserProg2Name></UserProg2Name>
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+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output bootloader.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
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+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
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+ <SimDllArguments></SimDllArguments>
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+ <SimDlgDllArguments></SimDlgDllArguments>
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+ <TargetDllArguments></TargetDllArguments>
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+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c62e3215a58ced73875ab679c2a8a2e3e9166f16
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/bootloader/makefile
@@ -0,0 +1,254 @@
+#//-----------------------------------------------------------------------------
+#// customised Cortex-M0 'nanosoc' controller
+#// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#//
+#// Contributors
+#//
+#// David Flynn (d.w.flynn@soton.ac.uk)
+#//
+#// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+#//-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+BOOTLOADER = bootloader
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x10000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_bootloader.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(BOOTLOADER).hex $(BOOTLOADER).lst
+
+$(BOOTLOADER).o : $(SOFTWARE_DIR)/common/bootloader/$(BOOTLOADER).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(BOOTLOADER).ELF : $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o $(DEPS_LIST)
+ armlink $(ARM_LINK_OPTIONS) $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o -o $@
+
+$(BOOTLOADER).hex : $(BOOTLOADER).ELF $(DEPS_LIST)
+ fromelf --vhx --8x1 $< --output $@
+
+$(BOOTLOADER).lst : $(BOOTLOADER).ELF $(DEPS_LIST)
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/bootloader/$(BOOTLOADER).c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(BOOTLOADER).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(BOOTLOADER).o > $(BOOTLOADER).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(BOOTLOADER).o -O binary $(BOOTLOADER).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(BOOTLOADER).o --adjust-vma -0x10000000 -O verilog $(BOOTLOADER).hex
+
+# Note:
+# Objcopy use --adjust-vma so that the Verilog hex address start at address 0 instead of actual address 0x10000000
+#
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(BOOTLOADER).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(BOOTLOADER).bin > $(BOOTLOADER).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(BOOTLOADER).hex ] ; then \
+ rm -rf $(BOOTLOADER).hex ; \
+ fi
+ @if [ -e $(BOOTLOADER).lst ] ; then \
+ rm -rf $(BOOTLOADER).lst ; \
+ fi
+ @if [ -e $(BOOTLOADER).ELF ] ; then \
+ rm -rf $(BOOTLOADER).ELF ; \
+ fi
+ @if [ -e $(BOOTLOADER).bin ] ; then \
+ rm -rf $(BOOTLOADER).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..c834b4cf29eedd63ce93b10a9e9a1b0754557524
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvopt
@@ -0,0 +1,293 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
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+ </OPTLEX>
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+ <CListInc>0</CListInc>
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+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
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+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
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+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
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+ <sDll></sDll>
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+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
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+ </DebugFlag>
+ <Tracepoint>
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+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
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+ <RteFlg>0</RteFlg>
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+
+ <Group>
+ <GroupName>Application</GroupName>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..4571bb5d0992be835f2e020bcf76f6a28856b58d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvproj
@@ -0,0 +1,445 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
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+ </TargetStatus>
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+ <OutputName>debug_tests</OutputName>
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+ </BeforeCompile>
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+ </BeforeMake>
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+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output debug_tests.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ </AfterMake>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..80d160bfd80e6141593cd3315720ef43ea491c33
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvopt
@@ -0,0 +1,272 @@
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+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..ab2bfbbab0ae25e88c95fd782aa695d85344ffb0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvproj
@@ -0,0 +1,442 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0+</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0+") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>6268</DeviceId>
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+ <InfinionOptionDll></InfinionOptionDll>
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+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>debug_tests</OutputName>
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+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <nStopU1X>0</nStopU1X>
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+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg1Name></UserProg1Name>
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+ </BeforeMake>
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+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output debug_tests.hex</UserProg1Name>
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+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
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+ </Simulator>
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+ </Target>
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+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
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+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
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+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
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+ </IROM>
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+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
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+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
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+ </OCR_RVCT3>
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+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
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+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
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+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
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+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>3</Optim>
+ <oTime>0</oTime>
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+ <OneElfS>0</OneElfS>
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+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget; ..\..\..\..\software\debug_tester; ..\..\..\..\software\common\debug_tests; ..\generic</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
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+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>debug_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\debug_tests\debug_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>mcu_debugtester_interface.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\generic\mcu_debugtester_interface.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ <File>
+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..bb0cdf66128a909eba3ae1243235ea2cf4a62400
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile
@@ -0,0 +1,265 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2010-08-06 12:28:21 +0100 (Fri, 06 Aug 2010) $
+#
+# Revision : $Revision: 145378 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+GENERIC_DIR = ../generic
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = debug_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# Configuration ID values
+GENERIC_FILE = $(GENERIC_DIR)/config_id.h
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) -I $(GENERIC_DIR) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/debug_tester
+ARM_ASM_OPTIONS = -g
+
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/debug_tests/$(TESTNAME).c $(SOFTWARE_DIR)/common/debug_tests/$(TESTNAME).h $(GENERIC_FILE) $(SOFTWARE_DIR)/debug_tester/debugtester_functions.h $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+mcu_debugtester_interface.o : $(GENERIC_DIR)/mcu_debugtester_interface.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF: $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o mcu_debugtester_interface.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o mcu_debugtester_interface.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/debug_tests/$(TESTNAME).c \
+ $(GENERIC_DIR)/mcu_debugtester_interface.c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/debug_tester \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..cd7bd16a040ff8f04528b2cc77d57015ebc689c5
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
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+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
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+ <uSim>1</uSim>
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+ </DebugOpt>
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+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
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+
+ <Group>
+ <GroupName>Startup</GroupName>
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+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
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+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
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+ <PathWithFileName>..\..\..\..\software\common\validation\default_slaves_tests.c</PathWithFileName>
+ <FilenameWithoutPath>default_slaves_tests.c</FilenameWithoutPath>
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+ <bShared>0</bShared>
+ </File>
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+ <GroupName>System</GroupName>
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+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..dc2614c520c45881a80b8f700cf49362ca605061
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
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+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
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+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
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+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
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+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>default_slaves_tests</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
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+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output default_slaves_tests.hex</UserProg1Name>
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+ <TargetDlls>
+ <CpuDll></CpuDll>
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+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..5b56980a54118b99242cb1f1d5bc1ea9447bb5a0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt
@@ -0,0 +1,244 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..9b1eb99946f2a79a6f86cf0f7067b44d3444fbbb
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvproj
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+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>3</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>default_slaves_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\default_slaves_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..2437c5ce159c80575ace2888fc641389ba5df544
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/default_slaves_tests/makefile
@@ -0,0 +1,251 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = default_slaves_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..41e4c6c5cfe3b4d547ad92432024f1dfafee61ba
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
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--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0.uvproj
@@ -0,0 +1,440 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..0eea87d28020f12d99743b6edad83f820b8cbb47
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0p.uvopt
@@ -0,0 +1,258 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..b5b42b15991b77933ba9002b6a2b6ed2534a4538
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/dhry_cm0p.uvproj
@@ -0,0 +1,437 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+ <Header>### uVision Project, (C) Keil Software</Header>
+
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+ </File>
+ <File>
+ <FileName>dhry_2.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\dhry\dhry_2.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..70c1b5db93b265af3c5c2f358d299493221d0c00
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/makefile
@@ -0,0 +1,260 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = dhry
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS -DITERATIONS=200
+else
+ USER_DEFINE = -DCORTEX_M0 -DITERATIONS=200
+endif
+
+DEPS_LIST = makefile
+DHRY_ARMCC_OPTION = -Ono_inline --no_inline --no_multifile -Oloopref
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime \
+ -I $(CORE_DIR) -I $(DEVICE_DIR)/Include -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/common/dhry \
+ $(DHRY_ARMCC_OPTION) $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE) -fno-inline -fno-common -Wl,-Map -Wl,$(TESTNAME).map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+dhry_1.o : $(SOFTWARE_DIR)/common/dhry/dhry_1.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+dhry_2.o : $(SOFTWARE_DIR)/common/dhry/dhry_2.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+
+$(TESTNAME).ELF : dhry_1.o dhry_2.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ dhry_1.o dhry_2.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/dhry/dhry_1.c \
+ $(SOFTWARE_DIR)/common/dhry/dhry_2.c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/common/dhry \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/transcript b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/transcript
new file mode 100644
index 0000000000000000000000000000000000000000..58d44cd9646eb4c0fce43153b46815e1567fe5f0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dhry/transcript
@@ -0,0 +1,14 @@
+# // Questa Sim-64
+# // Version 10.7c linux_x86_64 Aug 17 2018
+# //
+# // Copyright 1991-2018 Mentor Graphics Corporation
+# // All Rights Reserved.
+# //
+# // QuestaSim and its associated documentation contain trade
+# // secrets and commercial or financial information that are the property of
+# // Mentor Graphics Corporation and are privileged, confidential,
+# // and exempt from disclosure under the Freedom of Information Act,
+# // 5 U.S.C. Section 552. Furthermore, this information
+# // is prohibited from disclosure under the Trade Secrets Act,
+# // 18 U.S.C. Section 1905.
+# //
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..ad90f6c51560a36ef30e74165af766faaec8b2fd
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
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+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
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+ </OPTLEX>
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+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..7487889fc4a4330523353656616ba5601d8faddd
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
+ <SchemaVersion>1.1</SchemaVersion>
+
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+
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+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..617768fdc06da5c49181491cdc74fdf9a3e37d79
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0p.uvopt
@@ -0,0 +1,244 @@
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+ <FilenameWithoutPath>system_CMSDK_CM0plus.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..b453d95de1bf04ed2b647e30e585aa003ddd7348
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/dma_tests_cm0p.uvproj
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
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+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>3</Optim>
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+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget; ..\generic</IncludePath>
+ </VariousControls>
+ </Cads>
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+ <IncludePath></IncludePath>
+ </VariousControls>
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+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>dma_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\dma_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c4aff4d783178a7d5a9679135a1c1b06b346b8d3
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dma_tests/makefile
@@ -0,0 +1,253 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+GENERIC_DIR = ../generic
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = dma_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# Configuration ID values
+GENERIC_FILE = $(GENERIC_DIR)/config_id.h
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) -I $(GENERIC_DIR) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(GENERIC_FILE) $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..32eab05ad9c979944769d15964a0e92a1be18963
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\demos\dualtimer_demo.c</PathWithFileName>
+ <FilenameWithoutPath>dualtimer_demo.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..19d256498f5a26fb7988cea61ebe3df65b81c502
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>dualtimer_demo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output dualtimer_demo.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
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+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
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+ </Ocm1>
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+ </Ocm2>
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+ </Ocm5>
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+ <Size>0x0</Size>
+ </Ocm6>
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+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..97f28114f0ef2f5cbfb5cbbbdb7efc65372f0f45
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvopt
@@ -0,0 +1,244 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..22abff1437b5573c873999b4e3ad993a149edd2d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvproj
@@ -0,0 +1,432 @@
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+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>3</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>dualtimer_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\demos\dualtimer_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6863911d4594f51cf9051a75f8e27039ab73a2aa
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/dualtimer_demo/makefile
@@ -0,0 +1,250 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = dualtimer_demo
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option (DS-5)
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/config_id.h b/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/config_id.h
new file mode 100644
index 0000000000000000000000000000000000000000..3a4f01b858dc30dac377a41a424629f414eb13a0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/config_id.h
@@ -0,0 +1,408 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+#define TEST_PASS 0
+#define TEST_FAIL 1
+//==============================================================================
+// Cortex-M0+ & Cortex-M0 IDs header File
+//==============================================================================
+
+// Values used by generic tests, such as debug_tests, romtable_tests
+
+#ifdef CORTEX_M0PLUS
+#define MCU_CPU_NAME "Cortex-M0+"
+#define MCU_CPU_ID_VALUE 0x410cc601
+#define MCU_DP_IDR_VALUE 0x0BC11477
+#define MCU_AP_IDR_VALUE 0x04770031
+#define MCU_AP_BASE_VALUE 0xF0000003
+#else
+#define MCU_CPU_NAME "Cortex-M0"
+#define MCU_CPU_ID_VALUE 0x410cc200
+#define MCU_DP_IDR_VALUE 0x0BB11477
+#define MCU_AP_IDR_VALUE 0x04770021
+#define MCU_AP_BASE_VALUE 0xE00FF003
+#endif
+
+//==============================================================================
+//
+// GenericID values - DO NOT MODIFY
+//
+
+// CoreSight Component Identifier for Peripheral classes
+#define CORESIGHT_CID0 0x0D
+#define CORESIGHT_CID1_tbl 0x10
+#define CORESIGHT_CID1_dbg 0x90
+#define CORESIGHT_CID1_mem 0xE0
+#define CORESIGHT_CID1_prm 0xF0
+#define CORESIGHT_CID2 0x05
+#define CORESIGHT_CID3 0xB1
+
+// Component Part Numbers
+#define ARM_JEP_ID 0x3B
+#define ARM_JEP_CONT 0x4
+
+//==============================================================================
+//
+// Cortex-M0 ID values
+#define CORTEXM0_CPUID 0x410cc200
+
+#define CM0_CPU_PART 0x471
+#define CM0_SCS_PART 0x008
+#define CM0_DWT_PART 0x00A
+#define CM0_BPU_PART 0x00B
+#define CM0_CPU_PART 0x471
+#define CM0_CSI_PART 0x4C2
+#define CS_CTI_PART 0x906
+#define CM0_DAP_DP_PART 0xBB
+
+// Revision Codes
+#define CM0_ROM_REV 0x0
+#define CM0_SCS_REV 0x0
+#define CM0_DWT_REV 0x0
+#define CM0_BPU_REV 0x0
+
+// Revand
+#define CM0_ROM_ECO 0x0
+#define CM0_SCS_ECO 0x0
+#define CM0_DWT_ECO 0x0
+#define CM0_BPU_ECO 0x0
+
+#define CORTEXM0DAP_JTAG_TAPID 0x0BA01477
+#define CORTEXM0DAP_JTAG_DPIDR 0x0BB11477
+#define CORTEXM0DAP_SW_DPIDR 0x0BB11477
+#define CORTEXM0DAP_AP_IDR 0x04770021
+
+#define CORTEXM0_ROM_PID3 0x00
+#define CORTEXM0_SCS_PID3 0x00
+#define CORTEXM0_DWT_PID3 0x00
+#define CORTEXM0_BPU_PID3 0x00
+
+//==============================================================================
+//
+// Cortex-M0+ ID values
+#define CORTEXM0PLUS_CPUID (0x410cc601 ^ (EXPECTED_ECOREVNUM & 0x0000000F))
+
+#define CM0P_CPU_PART 0x4C0
+#define CM0P_SCS_PART 0x008
+#define CM0P_DWT_PART 0x00A
+#define CM0P_BPU_PART 0x00B
+#define CM0P_MTB_PART 0x932
+#define CM0P_CSI_PART 0x4C1
+#define CM0P_CTI_PART 0x9A6
+#define CM0P_DAP_DP_PART 0xBC
+
+// Revision Codes
+#define CM0P_ROM_REV 0x0
+#define CM0P_SCS_REV 0x0
+#define CM0P_DWT_REV 0x0
+#define CM0P_BPU_REV 0x0
+#define CM0P_MTB_REV 0x1
+#define CM0P_DAP_DP_REV (0x0 ^ ((EXPECTED_ECOREVNUM & 0x0F000000) >> 24))
+#define CM0P_DAP_AP_REV (0x0 ^ ((EXPECTED_ECOREVNUM & 0x00F00000) >> 20))
+
+// Revand
+#define CM0P_ROM_ECO ((EXPECTED_ECOREVNUM & 0x000F0000) >> 16)
+#define CM0P_SCS_ECO ((EXPECTED_ECOREVNUM & 0x0000F000) >> 12)
+#define CM0P_DWT_ECO ((EXPECTED_ECOREVNUM & 0x00000F00) >> 8)
+#define CM0P_BPU_ECO ((EXPECTED_ECOREVNUM & 0x000000F0) >> 4)
+#define CM0P_MTB_ECO ((EXPECTED_ECOREVNUM & 0xF0000000) >> 28)
+
+// DAP Registers
+#define CM0P_DAP_JTAG_TAPID (0x0BA01477 | (CM0P_DAP_DP_REV << 28))
+#define CM0P_DAP_JTAG_DPIDR (0x0BC11477 | (CM0P_DAP_DP_REV << 28))
+#define CM0P_DAP_SW_DPIDR (0x0BC11477 | (CM0P_DAP_DP_REV << 28))
+#define CM0P_DAP_SWMD_DPIDR (0x0BC12477 | (CM0P_DAP_DP_REV << 28))
+#define CM0P_DAP_APIDR (0x04770031 | (CM0P_DAP_AP_REV << 28))
+
+//==============================================================================
+
+//=====================================================================
+// Cortex-M0 & Cortex-M0+ Configuration
+//=====================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Processor configuration options.
+// These must match the expected hardware configuration of the processor.
+//
+// - EXPECTED_BE : Expected Endianness (0-1)
+// - EXPECTED_BKPT : Expected number of Breakpoint Comparators (0-4)
+// - EXPECTED_DBG : Expected Debug config (0-1)
+// - EXPECTED_NUMIRQ : Expected number of IRQ lines (0-32)
+// - EXPECTED_SMUL : Expected Multiplier config (0-1)
+// - EXPECTED_SYST : Expected SysTick extension (0-1)
+// - EXPECTED_WPT : Expected number of Watchpoint Comparators (0-2)
+//
+// Processor Tie-offs
+//
+// - EXPECTED_STCALIB : Expected value of STCALIB (0-0x3FFFFFF)
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// System ROM Table options.
+// These must match the values in the System ROM Table.
+//
+// - EXPECTED_CUST_JEP_ID : Expected JEDEC JEP-106 identity code (0-0x7F)
+// - EXPECTED_CUST_JEP_CONT : Expected JEDEC JEP-106 continuation code (0-0xF)
+// - EXPECTED_CUST_PART : Expected Part number (0-0xFFF)
+// - EXPECTED_CUST_REV : Expected Revision number (0-0xF)
+// - EXPECTED_CUST_REVAND : Expected Manufacturer Revision number (0-0xF)
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Engineering Change Order and Revision Number Tie-off.
+//
+// - EXPECTED_ECOREVNUM : Expected Engineering Change Order and Revision number (0-0xFFFFFFFF)
+//
+////////////////////////////////////////////////////////////////////////////////
+
+// <h> Processor configuration options
+// <o> EXPECTED_BE: Expected Endianness <0=> Little Endian <1=> Big Endian
+#define EXPECTED_BE 0
+
+
+// <o> EXPECTED_BKPT: Expected number of Breakpoint Comparators <0-4>
+#define EXPECTED_BKPT 4
+
+
+// <o> EXPECTED_DBG: Expected Debug config <0=> Absent <1=> Present
+#define EXPECTED_DBG 1
+
+
+// <o> EXPECTED_NUMIRQ: Expected number of IRQ lines <0-32>
+#define EXPECTED_NUMIRQ 32
+
+
+// <o> EXPECTED_SMUL: Expected Small Multiplier config <0=> Absent (Fast Multiplier) <1=> Present (Small Multiplier)
+#define EXPECTED_SMUL 0
+
+
+// <o> EXPECTED_SYST: Expected SysTick extension <0=> Absent <1=> Present
+#define EXPECTED_SYST 1
+
+
+// <o> EXPECTED_WPT: Expected number of Watchpoint Comparators <0-2>
+#define EXPECTED_WPT 2
+
+
+// <o> EXPECTED_SIMPLE_CHECK: <1=> only run the simple CPUID check <0=> more complex check included
+// like Lockup, Sleep, other ID check etc
+#define EXPECTED_SIMPLE_CHECK 0
+
+
+// <h> Processor port Tie-Offs
+// <o> EXPECTED_STCALIB: Expected value of STCALIB[25:0] at CORTEXM0INTEGRATION or CORTEXM0 <0x0-0x3FFFFFF>
+#define EXPECTED_STCALIB 0x1028B0A
+
+
+// <o> EXPECTED_BASEADDR: Expected value of BASEADDR[31:0] at CORTEXM0DAP <0x0-0xFFFFFFFF>
+#ifdef CORTEX_M0
+#define EXPECTED_BASEADDR 0xE00FF003
+#else
+#define EXPECTED_BASEADDR 0xF0000003
+#endif
+
+// <o> EXPECTED_JTAGnSW: Expected Cortex M0(+) DAP Protocol <0=> Serial Wire <1=> JTAG
+#define EXPECTED_JTAGnSW 0
+
+// <h> System ROM Table ID values
+// <o> EXPECTED_CUST_JEP_ID: Expected JEDEC JEP-106 identity code (0-0x7F)
+#define EXPECTED_CUST_JEP_ID 0x00
+
+
+// <o> EXPECTED_CUST_JEP_CONT: Expected JEDEC JEP-106 continuation code (0-0xF)
+#define EXPECTED_CUST_JEP_CONT 0x0
+
+
+// <o> EXPECTED_CUST_PART: Expected Part number (0-0xFFF)
+#define EXPECTED_CUST_PART 0x000
+
+
+// <o> EXPECTED_CUST_REV: Expected Revision number (0-0xF)
+#define EXPECTED_CUST_REV 0x0
+
+
+// <o> EXPECTED_CUST_REVAND: Expected Manufacturer Revision number (0-0xF)
+#define EXPECTED_CUST_REVAND 0x0
+
+// </h>
+
+// <h> EXPECTED_ECOREVNUM
+// <o> EXPECTED_ECOREVNUM: Expected Engineering Change Order and Revision number (0-0xFFFFFFFF)
+#define EXPECTED_ECOREVNUM 0x00000000
+
+// </h>
+
+// <h> CSI and CTI - Used by romtable test only
+// <o> EXPECTED_CSI: Expected CoreSight Integration Level <0=> Absent <1=> Present
+#define EXPECTED_CSI 0
+
+// <o> EXPECTED_CTI: Expected Cross Trigger Interface <0=> Absent <1=> Present
+#define EXPECTED_CTI 0
+// </h>
+
+//=====================================================================
+// Cortex-M0+ Configuration
+//=====================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Processor configuration options.
+// These must match the expected hardware configuration of the processor.
+//
+// - EXPECTED_BE : Expected Endianness (0-1)
+// - EXPECTED_BKPT : Expected number of Breakpoint Comparators (0-4)
+// - EXPECTED_DBG : Expected Debug config (0-1)
+// - EXPECTED_IOP : Expected IOP config (0-1)
+// - EXPECTED_IRQDIS : Expected IRQ disable (0-0xFFFFFFFF)
+// - EXPECTED_MPU : Expected MPU config (0,8)
+// - EXPECTED_NUMIRQ : Expected number of IRQ lines (0-32)
+// - EXPECTED_SMUL : Expected Multiplier config (0-1)
+// - EXPECTED_SYST : Expected SysTick extension (0-1)
+// - EXPECTED_USER : Expected User config (0-1)
+// - EXPECTED_VTOR : Expected VTOR config (0-1)
+// - EXPECTED_WIC : Expected Wake-up interrupt controller support <0-1>
+// - EXPECTED_WICLINES : Expected number of supported WIC lines <2-34>
+// - EXPECTED_WPT : Expected number of Watchpoint Comparators (0-2)
+//
+// Processor Tie-offs
+//
+// - EXPECTED_STCALIB : Expected value of STCALIB (0-0x3FFFFFF)
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// DAP configuration options.
+// These must match the expected hardware configuration of the DAP.
+//
+// - EXPECTED_BASEADDR : Expected BASEADDR at Cortex M0+ DAP (0-0xFFFFFFFF)
+// - EXPECTED_JTAGnSW : Expected Cortex M0+ DAP Protocol (0,1)
+// - EXPECTED_SWMD : Expected SW Multi-Drop config (0-1)
+//
+// DAP Tie-offs
+//
+// - EXPECTED_INSTANCEID : Expected DAP instance number (0-0xF)
+// - EXPECTED_TREVISION : Expected Revision number (0-0xF)
+// - EXPECTED_TPARTNO : Expected Part number (0-0xFFFF)
+// - EXPECTED_TDESIGNER : Expected Designer code (0-0x7FF)
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// CoreSight MTB-M0+ configuration options.
+//
+// - EXPECTED_MTB : Expected CoreSight MTB-M0+ config (0-1)
+// - EXPECTED_MTB_BASEADDR : Expected CoreSight MTB-M0+ BASEADDR (0-0xFFFFFFFF)
+// - EXPECTED_MTB_AWIDTH : Expected CoreSight MTB-M0+ Address width (5-32)
+//
+// NOTE : When the MTB (EXPECTED_MTB = 1) is included, the RAM that is used for
+// the data accesses is shared with the MTB, so if you set the address
+// width to be smaller than the default (EXPECTED_MTB_AWIDTH = 16), the
+// addresses that some tests are using to write data to will alias to
+// lower addresses,so some tests will not work with smaller memory.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// System ROM Table options.
+// These must match the values in the System ROM Table.
+//
+// - EXPECTED_CUST_JEP_ID : Expected JEDEC JEP-106 identity code (0-0x7F)
+// - EXPECTED_CUST_JEP_CONT : Expected JEDEC JEP-106 continuation code (0-0xF)
+// - EXPECTED_CUST_PART : Expected Part number (0-0xFFF)
+// - EXPECTED_CUST_REV : Expected Revision number (0-0xF)
+// - EXPECTED_CUST_REVAND : Expected Manufacturer Revision number (0-0xF)
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Engineering Change Order and Revision Number Tie-off.
+//
+// - EXPECTED_ECOREVNUM : Expected Engineering Change Order and Revision number (0-0xFFFFFFFF)
+//
+////////////////////////////////////////////////////////////////////////////////
+
+// <h> Processor configuration options
+// <o> EXPECTED_IOP: Expected IOP config <0=> Absent <1=> Present
+#define EXPECTED_IOP 0
+
+
+// <o> EXPECTED_IRQDIS: Expected interrupt disable <0x0-0xFFFFFFFF>
+#define EXPECTED_IRQDIS 0x00000000
+
+
+// <o> EXPECTED_MPU: Expected MPU config <0=> Absent <8=> Present (8 Regions)
+#define EXPECTED_MPU 8
+
+
+// <o> EXPECTED_USER: Expected User config <0=> Absent (Privilege mode only) <1=> Present
+#define EXPECTED_USER 1
+
+
+// <o> EXPECTED_VTOR: Expected VTOR config <0=> Absent <1=> Present
+#define EXPECTED_VTOR 1
+
+
+// <o> EXPECTED_WIC: Expected Wake-up interrupt controller support <0-1>
+#define EXPECTED_WIC 1
+
+
+// <o> EXPECTED_WICLINES : Expected number of supported WIC lines <2-34>
+#define EXPECTED_WICLINES 34
+
+
+// <h> Processor port Tie-Offs
+// <o> EXPECTED_SWMD: Expected SW Multi-Drop config <0=> Absent <1=> Present (Serial Wire Protocol 2)
+#define EXPECTED_SWMD 0
+
+// </h>
+
+// <h> DAP Tie-offs
+// <o> EXPECTED_INSTANCEID: Expected DAP instance number (0-0xF)
+#define EXPECTED_INSTANCEID 0x0
+
+
+// <o> EXPECTED_TREVISION: Expected Revision number (0-0xF)
+#define EXPECTED_TREVISION 0x0
+
+
+// <o> EXPECTED_TPARTNO: Expected Part number (0-0xFFFF)
+#define EXPECTED_TPARTNO 0x0000
+
+
+// <o> EXPECTED_TDESIGNER: Expected Designer code (0-0x7FF)
+#define EXPECTED_TDESIGNER 0x000
+
+// </h>
+
+// <h> CoreSight MTB-M0+ configuration options
+// <o> EXPECTED_MTB: Expected CoreSight MTB-M0+ config <0=> Absent <1=> Present
+#define EXPECTED_MTB 0
+
+
+// <o> EXPECTED_MTB_BASEADDR: Expected CoreSight MTB-M0+ BASEADDR <0x0-0xFFFFFFFF>
+#define EXPECTED_MTB_BASEADDR 0xF0210000
+
+
+// <o> EXPECTED_MTB_AWIDTH: Expected CoreSight MTB-M0+ Address width <5-32>
+#define EXPECTED_MTB_AWIDTH 16
+
+// </h>
+
+// <<< end of configuration section >>>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/mcu_debugtester_interface.c b/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/mcu_debugtester_interface.c
new file mode 100644
index 0000000000000000000000000000000000000000..75f73a10bb92b783fa6af2a15140736aa8c37e6c
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/mcu_debugtester_interface.c
@@ -0,0 +1,131 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: $
+ *
+ * Revision : $Revision: $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+#include "mcu_debugtester_interface.h" // For definition of interface to the debug tester
+
+void EnableDebugTester(void)
+{
+ uint32_t i;
+
+
+ //
+ // Initialise GPIO from MCU to Debug Tester
+ //
+
+ //Initialize the GPIO0 higher 8 bits output value, set to 0
+ CMSDK_GPIO0->DATAOUT = (0x00000000); //set GPIO output to 0 for default value, disable the function strobe
+ CMSDK_gpio_SetOutEnable (CMSDK_GPIO0, DEBUG_CMD); // set specified bit in out enable register
+
+
+ //
+ // Enable the Debug Tester in the testbench
+ //
+
+ // send command to enable the connection to debug tester
+ UartPutc((char) DBG_ESCAPE); //send ESCAPE code
+ UartPutc((char) DBG_CONNECT_ENABLE); //send debug test enable command
+ puts("\nEnabling debug tester...\n");
+ // If debug tester is not present,
+ if((CMSDK_GPIO0->DATA & DEBUG_ERROR) != 0)
+ {
+ puts("DBGERROR bit (debug error) asserted.\n");
+ puts("Debug tester not available:\n");
+ puts("1: The ARM_CMSDK_INCLUDE_DEBUG_TESTER macro is not defined, or\n");
+ puts("2: Cortex-M0 DesignStart is used\n");
+ puts("** TEST SKIPPED **\n");
+ // End simulation
+ UartEndSimulation();
+ }
+
+
+ //
+ // Initialise the Communication Region
+ // (Zero the 4 words above Stack Top)
+ //
+
+ for(i=0; i<4 ; i++)
+ {
+ DEBUGTESTERDATA[i] = 0;
+ }
+}
+
+
+void DisableDebugTester(void)
+{
+ //send command to disable the connection to debug tester
+ UartPutc((char) DBG_ESCAPE); //send debug test disable command,
+ UartPutc((char) DBG_CONNECT_DISABLE); //send debug test disable command,
+ UartEndSimulation(); //stop simulation
+}
+
+
+//===========================================================================
+// Start a function running on the debug tester
+//===========================================================================
+void StartDebugTester(uint32_t Function)
+{
+ // Write function onto function select pins
+ CMSDK_gpio_SetOutEnable (CMSDK_GPIO0, DEBUG_CMD); // set specified bit in out enable register
+
+ //setup function select and function strobe
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, Function<<DEBUG_BIT_LOC | DEBUG_STROBE, DEBUG_CMD|DEBUG_STROBE);
+
+ // Wait to see Running asserted
+ while((CMSDK_GPIO0->DATA & DEBUG_RUNNING) == 0);
+
+ // Clear strobe
+ CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0x0, DEBUG_STROBE);
+}
+
+
+//===========================================================================
+// Check that a debug tester function completed
+// Return pass/fail accordingly
+//===========================================================================
+uint32_t CheckDebugTester(void)
+{
+ // Wait to see Running deasserted
+ while((CMSDK_GPIO0->DATA & DEBUG_RUNNING)!= 0);
+
+ // Return status, check ERROR bit
+ if((CMSDK_GPIO0->DATA & DEBUG_ERROR) == 0)
+ {
+ return TEST_PASS;
+ }
+ else
+ {
+ return TEST_FAIL;
+ }
+}
+
+
+//===========================================================================
+// Execute a debug tester function
+//===========================================================================
+uint32_t CallDebugTester(uint32_t Function)
+{
+ StartDebugTester(Function);
+ return CheckDebugTester();
+}
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/mcu_debugtester_interface.h b/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/mcu_debugtester_interface.h
new file mode 100644
index 0000000000000000000000000000000000000000..162672da8074da9cc2d6c364e1644a079de0c2d8
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/generic/mcu_debugtester_interface.h
@@ -0,0 +1,102 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2013-01-18 17:35:18 +0000 (Fri, 18 Jan 2013) $
+//
+// Revision : $Revision: 234195 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//-----------------------------------------------------------------------------
+//
+
+//
+// Definition of CMSDK example MCU to the Debug Tester
+//
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+
+#else
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+
+#else
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+
+#else
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+
+#endif
+#endif
+#endif
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h" // for stdout
+#include "CMSDK_driver.h"
+#include "config_id.h" // general defines such as test_pass
+
+
+// Functions used by tests that communicate with the Debug Tester
+extern void EnableDebugTester(void);
+extern void DisableDebugTester(void);
+extern uint32_t CallDebugTester(uint32_t);
+extern void StartDebugTester(uint32_t);
+extern uint32_t CheckDebugTester(void);
+
+
+//Test command sequence definition
+#define DBG_ESCAPE 0x1B
+#define DBG_CONNECT_ENABLE 0x11
+#define DBG_CONNECT_DISABLE 0x12
+#define DBG_SIM_STOP 0x4
+
+
+// GPIO0 bit allocation
+//
+// CM0_MCU GPIO0 -------------------------------------- Debug Tester
+//
+// GPIO[15] 7 <----------------------------------------< Running
+// GPIO[14] 6 <----------------------------------------< Error
+// GPIO[13] 5 >----------------------------------------> Function Strobe
+// GPIO[12] 4 >----------------------------------------> Function Select bit 4
+// GPIO[11] 3 >----------------------------------------> Function Select bit 3
+// GPIO[10] 2 >----------------------------------------> Function Select bit 2
+// GPIO[9] 1 >----------------------------------------> Function Select bit 1
+// GPIO[8] 0 >----------------------------------------> Function Select bit 0
+//
+#define DEBUG_BIT_LOC 8 //GPIO[8] is the least bit of Function Select
+#define DEBUG_CMD 0x3f<<8 //GPIO [13:8]
+#define DEBUG_STROBE 0x00002000 //GPIO [13]
+#define DEBUG_ERROR 0x00004000 //GPIO [14]
+#define DEBUG_RUNNING 0x00008000 //GPIO [15]
+
+// GPIO1[7] 7
+// GPIO1[6] 6
+// GPIO1[5] 5
+// GPIO1[4] 4
+// GPIO1[3] 3
+// GPIO1[2] 2
+// GPIO1[1] 1
+// GPIO1[0] 0
+
+
+// CMSDK example MCU's view of the memory shared with the debugtester
+// (4 words above stack top)
+// This macro uses the SP value from the vector table as stacktop
+// The stacktop cannot be set to the top of the memory.
+#define DEBUGTESTERDATA ((volatile uint32_t *) *((uint32_t *) 0x0))
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..3b1eeedc14a7e6194dd55c711d8bdbf6f64e0ca9
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..6262fae2971340ba6579d077b7f632488943d125
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvproj
@@ -0,0 +1,440 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..c0fca7a88d8f23bc239ac8631e5359d52a4580f0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0p.uvopt
@@ -0,0 +1,258 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..bdd4ec23e0940198e31aa3b90495ae2926cfc9e8
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0p.uvproj
@@ -0,0 +1,437 @@
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+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ <File>
+ <FileName>gpio_driver_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\gpio_driver_tests.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d4bde33958fec1bef4e9ea19b520d07ecec65198
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_driver_tests/makefile
@@ -0,0 +1,255 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-01-25 10:05:56 +0000 (Tue, 25 Jan 2011) $
+#
+# Revision : $Revision: 159421 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = gpio_driver_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..39dfcaa5e5e15d556e59f3196b4436baf14ad2c6
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\validation\gpio_tests.c</PathWithFileName>
+ <FilenameWithoutPath>gpio_tests.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..284bc453f3b675710893e87e488b8e7f49ddcb6e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>gpio_tests</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
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+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..44d9aede3674070124fbecf1dab1957d603b5015
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0p.uvopt
@@ -0,0 +1,244 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
+ <Extensions>
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+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..8e0ea890c357175c4b3e0e3a003cada8d532964f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/gpio_tests_cm0p.uvproj
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
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+ <ToolsetName>ARM-ADS</ToolsetName>
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+ <Device>Cortex-M0+</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0+") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>6268</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>gpio_tests</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output gpio_tests.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>gpio_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\gpio_tests.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..74e83c09816f7e9e7e76dfb8693bd725859c99bc
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/gpio_tests/makefile
@@ -0,0 +1,253 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-01-25 10:05:56 +0000 (Tue, 25 Jan 2011) $
+#
+# Revision : $Revision: 159421 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = gpio_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/.project b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/.project
new file mode 100644
index 0000000000000000000000000000000000000000..b4807edc254e327ec1fd8bc72484806be1c6895c
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/.project
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>hello</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ </natures>
+</projectDescription>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello.c b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello.c
new file mode 100644
index 0000000000000000000000000000000000000000..ab9d77197d8013b3485072b9551d84e167151428
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello.c
@@ -0,0 +1,52 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#include "core_cm0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#include "core_cm0plus.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+int main (void)
+{
+ // UART init
+ UartStdOutInit();
+
+ printf("Hello world\n");
+
+ printf("** TEST PASSED **\n");
+
+ // End simulation
+ UartEndSimulation();
+
+ return 0;
+}
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..5145b64ae61d4493a64329b3bdf79657db4685de
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\hello.c</PathWithFileName>
+ <FilenameWithoutPath>hello.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..6baba5759567d594029cd964d3afca6de7a1a44f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>hello</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output hello.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..c39e058b45b197c488caf20d82ff0f772462a607
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0p.uvopt
@@ -0,0 +1,244 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..38048cf25d657ebcb9940c24f9b90d655373901f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/hello_cm0p.uvproj
@@ -0,0 +1,432 @@
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+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>hello.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\hello.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..e8ac4eec12e62a44286c83c02c35f8b22de5528b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/hello/makefile
@@ -0,0 +1,255 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = hello
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+#ARM_ASM_OPTIONS = -g
+#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+# --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+
+ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS =
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s -z -v $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..08449be179e94fe4c3759a657ead0cff5c2073e5
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
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--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0.uvproj
@@ -0,0 +1,440 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..d09b1c74e66119ce003fab8275cf1f3032e47448
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0p.uvopt
@@ -0,0 +1,258 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..58b9dd6b8a923e4f8166d5fa043330a0f19d0827
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/interrupt_demo_cm0p.uvproj
@@ -0,0 +1,437 @@
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+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7966b80315f8bf9a5b8892406ca73ce17e59de9e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/interrupt_demo/makefile
@@ -0,0 +1,255 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-01-25 10:05:56 +0000 (Tue, 25 Jan 2011) $
+#
+# Revision : $Revision: 159421 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = interrupt_demo
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..0f0163794b1131818238cc7d417e6569341b2c7d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/makefile
@@ -0,0 +1,251 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = memory_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..e832157abe2a01485dbd15a55c86d472d88525b7
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
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new file mode 100644
index 0000000000000000000000000000000000000000..9a165017f877c0f35fd58c14987afd982fb16c7b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0p.uvopt
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..a339a79983508bed5cb1f542310a88504ebde937
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/memory_tests/memory_tests_cm0p.uvproj
@@ -0,0 +1,432 @@
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+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b1b195ac9a807a52e932c63c00b7df32ba31c462
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/makefile
@@ -0,0 +1,266 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+GENERIC_DIR = ../generic
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = romtable_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# Configuration ID values
+GENERIC_FILE = $(GENERIC_DIR)/config_id.h
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(CORE_DIR) -I $(DEVICE_DIR)/Include -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/debug_tester $(USER_DEFINE)
+
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply take 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/romtable_tests/$(TESTNAME).c $(SOFTWARE_DIR)/common/romtable_tests/$(TESTNAME).h $(GENERIC_FILE) $(SOFTWARE_DIR)/debug_tester/debugtester_functions.h $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+mcu_debugtester_interface.o : $(GENERIC_DIR)/mcu_debugtester_interface.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF: $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o mcu_debugtester_interface.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o mcu_debugtester_interface.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/romtable_tests/$(TESTNAME).c \
+ $(GENERIC_DIR)/mcu_debugtester_interface.c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/debug_tester \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..f5deaa30f24b972be6e6c9f32666a86bfa9d9127
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0.uvopt
@@ -0,0 +1,293 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..94e86e6eb704c36dc416c19535b378da7b411db2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0.uvproj
@@ -0,0 +1,445 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..1819e7408d8220d705cb3b20193bf1aa5eb11441
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0p.uvopt
@@ -0,0 +1,272 @@
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+ <PathWithFileName>..\generic\mcu_debugtester_interface.c</PathWithFileName>
+ <FilenameWithoutPath>mcu_debugtester_interface.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
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+ <GroupName>System</GroupName>
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+ <FilenameWithoutPath>system_CMSDK_CM0plus.c</FilenameWithoutPath>
+ </File>
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+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..b3ed42cc32422869d5513fca6b9a565277974964
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/romtable_tests/romtable_tests_cm0p.uvproj
@@ -0,0 +1,442 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
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+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0+</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0+") ESEL ELITTLE</Cpu>
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+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
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+ <InfinionOptionDll></InfinionOptionDll>
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+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
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+ </TargetStatus>
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+ <OutputName>romtable_tests</OutputName>
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+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output romtable_tests.hex</UserProg1Name>
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+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
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+ <TargetDlls>
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+ <Driver></Driver>
+ </TargetDlls>
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+ <Utilities>
+ <Flash1>
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+ <Flash3></Flash3>
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+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
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+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
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+ </OCR_RVCT1>
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+ </OCR_RVCT2>
+ <OCR_RVCT3>
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+ </OCR_RVCT4>
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+ </OCR_RVCT5>
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+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
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+ <uThumb>0</uThumb>
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+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget; ..\..\..\..\software\debug_tester; ..\generic</IncludePath>
+ </VariousControls>
+ </Cads>
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+ <MiscControls></MiscControls>
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+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
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+ <umfTarg>1</umfTarg>
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+ <IncludeLibs></IncludeLibs>
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+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>romtable_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\romtable_tests\romtable_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>mcu_debugtester_interface.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\generic\mcu_debugtester_interface.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ <File>
+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/RTX_Config.c b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/RTX_Config.c
new file mode 100644
index 0000000000000000000000000000000000000000..262cc797ddf6c118bae136533babf916752902f7
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/RTX_Config.c
@@ -0,0 +1,187 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * R T L - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: RTX_CONFIG.C
+ * Purpose: Configuration of RTX Kernel for Cortex-M
+ * Rev.: V3.40
+ *----------------------------------------------------------------------------
+*/
+
+#include <RTL.h>
+
+/*----------------------------------------------------------------------------
+ * RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Task Definitions
+// ===================
+//
+// <o>Number of concurrent running tasks <0-250>
+// <i> Define max. number of tasks that will run at the same time.
+// <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT 6
+#endif
+
+// <o>Number of tasks with user-provided stack <0-250>
+// <i> Define the number of tasks that will use a bigger stack.
+// <i> The memory space for the stack is provided by the user.
+// <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT 0
+#endif
+
+// <o>Task stack size [bytes] <20-4096:8><#/4>
+// <i> Set the stack size for tasks which is assigned by the system.
+// <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE 200
+#endif
+
+// <q>Check for the stack overflow
+// ===============================
+// <i> Include the stack checking code for a stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK 1
+#endif
+
+// <q>Run in privileged mode
+// =========================
+// <i> Run all Tasks in privileged mode.
+// <i> Default: Unprivileged
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV 0
+#endif
+
+// <o>Number of user timers <0-250>
+// <i> Define max. number of user timers that will run at the same time.
+// <i> Default: 0 (User timers disabled)
+#ifndef OS_TIMERCNT
+ #define OS_TIMERCNT 0
+#endif
+
+// </h>
+// <h>SysTick Timer Configuration
+// =============================
+// <o>Timer clock value [Hz] <1-1000000000>
+// <i> Set the timer clock value for selected timer.
+// <i> Default: 6000000 (6MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK 50000000
+#endif
+
+// <o>Timer tick value [us] <1-1000000>
+// <i> Set the timer tick value for selected timer.
+// <i> Default: 10000 (10ms)
+#ifndef OS_TICK
+ #define OS_TICK 200
+#endif
+
+// </h>
+// <e>Round-Robin Task switching
+// =============================
+// <i> Enable Round-Robin Task switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN 1
+#endif
+
+// <o>Round-Robin Timeout [ticks] <1-1000>
+// <i> Define how long a task will execute before a task switch.
+// <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT 5
+#endif
+
+// </e>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+// Define max. number system mutexes that are used to protect
+// the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT 8
+#endif
+
+/*----------------------------------------------------------------------------
+ * RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+__task void os_idle_demon (void) {
+ /* The idle demon is a system task, running when no other task is ready */
+ /* to run. The 'os_xxx' function calls are not allowed from this task. */
+
+ for (;;) {
+ /* HERE: include optional user code to be executed when no task runs.*/
+ }
+}
+
+
+/*--------------------------- os_tmr_call -----------------------------------*/
+
+void os_tmr_call (U16 info) {
+ /* This function is called when the user timer has expired. Parameter */
+ /* 'info' holds the value, defined when the timer was created. */
+
+ /* HERE: include optional user code to be executed on timeout. */
+}
+
+
+/*--------------------------- os_stk_overflow -------------------------------*/
+
+void os_stk_overflow (OS_TID task_id) {
+ /* This function is called when a stack overflow is detected. Parameter */
+ /* 'task_id' holds the id of this task. You can use 'RTX Kernel' dialog,*/
+ /* page 'Active Tasks' to check, which task needs a bigger stack. */
+
+ /* HERE: include optional code to be executed on stack overflow. */
+ for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ * RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include <RTX_lib.c>
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b1edfa2aac5c3042f7d4074268169d758a34cb73
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/makefile
@@ -0,0 +1,101 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+TESTNAME = rtx_demo
+
+CPU_PRODUCT = CORTEX_M0PLUS
+HEXFILE = rtx_demo_cm0.hex
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0)
+ HEXFILE = rtx_demo_cm0.hex
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ HEXFILE = rtx_demo_cm0p.hex
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+hexfile_select:
+ @if [ -e $(HEXFILE) ] ; then \
+ cp $(HEXFILE) rtx_demo.hex ; \
+ fi
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : hexfile_select
+ @if [ -e $(TESTNAME).hex ] ; then \
+ echo "Found rtx_demo.hex ... use existing hex file. Continue ..." ; \
+ else \
+ echo "RTX demo compilation not available for DS-5." ; \
+ echo "Please compile RTX demo in Keil MDK and press ENTER when ready" ; \
+ read dummy ; \
+ fi
+
+# ---------------------------------------------------------------------------------------
+# gcc
+#
+all_gcc: hexfile_select
+ @if [ -e $(TESTNAME).hex ] ; then \
+ echo "Found rtx_demo.hex ... use existing hex file. Continue ..." ; \
+ else \
+ echo "RTX demo compilation not available for gcc." ;\
+ echo "Please compile RTX demo in Keil MDK and press ENTER when ready" ; \
+ read dummy ; \
+ fi
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+ cp $(HEXFILE) rtx_demo.hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.uvgui.*
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo.c b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo.c
new file mode 100644
index 0000000000000000000000000000000000000000..9e885b75073d3519db01d6fb7535dde143710170
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo.c
@@ -0,0 +1,86 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/* Simple demonstration of booting up an RTOS : Keil RTX */
+
+#include <RTL.h>
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+#include <stdio.h>
+#include "uart_stdout.h"
+
+OS_TID t_task1; // Declare a task ID for task1 : Event generator
+OS_TID t_task2; // Declare a task ID for task2 : Event receiver
+int num = 0; // Counter
+
+__task void task1(void) { // Task 1 - Event generator
+ while (1) {
+ os_dly_wait(1);
+ puts("task 1 ->");
+ os_evt_set (0x0001, t_task2); // Send a event 0x0001 to task 2
+ }
+ }
+
+__task void task2(void) { // Task 2 - Event receiver
+ while(1) {
+ os_evt_wait_and (0x0001, 0xffff); // wait for an event flag 0x0001
+ num ++;
+ printf (" task 2, %d\n", num);
+ if (num>=3) { /* Execute 3 times and stop simulation */
+ puts("Tasks ran 3 times.");
+ puts("** TEST PASSED ** \n");
+ UartEndSimulation();
+ }
+ }
+ }
+
+/* Initialize tasks */
+__task void init (void) {
+ t_task1 = os_tsk_create (task1, 1); // Create a task "task1" with priority 1
+ t_task2 = os_tsk_create (task2, 1); // Create a task "task2" with priority 1
+ os_tsk_delete_self ();
+}
+
+
+int main(void)
+{
+ // Starting from CMSIS 1.3,
+ // CMSIS System Initialization function SystemInit() is called from startup code.
+ // So there is no need to call it in here. (This test is based on CMSIS 2.0).
+
+ SysTick->VAL=0; /* Initialize SysTick timer value */
+
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - RTX Demo - revision $Revision: 371321 $\n");
+ puts("- Execute task 1 -> task 2 sequence three times\n");
+
+ os_sys_init(init); // Initialize OS
+} // end main
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.hex b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.hex
new file mode 100644
index 0000000000000000000000000000000000000000..1ab6c31cc0bc29a13f3baf5d4cd2211c4b84252b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.hex
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..ff858fab092fabc01c86864acaec1a8309823c85
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..6c7674df2069da9b99bcec6491ac33d3128b211b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.uvproj
@@ -0,0 +1,440 @@
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+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
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+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>rtx_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\rtx_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
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+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Config.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RTX_Config.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_CMSDK_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.hex b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.hex
new file mode 100644
index 0000000000000000000000000000000000000000..1ab6c31cc0bc29a13f3baf5d4cd2211c4b84252b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.hex
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..a123b288365e6a0009c48f49921a090b06718846
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.uvopt
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+ <FilenameWithoutPath>startup_CMSDK_CM0plus.s</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>26</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>30</TopLine>
+ <CurrentLine>51</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\rtx_demo.c</PathWithFileName>
+ <FilenameWithoutPath>rtx_demo.c</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\RTX_Config.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Config.c</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>6</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0plus.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..2093cada24d805606005ed888c25b112f540b716
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.uvproj
@@ -0,0 +1,437 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0+</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0+") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>6268</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>rtx_demo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output rtx_demo_cm0p.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>1</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>rtx_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\rtx_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Config.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RTX_Config.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c8c4fb60030bba1aa803977acbdbbc141f490bb1
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/makefile
@@ -0,0 +1,251 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = self_reset_demo
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option (DS-5)
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(CORE_DIR) -I $(DEVICE_DIR)/Include \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..5b724566b7d2154a0de1b4a8e7e3373d023b2945
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
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+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\demos\self_reset_demo.c</PathWithFileName>
+ <FilenameWithoutPath>self_reset_demo.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..c4b4745465bd42480bef443962aa86ab4eea8fe3
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>self_reset_demo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output self_reset_demo.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
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+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
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+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
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+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..549db58ebb93c544e87498bca3922050adc54f4a
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0p.uvopt
@@ -0,0 +1,244 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..d891cfcb9df9d62d5d4bc652aa427a6a179e7f38
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/self_reset_demo/self_reset_demo_cm0p.uvproj
@@ -0,0 +1,432 @@
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+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>3</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>self_reset_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\demos\self_reset_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/setup_ds5_tools.scr b/Cortex-M0/nanosoc/systems/mcu/testcodes/setup_ds5_tools.scr
new file mode 100644
index 0000000000000000000000000000000000000000..fa703ecf275a34a6d6a56e3751e5a9931deea1eb
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/setup_ds5_tools.scr
@@ -0,0 +1,6 @@
+export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
+export ARM_TOOL_VARIANT=gold
+export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
+
+
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..504d509072c85d4355c1a58fe3e5b6b535de51cb
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/makefile
@@ -0,0 +1,256 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2010-08-06 12:28:21 +0100 (Fri, 06 Aug 2010) $
+#
+# Revision : $Revision: 145378 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = sleep_demo
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option (DS-5)
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..e742bfa8cc99ceaa227b0601465658dd46efe167
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..e2c4d05390ee0d9e6dd25b6c83b43b68f21caaec
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0.uvproj
@@ -0,0 +1,440 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..f87fdd6d17a4fa4bcc4dfa8eb34ef96f17a6583f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0p.uvopt
@@ -0,0 +1,258 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..02c40bb587fc5c9dd84d92c8fe00dc1973c569f1
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/sleep_demo/sleep_demo_cm0p.uvproj
@@ -0,0 +1,437 @@
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+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>sleep_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\demos\sleep_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7fa0fa3032244c1c609c286bbf5b5500b6936e43
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/makefile
@@ -0,0 +1,254 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-01-25 10:05:56 +0000 (Tue, 25 Jan 2011) $
+#
+# Revision : $Revision: 159421 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = timer_driver_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..6663e83a70aecda0c01c97765d587be412e2796e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
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+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
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+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
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+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
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+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
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+ <File>
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index 0000000000000000000000000000000000000000..a7ff6737334fb2f2e083b13a5348e34e1152e6a2
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+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0p.uvopt
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+ </File>
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+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..2d1ed683f3878f7274301d9b2fa59cc10b1f6543
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0p.uvproj
@@ -0,0 +1,437 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
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+ <StartupFile></StartupFile>
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+ </VariousControls>
+ </Cads>
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+ </VariousControls>
+ </Aads>
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+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>timer_driver_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\timer_driver_tests.c</FilePath>
+ </File>
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+ <FileName>uart_stdout.c</FileName>
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+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
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+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
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+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ </Files>
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+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7133f7f6cde0b9efa08e65171d2b6e04c39b9e4a
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/makefile
@@ -0,0 +1,250 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = timer_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..173dc4009db2842da96fb2c72359ef7f6e716bd6
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
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+ <TargetOption>
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+ </OPTLEX>
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+ <LLibSym>1</LLibSym>
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+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
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+ <Tracepoint>
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+ </Tracepoint>
+ <LintExecutable></LintExecutable>
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+ <RteFlg>0</RteFlg>
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+ <Group>
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+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
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+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..b12e58d07c00c3db9a15371ce50c2a3ecf5c38bf
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
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+ <TargetName>Debug</TargetName>
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+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
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+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output timer_tests.hex</UserProg1Name>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..c4485d5ff65c469301c316107f7a366facd0b38a
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/timer_tests/timer_tests_cm0p.uvopt
@@ -0,0 +1,244 @@
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new file mode 100644
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+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
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+ <AdsLLst>1</AdsLLst>
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+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
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+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
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+ <CodeSel>0</CodeSel>
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+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
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+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
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+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
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+ <Ra3Chk>0</Ra3Chk>
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+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
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+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>timer_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\timer_tests.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1d02777a5643b14d27f3b76f1dd2d1b3b66f6b68
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/makefile
@@ -0,0 +1,255 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-01-25 10:05:56 +0000 (Tue, 25 Jan 2011) $
+#
+# Revision : $Revision: 159421 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = uart_driver_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+CMSDK_driver.o : $(DEVICE_DIR)/Source/CMSDK_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o CMSDK_driver.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/CMSDK_driver.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..dde1fbb702b61e1d34b307540d8c8cb14b3e3901
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvopt
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..3c667aa7ff3d8ea29218d9444e1a676fc9c376c1
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvproj
@@ -0,0 +1,440 @@
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new file mode 100644
index 0000000000000000000000000000000000000000..c2f595cdf32e50dba5f7659f6ae5175cd6120ac2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0p.uvopt
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new file mode 100644
index 0000000000000000000000000000000000000000..cf69fa2e4516339d976b710420481670f22ad58b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0p.uvproj
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+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>uart_driver_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\uart_driver_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>CMSDK_driver.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\CMSDK_driver.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..e645bc46d9c820dd78353683590ffc270777b5e7
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/makefile
@@ -0,0 +1,251 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-01-25 10:05:56 +0000 (Tue, 25 Jan 2011) $
+#
+# Revision : $Revision: 159421 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = uart_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime $(USER_DEFINE) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(SOFTWARE_DIR)/common/retarget
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..2ae0b81c21d8e58d438052208cfb10892cb05e01
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..627ff295474a817ed79d19f3b701f0b3961935df
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0.uvproj
@@ -0,0 +1,435 @@
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+ <ToolsetName>ARM-ADS</ToolsetName>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..583a77ade990adac99f49ea3ba96bc8e00e19ca5
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0p.uvopt
@@ -0,0 +1,244 @@
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+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\validation\uart_tests.c</PathWithFileName>
+ <FilenameWithoutPath>uart_tests.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0plus.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..cbe308e965371c10e6739d798530dd217946fc33
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/uart_tests/uart_tests_cm0p.uvproj
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0+</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0+") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>6268</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>uart_tests</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
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+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output uart_tests.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
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+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
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+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
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+ <AdsLLst>1</AdsLLst>
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+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
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+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
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+ <Ro3Chk>0</Ro3Chk>
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+ <Ra3Chk>0</Ra3Chk>
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+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
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+ </Ocm2>
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+ </Ocm3>
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+ </Ocm5>
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+ </Ocm6>
+ <IRAM>
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+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
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+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\validation\uart_tests.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d7c2ba5713144fb68f72b6aaa2fd430dafcc561d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/makefile
@@ -0,0 +1,250 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+# Shared software directory
+SOFTWARE_DIR = ../../../../software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = watchdog_demo
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option (DS-5)
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..d037b58462203350b98ced76f1e5baae04993599
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvopt
@@ -0,0 +1,261 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>50000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
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+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
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+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>0</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
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+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
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+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Application</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\demos\watchdog_demo.c</PathWithFileName>
+ <FilenameWithoutPath>watchdog_demo.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\uart_stdout.c</PathWithFileName>
+ <FilenameWithoutPath>uart_stdout.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\common\retarget\retarget.c</PathWithFileName>
+ <FilenameWithoutPath>retarget.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..1c90f5d5661b766e998976e1cbdf4942f7c0ff30
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Debug</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>watchdog_demo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>$K\ARM\ARMCC\BIN\fromelf.exe #L --vhx --8x1 --output watchdog_demo.hex</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
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+ <AlwaysBuild>0</AlwaysBuild>
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+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
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+ <RestoreBreakpoints>1</RestoreBreakpoints>
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+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
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+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
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+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
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+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0p.uvopt b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0p.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..5b4434b3c548c3a6ff1ff1865bc7202ef0f35ceb
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0p.uvopt
@@ -0,0 +1,244 @@
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diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0p.uvproj b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0p.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..82c742c0547d058d1df8851c2ca248529fd47f9f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/watchdog_demo/watchdog_demo_cm0p.uvproj
@@ -0,0 +1,432 @@
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+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>CORTEX_M0PLUS</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\..\..\software\cmsis\CMSIS\Include; ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Include; ..\..\..\..\software\common\retarget</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CMSDK_CM0plus.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\ARM\startup_CMSDK_CM0plus.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application</GroupName>
+ <Files>
+ <File>
+ <FileName>watchdog_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\demos\watchdog_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart_stdout.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\uart_stdout.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\common\retarget\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_CMSDK_CM0plus.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0plus\Source\system_CMSDK_CM0plus.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/Cortex-M0/nanosoc/systems/mcu/tools/setup_ds5_tools.scr b/Cortex-M0/nanosoc/systems/mcu/tools/setup_ds5_tools.scr
new file mode 100644
index 0000000000000000000000000000000000000000..477a508b4492fe00ad23b1b2bf82f6f5fefeecce
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/tools/setup_ds5_tools.scr
@@ -0,0 +1,3 @@
+export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
+export ARM_TOOL_VARIANT=gold
+export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
diff --git a/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz b/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz
new file mode 100644
index 0000000000000000000000000000000000000000..182d8c652424d5ed3c4caf2b2d26d32de7d3df16
Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz differ
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/ahb_bootrom.v b/Cortex-M0/nanosoc/systems/mcu/verilog/ahb_bootrom.v
new file mode 100644
index 0000000000000000000000000000000000000000..5031a98de8ff274fb846a9bc902ca595037db7ce
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/ahb_bootrom.v
@@ -0,0 +1,29 @@
+module ahb_bootrom #(
+ // Parameters
+ parameter AW = 10 // Address width
+ )
+ (
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+ input wire HSEL, // Device select
+ input wire [AW-1:0] HADDR, // Address
+ input wire [1:0] HTRANS, // Transfer control
+ input wire [2:0] HSIZE, // Transfer size
+ input wire HWRITE, // Write control
+ input wire [31:0] HWDATA, // Write data - not used
+ input wire HREADY, // Transfer phase done
+ output wire HREADYOUT, // Device ready
+ output wire [31:0] HRDATA, // Read data output
+ output wire HRESP // Device response (always OKAY)
+);
+
+ bootrom u_bootrom (
+ .CLK (HCLK),
+ .EN (HSEL & HTRANS[1] & HREADY & !HWRITE),
+ .ADDR (HADDR[AW-1:2]),
+ .RDATA (HRDATA)
+ );
+ assign HREADYOUT = 1'b1;
+ assign HRESP = 1'b0;
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/bootrom.v b/Cortex-M0/nanosoc/systems/mcu/verilog/bootrom.v
new file mode 100644
index 0000000000000000000000000000000000000000..95919b78af3dcc0a33c06a1b0aadedbd84e976dd
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/bootrom.v
@@ -0,0 +1,277 @@
+//------------------------------------------------------------------------------------
+// customised auto-generated synthesizable ROM module abstraction
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+// Date: 2302101100
+// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
+//------------------------------------------------------------------------------------
+module bootrom (
+ input wire CLK,
+ input wire EN,
+ input wire [9:2] ADDR,
+ output reg [31:0] RDATA );
+reg [9:2] addr_r;
+always @(posedge CLK) if (EN) addr_r <= ADDR;
+always @(addr_r) case(addr_r[9:2])
+ 8'h00 : RDATA <= 32'h30000368; // 0x0000
+ 8'h01 : RDATA <= 32'h10000335; // 0x0004
+ 8'h02 : RDATA <= 32'h1000033d; // 0x0008
+ 8'h03 : RDATA <= 32'h1000033f; // 0x000c
+ 8'h04 : RDATA <= 32'h00000000; // 0x0010
+ 8'h05 : RDATA <= 32'h00000000; // 0x0014
+ 8'h06 : RDATA <= 32'h00000000; // 0x0018
+ 8'h07 : RDATA <= 32'h00000000; // 0x001c
+ 8'h08 : RDATA <= 32'h00000000; // 0x0020
+ 8'h09 : RDATA <= 32'h00000000; // 0x0024
+ 8'h0a : RDATA <= 32'h00000000; // 0x0028
+ 8'h0b : RDATA <= 32'h10000341; // 0x002c
+ 8'h0c : RDATA <= 32'h00000000; // 0x0030
+ 8'h0d : RDATA <= 32'h00000000; // 0x0034
+ 8'h0e : RDATA <= 32'h10000343; // 0x0038
+ 8'h0f : RDATA <= 32'h10000345; // 0x003c
+ 8'h10 : RDATA <= 32'h10000347; // 0x0040
+ 8'h11 : RDATA <= 32'h10000347; // 0x0044
+ 8'h12 : RDATA <= 32'h10000347; // 0x0048
+ 8'h13 : RDATA <= 32'h10000347; // 0x004c
+ 8'h14 : RDATA <= 32'h10000347; // 0x0050
+ 8'h15 : RDATA <= 32'h10000347; // 0x0054
+ 8'h16 : RDATA <= 32'h10000347; // 0x0058
+ 8'h17 : RDATA <= 32'h10000347; // 0x005c
+ 8'h18 : RDATA <= 32'h10000347; // 0x0060
+ 8'h19 : RDATA <= 32'h10000347; // 0x0064
+ 8'h1a : RDATA <= 32'h10000347; // 0x0068
+ 8'h1b : RDATA <= 32'h00000000; // 0x006c
+ 8'h1c : RDATA <= 32'h10000347; // 0x0070
+ 8'h1d : RDATA <= 32'h10000347; // 0x0074
+ 8'h1e : RDATA <= 32'h10000347; // 0x0078
+ 8'h1f : RDATA <= 32'h10000347; // 0x007c
+ 8'h20 : RDATA <= 32'h10000347; // 0x0080
+ 8'h21 : RDATA <= 32'h10000347; // 0x0084
+ 8'h22 : RDATA <= 32'h10000347; // 0x0088
+ 8'h23 : RDATA <= 32'h10000347; // 0x008c
+ 8'h24 : RDATA <= 32'h10000347; // 0x0090
+ 8'h25 : RDATA <= 32'h10000347; // 0x0094
+ 8'h26 : RDATA <= 32'h10000347; // 0x0098
+ 8'h27 : RDATA <= 32'h10000347; // 0x009c
+ 8'h28 : RDATA <= 32'h10000347; // 0x00a0
+ 8'h29 : RDATA <= 32'h10000347; // 0x00a4
+ 8'h2a : RDATA <= 32'h10000347; // 0x00a8
+ 8'h2b : RDATA <= 32'h10000347; // 0x00ac
+ 8'h2c : RDATA <= 32'h10000347; // 0x00b0
+ 8'h2d : RDATA <= 32'h10000347; // 0x00b4
+ 8'h2e : RDATA <= 32'h10000347; // 0x00b8
+ 8'h2f : RDATA <= 32'h10000347; // 0x00bc
+ 8'h30 : RDATA <= 32'hf802f000; // 0x00c0
+ 8'h31 : RDATA <= 32'hf83ef000; // 0x00c4
+ 8'h32 : RDATA <= 32'hc830a00c; // 0x00c8
+ 8'h33 : RDATA <= 32'h18243808; // 0x00cc
+ 8'h34 : RDATA <= 32'h46a2182d; // 0x00d0
+ 8'h35 : RDATA <= 32'h46ab1e67; // 0x00d4
+ 8'h36 : RDATA <= 32'h465d4654; // 0x00d8
+ 8'h37 : RDATA <= 32'hd10142ac; // 0x00dc
+ 8'h38 : RDATA <= 32'hf830f000; // 0x00e0
+ 8'h39 : RDATA <= 32'h3e0f467e; // 0x00e4
+ 8'h3a : RDATA <= 32'h46b6cc0f; // 0x00e8
+ 8'h3b : RDATA <= 32'h42332601; // 0x00ec
+ 8'h3c : RDATA <= 32'h1afbd000; // 0x00f0
+ 8'h3d : RDATA <= 32'h46ab46a2; // 0x00f4
+ 8'h3e : RDATA <= 32'h47184333; // 0x00f8
+ 8'h3f : RDATA <= 32'h000002dc; // 0x00fc
+ 8'h40 : RDATA <= 32'h000002fc; // 0x0100
+ 8'h41 : RDATA <= 32'hd3023a10; // 0x0104
+ 8'h42 : RDATA <= 32'hc178c878; // 0x0108
+ 8'h43 : RDATA <= 32'h0752d8fa; // 0x010c
+ 8'h44 : RDATA <= 32'hc830d301; // 0x0110
+ 8'h45 : RDATA <= 32'hd501c130; // 0x0114
+ 8'h46 : RDATA <= 32'h600c6804; // 0x0118
+ 8'h47 : RDATA <= 32'h00004770; // 0x011c
+ 8'h48 : RDATA <= 32'h24002300; // 0x0120
+ 8'h49 : RDATA <= 32'h26002500; // 0x0124
+ 8'h4a : RDATA <= 32'hd3013a10; // 0x0128
+ 8'h4b : RDATA <= 32'hd8fbc178; // 0x012c
+ 8'h4c : RDATA <= 32'hd3000752; // 0x0130
+ 8'h4d : RDATA <= 32'hd500c130; // 0x0134
+ 8'h4e : RDATA <= 32'h4770600b; // 0x0138
+ 8'h4f : RDATA <= 32'hbd1fb51f; // 0x013c
+ 8'h50 : RDATA <= 32'hbd10b510; // 0x0140
+ 8'h51 : RDATA <= 32'hf915f000; // 0x0144
+ 8'h52 : RDATA <= 32'hf7ff4611; // 0x0148
+ 8'h53 : RDATA <= 32'hf000fff7; // 0x014c
+ 8'h54 : RDATA <= 32'hf000f868; // 0x0150
+ 8'h55 : RDATA <= 32'hb403f92d; // 0x0154
+ 8'h56 : RDATA <= 32'hfff2f7ff; // 0x0158
+ 8'h57 : RDATA <= 32'hf000bc03; // 0x015c
+ 8'h58 : RDATA <= 32'h0000f933; // 0x0160
+ 8'h59 : RDATA <= 32'h68012000; // 0x0164
+ 8'h5a : RDATA <= 32'h6841468d; // 0x0168
+ 8'h5b : RDATA <= 32'h00004708; // 0x016c
+ 8'h5c : RDATA <= 32'h48532141; // 0x0170
+ 8'h5d : RDATA <= 32'h61010149; // 0x0174
+ 8'h5e : RDATA <= 32'h60812101; // 0x0178
+ 8'h5f : RDATA <= 32'h60814851; // 0x017c
+ 8'h60 : RDATA <= 32'h20204951; // 0x0180
+ 8'h61 : RDATA <= 32'h47706188; // 0x0184
+ 8'h62 : RDATA <= 32'h684a494e; // 0x0188
+ 8'h63 : RDATA <= 32'hd1fc07d2; // 0x018c
+ 8'h64 : RDATA <= 32'h07d2684a; // 0x0190
+ 8'h65 : RDATA <= 32'h6008d100; // 0x0194
+ 8'h66 : RDATA <= 32'h494a4770; // 0x0198
+ 8'h67 : RDATA <= 32'h2b007803; // 0x019c
+ 8'h68 : RDATA <= 32'h684ad009; // 0x01a0
+ 8'h69 : RDATA <= 32'hd1fc07d2; // 0x01a4
+ 8'h6a : RDATA <= 32'h07d2684a; // 0x01a8
+ 8'h6b : RDATA <= 32'h600bd100; // 0x01ac
+ 8'h6c : RDATA <= 32'h2b001c40; // 0x01b0
+ 8'h6d : RDATA <= 32'h4770d1f2; // 0x01b4
+ 8'h6e : RDATA <= 32'h4c44b510; // 0x01b8
+ 8'h6f : RDATA <= 32'h48416821; // 0x01bc
+ 8'h70 : RDATA <= 32'hd00a2900; // 0x01c0
+ 8'h71 : RDATA <= 32'h781aa342; // 0x01c4
+ 8'h72 : RDATA <= 32'hd0212a00; // 0x01c8
+ 8'h73 : RDATA <= 32'h07c96841; // 0x01cc
+ 8'h74 : RDATA <= 32'h6841d1fc; // 0x01d0
+ 8'h75 : RDATA <= 32'hd01707c9; // 0x01d4
+ 8'h76 : RDATA <= 32'ha341e017; // 0x01d8
+ 8'h77 : RDATA <= 32'h2a00781a; // 0x01dc
+ 8'h78 : RDATA <= 32'h6841d009; // 0x01e0
+ 8'h79 : RDATA <= 32'hd1fc07c9; // 0x01e4
+ 8'h7a : RDATA <= 32'h07c96841; // 0x01e8
+ 8'h7b : RDATA <= 32'h6002d100; // 0x01ec
+ 8'h7c : RDATA <= 32'h2a001c5b; // 0x01f0
+ 8'h7d : RDATA <= 32'h2204d1f2; // 0x01f4
+ 8'h7e : RDATA <= 32'h07c96841; // 0x01f8
+ 8'h7f : RDATA <= 32'h6841d1fc; // 0x01fc
+ 8'h80 : RDATA <= 32'hd10007c9; // 0x0200
+ 8'h81 : RDATA <= 32'he7fe6002; // 0x0204
+ 8'h82 : RDATA <= 32'h1c5b6002; // 0x0208
+ 8'h83 : RDATA <= 32'hd1da2a00; // 0x020c
+ 8'h84 : RDATA <= 32'h60202000; // 0x0210
+ 8'h85 : RDATA <= 32'h8f4ff3bf; // 0x0214
+ 8'h86 : RDATA <= 32'h8f6ff3bf; // 0x0218
+ 8'h87 : RDATA <= 32'hffa2f7ff; // 0x021c
+ 8'h88 : RDATA <= 32'hb510bd10; // 0x0220
+ 8'h89 : RDATA <= 32'h48262141; // 0x0224
+ 8'h8a : RDATA <= 32'h61010149; // 0x0228
+ 8'h8b : RDATA <= 32'h60812101; // 0x022c
+ 8'h8c : RDATA <= 32'h60814824; // 0x0230
+ 8'h8d : RDATA <= 32'h21204a24; // 0x0234
+ 8'h8e : RDATA <= 32'ha32f6191; // 0x0238
+ 8'h8f : RDATA <= 32'h2a00781a; // 0x023c
+ 8'h90 : RDATA <= 32'h6841d009; // 0x0240
+ 8'h91 : RDATA <= 32'hd1fc07c9; // 0x0244
+ 8'h92 : RDATA <= 32'h07c96841; // 0x0248
+ 8'h93 : RDATA <= 32'h6002d100; // 0x024c
+ 8'h94 : RDATA <= 32'h2a001c5b; // 0x0250
+ 8'h95 : RDATA <= 32'h4c1dd1f2; // 0x0254
+ 8'h96 : RDATA <= 32'h29006821; // 0x0258
+ 8'h97 : RDATA <= 32'ha31cd00a; // 0x025c
+ 8'h98 : RDATA <= 32'h2a00781a; // 0x0260
+ 8'h99 : RDATA <= 32'h6841d021; // 0x0264
+ 8'h9a : RDATA <= 32'hd1fc07c9; // 0x0268
+ 8'h9b : RDATA <= 32'h07c96841; // 0x026c
+ 8'h9c : RDATA <= 32'he017d017; // 0x0270
+ 8'h9d : RDATA <= 32'h781aa31a; // 0x0274
+ 8'h9e : RDATA <= 32'hd0092a00; // 0x0278
+ 8'h9f : RDATA <= 32'h07c96841; // 0x027c
+ 8'ha0 : RDATA <= 32'h6841d1fc; // 0x0280
+ 8'ha1 : RDATA <= 32'hd10007c9; // 0x0284
+ 8'ha2 : RDATA <= 32'h1c5b6002; // 0x0288
+ 8'ha3 : RDATA <= 32'hd1f22a00; // 0x028c
+ 8'ha4 : RDATA <= 32'h68412204; // 0x0290
+ 8'ha5 : RDATA <= 32'hd1fc07c9; // 0x0294
+ 8'ha6 : RDATA <= 32'h07c96841; // 0x0298
+ 8'ha7 : RDATA <= 32'h6002d100; // 0x029c
+ 8'ha8 : RDATA <= 32'h6002e7fe; // 0x02a0
+ 8'ha9 : RDATA <= 32'h2a001c5b; // 0x02a4
+ 8'haa : RDATA <= 32'h2000d1da; // 0x02a8
+ 8'hab : RDATA <= 32'hf3bf6020; // 0x02ac
+ 8'hac : RDATA <= 32'hf3bf8f4f; // 0x02b0
+ 8'had : RDATA <= 32'hf7ff8f6f; // 0x02b4
+ 8'hae : RDATA <= 32'h2000ff55; // 0x02b8
+ 8'haf : RDATA <= 32'h0000bd10; // 0x02bc
+ 8'hb0 : RDATA <= 32'h40006000; // 0x02c0
+ 8'hb1 : RDATA <= 32'h4000e000; // 0x02c4
+ 8'hb2 : RDATA <= 32'h40011000; // 0x02c8
+ 8'hb3 : RDATA <= 32'h4001f000; // 0x02cc
+ 8'hb4 : RDATA <= 32'h52202a2a; // 0x02d0
+ 8'hb5 : RDATA <= 32'h70616d65; // 0x02d4
+ 8'hb6 : RDATA <= 32'h41523e2d; // 0x02d8
+ 8'hb7 : RDATA <= 32'h000a324d; // 0x02dc
+ 8'hb8 : RDATA <= 32'h72724540; // 0x02e0
+ 8'hb9 : RDATA <= 32'h203a726f; // 0x02e4
+ 8'hba : RDATA <= 32'h414d4552; // 0x02e8
+ 8'hbb : RDATA <= 32'h6c632050; // 0x02ec
+ 8'hbc : RDATA <= 32'h65726165; // 0x02f0
+ 8'hbd : RDATA <= 32'h00000a64; // 0x02f4
+ 8'hbe : RDATA <= 32'h530a0a0a; // 0x02f8
+ 8'hbf : RDATA <= 32'h414c434f; // 0x02fc
+ 8'hc0 : RDATA <= 32'h203a5342; // 0x0300
+ 8'hc1 : RDATA <= 32'h204d5241; // 0x0304
+ 8'hc2 : RDATA <= 32'h74726f43; // 0x0308
+ 8'hc3 : RDATA <= 32'h4d2d7865; // 0x030c
+ 8'hc4 : RDATA <= 32'h616e2030; // 0x0310
+ 8'hc5 : RDATA <= 32'h6f736f6e; // 0x0314
+ 8'hc6 : RDATA <= 32'h00000a63; // 0x0318
+ 8'hc7 : RDATA <= 32'h48034904; // 0x031c
+ 8'hc8 : RDATA <= 32'h47706008; // 0x0320
+ 8'hc9 : RDATA <= 32'h48014902; // 0x0324
+ 8'hca : RDATA <= 32'h47706008; // 0x0328
+ 8'hcb : RDATA <= 32'h05f5e100; // 0x032c
+ 8'hcc : RDATA <= 32'h30000000; // 0x0330
+ 8'hcd : RDATA <= 32'h47804807; // 0x0334
+ 8'hce : RDATA <= 32'h47004807; // 0x0338
+ 8'hcf : RDATA <= 32'he7fee7fe; // 0x033c
+ 8'hd0 : RDATA <= 32'he7fee7fe; // 0x0340
+ 8'hd1 : RDATA <= 32'he7fee7fe; // 0x0344
+ 8'hd2 : RDATA <= 32'h49054804; // 0x0348
+ 8'hd3 : RDATA <= 32'h4b064a05; // 0x034c
+ 8'hd4 : RDATA <= 32'h00004770; // 0x0350
+ 8'hd5 : RDATA <= 32'h10000325; // 0x0354
+ 8'hd6 : RDATA <= 32'h100000c1; // 0x0358
+ 8'hd7 : RDATA <= 32'h30000068; // 0x035c
+ 8'hd8 : RDATA <= 32'h30000368; // 0x0360
+ 8'hd9 : RDATA <= 32'h30000168; // 0x0364
+ 8'hda : RDATA <= 32'h30000168; // 0x0368
+ 8'hdb : RDATA <= 32'h47704770; // 0x036c
+ 8'hdc : RDATA <= 32'h46754770; // 0x0370
+ 8'hdd : RDATA <= 32'hf824f000; // 0x0374
+ 8'hde : RDATA <= 32'h000546ae; // 0x0378
+ 8'hdf : RDATA <= 32'h46534669; // 0x037c
+ 8'he0 : RDATA <= 32'h00c008c0; // 0x0380
+ 8'he1 : RDATA <= 32'hb0184685; // 0x0384
+ 8'he2 : RDATA <= 32'hf7ffb520; // 0x0388
+ 8'he3 : RDATA <= 32'hbc60ffdd; // 0x038c
+ 8'he4 : RDATA <= 32'h08492700; // 0x0390
+ 8'he5 : RDATA <= 32'h260046b6; // 0x0394
+ 8'he6 : RDATA <= 32'hc5c0c5c0; // 0x0398
+ 8'he7 : RDATA <= 32'hc5c0c5c0; // 0x039c
+ 8'he8 : RDATA <= 32'hc5c0c5c0; // 0x03a0
+ 8'he9 : RDATA <= 32'hc5c0c5c0; // 0x03a4
+ 8'hea : RDATA <= 32'h00493d40; // 0x03a8
+ 8'heb : RDATA <= 32'h4770468d; // 0x03ac
+ 8'hec : RDATA <= 32'h4604b510; // 0x03b0
+ 8'hed : RDATA <= 32'h46c046c0; // 0x03b4
+ 8'hee : RDATA <= 32'hf7ff4620; // 0x03b8
+ 8'hef : RDATA <= 32'hbd10fecc; // 0x03bc
+ 8'hf0 : RDATA <= 32'h47704800; // 0x03c0
+ 8'hf1 : RDATA <= 32'h30000004; // 0x03c4
+ 8'hf2 : RDATA <= 32'h20184901; // 0x03c8
+ 8'hf3 : RDATA <= 32'he7febeab; // 0x03cc
+ 8'hf4 : RDATA <= 32'h00020026; // 0x03d0
+ 8'hf5 : RDATA <= 32'h00004770; // 0x03d4
+ 8'hf6 : RDATA <= 32'h100003f8; // 0x03d8
+ 8'hf7 : RDATA <= 32'h30000000; // 0x03dc
+ 8'hf8 : RDATA <= 32'h00000004; // 0x03e0
+ 8'hf9 : RDATA <= 32'h10000104; // 0x03e4
+ 8'hfa : RDATA <= 32'h100003fc; // 0x03e8
+ 8'hfb : RDATA <= 32'h30000004; // 0x03ec
+ 8'hfc : RDATA <= 32'h00000364; // 0x03f0
+ 8'hfd : RDATA <= 32'h10000120; // 0x03f4
+ 8'hfe : RDATA <= 32'h05f5e100; // 0x03f8
+ 8'hff : RDATA <= 32'h00000000; // 0x03fc
+ default : RDATA <=32'h0;
+ endcase
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
new file mode 100644
index 0000000000000000000000000000000000000000..505b097314327cc03b6bab280846541e518240a2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
@@ -0,0 +1,272 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2011-11-03 16:07:17 +0000 (Thu, 03 Nov 2011) $
+//
+// Revision : $Revision: 190657 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// This block implements a Generic 4-entry AHB CoreSight ROM Table
+//-----------------------------------------------------------------------------
+//
+// This example block occupies an 4kB space on the AHB bus at the address
+// specified by the BASE[31:0] parameter.
+//
+// BASE[31:0] + 0x1000 +--------------------------------------+
+// | CID: CoreSight ROM Table |
+// |--------------------------------------|
+// | PID: Manufacturer and Partnumber |
+// |--------------------------------------|
+// . .
+// . .
+// . .
+// |--------------------------------------|
+// | Fourth Entry |
+// BASE[31:0] + 0xC |--------------------------------------|
+// | Third Entry |
+// BASE[31:0] + 0x8 |--------------------------------------|
+// | Second Entry |
+// BASE[31:0] + 0x4 |--------------------------------------|
+// | First Entry |
+// BASE[31:0] +--------------------------------------+
+//
+//
+// The ROM table allows debug tools to identify the CoreSight components in
+// a SoC or subsystem, and to identify the manufacturer and part and revision
+// information for the SoC or subsystem.
+// The PID fields include the manufacturer's JEDEC JEP106 identity code and
+// manufacturer-defined partnumber and revision values.
+//
+// Considerations:
+//
+// To allow debug tools to discover the ROM table, it must be pointed to by
+// another ROM table in the system, or by the BASEADDR pointer in the DAP.
+//
+// The ROM table contents must contain correct ID values. To allow for late
+// changes (e.g. metal fixes) to be identified from the ID values, the
+// ECOREVNUM bus should be easily identifiable and modifiable.
+//-----------------------------------------------------------------------------
+
+module cmsdk_ahb_cs_rom_table
+ #(
+ // ------------------------------------------------------------
+ // ROM Table BASE Address
+ // ------------------------------------------------------------
+ parameter [31:0] BASE = 32'h00000000,
+
+ // ------------------------------------------------------------
+ // ROM Table Manufacturer, Part Number and Revision
+ // ------------------------------------------------------------
+ parameter [6:0] JEPID = 7'b0000000, // JEP106 identity code
+ parameter [3:0] JEPCONTINUATION = 4'h0, // number of JEP106
+ // continuation codes
+ parameter [11:0] PARTNUMBER = 12'h000, // part number
+ parameter [3:0] REVISION = 4'h0, // part revision
+
+ // ------------------------------------------------------------
+ // ROM Table entries: (Base Address | Present)
+ // ------------------------------------------------------------
+ parameter [31:0] ENTRY0BASEADDR = 32'h00000000,
+ parameter ENTRY0PRESENT = 1'b0,
+
+ parameter [31:0] ENTRY1BASEADDR = 32'h00000000,
+ parameter ENTRY1PRESENT = 1'b0,
+
+ parameter [31:0] ENTRY2BASEADDR = 32'h00000000,
+ parameter ENTRY2PRESENT = 1'b0,
+
+ parameter [31:0] ENTRY3BASEADDR = 32'h00000000,
+ parameter ENTRY3PRESENT = 1'b0
+ )
+ (
+ input wire HCLK, // AHB clock
+ input wire HSEL, // AHB select
+ input wire [31:0] HADDR, // AHB address
+ input wire [ 2:0] HBURST, // AHB burst
+ input wire HMASTLOCK, // AHB lock
+ input wire [ 3:0] HPROT, // AHB prot
+ input wire [ 2:0] HSIZE, // AHB size
+ input wire [ 1:0] HTRANS, // AHB transfer
+ input wire [31:0] HWDATA, // AHB write data
+ input wire HWRITE, // AHB write
+ input wire HREADY, // AHB ready
+ input wire [ 3:0] ECOREVNUM, // part minor revision (metal fix)
+ output wire [31:0] HRDATA, // AHB read-data
+ output wire HRESP, // AHB response
+ output wire HREADYOUT); // AHB ready out
+
+ // ------------------------------------------------------------
+ // Local wires
+ // ------------------------------------------------------------
+ reg [ 9:0] haddr_reg;
+ wire [31:0] rdata;
+
+
+ // ------------------------------------------------------------
+ // ROM Tables
+ // ------------------------------------------------------------
+
+ //
+ // ROM Table Entry Calculation:
+ //
+ // Ref: ARM IHI0029B CoreSight Architecture Specification
+ //
+ // ROM table entry format:
+ // [31:12] Address Offset. Base address of highest 4KB block relative to ROM
+ // table address.
+ // [11: 2] RESERVED, RAZ
+ // [1] Format. 1=32-bit format
+ // [0] Entry Present.
+ //
+ // ComponentAddress = ROMAddress + (AddressOffset SHL 12)
+ //
+
+ // Calculate address offset values
+ localparam [19:0] ENTRY0OFFSET = ENTRY0BASEADDR[31:12] - BASE[31:12];
+ localparam [19:0] ENTRY1OFFSET = ENTRY1BASEADDR[31:12] - BASE[31:12];
+ localparam [19:0] ENTRY2OFFSET = ENTRY2BASEADDR[31:12] - BASE[31:12];
+ localparam [19:0] ENTRY3OFFSET = ENTRY3BASEADDR[31:12] - BASE[31:12];
+
+ // Construct entries
+ localparam [31:0] ENTRY0 = { ENTRY0OFFSET, 10'b0, 1'b1, ENTRY0PRESENT!=0 };
+ localparam [31:0] ENTRY1 = { ENTRY1OFFSET, 10'b0, 1'b1, ENTRY1PRESENT!=0 };
+ localparam [31:0] ENTRY2 = { ENTRY2OFFSET, 10'b0, 1'b1, ENTRY2PRESENT!=0 };
+ localparam [31:0] ENTRY3 = { ENTRY3OFFSET, 10'b0, 1'b1, ENTRY3PRESENT!=0 };
+
+
+ // ------------------------------------------------------------
+ // AHB Interface
+ // ------------------------------------------------------------
+ wire trans_valid = HSEL & HTRANS[1] & HREADY;
+
+ always @(posedge HCLK)
+ if (trans_valid)
+ haddr_reg[9:0] <= HADDR[11:2];
+
+ assign HREADYOUT = 1'b1;
+ assign HRDATA = rdata;
+ assign HRESP = 1'b0;
+
+ wire [11:0] word_addr = {haddr_reg, 2'b00};
+
+ // Make unused AHB-Lite signals obvious for Lint purposes
+ wire [66:0] unused = { HADDR[31:12], HADDR[1:0], HBURST[2:0], HMASTLOCK,
+ HPROT[3:0], HSIZE[2:0], HTRANS[0], HWDATA[31:0],
+ HWRITE };
+
+
+ // ------------------------------------------------------------
+ // ROM Table Content
+ // ------------------------------------------------------------
+
+ wire cid3_en = (word_addr[11:0] == 12'hFFC);
+ wire cid2_en = (word_addr[11:0] == 12'hFF8);
+ wire cid1_en = (word_addr[11:0] == 12'hFF4);
+ wire cid0_en = (word_addr[11:0] == 12'hFF0);
+
+ wire pid7_en = (word_addr[11:0] == 12'hFDC);
+ wire pid6_en = (word_addr[11:0] == 12'hFD8);
+ wire pid5_en = (word_addr[11:0] == 12'hFD4);
+ wire pid4_en = (word_addr[11:0] == 12'hFD0);
+ wire pid3_en = (word_addr[11:0] == 12'hFEC);
+ wire pid2_en = (word_addr[11:0] == 12'hFE8);
+ wire pid1_en = (word_addr[11:0] == 12'hFE4);
+ wire pid0_en = (word_addr[11:0] == 12'hFE0);
+
+ wire systemaccess_en = (word_addr[11:0] == 12'hFCC);
+
+ wire entry0_en = (word_addr[11:0] == 12'h000);
+ wire entry1_en = (word_addr[11:0] == 12'h004);
+ wire entry2_en = (word_addr[11:0] == 12'h008);
+ wire entry3_en = (word_addr[11:0] == 12'h00C);
+
+ wire [7:0] ids =
+ ( ( {8{cid3_en}} & 8'hB1 ) | // CID3 : Rom Table
+ ( {8{cid2_en}} & 8'h05 ) | // CID2 : Rom Table
+ ( {8{cid1_en}} & 8'h10 ) | // CID1 : Rom Table
+ ( {8{cid0_en}} & 8'h0D ) | // CID0 : Rom Table
+
+ ( {8{pid7_en}} & 8'h00 ) | // PID7 : RESERVED
+ ( {8{pid6_en}} & 8'h00 ) | // PID6 : RESERVED
+ ( {8{pid5_en}} & 8'h00 ) | // PID5 : RESERVED
+ ( {8{pid4_en}} & { {4{1'b0}}, JEPCONTINUATION[3:0] } ) |
+ ( {8{pid3_en}} & { ECOREVNUM[3:0], {4{1'b0}} } ) |
+ ( {8{pid2_en}} & { REVISION[3:0], 1'b1, JEPID[6:4] } ) |
+ ( {8{pid1_en}} & { JEPID[3:0], PARTNUMBER[11:8] } ) |
+ ( {8{pid0_en}} & PARTNUMBER[7:0] )
+ );
+
+ //
+ // Assign Read Data. Default value of 32'h00000000
+ // corresponds to the End Of Table marker.
+ //
+ assign rdata[31:0] =
+ ( ( {{24{1'b0}}, ids[7:0] } ) |
+ ( {32{systemaccess_en}} & 32'h00000001 ) |
+ // Pointers to CoreSight Components
+ ( {32{entry0_en}} & ENTRY0[31:0] ) |
+ ( {32{entry1_en}} & ENTRY1[31:0] ) |
+ ( {32{entry2_en}} & ENTRY2[31:0] ) |
+ ( {32{entry3_en}} & ENTRY3[31:0] )
+ );
+
+ // -------------------------------------------------------------------------
+
+`ifdef ARM_ASSERT_ON
+
+ // -------------------------------------------------------------------------
+ // Assertions
+ // -------------------------------------------------------------------------
+
+ `include "std_ovl_defines.h"
+
+
+ // Addresses must always be 4KB aligned
+ assert_never
+ #(`OVL_FATAL,`OVL_ASSERT,"Rom Table BASE must be 4K aligned")
+ u_asrt_rom_table_base_alignment
+ (.clk(HCLK), .reset_n(1'b1), .test_expr(|BASE[11:0]));
+
+ // Addresses must always be 4KB aligned
+ assert_never
+ #(`OVL_FATAL,`OVL_ASSERT,"Rom Table ENTRY0BASEADDR must be 4K aligned")
+ u_asrt_rom_table_entry0_alignment
+ (.clk(HCLK), .reset_n(1'b1), .test_expr(|ENTRY0BASEADDR[11:0]));
+
+ // Addresses must always be 4KB aligned
+ assert_never
+ #(`OVL_FATAL,`OVL_ASSERT,"Rom Table ENTRY1BASEADDR must be 4K aligned")
+ u_asrt_rom_table_entry1_alignment
+ (.clk(HCLK), .reset_n(1'b1), .test_expr(|ENTRY1BASEADDR[11:0]));
+
+ // Addresses must always be 4KB aligned
+ assert_never
+ #(`OVL_FATAL,`OVL_ASSERT,"Rom Table ENTRY2BASEADDR must be 4K aligned")
+ u_asrt_rom_table_entry2_alignment
+ (.clk(HCLK), .reset_n(1'b1), .test_expr(|ENTRY2BASEADDR[11:0]));
+
+ // Addresses must always be 4KB aligned
+ assert_never
+ #(`OVL_FATAL,`OVL_ASSERT,"Rom Table ENTRY3BASEADDR must be 4K aligned")
+ u_asrt_rom_table_entry3_alignment
+ (.clk(HCLK), .reset_n(1'b1), .test_expr(|ENTRY3BASEADDR[11:0]));
+
+`endif
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v
new file mode 100644
index 0000000000000000000000000000000000000000..f695ecc23108654e6983c19fdd5e9ad049a6cd25
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v
@@ -0,0 +1,1159 @@
+//-----------------------------------------------------------------------------
+// customised top-level example Cortex-M0 controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple APB UART
+//-----------------------------------------------------------------------------
+//-------------------------------------
+// Programmer's model
+// 0x00 R RXD[7:0] Received Data
+// W TXD[7:0] Transmit data
+// 0x04 RW STAT[3:0]
+// [3] RX buffer overrun (write 1 to clear)
+// [2] TX buffer overrun (write 1 to clear)
+// [1] RX buffer full (Read only)
+// [0] TX buffer full (Read only)
+// 0x08 RW CTRL[3:0] TxIntEn, RxIntEn, TxEn, RxEn
+// [6] High speed test mode Enable
+// [5] RX overrun interrupt enable
+// [4] TX overrun interrupt enable
+// [3] RX Interrupt Enable
+// [2] TX Interrupt Enable
+// [1] RX Enable
+// [0] TX Enable
+// 0x0C R/Wc intr_status/INTCLEAR
+// [3] RX overrun interrupt
+// [2] TX overrun interrupt
+// [1] RX interrupt
+// [0] TX interrupt
+// 0x10 RW BAUDDIV[19:0] Baud divider
+// (minimum value is 16)
+// 0x3E0 - 0x3FC ID registers
+//-------------------------------------
+
+module cmsdk_apb_usrt (
+// --------------------------------------------------------------------------
+// Port Definitions
+// --------------------------------------------------------------------------
+ input wire PCLK, // Clock
+ input wire PCLKG, // Gated Clock
+ input wire PRESETn, // Reset
+
+ input wire PSEL, // Device select
+ input wire [11:2] PADDR, // Address
+ input wire PENABLE, // Transfer control
+ input wire PWRITE, // Write control
+ input wire [31:0] PWDATA, // Write data
+
+ input wire [3:0] ECOREVNUM,// Engineering-change-order revision bits
+
+ output wire [31:0] PRDATA, // Read data
+ output wire PREADY, // Device ready
+ output wire PSLVERR, // Device error response
+
+ output wire TX_VALID_o,
+ output wire [7:0] TX_DATA8_o,
+ input wire TX_READY_i,
+
+ input wire RX_VALID_i,
+ input wire [7:0] RX_DATA8_i,
+ output wire RX_READY_o,
+
+ output wire TXINT, // Transmit Interrupt
+ output wire RXINT, // Receive Interrupt
+ output wire TXOVRINT, // Transmit overrun Interrupt
+ output wire RXOVRINT, // Receive overrun Interrupt
+ output wire UARTINT); // Combined interrupt
+
+// Local ID parameters, APB UART part number is 0x821
+localparam ARM_CMSDK_APB_UART_PID4 = 8'h04;
+localparam ARM_CMSDK_APB_UART_PID5 = 8'h00;
+localparam ARM_CMSDK_APB_UART_PID6 = 8'h00;
+localparam ARM_CMSDK_APB_UART_PID7 = 8'h00;
+localparam ARM_CMSDK_APB_UART_PID0 = 8'h21;
+localparam ARM_CMSDK_APB_UART_PID1 = 8'hB8;
+localparam ARM_CMSDK_APB_UART_PID2 = 8'h1B;
+localparam ARM_CMSDK_APB_UART_PID3 = 4'h0;
+localparam ARM_CMSDK_APB_UART_CID0 = 8'h0D;
+localparam ARM_CMSDK_APB_UART_CID1 = 8'hF0;
+localparam ARM_CMSDK_APB_UART_CID2 = 8'h05;
+localparam ARM_CMSDK_APB_UART_CID3 = 8'hB1;
+
+// original external IOs
+wire RXD = 1'b1; // Serial input
+wire TXD; // Transmit data output
+wire TXEN; // Transmit enabled
+wire BAUDTICK; // Baud rate (x16) Tick
+
+
+ // --------------------------------------------------------------------------
+ // Internal wires
+ // --------------------------------------------------------------------------
+// Signals for read/write controls
+wire read_enable;
+wire write_enable;
+wire write_enable00; // Write enable for data register
+wire write_enable04; // Write enable for Status register
+wire write_enable08; // Write enable for control register
+wire write_enable0c; // Write enable for interrupt status register
+wire write_enable10; // Write enable for Baud rate divider
+reg [7:0] read_mux_byte0; // Read data multiplexer for lower 8-bit
+reg [7:0] read_mux_byte0_reg; // Register read data for lower 8-bit
+wire [31:0] read_mux_word; // Read data multiplexer for whole 32-bit
+wire [3:0] pid3_value; // constant value for lower 4-bit in perpherial ID3
+
+// Signals for Control registers
+reg [6:0] reg_ctrl; // Control register
+reg [7:0] reg_tx_buf; // Transmit data buffer
+reg [7:0] reg_rx_buf; // Receive data buffer
+reg [19:0] reg_baud_div; // Baud rate setting
+
+// Internal signals
+ // Baud rate divider
+reg [15:0] reg_baud_cntr_i; // baud rate divider counter i (integer)
+wire [15:0] nxt_baud_cntr_i;
+reg [3:0] reg_baud_cntr_f; // baud rate divider counter f (fraction)
+wire [3:0] nxt_baud_cntr_f;
+wire [3:0] mapped_cntr_f; // remapped counter f value
+reg reg_baud_tick; // Register baud rate tick (16 times of baud rate)
+reg baud_updated; // baud rate value has bee updated from APB
+wire reload_i; // baud rate divider counter i reload
+wire reload_f; // baud rate divider counter f reload
+wire baud_div_en; // enable baud rate counter
+
+ // Status
+wire [3:0] uart_status; // UART status
+reg reg_rx_overrun; // Receive overrun status register
+wire rx_overrun; // Receive overrun detection
+reg reg_tx_overrun; // Transmit overrun status register
+wire tx_overrun; // Transmit overrun detection
+wire nxt_rx_overrun; // next state for reg_rx_overrun
+wire nxt_tx_overrun; // next state for reg_tx_overrun
+ // Interrupts
+reg reg_txintr; // Transmit interrupt register
+reg reg_rxintr; // Receive interrupt register
+wire tx_overflow_intr;// Transmit overrun/overflow interrupt
+wire rx_overflow_intr;// Receive overrun/overflow interrupt
+wire [3:0] intr_state; // UART interrupt status
+wire [1:0] intr_stat_set; // Set TX/RX interrupt
+wire [1:0] intr_stat_clear; // Clear TX/RX interrupt
+
+ // transmit
+reg [3:0] tx_state; // Transmit FSM state
+reg [4:0] nxt_tx_state;
+wire tx_state_update;
+wire tx_state_inc; // Bit pulse
+reg [3:0] tx_tick_cnt; // Transmit Tick counter
+wire [4:0] nxt_tx_tick_cnt;
+reg [7:0] tx_shift_buf; // Transmit shift register
+wire [7:0] nxt_tx_shift_buf; // next state for tx_shift_buf
+wire tx_buf_ctrl_shift; // shift control for tx_shift_buf
+wire tx_buf_ctrl_load; // load control for tx_shift_buf
+reg tx_buf_full; // TX Buffer full
+reg reg_txd; // Tx Data
+wire nxt_txd; // next state of reg_txd
+wire update_reg_txd; // update reg_txd
+wire tx_buf_clear; // Clear buffer full status when data is load into TX shift register
+
+ // Receive data sync and filter
+reg rxd_sync_1; // Double flip-flop syncrhoniser
+reg rxd_sync_2; // Double flip-flop syncrhoniser
+reg [2:0] rxd_lpf; // Averaging Low Pass Filter
+wire [2:0] nxt_rxd_lpf;
+wire rx_shift_in; // Shift Register Input
+
+ // Receiver
+reg [3:0] rx_state; // Receiver FSM state
+reg [4:0] nxt_rx_state;
+wire rx_state_update;
+reg [3:0] rx_tick_cnt; // Receiver Tick counter
+wire [4:0] nxt_rx_tick_cnt;
+wire update_rx_tick_cnt;
+wire rx_state_inc;// Bit pulse
+reg [6:0] rx_shift_buf;// Receiver shift data register
+wire [6:0] nxt_rx_shift_buf;
+reg rx_buf_full; // Receive buffer full status
+wire nxt_rx_buf_full;
+wire rxbuf_sample; // Sample received data into receive data buffer
+wire rx_data_read; // Receive data buffer read by APB interface
+wire [7:0] nxt_rx_buf;
+
+// Start of main code
+// Read and write control signals
+assign read_enable = PSEL & (~PWRITE); // assert for whole APB read transfer
+assign write_enable = PSEL & (~PENABLE) & PWRITE; // assert for 1st cycle of write transfer
+assign write_enable00 = write_enable & (PADDR[11:2] == 10'h000);
+assign write_enable04 = write_enable & (PADDR[11:2] == 10'h001);
+assign write_enable08 = write_enable & (PADDR[11:2] == 10'h002);
+assign write_enable0c = write_enable & (PADDR[11:2] == 10'h003);
+assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
+
+// Write operations
+ // Transmit data register
+ always @(posedge PCLKG or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_tx_buf <= {8{1'b0}};
+ else if (write_enable00)
+ reg_tx_buf <= PWDATA[7:0];
+ end
+
+ assign TX_DATA8_o = reg_tx_buf[7:0];
+
+ // Status register overrun registers
+ assign nxt_rx_overrun = (reg_rx_overrun & (~((write_enable04|write_enable0c) & PWDATA[3]))) | rx_overrun;
+ assign nxt_tx_overrun = (reg_tx_overrun & (~((write_enable04|write_enable0c) & PWDATA[2]))) | tx_overrun;
+
+ // RX OverRun status
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_rx_overrun <= 1'b0;
+ else if (rx_overrun | write_enable04 | write_enable0c)
+ reg_rx_overrun <= nxt_rx_overrun;
+ end
+
+ // TX OverRun status
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_tx_overrun <= 1'b0;
+ else if (tx_overrun | write_enable04 | write_enable0c)
+ reg_tx_overrun <= nxt_tx_overrun;
+ end
+
+ // Control register
+ always @(posedge PCLKG or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_ctrl <= {7{1'b0}};
+ else if (write_enable08)
+ reg_ctrl <= PWDATA[6:0];
+ end
+
+ // Baud rate divider - integer
+ always @(posedge PCLKG or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_baud_div <= {20{1'b0}};
+ else if (write_enable10)
+ reg_baud_div <= PWDATA[19:0];
+ end
+
+// Read operation
+ assign uart_status = {reg_rx_overrun, reg_tx_overrun, rx_buf_full, tx_buf_full};
+
+ assign pid3_value = ARM_CMSDK_APB_UART_PID3;
+
+ // First level of read mux
+ always @(PADDR or reg_rx_buf or uart_status or reg_ctrl or intr_state or reg_baud_div
+ or ECOREVNUM or pid3_value)
+ begin
+ if (PADDR[11:5] == 7'h00) begin
+ case (PADDR[4:2])
+ 3'h0: read_mux_byte0 = reg_rx_buf;
+ 3'h1: read_mux_byte0 = {{4{1'b0}},uart_status};
+ 3'h2: read_mux_byte0 = {{1{1'b0}},reg_ctrl};
+ 3'h3: read_mux_byte0 = {{4{1'b0}},intr_state};
+ 3'h4: read_mux_byte0 = reg_baud_div[7:0];
+ 3'h5, 3'h6, 3'h7: read_mux_byte0 = {8{1'b0}}; //default read out value
+ default: read_mux_byte0 = {8{1'bx}};// x propogation
+ endcase
+ end
+ else if (PADDR[11:6] == 6'h3F) begin
+ case (PADDR[5:2])
+ 4'h0, 4'h1,4'h2,4'h3: read_mux_byte0 = {8{1'b0}}; //default read out value
+ // ID register - constant values
+ 4'h4: read_mux_byte0 = ARM_CMSDK_APB_UART_PID4; // 0xFD0 : PID 4
+ 4'h5: read_mux_byte0 = ARM_CMSDK_APB_UART_PID5; // 0xFD4 : PID 5
+ 4'h6: read_mux_byte0 = ARM_CMSDK_APB_UART_PID6; // 0xFD8 : PID 6
+ 4'h7: read_mux_byte0 = ARM_CMSDK_APB_UART_PID7; // 0xFDC : PID 7
+ 4'h8: read_mux_byte0 = ARM_CMSDK_APB_UART_PID0; // 0xFE0 : PID 0 APB UART part number[7:0]
+ 4'h9: read_mux_byte0 = ARM_CMSDK_APB_UART_PID1; // 0xFE0 : PID 1 [7:4] jep106_id_3_0. [3:0] part number [11:8]
+ 4'hA: read_mux_byte0 = ARM_CMSDK_APB_UART_PID2; // 0xFE0 : PID 2 [7:4] revision, [3] jedec_used. [2:0] jep106_id_6_4
+ 4'hB: read_mux_byte0 = {ECOREVNUM[3:0],pid3_value[3:0]};
+ // 0xFE0 : PID 3 [7:4] ECO revision, [3:0] modification number
+ 4'hC: read_mux_byte0 = ARM_CMSDK_APB_UART_CID0; // 0xFF0 : CID 0
+ 4'hD: read_mux_byte0 = ARM_CMSDK_APB_UART_CID1; // 0xFF4 : CID 1 PrimeCell class
+ 4'hE: read_mux_byte0 = ARM_CMSDK_APB_UART_CID2; // 0xFF8 : CID 2
+ 4'hF: read_mux_byte0 = ARM_CMSDK_APB_UART_CID3; // 0xFFC : CID 3
+ default : read_mux_byte0 = {8{1'bx}}; // x propogation
+ endcase
+ end
+ else begin
+ read_mux_byte0 = {8{1'b0}}; //default read out value
+ end
+ end
+
+
+
+ // Register read data
+ always @(posedge PCLKG or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ read_mux_byte0_reg <= {8{1'b0}};
+ else if (read_enable)
+ read_mux_byte0_reg <= read_mux_byte0;
+ end
+
+ // Second level of read mux
+ assign read_mux_word[ 7: 0] = read_mux_byte0_reg;
+ assign read_mux_word[19: 8] = (PADDR[11:2]==10'h004) ? reg_baud_div[19:8] : {12{1'b0}};
+ assign read_mux_word[31:20] = {12{1'b0}};
+
+
+ // Output read data to APB
+ assign PRDATA[31: 0] = (read_enable) ? read_mux_word : {32{1'b0}};
+ assign PREADY = 1'b1; // Always ready
+ assign PSLVERR = 1'b0; // Always okay
+
+// --------------------------------------------
+// Baud rate generator
+ // Baud rate generator enable
+ assign baud_div_en = (reg_ctrl[1:0] != 2'b00);
+ assign mapped_cntr_f = {reg_baud_cntr_f[0],reg_baud_cntr_f[1],
+ reg_baud_cntr_f[2],reg_baud_cntr_f[3]};
+ // Reload Integer divider
+ // when UART enabled and (reg_baud_cntr_f < reg_baud_div[3:0])
+ // then count to 1, or
+ // when UART enabled then count to 0
+ assign reload_i = (baud_div_en &
+ (((mapped_cntr_f >= reg_baud_div[3:0]) &
+ (reg_baud_cntr_i[15:1] == {15{1'b0}})) |
+ (reg_baud_cntr_i[15:0] == {16{1'b0}})));
+
+ // Next state for Baud rate divider
+ assign nxt_baud_cntr_i = (baud_updated | reload_i) ? reg_baud_div[19:4] :
+ (reg_baud_cntr_i - 16'h0001);
+ // Update at reload or decrement
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_baud_cntr_i <= {16{1'b0}};
+ else if (baud_updated | baud_div_en)
+ reg_baud_cntr_i <= nxt_baud_cntr_i;
+ end
+
+ // Reload fraction divider
+ assign reload_f = baud_div_en & (reg_baud_cntr_f==4'h0) &
+ reload_i;
+ // Next state for fraction part of Baud rate divider
+ assign nxt_baud_cntr_f =
+ (reload_f|baud_updated) ? 4'hF :
+ (reg_baud_cntr_f - 4'h1);
+
+ // Update at reload or decrement
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_baud_cntr_f <= {4{1'b0}};
+ else if (baud_updated | reload_f | reload_i)
+ reg_baud_cntr_f <= nxt_baud_cntr_f;
+ end
+
+ // Generate control signal to update baud rate counters
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ baud_updated <= 1'b0;
+ else if (write_enable10 | baud_updated)
+ // Baud rate updated - to load new value to counters
+ baud_updated <= write_enable10;
+ end
+
+ // Generate Tick signal for external logic
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_baud_tick <= 1'b0;
+ else if (reload_i | reg_baud_tick)
+ reg_baud_tick <= reload_i;
+ end
+
+ // Connect to external
+ assign BAUDTICK = reg_baud_tick;
+
+// --------------------------------------------
+// Transmit
+
+ // Buffer full status
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ tx_buf_full <= 1'b0;
+ else if (write_enable00) // | tx_buf_clear)
+ tx_buf_full <= write_enable00;
+ else if (tx_buf_full & TX_READY_i) // AXI stream ack
+ tx_buf_full <= 0;
+ end
+
+ assign TX_VALID_o = tx_buf_full;
+
+ // Increment TickCounter
+ assign nxt_tx_tick_cnt = ((tx_state==4'h1) & reg_baud_tick) ? {5{1'b0}} :
+ tx_tick_cnt + {{3{1'b0}},reg_baud_tick};
+
+ // Registering TickCounter
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ tx_tick_cnt <= {4{1'b0}};
+ else if (reg_baud_tick)
+ tx_tick_cnt <= nxt_tx_tick_cnt[3:0];
+ end
+
+ // Increment state (except Idle(0) and Wait for Tick(1))
+ assign tx_state_inc = (((&tx_tick_cnt)|(tx_state==4'h1)) & reg_baud_tick)|reg_ctrl[6];
+ // state increment every cycle of high speed test mode is enabled
+ // Clear buffer full status when data is load into shift register
+ assign tx_buf_clear = ((tx_state==4'h0) & tx_buf_full) |
+ ((tx_state==4'hB) & tx_buf_full & tx_state_inc);
+
+ // tx_state machine
+ // 0 = Idle, 1 = Wait for Tick,
+ // 2 = Start bit, 3 = D0 .... 10 = D7
+ // 11 = Stop bit
+ always @(tx_state or tx_buf_full or tx_state_inc or reg_ctrl)
+ begin
+ case (tx_state)
+ 0: begin
+ nxt_tx_state = (tx_buf_full & reg_ctrl[0]) ? 5'h01 : 5'h00; // New data is written to buffer
+ end
+ 1, // State 1 : Wait for next Tick
+ 2,3,4,5,6,7,8,9,10: begin // State 2-10: Start bit, D0 - D7
+ nxt_tx_state = tx_state + {3'b000,tx_state_inc};
+ end
+ 11: begin // Stop bit , goto next start bit or Idle
+ nxt_tx_state = (tx_state_inc) ? ( tx_buf_full ? 5'h02:5'h00) : {1'b0, tx_state};
+ end
+ default:
+ nxt_tx_state = {5{1'bx}};
+ endcase
+ end
+
+ assign tx_state_update = tx_state_inc | ((tx_state==4'h0) & tx_buf_full & reg_ctrl[0]) | (tx_state>4'd11);
+
+ // Registering outputs
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ tx_state <= {4{1'b0}};
+ else if (tx_state_update)
+ tx_state <= nxt_tx_state[3:0];
+ end
+
+ // Load/shift TX register
+ assign tx_buf_ctrl_load = (((tx_state==4'h0) & tx_buf_full) |
+ ((tx_state==4'hB) & tx_buf_full & tx_state_inc));
+ assign tx_buf_ctrl_shift = ((tx_state>4'h2) & tx_state_inc);
+
+ assign nxt_tx_shift_buf = tx_buf_ctrl_load ? reg_tx_buf[7:0] : {1'b1,tx_shift_buf[7:1]};
+
+ // Registering TX shift register
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ tx_shift_buf <= {8{1'b0}};
+ else if (tx_buf_ctrl_shift | tx_buf_ctrl_load)
+ tx_shift_buf <= nxt_tx_shift_buf;
+ end
+
+ // Data output
+ assign nxt_txd = (tx_state==4'h2) ? 1'b0 :
+ (tx_state>4'h2) ? tx_shift_buf[0] : 1'b1;
+
+ assign update_reg_txd = (nxt_txd != reg_txd);
+
+ // Registering outputs
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_txd <= 1'b1;
+ else if (update_reg_txd)
+ reg_txd <= nxt_txd;
+ end
+
+ // Generate TX overrun error status
+ assign tx_overrun = tx_buf_full & (~tx_buf_clear) & write_enable00;
+
+ // Connect to external
+ assign TXD = reg_txd;
+ assign TXEN = reg_ctrl[0];
+
+// --------------------------------------------
+// Receive synchronizer and low pass filter
+
+ // Doubling Flip-flop synxt_rx_tick_cntnchroniser
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ begin
+ rxd_sync_1 <= 1'b1;
+ rxd_sync_2 <= 1'b1;
+ end
+ else if (reg_ctrl[1]) // Turn off synchronizer if receive is not enabled
+ begin
+ rxd_sync_1 <= RXD;
+ rxd_sync_2 <= rxd_sync_1;
+ end
+ end
+
+ // Averaging low pass filter
+ assign nxt_rxd_lpf = {rxd_lpf[1:0], rxd_sync_2};
+ // Registering stage for low pass filter
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ rxd_lpf <= 3'b111;
+ else if (reg_baud_tick)
+ rxd_lpf <= nxt_rxd_lpf;
+ end
+
+ // Averaging values
+ assign rx_shift_in = (rxd_lpf[1] & rxd_lpf[0]) |
+ (rxd_lpf[1] & rxd_lpf[2]) |
+ (rxd_lpf[0] & rxd_lpf[2]);
+
+// --------------------------------------------
+// Receive
+
+ // Increment TickCounter
+ assign nxt_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) ? 5'h08 :
+ rx_tick_cnt + {{3{1'b0}},reg_baud_tick};
+
+ assign update_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) | reg_baud_tick;
+
+ // Registering other register
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ rx_tick_cnt <= {4{1'b0}};
+ else if (update_rx_tick_cnt)
+ rx_tick_cnt <= nxt_rx_tick_cnt[3:0];
+ end
+
+ // Increment state
+ assign rx_state_inc = ((&rx_tick_cnt) & reg_baud_tick);
+ // Buffer full status
+ assign nxt_rx_buf_full = rxbuf_sample | (rx_buf_full & (~rx_data_read));
+
+ // Sample shift register when D7 is sampled
+/// assign rxbuf_sample = ((rx_state==4'h9) & rx_state_inc);
+ assign rxbuf_sample = RX_VALID_i & !rx_buf_full;
+
+ // Reading receive buffer (Set at 1st cycle of APB transfer
+ // because read mux is registered before output)
+ assign rx_data_read = (PSEL & (~PENABLE) & (PADDR[11:2]==10'h000) & (~PWRITE));
+ // Generate RX overrun error status
+ assign rx_overrun = rx_buf_full & rxbuf_sample & (~rx_data_read);
+
+ // rx_state machine
+ // 0 = Idle, 1 = Start of Start bit detected
+ // 2 = Sample Start bit, 3 = D0 .... 10 = D7
+ // 11 = Stop bit
+ // 11, 12, 13, 14, 15: illegal/unused states
+ always @(rx_state or rx_shift_in or rx_state_inc or reg_ctrl)
+ begin
+ case (rx_state)
+ 0: begin
+ nxt_rx_state = ((~rx_shift_in) & reg_ctrl[1]) ? 5'h01 : 5'h00; // Wait for Start bit
+ end
+ 1, // State 1 : Wait for middle of start bit
+ 2,3,4,5,6,7,8,9: begin // State 2-9: D0 - D7
+ nxt_rx_state = rx_state + {3'b000,rx_state_inc};
+ end
+ 10: begin // Stop bit , goto back to Idle
+ nxt_rx_state = (rx_state_inc) ? 5'h00 : 5'h0A;
+ end
+ default:
+ nxt_rx_state = {5{1'bx}};
+ endcase
+ end
+
+ assign rx_state_update = rx_state_inc | ((~rx_shift_in) & reg_ctrl[1]);
+
+ // Registering rx_state
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ rx_state <= {4{1'b0}};
+ else if (rx_state_update)
+ rx_state <= nxt_rx_state[3:0];
+ end
+
+ // Buffer full status
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ rx_buf_full <= 1'b0;
+ else if (rxbuf_sample | rx_data_read)
+ rx_buf_full <= nxt_rx_buf_full;
+ end
+
+ // Sample receive buffer
+/// assign nxt_rx_buf = {rx_shift_in, rx_shift_buf};
+ assign nxt_rx_buf = RX_DATA8_i[7:0];
+
+ // Registering receive data buffer
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_rx_buf <= {8{1'b0}};
+ else if (rxbuf_sample)
+ reg_rx_buf <= nxt_rx_buf;
+ end
+
+ // Shift register
+ assign nxt_rx_shift_buf= {rx_shift_in, rx_shift_buf[6:1]};
+ // Registering shift buffer
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ rx_shift_buf <= {7{1'b0}};
+ else if (rx_state_inc)
+ rx_shift_buf <= nxt_rx_shift_buf;
+ end
+
+
+
+// --------------------------------------------
+// Interrupts
+ // Set by event
+ assign intr_stat_set[1] = reg_ctrl[3] & rxbuf_sample; // A new receive data is sampled
+ assign intr_stat_set[0] = reg_ctrl[2] & reg_ctrl[0] & tx_buf_full & tx_buf_clear;
+ // Falling edge of buffer full
+ // Clear by write to IntClear register
+ assign intr_stat_clear[1:0] = {2{write_enable0c}} & PWDATA[1:0];
+
+ // Registering outputs
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_txintr <= 1'b0;
+ else if (intr_stat_set[0] | intr_stat_clear[0])
+ reg_txintr <= intr_stat_set[0];
+ end
+
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ reg_rxintr <= 1'b0;
+ else if (intr_stat_set[1] | intr_stat_clear[1])
+ reg_rxintr <= intr_stat_set[1];
+ end
+
+ assign rx_overflow_intr = reg_rx_overrun & reg_ctrl[5];
+ assign tx_overflow_intr = reg_tx_overrun & reg_ctrl[4];
+
+ // Interrupt status for read back
+ assign intr_state = {rx_overflow_intr, tx_overflow_intr, reg_rxintr, reg_txintr};
+
+ // Connect to external
+ assign TXINT = reg_txintr;
+ assign RXINT = reg_rxintr;
+ assign TXOVRINT = tx_overflow_intr;
+ assign RXOVRINT = rx_overflow_intr;
+ assign UARTINT = reg_txintr | reg_rxintr | tx_overflow_intr | rx_overflow_intr;
+
+
+`ifdef ARM_APB_ASSERT_ON
+ // ------------------------------------------------------------
+ // Assertions
+ // ------------------------------------------------------------
+`include "std_ovl_defines.h"
+
+ // Prepare signals for OVL checking
+ reg [15:0] ovl_last_reg_baud_cntr_i;
+ reg [3:0] ovl_last_reg_baud_cntr_f;
+ reg ovl_last_baud_div_en;
+ reg ovl_last_baud_updated;
+ always @(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ begin
+ ovl_last_reg_baud_cntr_i <= {16{1'b0}};
+ ovl_last_reg_baud_cntr_f <= {4{1'b0}};
+ ovl_last_baud_div_en <= 1'b0;
+ ovl_last_baud_updated <= 1'b0;
+ end
+ else
+ begin
+ ovl_last_reg_baud_cntr_i <= reg_baud_cntr_i;
+ ovl_last_reg_baud_cntr_f <= reg_baud_cntr_f;
+ ovl_last_baud_div_en <= baud_div_en;
+ ovl_last_baud_updated <= baud_updated;
+ end
+ end
+
+ reg ovl_reg_hs_test_mode_triggered; // Indicate if HighSpeed testmode has been activated
+ wire ovl_nxt_hs_test_mode_triggered;
+ reg [7:0] ovl_reg_tx_tick_count; // For measuring width of TX state
+ wire [7:0] ovl_nxt_tx_tick_count;
+ reg [7:0] ovl_reg_rx_tick_count; // For measuring width of RX state
+ wire [7:0] ovl_nxt_rx_tick_count;
+ reg [3:0] ovl_reg_last_tx_state; // last state
+ reg [3:0] ovl_reg_last_rx_state;
+ reg [6:0] ovl_last_reg_ctrl;
+
+ // Clear test mode indicator each time state is changed, set to 1 if high speed test mode is
+ // enabled
+ assign ovl_nxt_hs_test_mode_triggered =
+ (tx_state!=ovl_reg_last_tx_state) ? reg_ctrl[6]: (reg_ctrl[6] | ovl_reg_hs_test_mode_triggered);
+
+ // Counter clear at each state change, increasement at each reg_baud_tick
+ assign ovl_nxt_tx_tick_count = (tx_state!=ovl_reg_last_tx_state) ? (8'h00) :
+ (ovl_reg_tx_tick_count + {{7{1'b0}}, reg_baud_tick});
+
+ // Counter clear at each state change, increasement at each reg_baud_tick
+ assign ovl_nxt_rx_tick_count = (rx_state!=ovl_reg_last_rx_state) ? (8'h00) :
+ (ovl_reg_rx_tick_count + {{7{1'b0}}, reg_baud_tick});
+
+ always@(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ begin
+ ovl_reg_hs_test_mode_triggered <= 1'b0;
+ ovl_reg_last_tx_state <= 4'h0;
+ ovl_reg_last_rx_state <= 4'h0;
+ ovl_reg_tx_tick_count <= 8'h00;
+ ovl_reg_rx_tick_count <= 8'h00;
+ ovl_last_reg_ctrl <= 7'h00;
+ end
+ else
+ begin
+ ovl_reg_hs_test_mode_triggered <= ovl_nxt_hs_test_mode_triggered;
+ ovl_reg_last_tx_state <= tx_state;
+ ovl_reg_last_rx_state <= rx_state;
+ ovl_reg_tx_tick_count <= ovl_nxt_tx_tick_count;
+ ovl_reg_rx_tick_count <= ovl_nxt_rx_tick_count;
+ ovl_last_reg_ctrl <= reg_ctrl;
+ end
+ end
+
+ // Signals for checking clearing of interrupts
+ reg ovl_last_txint;
+ reg ovl_last_rxint;
+ reg ovl_last_psel;
+ reg ovl_last_penable;
+ reg ovl_last_pwrite;
+ reg [31:0] ovl_last_pwdata;
+ reg [11:2] ovl_last_paddr;
+ reg ovl_last_rx_buf_full;
+ reg ovl_last_tx_shift_buf_0;
+
+
+ always@(posedge PCLK or negedge PRESETn)
+ begin
+ if (~PRESETn)
+ begin
+ ovl_last_txint <= 1'b0;
+ ovl_last_rxint <= 1'b0;
+ ovl_last_psel <= 1'b0;
+ ovl_last_penable <= 1'b0;
+ ovl_last_pwrite <= 1'b0;
+ ovl_last_paddr <= {10{1'b0}};
+ ovl_last_pwdata <= {32{1'b0}};
+ ovl_last_rx_buf_full <= 1'b0;
+ ovl_last_tx_shift_buf_0 <= 1'b0;
+ end
+ else
+ begin
+ ovl_last_txint <= TXINT;
+ ovl_last_rxint <= RXINT;
+ ovl_last_psel <= PSEL;
+ ovl_last_penable <= PENABLE;
+ ovl_last_pwrite <= PWRITE;
+ ovl_last_paddr <= PADDR;
+ ovl_last_pwdata <= PWDATA;
+ ovl_last_rx_buf_full <= rx_buf_full;
+ ovl_last_tx_shift_buf_0 <= tx_shift_buf[0];
+ end
+ end
+
+ // Ensure rx_state must not be 11, 12, 13, 14, 15
+ assert_never
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "rx_state in illegal state")
+ u_ovl_rx_state_illegal
+ (.clk(PCLK), .reset_n(PRESETn),
+ .test_expr((rx_state==4'hB)|(rx_state==4'hC)|(rx_state==4'hD)|
+ (rx_state==4'hE)|(rx_state==4'hF)));
+
+ // Ensure tx_state must not be 12, 13, 14, 15
+ assert_never
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "tx_state in illegal state")
+ u_ovl_tx_state_illegal
+ (.clk(PCLK), .reset_n(PRESETn),
+ .test_expr((tx_state==4'hC)|(tx_state==4'hD)|
+ (tx_state==4'hE)|(tx_state==4'hF)));
+
+ // Ensure reg_baud_cntr_i change only if UART is enabled
+ // or if write to baud rate divider
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "Unexpected baud rate divider change")
+ u_ovl_reg_baud_cntr_i_change
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(ovl_last_reg_baud_cntr_i!=reg_baud_cntr_i),
+ .consequent_expr(ovl_last_baud_div_en | ovl_last_baud_updated )
+ );
+
+ // Ensure reg_baud_div[19:4] >= reg_baud_cntr_i unless reg_baud_div just been programmed
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "Unexpected baud rate divided change")
+ u_ovl_reg_baud_cntr_i_range
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(reg_baud_cntr_i>reg_baud_div[19:4]),
+ .consequent_expr(baud_updated)
+ );
+
+ // Ensure reg_baud_cntr_f change only if UART is enabled
+ // or if write to baud rate divider
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "Unexpected baud rate divider change")
+ u_ovl_reg_baud_cntr_f_change
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(ovl_last_reg_baud_cntr_f!=reg_baud_cntr_f),
+ .consequent_expr(ovl_last_baud_div_en | ovl_last_baud_updated )
+ );
+
+ // Ensure tx_buf_full is set to 1 after write to TX buffer (PADDR[11:2]==0)
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "tx_buf_full should be asserted after write to TX buffer")
+ u_ovl_tx_buf_full
+ (.clk(PCLK), .reset_n(PRESETn),
+ .start_event (PSEL & (~PENABLE) & PWRITE & (PADDR[11:2] == 10'h000)),
+ .test_expr (tx_buf_full)
+ );
+
+ // If last tx_state=0 (idle) or 1 (wait for tick), TXD = 1.
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "TXD should be 1 when idle or just before data transmission")
+ u_ovl_txd_state_0_1
+ (.clk(PCLK), .reset_n(PRESETn),
+ .start_event ((tx_state==4'd0)|(tx_state==4'd1)),
+ .test_expr (TXD==1'b1)
+ );
+
+ // If last tx_state=2 (start bit), TXD = 0.
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "TXD should be 0 when output start bit")
+ u_ovl_txd_state_2
+ (.clk(PCLK), .reset_n(PRESETn),
+ .start_event (tx_state==4'd2),
+ .test_expr (TXD==1'b0)
+ );
+
+ // If last tx_state=3-10 (D0 to D7), TXD = anything (tx_shift_buf[0]).
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "TXD should be same as first bit of shift register during transfer")
+ u_ovl_txd_state_3_to_10
+ (.clk(PCLK), .reset_n(PRESETn),
+ .start_event ((tx_state>4'd2) & (tx_state<4'd11)),
+ .test_expr (TXD==ovl_last_tx_shift_buf_0)
+ );
+
+ // If last tx_state=11 (stop bit), TXD = 1.
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "TXD should be 1 when output stop bit")
+ u_ovl_txd_state_11
+ (.clk(PCLK), .reset_n(PRESETn),
+ .start_event (tx_state==4'd11),
+ .test_expr (TXD==1'b1)
+ );
+
+ // Duration of tx_state in 2 to 11 must have 16 reg_baud_tick
+ // (unless high speed test mode has been active)
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "Duration of tx_state when in state 2 to state 11 should have 16 ticks")
+ u_ovl_width_of_tx_state
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr((tx_state!=ovl_reg_last_tx_state) & // at state change
+ (ovl_reg_last_tx_state>4'd1)&(ovl_reg_last_tx_state<4'd12) & // from state 2 to 11
+ (ovl_reg_hs_test_mode_triggered==1'b0)), // high speed test mode not triggered
+ .consequent_expr((ovl_reg_tx_tick_count==8'd15) | (ovl_reg_tx_tick_count==8'd16))
+ // count from 0 to 15 (16 ticks)
+ );
+
+
+ // In high speed test mode, tx_state must change if it is in range of 2 to 11
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "Duration of tx_state should be 1 cycle if high speed test mode is enabled")
+ u_ovl_width_of_tx_state_in_high_speed_test_mode
+ (.clk(PCLK), .reset_n(PRESETn),
+ .start_event((tx_state>4'd1)&(tx_state<4'd12) & reg_ctrl[6]),
+ .test_expr (tx_state != ovl_reg_last_tx_state)
+ );
+
+ // Duration of rx_state in 1 must have 8 reg_baud_tick
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "Duration of rx_state when state 1 should have 8 ticks")
+ u_ovl_width_of_rx_state_1
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr((rx_state!=ovl_reg_last_rx_state) & // at state change
+ (ovl_reg_last_rx_state==4'd1)), // last state was state 1
+ .consequent_expr((ovl_reg_rx_tick_count==8'd7)|(ovl_reg_rx_tick_count==8'd8))
+ // count from 0 to 7 (8 ticks)
+ );
+
+ // Duration of rx_state in 2 to 10 must have 16 reg_baud_tick
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "Duration of rx_state when in state 2 to state 10 should have 16 ticks")
+ u_ovl_width_of_rx_state_data
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr((rx_state!=ovl_reg_last_rx_state) & // at state change
+ (ovl_reg_last_rx_state>4'd1)&(ovl_reg_last_rx_state<4'd11)), // from state 2 to 9
+ .consequent_expr((ovl_reg_rx_tick_count==8'd15)|(ovl_reg_rx_tick_count==8'd16))
+ // count from 0 to 15 (16 ticks)
+ );
+
+ // UARTINT must be 0 if TXINT, RXINT, TXOVRINT and RXOVRINT are all 0
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "UARTINT must be 0 if TXINT, RXINT, TXOVRINT and RXOVRINT are all 0")
+ u_ovl_uartint_mismatch
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr((TXINT | RXINT | TXOVRINT | RXOVRINT) == 1'b0), // No interrupt
+ .consequent_expr(UARTINT==1'b0) // Combined interrupt = 0
+ );
+
+ // TXINT should be asserted when TX interrupt enabled and transmit buffer is available
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "TXINT should be triggered when enabled")
+ u_ovl_txint_enable
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (reg_ctrl[0] & reg_ctrl[2] & tx_buf_full & tx_buf_clear),
+ .test_expr (TXINT == 1'b1)
+ );
+
+ // There should be no rising edge of TXINT if transmit is disabled or transmit interrupt is disabled
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "TXINT should not be triggered when disabled")
+ u_ovl_txint_disable
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (((reg_ctrl[0]==1'b0) | (reg_ctrl[2]==1'b0)) & (TXINT == 1'b0)),
+ .test_expr (TXINT == 1'b0)
+ );
+
+ // if TXINT falling edge, there must has been a write to INTCLEAR register with bit[0]=1
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "When there is a falling edge of TXINT, there must has been a write to INTCLEAR")
+ u_ovl_txint_clear
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(ovl_last_txint & (~TXINT)), // Falling edge of TXINT
+ .consequent_expr(ovl_last_psel & ovl_last_pwrite &
+ (ovl_last_paddr==10'h003) & (ovl_last_pwdata[0]) ) // There must has been a write to INTCLEAR
+ );
+
+ // RXINT should be asserted when RX interrupt enabled and a new data is received
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "RXINT should be triggered when enabled")
+ u_ovl_rxint_enable
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (reg_ctrl[3] & (rx_state==9) & (nxt_rx_state==10)),
+ .test_expr (RXINT == 1'b1)
+ );
+
+ // There should be no rising edge of RXINT if receive interrupt is disabled
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "RXINT should not be triggered when disabled")
+ u_ovl_rxint_disable
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event ((reg_ctrl[3]==1'b0) & (RXINT == 1'b0)),
+ .test_expr (RXINT == 1'b0)
+ );
+
+ // if RXINT falling edge, there must has been a write to INTCLEAR register with bit[1]=1
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "When there is a falling edge of RXINT, there must has been a write to INTCLEAR")
+ u_ovl_rxint_clear
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(ovl_last_rxint & (~RXINT)), // Falling edge of TXINT
+ .consequent_expr(ovl_last_psel & ovl_last_pwrite &
+ (ovl_last_paddr==10'h003) & (ovl_last_pwdata[1]) ) // There must has been a write to INTCLEAR
+ );
+
+ // rx_buf_full should rise if rx_state change from 9 to 10
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "rx_buf_full should be asserted when a new character is received")
+ u_ovl_rx_buf_full
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event ((rx_state==9) & (nxt_rx_state==10)),
+ .test_expr (rx_buf_full == 1'b1)
+ );
+
+ // if rx_buf_full falling edge, there must has been a read to the receive buffer
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "When there is a falling edge of RXINT, there must has been a read to receive buffer")
+ u_ovl_rx_buf_full_clear
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr((~rx_buf_full) & ovl_last_rx_buf_full), // Falling edge of rx_buf_full
+ .consequent_expr(ovl_last_psel & (~ovl_last_pwrite) &
+ (ovl_last_paddr==10'h000) ) // There must has been a read to rx data
+ );
+
+ // TXOVRINT must be 0 if reg_ctrl[4]=0
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "When there is a falling edge of RXINT, there must has been a write to INTCLEAR")
+ u_ovl_txovrint_disable
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(~reg_ctrl[4]),
+ .consequent_expr(~TXOVRINT)
+ );
+
+ // RXOVRINT must be 0 if reg_ctrl[5]=0
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "When there is a falling edge of RXINT, there must has been a write to INTCLEAR")
+ u_ovl_rxovrint_disable
+ (.clk(PCLK), .reset_n(PRESETn),
+ .antecedent_expr(~reg_ctrl[5]),
+ .consequent_expr(~RXOVRINT)
+ );
+
+ // if a write take place to TX data buffer and tx_buf_full was 1, reg_tx_overrun will be set
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "tx buffer overrun should be asserted when a new character is write to buffer and buffer is already full")
+ u_ovl_tx_buffer_overrun
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (write_enable00 & tx_buf_full & (~tx_buf_clear)),
+ .test_expr (reg_tx_overrun == 1'b1)
+ );
+
+ // if rx_buf_full is high and rx_state change from 9 to 10, reg_rx_overrun will be set
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "rx buffer overrun should be asserted when a new character is received and rx buffer is already full")
+ u_ovl_rx_buffer_overrun
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (rx_buf_full & (~rx_data_read) & (rx_state==9) & (nxt_rx_state==10)),
+ .test_expr (reg_rx_overrun == 1'b1)
+ );
+
+ // if write to INTCLEAR with bit[2]=1, reg_tx_overrun will be cleared,
+ // Cannot have new overrun at the same time because the APB can only do onething at a time
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "tx buffer overrun should be clear when write to INTCLEAR")
+ u_ovl_tx_buffer_overrun_clear_a
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (write_enable0c & (PWDATA[2])),
+ .test_expr (reg_tx_overrun==1'b0)
+ );
+
+ // if write to STATUS with bit[2]=1, reg_tx_overrun will be cleared,
+ // Cannot have new overrun at the same time because the APB can only do onething at a time
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "tx buffer overrun should be clear when write to INTCLEAR")
+ u_ovl_tx_buffer_overrun_clear_b
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (write_enable04 & (PWDATA[2])),
+ .test_expr (reg_tx_overrun==1'b0)
+ );
+
+ // if write to INTCLEAR with bit[3]=1, reg_rx_overrun will be cleared, unless a new overrun take place
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "rx buffer overrun should be clear when write to INTCLEAR, unless new overrun")
+ u_ovl_rx_buffer_overrun_clear_a
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (write_enable0c & (PWDATA[3]) & (~(rx_buf_full & (rx_state==9) & (nxt_rx_state==10)))),
+ .test_expr (reg_rx_overrun==1'b0)
+ );
+
+ // If rx buffer is not full, it cannot have new overrun
+ assert_next
+ #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
+ "rx buffer overrun should be clear when write to INTCLEAR, unless new overrun")
+ u_ovl_rx_buffer_overrun_when_empty
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event ((~rx_buf_full) & (reg_rx_overrun==1'b0)),
+ .test_expr (reg_rx_overrun==1'b0)
+ );
+
+
+ // Reading of reg_baud_div (worth checking due to two stage read mux)
+ assert_next
+ #(`OVL_ERROR, 1, 1, 0, `OVL_ASSERT,
+ "Reading of baud rate divider value")
+ u_ovl_read_baud_rate_divide_cfg
+ (.clk(PCLK ), .reset_n (PRESETn),
+ .start_event (PSEL & (~PENABLE) & (~PWRITE) & (PADDR[11:2]==10'h004)),
+ .test_expr (PRDATA=={{12{1'b0}}, reg_baud_div})
+ );
+
+ // Recommended Baud Rate divider value is at least 16
+ assert_never
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "UART enabled with baud rate less than 16")
+ u_ovl_baud_rate_divider_illegal
+ (.clk(PCLK), .reset_n(PRESETn),
+ .test_expr(((reg_ctrl[0]) & (reg_ctrl[6]==1'b0) & (reg_baud_div[19:4]=={16{1'b0}}) ) |
+ ((reg_ctrl[1]) & (reg_baud_div[19:4]=={16{1'b0}}) ) )
+ );
+
+ // Test mode never changes from hi-speed to normal speed unless TX is idle
+ assert_never
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "High speed test mode has been changed when TX was not idle")
+ u_ovl_change_speed_tx_illegal
+ (.clk(PCLK), .reset_n(PRESETn),
+ .test_expr((tx_state != 4'd00) & (reg_ctrl[6] != ovl_last_reg_ctrl[6]))
+ );
+
+`endif
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_clkreset.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_clkreset.v
new file mode 100644
index 0000000000000000000000000000000000000000..d30c3c8441cc413437ae5779d0827097bb97a8f0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_clkreset.v
@@ -0,0 +1,62 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple clock and power on reset generator
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ps
+
+module cmsdk_clkreset(
+ output wire CLK,
+ output wire NRST);
+
+ reg clock_q = 1'b0;
+ reg reset_n_q = 1'b0;
+
+ initial
+ begin
+ #40 clock_q <= 1'b1;
+ #100 reset_n_q <= 1'b1;
+ end
+
+ always @(clock_q)
+ // #25 clock_q <= ~clock_q; // 50ns period 20MHz - 9600 baud
+ #5 clock_q <= ~clock_q; // 10ns period, 100MHz - 48000 baud
+
+ assign CLK = clock_q;
+ assign NRST = reset_n_q;
+
+endmodule
+
+
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ft1248x1_adpio.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ft1248x1_adpio.v
new file mode 100644
index 0000000000000000000000000000000000000000..89ecfe668de15e22decfa5cc6e242e9427f6dde6
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ft1248x1_adpio.v
@@ -0,0 +1,157 @@
+//-----------------------------------------------------------------------------
+// customised example Cortex-M0 controller UART with file logging
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+// and allows cmsdk_uart_capture testbench models to log ADP ip, op streams
+//-----------------------------------------------------------------------------
+
+
+module cmsdk_ft1248x1_adpio
+ #(parameter ADPFILENAME = "adp.cmd",
+ parameter VERBOSE = 0)
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+ inout wire ft_miosio_io, // MIOSIO tristate output when enabled
+
+ output wire FTDI_CLK2UART_o, // Clock (baud rate)
+ output wire FTDI_OP2UART_o, // Received data to UART capture
+ output wire FTDI_IP2UART_o // Transmitted data to UART capture
+ );
+
+
+ //----------------------------------------------
+ //-- File I/O
+ //----------------------------------------------
+
+
+ integer fdcmd; // channel descriptor for cmd file input
+ integer ch;
+`define EOF -1
+
+ reg ft_rxreq;
+ wire ft_rxack;
+ reg [7:0] ft_adpbyte;
+
+ initial
+ begin
+ ft_rxreq <= 0;
+ $timeformat(-9, 0, " ns", 14);
+ fdcmd= $fopen(ADPFILENAME,"r");
+ if (fdcmd == 0)
+ $write("** FT1248x1 : no command file **\n");
+ else begin
+ ch = $fgetc(fdcmd);
+ while (ch != `EOF) begin
+ ft_adpbyte <= (ch & 8'hff);
+ ft_rxreq <= 1'b1;
+ while (ft_ssn_i == 1'b0)
+ @(posedge ft_ssn_i);
+ @(posedge ft_rxack);
+ ft_rxreq <=0;
+ @(negedge ft_rxack);
+ ch = $fgetc(fdcmd);
+ end
+ end
+ $fclose(fdcmd);
+ ft_rxreq <= 0;
+ end
+
+
+//----------------------------------------------
+//-- State Machine
+//----------------------------------------------
+
+wire ft_miosio_i;
+wire ft_miosio_o;
+wire ft_miosio_z;
+
+// tri-state pad control for MIOSIO
+assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;
+// add notinal delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
+assign #1 ft_miosio_i = ft_miosio_io;
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [5:0] ft_nextstate = ft_state + 5'b00001;
+
+always @(posedge ft_clk_i or posedge ft_ssn_i)
+ if (ft_ssn_i)
+ ft_state <= 5'b11111;
+ else // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// ft_miso_o reflects RXE when deselected
+assign ft_miso_o = (ft_ssn_i) ? !ft_rxreq : (ft_state == 5'b00111);
+
+// capture CMD on falling edge of clock (mid-data)
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+reg [7:0] ft_cmd;
+always @(negedge ft_clk_i or posedge ft_ssn_i)
+ if (ft_ssn_i)
+ ft_cmd <= 8'b00000001;
+ else // shift in data
+ ft_cmd <= (!ft_state[3] & !ft_nextstate[3]) ? {ft_cmd[6:0],ft_miosio_i} : ft_cmd;
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// serial data formatted with start bit for UART capture (on rising uart-clock)
+assign FTDI_CLK2UART_o = !ft_clk_i;
+// suitable for CMSDK UART capture IO
+// inject a start bit low else mark high
+assign FTDI_OP2UART_o = (ft_cmd_txd & (ft_state[4:3]) == 2'b01) ? ft_miosio_i : !(ft_cmd_txd & (ft_state == 5'b00111));
+assign FTDI_IP2UART_o = (ft_cmd_rxd & (ft_state[4:3]) == 2'b01) ? ft_miosio_io : !(ft_cmd_rxd & (ft_state == 5'b00111));
+
+// capture RXD on falling edge of clock
+reg [8:0] ft_rxd;
+always @(negedge ft_clk_i or posedge ft_ssn_i)
+ if (ft_ssn_i)
+ ft_rxd <= 9'b111111111;
+ else if (ft_cmd_txd & !(ft_miosio_i & (&ft_rxd[8:0]))) //only on valid start-bit
+ ft_rxd <= {ft_miosio_i, ft_rxd[8:1]};
+
+// shift TXD on rising edge of clock
+reg [8:0] ft_txd;
+always @(posedge ft_clk_i or posedge ft_ssn_i)
+ if (ft_ssn_i)
+ ft_txd <= {1'b1,ft_adpbyte};
+ else if (ft_rxreq & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //valid TX shift
+ ft_txd <= {1'b0,ft_txd[8:1]};
+
+assign ft_rxack = (ft_cmd_rxd & (ft_state==5'b01111));
+
+// ft_miso_o reflects TXF when deselected (never full for simulation output)
+assign ft_miosio_o = (ft_ssn_i) ? 1'b0 : ft_txd[0];
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_clkctrl.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_clkctrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..a994d017f4cb9d304bd31559392446b796ef8379
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_clkctrl.v
@@ -0,0 +1,191 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple clock controller for Cortex-M0 example system
+//-----------------------------------------------------------------------------
+// Note : Most of the clock gating are handled by the example PMU provided
+// in the Cortex-M0/Cortex-M0+ deliverable.
+
+module cmsdk_mcu_clkctrl #(
+ parameter CLKGATE_PRESENT = 0)
+ (
+ input wire XTAL1, // Clock source
+ input wire NRST, // active low external reset
+
+ input wire APBACTIVE, // APB active status
+ input wire SLEEPING, // Sleep status
+ input wire SLEEPDEEP, // Deep Sleep status
+ input wire SYSRESETREQ, // System reset request
+ input wire DBGRESETREQ, // Debug reset request
+ input wire LOCKUP, // LOCKUP status
+ input wire LOCKUPRESET, // Config - generation reset if locked up
+
+ input wire CGBYPASS, // Clock gating bypass
+ input wire RSTBYPASS, // Reset by pass
+
+ output wire XTAL2, // Feedback for Crystal oscillator
+ output wire FCLK, // Free running clock
+ output wire PCLK, // Peripheral clock
+ output wire PCLKG, // Gated PCLK for APB transfers
+ output wire PCLKEN, // Clock divide control for AHB to APB bridge
+`ifdef CORTEX_M0DESIGNSTART
+ output wire PORESETn, // Power on reset
+ output wire HRESETn, // System and AHB reset
+`endif
+ output wire PRESETn); // Peripheral reset
+
+ wire clk;
+ wire reset_n;
+ reg [2:0] reset_sync_reg;
+ wire [2:0] nxt_reset_sync;
+`ifdef CORTEX_M0DESIGNSTART
+ reg hrst_reg;
+ wire nxt_hrst;
+ reg dbgrst_reg;
+`endif
+ reg prst_reg;
+ wire nxt_prst;
+ wire i_pclken;
+ wire i_pclkgen;
+
+ // Crystal oscillator inverter
+ assign XTAL2 = (~(XTAL1 | SLEEPDEEP));
+
+ // Clock source
+ assign clk = XTAL1;
+
+ // Reset synchronizer
+ assign nxt_reset_sync = {reset_sync_reg[1:0], 1'b1};
+
+ always @(posedge clk or negedge NRST)
+ begin
+ if (~NRST)
+ reset_sync_reg <= 3'b000;
+ else
+ reset_sync_reg <= nxt_reset_sync;
+ end
+
+ assign reset_n = reset_sync_reg[2];
+
+`ifdef CORTEX_M0DESIGNSTART
+ // AHB HRESETn
+ assign nxt_hrst = ~(SYSRESETREQ | (LOCKUP & LOCKUPRESET));
+
+ always @(posedge clk or negedge reset_n)
+ begin
+ if (~reset_n)
+ hrst_reg <= 1'b0;
+ else
+ hrst_reg <= nxt_hrst;
+ end
+
+ // Debug Reset
+ always @(posedge clk or negedge reset_n)
+ begin
+ if (~reset_n)
+ dbgrst_reg <= 1'b0;
+ else
+ dbgrst_reg <= ~DBGRESETREQ;
+ end
+`endif
+
+ // APB PRESETn
+ assign nxt_prst = ~(SYSRESETREQ | (LOCKUP & LOCKUPRESET));
+
+ always @(posedge clk or negedge reset_n)
+ begin
+ if (~reset_n)
+ prst_reg <= 1'b0;
+ else
+ prst_reg <= nxt_prst;
+ end
+
+ generate if (CLKGATE_PRESENT == 0) begin : gen_no_clock_gating
+
+ // No clock gating for PCLK
+ assign i_pclken = 1'b1; // Currently PCLK = HCLK (for AHB to APB bridge)
+ assign i_pclkgen = 1'b1; // Not used
+ assign PCLK = clk; // Peripheral clock
+ assign PCLKG = clk; // Peripheral clock for APB interface
+
+ end else
+ begin : gen_clock_gating
+ // Clock gate is present.
+ // Testing of divided PCLK is only possible when clock gating is available
+`ifdef ARM_CMSDK_SLOWSPEED_PCLK
+ reg reg_pclk_divide;
+
+ always @(posedge clk or negedge reset_n)
+ if (~reset_n)
+ reg_pclk_divide <= 1'b1;
+ else
+ reg_pclk_divide <= ~reg_pclk_divide;
+
+ assign i_pclken = reg_pclk_divide; // PCLKEN toggle every cycle (PCLK at half speed)
+
+`else
+ assign i_pclken = 1'b1; // PCLK = HCLK
+`endif
+ assign i_pclkgen = i_pclken & APBACTIVE;
+
+ // PCLK generation
+ cmsdk_clock_gate
+ #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
+ u_cmsdk_clock_gate_pclk(
+ .CLK (clk),
+ .CLKENABLE (i_pclken),
+ .DISABLEG (CGBYPASS),
+ .GATEDCLK (PCLK));
+
+ // Gated PCLK (PCLKG) generation
+ cmsdk_clock_gate
+ #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
+ u_cmsdk_clock_gate_pclkg(
+ .CLK (clk),
+ .CLKENABLE (i_pclkgen),
+ .DISABLEG (CGBYPASS),
+ .GATEDCLK (PCLKG));
+
+ end endgenerate
+
+ // Connect to top level
+`ifdef CORTEX_M0DESIGNSTART
+ assign PORESETn = (RSTBYPASS) ? NRST : reset_n;
+ assign HRESETn = (RSTBYPASS) ? NRST : hrst_reg;
+`endif
+ assign PRESETn = (RSTBYPASS) ? NRST : prst_reg;
+ assign FCLK = clk; // Free running clock
+ assign PCLKEN = i_pclken;
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_pin_mux.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_pin_mux.v
new file mode 100644
index 0000000000000000000000000000000000000000..82d0ae5d32d2233ac83213d5d1c1b94ebd6dd671
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_pin_mux.v
@@ -0,0 +1,233 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Pin multiplexing control for example Cortex-M0/Cortex-M0+
+// microcontroller
+//-----------------------------------------------------------------------------
+//
+module cmsdk_mcu_pin_mux (
+ //-------------------------------------------
+ // I/O ports
+ //-------------------------------------------
+
+ // UART
+ output wire uart0_rxd,
+ input wire uart0_txd,
+ input wire uart0_txen,
+ output wire uart1_rxd,
+ input wire uart1_txd,
+ input wire uart1_txen,
+ output wire uart2_rxd,
+ input wire uart2_txd,
+ input wire uart2_txen,
+
+ // Timer
+ output wire timer0_extin,
+ output wire timer1_extin,
+
+`ifdef CORTEX_M0PLUS
+`ifdef ARM_CMSDK_INCLUDE_MTB
+ // CoreSight MTB M0+
+ output wire TSTART,
+ output wire TSTOP,
+`endif
+`endif
+
+ // IO Ports
+ output wire [15:0] p0_in,
+ input wire [15:0] p0_out,
+ input wire [15:0] p0_outen,
+ input wire [15:0] p0_altfunc,
+
+ output wire [15:0] p1_in,
+ input wire [15:0] p1_out,
+ input wire [15:0] p1_outen,
+ input wire [15:0] p1_altfunc,
+
+ // Processor debug interface
+ output wire i_trst_n,
+ output wire i_swditms,
+ output wire i_swclktck,
+ output wire i_tdi,
+ input wire i_tdo,
+ input wire i_tdoen_n,
+ input wire i_swdo,
+ input wire i_swdoen,
+
+ // IO pads
+ inout wire [15:0] P0, // legacy
+ inout wire [15:0] P1, // legacy
+
+ output wire [15:0] p1_out_mux, //alt-function mux
+ output wire [15:0] p1_out_en_mux, //alt-function mux
+
+ input wire nTRST, // Not needed if serial-wire debug is used
+ input wire TDI, // Not needed if serial-wire debug is used
+ inout wire SWDIOTMS,
+ input wire SWCLKTCK,
+ output wire TDO); // Not needed if serial-wire debug is used
+
+ //-------------------------------------------
+ // Internal wires
+ //-------------------------------------------
+ wire [15:0] p0_out_mux;
+ wire [15:0] p0_out_en_mux;
+// wire [15:0] p1_out_mux; // promoted to block output
+// wire [15:0] p1_out_en_mux; // promoted to block output
+
+ //-------------------------------------------
+ // Beginning of main code
+ //-------------------------------------------
+ // inputs
+ assign uart0_rxd = p1_in[0];
+ assign uart1_rxd = p1_in[2];
+ assign uart2_rxd = p1_in[4];
+ assign timer0_extin = p1_in[8];
+ assign timer1_extin = p1_in[9];
+
+ assign p0_in = P0;
+ assign p1_in = P1;
+
+ // Output function mux
+ assign p0_out_mux = p0_out; // No function muxing for Port 0
+
+ assign p1_out_mux[0] = p1_out[0];
+ assign p1_out_mux[1] = (p1_altfunc[1]) ? uart0_txd : p1_out[1];
+ assign p1_out_mux[2] = p1_out[2];
+ assign p1_out_mux[3] = (p1_altfunc[3]) ? uart1_txd : p1_out[3];
+ assign p1_out_mux[4] = p1_out[4];
+ assign p1_out_mux[5] = (p1_altfunc[5]) ? uart2_txd : p1_out[5];
+ assign p1_out_mux[15:6] = p1_out[15:6];
+
+`ifdef CORTEX_M0PLUS
+`ifdef ARM_CMSDK_INCLUDE_MTB
+ // MTB control
+ // The TSTART/TSTOP synchronising logic is instantiated within the
+ // cmsdk_mcu_system module.
+ assign TSTART = p1_in[7];
+ assign TSTOP = p1_in[6];
+ // This allows TSTART and TSTOP to be controlled from external sources.
+`endif
+`endif
+
+ // Output enable mux
+ assign p0_out_en_mux = p0_outen; // No function muxing for Port 0
+
+ assign p1_out_en_mux[0] = p1_outen[0];
+ assign p1_out_en_mux[1] = (p1_altfunc[1]) ? uart0_txen : p1_outen[1];
+ assign p1_out_en_mux[2] = p1_outen[2];
+ assign p1_out_en_mux[3] = (p1_altfunc[3]) ? uart1_txen : p1_outen[3];
+ assign p1_out_en_mux[4] = p1_outen[4];
+ assign p1_out_en_mux[5] = (p1_altfunc[5]) ? uart2_txen : p1_outen[5];
+ assign p1_out_en_mux[15:6] = p1_outen[15:6];
+
+
+ // Output tristate
+ assign P0[ 0] = p0_out_en_mux[ 0] ? p0_out_mux[ 0] : 1'bz;
+ assign P0[ 1] = p0_out_en_mux[ 1] ? p0_out_mux[ 1] : 1'bz;
+ assign P0[ 2] = p0_out_en_mux[ 2] ? p0_out_mux[ 2] : 1'bz;
+ assign P0[ 3] = p0_out_en_mux[ 3] ? p0_out_mux[ 3] : 1'bz;
+ assign P0[ 4] = p0_out_en_mux[ 4] ? p0_out_mux[ 4] : 1'bz;
+ assign P0[ 5] = p0_out_en_mux[ 5] ? p0_out_mux[ 5] : 1'bz;
+ assign P0[ 6] = p0_out_en_mux[ 6] ? p0_out_mux[ 6] : 1'bz;
+ assign P0[ 7] = p0_out_en_mux[ 7] ? p0_out_mux[ 7] : 1'bz;
+ assign P0[ 8] = p0_out_en_mux[ 8] ? p0_out_mux[ 8] : 1'bz;
+ assign P0[ 9] = p0_out_en_mux[ 9] ? p0_out_mux[ 9] : 1'bz;
+ assign P0[10] = p0_out_en_mux[10] ? p0_out_mux[10] : 1'bz;
+ assign P0[11] = p0_out_en_mux[11] ? p0_out_mux[11] : 1'bz;
+ assign P0[12] = p0_out_en_mux[12] ? p0_out_mux[12] : 1'bz;
+ assign P0[13] = p0_out_en_mux[13] ? p0_out_mux[13] : 1'bz;
+ assign P0[14] = p0_out_en_mux[14] ? p0_out_mux[14] : 1'bz;
+ assign P0[15] = p0_out_en_mux[15] ? p0_out_mux[15] : 1'bz;
+
+ assign P1[ 0] = p1_out_en_mux[ 0] ? p1_out_mux[ 0] : 1'bz;
+ assign P1[ 1] = p1_out_en_mux[ 1] ? p1_out_mux[ 1] : 1'bz;
+ assign P1[ 2] = p1_out_en_mux[ 2] ? p1_out_mux[ 2] : 1'bz;
+ assign P1[ 3] = p1_out_en_mux[ 3] ? p1_out_mux[ 3] : 1'bz;
+ assign P1[ 4] = p1_out_en_mux[ 4] ? p1_out_mux[ 4] : 1'bz;
+ assign P1[ 5] = p1_out_en_mux[ 5] ? p1_out_mux[ 5] : 1'bz;
+ assign P1[ 6] = p1_out_en_mux[ 6] ? p1_out_mux[ 6] : 1'bz;
+ assign P1[ 7] = p1_out_en_mux[ 7] ? p1_out_mux[ 7] : 1'bz;
+ assign P1[ 8] = p1_out_en_mux[ 8] ? p1_out_mux[ 8] : 1'bz;
+ assign P1[ 9] = p1_out_en_mux[ 9] ? p1_out_mux[ 9] : 1'bz;
+ assign P1[10] = p1_out_en_mux[10] ? p1_out_mux[10] : 1'bz;
+ assign P1[11] = p1_out_en_mux[11] ? p1_out_mux[11] : 1'bz;
+ assign P1[12] = p1_out_en_mux[12] ? p1_out_mux[12] : 1'bz;
+ assign P1[13] = p1_out_en_mux[13] ? p1_out_mux[13] : 1'bz;
+ assign P1[14] = p1_out_en_mux[14] ? p1_out_mux[14] : 1'bz;
+ assign P1[15] = p1_out_en_mux[15] ? p1_out_mux[15] : 1'bz;
+
+/*
+// synopsys translate_off
+
+ // Pullup
+ pullup(P0[ 0]);
+ pullup(P0[ 1]);
+ pullup(P0[ 2]);
+ pullup(P0[ 3]);
+ pullup(P0[ 4]);
+ pullup(P0[ 5]);
+ pullup(P0[ 6]);
+ pullup(P0[ 7]);
+ pullup(P0[ 8]);
+ pullup(P0[ 9]);
+ pullup(P0[10]);
+ pullup(P0[11]);
+ pullup(P0[12]);
+ pullup(P0[13]);
+ pullup(P0[14]);
+ pullup(P0[15]);
+
+ pullup(P1[ 0]);
+ pullup(P1[ 1]);
+ pullup(P1[ 2]);
+ pullup(P1[ 3]);
+ pullup(P1[ 4]);
+ pullup(P1[ 5]);
+ pullup(P1[ 6]);
+ pullup(P1[ 7]);
+ pullup(P1[ 8]);
+ pullup(P1[ 9]);
+ pullup(P1[10]);
+ pullup(P1[11]);
+ pullup(P1[12]);
+ pullup(P1[13]);
+ pullup(P1[14]);
+ pullup(P1[15]);
+
+// synopsys translate_on
+*/
+ //-------------------------------------------
+ // Debug connections
+ //-------------------------------------------
+
+ assign i_trst_n = nTRST;
+ assign i_tdi = TDI;
+ assign i_swclktck = SWCLKTCK;
+ assign i_swditms = SWDIOTMS;
+
+ // Tristate buffers for debug output signals
+ bufif1 (SWDIOTMS, i_swdo, i_swdoen);
+ bufif0 (TDO, i_tdo, i_tdoen_n);
+
+ endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..30221aa2af4c4e618d43a84b21db796883ad6ae8
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
@@ -0,0 +1,80 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple control for SysTick signals for Cortex-M processor
+//-----------------------------------------------------------------------------
+
+module cmsdk_mcu_stclkctrl #(
+ // Ratio between FCLK and SysTck reference clock
+ parameter DIV_RATIO = 18'd01000,
+
+ // Divide by half for each phase
+ parameter DIVIDER_RELOAD = (DIV_RATIO>>1)-1
+ )
+ (
+ input wire FCLK, // Free running clock
+ input wire SYSRESETn, // System reset
+
+ output wire STCLKEN, // SysTick clock
+ output wire [25:0] STCALIB // SysTick calibration
+ );
+
+ reg [17:0] reg_clk_divider;
+ reg reg_stclken;
+
+ assign STCALIB[25] = 1'b0; // NoRef - reference clock provided
+ assign STCALIB[24] = 1'b1; // Skew - reference info not available
+ assign STCALIB[23:0] = {24{1'b0}}; // 10 ms value set to 0, indicate this value is not used
+
+ // Divider
+ wire [17:0] reg_clk_div_min1 = reg_clk_divider -1;
+ always @(posedge FCLK or negedge SYSRESETn)
+ begin
+ if (~SYSRESETn)
+ reg_clk_divider <= {18{1'b0}};
+ else
+ begin
+ if (|reg_clk_divider)
+ reg_clk_divider <= reg_clk_div_min1[17:0];
+ else
+ reg_clk_divider <= DIVIDER_RELOAD[17:0];
+ end
+ end
+
+ // Toggle register
+ always @(posedge FCLK or negedge SYSRESETn)
+ begin
+ if (~SYSRESETn)
+ reg_stclken <= 1'b0;
+ else
+ begin
+ if (reg_clk_divider==18'h00000)
+ reg_stclken <= ~reg_stclken;
+ end
+ end
+
+ // Connect to top level
+ assign STCLKEN = reg_stclken;
+
+endmodule
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_sysctrl.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_sysctrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..383b4af8544cb3249dba4825e6d44d61c7ff49fd
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_sysctrl.v
@@ -0,0 +1,351 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : System controller for simple Cortex-M Microcontroller system
+//-----------------------------------------------------------------------------
+//-------------------------------------
+// Programmer's model
+// -------------------------------
+// 0x000 RW MEM_CTRL
+// bit [ 0] REMAP - default value 1
+// 0x004 RW PMU_CTRL
+// bit [ 0] PMUENABLE - default value 0
+// 0x008 R/W SYS_CTRL
+// bit [ 0] LOCKUPRESETEN - default value 0
+// 0x00C -- Not used
+//
+// 0x010 R/Wc Reset Information
+// bit [ 2] LOCKUPRESET
+// bit [ 1] WDOGRESETREQ
+// bit [ 0] SYSRESETREQ
+//
+//-------------------------------------
+
+module cmsdk_mcu_sysctrl #(
+ parameter BE = 0 // By default use little endian
+
+ )
+ (
+ // AHB Inputs
+ input wire HCLK, // system bus clock
+ input wire HRESETn, // system bus reset
+ input wire FCLK, // Free running clock
+ input wire PORESETn, // power on reset
+ input wire HSEL, // AHB peripheral select
+ input wire HREADY, // AHB ready input
+ input wire [1:0] HTRANS, // AHB transfer type
+ input wire [2:0] HSIZE, // AHB hsize
+ input wire HWRITE, // AHB hwrite
+ input wire [11:0] HADDR, // AHB address bus
+ input wire [31:0] HWDATA, // AHB write data bus
+
+ // AHB Outputs
+ output wire HREADYOUT, // AHB ready output to S->M mux
+ output wire HRESP, // AHB response
+ output wire [31:0] HRDATA, // AHB read data bus
+
+ // Reset information
+ input wire SYSRESETREQ,// System reset request
+ input wire WDOGRESETREQ,// Watchdog reset request
+ input wire LOCKUP, // CPU locked up
+
+ //ECO revision number
+ input wire [3:0] ECOREVNUM, // ECO revision number
+
+ // System control signals
+ output wire REMAP, // memory remap
+ output wire PMUENABLE, // Power Management Unit enable, will be disabled in design
+ // start version
+ output wire LOCKUPRESET // Enable reset if lockup
+ );
+
+// --------------------------------------------------------------------------
+// Port Definitions
+// --------------------------------------------------------------------------
+
+//Local parameter for IDs,
+localparam ARM_CMSDK_CM0_SYSCTRL_PID4 = {32'h00000004}; // 0xFD0 : PID 4
+localparam ARM_CMSDK_CM0_SYSCTRL_PID5 = {32'h00000000}; // 0xFD4 : PID 5
+localparam ARM_CMSDK_CM0_SYSCTRL_PID6 = {32'h00000000}; // 0xFD8 : PID 6
+localparam ARM_CMSDK_CM0_SYSCTRL_PID7 = {32'h00000000}; // 0xFDC : PID 7
+localparam ARM_CMSDK_CM0_SYSCTRL_PID0 = {32'h00000026}; // 0xFE0 : PID 0 part number[7:0]
+localparam ARM_CMSDK_CM0_SYSCTRL_PID1 = {32'h000000B8}; // 0xFE4 : PID 1 [7:4] jep106_id_3_0. [3:0] part number [11:8]
+localparam ARM_CMSDK_CM0_SYSCTRL_PID2 = {32'h0000001B}; // 0xFE8 : PID 2 [7:4] revision, [3] jedec_used. [2:0] jep106_id_6_4
+localparam ARM_CMSDK_CM0_SYSCTRL_PID3 = {32'h00000000}; // 0xFEC : PID 3
+localparam ARM_CMSDK_CM0_SYSCTRL_CID0 = {32'h0000000D}; // 0xFF0 : CID 0
+localparam ARM_CMSDK_CM0_SYSCTRL_CID1 = {32'h000000F0}; // 0xFF4 : CID 1 PrimeCell class
+localparam ARM_CMSDK_CM0_SYSCTRL_CID2 = {32'h00000005}; // 0xFF8 : CID 2
+localparam ARM_CMSDK_CM0_SYSCTRL_CID3 = {32'h000000B1}; // 0xFFC : CID 3
+ // Note : Customer changing the design should modify
+ // - jep106 value (www.jedec.org)
+ // - part number (customer define)
+ // - Optional revision and modification number (e.g. rXpY)
+
+ // --------------------------------------------------------------------------
+ // Internal wires
+ // --------------------------------------------------------------------------
+
+ reg [31:0] read_mux;
+ reg [31:0] read_mux_le; // little endian of read mux
+ reg reg_remap;
+`ifdef CORTEX_M0DESIGNSTART
+ wire reg_pmuenable;
+`else
+ reg reg_pmuenable;
+`endif
+ reg reg_lockupreset;
+ reg [2:0] reg_resetinfo;
+
+ // ----------------------------------------------------------
+ // Read/write control logic
+ // ----------------------------------------------------------
+
+ wire bigendian = (BE!=0) ? 1'b1 : 1'b0;
+ wire ahb_access = HTRANS[1] & HSEL & HREADY;
+ wire ahb_write = ahb_access & HWRITE;
+ wire ahb_read = ahb_access & (~HWRITE);
+ wire [3:0] nxt_byte_strobe;
+ reg [3:0] reg_byte_strobe;
+ reg reg_read_enable;
+ reg reg_write_enable;
+ reg [11:2] reg_addr;
+ reg [1:0] reg_hsize;
+ reg [31:0] HWDATALE; // Little endian version of HWDATA
+
+ // Generate byte strobes to allow the GPIO registers to handle different transfer sizes
+ assign nxt_byte_strobe[0] = (HSIZE[1] | ((HADDR[1]==1'b0) & HSIZE[0]) | (HADDR[1:0]==2'b00)) & ahb_access;
+ assign nxt_byte_strobe[1] = (HSIZE[1] | ((HADDR[1]==1'b0) & HSIZE[0]) | (HADDR[1:0]==2'b01)) & ahb_access;
+ assign nxt_byte_strobe[2] = (HSIZE[1] | ((HADDR[1]==1'b1) & HSIZE[0]) | (HADDR[1:0]==2'b10)) & ahb_access;
+ assign nxt_byte_strobe[3] = (HSIZE[1] | ((HADDR[1]==1'b1) & HSIZE[0]) | (HADDR[1:0]==2'b11)) & ahb_access;
+
+ // Data phase read write and byte lane strobe
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ begin
+ reg_byte_strobe <= 4'b0000;
+ reg_read_enable <= 1'b0;
+ reg_write_enable <= 1'b0;
+ end
+ else if (HREADY)
+ begin
+ reg_byte_strobe <= nxt_byte_strobe;
+ reg_read_enable <= ahb_read;
+ reg_write_enable <= ahb_write;
+ end
+ end
+
+ // registered address, undate only if selected to reduce toggling
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_addr <= {10{1'b0}};
+ else if (ahb_access)
+ reg_addr <= HADDR[11:2];
+ end
+
+ // registered hsize, update only if selected to reduce toggling
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_hsize <= {2{1'b0}};
+ else if (ahb_access)
+ reg_hsize <= HSIZE[1:0];
+ end
+
+
+ // Read operation
+ always @(reg_addr or reg_remap or reg_pmuenable or ECOREVNUM or
+ reg_lockupreset or reg_resetinfo or reg_read_enable)
+ begin
+ case (reg_read_enable)
+ 1'b1:
+ begin
+ if (reg_addr[11:5] == 7'h00) begin
+ case(reg_addr[4:2])
+ 3'b000: read_mux_le ={{31{1'b0}}, reg_remap} ;
+ 3'b001: read_mux_le ={{31{1'b0}}, reg_pmuenable} ;
+ 3'b010: read_mux_le ={{31{1'b0}}, reg_lockupreset} ;
+ 3'b100: read_mux_le ={{29{1'b0}}, reg_resetinfo} ;
+ 3'b011,3'b101,3'b110,3'b111: read_mux_le = {32{1'b0}};
+ default: read_mux_le = {32{1'bx}};
+ endcase
+ end
+ else if (reg_addr[11:6] == 6'h3F)begin
+ case (reg_addr[5:2])
+ 4'h4: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID4; //0xFD0 Peripheral ID 4
+ 4'h5: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID5; //0xFD4 Peripheral ID 5
+ 4'h6: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID6; //0xFD8 Peripheral ID 6
+ 4'h7: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID7; //0xFDC Peripheral ID 7
+ 4'h8: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID0; //0xFE0 Peripheral ID 0
+ 4'h9: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID1; //0xFE4 Peripheral ID 1
+ 4'hA: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_PID2; //0xFE8 Peripheral ID 2
+ 4'hB: read_mux_le = {ARM_CMSDK_CM0_SYSCTRL_PID3[31:8], ECOREVNUM[3:0], 4'h0}; //0xFEC Peripheral ID 3
+ 4'hC: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_CID0; //0xFF0 Component ID 0
+ 4'hD: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_CID1; //0xFF4 Component ID 1
+ 4'hE: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_CID2; //0xFF8 Component ID 2
+ 4'hF: read_mux_le = ARM_CMSDK_CM0_SYSCTRL_CID3; //0xFFC Component ID 3
+ 4'h0, 4'h1, 4'h2,4'h3: read_mux_le = {32{1'b0}};
+ default: read_mux_le = {32{1'bx}};
+ endcase
+ end
+ else begin
+ read_mux_le = {32{1'b0}};
+ end
+ end
+ 1'b0:// read_enable is not active
+ begin
+ read_mux_le = {32{1'b0}};
+ end
+ default:
+ read_mux_le = {32{1'bx}};
+ endcase
+ end
+
+ // endian conversion
+ always @(bigendian or reg_hsize or read_mux_le or HWDATA)
+ begin
+ if ((bigendian)&(reg_hsize==2'b10))
+ begin
+ read_mux = {read_mux_le[ 7: 0],read_mux_le[15: 8],
+ read_mux_le[23:16],read_mux_le[31:24]};
+ HWDATALE = {HWDATA[ 7: 0],HWDATA[15: 8],HWDATA[23:16],HWDATA[ 31:24]};
+ end
+ else if ((bigendian)&(reg_hsize==2'b01))
+ begin
+ read_mux = {read_mux_le[23:16],read_mux_le[31:24],
+ read_mux_le[ 7: 0],read_mux_le[15: 8]};
+ HWDATALE = {HWDATA[23:16],HWDATA[ 31:24],HWDATA[ 7: 0],HWDATA[15: 8]};
+ end
+ else
+ begin
+ read_mux = read_mux_le;
+ HWDATALE = HWDATA;
+ end
+ end
+ // ----------------------------------------------------------
+ // Remap register
+ // ----------------------------------------------------------
+ wire reg_remap_write;
+ assign reg_remap_write = reg_write_enable &
+ (reg_addr[11:2] == 10'h000) & reg_byte_strobe[0];
+
+ // registering stage
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_remap <= 1'b1;
+ else if (reg_remap_write)
+ reg_remap <= HWDATALE[0];
+ end
+
+ // ----------------------------------------------------------
+ // PMUENABLE register
+ // ----------------------------------------------------------
+
+`ifdef CORTEX_M0DESIGNSTART
+ // Power management unit not available with Cortex-M0 DesignStart.
+ // PMU control is disabled
+ assign reg_pmuenable = 1'b0;
+`else
+ // Normal Cortex-M0 can have a programmable PMU
+ wire reg_pmuenable_write;
+ assign reg_pmuenable_write = reg_write_enable &
+ (reg_addr[11:2] == 10'h001) & reg_byte_strobe[0];
+
+ // registering stage
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_pmuenable <= 1'b0;
+ else if (reg_pmuenable_write)
+ reg_pmuenable <= HWDATALE[0];
+ end
+`endif
+
+ // ----------------------------------------------------------
+ // LOCKUPRESETEN register
+ // ----------------------------------------------------------
+ wire reg_lockupreset_write;
+ assign reg_lockupreset_write = reg_write_enable &
+ (reg_addr[11:2] == 10'h002) & reg_byte_strobe[0];
+
+ // registering stage
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_lockupreset <= 1'b0;
+ else if (reg_lockupreset_write)
+ reg_lockupreset <= HWDATALE[0];
+ end
+
+ // ----------------------------------------------------------
+ // Reset information register
+ // ----------------------------------------------------------
+
+ wire reg_resetinfo_write;
+ assign reg_resetinfo_write = reg_write_enable &
+ (reg_addr[11:2] == 10'h004) & reg_byte_strobe[0];
+
+ // capture reset information
+ wire [2:0] nxt_resetinfo;
+ // Write 1 to clear
+ assign nxt_resetinfo[0] = ((~(reg_resetinfo_write & HWDATALE[0])) & reg_resetinfo[0]) | SYSRESETREQ;
+ assign nxt_resetinfo[1] = ((~(reg_resetinfo_write & HWDATALE[1])) & reg_resetinfo[1]) | WDOGRESETREQ;
+ assign nxt_resetinfo[2] = ((~(reg_resetinfo_write & HWDATALE[2])) & reg_resetinfo[2]) | (reg_lockupreset & LOCKUP);
+
+ // Enable flip-flop only if it should be updated to reduce power
+ wire reg_resetinfo_en;
+ assign reg_resetinfo_en = reg_resetinfo_write | SYSRESETREQ | WDOGRESETREQ | (reg_lockupreset & LOCKUP);
+
+ // registering stage
+ always @(posedge FCLK or negedge PORESETn)
+ begin
+ if (~PORESETn)
+ reg_resetinfo <= 3'b000;
+ else if (reg_resetinfo_en)
+ reg_resetinfo <= nxt_resetinfo;
+ end
+
+ // Connect to higher level
+ assign REMAP = reg_remap;
+ assign PMUENABLE = reg_pmuenable;
+ assign LOCKUPRESET = reg_lockupreset;
+
+ assign HREADYOUT = 1'b1;
+ assign HRDATA = read_mux;
+ assign HRESP = 1'b0;
+
+endmodule
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_uart_capture.v b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_uart_capture.v
new file mode 100644
index 0000000000000000000000000000000000000000..cbc46f7ed04fd18feaa300f2e03dc542864feb42
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_uart_capture.v
@@ -0,0 +1,251 @@
+//-----------------------------------------------------------------------------
+// updated UART RXD capture with file logging
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : A device to capture serial data
+//-----------------------------------------------------------------------------
+// This module assume CLK is same frequency as baud rate.
+// In the example UART a test mode is used to enable data output as maximum
+// speed (PCLK). In such case we can connect CLK signal directly to PCLK.
+// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
+// accordingly as well.
+//
+// This module stop the simulation when character 0x04 is received.
+// An output called SIMULATION_END is set for 1 cycle before simulation is
+// terminated to allow other testbench component like profiler (if any)
+// to output reports before the simulation stop.
+//
+// This model also support ESCAPE (0x1B, decimal 27) code sequence
+// ESC - 0x10 - XY Capture XY to AUXCTRL output
+// ESC - 0x11 Set DEBUG_TESTER_ENABLE to 1
+// ESC - 0x12 Clear DEBUG_TESTER_ENABLE to 0
+
+
+module cmsdk_uart_capture
+ #(parameter LOGFILENAME = "uart.log",
+ parameter VERBOSE = 0)
+ (
+ input wire RESETn, // Power on reset
+ input wire CLK, // Clock (baud rate)
+ input wire RXD, // Received data
+ output wire SIMULATIONEND, // Simulation end indicator
+ output wire DEBUG_TESTER_ENABLE, // Enable debug tester
+ output wire [7:0] AUXCTRL); // Auxiliary control
+
+ reg [8:0] rx_shift_reg;
+ wire [8:0] nxt_rx_shift;
+ reg [6:0] string_length;
+ reg [7:0] tube_string [127:0];
+ reg [7:0] text_char;
+ integer i;
+ reg nxt_end_simulation;
+ reg reg_end_simulation;
+ wire char_received;
+ reg reg_esc_code_mode; // Escape code mode
+ reg reg_aux_ctrl_mode; // Auxiliary control capture mode
+ reg [7:0] reg_aux_ctrl; // Registered Auxiliary control
+ reg reg_dbgtester_enable;
+
+ integer mcd; // channel descriptor for log file output
+ reg [40*8-1:0] log_file; // File name can't be > *40* characters
+
+`define UartSTDOUT 32'h00000001
+ initial
+ begin
+ $timeformat(-9, 0, " ns", 14);
+ log_file = LOGFILENAME;
+ mcd = $fopen(log_file);
+ mcd = mcd | `UartSTDOUT; // always echo to console
+ if(mcd == 0) begin
+ $fwrite(mcd,"tarmac: Error, zero returned in response to $fopen\n");
+ $finish(2);
+ end
+ $fwrite(mcd,"uartcapture: Generating output file %0s using MCD %x @ %m\n",
+ log_file, mcd);
+ end
+
+ // Receive shift register
+ assign nxt_rx_shift = {RXD,rx_shift_reg[8:1]};
+ assign char_received = (rx_shift_reg[0]==1'b0);
+
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ rx_shift_reg <= {9{1'b1}};
+ else
+ if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
+ rx_shift_reg <= {9{1'b1}};
+ else
+ rx_shift_reg <= nxt_rx_shift;
+ end
+
+ // Escape code mode register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_esc_code_mode <= 1'b0;
+ else // Set to escape mode if ESC code is detected
+ if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
+ reg_esc_code_mode <= 1'b1;
+ else if (char_received)
+ reg_esc_code_mode <= 1'b0;
+ end
+
+ // Aux Ctrl capture mode register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_aux_ctrl_mode <= 1'b0;
+ else // Set to Aux control capture mode if ESC-0x10 sequence is detected
+ if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
+ reg_aux_ctrl_mode <= 1'b1;
+ else if (char_received)
+ reg_aux_ctrl_mode <= 1'b0;
+ end
+
+ // Aux Ctrl capture data register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_aux_ctrl <= {8{1'b0}};
+ else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
+ if (char_received & (reg_aux_ctrl_mode==1'b1))
+ reg_aux_ctrl <= rx_shift_reg[8:1];
+ end
+
+ assign AUXCTRL = reg_aux_ctrl;
+
+ // Debug tester enable
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_dbgtester_enable <= 1'b0;
+ else // Enable debug tester if ESC-0x11 sequence is detected
+ if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
+ reg_dbgtester_enable <= 1'b1;
+ else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
+ // Disable debug tester if ESC-0x12 sequence is detected
+ reg_dbgtester_enable <= 1'b0;
+ end
+
+ assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
+
+ // Message display
+ always @ (posedge CLK or negedge RESETn)
+ begin: p_tube
+ if (~RESETn)
+ begin
+ string_length = 7'b0;
+ nxt_end_simulation <= 1'b0;
+ for (i=0; i<= 127; i=i+1) begin
+ tube_string [i] = 8'h00;
+ end
+ end
+ else
+ if (char_received)
+ begin
+ if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
+ begin
+ // Escape code, or in escape code mode
+ // Data receive can be command, aux ctrl data
+ // Ignore this data
+ end
+ else if (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
+ nxt_end_simulation <= 1'b1;
+ else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
+ // New line
+ begin
+ tube_string[string_length] = 8'h00;
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: ",$time);
+
+ for (i=0; i<= string_length; i=i+1)
+ begin
+ text_char = tube_string[i];
+ $fwrite(mcd,"%s",text_char);
+ end
+
+ $fwrite(mcd,"\n");
+ string_length = 7'b0;
+ end
+ else
+ begin
+ tube_string[string_length] = rx_shift_reg[8:1];
+ string_length = string_length + 1;
+ if (string_length >79) // line too long, display and clear buffer
+ begin
+ tube_string[string_length] = 8'h00;
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: ",$time);
+
+ for (i=0; i<= string_length; i=i+1)
+ begin
+ text_char = tube_string[i];
+ $fwrite(mcd,"%s",text_char);
+ end
+
+ $fwrite(mcd,"\n");
+ string_length = 7'b0;
+
+ end
+
+ end
+
+ end
+
+ end // p_TUBE
+
+ // Delay for simulation end
+ always @ (posedge CLK or negedge RESETn)
+ begin: p_sim_end
+ if (~RESETn)
+ begin
+ reg_end_simulation <= 1'b0;
+ end
+ else
+ begin
+ reg_end_simulation <= nxt_end_simulation;
+ if (reg_end_simulation==1'b1)
+ begin
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: Test Ended\n",$time);
+ else
+ $fwrite(mcd,"Test Ended\n");
+ $stop;
+ end
+ end
+ end
+
+ assign SIMULATIONEND = nxt_end_simulation & (~reg_end_simulation);
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/README.txt b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..815517646f691ef3c9f91085fc744b984063ff7d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/README.txt
@@ -0,0 +1,66 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : AHB BusMatrix top level README file
+//------------------------------------------------------------------------------
+
+Introduction
+------------
+
+This directory contains the AHB BusMatrix component.
+
+cmsdk_ahb_busmatrix/bin/BuildBusMatrix.pl
+ The AHB BusMatrix is a configurable component. The configuration
+ process is handled by a Perl script, located in bin/BuildBusMatrix.pl
+
+cmsdk_ahb_busmatrix/verilog/src
+ The source code of the configurable AHB Bus matrix is located in
+ verilog/src directory. Do not use the Verilog files in this directory
+ directly.
+
+cmsdk_ahb_busmatrix/verilog/built
+ After configuration process, the Verilog files generated will be stored
+ in verilog/built directory.
+
+cmsdk_ahb_busmatrix/xml/
+ During the configuration process, the configuration of the AHB BusMatrix
+ can be controlled by command line options or by an XML file.
+ Example XML files can be found in the xml directory.
+
+cmsdk_mtx4x2/verilog/
+ A preconfigured version of AHB Bus matrix for the example Cortex-M3/M4
+ system is prepared in the cmsdk_mcu_mtx4x2 directory. The configuration
+ of this bus matrix can be found in cmsdk_mcu_mtx4x2/xml/
+
+Several example AHB Bus Matrix configuration XML files are provided.
+You can generate the AHB bus matrix RTL by running the following command:
+
+> cd logical/cmsdk_ahb_busmatrix
+> bin/BuildBusMatrix.pl -xmldir xml -cfg example2x3_full.xml -over -verbose
+
+
+Please refer to the Cortex-M System Design Kit Technical Reference Manual for
+further details on the use of this component.
+
+======================== End of README.txt ===========================
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/bin/BuildBusMatrix.pl b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/bin/BuildBusMatrix.pl
new file mode 100755
index 0000000000000000000000000000000000000000..73aa34ef8177a83f40949159df991f6f5ed51fe6
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/bin/BuildBusMatrix.pl
@@ -0,0 +1,2975 @@
+eval "exec perl -w -S $0 $@" # -*- Perl -*-
+ if ($running_under_some_sh);
+ undef ($running_under_some_sh);
+
+################################################################################
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+################################################################################
+# Version and Release Control Information:
+#
+# File Name : $RCSfile: BuildBusMatrix.pl,v $
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#
+################################################################################
+
+################################################################################
+# Purpose : Builds particular configurations of the AHB BusMatrix
+#
+################################################################################
+# Usage:
+# Builds an AHB Bus Matrix component with a given number of input ports,
+# a given number of output ports, a particular arbitration scheme and ARM
+# processor interface.
+#
+# Notes: This version of the script uses an interface information hash with
+# the following structure:
+#
+# my %InterfaceInfo = (
+# SLAVES => {
+# SI<n> => {
+# NAME => '@name',
+# CONNECTIONS => [ @MI<n> ... ],
+# ADDRESS_MAP => {
+# NORMAL => [ <address_info> ... ],
+# REMAP => [ <remap_info> ... ]
+# }
+# }
+# },
+#
+# MASTERS => {
+# MI<n> => {
+# NAME => '@name',
+# CONNECTIONS => [ @SI<n> ... ]
+# }
+# }
+# );
+#
+# Options: See the ShowHelp() function.
+#
+################################################################################
+
+# ------------------------------------------------------------------------------
+# Load PERL libraries
+# ------------------------------------------------------------------------------
+
+use strict;
+use warnings;
+use Getopt::Long;
+
+use lib 'bin/lib'; # Collapse namespace 'lib::'
+use xmlparser; # Load the XML parser module
+
+use Data::Dumper;
+use Storable 'dclone';
+use File::Spec;
+
+# ------------------------------------------------------------------------------
+# Declare global variables
+# ------------------------------------------------------------------------------
+
+# General script variables
+my $Debug = 0;
+my $RenderDebug = 0;
+my $Errors = 0;
+my $HdlType = 'verilog';
+my $HdlExt = '.v';
+my $Connections = '';
+my $Sparse = 0;
+my $DefaultSlave = 'cmsdk_ahb_bm_default_slave';
+
+# Parameter legal ranges
+my $MinSlaveIF = 1;
+my $MaxSlaveIF = 16;
+my $MinMasterIF = 1;
+my $MaxMasterIF = 16;
+my $DataWidths = '32|64';
+my $MinNameLength = 1;
+my $MaxNameLength = 128;
+my $MinUserWidth = 0;
+my $MaxUserWidth = 32;
+my $MinAddrWidth = 32;
+my $MaxAddrWidth = 64;
+
+# Interface ID tags (updated later)
+my $IdWidthMI = 4;
+my $IdWidthSI = 4;
+
+# Interface information hash
+my %InterfaceInfo = ();
+
+# A processed version needed for the differences in IPXact
+my %InterfaceInfoIPXact = ();
+
+# Remap state information hash
+my %RemapStates = ();
+
+# Address space information hash
+my %AddressSpace = ();
+
+# Get the run date and correct offset
+my ( $Sec, $Min, $Hour, $Mday, $Mon, $Year ) = localtime(time); $Year+=1900; $Mon++;
+
+# Filename variables
+my %FileList = ();
+my ($Scriptname) = $0 =~ /([\w\.]+)$/;
+
+# Hash for search and replacement of macros
+my %Macro = ();
+
+# Hash for processing text sections
+my %Section = ();
+
+# Arrays of instance names
+my @MatrixDecodeNames = ();
+my @OutputArbNames = ();
+my @OutputStageNames = ();
+
+# Hash for remapping information
+my %RemapInfo = ();
+
+# Hash array of name aliases
+my %NameAliases = ();
+
+# IP-XACT component name - default value is set later
+my $ComponentName = '';
+
+
+# ------------------------------------------------------------------------------
+# Check for pre-requisites
+# ------------------------------------------------------------------------------
+
+# Check for the supported OS platform(s)
+unless ( $^O =~ /(solaris|linux)\b/ ) {
+ die "Error: This script does not support the '$^0' OS!\n\n";
+}
+
+# Check for the required version of PERL
+unless ( $] >= 5.005 ) {
+ die "Error: This script requires PERL version >= 5.005!\n\n";
+}
+
+# Check system clock for inappropriate roll-back - the date is used
+# in the copyright field of file headers
+unless ( $Year >= 2013 ) {
+ warn "Warning: The system clock is incorrectly set to '$Year'!\n";
+ $Year = 2013;
+}
+
+
+# ------------------------------------------------------------------------------
+# Parse the command line
+# ------------------------------------------------------------------------------
+
+# Default values for command-line options
+my $SlaveInterfaces = 1;
+my $MasterInterfaces = 1;
+my $Connectivity = 'full';
+my $ArbiterType = 'fixed';
+my $ArchitectureType = 'ahb2';
+my $XmlConfigFile = '';
+my $RoutingDataWidth = 32;
+my $RoutingAddressWidth = 32;
+my $UserSignalWidth = 0;
+my $OutputArbName = 'cmsdk_ahb_bm_output_arb';
+my $OutputStageName = 'cmsdk_ahb_bm_output_stage';
+my $MatrixDecodeName = 'cmsdk_ahb_bm_decode';
+my $InputStageName = 'cmsdk_ahb_bm_input_stage';
+my $BusMatrixName = ''; # Default value is set later
+my $Help = 0;
+my $Verbose = 0;
+my $SourceDir = "./$HdlType/src";
+my $TargetDir = "./$HdlType/built";
+my $IPXactSourceDir = "./ipxact/src";
+my $IPXactTargetDir = "./ipxact/built";
+my $XmlDir = './xml';
+my $Overwrite = 0;
+my $Timescales = 0;
+my $NoTimescales = 0;
+my $XmlTimescales = 0;
+my $CheckMode = 0;
+my $IPXact = 0;
+
+
+# Display usage message if requested
+if ( grep(/^-?-help$/, @ARGV) ) { ShowHelp(); }
+
+# Get command line arguments
+GetOptions( 'inports=i' => \$SlaveInterfaces,
+ 'outports=i' => \$MasterInterfaces,
+ 'connectivity=s' => \$Connectivity,
+ 'arb=s' => \$ArbiterType,
+ 'arch=s' => \$ArchitectureType,
+ 'cfg=s' => \$XmlConfigFile,
+ 'datawidth=i' => \$RoutingDataWidth,
+ 'addrwidth=i' => \$RoutingAddressWidth,
+ 'userwidth=i' => \$UserSignalWidth,
+ 'outputarb=s' => \$OutputArbName,
+ 'outputstage=s' => \$OutputStageName,
+ 'matrixdecode=s' => \$MatrixDecodeName,
+ 'inputstage=s' => \$InputStageName,
+ 'busmatrix=s' => \$BusMatrixName,
+ 'verbose' => \$Verbose,
+ 'srcdir=s' => \$SourceDir,
+ 'tgtdir=s' => \$TargetDir,
+ 'ipxactsrcdir=s' => \$IPXactSourceDir,
+ 'ipxacttgtdir=s' => \$IPXactTargetDir,
+ 'xmldir=s' => \$XmlDir,
+ 'overwrite' => \$Overwrite,
+ 'timescales' => \$Timescales, 'notimescales' => \$NoTimescales,
+ 'check' => \$CheckMode,
+ 'ipxact' => \$IPXact,
+ 'debug' => \$Debug,
+ 'renderdebug' => \$RenderDebug,
+ );
+
+if ( $Timescales and $NoTimescales ) {
+ die "Error: Can't use --timescales and --notimescales at the same time\n";
+}
+
+# Display script header when in verbose mode
+if ( $Verbose ) {
+ printf "\n==============================================================\n" .
+ "= The confidential and proprietary information contained in this file may\n" .
+ "= only be used by a person authorised under and to the extent permitted\n" .
+ "= by a subsisting licensing agreement from Arm Limited or its affiliates.\n" .
+ "= \n" .
+ "= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.\n" .
+ "= ALL RIGHTS RESERVED\n" .
+ "= \n" .
+ "= This entire notice must be reproduced on all copies of this file\n" .
+ "= and copies of this file may only be made by a person if such person is\n" .
+ "= permitted to do so under the terms of a subsisting license agreement\n" .
+ "= from Arm Limited or its affiliates.\n" .
+ "=\n" .
+ "= $Scriptname\n" .
+ "=\n" .
+ "= Run Date : %02d/%02d/%04d %02d:%02d:%02d" .
+ "\n==============================================================\n\n",
+ $Mday, $Mon, $Year, $Hour, $Min, $Sec;
+}
+
+
+# ------------------------------------------------------------------------------
+# Parse the configuration file if specified, or initialise by elaborating
+# the '-connectivity' command-line argument and calculating an address map
+# ------------------------------------------------------------------------------
+
+if ( $XmlConfigFile ne '' ) {
+ # Conditionally prepend the XML directory path to the filename
+ if ( $XmlConfigFile !~ /^$XmlDir/ ) { $XmlConfigFile = "$XmlDir/$XmlConfigFile"; }
+ $XmlConfigFile = TidyPath($XmlConfigFile);
+
+ # Configure and run the XML parser
+ ProcessXmlConfigFile();
+} else {
+ # Translate into internal form, the design specified on the command line
+ InitialiseInterfaceInfo();
+}
+
+ # Do some preprocessing for IPXact generation
+ if ($IPXact) {
+ ProcessDataForIPXact();
+ }
+
+# Set the default top-level name if required
+if ( $BusMatrixName eq '' ) {
+ $BusMatrixName = sprintf( "cmsdk_ahb_busmatrix%dx%d%s%dd%da%du", $SlaveInterfaces,
+ $MasterInterfaces, substr($ArbiterType, 0, 1),
+ $RoutingDataWidth, $RoutingAddressWidth, $UserSignalWidth );
+}
+
+# Set the default IP-XACT component name if required
+if ( $ComponentName eq '' ) { $ComponentName = $BusMatrixName . "_lite"; }
+
+
+# ------------------------------------------------------------------------------
+# Validate the parameters and abort if necessary
+# ------------------------------------------------------------------------------
+
+ValidateParameters();
+if ( $Errors ) { die "\nBuild not started because of parameter errors!\n\n"; }
+
+
+# ------------------------------------------------------------------------------
+# Determine calculated parameters
+# ------------------------------------------------------------------------------
+
+SelectParameters();
+
+
+# ------------------------------------------------------------------------------
+# Display settings when in verbose mode
+# ------------------------------------------------------------------------------
+
+my $XmlTimescales_interpreted = ($XmlTimescales eq 'yes' || $XmlTimescales eq 'no') ? $XmlTimescales
+ : "no ($XmlTimescales)";
+
+if ( $Verbose ) {
+ printf "Script accepted the following parameters:\n\n" .
+ "%s - Top-level name : '$BusMatrixName'\n" .
+ " - Slave interfaces : $SlaveInterfaces\n" .
+ " - Master interfaces : $MasterInterfaces\n" .
+ " - Architecture type : '$ArchitectureType'\n" .
+ " - Arbitration scheme : '$ArbiterType'\n" .
+ " - Address map : %s\n" .
+ " - Connectivity mapping : %s\n" .
+ " - Connectivity type : %s\n" .
+ " - Routing data width : $RoutingDataWidth\n" .
+ " - Routing address width : $RoutingAddressWidth\n" .
+ " - User signal width : $UserSignalWidth\n" .
+ " - Timescales : ". ($Timescales ? "yes" :
+ $NoTimescales ? "no" :
+ '') .
+ ( $XmlTimescales ? $Timescales || $NoTimescales ? " - overriding $XmlTimescales_interpreted setting from XML"
+ : "$XmlTimescales_interpreted (from XML)"
+ : '' ) .
+ ( ! ($XmlTimescales || $Timescales || $NoTimescales) ? 'yes (default)' : '') . "\n" .
+ " - Configuration directory : '$TargetDir'\n" .
+ " - Source directory : '$SourceDir'\n" .
+ ($IPXact ?
+ " - IPXact target directory : '$IPXactTargetDir'\n" .
+ " - IPXact source directory : '$IPXactSourceDir'\n" : "") .
+ " - Overwrite mode : %s\n\n",
+ ( $XmlConfigFile ne '' ) ? " - Configuration file : '$XmlConfigFile'\n" : '',
+ ( $XmlConfigFile ne '' ) ? 'user defined' : 'calculated',
+ ( $Connectivity ne 'full' ) ? $Connections : 'automatic',
+ ( $Sparse ) ? 'sparse' : 'full',
+ ( $Overwrite ) ? 'enabled' : 'disabled';
+}
+
+
+# ------------------------------------------------------------------------------
+# Expand template macros if not in check mode
+# ------------------------------------------------------------------------------
+
+unless ( $CheckMode ) { CreateBusMatrix(); }
+
+
+################################################################################
+### Subroutines and Functions ##################################################
+################################################################################
+
+# ------------------------------------------------------------------------------
+# SelectParameters - Selects the corresponding parameter set according to
+# the fundamental specification
+# ------------------------------------------------------------------------------
+sub SelectParameters {
+
+ # Local variable(s)
+ my $Instance = '';
+ my $Index = 0;
+ my $Interface = '';
+ my %Arbiter = ( fixed => 'cmsdk_ahb_bm_fixed_arb', round => 'cmsdk_ahb_bm_round_arb', burst => 'cmsdk_ahb_bm_burst_arb' );
+ my $ArbType = '';
+ my $OutType = '';
+ my $BstrbWidth = $RoutingDataWidth / 8;
+ my $MakefileName = 'makefile';
+ my $MkfileName = 'cmsdk_ahb_busmatrix.mk';
+ my $IPXactFile_AHB2 = 'cmsdk_ahb_busmatrix_ipxact.xml';
+ my $IPXactFile_AHBLite = 'cmsdk_ahb_busmatrix_lite_ipxact.xml';
+ my $Mappings = $Connections;
+ my $Packing = ' ' x 14;
+ my $Unmapping = '';
+ my $RemapBit = 0;
+ my $OpenBr = '';
+ my $CloseBr = '';
+ my @RemapBits = ();
+
+ # Determine the connectivity type
+ $Sparse = IsSparse();
+
+ # Determine the slave interface ID width
+ $IdWidthSI = NumberOfDigits($SlaveInterfaces - 1, 2);
+
+ # Determine the master interface ID width, including an MSbit for
+ # selecting the default slave
+ $IdWidthMI = NumberOfDigits($MasterInterfaces - 1, 2) + 1;
+
+ # Format the mappings
+ $Mappings =~ s/\n/\n\/\//g;
+
+ # Determine single entity filenames
+ #$FileList{$MkfileName} = $MkfileName; # Note:Generation of ADK makefile is not required in BP210
+ #$FileList{$MakefileName} = $MakefileName; # Note:Generation of ADK makefile is not required in BP210
+ if ( $IPXact ) { $FileList{$ComponentName . '.xml'} = $IPXactFile_AHBLite; # Component already contains the -lite suffix or other name
+ $FileList{$BusMatrixName . '.xml'} = $IPXactFile_AHB2; }
+ $DefaultSlave = $BusMatrixName . '_default_slave';
+ $FileList{$BusMatrixName . $HdlExt} = 'cmsdk_ahb_busmatrix' . $HdlExt;
+ $FileList{$ComponentName . $HdlExt} = 'cmsdk_ahb_busmatrix_lite' . $HdlExt;
+ $FileList{$InputStageName . $HdlExt} = 'cmsdk_ahb_bm_input_stage' . $HdlExt;
+ $FileList{$DefaultSlave . $HdlExt} = 'cmsdk_ahb_bm_default_slave' . $HdlExt;
+
+ # Generate filenames and macro names for each instance of bm_decode
+ # and process any REMAP declarations accordingly
+ $Section{'remap_used'} = '0';
+ $Section{'no_remap_used'} = '1';
+ for ( $Index = 0; $Index < $SlaveInterfaces; $Index++ ) {
+ $Interface = 'SI' . $Index;
+
+ $Instance = $MatrixDecodeName . $InterfaceInfo{SLAVES}{$Interface}{NAME};
+ $FileList{$Instance . $HdlExt} = 'cmsdk_ahb_bm_decode' . $HdlExt;
+ push @MatrixDecodeNames, $Instance;
+
+ $RemapInfo{$Interface}{REMAP_BITS} = [];
+ $RemapInfo{$Interface}{REMAP_WIDTH} = 0;
+ $RemapInfo{$Interface}{REMAP_MAPPING} = {};
+ @RemapBits = ();
+ for ( $RemapBit = 0; $RemapBit < 4; $RemapBit++ ) {
+ if ( ( grep /:remap$RemapBit:/,
+ @{ $InterfaceInfo{SLAVES}{$Interface}{ADDRESS_MAP}{REMAP} } ) ||
+ ( grep /:.*(del|_|,|\s)$RemapBit(_|,|\s|:|$)/,
+ @{ $InterfaceInfoIPXact{SLAVES}{$Interface}{ADDRESS_MAP}{NORMAL} } ) ) {
+ push @RemapBits, "REMAP[$RemapBit]";
+ push @{ $RemapInfo{$Interface}{REMAP_BITS} }, $RemapBit;
+ $RemapInfo{$Interface}{REMAP_MAPPING}{$RemapBit} = $RemapInfo{$Interface}{REMAP_WIDTH};
+ $RemapInfo{$Interface}{REMAP_WIDTH}++;
+ $Section{'remap_used'} = '1';
+ $Section{'no_remap_used'} = '0';
+ }
+ }
+ $OpenBr = ( $RemapInfo{$Interface}{REMAP_WIDTH} > 1 ) ? '{ ' : '';
+ $CloseBr = ( $RemapInfo{$Interface}{REMAP_WIDTH} > 1 ) ? ' }' : '';
+ $RemapInfo{$Interface}{REMAP_PORT} = $OpenBr . join( ', ', reverse @RemapBits ) . $CloseBr;
+ }
+
+ print "RemapInfo:\n" if $Debug;
+ print Dumper(\%RemapInfo) if $Debug;
+
+
+ # Determine names for the output_arb and output_stage instances
+ if ( $Sparse ) {
+
+ # Generate filenames and macro names for each instance of output_stage and
+ # output_arb modules
+ for ( $Index = 0; $Index < $MasterInterfaces; $Index++ ) {
+ $Interface = 'MI' . $Index;
+
+ # If the current output stage has only one connection, then override
+ # the template selection for the arbiter type and output stage
+ $ArbType = $Arbiter{$ArbiterType}; $OutType = 'cmsdk_ahb_bm_output_stage';
+ unless ( @{ $InterfaceInfo{MASTERS}{$Interface}{CONNECTIONS} } > 1 ) {
+ $ArbType = 'cmsdk_ahb_bm_single_arb'; $OutType = 'cmsdk_ahb_bm_single_output_stage';
+ }
+
+ $Instance = $OutputArbName . $InterfaceInfo{MASTERS}{$Interface}{NAME};
+ $FileList{$Instance . $HdlExt} = $ArbType . $HdlExt;
+ push @OutputArbNames, $Instance;
+ $Instance = $OutputStageName . $InterfaceInfo{MASTERS}{$Interface}{NAME};
+ $FileList{$Instance . $HdlExt} = $OutType . $HdlExt;
+ push @OutputStageNames, $Instance;
+
+ }
+
+ } else {
+
+ # The same output_stage and output_arb modules are used in a fully connected
+ # bus matrix
+ $FileList{$OutputArbName . $HdlExt} = $Arbiter{$ArbiterType} . ${HdlExt};
+ push @OutputArbNames, $OutputArbName;
+ $FileList{$OutputStageName . $HdlExt} = 'cmsdk_ahb_bm_output_stage' . ${HdlExt};
+ push @OutputStageNames, $OutputStageName;
+
+ # Initialise particular static instance names
+ $Macro{'output_arb_name'} = $OutputArbName;
+ $Macro{'output_stage_name'} = $OutputStageName;
+ $Macro{'output_stage_name_lc'} = lc($Macro{'output_stage_name'});
+
+ }
+
+ # Conditionally initialise the macro and section control hashes
+
+ # Determine architecture options
+ if ( $ArchitectureType =~ /^(v6|excl)$/ ){
+ $Section{'excl'} = 1;
+ $Macro{'prot'} = 5;
+ $Macro{'prot_v'} = 6;
+ $Macro{'resp'} = 2;
+ $Macro{'resp_v'} = 3;
+ $Macro{'bin_resp_xfail'} = '100';
+ } else {
+ $Section{'excl'} = 0;
+ $Macro{'prot'} = 3;
+ $Macro{'prot_v'} = 4;
+ $Macro{'resp'} = 1;
+ $Macro{'resp_v'} = 2;
+ $Macro{'bin_resp_xfail'} = 'xx';
+ }
+
+ # Determine response encoding
+ $Macro{'bin_resp_okay'} = substr( '000', -$Macro{'resp_v'}, $Macro{'resp_v'} );
+ $Macro{'bin_resp_error'} = substr( '001', -$Macro{'resp_v'}, $Macro{'resp_v'} );
+ $Macro{'bin_resp_retry'} = substr( '010', -$Macro{'resp_v'}, $Macro{'resp_v'} );
+ $Macro{'bin_resp_split'} = substr( '011', -$Macro{'resp_v'}, $Macro{'resp_v'} );
+
+ # Determine HUNALIGN support and xUSER width
+ $Section{'unalign'} = ( $ArchitectureType =~ /^(v6|unalign)$/ ) ? 1 : 0;
+ $Section{'user'} = ( $UserSignalWidth > 0 ) ? 1 : 0;
+
+ # Bus width fields
+ $Macro{'data'} = $RoutingDataWidth - 1;
+ $Macro{'data_v'} = $RoutingDataWidth;
+ $Macro{'addr'} = $RoutingAddressWidth - 1;
+ $Macro{'addr_v'} = $RoutingAddressWidth;
+ $Macro{'user'} = $UserSignalWidth - 1;
+ $Macro{'user_v'} = $UserSignalWidth;
+ $Macro{'bstrb'} = $BstrbWidth - 1;
+ $Macro{'bstrb_v'} = $BstrbWidth;
+
+ $Macro{'address_space_range'} = $RoutingAddressWidth >= 40 ? (2**($RoutingAddressWidth-40) )."T" :
+ $RoutingAddressWidth >= 30 ? (2**($RoutingAddressWidth-30) )."G" :
+ $RoutingAddressWidth >= 20 ? (2**($RoutingAddressWidth-20) )."M" :
+ $RoutingAddressWidth >= 10 ? (2**($RoutingAddressWidth-10) )."K" :
+ 2**$RoutingAddressWidth ; # P and E not supported by IP-XACT standard
+
+ $Macro{'verilog_to_ipxact_path'} = File::Spec->abs2rel("$TargetDir/$BusMatrixName","$IPXactTargetDir/$BusMatrixName");
+
+ # Interface ID-width fields
+ $Macro{'idw_si'} = $IdWidthSI - 1;
+ $Macro{'idw_si_v'} = $IdWidthSI;
+ $Macro{'idw_mi'} = $IdWidthMI - 1;
+ $Macro{'idw_mi_v'} = $IdWidthMI;
+
+ # Determine default slave selection encoding (can be up to 5 bits)
+ $Macro{'dsid_bin'} = substr('10000', 0, $IdWidthMI);
+
+ # Determine a list of sub-module names
+ $Macro{'other_module_names'} = $DefaultSlave . " \\\n$Packing" .
+ $InputStageName . " \\\n$Packing" .
+ join( " \\\n$Packing", @MatrixDecodeNames ) .
+ " \\\n$Packing" .
+ join( " \\\n$Packing", @OutputArbNames ) .
+ " \\\n$Packing" .
+ join( " \\\n$Packing", @OutputStageNames );
+
+ # Initialise the static instance names
+ $Macro{'bus_matrix_name'} = $BusMatrixName;
+ $Macro{'input_stage_name'} = $InputStageName;
+ $Macro{'output_arb_stemname'} = $OutputArbName;
+ $Macro{'output_stage_stemname'} = $OutputStageName;
+ $Macro{'matrix_decode_stemname'} = $MatrixDecodeName;
+ $Macro{'component_name'} = $ComponentName;
+
+ # Miscellaneous fields
+ $Macro{'copyright_year'} = $Year;
+ $Macro{'timescale_directive'} = ( $NoTimescales || ( ($XmlTimescales eq 'no') && !$Timescales )) ? '' : "\n`timescale 1ns/1ps\n"; # On by default on CMSDK
+ $Macro{'arbiter_type'} = $ArbiterType;
+ $Macro{'architecture_type'} = $ArchitectureType;
+ $Macro{'total_si'} = $SlaveInterfaces;
+ $Macro{'total_mi'} = $MasterInterfaces;
+ $Macro{'connectivity'} = ( $Sparse ) ? 'sparse' : 'full';
+ $Macro{'mappings'} = ( $Sparse ) ? $Mappings :
+ sprintf("S<0..%d> -> M<0..%d>", $SlaveInterfaces - 1, $MasterInterfaces - 1);
+
+}
+
+
+# ------------------------------------------------------------------------------
+# CreateBusMatrix - Creates a version of the Bus Matrix using the currently
+# selected parameter set
+# ------------------------------------------------------------------------------
+sub CreateBusMatrix {
+
+ # Local variable(s)
+ my $VariantDir = "$TargetDir/$BusMatrixName";
+ my $IPXactVariantDir = "$IPXactTargetDir/$BusMatrixName";
+ my @ExistingFiles = glob( "$VariantDir/*" );
+ my @NewFiles = keys( %FileList );
+ my $File = '';
+
+ # Determine target preparation
+ if ( -e $VariantDir ) {
+ # Delete files when in overwrite mode, otherwise display an error
+ if ( $Overwrite ) {
+ foreach $File ( @ExistingFiles ) {
+ print "Deleting the '$File' file...\n" if ( $Verbose );
+ unlink $File or die "Error: Could not delete the file!\n\n";
+ }
+ print "\n" if ( @ExistingFiles and $Verbose );
+ } else {
+ die "Error: This variant of the bus matrix already exists!\n\n";
+ }
+ } else {
+ # Create the output directory for this Bus Matrix variant
+ mkdir $VariantDir or
+ die "Error: Could not create the output directory '$VariantDir'!\n\n";
+ }
+
+ if ($IPXact) {
+ @ExistingFiles = glob( "$IPXactVariantDir/*" );
+ # Determine ipxact target preparation
+ if ( -e $IPXactVariantDir ) {
+ # Delete files when in overwrite mode, otherwise display an error
+ if ( $Overwrite ) {
+ foreach $File ( @ExistingFiles ) {
+ print "Deleting the '$File' file...\n" if ( $Verbose );
+ unlink $File or die "Error: Could not delete the file!\n\n";
+ }
+ print "\n" if ( @ExistingFiles and $Verbose );
+ } else {
+ die "Error: IPXact directory for this variant of the bus matrix already exists!\n\n";
+ }
+ } else {
+ # Create the output directory for this Bus Matrix variant
+ mkdir $IPXactVariantDir or
+ die "Error: Could not create the output directory '$IPXactVariantDir'!\n\n";
+ }
+ }
+
+ # Process all required files
+ print "Creating the bus matrix variant...\n\n" if ( $Verbose );
+ foreach $File ( @NewFiles ) {
+ print " - Rendering '$File'\n" if ( $Verbose );
+ if ($FileList{$File} =~ /.*ipxact\.xml$/) {
+ RenderFile( "$IPXactSourceDir/$FileList{$File}", "$IPXactVariantDir/$File" );
+ } else{
+ RenderFile( "$SourceDir/$FileList{$File}", "$VariantDir/$File" );
+ }
+ }
+
+ print "\nDone!\n\n" if ( $Verbose );
+
+}
+
+
+# ------------------------------------------------------------------------------
+# RenderFile - Processes nested sections embedded hierarchically within the
+# specified template file, and expands macros accordingly. The
+# variables '$SlaveIF' and '$MasterIF' have a reserved use
+# depending upon the template being rendered. The variables may
+# be assigned values from 'in' or 'out' sections, or assigned
+# to a value extracted from a port-specific target filename. In
+# all other cases, these variables just retain their values
+# ------------------------------------------------------------------------------
+sub RenderFile {
+
+ # Passed parameter 1 is the template filename
+ my $TemplateFile = shift;
+ # Passed parameter 2 is the rendered output filename
+ my $RenderedFile = shift;
+
+ # Local variable(s)
+ my $TextLine = '';
+ my $Field = '';
+ my $Type = '';
+ my $Level = 0;
+ my $LineNum = 0;
+ my $StartName = '';
+ my $EndName = '';
+ my @Section = ( { LINE => 0, PTR => 0, NAME => '', COPIES => 0, COUNT => 0, EN => 1 } );
+ my ($SourceFile) = $TemplateFile =~ /([\w\.]+)$/;
+ my $RefId = 0;
+ my $Interface = '';
+ my $SlaveIF = '';
+ my $MasterIF = '';
+ my @MIRegions = ();
+ my @FoundRegions = ();
+ my $Decodings = 0;
+ my $Region = 0;
+ my $AddrLo = '';
+ my $AddrHi = '';
+ my $Remapping = '';
+ my $Unmapping = '';
+ my $RemapBit = 0;
+ my $Bit = 0;
+ my $RemapState = 0;
+ my @ActiveRemap = ();
+ my $GotFirst = 0;
+ my $Arbiters = 'cmsdk_ahb_bm_burst_arb|cmsdk_ahb_bm_fixed_arb|cmsdk_ahb_bm_round_arb|cmsdk_ahb_bm_single_arb';
+ my @PortIds = ();
+ my $TotalIds = 0;
+ my @IPXactFiles = ( $ComponentName, $BusMatrixName, $DefaultSlave, $InputStageName,
+ @MatrixDecodeNames, @OutputArbNames, @OutputStageNames );
+ my %RemapTypes = ( none => 'Static', alias => 'Alias', move => 'Unmoved' );
+ my $Debug = $RenderDebug;
+ my @i_remapstate = ();
+
+
+ # Open the template file for reading
+ open( IN, "<$TemplateFile")
+ or die "Cannot open input file '$TemplateFile'!\n\n";
+
+ # Open the output file for writing the rendered text
+ open( OUT, ">$RenderedFile" )
+ or die "Cannot open output file '$RenderedFile'!\n\n";
+
+ # For the bm_decode template only, initialise specific macros and variables
+ if ( $TemplateFile =~ /cmsdk_ahb_bm_decode$HdlExt$/ ) {
+
+ # Set the current instance name for search and replacement, and also extract
+ # the slave interface number for reference use
+ if ( ($SlaveIF) = $RenderedFile =~ /$MatrixDecodeName(\w+)$HdlExt$/ ) {
+ $Macro{'matrix_decode_name'} = $MatrixDecodeName . $SlaveIF;
+ $Macro{'matrix_decode_name_lc'} = lc($Macro{'matrix_decode_name'});
+ $SlaveIF = $NameAliases{$SlaveIF} if ( $XmlConfigFile ne '' );
+ }
+
+ # Initialise macros for search and replace, then determine if the map or
+ # remap section is to be processed
+ $Section{'remap'} = 0;
+ $Macro{'idw_remap'} = '';
+ $Macro{'idw_remap_v'} = '';
+ $Macro{'bin_remapstate'} = '';
+ $Macro{'remapping_vector'} = '';
+ $Macro{'region_type'} = '';
+ if ( $RemapInfo{$SlaveIF}{REMAP_WIDTH} > 0 ) {
+ $Section{'remap'} = 1;
+ $Macro{'idw_remap'} = $RemapInfo{$SlaveIF}{REMAP_WIDTH} - 1;
+ $Macro{'address_map'} = '';
+ $Macro{'mdelse'} = '';
+ $Macro{'mem_lo'} = '';
+ $Macro{'mem_hi'} = '';
+ $Macro{'remapping_vector'} = $RemapInfo{$SlaveIF}{REMAP_PORT};
+ }
+ $Section{'map'} = ( $Section{'remap'} ) ? 0 : 1;
+
+ }
+
+ $Macro{'remap_name'} = '';
+ $Macro{'top_remap_bit'} = '';
+ $Macro{'top_remap_bitvalue'} = '';
+
+ # For a sparse bus matrix only, and concerning the output_arb or output_stage
+ # only, set the current instance names for search and replacement. Also
+ # extract the master interface number for reference use
+ if ( $Sparse ) {
+ if ( $TemplateFile =~ /($Arbiters)$HdlExt$/ ) {
+ if ( ($MasterIF) = $RenderedFile =~ /$OutputArbName(\w+)$HdlExt$/ ) {
+ $Macro{'output_arb_name'} = $OutputArbName . $MasterIF;
+ $MasterIF = $NameAliases{$MasterIF} if ( $XmlConfigFile ne '' );
+ }
+ } elsif ( $TemplateFile =~ /cmsdk_ahb_bm(_single)?_output_stage$HdlExt$/ ) {
+ if ( ($MasterIF) = $RenderedFile =~ /$OutputStageName(\w+)$HdlExt$/ ) {
+ $Macro{'output_stage_name'} = $OutputStageName . $MasterIF;
+ $Macro{'output_stage_name_lc'} = lc($Macro{'output_stage_name'});
+ $MasterIF = $NameAliases{$MasterIF} if ( $XmlConfigFile ne '' );
+ $MasterIF =~ /([0-9]+)$/;
+ $Macro{'output_arb_name'} = $OutputArbNames[$1];
+ }
+ }
+ }
+
+ # Convert default slave name
+ $Macro{'default_slave_name'} = $DefaultSlave;
+
+ # Process each line of the template file
+ while ( $TextLine = <IN> ) {
+
+ # Increment the source file line number
+ $LineNum++;
+
+ # Display each line of the template when in debug mode
+ print "$LineNum:" . $TextLine if ( $Debug );
+
+ # Expand any macro found in the line
+ unless ( $TextLine !~ /<<[^<>]+>>/ ) {
+
+ # Search for all replaceable macros within the line
+ while ( ($Field, $Type) = $TextLine =~ /(<<(\w+)>>)/gc ) {
+ if ( exists $Macro{$Type} ) {
+ $TextLine =~ s/$Field/$Macro{$Type}/;
+ # Display replacement token name when in debug mode
+ print "Replaced '$Field' on line $LineNum of '$SourceFile' with '$Macro{$Type}'...\n" if ( $Debug );
+ } else {
+ warn "Warning: Unidentified field '$Field' on line $LineNum of '$SourceFile'...\n";
+ }
+ }
+
+ # Extract sections and store the current file pointer position
+ if ( ($StartName) = $TextLine =~ /<<\s+start\s+(.+)\s+>>/ ) {
+
+ # Store the information onto the section stack
+ $Section[++$Level] = {
+ LINE => $LineNum,
+ PTR => tell(IN),
+ NAME => $StartName,
+ COPIES => 0,
+ COUNT => 0,
+ EN => 1
+ };
+
+ # Display section start name when in debug mode
+ print "Found start section $Level '$StartName'\n" if ( $Debug );
+
+ # Exclude child sections if the parent section was excluded, otherwise
+ # conditionally process specificaly named sections of the template
+ if ( $Section[$Level - 1]{EN} == 0 ) {
+
+ $Section[$Level]{EN} = 0;
+
+ } elsif ( $StartName eq 'unalign' ) { # Optional section
+
+ $Section[$Level]{EN} = ( $Section{'unalign'} ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'excl' ) { # Optional section
+
+ $Section[$Level]{EN} = ( $Section{'excl'} ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'user' ) { # Optional section
+
+ $Section[$Level]{EN} = ( $Section{'user'} ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'map' ) { # Optional section
+
+ $Section[$Level]{EN} = ( $Section{'map'} ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'remap' ) { # Optional section
+
+ $Section[$Level]{EN} = ( $Section{'remap'} ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'vendor_extension' ) { # Optional section
+
+ # This is a dummy section to reset NoMoreIPXactInSections
+ $Section[$Level]{EN} = 0;
+
+ } elsif ( $StartName eq 'topfile' ) {
+
+ if ($TemplateFile =~ /.*lite_ipxact\.xml$/) { # Lite has the component/wrapper as top, the other has the AHB2 main top
+ $Section[$Level]{EN} = ( $Macro{'filename'} eq $ComponentName ) ? -1 : 0;
+ } else {
+ $Section[$Level]{EN} = ( $Macro{'filename'} eq $BusMatrixName ) ? -1 : 0;
+ }
+
+ } elsif ( $StartName eq 'connection' ) { # Optional section
+
+ # Determine template specific settings
+ if ( ($TemplateFile =~ /(cmsdk_ahb_busmatrix|$Arbiters|cmsdk_ahb_bm(_single)?_output_stage)$HdlExt$/) or
+ ($TemplateFile =~ /.*ipxact\.xml$/) ){
+ $SlaveIF = 'SI' . $Macro{'in'};
+ }
+ $Interface = ( $TemplateFile =~ /($Arbiters|cmsdk_ahb_bm(_single)?_output_stage)$HdlExt$/ ) ?
+ $MasterIF : 'MI' . $Macro{'out'};
+
+ # For sparse bus matrix only, check for at least one connection
+ $Section[$Level]{EN} = ( grep /^$Interface$/,
+ @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} } or !$Sparse ) ? -1 : 0;
+
+ # Indicate the first connection for the round_arb template
+ if ( $TemplateFile =~ /cmsdk_ahb_bm_round_arb$HdlExt$/ and $Section[$Level]{EN} ) {
+ $GotFirst = 1;
+ }
+
+ } elsif ( $StartName eq 'in' ) { # Common macro
+
+ # Set the number of times this section will be repeated
+ $Section[$Level]{COPIES} = $SlaveInterfaces - 1;
+ $Section[$Level]{EN} = -1;
+
+ # Set the current slave interface number and macros
+ $Macro{'in'} = $Section[$Level]{COUNT};
+ $Interface = 'SI' . $Section[$Level]{COUNT};
+ $Macro{'si_name'} = $InterfaceInfo{SLAVES}{$Interface}{NAME};
+ $SlaveIF = $Interface;
+
+ # Determine template specific settings
+ if ( $TemplateFile =~ /($Arbiters|cmsdk_ahb_bm(_single)?_output_stage)$HdlExt$/ ) {
+ $Macro{'bin_in'} = ToBinary($Section[$Level]{COUNT}, $IdWidthSI);
+ $Macro{'rrelse'} = ''; # Used in round_arb only
+ $GotFirst = 0;
+ } elsif ( $TemplateFile =~ /cmsdk_ahb_busmatrix$HdlExt$/ ) {
+ # Determine if the remap section should be processed
+ $Section{'remap'} = 0;
+ $Macro{'remapping_vector'} = '';
+ if ( $RemapInfo{$Interface}{REMAP_WIDTH} > 0 ) {
+ $Section{'remap'} = 1;
+ $Macro{'remapping_vector'} = $RemapInfo{$Interface}{REMAP_PORT};
+ }
+ $Macro{'matrix_decode_name'} = $MatrixDecodeNames[$Section[$Level]{COUNT}];
+ $Macro{'matrix_decode_name_lc'} = lc($Macro{'matrix_decode_name'});
+ }
+
+ } elsif ( $StartName eq 'out' ) { # Common macro
+
+ # Set the number of times this section will be repeated
+ $Section[$Level]{COPIES} = $MasterInterfaces - 1;
+ $Section[$Level]{EN} = -1;
+
+ # Set the current master interface number and macros
+ $Macro{'out'} = $Section[$Level]{COUNT};
+ $Interface = 'MI' . $Section[$Level]{COUNT};
+ $Macro{'mi_name'} = $InterfaceInfo{MASTERS}{$Interface}{NAME};
+ $Macro{'mi_name_lc'} = lc($Macro{'mi_name'});
+
+ # Determine template specific settings
+ if ( $TemplateFile =~ /cmsdk_ahb_bm_decode$HdlExt$/ ) {
+ $Macro{'bin_out'} = ToBinary($Section[$Level]{COUNT}, $IdWidthMI - 1);
+ } elsif ( $TemplateFile =~ /cmsdk_ahb_busmatrix$HdlExt$/ and $Sparse ) {
+ $Macro{'output_stage_name'} = $OutputStageNames[$Section[$Level]{COUNT}];
+ $Macro{'output_stage_name_lc'} = lc($Macro{'output_stage_name'});
+ }
+
+ } elsif ( $StartName eq 'rrin' ) { # Used in round_arb and output_stage
+
+ # Determine the port ID enumeration and the total number
+ if ( $Sparse ) {
+ @PortIds = @{ $InterfaceInfo{MASTERS}{$MasterIF}{CONNECTIONS} };
+ @PortIds = grep s/^SI//, @PortIds; # Remove all 'SI' prefixes
+ } else {
+ @PortIds = ( 0..$SlaveInterfaces-1 );
+ }
+ $TotalIds = scalar @PortIds;
+
+ # Set the number of times this section will be repeated, and determine
+ # the slave interface ID macros for the round_arb template
+ $Section[$Level]{COPIES} = $TotalIds - 1;
+ $Section[$Level]{EN} = -1;
+ $Macro{'rrin'} = $PortIds[$Section[$Level]{COUNT}];
+ $Macro{'bin_rrin'} = ToBinary($PortIds[$Section[$Level]{COUNT}], $IdWidthSI);
+
+ } elsif ( $StartName eq 'rridx' ) { # Used in round_arb only
+
+ # Set the number of times this section will be repeated, and determine
+ # the slave interface ID macros for the round_arb template
+ $Section[$Level]{COPIES} = $TotalIds - 2;
+ $Section[$Level]{EN} = -1;
+ $Macro{'rrelse'} = '';
+ $RefId = ($Section[$Level - 1]{COUNT} + 1) % $TotalIds;
+ $Macro{'rridx'} = $PortIds[$RefId];
+ $Macro{'bin_rridx'} = ToBinary($PortIds[$RefId], $IdWidthSI);
+
+ } elsif ( $StartName eq 'addr_map' ) { # Used in bm_decode only
+
+ # For the current remapping state and master interface, determine which
+ # address regions are visible
+ @MIRegions = grep /^$Interface:/,
+ @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} };
+
+ if ( $RemapState > 0 ) { # Only when remapping is asserted non-zero
+
+ # Translate the active remapping bits into a regexp filter
+ @ActiveRemap = ();
+ for ($Bit = 0; $Bit < $RemapInfo{$SlaveIF}{REMAP_WIDTH}; $Bit++) {
+ if ( ($RemapState >> $Bit) & 0x01 ) {
+ push @ActiveRemap, @{ $RemapInfo{$SlaveIF}{REMAP_BITS} }[$Bit];
+ }
+ }
+ $RemapBit = join( '|', @ActiveRemap );
+
+ # Determine if there are activated remap regions, and if so, delete
+ # normal but movable address map regions
+ if ( grep /^$Interface:remap($RemapBit):/,
+ @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} } ) {
+ @MIRegions = grep !/^.*:move:/,
+ @MIRegions;
+
+ }
+
+ }
+ $Region = 0;
+
+ # Initialise macros in preparation for search and replace
+ $Macro{'mdelse'} = '';
+ $Macro{'address_map'} = '';
+ $Macro{'mem_lo'} = '';
+ $Macro{'mem_hi'} = '';
+
+ # Include this section if a mapping exists
+ $Section[$Level]{EN} = ( @MIRegions > 0 ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'addr_map_ipxact' ) {
+
+ # All normal (non-remap) regions
+ @MIRegions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} };
+
+ # Initialise macros in preparation for search and replace
+ $Macro{'address_map'} = '';
+ $Macro{'mem_lo'} = '';
+ $Macro{'mem_hi'} = '';
+
+ # Include this section if a mapping exists
+ $Section[$Level]{EN} = ( @MIRegions > 0 ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'segments' ) {
+
+ $Section[$Level]{COPIES} = scalar @{$AddressSpace{$Interface}} - 1;
+ $Section[$Level]{EN} = -1;
+
+ $Macro{'segment_name'} = '0x'.$AddressSpace{$Interface}[$Section[$Level]{COUNT}][0]."_".'0x'.$AddressSpace{$Interface}[$Section[$Level]{COUNT}][1];
+ $Macro{'segment_offset'} = '0x'.$AddressSpace{$Interface}[$Section[$Level]{COUNT}][0];
+ $Macro{'segment_range'} = '0x' . HexAdd( '0'. HexSubstract($AddressSpace{$Interface}[$Section[$Level]{COUNT}][1],
+ $AddressSpace{$Interface}[$Section[$Level]{COUNT}][0]) , 1 );
+
+ } elsif ( $StartName eq 'addr_remap_and_normal_all_this_remap' ) {
+
+ @MIRegions = ();
+
+ # All remap regions
+ my @allRegions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} };
+ push (@allRegions, @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} });
+ foreach my $address_region ( @allRegions ) {
+
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi, $Unmapping) = split(/:/,$address_region);
+
+ # get canonical name for remap state
+ my @bits = GetRemapBits ($Remapping, $Unmapping);
+ my $i_remap_name = join( '_' , @bits );
+ # Change ! to n
+ $i_remap_name =~ s/!/n/g ;
+
+ if ($Macro{'remap_name'} eq "remap_".$i_remap_name) {
+ push (@MIRegions,$address_region);
+ }
+ }
+
+ # Initialise macros in preparation for search and replace
+ $Macro{'address_map'} = '';
+ $Macro{'mem_lo'} = '';
+ $Macro{'mem_hi'} = '';
+
+ # Include this section if a mapping exists
+ $Section[$Level]{EN} = ( @MIRegions > 0 ) ? -1 : 0;
+
+ } elsif ( $StartName =~ /^(addr|remap)_region$/ ) { # Used bm_decode and Spirit file only
+ # Do not add an else if it is the first address/remap region
+ $Macro{'mdelse'} = ( $Decodings > 0 ) ? 'else ' : '';
+
+ # Conditionally reference the first address/remap region and extract its info
+ if ( @MIRegions > 0 ) {
+ # Set the number of copies
+ $Section[$Level]{COPIES} = scalar @MIRegions - 1;
+
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $MIRegions[$Region]);
+ $Macro{'address_block_name'} = 'Default';
+ $Macro{'address_block_remap'} = ($Remapping eq "move") ? 'TRUE' : 'FALSE';
+ $Macro{'base_address'} = "0x$AddrLo";
+ $Macro{'address_range'} = '0x' . HexSubstract($AddrHi, $AddrLo);
+ $Macro{'address_map'} = "0x$AddrLo-0x$AddrHi";
+ $Macro{'mem_lo'} = ToDecodeAddr($AddrLo);
+ $Macro{'mem_hi'} = ToDecodeAddr($AddrHi);
+
+ # Determine template specific settings
+ if ( $TemplateFile =~ /cmsdk_ahb_bm_decode$HdlExt$/ ) {
+ $Macro{'remapping_bit'} = '';
+ if ( $StartName eq 'remap_region' ) {
+ $Macro{'remapping_bit'} = substr($Remapping, 5, 1);
+ $Macro{'out'} = substr($MasterIF, 2);
+ $Macro{'bin_out'} = ToBinary( substr($MasterIF, 2), $IdWidthMI - 1);
+ } else {
+ $Macro{'region_type'} = $RemapTypes{$Remapping};
+ }
+ }
+ $Decodings++;
+ }
+ $Section[$Level]{EN} = -1;
+
+ } elsif ( $StartName =~ /^(addr|remap)_region_ipxact$/ ) { # Used bm_decode and IPXACT file only
+
+ # Conditionally reference the first address/remap region and extract its info
+ if ( @MIRegions > 0 ) {
+
+ # Set the number of copies
+ $Section[$Level]{COPIES} = scalar @MIRegions - 1;
+ $Section[$Level]{EN} = -1;
+
+
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi, $Unmapping) = split(/:/, $MIRegions[$Section[$Level]{COUNT}]);
+ $Macro{'address_block_name'} = 'Default';
+ $Macro{'address_block_remap'} = ($Remapping eq "move") ? 'TRUE' : 'FALSE';
+ $Macro{'base_address'} = "0x$AddrLo";
+ $Macro{'end_address'} = "0x$AddrHi";
+ $Macro{'address_range'} = '0x' . HexSubstract($AddrHi, HexSubstract($AddrLo,1));
+ $Macro{'address_map'} = "0x$AddrLo-0x$AddrHi";
+ $Macro{'mem_lo'} = ToDecodeAddr($AddrLo);
+ $Macro{'mem_hi'} = ToDecodeAddr($AddrHi);
+ $Macro{'out'} = substr($MasterIF, 2);
+ $Macro{'bin_out'} = ToBinary( substr($MasterIF, 2), $IdWidthMI - 1);
+ $Macro{'mi_name'} = $InterfaceInfo{MASTERS}{$MasterIF}{NAME};
+ $Macro{'mi_name_lc'} = lc($Macro{'mi_name'});
+
+ my @bits = GetRemapBits ($Remapping, $Unmapping);
+
+ my $remap_name = join( '_' , @bits );
+ # Change ! to n
+ $remap_name =~ s/!/n/g ;
+ $Macro{'remap_name'} = "remap_".$remap_name;
+
+ my $bit;
+ $Macro{'active_cond'} = '';
+
+ foreach $bit (@bits) {
+ if (substr($bit,0,1) eq '!') {
+ $Macro{'active_cond'} .= "\n" . ' 'x25 . ' & !remapping_dec['.$RemapInfo{$SlaveIF}{REMAP_MAPPING}{substr($bit,1)} .']';
+ } else {
+ $Macro{'active_cond'} .= "\n" . ' 'x25 . ' & remapping_dec['.$RemapInfo{$SlaveIF}{REMAP_MAPPING}{$bit} .']';
+ }
+ }
+ $Macro{'remapping_bit'} = $remap_name;
+
+ $Section{'remap_static'} = @bits ? 0 : 1;
+ $Section{'remap_conditional'} = @bits ? 1 : 0;
+
+ if (@bits) {
+ if ( substr($Remapping,0,5) eq 'remap' ) {
+ $Macro{'region_type'} = "Remapped region, active when REMAP bitcombination is " . $remap_name;
+ $Macro{'region_type_sanitized'} = "Remapped_" . $remap_name;
+ } else {
+ $Macro{'region_type'} = "Removable region, active only when REMAP bitcombination is " . $remap_name;
+ $Macro{'region_type_sanitized'} = "Removable_" . $remap_name;
+ }
+ } else {
+ $Macro{'region_type'} = "Static";
+ $Macro{'region_type_sanitized'} = $Macro{'region_type'};
+ }
+
+ }
+
+ } elsif ( $StartName eq 'ipxact_remap_region' ) { # Used in IPXact file only
+
+ # Get the remap regions for the current master interface
+ @MIRegions = grep /^$MasterIF:/,
+ @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} };
+
+ if ( @MIRegions > 0 ) {
+ $Section[$Level]{COPIES} = scalar @MIRegions - 1;
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $MIRegions[$Region]);
+ $Remapping =~ /([0-9])$/; $Remapping = $1;
+ $Macro{'address_block_name'} = 'Remap-Pin' . $Remapping;
+ $Macro{'base_address'} = "0x$AddrLo";
+ $Macro{'address_range'} = '0x' . HexSubstract($AddrHi, $AddrLo);
+ $Macro{'mem_lo'} = ToDecodeAddr($AddrLo);
+ $Macro{'mem_hi'} = ToDecodeAddr($AddrHi);
+ }
+ $Section[$Level]{EN} = ( $Macro{'base_address'} eq '' ) ? 0 : -1;
+
+ } elsif ( $StartName eq 'remap_state' ) { # Used in bm_decode only
+
+ # Initialise macros in preparation for search and replace
+ $Macro{'address_map'} = '';
+ $Macro{'mem_lo'} = '';
+ $Macro{'mem_hi'} = '';
+ $Macro{'remapping_bit'} = '';
+ $Macro{'idw_remap_v'} = $RemapInfo{$SlaveIF}{REMAP_WIDTH};
+ $Macro{'bin_remapstate'} = ToBinary(0, $RemapInfo{$SlaveIF}{REMAP_WIDTH});
+
+ # Initialise variables used in remap processing and calculate the required
+ # number of section copies
+ $RemapState = 0;
+ $Decodings = 0;
+ $Section[$Level]{COPIES} = (2 ** $RemapInfo{$SlaveIF}{REMAP_WIDTH}) - 1;
+ $Section[$Level]{EN} = -1;
+
+ } elsif ( $StartName eq 'remap_state_ipxact' ) { # Used in ipxact only
+
+ @i_remapstate = keys( %RemapStates );
+ #$Macro{'remapping_bit'} = '';
+ #$Macro{'idw_remap_v'} = $RemapInfo{$SlaveIF}{REMAP_WIDTH};
+
+ # Initialise variables used in remap processing and calculate the required
+ # number of section copies
+
+ $Section[$Level]{COPIES} = scalar @i_remapstate -1;
+ $Section[$Level]{EN} = ($Section{'remap_used'} > 0) ? -1 : 0;
+
+ $RemapState = $Section[$Level]{COUNT};
+
+ $Macro{'remap_name'} = $i_remapstate[$RemapState];
+ print "Processing remap state: $Macro{'remap_name'}\n" if ( $Debug );
+
+ } elsif ( $StartName eq 'remap_bit' ) { # Used in bm_decode only
+
+ # Set the number of copies
+ $Section[$Level]{COPIES} = $RemapInfo{$SlaveIF}{REMAP_WIDTH} - 1;
+ $Section[$Level]{EN} = -1;
+ $Bit = 0;
+
+ } elsif ( $StartName eq 'remap_bit_ipxact' ) { # Used in bm_decode only
+
+ # Set the number of copies
+ $Section[$Level]{COPIES} = scalar @{$RemapStates{$i_remapstate[$RemapState]}} -1;
+ $Section[$Level]{EN} = -1;
+ $Bit = 0;
+
+ my $r_bit = @{$RemapStates{$i_remapstate[$RemapState]}}[$Section[$Level]{COUNT}];
+
+ if (substr($r_bit,0,1) eq '!') {
+ $Macro{'top_remap_bit'} = substr($r_bit,1);
+ $Macro{'top_remap_bitvalue'} = 0;
+ } else {
+ $Macro{'top_remap_bit'} = $r_bit;
+ $Macro{'top_remap_bitvalue'} = 1;
+ }
+
+ } elsif ( $StartName eq 'addr_remap' ) { # Used in bm_decode only
+
+ # For the current remapping state, determine which remap regions are
+ # active per master interface
+ @MIRegions = ();
+ $Region = 0;
+ if ( ($RemapState >> $Bit) & 0x01 ) {
+ $RemapBit = @{ $RemapInfo{$SlaveIF}{REMAP_BITS} }[$Bit];
+ @MIRegions = grep /:remap$RemapBit:/,
+ @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} };
+ }
+
+ # Initialise macros in preparation for search and replace
+ $Macro{'mdelse'} = '';
+ $Macro{'address_map'} = '';
+ $Macro{'mem_lo'} = '';
+ $Macro{'mem_hi'} = '';
+
+ # Include this section if a mapping exists
+ $Section[$Level]{EN} = ( @MIRegions > 0 ) ? -1 : 0;
+
+ } elsif ( $StartName eq 'file' ) { # Used in ipxact file only
+
+ $Macro{'filename'} = $IPXactFiles[0];
+ $Section[$Level]{COPIES} = scalar @IPXactFiles - 1;
+ $Section[$Level]{EN} = -1;
+
+ if ($TemplateFile =~ /.*lite_ipxact\.xml$/) {# Remove the wrapper from non-lite
+ #
+ } else {
+ # Don't include the lite wrapper in the AHB2 ipxact
+ if ( $Macro{'filename'} eq $ComponentName ) {
+ $Macro{'filename'} = $IPXactFiles[1];
+ ++$Section[$Level]{COUNT};
+ }
+ }
+
+ } elsif ( exists $Section{$StartName} ) { # Optional section
+
+ $Section[$Level]{EN} = ( $Section{$StartName} ) ? -1 : 0;
+
+
+ }
+
+ # Display the number of section copies when in debug mode
+ print "Section copies: $Section[$Level]{COPIES}\n" if ( $Debug );
+
+ } elsif ( ($EndName) = $TextLine =~ /<<\s+end\s+(.+)\s+>>/ ) {
+
+ # Display section end name when in debug mode
+ print "Found end section $Level '$EndName'\n" if ( $Debug );
+
+ # Check for matching section markers
+ unless ( $EndName eq $Section[$Level]{NAME} ) {
+ die "Error: Unexpected section end on line $LineNum of '$SourceFile'...\n\n";
+ }
+
+ # Determine if the section is to be repeated
+ if ( $Section[$Level]{COUNT} < $Section[$Level]{COPIES} ) {
+
+ # Adjust input file pointer and line number
+ seek( IN, $Section[$Level]{PTR}, 0 );
+ $LineNum = $Section[$Level]{LINE};
+
+ # Update macro settings as necessary
+ if ( $EndName eq 'in' ) {
+
+ $Macro{'in'} = ++$Section[$Level]{COUNT};
+ $Interface = 'SI' . $Section[$Level]{COUNT};
+ $Macro{'si_name'} = $InterfaceInfo{SLAVES}{$Interface}{NAME};
+ $SlaveIF = $Interface;
+
+ # Determine template specific settings
+ if ( $TemplateFile =~ /($Arbiters|cmsdk_ahb_bm(_single)?_output_stage)$HdlExt$/ ) {
+ $Macro{'bin_in'} = ToBinary($Section[$Level]{COUNT}, $IdWidthSI);
+ if ( $GotFirst ) { $Macro{'rrelse'} = 'else '; }
+ } elsif ( $TemplateFile =~ /cmsdk_ahb_busmatrix$HdlExt$/ ) {
+ # Determine if the remap section should be processed
+ $Section{'remap'} = 0;
+ $Macro{'remapping_vector'} = '';
+ if ( $RemapInfo{$Interface}{REMAP_WIDTH} > 0 ) {
+ $Section{'remap'} = 1;
+ $Macro{'remapping_vector'} = $RemapInfo{$Interface}{REMAP_PORT};
+ }
+ $Macro{'matrix_decode_name'} = $MatrixDecodeNames[$Section[$Level]{COUNT}];
+ $Macro{'matrix_decode_name_lc'} = lc($Macro{'matrix_decode_name'});
+ }
+
+ } elsif ( $EndName eq 'out' ) {
+
+ $Macro{'out'} = ++$Section[$Level]{COUNT};
+ $Interface = 'MI' . $Section[$Level]{COUNT};
+ $Macro{'mi_name'} = $InterfaceInfo{MASTERS}{$Interface}{NAME};
+ $Macro{'mi_name_lc'} = lc($Macro{'mi_name'});
+
+ # Determine template specific settings
+ if ( $TemplateFile =~ /cmsdk_ahb_bm_decode$HdlExt$/ ) {
+ $Macro{'bin_out'} = ToBinary($Section[$Level]{COUNT}, $IdWidthMI - 1);
+ } elsif ( $TemplateFile =~ /cmsdk_ahb_busmatrix$HdlExt$/ and $Sparse ) {
+ $Macro{'output_stage_name'} = $OutputStageNames[$Section[$Level]{COUNT}];
+ $Macro{'output_stage_name_lc'} = lc($Macro{'output_stage_name'});
+ }
+
+ } elsif ( $EndName eq 'rrin' ) {
+
+ $Macro{'rrin'} = $PortIds[ ++$Section[$Level]{COUNT} ];
+ $Macro{'bin_rrin'} = ToBinary($PortIds[$Section[$Level]{COUNT}], $IdWidthSI);
+
+ } elsif ( $EndName eq 'rridx' ) {
+
+ $Section[$Level]{COUNT}++;
+ $Macro{'rrelse'} = 'else ';
+
+ # Determine next round robin port
+ $RefId = ++$RefId % $TotalIds;
+ $Macro{'rridx'} = $PortIds[$RefId];
+ $Macro{'bin_rridx'} = ToBinary($PortIds[$RefId], $IdWidthSI);
+
+ } elsif ( $EndName eq 'remap_state' ) {
+
+ $Macro{'bin_remapstate'} = ToBinary(++$Section[$Level]{COUNT},
+ $RemapInfo{$SlaveIF}{REMAP_WIDTH});
+ $Decodings = 0;
+ $RemapState++;
+
+ } elsif ( $EndName eq 'remap_state_ipxact' ) {
+
+ $Section[$Level]{COUNT}++;
+
+ $RemapState = $Section[$Level]{COUNT};
+
+ $Macro{'remap_name'} = $i_remapstate[$RemapState];
+ print "Processing remap state: $Macro{'remap_name'}\n" if ( $Debug );
+
+ } elsif ( $EndName eq 'remap_bit' ) {
+
+ $Section[$Level]{COUNT}++;
+ $Bit++;
+
+ } elsif ( $EndName eq 'remap_bit_ipxact' ) {
+
+ $Bit++;
+
+ $Section[$Level]{COUNT}++;
+
+ my $r_bit = @{$RemapStates{$i_remapstate[$RemapState]}}[$Section[$Level]{COUNT}];
+
+ if (substr($r_bit,0,1) eq '!') {
+ $Macro{'top_remap_bit'} = substr($r_bit,1);
+ $Macro{'top_remap_bitvalue'} = 0;
+ } else {
+ $Macro{'top_remap_bit'} = $r_bit;
+ $Macro{'top_remap_bitvalue'} = 1;
+ }
+
+ } elsif ( $EndName eq 'segments' ) {
+
+ $Section[$Level]{COUNT}++;
+
+ $Macro{'segment_name'} = '0x'.$AddressSpace{$Interface}[$Section[$Level]{COUNT}][0]."_".'0x'.$AddressSpace{$Interface}[$Section[$Level]{COUNT}][1];
+ $Macro{'segment_offset'} = '0x'.$AddressSpace{$Interface}[$Section[$Level]{COUNT}][0];
+ $Macro{'segment_range'} = '0x' . HexAdd( '0'. HexSubstract($AddressSpace{$Interface}[$Section[$Level]{COUNT}][1],
+ $AddressSpace{$Interface}[$Section[$Level]{COUNT}][0]) , 1 );
+
+ } elsif ( $EndName eq 'addr_remap_and_normal_all_this_remap' ) {
+
+ # Empty
+
+ } elsif ( $EndName =~ /^(addr|remap)_region$/ ) {
+
+ $Section[$Level]{COUNT}++;
+
+ # Conditionally reference the subsequent address/remap region
+ if ( @MIRegions > 0 ) {
+ $Macro{'mdelse'} = ( $Decodings > 0 ) ? 'else ' : '';
+
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $MIRegions[++$Region]);
+ $Macro{'address_block_name'} = 'Default';
+ $Macro{'address_block_remap'} = ($Remapping eq "move") ? 'TRUE' : 'FALSE';
+ $Macro{'base_address'} = "0x$AddrLo";
+ $Macro{'address_range'} = '0x' . HexSubstract($AddrHi, $AddrLo);
+ $Macro{'address_map'} = "0x$AddrLo-0x$AddrHi";
+ $Macro{'mem_lo'} = ToDecodeAddr($AddrLo);
+ $Macro{'mem_hi'} = ToDecodeAddr($AddrHi);
+
+ # Determine template specific settings
+ if ( $TemplateFile =~ /cmsdk_ahb_bm_decode$HdlExt$/ ) {
+ $Macro{'remapping_bit'} = '';
+ if ( $EndName eq 'remap_region' ) {
+ $Macro{'remapping_bit'} = substr($Remapping, 5, 1);
+ $Macro{'out'} = substr($MasterIF, 2);
+ $Macro{'bin_out'} = ToBinary( substr($MasterIF, 2), $IdWidthMI - 1);
+ } else {
+ $Macro{'region_type'} = $RemapTypes{$Remapping};
+ }
+ }
+ $Decodings++;
+ }
+
+ } elsif ( $EndName =~ /^(addr|remap)_region_ipxact$/ ) { # Used bm_decode and IPXACT file only
+
+ $Section[$Level]{COUNT}++;
+
+ # Conditionally reference the first address/remap region and extract its info
+ if ( @MIRegions > 0 ) {
+
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi, $Unmapping) = split(/:/, $MIRegions[$Section[$Level]{COUNT}]);
+ $Macro{'address_block_name'} = 'Default';
+ $Macro{'address_block_remap'} = ($Remapping eq "move") ? 'TRUE' : 'FALSE';
+ $Macro{'base_address'} = "0x$AddrLo";
+ $Macro{'end_address'} = "0x$AddrHi";
+ $Macro{'address_range'} = '0x' . HexSubstract($AddrHi, HexSubstract($AddrLo,1));
+ $Macro{'address_map'} = "0x$AddrLo-0x$AddrHi";
+ $Macro{'mem_lo'} = ToDecodeAddr($AddrLo);
+ $Macro{'mem_hi'} = ToDecodeAddr($AddrHi);
+ $Macro{'out'} = substr($MasterIF, 2);
+ $Macro{'bin_out'} = ToBinary( substr($MasterIF, 2), $IdWidthMI - 1);
+ $Macro{'mi_name'} = $InterfaceInfo{MASTERS}{$MasterIF}{NAME};
+ $Macro{'mi_name_lc'} = lc($Macro{'mi_name'});
+
+ $Section{'remapped'} = ($Remapping =~ /^(move|remap).*/) ? 1 : 0;
+ $Section{'not_remapped'} = !$Section{'remapped'};
+
+ my @bits = GetRemapBits ($Remapping, $Unmapping);
+
+ my $remap_name = join( '_' , @bits );
+ # Change ! to n
+ $remap_name =~ s/!/n/g ;
+ $Macro{'remap_name'} = "remap_".$remap_name;
+
+ my $bit;
+ $Macro{'active_cond'} = '';
+
+ foreach $bit (@bits) {
+ if (substr($bit,0,1) eq '!') {
+ $Macro{'active_cond'} .= "\n" . ' 'x25 . ' & !remapping_dec['.$RemapInfo{$SlaveIF}{REMAP_MAPPING}{substr($bit,1)} .']';
+ } else {
+ $Macro{'active_cond'} .= "\n" . ' 'x25 . ' & remapping_dec['.$RemapInfo{$SlaveIF}{REMAP_MAPPING}{$bit} .']';
+ }
+ }
+ $Macro{'remapping_bit'} = $remap_name;
+
+ $Section{'remap_static'} = @bits ? 0 : 1;
+ $Section{'remap_conditional'} = @bits ? 1 : 0;
+
+ if (@bits) {
+ if ( substr($Remapping,0,5) eq 'remap' ) {
+ $Macro{'region_type'} = "Remapped region, active when REMAP bitcombination is " . $remap_name;
+ $Macro{'region_type_sanitized'} = "Remapped_" . $remap_name;
+ } else {
+ $Macro{'region_type'} = "Removable region, active only when REMAP bitcombination is " . $remap_name;
+ $Macro{'region_type_sanitized'} = "Removable_" . $remap_name;
+ }
+ } else {
+ $Macro{'region_type'} = "Static";
+ $Macro{'region_type_sanitized'} = $Macro{'region_type'};
+ }
+
+ }
+
+ } elsif ( $EndName eq 'ipxact_remap_region' ) {
+
+ $Section[$Level]{COUNT}++;
+
+ if ( @MIRegions > 0 ) {
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $MIRegions[++$Region]);
+ $Remapping =~ /([0-9])$/; $Remapping = $1;
+ $Macro{'address_block_name'} = 'Remap-Pin' . $Remapping;
+ $Macro{'base_address'} = "0x$AddrLo";
+ $Macro{'address_range'} = '0x' . HexSubstract($AddrHi, $AddrLo);
+ $Macro{'mem_lo'} = ToDecodeAddr($AddrLo);
+ $Macro{'mem_hi'} = ToDecodeAddr($AddrHi);
+ }
+
+ } elsif ( $EndName eq 'file' ) { # Used in ipxact file only
+
+
+ if ($TemplateFile =~ /.*lite_ipxact\.xml$/) { # Remove the wrapper from non-lite
+ #
+ } else {
+ if ( $Macro{'filename'} eq $ComponentName ) {
+ ++$Section[$Level]{COUNT};
+ }
+ }
+
+ $Macro{'filename'} = $IPXactFiles[++$Section[$Level]{COUNT}];
+
+ }
+
+ # Display pointer adjustment when in debug mode
+ printf ("Reversing back to line %d...\n", $LineNum + 1) if ( $Debug );
+
+ } elsif ( $Level > 0 ) {
+ $Level--;
+ }
+
+ # Do not include this line in the output
+ unless ($Section[$Level]{EN} == 0) { $Section[$Level]{EN} = -1; }
+
+ }
+
+ }
+
+ # Write the line(s) to the rendered output file when (delay) enabled
+ if ( $Section[$Level]{EN} ) {
+ print OUT $TextLine if ( $Section[$Level]{EN} > 0 );
+ $Section[$Level]{EN} = 1;
+ }
+
+ }
+
+ # Close the template file and rendered output file
+ close(IN);
+ close(OUT);
+
+ # If still inside a nested section, there were too few end macros
+ unless ( $Level == 0 ) {
+ die "Error: Section '$Section[$Level]{NAME}' expected in '$SourceFile'!\n\n";
+ }
+
+}
+
+
+# ------------------------------------------------------------------------------
+# IsSparse - Determines the connectivity completeness
+# ------------------------------------------------------------------------------
+sub IsSparse {
+
+ # Local variable(s)
+ my $SlaveIF = '';
+ my @SlaveIFs = keys( %{ $InterfaceInfo{SLAVES} } );
+ my @MasterIFs = keys( %{ $InterfaceInfo{MASTERS} } );
+ my $Mappings = '';
+ my $Result = 0;
+
+ # Check each mapping
+ foreach $SlaveIF ( @SlaveIFs ) {
+ $Mappings = join( '|', @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} } );
+ if ( grep $_ !~ /^($Mappings)$/, @MasterIFs ) { $Result = 1; last; }
+ }
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# HexSubstract - Does argument1 - argument2 substraction in hex.
+# Assumes argument1 >= argument2
+# ------------------------------------------------------------------------------
+sub HexSubstract {
+
+ # Passed parameter 1 is the LHS hexadecimal operand value
+ my $Value1 = shift;
+ # Passed parameter 2 is the RHS hexadecimal operand value
+ my $Value2 = shift;
+
+ # Local variable(s)
+ my $Len1 = length($Value1);
+ my $Len2 = length($Value2);
+ my $Index = 0;
+ my $Char1 = '';
+ my $Char2 = '';
+ my $Borrow = 0;
+ my $Result = '';
+
+ # Append zeros to the 2nd operand
+ if ( $Len1 > $Len2 ) { $Value2 = '0' x ($Len1 - $Len2) . $Value2; }
+
+ # Substract using strings instead of conversion to decimal to support 64 bit numbers
+ for ( $Index = 1; $Index <= $Len1; $Index++ ) {
+ $Char1 = hex substr($Value1, $Len1 - $Index, 1);
+ $Char2 = hex substr($Value2, $Len1 - $Index, 1);
+ if ( $Char1 < ($Char2 + $Borrow) ) {
+ $Char1 = $Char1 + 16;
+ $Result = sprintf("%1x", $Char1 - $Char2 - $Borrow) . $Result;
+ $Borrow = 1;
+ } else {
+ $Result = sprintf("%1x", $Char1 - $Char2 - $Borrow) . $Result;
+ $Borrow = 0;
+ }
+ }
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# HexAdd - Does argument1 + argument2 substraction in hex.
+# ------------------------------------------------------------------------------
+sub HexAdd {
+
+ # Passed parameter 1 is the LHS hexadecimal operand value
+ my $Value1 = shift;
+ # Passed parameter 2 is the RHS hexadecimal operand value
+ my $Value2 = shift;
+
+ # Local variable(s)
+ my $Len1 = length($Value1);
+ my $Len2 = length($Value2);
+ my $Index = 0;
+ my $Char1 = '';
+ my $Char2 = '';
+ my $Carry = 0;
+ my $Result = '';
+
+ # Append zeros to the 2nd operand
+ if ( $Len1 > $Len2 ) { $Value2 = '0' x ($Len1 - $Len2) . $Value2; }
+
+ # Substract using strings instead of conversion to decimal to support 64 bit numbers
+ for ( $Index = 1; $Index <= $Len1; $Index++ ) {
+ $Char1 = hex substr($Value1, $Len1 - $Index, 1);
+ $Char2 = hex substr($Value2, $Len1 - $Index, 1);
+ if ( $Char1 +$Char2 + $Carry > 15) {
+ $Result = sprintf("%1x", $Char1 + $Char2 + $Carry - 16) . $Result;
+ $Carry = 1;
+ } else {
+ $Result = sprintf("%1x", $Char1 + $Char2 + $Carry) . $Result;
+ $Carry = 0;
+ }
+ }
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# RoundPowerOfTwo - Finds the minimum binary quantum for the specified
+# integer value
+# ------------------------------------------------------------------------------
+sub RoundPowerOfTwo {
+
+ # Passed parameter 1 is the integer value
+ my $Value = shift;
+
+ # Local variable(s)
+ my $Result = 0;
+ my $ShiftCount = 0;
+
+ # Determine the number of available regions
+ while ( $Value > $Result ) { $Result = 1 << $ShiftCount++; }
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# NumberOfDigits - Calculates the number of digits required to describe
+# the specified integer value in the specified base
+# ------------------------------------------------------------------------------
+sub NumberOfDigits {
+
+ # Passed parameter 1 is the integer value
+ my $Value = shift;
+ # Passed parameter 2 is the base
+ my $Base = shift;
+
+ # Local variable(s)
+ my $Result = 1;
+ my $XToTheY = 0;
+
+ # Determine the number of digits for values greater than the radix
+ unless ( $Base < 2 or $Value < $Base ) {
+ while ( $Value > $XToTheY ) { $XToTheY = $Base ** $Result++; }
+ if ( $Value != $XToTheY ) { $Result--; }
+ }
+
+ return ( $Result );
+}
+
+
+# ------------------------------------------------------------------------------
+# NumberOfHexChars - Calculates the number of hexadecimal characters
+# required to describe the specified number of bits
+# ------------------------------------------------------------------------------
+sub NumberOfHexChars {
+
+ # Passed parameter 1 is the integer value
+ my $Value = shift;
+
+ # Local variable(s)
+ my $Result = $Value / 4.0;
+ my $Integer = int($Result);
+ my $Fraction = $Result - $Integer;
+
+ # Determine the number of digits
+ $Result = ($Fraction > 0) ? $Integer + 1 : $Integer;
+
+ return ( $Result );
+}
+
+
+# ------------------------------------------------------------------------------
+# ToBinary - Converts the specified integer into an n-bit binary string
+# ------------------------------------------------------------------------------
+sub ToBinary {
+
+ # Passed parameter 1 is the integer value
+ my $Value = shift;
+ # Passed parameter 2 is the binary string length
+ my $Length = shift;
+
+ # Local variable(s)
+ my $Format = "%0${Length}b";
+ my $Result = ( $Value =~ /^\d+$/ ) ? sprintf($Format, $Value) : '';
+
+ return ( substr($Result, -$Length, $Length) );
+}
+
+
+# ------------------------------------------------------------------------------
+# ToDecodeAddr - Shifts the specified n-bit address to the correct alignment
+# for the Matrix Decoder because HADDR[9:0] is not decoded
+# ------------------------------------------------------------------------------
+sub ToDecodeAddr {
+
+ # Passed parameter 1 is the address value
+ my $FullAddr = shift;
+
+ # Local variable(s)
+ my $AddrBits = $RoutingAddressWidth - 10;
+ my $HexChars = NumberOfHexChars($AddrBits);
+ my $Length = length($FullAddr);
+ my $BinAddr = sprintf( "%032b%032b", hex substr($FullAddr, 0, $Length - 8),
+ hex substr($FullAddr, $Length - 8) );
+ my $Result = '';
+
+ # Right-shift the binary string to remove the non-decoded bits, and repack
+ # it into 32-bit chunks for reformatting into a hexadecimal representation
+ $BinAddr = '0' x 10 . substr($BinAddr, 0, -10);
+ $Result = sprintf( "%08lx%08lx",
+ unpack( 'N', pack('B32', substr($BinAddr, 0, 32)) ),
+ unpack( 'N', pack('B32', substr($BinAddr, 32)) ) );
+
+ return ( sprintf("%d'h%s", $AddrBits, substr($Result, 16 - $HexChars)) );
+}
+
+
+# ------------------------------------------------------------------------------
+# UnsignedFloatToHex - Converts the specified float value into a hex string
+# ------------------------------------------------------------------------------
+sub UnsignedFloatToHex {
+
+ # Passed parameter 1 is the float value
+ my $Value = shift;
+
+ # Local variable(s)
+ my $HexDigits = NumberOfDigits($Value, 16);
+ my $Divisor = 16 ** ($HexDigits - 1);
+ my $Dividend = 0;
+ my $Result = '';
+
+ # Determine number sequence
+ while ( length($Result) < $HexDigits ) {
+ $Dividend = int( $Value / $Divisor );
+ if ( $Dividend > 0 ) {
+ $Result = $Result . substr('0123456789abcdef', $Dividend, 1);
+ $Value -= ($Divisor * $Dividend);
+ } else {
+ $Result = $Result . '0';
+ }
+ $Divisor /= 16;
+ }
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# IsGtOrEq - Operator '>=' test for up to 64-bit hexadecimal numbers
+# ------------------------------------------------------------------------------
+sub IsGtOrEq {
+
+ # Passed parameter 1 is the LHS value
+ my $OperandLHS = shift;
+ # Passed parameter 2 is the RHS value
+ my $OperandRHS = shift;
+
+ # Local variable(s)
+ my $LengthLHS = length($OperandLHS);
+ my @LHS = ( hex substr($OperandLHS, 0, $LengthLHS - 8),
+ hex substr($OperandLHS, $LengthLHS - 8) );
+ my $LengthRHS = length($OperandRHS);
+ my @RHS = ( hex substr($OperandRHS, 0, $LengthRHS - 8),
+ hex substr($OperandRHS, $LengthRHS - 8) );
+ my $Result = ( $LHS[0] > $RHS[0] or
+ ($LHS[0] == $RHS[0] and $LHS[1] >= $RHS[1]) ) ? 1 : 0;
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# IsLtOrEq - Operator '<=' test for up to 64-bit hexadecimal numbers
+# ------------------------------------------------------------------------------
+sub IsLtOrEq {
+
+ # Passed parameter 1 is the LHS value
+ my $OperandLHS = shift;
+ # Passed parameter 2 is the RHS value
+ my $OperandRHS = shift;
+
+ # Local variable(s)
+ my $LengthLHS = length($OperandLHS);
+ my @LHS = ( hex substr($OperandLHS, 0, $LengthLHS - 8),
+ hex substr($OperandLHS, $LengthLHS - 8) );
+ my $LengthRHS = length($OperandRHS);
+ my @RHS = ( hex substr($OperandRHS, 0, $LengthRHS - 8),
+ hex substr($OperandRHS, $LengthRHS - 8) );
+ my $Result = ( $LHS[0] < $RHS[0] or
+ ($LHS[0] == $RHS[0] and $LHS[1] <= $RHS[1]) ) ? 1 : 0;
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# IsGt - Operator '>' test for up to 64-bit hexadecimal numbers
+# ------------------------------------------------------------------------------
+sub IsGt {
+
+ # Passed parameter 1 is the LHS value
+ my $OperandLHS = shift;
+ # Passed parameter 2 is the RHS value
+ my $OperandRHS = shift;
+
+ # Local variable(s)
+ my $LengthLHS = length($OperandLHS);
+ my @LHS = ( hex substr($OperandLHS, 0, $LengthLHS - 8),
+ hex substr($OperandLHS, $LengthLHS - 8) );
+ my $LengthRHS = length($OperandRHS);
+ my @RHS = ( hex substr($OperandRHS, 0, $LengthRHS - 8),
+ hex substr($OperandRHS, $LengthRHS - 8) );
+ my $Result = ( $LHS[0] > $RHS[0] or
+ ($LHS[0] == $RHS[0] and $LHS[1] > $RHS[1]) ) ? 1 : 0;
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# IsLt - Operator '<' test for up to 64-bit hexadecimal numbers
+# ------------------------------------------------------------------------------
+sub IsLt {
+
+ # Passed parameter 1 is the LHS value
+ my $OperandLHS = shift;
+ # Passed parameter 2 is the RHS value
+ my $OperandRHS = shift;
+
+ # Local variable(s)
+ my $LengthLHS = length($OperandLHS);
+ my @LHS = ( hex substr($OperandLHS, 0, $LengthLHS - 8),
+ hex substr($OperandLHS, $LengthLHS - 8) );
+ my $LengthRHS = length($OperandRHS);
+ my @RHS = ( hex substr($OperandRHS, 0, $LengthRHS - 8),
+ hex substr($OperandRHS, $LengthRHS - 8) );
+ my $Result = ( $LHS[0] < $RHS[0] or
+ ($LHS[0] == $RHS[0] and $LHS[1] < $RHS[1]) ) ? 1 : 0;
+
+ return ($Result);
+}
+
+# ------------------------------------------------------------------------------
+# IsEq - Operator '=' test for up to 64-bit hexadecimal numbers
+# ------------------------------------------------------------------------------
+sub IsEq {
+
+ # Passed parameter 1 is the LHS value
+ my $OperandLHS = shift;
+ # Passed parameter 2 is the RHS value
+ my $OperandRHS = shift;
+
+ # Local variable(s)
+ my $LengthLHS = length($OperandLHS);
+ my @LHS = ( hex substr($OperandLHS, 0, $LengthLHS - 8),
+ hex substr($OperandLHS, $LengthLHS - 8) );
+ my $LengthRHS = length($OperandRHS);
+ my @RHS = ( hex substr($OperandRHS, 0, $LengthRHS - 8),
+ hex substr($OperandRHS, $LengthRHS - 8) );
+ my $Result = ($LHS[0] == $RHS[0] and $LHS[1] == $RHS[1]) ? 1 : 0;
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# TidyPath - Removes double and trailing slash characters from filename paths
+# ------------------------------------------------------------------------------
+sub TidyPath {
+
+ # Passed parameter 1 is the filepath string
+ my $Filepath = shift;
+
+ $Filepath =~ s/(\/\/|\\)/\//g; $Filepath =~ s/\/$//;
+
+ return ($Filepath);
+}
+
+
+# ------------------------------------------------------------------------------
+# GetRemapBits - Takes the Remapping and Unmapping (if exists) of an
+# address_region or remap_region and returns a sorted list of the bits
+# when the region is enabled. Returns an empty list if the region is always
+# enabled. Negative bits are marked with an exclamation mark
+# example:
+# a remap region that is activated by bit 3
+# but is eclipsed when bit 1 is active will return:
+# [
+# '!1',
+# '3'
+# ],
+# ------------------------------------------------------------------------------
+sub GetRemapBits {
+ my $Remapping = shift;
+ my $Unmapping = shift;
+ my @bits = ();
+ my @c_bits = ();
+ my $r_bit;
+ if (substr($Remapping,0,3) eq "del") {
+ @c_bits = split ( /,| |_/,substr($Remapping,3)) ;
+ foreach $r_bit (@c_bits) {
+ if (!($r_bit eq '')) { # need to ignore leading empty characters generated by a leading separator
+ push @bits, '!'.$r_bit;
+ }
+ }
+ }
+ if (substr($Remapping,0,5) eq "remap") {
+ @c_bits = split ( /,| |_/,substr($Remapping,5)) ;
+ foreach $r_bit (@c_bits) {
+ if (!($r_bit eq '')) { # need to ignore leading empty characters generated by a leading separator
+ push @bits, $r_bit;
+ }
+ }
+ }
+ if ($Unmapping) {
+ @c_bits = split ( /,| |_/,substr($Unmapping,5)) ;
+ foreach $r_bit (@c_bits) {
+ if (!($r_bit eq '')) { # need to ignore leading empty characters generated by a leading separator
+ push @bits, '!'.$r_bit;
+ }
+ }
+ }
+
+ # Sort bits in order, so they are easier to match
+ @bits = sort {
+ my $c = $a;
+ my $d = $b;
+ if ( substr($a,0,1) eq '!') {
+ $c = substr($a,1)
+ }
+ if ( substr($b,0,1) eq '!') {
+ $d = substr($b,1)
+ }
+
+ $c <=> $d
+ } @bits;
+ return (@bits);
+}
+
+# ------------------------------------------------------------------------------
+# ValidateParameters - Checks the value of user configurable script parameters
+# ------------------------------------------------------------------------------
+sub ValidateParameters {
+
+ # Local variable(s)
+ my %Names = (
+ bus_matrix_name => \$BusMatrixName,
+ input_stage_name => \$InputStageName,
+ matrix_decode_name => \$MatrixDecodeName,
+ output_arbiter_name => \$OutputArbName,
+ output_stage_name => \$OutputStageName
+ );
+ my @NameKeys = keys( %Names );
+ my $Name = '';
+ my $NameLength = 0;
+ my $ShowName = '';
+ my @OtherNameKeys = ();
+ my $OtherName = '';
+ my $Type = '';
+ my @Interfaces = ();
+ my $Interface = '';
+
+ # Validate permitted values for the total slave interfaces
+ unless ( $SlaveInterfaces >= $MinSlaveIF and $SlaveInterfaces <= $MaxSlaveIF ) {
+ warn "Error: The number of slave ports must be in the range from $MinSlaveIF to $MaxSlaveIF \n";
+ $Errors++;
+ }
+
+ # Validate permitted values for the total master interfaces
+ unless ( $MasterInterfaces >= $MinMasterIF and $MasterInterfaces <= $MaxMasterIF ) {
+ warn "Error: The number of master ports must be in the range from $MinMasterIF to $MaxMasterIF \n";
+ $Errors++;
+ }
+
+ # Raise a warning about the '1 x n' bus matrix configuration
+ if ( $SlaveInterfaces == 1 ) {
+ warn "Warning: This configuration has one slave port and will use 'single' output\n" .
+ " and arbiter stage(s) only.\n";
+ }
+
+ # Validate permitted values of arbitration scheme
+ unless ( $ArbiterType =~ /^(fixed|round|burst)$/ ) {
+ warn "Error: Invalid type of arbitration-scheme '$ArbiterType'!\n";
+ $Errors++;
+ }
+
+ # Validate permitted values of architecture version
+ unless ( $ArchitectureType =~ /^(ahb2|v6|excl|unalign)$/ ) {
+ warn "Error: Invalid type of architecture '$ArchitectureType'!\n";
+ $Errors++;
+ }
+
+ # Validate permitted values of routing-data width
+ unless ( $RoutingDataWidth =~ /^($DataWidths)$/ ) {
+ warn "Error: Invalid routing-data width '$RoutingDataWidth'!\n";
+ $Errors++;
+ }
+
+ # Validate permitted values of user-signal width
+ if ( $RoutingAddressWidth =~ /[^0-9]/ ) {
+ warn "Error: Invalid routing-address width '$RoutingAddressWidth'!\n";
+ $Errors++;
+ } elsif ( $RoutingAddressWidth < $MinAddrWidth or $RoutingAddressWidth > $MaxAddrWidth ) {
+ warn "Error: Routing-address width must be in the range $MinAddrWidth..$MaxAddrWidth!\n";
+ $Errors++;
+ }
+
+ # Validate permitted values of user-signal width
+ if ( $UserSignalWidth =~ /[^0-9]/ ) {
+ warn "Error: Invalid user-signal width '$UserSignalWidth'!\n";
+ $Errors++;
+ } elsif ( $UserSignalWidth < $MinUserWidth or $UserSignalWidth > $MaxUserWidth ) {
+ warn "Error: User-signal width must be in the range $MinUserWidth..$MaxUserWidth!\n";
+ $Errors++;
+ }
+
+ # Validate permitted values of module names
+ foreach $Name ( @NameKeys ) {
+ $ShowName = $Name; $ShowName =~ s/_/ /g;
+ $NameLength = length( ${ $Names{$Name} } );
+
+ # Check for illegal characters and then check the string length
+ if ( ${ $Names{$Name} } =~ /[^\w]/ ) {
+ warn "Error: The $ShowName contains illegal characters!\n";
+ $Errors++;
+ } elsif ( $NameLength < $MinNameLength or $NameLength > $MaxNameLength ) {
+ warn "Error: The $ShowName is incorrect length ($MinNameLength..$MaxNameLength characters)!\n";
+ $Errors++;
+ }
+
+ # Check for unique name
+ @OtherNameKeys = grep $_ ne $Name , @NameKeys;
+ foreach $OtherName ( @OtherNameKeys ) {
+ if ( ${ $Names{$OtherName} } eq ${ $Names{$Name} } ) {
+ warn "Error: The $ShowName is not assigned a unique value!\n";
+ $Errors++;
+ }
+ }
+ }
+
+ # Check interface information
+ foreach $Type ( ('SLAVES', 'MASTERS') ) {
+
+ @Interfaces = keys( %{ $InterfaceInfo{$Type} } );
+ foreach $Interface ( @Interfaces ) {
+ # Inspect interface names
+ $Name = $InterfaceInfo{$Type}{$Interface}{NAME};
+ if ( $Name =~ /[^\w]/ ) {
+ warn "Error: Interface $Interface name '$Name' contains illegal characters!\n";
+ $Errors++;
+ }
+ if ( length($Name) > $MaxNameLength ) {
+ warn "Error: Interface $Interface name '$Name' is too long ($MaxNameLength" .
+ " characters max)!\n";
+ $Errors++;
+ }
+
+ # Inspect connectivity for isolated nodes resulting from an
+ # incomplete sparse mapping
+ if ( @{ $InterfaceInfo{$Type}{$Interface}{CONNECTIONS} } == 0 ) {
+ warn "Error: Interface $Interface has no connectivity mapping and is isolated!\n";
+ $Errors++;
+ }
+
+ # If this is a slave, then check its address map
+ if ( $Type eq 'SLAVES' ) { CheckAddressMap($Interface); }
+ }
+
+ }
+
+}
+
+
+# ------------------------------------------------------------------------------
+# CheckAddressMap - Checks the address map of the specified slave interface
+# for tags and overlapping regions
+# ------------------------------------------------------------------------------
+sub CheckAddressMap {
+
+ # Passed parameter 1 is the integer value
+ my $SlaveIF = shift;
+
+ # Local variable(s)
+ my $Class = '';
+ my $Index = 0;
+ my $MasterIF = '';
+ my @MIRegions = ();
+ my $Region = '';
+ my $MI = '';
+ my $Tag = '';
+ my $RegionHi = '';
+ my $RegionLo = '';
+ my $RegionHiLSW = 0;
+ my $RegionLoLSW = 0;
+ my $CheckBound = '';
+ my $OtherRegion = '';
+ my $OtherMI = '';
+ my $OtherHi = '';
+ my $OtherLo = '';
+ my $OtherTag = 0;
+ my $Exclusions = '';
+ my $HexChars = NumberOfHexChars($RoutingAddressWidth);
+ my %Tags = ( NORMAL => 'none|move|alias', REMAP => 'remap[0-3]' );
+ my %TagMessages = ( NORMAL => 'remapping action', REMAP => 'REMAP bit' );
+ my %WarnType = ( NORMAL => 'address', REMAP => 'remap' );
+
+ # Process each mapping type
+ foreach $Class ( ('REMAP', 'NORMAL') ) {
+
+ # Check the address map for each master interface
+ for ( $Index = 0; $Index < $MasterInterfaces; $Index++ ) {
+ $MasterIF = 'MI' . $Index;
+
+ # Find regions matching the master interface under inspection
+ @MIRegions = grep /^$MasterIF:/, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{$Class} };
+
+ # Determine if this slave interface has connectivity with the master interface
+ if ( grep $_ eq $MasterIF, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} } ) {
+
+ # Check for expected address regions
+ unless ( $Class eq 'REMAP' or @MIRegions > 0 ) {
+ warn "Error: Interface $SlaveIF has no address regions defined for the $MasterIF interface!\n";
+ $Errors++;
+ }
+
+ # Inspect each region mapped to the master interface
+ foreach $Region ( @MIRegions ) {
+
+ # Split the region into its constituent parts
+ ($MI, $Tag, $RegionLo, $RegionHi) = split(/:/, $Region);
+
+ # Extract and remove the expected prefix, then check its type
+ unless ( $Tag =~ /^($Tags{$Class})$/ ) {
+ warn "Error: Interface $SlaveIF address region '$MI: $RegionLo-$RegionHi'" .
+ " declares\n unsupported $TagMessages{$Class}!\n";
+ $Errors++;
+ }
+
+ # Check that each bound only consists of hexadecimal characters
+ # and is the expected number of hexadecimal digits
+ foreach $CheckBound ( $RegionLo, $RegionHi ) {
+ if ( length($CheckBound) != $HexChars ) {
+ warn "Error: Interface $SlaveIF address bound '$MI: $CheckBound' is incorrect length should be $HexChars characters!\n";
+ $Errors++;
+ }
+ if ( $CheckBound =~ /[^a-f0-9]+/i ) {
+ warn "Error: Interface $SlaveIF address bound '$MI: $CheckBound' contains illegal characters!\n";
+ $Errors++;
+ }
+ }
+
+ # Check the region syntax
+ if ( IsGtOrEq($RegionLo, $RegionHi) ) {
+ warn "Error: Interface $SlaveIF address region '$MI: $RegionLo-$RegionHi' is invalid!\n";
+ $Errors++;
+ }
+
+ # Check the region size - minimum is 1kBytes
+ $RegionHiLSW = hex substr($RegionHi, length($RegionHi) - 8);
+ $RegionLoLSW = hex substr($RegionLo, length($RegionLo) - 8);
+ if ( abs( $RegionHiLSW - $RegionLoLSW ) < 1023 ) {
+ warn "Error: Interface $SlaveIF address region '$MI: $RegionLo-$RegionHi' is < 1kBytes!\n";
+ $Errors++;
+ }
+
+ # Check alignment of lower address bound
+ if ( ( hex(substr($RegionLo, -3, 3)) & 0x3ff ) != 0x000 ) {
+ warn "Warning: Interface $SlaveIF address bound '$MI: $RegionLo' is misaligned!\n";
+ }
+
+ # Check alignment of upper address bound
+ if ( ( hex(substr($RegionHi, -3, 3)) & 0x3ff ) != 0x3ff ) {
+ warn "Warning: Interface $SlaveIF address bound '$MI: $RegionHi' is misaligned!\n";
+ }
+
+ # Check the current region against all others for illegal overlap
+ foreach $OtherRegion ( @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{$Class} } ) {
+
+ # Split the other region into its constituent parts
+ ($OtherMI, $OtherTag, $OtherLo, $OtherHi) = split(/:/, $OtherRegion);
+
+ # Exclude remap regions with different remap bits
+ if ( $Class eq 'REMAP' and $Tag ne $OtherTag ) { next; }
+
+ # Filter out the current region and any previously reported ones
+ unless ( $OtherRegion =~ /^($Region$Exclusions)$/ ) {
+
+ # Check bounds for overlap
+ if ( (IsGtOrEq($OtherLo, $RegionLo) and IsLtOrEq($OtherLo, $RegionHi)) or
+ (IsGtOrEq($OtherHi, $RegionLo) and IsLtOrEq($OtherHi, $RegionHi)) ) {
+
+ warn "Error: Interface $SlaveIF $WarnType{$Class} region '$OtherMI: $OtherLo-$OtherHi'" .
+ " overlaps\n with another $WarnType{$Class} region '$MI: $RegionLo-$RegionHi'!\n";
+ $Errors++;
+
+ # Suppress multiple messages that show the same error
+ $Exclusions = $Exclusions . "|$MI:[^:]+:$RegionLo:$RegionHi";
+ }
+
+ }
+ }
+
+ }
+
+ } elsif ( @MIRegions > 0 ) {
+ # This slave interface is not connected to the master interface and
+ # therefore should not have any address map information
+ warn "Error: Interface $SlaveIF has an address map for $MasterIF interface,\n" .
+ " while not connected!\n";
+ $Errors++;
+ }
+ }
+
+ # Clear the exclusions for checking the next class
+ $Exclusions = '';
+
+ }
+
+}
+
+
+# ------------------------------------------------------------------------------
+# InitialiseInterfaceInfo - Determines the connectivity mapping and address
+# map, assigning values to the global interface
+# information hash
+# ------------------------------------------------------------------------------
+sub InitialiseInterfaceInfo {
+
+ # Local variable(s)
+ my $SlaveIF = '';
+ my $MasterIF = '';
+ my $Index1 = 0;
+ my $Index2 = 0;
+ my $Regions = RoundPowerOfTwo($MasterInterfaces);
+ my $RegionSize = (2 ** $RoutingAddressWidth) / $Regions;
+ my $BaseAddress = 0;
+ my $TopAddress = 0;
+ my @Mappings = split(/:\s*/, $Connectivity);
+ my $Mapping = '';
+ my @Interfaces = ();
+ my $HexChars = NumberOfHexChars($RoutingAddressWidth);
+ my $Format = "%0${HexChars}s";
+
+ # Initialise master interface parameter(s) first to simplify the sequence
+ for ( $Index1 = 0; $Index1 < $MasterInterfaces; $Index1++ ) {
+ $MasterIF = 'MI' . $Index1;
+ $InterfaceInfo{MASTERS}{$MasterIF}{NAME} = $MasterIF;
+ $InterfaceInfo{MASTERS}{$MasterIF}{CONNECTIONS} = [];
+ }
+
+ # Initialise slave interface parameter(s)
+ for ( $Index1 = 0; $Index1 < $SlaveInterfaces; $Index1++ ) {
+ # Initialise slave information container
+ $SlaveIF = 'SI' . $Index1;
+ $InterfaceInfo{SLAVES}{$SlaveIF}{NAME} = $SlaveIF;
+ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} = [];
+ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} = [];
+ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} = [];
+
+ # Establish the connectivity
+ if ( $Connectivity ne 'full' ) {
+
+ # Initialise or concatenate the connection description string
+ $Connectivity = 'sparse';
+ $Connections = $Connections . sprintf("%s%s -> ", ($Connections eq '') ?
+ '' : "\n" . ' ' x 29, $InterfaceInfo{SLAVES}{$SlaveIF}{NAME});
+
+ # Search the connectivity string for a mapping from this slave interface
+ foreach $Mapping ( @Mappings ) {
+ if ( $Mapping =~ /^$SlaveIF=MI\{([0-9,]+)\}/) {
+ # Process each master interface in turn, checking for its existence
+ @Interfaces = split(/,\s*/, $1);
+ foreach $MasterIF ( @Interfaces ) {
+ $MasterIF = 'MI' . $MasterIF;
+ if ( exists( $InterfaceInfo{MASTERS}{$MasterIF} ) ) {
+ # Append the details of this sparse connection
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} }, $MasterIF;
+ $Connections = $Connections . "$MasterIF, ";
+ } else {
+ warn "Error: Interface $SlaveIF has an unresolved sparse connection '$MasterIF'!\n";
+ $Errors++;
+ }
+ }
+ }
+ }
+
+ } else {
+ # Full connectivity is default
+ for ( $Index2 = 0; $Index2 < $MasterInterfaces; $Index2++ ) {
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} }, 'MI' . $Index2;
+ }
+ }
+
+ # Determine address map (assume no remap regions)
+ for ( $Index2 = 0; $Index2 < $MasterInterfaces; $Index2++ ) {
+ $MasterIF = 'MI' . $Index2;
+ $BaseAddress = $RegionSize * $Index2;
+ $TopAddress = $BaseAddress + $RegionSize - 1;
+ if ( grep $_ eq $MasterIF, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} } ) {
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} },
+ sprintf("%s:none:$Format:$Format", $MasterIF, UnsignedFloatToHex($BaseAddress),
+ UnsignedFloatToHex($TopAddress));
+ }
+ }
+ }
+
+ # Remove leading whitespace from the connections detail
+ $Connections =~ s/,\s+$//;
+
+ # Determine connectivity information from master interface perspective
+ for ( $Index1 = 0; $Index1 < $MasterInterfaces; $Index1++ ) {
+ $MasterIF = 'MI' . $Index1;
+ for ( $Index2 = 0; $Index2 < $SlaveInterfaces; $Index2++ ) {
+ $SlaveIF = 'SI' . $Index2;
+ if ( grep $_ eq $MasterIF, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} } ) {
+ push @{ $InterfaceInfo{MASTERS}{$MasterIF}{CONNECTIONS} }, $SlaveIF;
+ }
+ }
+ }
+
+}
+
+
+# ------------------------------------------------------------------------------
+# ProcessXmlConfigFile - Reads the specified XML configuration file and
+# assigns values to the global variables including
+# the interface information hash
+# ------------------------------------------------------------------------------
+sub ProcessXmlConfigFile {
+
+ # Local variable(s)
+ my @Elements = ();
+ my $XmlItem = '';
+ my $XmlElement = '';
+ my @SlavePorts = ();
+ my @MasterPorts = ();
+ my $Index1 = 1;
+ my $Index2 = 0;
+ my $SlaveIF = '';
+ my $MasterIF = '';
+ my $Name = '';
+ my $Region = '';
+
+ # Configure the XML parser
+ ConfigureXmlParser( show_ids => 0, verbose => 0, show_warnings => 0 );
+
+ # Read the specified configuration file
+ RunXmlParser($XmlConfigFile);
+
+ # Display the XML structure when in debug mode
+ if ( $Debug ) { ListXmlHash('ROOT'); }
+
+ # Access mandatory items of information (bus matrix dimensions)
+ @SlavePorts = GetXmlNodeList('//cfgfile/slave_interface');
+ $SlaveInterfaces = scalar @SlavePorts;
+ @MasterPorts = GetXmlNodeList('//cfgfile/master_interface');
+ $MasterInterfaces = scalar @MasterPorts;
+
+ # Access optional items of information
+ @Elements = GetXmlNodeList('/cfgfile');
+ foreach $XmlElement ( @Elements ) {
+ # Assign the extracted value to the appropriate parameter name
+ $XmlItem = GetXmlValue("/cfgfile/$XmlElement");
+ if ( $XmlElement =~ /arbitration_scheme\[1\]$/ ) {
+ $ArbiterType = $XmlItem;
+ } elsif ( $XmlElement =~ /architecture_version\[1\]$/ ) {
+ $ArchitectureType = $XmlItem;
+ } elsif ( $XmlElement =~ /routing_data_width\[1\]$/ ) {
+ $RoutingDataWidth = $XmlItem;
+ } elsif ( $XmlElement =~ /routing_address_width\[1\]$/ ) {
+ $RoutingAddressWidth = $XmlItem;
+ } elsif ( $XmlElement =~ /user_signal_width\[1\]$/ ) {
+ $UserSignalWidth = $XmlItem;
+ } elsif ( $XmlElement =~ /timescales\[1\]$/ ) {
+ $XmlTimescales = $XmlItem;
+ } elsif ( $XmlElement =~ /bus_matrix_name\[1\]$/ ) {
+ $BusMatrixName = $XmlItem;
+ } elsif ( $XmlElement =~ /input_stage_name\[1\]$/ ) {
+ $InputStageName = $XmlItem;
+ } elsif ( $XmlElement =~ /matrix_decode_name\[1\]$/ ) {
+ $MatrixDecodeName = $XmlItem;
+ } elsif ( $XmlElement =~ /output_arbiter_name\[1\]$/ ) {
+ $OutputArbName = $XmlItem;
+ } elsif ( $XmlElement =~ /output_stage_name\[1\]$/ ) {
+ $OutputStageName = $XmlItem;
+ } elsif ( $XmlElement =~ /product_version_info\[1\]$/ ) {
+ $ComponentName = GetXmlValue("/cfgfile/$XmlElement" . '@component_name');
+ } elsif ( $XmlElement !~ /(slave|master)_interface\[\d+\]/ ) {
+ warn "Error: Unknown XML option '$XmlElement'!\n";
+ $Errors++;
+ }
+ }
+
+ # Extract master interface parameter(s) first to simplify the sequence
+ foreach $XmlElement ( @MasterPorts ) {
+
+ # Initialise information container and increment the count
+ $MasterIF = sprintf("MI%d", $Index2++);
+ $Name = GetXmlValue($XmlElement . '@name');
+ $InterfaceInfo{MASTERS}{$MasterIF}{NAME} = $Name;
+ $InterfaceInfo{MASTERS}{$MasterIF}{CONNECTIONS} = [];
+
+ # Add the name to the master alias lookup hash
+ if ( ! exists( $NameAliases{$Name} ) ) {
+ $NameAliases{$Name} = $MasterIF;
+ } else {
+ warn "Error: Interface $MasterIF name '$Name' is not unique!\n";
+ $Errors++;
+ }
+
+ }
+
+ # Extract slave interface parameter(s)
+ foreach $XmlElement ( @SlavePorts ) {
+
+ # Initialise information container
+ $SlaveIF = sprintf("SI%d", $Index1 - 1);
+ $Name = GetXmlValue($XmlElement . '@name');
+ $InterfaceInfo{SLAVES}{$SlaveIF}{NAME} = $Name;
+ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} = [];
+ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} = [];
+ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} = [];
+
+ # Add the name to the slave alias lookup hash
+ if ( ! exists( $NameAliases{$Name} ) ) {
+ $NameAliases{$Name} = $SlaveIF;
+ } else {
+ warn "Error: Interface $SlaveIF name '$Name' is not unique!\n";
+ $Errors++;
+ }
+
+ # Extract connectivity information or assign full connectivity as default
+ @Elements = GetXmlNodeList("//cfgfile/slave_interface[$Index1]/sparse_connect");
+ if ( @Elements > 0 ) {
+ # Initialise or concatenate the connection description string
+ $Connectivity = 'sparse';
+ $Connections = $Connections . sprintf("%s%s -> ", ($Connections eq '') ?
+ '' : "\n" . ' ' x 29, $InterfaceInfo{SLAVES}{$SlaveIF}{NAME});
+
+ # Convert the symbolic interface names to the MI<n> notation
+ foreach $XmlItem ( @Elements ) {
+ # Extract sparse connection attribute and check for existence of the
+ # named interface
+ $MasterIF = GetXmlValue($XmlItem . '@interface');
+ if ( exists( $NameAliases{$MasterIF} ) ) {
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} }, $NameAliases{$MasterIF};
+ } else {
+ warn "Error: Interface '$Name' has an unresolved sparse connection '$MasterIF'!\n";
+ $Errors++;
+ }
+ # Append this sparse connection detail
+ $Connections = $Connections . "$MasterIF, ";
+ }
+
+ } else {
+ # Full connectivity is default
+ for ( $Index2 = 0; $Index2 < $MasterInterfaces; $Index2++ ) {
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} }, 'MI' . $Index2;
+ }
+ }
+
+ # Extract address mapping information
+ @Elements = GetXmlNodeList("//cfgfile/slave_interface[$Index1]/address_region");
+ if ( @Elements > 0 ) {
+ foreach $XmlItem ( @Elements ) {
+ # Determine which master interface this address region is for, and
+ # check that it exists
+ $MasterIF = GetXmlValue($XmlItem . '@interface');
+ if ( exists( $NameAliases{$MasterIF} ) ) {
+ $Region = sprintf("%s:%s:%s:%s", $NameAliases{$MasterIF},
+ GetXmlValue($XmlItem . '@remapping'),
+ GetXmlValue($XmlItem . '@mem_lo'),
+ GetXmlValue($XmlItem . '@mem_hi'));
+ # Check for duplicated definitions
+ if ( grep $_ eq $Region, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} } ) {
+ warn "Error: Interface '$Name' has duplicated address region for master interface '$MasterIF'\n";
+ $Errors++;
+ } else {
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} }, $Region;
+ }
+
+ } else {
+ warn "Error: Address region maps to unknown master interface '$MasterIF'\n";
+ $Errors++;
+ }
+ }
+ } else {
+ warn "Error: Expecting an address region for interface '$SlaveIF'\n";
+ $Errors++;
+ }
+
+ # Extract the optional remapped address information
+ @Elements = GetXmlNodeList("//cfgfile/slave_interface[$Index1]/remap_region");
+ foreach $XmlItem ( @Elements ) {
+ # Determine which master interface this remap region is for, and
+ # check that it exists
+ $MasterIF = GetXmlValue($XmlItem . '@interface');
+ if ( exists( $NameAliases{$MasterIF} ) ) {
+ $Region = sprintf("%s:remap%s:%s:%s", $NameAliases{$MasterIF},
+ GetXmlValue($XmlItem . '@bit'),
+ GetXmlValue($XmlItem . '@mem_lo'),
+ GetXmlValue($XmlItem . '@mem_hi'));
+ # Check for duplicated definitions
+ if ( grep $_ eq $Region, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} } ) {
+ warn "Error: Interface '$Name' has duplicated remap region for master interface '$MasterIF'\n";
+ $Errors++;
+ } else {
+ push @{ $InterfaceInfo{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} }, $Region;
+ }
+
+ } else {
+ warn "Error: Remap region maps to unknown master interface '$MasterIF'\n";
+ $Errors++;
+ }
+ }
+
+ # Increment index
+ $Index1++;
+ }
+
+ # Remove leading whitespace from the connections detail
+ $Connections =~ s/,\s+$//;
+
+ # Determine connectivity information from master interface perspective
+ for ( $Index1 = 0; $Index1 < $MasterInterfaces; $Index1++ ) {
+ $MasterIF = 'MI' . $Index1;
+ for ( $Index2 = 0; $Index2 < $SlaveInterfaces; $Index2++ ) {
+ $SlaveIF = 'SI' . $Index2;
+ if ( grep $_ eq $MasterIF, @{ $InterfaceInfo{SLAVES}{$SlaveIF}{CONNECTIONS} } ) {
+ push @{ $InterfaceInfo{MASTERS}{$MasterIF}{CONNECTIONS} }, $SlaveIF;
+ }
+ }
+ }
+
+
+}
+
+sub ProcessDataForIPXact {
+
+ # Work on a copy for IPXact
+ %InterfaceInfoIPXact = %{ dclone \%InterfaceInfo };
+
+ my $SlaveIF = '';
+ my $MasterIF = '';
+
+ my @address_regions = ();
+ my $address_region;
+ my $remap_region;
+ my $AddrLo = '';
+ my $AddrHi = '';
+ my $Remapping = '';
+ my $r_MasterIF = '';
+ my $r_AddrLo = '';
+ my $r_AddrHi = '';
+ my $r_Remapping = '';
+ my $new_Remapping= '';
+ my $split_done = '';
+ my $r_bit = '';
+ my $r2_bit = '';
+ my $Unmapping = '';
+ my $new_Unmapping= '';
+
+ # Convert move to del
+ foreach $SlaveIF (keys %{$InterfaceInfoIPXact{SLAVES}} ) {
+ @address_regions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} };
+ foreach $address_region (@address_regions) {
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $address_region);
+ $new_Remapping = $Remapping;
+ if ($Remapping eq 'move') {
+ foreach $remap_region (@{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} }) {
+ ($r_MasterIF, $r_Remapping, $r_AddrLo, $r_AddrHi) = split(/:/, $remap_region);
+ $r_bit = substr($r_Remapping, 5);
+ if ($r_MasterIF eq $MasterIF) {
+ if (substr($new_Remapping,0,3) eq "del") {
+ # Check if it's already in the _del_
+ if ($new_Remapping =~ m/.*(del|_|,|\s)$r_bit(_|,|\s|$)/ ) {
+ $new_Remapping = $new_Remapping;
+ } else {
+ $new_Remapping = $new_Remapping . "," . $r_bit;
+ }
+ } else {
+ $new_Remapping = "del" . $r_bit;
+ }
+ }
+ }
+ if ( !($new_Remapping eq $Remapping) ) {
+ $address_region = $MasterIF .":". $new_Remapping .":". $AddrLo .":". $AddrHi;
+ print "Converted " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi . " to " . $new_Remapping . "\n" if $Debug;
+ }
+ }
+ }
+ @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} } = @address_regions;
+ }
+
+ ############################ ADDRESS REGION ############################
+ # Cut address_regions if remap_regions overlap
+ foreach $SlaveIF (keys %{$InterfaceInfoIPXact{SLAVES}} ) {
+
+ # Cut address_regions
+ @address_regions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} };
+ foreach $remap_region (@{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} }) {
+ ($r_MasterIF, $r_Remapping, $r_AddrLo, $r_AddrHi) = split(/:/, $remap_region);
+ $r_bit = substr($r_Remapping, 5);
+ foreach $address_region (@address_regions) {
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $address_region);
+ # Make new address region remapping type
+ if (substr($Remapping,0,3) eq "del") {
+ # Check if it's already in the _del_
+ if ($Remapping =~ m/.*(del|_|,|\s)$r_bit(_|,|\s|$)/ ) {
+ $new_Remapping = $Remapping;
+ } else {
+ $new_Remapping = $Remapping . "," . $r_bit;
+ }
+ } else {
+ $new_Remapping = "del" . $r_bit;
+ }
+ # Split the address region that is covered by a remap region
+ if ( IsLt( $AddrLo , $r_AddrLo) && IsLt( $r_AddrHi, $AddrHi) ) {
+ $address_region = $MasterIF .":". $new_Remapping .":". $r_AddrLo .":". $r_AddrHi;
+ push (@address_regions, $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1));
+ push (@address_regions, $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi);
+
+ if ($Debug) {
+ print "Splitting for encapsulated " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi . "\n";
+ print " Into " . $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1) . "\n";
+ print " Add " . $MasterIF .":". $new_Remapping .":". $r_AddrLo .":". $r_AddrHi . "\n";
+ print " And " . $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi . "\n";
+ if (substr($Remapping,0,3) eq "del") {
+ print "^ (Double Del)\n";
+ }
+ print "---------------------------------------------------------------------\n";
+ }
+ redo;
+ } elsif ( IsLt( $AddrLo , $r_AddrLo) && IsLt( $r_AddrLo , $AddrHi) ) {
+ $address_region = $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1);
+ push (@address_regions, $MasterIF .":". $new_Remapping .":". $r_AddrLo .":". $AddrHi);
+
+ if ($Debug) {
+ print "Splitting low region " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi . "\n";
+ print " Into " . $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1) . "\n";
+ print " And " . $MasterIF .":". $new_Remapping .":". $r_AddrLo .":". $AddrHi . "\n";
+ if (substr($Remapping,0,3) eq "del") {
+ print "^ (Double Del)\n";
+ }
+ print "---------------------------------------------------------------------\n";
+ }
+ redo;
+ } elsif ( IsLt( $AddrLo , $r_AddrHi) && IsLt( $r_AddrHi , $AddrHi) ) {
+ $address_region = $MasterIF .":". $new_Remapping .":". $AddrLo .":". $r_AddrHi;
+ push (@address_regions, $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi);
+ if ($Debug) {
+ print "Splitting high region " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi . "\n";
+ print " Into " . $MasterIF .":". $new_Remapping .":". $AddrLo .":". $r_AddrHi . "\n";
+ print " And " . $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi . "\n";
+ if (substr($Remapping,0,3) eq "del") {
+ print "^ (Double Del)\n";
+ }
+ print "---------------------------------------------------------------------\n";
+ }
+ redo;
+ } elsif ( IsGtOrEq( $AddrLo , $r_AddrLo) && IsGtOrEq( $r_AddrHi , $AddrHi) && !($new_Remapping eq $Remapping) ) {
+ $address_region = $MasterIF .":". $new_Remapping .":". $AddrLo .":". $AddrHi;
+ if ($Debug) {
+ print "Changed region to deletable " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi . "\n";
+ print " Into " . $MasterIF .":". $new_Remapping .":". $AddrLo .":". $AddrHi . "\n";
+ if (substr($Remapping,0,3) eq "del") {
+ print "^ (Double Del)\n";
+ }
+ print "---------------------------------------------------------------------\n";
+ }
+
+ }
+ }
+ }
+ @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} } =
+ sort {
+ my @split_a = split /:/, $a;
+ my @split_b = split /:/, $b;
+ my $c;
+ my $d;
+ if ( IsLt($split_a[2],$split_b[2]) ) {
+ $c = 1;
+ $d = 2;
+ } else {
+ $c = 2;
+ $d = 1;
+ }
+ $c <=> $d
+# (hex $split_a[2]) <=> (hex $split_b[2] )
+ } @address_regions;
+
+ ############################ REMAP ############################
+ # Cut remap_regions
+ @address_regions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} }; # reusing address_region for remaps
+ foreach $remap_region (@{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} }) {
+ ($r_MasterIF, $r_Remapping, $r_AddrLo, $r_AddrHi) = split(/:/, $remap_region);
+ $r_bit = substr($r_Remapping, 5);
+ foreach $address_region (@address_regions) {
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi, $Unmapping) = split(/:/, $address_region);
+ $r2_bit = substr($Remapping, 5);
+
+ if ($r_bit<$r2_bit) {
+
+ # If there is already an Unmapping defined
+ if ($Unmapping) {
+ # Check if it's already in the _del_
+ if ($Unmapping =~ m/.*(unmap|_|,|\s)$r_bit(_|,|\s|$)/ ) {
+ $new_Unmapping = $Unmapping;
+ } else {
+ $new_Unmapping = $r_bit < $r2_bit ? $Unmapping . "," . $r_bit : $Unmapping;
+ }
+ } else {
+ $new_Unmapping = "unmap " . $r_bit;
+ $Unmapping = '';
+ }
+ # Lower remap bit has higher priority
+
+ # Split the remap region that is covered by another remap region of higher priority
+ if ( IsLt( $AddrLo , $r_AddrLo) && IsLt( $r_AddrHi, $AddrHi) ) {
+ $address_region = $MasterIF .":". $Remapping .":". $r_AddrLo .":". $r_AddrHi.":".$new_Unmapping;
+ push (@address_regions, $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1).":".$Unmapping);
+ push (@address_regions, $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi.":".$Unmapping);
+ if ($Debug) {
+ print "Splitting remap for encapsulated " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi .":".$Unmapping. "\n";
+ print " Into " . $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1) .":".$Unmapping. "\n";
+ print " Add " . $MasterIF .":". $Remapping .":". $r_AddrLo .":". $r_AddrHi . ":".$new_Unmapping . "\n";
+ print " And " . $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi .":".$Unmapping. "\n";
+ print "---------------------------------------------------------------------\n";
+ }
+ redo;
+ } elsif ( IsLt( $AddrLo , $r_AddrLo) && IsLt( $r_AddrLo , $AddrHi) ) {
+ $address_region = $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1).":".$Unmapping;
+ push (@address_regions, $MasterIF .":". $Remapping .":". $r_AddrLo .":". $AddrHi.":".$new_Unmapping);
+ if ($Debug) {
+ print "Splitting low remap region " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi .":".$Unmapping. "\n";
+ print " Into " . $MasterIF .":". $Remapping .":". $AddrLo .":". HexSubstract($r_AddrLo,1) .":".$Unmapping. "\n";
+ print " And " . $MasterIF .":". $Remapping .":". $r_AddrLo .":". $AddrHi .":".$new_Unmapping. "\n";
+ print "---------------------------------------------------------------------\n";
+ }
+ redo;
+ } elsif ( IsLt( $AddrLo , $r_AddrHi) && IsLt( $r_AddrHi , $AddrHi) ) {
+ $address_region = $MasterIF .":". $Remapping .":". $AddrLo .":". $r_AddrHi.":".$new_Unmapping;
+ push (@address_regions, $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi.":".$Unmapping);
+ if ($Debug) {
+ print "Splitting high remap region " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi .":".$Unmapping. "\n";
+ print " Into " . $MasterIF .":". $Remapping .":". $AddrLo .":". $r_AddrHi .":".$new_Unmapping. "\n";
+ print " And " . $MasterIF .":". $Remapping .":". HexAdd($r_AddrHi,1) .":". $AddrHi .":".$Unmapping. "\n";
+ print "---------------------------------------------------------------------\n";
+ }
+ redo;
+ } elsif ( IsGtOrEq( $AddrLo , $r_AddrLo) && IsGtOrEq( $r_AddrHi , $AddrHi) && !($new_Unmapping eq $Unmapping) ) {
+ $address_region = $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi.":".$new_Unmapping;
+ if ($Debug) {
+ print "Changed remap region to unmappable " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi .":".$Unmapping. "\n";
+ print " Into " . $MasterIF .":". $Remapping .":". $AddrLo .":". $AddrHi .":".$new_Unmapping. "\n";
+ print "---------------------------------------------------------------------\n";
+ }
+
+ }
+ }
+ }
+ }
+ @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} } =
+ sort {
+ my @split_a = split /:/, $a;
+ my @split_b = split /:/, $b;
+ my $c;
+ my $d;
+ if ( IsLt($split_a[2],$split_b[2]) ) {
+ $c = 1;
+ $d = 2;
+ } else {
+ $c = 2;
+ $d = 1;
+ }
+ $c <=> $d
+# (hex $split_a[2]) <=> (hex $split_b[2] )
+ } @address_regions;
+
+
+
+
+ # Sort remap in order of priority
+ @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} } =
+ sort {
+ my @split_a = split /:/, $a;
+ my @split_b = split /:/, $b;
+ substr($split_a[1],5) <=> substr($split_b[1],5)
+ } @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} };
+
+ }
+
+ # Generate Remapstates
+ my @bits;
+ my @c_bits;
+ my $remap_name;
+ foreach $SlaveIF (keys %{$InterfaceInfoIPXact{SLAVES}} ) {
+ @address_regions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} };
+ push (@address_regions, @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} });
+ foreach $address_region (@address_regions) {
+ $Unmapping = '';
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi,$Unmapping) = split(/:/, $address_region);
+ @bits = GetRemapBits ($Remapping, $Unmapping);
+ $remap_name = "remap_".join( '_' , @bits );
+ # Change ! to n
+ $remap_name =~ s/!/n/g ;
+
+ # don't put in duplicates
+ if ( @bits && !$RemapStates{$remap_name}) {
+ @{ $RemapStates{$remap_name}} = @bits;
+ }
+ }
+ }
+
+ print "RemapStates:\n" if $Debug;
+ print Dumper(\%RemapStates) if $Debug;
+
+ # Generate AddressSpace regions
+ foreach $SlaveIF (keys %{$InterfaceInfoIPXact{SLAVES}} ) {
+ @address_regions = @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{NORMAL} };
+ push (@address_regions, @{ $InterfaceInfoIPXact{SLAVES}{$SlaveIF}{ADDRESS_MAP}{REMAP} });
+ foreach $address_region (@address_regions) {
+ ($MasterIF, $Remapping, $AddrLo, $AddrHi) = split(/:/, $address_region);
+ if ( !( grep {(@{$_}[0] eq $AddrLo) && (@{$_}[1] eq $AddrHi)} @{ $AddressSpace{$MasterIF} } ) ) {
+ push @{ $AddressSpace{$MasterIF}}, [$AddrLo,$AddrHi];
+ }
+ }
+ }
+
+ # Sort the AddressSpace
+ foreach $MasterIF (keys %AddressSpace) {
+ @{ $AddressSpace{$MasterIF}} = sort {
+ my $c;
+ my $d;
+ if ( IsLt(@{$a}[0],@{$b}[0]) ) {
+ $c = 1;
+ $d = 2;
+ } else {
+ $c = 2;
+ $d = 1;
+ }
+ $c <=> $d
+ } @{ $AddressSpace{$MasterIF}};
+ }
+
+ print "AddressSpace:\n" if $Debug;
+ print Dumper(\%AddressSpace) if $Debug;
+
+ print "InterfaceInfo:\n" if $Debug;
+ print Dumper(\%InterfaceInfo) if $Debug;
+
+ print "InterfaceInfoIPXact:\n" if $Debug;
+ print Dumper(\%InterfaceInfoIPXact) if $Debug;
+
+}
+
+
+# ------------------------------------------------------------------------------
+# ShowHelp - Displays help dialogue (developer's options are not advertised)
+# ------------------------------------------------------------------------------
+sub ShowHelp {
+
+ # Local variable(s)
+ my $ShowArchitectureOptions = 0;
+
+ printf "%sPurpose:\n" .
+ " Builds particular configurations of the AHB BusMatrix component.\n\n" .
+ "Usage:\n" .
+ " Builds an AHB BusMatrix component with a given number of input\n" .
+ " ports, a given number of output ports, a particular arbitration\n" .
+ " scheme and ARM processor interface.\n\n" .
+ "Options:\n" .
+ " --cfg=FILENAME Name of an XML configuration file that\n" .
+ " defines the bus matrix specification\n" .
+ " in place of most command line arguments.\n" .
+ " Note that this is the only method to\n" .
+ " specify customised address maps.\n".
+ "\n" .
+ " use these if not using the config file method:\n" .
+ " --inports=NUM Number of input (slave) ports ($MinSlaveIF..$MaxSlaveIF).\n" .
+ " --outports=NUM Number of output (master) ports ($MinMasterIF..$MaxMasterIF).\n\n" .
+ " --connectivity='SI0=MI\\{0,1,2}:SI1=MI{3,4,5}'\n\n" .
+
+ " Sparse interconnect declarations. The\n" .
+ " example above means inport 0 connects\n" .
+ " to outports 0, 1 and 2, and inport 1\n" .
+ " connects to outports 3, 4 and 5.\n\n" .
+
+ " --arb=SCHEME Arbitration scheme:\n" .
+ " burst - Fixed priority; Master 0 has\n" .
+ " highest priority, does not\n" .
+ " break defined length bursts.\n" .
+ " fixed - Fixed priority; Master 0 has\n" .
+ " highest priority.\n" .
+ " round - Round robin priority; priority\n" .
+ " goes to next available master.\n\n",
+ ( $Verbose ) ? '' : "\n--- $Scriptname ---\n\n";
+
+ # Display option
+ if ( $ShowArchitectureOptions ) {
+ print " --arch=VER ARM Processor interface:\n" .
+ " ahb2 - AMBA2.0 interface.\n" .
+ " v6 - All ARM V6 extensions.\n" .
+ " excl - ARM V6 exclusive access\n" .
+ " extensions only.\n" .
+ " unalign - ARM V6 unaligned and byte-\n" .
+ " strobed access extensions\n" .
+ " only.\n";
+ }
+
+ print " --datawidth=WIDTH Width of data bus ($DataWidths).\n" .
+ " --addrwidth=WIDTH Width of address bus ($MinAddrWidth..$MaxAddrWidth).\n" .
+ " --userwidth=WIDTH Width of user signals ($MinUserWidth..$MaxUserWidth).\n\n" .
+
+ " --OutputArb=NAME Name of arbitration component\n" .
+ " (max $MaxNameLength characters).\n" .
+ " --OutputStage=NAME Name of output stage component\n" .
+ " (max $MaxNameLength characters).\n" .
+ " --MatrixDecode=NAME Name of address decoder component(s)\n" .
+ " (max $MaxNameLength characters).\n" .
+ " --InputStage=NAME Name of input stage component\n" .
+ " (max $MaxNameLength characters).\n" .
+ " --BusMatrix=NAME Name of top level entity\n" .
+ " (max $MaxNameLength characters).\n\n" .
+
+ " --ipxact Alos generates SPIRIT-2009 compatible IPXACT file.\n" .
+ " --verbose Prints run information.\n" .
+ " --help Prints this help.\n" .
+ " --srcdir=DIRNAME Directory name where source files are\n" .
+ " located (defaults to $SourceDir).\n" .
+ " --tgtdir=DIRNAME Directory name where RTL files will be\n" .
+ " generated (defaults to $TargetDir).\n" .
+ " --xmldir=DIRNAME Directory name where XML configuration\n" .
+ " files are located (defaults to $XmlDir).\n" .
+ " --ipxactsrcdir=DIRNAME Directory name where IPXact source files are\n" .
+ " located (defaults to $IPXactSourceDir).\n" .
+ " --ipxacttgtdir=DIRNAME Directory name where IPXact files will be\n" .
+ " generated (defaults to $IPXactTargetDir).\n" .
+ " --overwrite Overwrites existing bus matrix of the\n" .
+ " same name.\n" .
+ " --(no)timescales Adds or suppressed the '`timescale' directive in the rendered Verilog files.\n" .
+ " --check Disables file generation and just checks the\n" .
+ " XML configuration file.\n\n";
+
+ # Abort session with exit code = 0
+ exit (0);
+}
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/bin/lib/xmlparser.pm b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/bin/lib/xmlparser.pm
new file mode 100755
index 0000000000000000000000000000000000000000..c8b144c50dc07e9f9bc00eeb2d4d9cc03230c8ae
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/bin/lib/xmlparser.pm
@@ -0,0 +1,1393 @@
+# ------------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2006-2011,2017 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# ------------------------------------------------------------------------------
+# Version and Release Control Information:
+#
+# File Name : $RCSfile: xmlparser.pm,v $
+#
+# SVN Information
+#
+# Checked In : $Date: 2011-02-21 17:53:53 +0000 (Mon, 21 Feb 2011) $
+#
+# Revision : $Revision: 162121 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#
+# ------------------------------------------------------------------------------
+# Purpose : Parse XML file input and produce equivalent structure
+# hash array, which can be accessed via public methods.
+#
+# Requirements : Perl version 5.005 or later for thread safety
+#
+# Limitations : See the POD after the __END__ marker in this file. Try:
+#
+# pod2text xmlparser.pm | more
+#
+# ------------------------------------------------------------------------------
+
+eval "exec perl -w -S $0 $@" # -*- Perl -*-
+ if ($running_under_some_sh);
+ undef ($running_under_some_sh);
+
+# Declare module name
+package xmlparser;
+
+# Declare import modules and libraries
+require Exporter;
+use strict;
+use vars qw( $VERSION @ISA @EXPORT @EXPORT_OK %XmlNodeTree %XmlNodeTotals );
+
+# Declare public and private entities
+@ISA = qw( Exporter );
+
+@EXPORT = qw( ConfigureXmlParser
+ RunXmlParser
+ ListXmlHash
+ ChangeRelativePath
+ GetXmlNodeList
+ GetXmlValue
+ GetXmlName
+ %XmlNodeTotals
+ %XmlNodeTree );
+
+@EXPORT_OK = qw( %XmlNodeTree );
+
+$VERSION = 1.00;
+
+# Dummy 'lock' routine for non-threaded versions of Perl
+BEGIN {
+ if ( $] < 5.005 ) { eval "sub lock {}"; }
+}
+
+# ------------------------------------------------------------------------------
+
+# Script variables
+my $DebugMode = 0;
+my $RecursionDepth = 0;
+my $RecursionLimit = 25;
+my $ShowIds = 0;
+my $ShowWarnings = 1;
+my $Verbose = 1;
+my $Warnings = 0;
+
+# Relative access path, serviced by ChangeRelativePath() function
+my $RelativePath = '';
+
+# Node stack
+my @PathStack = ( 'ROOT' );
+my $PathLevel = 0;
+
+# Exportable global data structure and node counters (note that values and
+# attributes will be added dynamically when the XML file is parsed)
+%XmlNodeTree = ( ROOT => { ITEMS => {ELEMENTS => [], ATTRIBUTES => []} } );
+%XmlNodeTotals = ( TOTAL => 0, ELEMENTS => 0, ATTRIBUTES => 0 );
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: RunXmlParser - Extracts the multi-line value and fields
+# ------------------------------------------------------------------------------
+sub RunXmlParser {
+
+ # Passed parameter 1 is the XML filename
+ my $XmlFilename = shift;
+
+ # Local variable(s)
+ my $TextLine = '';
+ my $LineCount = 0;
+ my $LeadingSpace = 0;
+ my $Delimeter = '';
+ my $Before = '';
+ my $After = '';
+ my $Field = '';
+ my $Residue = '';
+ my $InContainer = 0;
+ my $GotHeader = 0;
+ my $HeaderMisaligned = 0;
+ my $ContainerType = '';
+ my $Element = '';
+ my $EmptyElement = 0;
+ my $InstanceId = 1;
+ my $Increment = 1;
+ my $CurrentPath = 'ROOT';
+ my $ParentPath = 'ROOT';
+ my $AttributeCount = 0;
+ my $ParseEnable = 1;
+ my ($JustFilename) = $XmlFilename =~ /([^\/]+)$/;
+
+ # Open the input file
+ open (INPUT_FILE, "<$XmlFilename") or
+ ReportError('Cannot open the specified file for reading');
+
+ print "Parsing the '$JustFilename' file...\n" if ( $Verbose );
+
+ # Process each line of the file
+ while ( $TextLine = <INPUT_FILE> ) {
+
+ # Increment line count
+ $LineCount++;
+
+ # Parse the line(s), when enabled
+ while ( $ParseEnable ) {
+
+ # Remove single line comments, leading or end-of-line whitespace,
+ # carriage returns, newlines and tab characters. Leading whitespace
+ # is tracked for checking the <?xml ...?> processing instruction
+ $TextLine =~ s/<!--.*-->//g;
+ $LeadingSpace = ( $TextLine =~ s/^\s+// ) ? 1 : 0;
+ $TextLine =~ s/\s*(\r|\n|\t)$//g;
+
+ # Only process lines that are not blank
+ unless ( $TextLine eq '' ) {
+
+ # Display line when in debug mode
+ if ( $DebugMode ) { printf "Line %-03d: '$TextLine'\n", $LineCount; }
+
+ # Reconstruct fields of text (from multiple lines), which are delimited
+ # by the reserved characters '<' and '>'. Store the extracted tokens
+ # in the same order as they are processed. A path stack is used to
+ # determine the name of the current container. All nodes found within
+ # the scope of the current container are stored in a keyed list (the
+ # node structure hash array)
+ if ( ($Delimeter) = $TextLine =~ /([<>])/ ) {
+
+ # Store the patterns before and after the delimeter
+ $Before = $`;
+ $After = $';
+
+ # Determine appropriate action for the '<' delimeter
+ if ( $Delimeter eq '<' ) {
+
+ # Terminate reconstruction of a value field?
+ if ( ! $InContainer ) {
+
+ # Terminate the reconstructed value by concatenating the string
+ # preceding the '<' delimeter and extracting any residual text
+ $Field = $Field . $Before;
+
+ unless ( $Field eq '' ) {
+ # Display the value when in debug mode
+ if ( $DebugMode ) { print "Value of '$Element' = '$Field'\n"; }
+
+ # Check and store the extracted value
+ CheckValue($Field, $LineCount);
+ $XmlNodeTree{$CurrentPath}{VALUE} = $Field;
+
+ # Clear the field ready for a new reconstruction
+ $Field = '';
+ }
+
+ # Change to the 'in-container' state
+ $InContainer = 1;
+ }
+
+ # Initiate reconstruction of a container field?
+ if ( $InContainer ) {
+
+ # Initiate reconstruction of a new container by storing it and
+ # testing for the closing delimeter. If found, then trim the
+ # field accordingly and extract any residual text, else pad
+ # the field to support multi-line reconstruction
+ $Field = $After;
+ if ( $Field =~ s/>(.*)$// ) {
+ $After = $1;
+ $Before = '';
+ $Delimeter = '>';
+ } else {
+ $Field = $Field . ' ';
+ }
+
+ # If '<?xml' is found then check the alignment of the field
+ unless ( $GotHeader ) {
+ if ( $TextLine =~ /<\?xml/ ) {
+ $HeaderMisaligned = ($LineCount > 1 or $LeadingSpace);
+ }
+ }
+
+ }
+ }
+
+ # Determine appropriate action for the '>' delimeter
+ if ( $Delimeter eq '>' ) {
+
+ # Determine action for this delimeter
+ if ( ! $InContainer ) {
+
+ # Initiate reconstruction of a new value by storing it and
+ # testing for the opening delimeter. If found, then trim the
+ # field accordingly and extract any residual text
+ $Field = $After;
+ if ( $Field =~ s/<(.*)$// ) { $Residue = '<' . $1; }
+
+ } else {
+
+ # Terminate the reconstructed container by concatenating the
+ # remaining portion and smartly formatting the field to simplify
+ # pattern-matching. Selectively extract and residual text
+ $Field = TidyXmlContainer($Field . $Before, $LineCount);
+ $Residue = ( $After ne '' ) ? '>' . $After : '';
+
+ # Display the container name when in debug mode
+ if ( $DebugMode ) { print "Container: '$Field'\n"; }
+
+ # Ignore blank fields when produced by the removal of
+ # multi-line comments
+ unless ( $Field eq '' ) {
+
+ # Check the 'wellformedness' of the reconstructed container
+ CheckWellformedXml($Field, $LineCount);
+
+ # Re-initialise the node reference increment
+ $Increment = 1;
+
+ # Determine container type from beginning of the field, and
+ # apply appropriate syntax checks
+ $ContainerType = substr($Field, 0, 1);
+ if ( $ContainerType eq '?' ) {
+
+ # Check processing instructions
+ if ( $Field =~ /^\?xml/ ) {
+ unless ( $GotHeader ) {
+ CheckXmlHeader($Field, $HeaderMisaligned);
+ $GotHeader = 1;
+ }
+ } else {
+ # Anything else is not supported
+ ReportError("Unsupported XML processing instruction starting on line $LineCount");
+ }
+
+ } elsif ( $ContainerType eq '!' ) {
+
+ # Check declarations
+ CheckDeclaration($Field, $LineCount);
+
+ } elsif ( $ContainerType =~ /[a-z_.\-\/]/i ) {
+
+ # Check elements
+ CheckElement($Field, $LineCount);
+
+ # Determine element sub-type
+ if ( $ContainerType ne '/' ) {
+
+ # Extract and remove the element name
+ $Field =~ s/([a-z0-9_:\.\-]+)\s?//i;
+ $Element = $1;
+
+ # Check if this is an empty element
+ $EmptyElement = ( $Field =~ /\/$/ ) ? 1 : 0;
+
+ # Determine the parent path and then post-increment the path stack pointer
+ $ParentPath = DetermineStructPath($PathLevel++);
+
+ # For this new element, determine its unique current path. If the key is
+ # unique, then initialise the item lists in the current node record
+ $InstanceId = 1;
+ while ( 1 ) {
+ $PathStack[$PathLevel] = sprintf("%s[%d]", $Element, $InstanceId++);
+ $CurrentPath = DetermineStructPath($PathLevel);
+ unless ( exists($XmlNodeTree{$CurrentPath}) ) {
+ $XmlNodeTree{$CurrentPath}{ITEMS}{ELEMENTS} = [];
+ $XmlNodeTree{$CurrentPath}{ITEMS}{ATTRIBUTES} = [];
+ last;
+ }
+ }
+
+ # Display element name and path information when in debug mode
+ if ( $DebugMode ) {
+ printf "Element (%s): '%s'\nPUSH: Appending path: '%s', Parent path: '%s'\n",
+ $EmptyElement ? 'empty' : 'open', $PathStack[$PathLevel], $CurrentPath, $ParentPath;
+ }
+
+ # Update the item list of the parent node record
+ push ( @{ $XmlNodeTree{$ParentPath}{ITEMS}{ELEMENTS} }, $PathStack[$PathLevel] );
+
+ # Extract attributes and add the count to the node total
+ $AttributeCount = ExtractAttributes($Field, $CurrentPath);
+ $XmlNodeTotals{ATTRIBUTES} += $AttributeCount;
+
+ # Display number of extracted attributes when in debug mode
+ if ( $DebugMode ) {
+ unless ( $AttributeCount == 0 ) {
+ print "Extracted $AttributeCount attribute(s) from element '$PathStack[$PathLevel]'\n";
+ }
+ }
+
+ # Selectively decrement the path stack pointer and determine paths
+ if ( $EmptyElement ) {
+ $CurrentPath = DetermineStructPath(--$PathLevel);
+ $ParentPath = DetermineStructPath($PathLevel - 1);
+
+ # Display current and parent paths when in debug mode
+ if ( $DebugMode ) {
+ print "POP: Current path: '$CurrentPath', Parent path: '$ParentPath'\n";
+ }
+ }
+
+ } else {
+
+ # Decrement the node stack pointer and determine the paths
+ $CurrentPath = DetermineStructPath(--$PathLevel);
+ $ParentPath = DetermineStructPath($PathLevel - 1);
+
+ # Display paths when in debug mode
+ if ( $DebugMode ) {
+ print "POP: Current path: '$CurrentPath', Parent path: '$ParentPath'\n";
+ }
+
+ # Disable the node reference increment for closed elements
+ $Increment = 0;
+
+ }
+
+ } else {
+ # Any other type of field is not supported
+ ReportError("Unrecognised or illegal XML field starting on line $LineCount");
+ }
+
+ # Increment the node counts
+ $XmlNodeTotals{ELEMENTS} += $Increment;
+ $XmlNodeTotals{TOTAL}++;
+
+ # Clear the field ready for a new reconstruction and change to
+ # the 'in-value' state
+ $Field = '';
+ $InContainer = 0;
+ }
+
+ }
+ }
+
+ } else {
+ # Continue to build the field from multiple lines
+ $Field = $Field . $TextLine;
+ }
+
+ }
+
+ # If a second pass is required to process any residual text from the
+ # first attempt then remain in this loop, else exit the parsing loop
+ if ( $Residue ne '' ) {
+ # Display residual text when in debug mode
+ if ( $DebugMode ) { print "Residue: '$Residue'\n"; }
+ $TextLine = $Residue;
+ $Residue = '';
+ } else {
+ $ParseEnable = 0;
+ }
+ }
+
+ # Re-enable parsing for a fresh line of text
+ $ParseEnable = 1;
+ }
+
+ # Check that the root node is properly terminated upon the EOF
+ if ( $PathLevel != 0 ) {
+ ReportError('Unexpected end-of-file due to a syntax error');
+ }
+
+ # Close the XML file
+ close (INPUT_FILE);
+
+ # Display node totals when in verbose mode
+ if ( $Verbose ) {
+ printf "Processed %d line(s) with %d warning(s) - extracted %d XML node(s) [%d, @%d]...\n",
+ $LineCount, $Warnings, $XmlNodeTotals{TOTAL},
+ $XmlNodeTotals{ELEMENTS}, $XmlNodeTotals{ATTRIBUTES};
+ }
+}
+
+
+# ------------------------------------------------------------------------------
+# TidyXmlContainer - Apply intelligent text formatting to the container
+# ------------------------------------------------------------------------------
+sub TidyXmlContainer {
+
+ # Passed parameter 1 is the container
+ my $Container = shift;
+ # Passed parameter 2 is the line number
+ my $LineNumber = shift;
+
+ # Local variable(s)
+ my $Field = '';
+ my $Quote = '';
+ my $Token = '';
+ my $InQuotes = 0;
+
+ # Check for illegal empty container
+ if ( $Container eq '' ) {
+ ReportError("Empty XML field starting on line $LineNumber");
+ }
+
+ # Remove multi-line comments and end-of-field or leading whitespace
+ $Container =~ s/^!--.*--$//;
+ $Container =~ s/^\s*//;
+ $Container =~ s/\s*$//g;
+
+ # If the container is an element with attributes, then process it with
+ # respect for embedded whitespace within quoted strings
+ $Field = $Container;
+ while ( ($Quote) = $Field =~ /[^=]+=\s*(['"]).*['"]/ ) {
+
+ # Selectively clear the container string for recomposition
+ if ( $InQuotes == 0 ) { $Container = ''; }
+
+ # Extract portions of the container between matching quote characters
+ # and process whitespace on alternate iterations
+ while ( $Field =~ s/([^$Quote]+)($Quote*)// ) {
+ $Token = $1 . $2;
+ unless ( $InQuotes % 1 ) {
+ $Token =~ s/\s+/ /g;
+ $Token =~ s/\s?=\s?/=/g;
+ }
+ $Container = $Container . $Token;
+ $InQuotes++;
+ }
+
+ }
+
+ return ($Container);
+}
+
+
+# ------------------------------------------------------------------------------
+# CheckWellformedXml - Check the 'wellformedness' of the container
+# ------------------------------------------------------------------------------
+sub CheckWellformedXml {
+
+ # Passed parameter 1 is the container
+ my $Container = shift;
+ # Passed parameter 2 is the line number
+ my $LineNumber = shift;
+
+ # Local variable(s)
+ my $BadProcInstr = ( $Container =~ /^\?/ and
+ $Container !~ /\?$/ ) ? 1 : 0;
+ my $BadDecl = ( $Container =~ /^\!/ and
+ $Container =~ /[\!\?\/]$/ ) ? 1 : 0;
+ my $BadOpenElement = ( $Container =~ /^[a-z_.\-]/i and
+ $Container !~ /\/?$/ ) ? 1 : 0;
+ my $BadCloseElement = ( $Container =~ /^\// and
+ $Container =~ /(=|\/$)/ ) ? 1 : 0;
+
+ # Check and display an error if invalid
+ if ( $BadProcInstr or $BadDecl or $BadOpenElement or $BadCloseElement ) {
+ ReportError("XML field starting on line $LineNumber is not well-formed");
+ }
+}
+
+
+# ------------------------------------------------------------------------------
+# CheckXmlHeader - Validate the <?xml ...?> header container
+# ------------------------------------------------------------------------------
+sub CheckXmlHeader {
+
+ # Passed parameter 1 is the header
+ my $Header = shift;
+ # Passed parameter 2 is the alignment error flag
+ my $Misaligned = shift;
+
+ # Local variable(s)
+ my $XMLVersion = '1.0 (default)';
+ my $XMLEncoding = 'iso-8859-1 (default)';
+ my $XMLMode = 'yes (default)';
+
+ # Announce the header check
+ print "Validating XML header...\n" if ( $Verbose );
+
+ # Check the mis-alignment flag
+ if ( $Misaligned ) {
+ ReportError("The '?xml' declaration must start on line 1, column 1");
+ }
+
+ # Check syntax of supported attributes
+ if ( ($Header !~ /^\?xml[\s\?]/) or
+ ($Header !~ /((version|encoding|standalone)=("[^"]+"|'[^']+'))*/) ) {
+ ReportError("Invalid '<?xml ...?>' processing instruction");
+ }
+
+ # Check version, encoding and standalone (mode) attributes
+ if ( $Header =~ /version=("[^"]+"|'[^']+')/ ) {
+ $XMLVersion = $1; $XMLVersion =~ s/["']//g;
+ if ($XMLVersion ne '1.0') {
+ ReportError('Unsupported XML version');
+ }
+ }
+ if ( $Header =~ /encoding=("[^"]+"|'[^']+')/ ) {
+ $XMLEncoding = $1; $XMLEncoding =~ s/["']//g;
+ if ( $XMLEncoding !~ /^(iso\-8859\-1|UTF\-8)$/ ) {
+ ReportError('Unsupported XML encoding');
+ }
+ }
+ if ( $Header =~ /standalone=("[^"]+"|'[^']+')/ ) {
+ $XMLMode = $1; $XMLMode =~ s/["']//g;
+ if ( $XMLMode !~ /(yes|no)\b/ ) {
+ ReportError('Unsupported standalone declaration');
+ }
+ }
+
+ # Display header settings
+ print "XML version '$XMLVersion', encoding '$XMLEncoding', standalone" .
+ " '$XMLMode'...\n" if ( $Verbose );
+}
+
+
+# ------------------------------------------------------------------------------
+# CheckDeclaration - Validate the <!... > declaration container
+# NOTE: This procedure needs further work if required
+# ------------------------------------------------------------------------------
+sub CheckDeclaration {
+
+ # Passed parameter 1 is the container
+ my $Container = shift;
+ # Passed parameter 2 is the line number
+ my $LineNumber = shift;
+
+ # Local variable(s)
+ my $DeclarationType = '';
+
+ # Check and display an error if invalid
+ if ( ($DeclarationType) = $Container !~ /^\!(DOCTYPE|ENTITY)\b/ ) {
+ ReportError("Unrecognised XML declaration starting on line $LineNumber");
+ }
+}
+
+
+# ------------------------------------------------------------------------------
+# CheckElement - Validate the element container
+# ------------------------------------------------------------------------------
+sub CheckElement {
+
+ # Passed parameter 1 is the container
+ my $Container = shift;
+ # Passed parameter 2 is the line number
+ my $LineNumber = shift;
+
+ # Local variable(s)
+ my $ElementName = '';
+ my $AttributeName = '';
+ my $AttributeValue = '';
+ my $StartQuote = '';
+ my $EndQuote = '';
+ my $ForbiddenQuote = '';
+ my %Names = ();
+
+ # Extract and remove the element name, then check it for illegal
+ # chacters
+ $Container =~ s/^\/?([^\s]+)\s?//;
+ $ElementName = $1;
+ if ( $ElementName =~ /[^a-z0-9_:\.\-]/i ) {
+ ReportError("XML element starting on line $LineNumber has an illegal name");
+ }
+
+ # If defined, check attributes of element fields. Extract, remove
+ # and test the LHS and RHS fields of '=' assignments in turn
+ while ( $Container =~ s/([^=]+)=(['"])// ) {
+
+ $AttributeName = $1; $StartQuote = $2;
+ $ForbiddenQuote = ($StartQuote eq '"') ? '"' : "'";
+
+ # Check the attribute name for illegal characters
+ if ( $AttributeName =~ /[^a-z0-9_:\.\-]/i ) {
+ ReportError("XML element starting on line $LineNumber has an illegal attribute name");
+ }
+ # Check the attribute name for duplicates and note unique ones
+ if ( exists($Names{$AttributeName}) ) {
+ ReportError("XML element starting on line $LineNumber has a duplicate attribute name");
+ }
+ $Names{$AttributeName} = ''; # Value unimportant for purpose
+
+ # Extract and remove the attribute value, restoring the container
+ # field appropriately for the next iteration
+ if ( $Container =~ s/([^=]+)// ) {
+ $AttributeValue = $1;
+ $AttributeValue =~ s/(['"])\s?([^'"]*)$//;
+ $EndQuote = $1; $Container = $2 . $Container;
+
+ # Check the attribute value for illegal characters
+ if ( $AttributeValue =~ /[<>$ForbiddenQuote]/ or
+ ($AttributeValue =~ /&/ and
+ $AttributeValue !~ /&(amp|lt|gt|apos|quot|\#[0-9]{3}|\#x[A-Fa-f0-9]{2});/) ) {
+ ReportError("XML element starting on line $LineNumber has an illegal attribute value");
+ }
+ # Check for misquoted attribute value
+ unless ( $StartQuote eq $EndQuote ) {
+ ReportError("XML element starting on line $LineNumber has a misquoted attribute value");
+ }
+ }
+
+ }
+}
+
+
+# ------------------------------------------------------------------------------
+# CheckValue - Check the XML value field for illegal characters
+# ------------------------------------------------------------------------------
+sub CheckValue {
+
+ # Passed parameter 1 is the value
+ my $Field = shift;
+ # Passed parameter 2 is the line number
+ my $LineNumber = shift;
+
+ # Local variable(s)
+ my $BadLTGT = ( $Field =~ /[<>]/ ) ? 1 : 0;
+ my $BadAmpersand = ( $Field =~ /&/ and
+ $Field !~ /&(amp|lt|gt|apos|quot|\#[0-9]{3}|\#x[A-Fa-f0-9]{2});/ ) ? 1 : 0;
+
+ # Check and display an error if invalid
+ if ( $BadLTGT or $BadAmpersand ) {
+ ReportError("XML value field starting on line $LineNumber contains illegal characters");
+ }
+}
+
+
+# ------------------------------------------------------------------------------
+# ExtractAttributes - Inspect and extract the attributes from elements
+# ------------------------------------------------------------------------------
+sub ExtractAttributes {
+
+ # Passed parameter 1 is the container
+ my $Container = shift;
+ # Passed parameter 2 is the current path
+ my $Path = shift;
+
+ # Local variable(s)
+ my $Attributes = 0;
+ my $AttributeName = '';
+ my $AttributeValue = '';
+
+ # If defined, check attributes of element fields. Extract, remove
+ # and test the LHS and RHS fields of '=' assignments in turn
+ while ( $Container =~ s/([^=]+)=['"]// ) {
+ # Store the attribute name
+ $AttributeName = $1;
+
+ # Extract and remove the attribute value, restoring the container
+ # field appropriately for the next iteration
+ if ( $Container =~ s/([^=]+)// ) {
+ $AttributeValue = $1;
+ $AttributeValue =~ s/['"]\s?([^'"]*)$//;
+ $Container = $1 . $Container;
+
+ # Update the item list in the current node record and then save
+ # both the attribute name and its value
+ push ( @{ $XmlNodeTree{$Path}{ITEMS}{ATTRIBUTES} }, $AttributeName );
+ $XmlNodeTree{$Path}{ATTRIBUTES}{$AttributeName} = $AttributeValue;
+ $Attributes++;
+ }
+ }
+
+ return ($Attributes);
+}
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: ListXmlHash - List contents of the structure, using safe recursion
+# ------------------------------------------------------------------------------
+sub ListXmlHash {
+
+ # Passed parameter 1 is the requested node start point
+ my $NodeKey = shift;
+
+ # Local variable(s)
+ my ($NodeName) = $NodeKey =~ /([^{]+)$/;;
+ my @NodeKeys = @{ $XmlNodeTree{$NodeKey}{ITEMS}{ELEMENTS} };
+ my $NodeValue = $XmlNodeTree{$NodeKey}{VALUE};
+ my $NodeItem = '';
+ my @Markup = ('', '@');
+
+ # Initially display the 'listing structure' message
+ if ( $RecursionDepth == 0 ) { print "Listing the data structure:\n\n"; }
+
+ # Remove the reference number from the node name
+ unless ( $ShowIds ) { $NodeName = GetXmlName($NodeName); }
+
+ # Display the element name and optional value
+ if ( not defined $NodeValue ) {
+ printf " %s- $NodeName\n", ' ' x ($RecursionDepth * 2);
+ } else {
+ printf " %s- $NodeName = '$NodeValue'\n", ' ' x ($RecursionDepth * 2);
+ }
+
+ # Selectively display attributes
+ foreach $NodeItem ( @{ $XmlNodeTree{$NodeKey}{ITEMS}{ATTRIBUTES} } ) {
+ printf " %s%s$NodeItem %s= '$XmlNodeTree{$NodeKey}{ATTRIBUTES}{$NodeItem}'\n",
+ ' ' x ($RecursionDepth * 2), $Markup[1 - $ShowIds], $Markup[$ShowIds];
+ }
+
+ # List content of the current node by recursion within limits
+ foreach $NodeItem ( @NodeKeys ) {
+ if ( ++$RecursionDepth > $RecursionLimit ) {
+ ReportError("Recursion depth of $RecursionLimit exceeded");
+ } else {
+ # Interrogate the next level of the hierarchy
+ ListXmlHash("$NodeKey}{$NodeItem");
+ }
+ $RecursionDepth--;
+ }
+}
+
+
+# ------------------------------------------------------------------------------
+# DetermineStructPath - Determine the structure path key
+# ------------------------------------------------------------------------------
+sub DetermineStructPath {
+
+ # Passed parameter 1 is the level
+ my $RequestedLevel = shift;
+
+ # Local variable(s)
+ my $LevelPointer = 0;
+ my $Result = 'ROOT';
+
+ # Build the path and remove the outermost pair of braces, else return
+ # the root node
+ if ( $RequestedLevel > 0 ) {
+ $Result = '';
+ while ( $LevelPointer <= $RequestedLevel ) {
+ $Result = $Result . '{' . $PathStack[$LevelPointer++] . '}';
+ }
+ $Result =~ s/(^{|}$)//g;
+ }
+
+ return ($Result);
+}
+
+
+# ------------------------------------------------------------------------------
+# 'TranslateXPath' - Translates the specified XPath into the nearest match
+# access key
+# ------------------------------------------------------------------------------
+sub TranslateXPath {
+
+ # Passed parameter 1 is the specified XPath
+ my $Path = shift;
+
+ # Local variable(s)
+ my @XPathTokens = [];
+ my $Token = '';
+ my $Key = '';
+ my $ResolvedPath = 'ROOT';
+
+ if ( $Path =~ s/^\/// ) {
+ # Determine the key lookup for absolute paths
+ @XPathTokens = split('/', $Path);
+ foreach $Token ( @XPathTokens ) {
+ foreach $Key ( @{ $XmlNodeTree{$ResolvedPath}{ITEMS}{ELEMENTS} } ) {
+ if ( $Key eq $Token or $Key =~ /$Token/ ) {
+ $ResolvedPath = $ResolvedPath . '}{' . $Key;
+ last;
+ }
+ }
+ }
+ $Path = $ResolvedPath;
+ } else {
+ ReportError('Unsupported or badly formed XPath');
+ }
+
+ # Display the translated access key when in debug mode
+ if ( $DebugMode ) { print "Key: '$Path'\n"; }
+
+ return ($Path);
+}
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: 'GetXmlName' - Returns the XML node name without uniquifier(s)
+# ------------------------------------------------------------------------------
+sub GetXmlName {
+
+ # Passed parameter 1 is the specified XML node
+ my $XmlNode = shift;
+
+ $XmlNode =~ s/\[\d+\]//g;
+
+ return ($XmlNode);
+}
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: 'ChangeRelativePath' - Sets and returns the relative path
+# ------------------------------------------------------------------------------
+sub ChangeRelativePath {
+
+ # Passed parameter 1 is the specified path stem
+ $RelativePath = shift;
+
+ return ($RelativePath);
+}
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: 'GetXmlNodeList' - Return child node list for the specified parent
+# node. Append '@' character to get attributes
+# ------------------------------------------------------------------------------
+sub GetXmlNodeList {
+
+ # Passed parameter 1 is the requested node
+ my $NodeKey = shift;
+
+ # Local variable(s)
+ my $NodeType = ( $NodeKey =~ s/@// ) ? 'ATTRIBUTES' : 'ELEMENTS';
+ my $ParentKey = '';
+ my $Key = '';
+ my $MatchNode = '';
+ my @Nodes = ();
+
+ # Determine nodename search or specific lookup
+ if ( $NodeKey =~ s/^\/\//\// ) {
+
+ # Translate the XPath, then split it into the parent key and search element
+ $ParentKey = TranslateXPath($NodeKey);
+ if ( $ParentKey =~ s/\}\{([a-z0-9\.\-\_]+)\[1\]$// ) { $MatchNode = $1; }
+
+ # Conditionally search for matching keys and store full paths of matches
+ unless ( $MatchNode eq '' or $NodeKey !~ /$MatchNode$/ ) {
+ foreach $Key ( @{ $XmlNodeTree{$ParentKey}{ITEMS}{$NodeType} } ) {
+ if ( $Key =~ /$MatchNode\[\d+\]/ ) { push @Nodes, "$ParentKey}{$Key"; }
+ }
+ }
+
+ } else { # Specific look-up
+
+ # Conditionally prepend the current relative path
+ unless ( $NodeKey =~ /^ROOT/ ) { $NodeKey = $RelativePath . $NodeKey; }
+
+ # Translate XPaths when specified
+ if ( $NodeKey =~ /\// ) { $NodeKey = TranslateXPath($NodeKey); }
+
+ # Lookup listing node if it exists
+ if ( exists($XmlNodeTree{$NodeKey}{ITEMS}{$NodeType}) ) {
+ @Nodes = @{ $XmlNodeTree{$NodeKey}{ITEMS}{$NodeType} };
+ } elsif ( $ShowWarnings ) {
+ ReportWarning('Unable to get node list due to non-existent access path');
+ }
+
+ }
+
+ # Display a list of nodes when in debug mode
+ if ( $DebugMode ) { foreach $Key ( @Nodes) { print "List node: '$Key'\n"; } }
+
+ return ( @Nodes );
+}
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: 'GetXmlValue' - Extract the value of the specified element.
+# Prepend '@' character before name to get attributes
+# ------------------------------------------------------------------------------
+sub GetXmlValue {
+
+ # Passed parameter 1 is the requested node start point
+ my $NodeKey = shift;
+
+ # Local variable(s)
+ my $Attribute = ( $NodeKey =~ s/@(.+)$// ) ? $1 : '';
+ my $Value = '';
+ my $NoValue = '';
+
+ # Conditionally prepend the current relative path
+ unless ( $NodeKey =~ /^ROOT/ ) { $NodeKey = $RelativePath . $NodeKey; }
+
+ # Translate XPaths when specified
+ if ( $NodeKey =~ /\// ) { $NodeKey = TranslateXPath($NodeKey); }
+
+ # Lookup the value or attribute node if it exists. It must be coded like this
+ # to avoid non-existent keys from being incorrectly added to the hash as a
+ # side effect of the 'exists()' function
+ if ( exists($XmlNodeTree{$NodeKey}) ) {
+ # Now check and extract the element or attribute value
+ if ( $Attribute ne '' ) {
+ if ( exists($XmlNodeTree{$NodeKey}{ATTRIBUTES}{$Attribute}) ) {
+ $Value = $XmlNodeTree{$NodeKey}{ATTRIBUTES}{$Attribute};
+ unless ( defined($Value) ) { $Value = $NoValue; }
+ } elsif ( $ShowWarnings ) {
+ ReportWarning('Access attempted to a non-existent attribute name');
+ }
+ } else {
+ $Value = exists( $XmlNodeTree{$NodeKey}{VALUE} ) ?
+ $XmlNodeTree{$NodeKey}{VALUE} : $NoValue;
+ }
+ } elsif ( $ShowWarnings ) {
+ ReportWarning("Access attempted to a non-existent element '$NodeKey'");
+ }
+
+ # Perform substitution of ampersand fields
+ if ( $Value =~ /&(quot|apos|lt|gt|amp|#x?[A-Fa-f0-9]+);/ ) {
+ $Value =~ s/"/"/g;
+ $Value =~ s/'/'/g;
+ $Value =~ s/</</g;
+ $Value =~ s/>/>/g;
+ $Value =~ s/&/&/g;
+ $Value =~ s/&#([A-Fa-f0-9]{3});/chr( scalar $1 )/ge; # Only UTF-8!
+ $Value =~ s/&#x([A-Fa-f0-9]{2});/chr( hex( scalar $1 ) )/ge; # Only UTF-8!
+ }
+
+ return ( $Value );
+}
+
+
+# ------------------------------------------------------------------------------
+# PUBLIC: 'ConfigureXmlParser' - Configure aspects of module behaviour
+# ------------------------------------------------------------------------------
+sub ConfigureXmlParser {
+
+ # Passed parameter 1 is the hash array of options
+ my %XmlParserOptions = @_;
+
+ # Local variable(s)
+ my @Keys = keys( %XmlParserOptions );
+ my $Item = '';
+ my $Result = 0;
+
+ # Extract values and execute requested actions
+ foreach $Item ( @Keys ) {
+ if ($Item eq 'debug_mode' and $XmlParserOptions{$Item} ) {
+ $DebugMode = 1;
+ } elsif ( $Item eq 'recursion_limit' and $XmlParserOptions{$Item} > 0 ) {
+ $RecursionLimit = $XmlParserOptions{$Item};
+ } elsif ( $Item eq 'reset' and $XmlParserOptions{$Item} ) {
+ %XmlNodeTree = ( ROOT => { ITEMS => {ELEMENTS => [], ATTRIBUTES => []} } );
+ %XmlNodeTotals = ( TOTAL => 0, ELEMENTS => 0, ATTRIBUTES => 0 );
+ @PathStack = ( 'ROOT' );
+ $PathLevel = 0;
+ $RelativePath = '';
+ } elsif ( $Item eq 'show_ids' ) {
+ $ShowIds = ( $XmlParserOptions{$Item} ) ? 1 : 0;
+ } elsif ( $Item eq 'show_warnings' ) {
+ $ShowWarnings = ( ! $XmlParserOptions{$Item} ) ? 0 : 1;
+ } elsif ( $Item eq 'verbose' ) {
+ $Verbose = ( $XmlParserOptions{$Item} ) ? 1 : 0;
+ } else {
+ $Result = 1; # Flag a return code error
+ }
+ }
+ return ( $Result );
+}
+
+
+# ------------------------------------------------------------------------------
+# ReportError - Reports an error message on STDOUT and forces exit(1)
+# ------------------------------------------------------------------------------
+sub ReportError {
+
+ # Passed parameter 1 is the error message
+ my $ErrorMessage = shift;
+
+ print "ERROR (xmlparser): $ErrorMessage - aborting!\n\n";
+ exit 1;
+}
+
+
+# ------------------------------------------------------------------------------
+# ReportWarning - Reports a warning message on STDOUT
+# ------------------------------------------------------------------------------
+sub ReportWarning {
+
+ # Passed parameter 1 is the warning message
+ my $WarningMessage = shift;
+
+ print "WARNING (xmlparser): $WarningMessage!\n\n";
+ $Warnings++;
+}
+
+1;
+
+__END__
+
+
+# ------------------------------------------------------------------------------
+# POD section (formatting is sensitive to blankline whitespace!)
+# ------------------------------------------------------------------------------
+
+=pod
+
+=head1 NAME
+
+xmlparser - Standalone XML parser with hash array output
+
+=head1 SYNOPSIS
+
+Example usage:
+
+ # Reference the module
+ use xmlparser;
+
+ # Configure parser options, parse the file and list its structure
+ ConfigureXmlParser( verbose => 0, reset => 1 );
+ RunXmlParser('my.xml');
+ ListXmlHash('ROOT');
+
+ # Access specific groups of elements
+ my @MyElements = GetXmlNodeList('/myxml/mynames');
+ my $Element = '';
+ my $Attribute = '';
+
+ foreach $Element ( @MyElements ) {
+ ChangeRelativePath('/myxml/mynames/');
+ printf "Element '%s'='%s'\n", GetXmlName($Element), GetXmlValue($Element);
+
+ foreach $Attribute ( GetXmlNodeList("\@$Element") ) {
+ ChangeRelativePath("/myxml/mynames/$Element/");
+ printf "Attribute '$Attribute'='%s'\n", GetXmlValue("\@$Attribute");
+ }
+ }
+
+=head1 DESCRIPTION
+
+In the absence of complete documentation, this section contains the
+best source of information.
+
+=head2 DOCUMENTATION
+
+Documentation about this module does not yet exist for developers
+within ARM Limited, but this section will provide essential clues
+to the usage.
+
+=head2 PRINCIPLES
+
+This multi-line parser will extract elements and value text separated
+by <tagged_delimeters>. XML directives and declarations are treated as
+exceptions and these values will not be added to the hash array.
+
+The parsing algorithm alternates between these two states:
+
+=over 3
+
+=item 1.
+
+ Accumulate value fields until detection of '<' character and
+ then change to the 'in-container' state.
+
+=item 2.
+
+ Accumulate element fields until detection of '>' character and
+ then change to the 'in-value' state if an end of element is detected.
+
+=back
+
+Upon successfully identifying the closing brace of an element field,
+a new item is added to the child element list at the current level of
+hierarchy. A new hash key, bearing the element name, is added and
+the new hierarchical path is pushed onto the stack. For hierarchical
+reference, the current path and parent path are updated. Attributes
+are extracted and placed into a separate key-value node, using the
+same principles. The parser changes state to accumulate text fields.
+Upon closure of the element container, i.e. the next opening brace,
+the accumulated text is assigned as the value of the current element.
+Also upon this event, the path stack is popped and hierarchical paths
+are re-evaluated. Every extracted field is checked for legal composition.
+Elements and attributes are checked for wellformedness.
+
+The following example will show the relationship:
+
+B<XML source:>
+
+ <cfgfile>
+ <my_element animal="dog"/>
+ <my_element>
+ cat
+ </my_element>
+ </cfgfile>
+
+B<Storage structure:>
+
+ my %XmlNodeTree = (
+ ROOT => {
+ ITEMS => {
+ ELEMENTS => [ cfgfile[1] ],
+ ATTRIBUTES => []
+ }
+ }
+ ROOT}{cfgfile[1] => {
+ ITEMS => {
+ ELEMENTS => [ my_element[1], my_element[2] ],
+ ATTRIBUTES => []
+ }
+ }
+ ROOT}{cfgfile[1]}{my_element[1] => {
+ ITEMS => {
+ ELEMENTS => [],
+ ATTRIBUTES => [ animal ]
+ }
+ ATTRIBUTES => {
+ animal => 'dog'
+ }
+ }
+ ROOT}{cfgfile[1]}{my_element[2] => {
+ ITEMS => {
+ ELEMENTS => [],
+ ATTRIBUTES => []
+ }
+ VALUE => 'cat'
+ }
+ );
+
+B<Extracted structure:>
+
+ - ROOT
+ - cfgfile
+ - my_element
+ @value = 'dog'
+ - my_element = 'cat'
+
+
+Note that data is stored in the hash array using a pseudo hierarchical
+method. This makes it very simple to use grep when needing to find
+specifically named elements.
+
+To interrogate the hash array, it is recommended to use the public
+access functions GetXmlNodes() and GetXmlValue(). These functions will
+translate a basic XPath notation into keys for hash access and perform
+substitution of escaped character sequences.
+
+=head1 FUNCTIONS
+
+Currently, there are only a few public methods available. This section
+describes each one.
+
+=head2 ConfigureXmlParser(<key-value pairs>)
+
+Use this procedure to modify the behaviour of the parser, e.g. to reset
+the hash array. It accepts the following key-value pairs, also shown in
+the above example:
+
+=over 3
+
+=item *
+
+debug_mode => <integer: 0|1> - show debugging information.
+
+=item *
+
+recursion_limit => <integer: 1..n> - for the B<ListXmlHash()> fn.
+
+=item *
+
+reset => <integer: 0|1> - resets the hash and stack.
+
+=item *
+
+verbose => <integer: 0|1> - modifies verbosity, e.g. quiet mode.
+
+=item *
+
+show_ids => <integer: 0|1> - shows actual hash keynames.
+
+=item *
+
+show_warnings => <integer: 0|1> - control reports of warnings.
+
+=back
+
+Further options may be added over time.
+
+=head2 RunXmlParser(<xml_filename>)
+
+Use this procedure to read in the specified XML file. Ensure that
+you reset the hash array before attempting to read another file - see
+B<ConifigureXmlParser()>.
+
+=head2 ListXmlHash(<starting_key>)
+
+Use this procedure to verify the extraction process. All data is
+contained under the B<'ROOT'> node, so this is often the only key
+that you should specify.
+
+=head2 ChangeRelativePath(<xpath or key>)
+
+This function sets the relative path to be prepended to the specified
+argument when calling the B<GetXmlNodeList()> and B<GetXmlValue()>
+public access functions. Building XPaths and keys is more managable
+this way.
+
+=head2 GetXmlNodeList(<xpath or key>)
+
+Use this function to obtain the list of child elements or a list of
+attributes under the specified hierarchical level. By specifying the
+'@' character in the XPath or at the end of the key, you can request
+attributes instead of elements. Access to a non-existent xpath or key
+will return a zero-item list.
+
+=head2 GetXmlValue(<xpath or key>)
+
+Use this function to obtain the value of the element or attribute
+under the specified hierarchical level. By specifying the '@' character
+at the start of the attribute name (i.e. the rightmost item in the
+XPath or key), you can request attributes instead of elements. Access
+to a non-existent xpath or key will return a zero-length string. Access
+to elements or attributes without value will return a zero-length string.
+
+The following 'escaped' characters will be substituted to their
+true ASCII character:
+
+=over 3
+
+=item *
+
+" -> "
+
+=item *
+
+' -> '
+
+=item *
+
+< -> <
+
+=item *
+
+> -> >
+
+=item *
+
+& -> &
+
+=item *
+
+&#x<2_hex_chars>; -> equivalent hexadecimal character
+
+=item *
+
+&#<3_dec_chars>; -> equivalent decimal character
+
+=back
+
+=head2 GetXmlName(<item string>)
+
+Removes the uniquifying index from the hash key item and returns the
+originally named item.
+
+=head2 Direct hash access
+
+Knowing the format of key structure will allow you to perform access
+to the hash array directly. You always need to know something about the
+information structure in order to specify an XPath or key. This is
+true even when letting XSLT do the work!
+
+With reference to the example shown above, to access the 2nd element,
+you would need to recreate this key:
+
+ # Direct access of an element
+ my $Value = $XmlNodeTree{'ROOT}{cfgfile[1]}{my_element[2]'}{VALUE};
+
+ # Direct access of an attribute
+ my $Attribute = $XmlNodeTree{'ROOT}{cfgfile[1]}{my_element[1]'}{ATTRIBUTES}{animal};
+
+
+To access the desired positional element without hardcoding the node
+keys, you could try resolving this through the appropriate ITEMS array
+which records the ordering of all child items at the access level.
+Examples of this are shown below:
+
+ # Set-up
+ use xmlparser; # Load the XML parser module
+ use xmlparser qw ( %XmlNodeTree ); # Request direct hash access
+
+ # Indirectly access the 2nd 'my_element' element
+ my $EI = $XmlNodeTree{'ROOT}{cfgfile[1]'}{ITEMS}{ELEMENTS}[1];
+ my $Value = $XmlNodeTree{"ROOT}{cfgfile[1]}{$EI"}{VALUE};
+
+ # Indirectly access the 1st attribute of the 1st element
+ my $EI = $XmlNodeTree{'ROOT}{cfgfile[1]'}{ITEMS}{ELEMENTS}[0];
+ my $AI = $XmlNodeTree{"ROOT}{cfgfile[1]}{$EI"}{ITEMS}{ATTRIBUTES}[0];
+ my $Value = $XmlNodeTree{"ROOT}{cfgfile[1]}{$EI"}{ATTRIBUTES}{$AI};
+
+As will be appreciated, this is quite complicated! Therefore it is
+better to use the public access functions for ease of use. Your choice.
+
+=head1 SUPPORT
+
+The following support issues are noted under this section.
+
+=head2 Regarding XML
+
+This is a lightweight parser, compliant to only a subset of the
+XML 1.0 standard. Namespaces are supported at a basic level, that
+is, the ':' character is permitted in element names. The following
+support issues are defined below:
+
+=over 3
+
+=item 1.
+
+The ENTITY declaration is not fully implemented and there is no
+preprocessor for expanding macros instantiated by the '&MyFile;'
+notation.
+
+=item 2.
+
+The DOCTYPE declaration is not fully implemented and there is no
+support for DTD or XML-Schema. Checks can be performed efficiently
+by writing a customised checking procedure within the PERL domain.
+
+=item 4.
+
+Only the '<?xml ?>' processing instruction is supported as far as
+basic validation.
+
+=item 5.
+
+Only character sets 'iso-8859-1' and 'UTF-8' are accepted in the
+header check.
+
+=item 6.
+
+Elements embedded in the <emphasis>middle</emphasis> of value fields,
+like the 'emphasis' tag you have just read, are not supported. It will
+truncate the text value and prepend the remainder to the value of the
+next element.
+
+=back
+
+=head2 Regarding XPath and XPointer
+
+The XPath facility of the public access functions is only a basic
+provision. It only translates very simple XPaths into access-key
+notation, and it does not support any of the XPath functions. The
+XPointer notation allows indexed dereferencing of specific elements.
+This is sufficient to get the values of elements and attributes.
+Some examples of XPath and XPointer interpretations are shown below:
+
+ '/myxml' = 'ROOT}{myxml[1]' # Absolute
+ '/myxml[1]' = 'ROOT}{myxml[1]'
+
+ 'myxml' = 'myxml[1]' # Relative
+ 'myxml[2] = 'myxml[2]'
+
+ '//myxml' = [ 'ROOT}{myxml[1]' 'ROOT}{myxml[2]' ... ] # Search
+
+Generally speaking, the relationship is to convert '/' characters into
+'}{' brace-pairs, and to assume the first item when resolving non-indexed
+references.
+
+=head1 STATUS
+
+This version (1.00) is the current initial version, dated 11th January 2007.
+
+=head1 SEE ALSO
+
+This is a customised standalone module. There are no references to other
+modules from the developers community. Information for developers may be
+obtained through internal ARM documentation.
+
+=head1 COPYRIGHT
+
+Copyright 2006 ARM Limited. All rights reserved <support@arm.com>
+
+This library is free software; you can redistribute it and/or modify it
+under the same terms as Perl itself. However, because this file is supplied
+to support licenced IP from ARM Limited, please carefully check the terms
+and conditions defined in your legal agreement with ARM Limited.
+
+=cut
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
new file mode 100644
index 0000000000000000000000000000000000000000..3be03d724a83977dbd28a467a36acbea27c04aab
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
@@ -0,0 +1,2 @@
+bin/BuildBusMatrix.pl -xmldir xml -cfg soclabs_ahb32_4x7.xml -ipxact -ipxactsrcdir=ipxact/src -ipxacttgtdir=ipxact/built -over -verbose >& soclabs_ahb32_4x7.log
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ccf604e836286f2121735615a00e0ecef87c3ff2
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
@@ -0,0 +1,4257 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the main top of soclabs_4x7_AhbMatrix -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name>soclabs_4x7_AhbMatrix</spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__adp</spirit:name>
+ <spirit:description>Slave port _adp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__adp_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_adp unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_adp</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__dma</spirit:name>
+ <spirit:description>Slave port _dma</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dma unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__dma2</spirit:name>
+ <spirit:description>Slave port _dma2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma2_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dma2 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__cpu</spirit:name>
+ <spirit:description>Slave port _cpu</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__cpu_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_cpu unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Master interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__rom1</spirit:name>
+ <spirit:description>Master port _rom1</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__rom1_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_rom1 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram2</spirit:name>
+ <spirit:description>Master port _ram2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram2_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram2 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram3</spirit:name>
+ <spirit:description>Master port _ram3</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram3_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram3 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__sys</spirit:name>
+ <spirit:description>Master port _sys</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sys_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_sys unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_sys</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram8</spirit:name>
+ <spirit:description>Master port _ram8</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram8_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram8 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram9</spirit:name>
+ <spirit:description>Master port _ram9</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram9_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram9 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__exp</spirit:name>
+ <spirit:description>Master port _exp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__exp_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_exp unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+
+ <spirit:remapStates>
+
+ <spirit:remapState>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+
+ </spirit:remapStates>
+
+ <spirit:addressSpaces>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__rom1_AS</spirit:name>
+ <spirit:description>_rom1 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_rom1_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_rom1_0x10000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram2_AS</spirit:name>
+ <spirit:description>_ram2 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram2_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_ram2_0x20000000_0x2fffffff</spirit:name>
+ <spirit:addressOffset>0x20000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram3_AS</spirit:name>
+ <spirit:description>_ram3 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram3_0x30000000_0x3fffffff</spirit:name>
+ <spirit:addressOffset>0x30000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__sys_AS</spirit:name>
+ <spirit:description>_sys address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_sys_0x40000000_0x5fffffff</spirit:name>
+ <spirit:addressOffset>0x40000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_sys_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram8_AS</spirit:name>
+ <spirit:description>_ram8 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram8_0x80000000_0x8fffffff</spirit:name>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram9_AS</spirit:name>
+ <spirit:description>_ram9 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram9_0x90000000_0x9fffffff</spirit:name>
+ <spirit:addressOffset>0x90000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__exp_AS</spirit:name>
+ <spirit:description>_exp address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_exp_0x60000000_0x7fffffff</spirit:name>
+ <spirit:addressOffset>0x60000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_exp_0xa0000000_0xdfffffff</spirit:name>
+ <spirit:addressOffset>0xa0000000</spirit:addressOffset>
+ <spirit:range>0x040000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__adp_MM</spirit:name>
+ <spirit:description>_adp memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__adp_remap_0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteTarget_Slave__adp_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__dma_MM</spirit:name>
+ <spirit:description>_dma memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__dma2_MM</spirit:name>
+ <spirit:description>_dma2 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__cpu_MM</spirit:name>
+ <spirit:description>_cpu memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description>soclabs_4x7_AhbMatrix bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>soclabs_4x7_AhbMatrix</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>2</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>3</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
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+ </spirit:vector>
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+ </spirit:wire>
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+ </spirit:vector>
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+ </spirit:wire>
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+ </spirit:wire>
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+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
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+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for soclabs_4x7_AhbMatrix</spirit:description>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description>soclabs_4x7_AhbMatrix</spirit:description>
+
+</spirit:component>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
new file mode 100644
index 0000000000000000000000000000000000000000..787baebc5ddfaf0707bde7aea78e3523bd60a121
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
@@ -0,0 +1,3902 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the AHB-Lite wrapper of soclabs_4x7_AhbMatrix_lite -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name>soclabs_4x7_AhbMatrix_lite</spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__adp</spirit:name>
+ <spirit:description>Slave port _adp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__adp_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__dma</spirit:name>
+ <spirit:description>Slave port _dma</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__dma2</spirit:name>
+ <spirit:description>Slave port _dma2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma2_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__cpu</spirit:name>
+ <spirit:description>Slave port _cpu</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__cpu_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Master interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__rom1</spirit:name>
+ <spirit:description>Master port _rom1</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__rom1_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram2</spirit:name>
+ <spirit:description>Master port _ram2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram2_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram3</spirit:name>
+ <spirit:description>Master port _ram3</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram3_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__sys</spirit:name>
+ <spirit:description>Master port _sys</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sys_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram8</spirit:name>
+ <spirit:description>Master port _ram8</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram8_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram9</spirit:name>
+ <spirit:description>Master port _ram9</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram9_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__exp</spirit:name>
+ <spirit:description>Master port _exp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__exp_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+
+ <spirit:remapStates>
+
+ <spirit:remapState>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+
+ </spirit:remapStates>
+
+ <spirit:addressSpaces>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__rom1_AS</spirit:name>
+ <spirit:description>_rom1 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_rom1_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_rom1_0x10000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram2_AS</spirit:name>
+ <spirit:description>_ram2 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram2_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_ram2_0x20000000_0x2fffffff</spirit:name>
+ <spirit:addressOffset>0x20000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram3_AS</spirit:name>
+ <spirit:description>_ram3 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram3_0x30000000_0x3fffffff</spirit:name>
+ <spirit:addressOffset>0x30000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__sys_AS</spirit:name>
+ <spirit:description>_sys address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_sys_0x40000000_0x5fffffff</spirit:name>
+ <spirit:addressOffset>0x40000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_sys_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram8_AS</spirit:name>
+ <spirit:description>_ram8 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram8_0x80000000_0x8fffffff</spirit:name>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram9_AS</spirit:name>
+ <spirit:description>_ram9 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram9_0x90000000_0x9fffffff</spirit:name>
+ <spirit:addressOffset>0x90000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__exp_AS</spirit:name>
+ <spirit:description>_exp address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_exp_0x60000000_0x7fffffff</spirit:name>
+ <spirit:addressOffset>0x60000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_exp_0xa0000000_0xdfffffff</spirit:name>
+ <spirit:addressOffset>0xa0000000</spirit:addressOffset>
+ <spirit:range>0x040000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__adp_MM</spirit:name>
+ <spirit:description>_adp memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__adp_remap_0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__adp_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__dma_MM</spirit:name>
+ <spirit:description>_dma memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__dma2_MM</spirit:name>
+ <spirit:description>_dma2 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__cpu_MM</spirit:name>
+ <spirit:description>_cpu memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description>soclabs_4x7_AhbMatrix_lite bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>soclabs_4x7_AhbMatrix_lite</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HADDR_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
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+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
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+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram3</spirit:name>
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+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
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+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
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+ <spirit:name>HWUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_adp</spirit:name>
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+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma2</spirit:name>
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+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for soclabs_4x7_AhbMatrix_lite</spirit:description>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description>soclabs_4x7_AhbMatrix_lite</spirit:description>
+
+</spirit:component>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
new file mode 100755
index 0000000000000000000000000000000000000000..f7280ffe8d3f0d5187368bab6ad257c8a818b10b
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
@@ -0,0 +1,1050 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the main top of <<bus_matrix_name>> -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name><<bus_matrix_name>></spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+//---------------------------------------- << start in >> ---------------------------------------
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave_<<si_name>></spirit:name>
+ <spirit:description>Slave port <<si_name>></spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave_<<si_name>>_MM"/>
+//---------------------------------------- << start out >> --------------------------------------
+//------------------------------------- << start connection >> ------------------------------------
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master_<<mi_name>>" spirit:opaque="true"/>
+//------------------------------------- << end connection >> --------------------------------------
+//---------------------------------------- << end out >> ----------------------------------------
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT<<si_name>></spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------- << start unalign >> -----------------------------
+
+ <!-- HUNALIGN<<si_name>> unmapped -->
+ <!-- HBSTRB<<si_name>> unmapped -->
+
+//----------------------------- << end unalign >> ------------------------------
+
+ <!-- HMASTER<<si_name>> unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP<<si_name>></spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+ </spirit:portMaps>
+ </spirit:busInterface>
+//----------------------------------------- << end in >> ----------------------------------------
+
+ <!--Master interfaces -->
+//---------------------------------------- << start out >> --------------------------------------
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>></spirit:name>
+ <spirit:description>Master port <<mi_name>></spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master_<<mi_name>>_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT<<mi_name>></spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------- << start unalign >> -----------------------------
+
+ <!-- HUNALIGN<<mi_name>> unmapped -->
+
+ <!-- HBSTRB<<mi_name>> unmapped -->
+
+//----------------------------- << end unalign >> ------------------------------
+
+ <!-- HMASTER<<mi_name>> unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP<<mi_name>></spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+ </spirit:portMaps>
+ </spirit:busInterface>
+//---------------------------------------- << end out >> ----------------------------------------
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+//--------------------------------- << start vendor_extension >> ---------------------------------
+//---------------------------------- << end vendor_extension >> ----------------------------------
+
+//---------------------------- << start remap_used >> -------------------------------
+ <spirit:remapStates>
+
+//---------------------------- << start remap_state_ipxact >> -------------------------------
+ <spirit:remapState>
+ <spirit:name><<remap_name>></spirit:name>
+ <spirit:description>Remap state <<remap_name>></spirit:description>
+ <spirit:remapPorts>
+//---------------------------- << start remap_bit_ipxact >> -------------------------------
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="<<top_remap_bit>>"><<top_remap_bitvalue>></spirit:remapPort>
+//---------------------------- << end remap_bit_ipxact >> -------------------------------
+ </spirit:remapPorts>
+ </spirit:remapState>
+//------------------------------ << end remap_state_ipxact >> -------------------------
+
+ </spirit:remapStates>
+
+//----------------------------- << end remap_used >> --------------------------------
+ <spirit:addressSpaces>
+//---------------------------------------- << start out >> ----------------------------------------
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_AS</spirit:name>
+ <spirit:description><<mi_name>> address space</spirit:description>
+ <spirit:range><<address_space_range>></spirit:range>
+ <spirit:width><<data_v>></spirit:width>
+ <spirit:segments>
+//---------------------------------------- << start segments >> ----------------------------------------
+ <spirit:segment>
+ <spirit:name><<mi_name>>_<<segment_name>></spirit:name>
+ <spirit:addressOffset><<segment_offset>></spirit:addressOffset>
+ <spirit:range><<segment_range>></spirit:range>
+ </spirit:segment>
+//---------------------------------------- << end segments >> ----------------------------------------
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+//---------------------------------------- << end out >> ----------------------------------------
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+//---------------------------------------- << start in >> ----------------------------------------
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave_<<si_name>>_MM</spirit:name>
+ <spirit:description><<si_name>> memory map</spirit:description>
+
+//----------------------------- << start addr_map_ipxact >> ---------------------------
+//----------------------------- << start addr_region_ipxact >> ------------------------
+//----------------------------- << start remap_static >> ------------------------
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master_<<mi_name>>"
+ spirit:segmentRef="<<mi_name>>_<<base_address>>_<<end_address>>">
+ <!-- Address_region <<address_map>> -->
+//---------------------------- << start remap_used >> -------------------------------
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_<<base_address>>_0_state_always_SM</spirit:name>
+//---------------------------- << end remap_used >> -------------------------------
+//---------------------------- << start no_remap_used >> -------------------------------
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_<<base_address>>_0_state_default_SM</spirit:name>
+//---------------------------- << end no_remap_used >> -------------------------------
+ <spirit:baseAddress><<base_address>></spirit:baseAddress>
+ </spirit:subspaceMap>
+
+//----------------------------- << end remap_static >> ------------------------
+//------------------------------ << end addr_region_ipxact >> -------------------------
+//----------------------------- << end addr_map_ipxact >> -----------------------------
+//---------------------------- << start remap_used >> -------------------------------
+//----------------------------- << start remap_state_ipxact >> -------------------------
+//----------------------------- << start addr_remap_and_normal_all_this_remap >> -------------------------
+ <spirit:memoryRemap spirit:state="<<remap_name>>">
+ <spirit:name>AHBLiteTarget_Slave_<<si_name>>_<<remap_name>>_remap_MM</spirit:name>
+ <spirit:description><<si_name>> <<remap_name>> remap</spirit:description>
+//----------------------------- << start remap_region_ipxact >> -----------------------
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master_<<mi_name>>"
+ spirit:segmentRef="<<mi_name>>_<<base_address>>_<<end_address>>">
+ <!-- <<region_type>> address_region <<address_map>> -->
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_<<base_address>>_0_state_<<remap_name>>_SM</spirit:name>
+ <spirit:baseAddress><<base_address>></spirit:baseAddress>
+ </spirit:subspaceMap>
+//------------------------------ << end remap_region_ipxact >> -------------------------
+ </spirit:memoryRemap>
+
+//----------------------------- << end addr_remap_and_normal_all_this_remap >> ---------------------------
+//----------------------------- << end remap_state_ipxact >> -------------------------
+//---------------------------- << end remap_used >> -------------------------------
+ </spirit:memoryMap>
+
+//----------------------------------------- << end in >> ------------------------------------------
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description><<bus_matrix_name>> bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName><<bus_matrix_name>></spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+//----------------------------------------- << start in >> ------------------------------------------
+ <spirit:port>
+ <spirit:name>HSEL<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<addr>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<prot>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------- << start unalign >> -----------------------------
+ <spirit:port>
+ <spirit:name>HUNALIGN<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBSTRB<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<bstrb>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+//----------------------------- << end unalign >> ------------------------------
+ <spirit:port>
+ <spirit:name>HMASTER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue><<in>></spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HAUSER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//----------------------------------------- << end in >> ----------------------------------------
+
+ <!-- Input signals of Master interfaces -->
+
+//----------------------------------------- << start out >> ----------------------------------------
+ <spirit:port>
+ <spirit:name>HRDATA<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<resp>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HRUSER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//----------------------------------------- << end out >> ----------------------------------------
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+//---------------------------------------- << start out >> --------------------------------------
+ <spirit:port>
+ <spirit:name>HSEL<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<addr>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<prot>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------- << start unalign >> -----------------------------
+ <spirit:port>
+ <spirit:name>HUNALIGN<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBSTRB<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<bstrb>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//----------------------------- << end unalign >> ------------------------------
+ <spirit:port>
+ <spirit:name>HMASTER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HAUSER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//---------------------------------------- << end out >> ----------------------------------------
+
+ <!-- Output signals of Slave interfaces -->
+
+//---------------------------------------- << start in >> ----------------------------------------
+ <spirit:port>
+ <spirit:name>HRDATA<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<resp>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HRUSER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//---------------------------------------- << end in >> ----------------------------------------
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for <<bus_matrix_name>></spirit:description>
+//-------------------------------------- << start file >> ---------------------------------------
+ <spirit:file>
+ <spirit:name><<verilog_to_ipxact_path>>/<<filename>>.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+//-------------------------------------- << start topfile >> ---------------------------------------
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+//-------------------------------------- << end topfile >> ---------------------------------------
+ </spirit:file>
+//--------------------------------------- << end file >> ----------------------------------------
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description><<bus_matrix_name>></spirit:description>
+
+</spirit:component>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
new file mode 100755
index 0000000000000000000000000000000000000000..7fe69e421c20e128ad9753d2b9ca4fc6952f0449
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
@@ -0,0 +1,921 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the AHB-Lite wrapper of <<component_name>> -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name><<component_name>></spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+//---------------------------------------- << start in >> ---------------------------------------
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave_<<si_name>></spirit:name>
+ <spirit:description>Slave port <<si_name>></spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave_<<si_name>>_MM"/>
+//---------------------------------------- << start out >> --------------------------------------
+//------------------------------------- << start connection >> ------------------------------------
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master_<<mi_name>>" spirit:opaque="true"/>
+//------------------------------------- << end connection >> --------------------------------------
+//---------------------------------------- << end out >> ----------------------------------------
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT<<si_name>></spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER<<si_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+ </spirit:portMaps>
+ </spirit:busInterface>
+//----------------------------------------- << end in >> ----------------------------------------
+
+ <!--Master interfaces -->
+//---------------------------------------- << start out >> --------------------------------------
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>></spirit:name>
+ <spirit:description>Master port <<mi_name>></spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master_<<mi_name>>_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT<<mi_name>></spirit:name>
+//---------------------------------------- << start excl >> -------------------------------------
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+//---------------------------------------- << end excl >> -------------------------------------
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER<<mi_name>></spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+//---------------------------------------- << end user >> ---------------------------------------
+ </spirit:portMaps>
+ </spirit:busInterface>
+//---------------------------------------- << end out >> ----------------------------------------
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+//--------------------------------- << start vendor_extension >> ---------------------------------
+//---------------------------------- << end vendor_extension >> ----------------------------------
+
+//---------------------------- << start remap_used >> -------------------------------
+ <spirit:remapStates>
+
+//---------------------------- << start remap_state_ipxact >> -------------------------------
+ <spirit:remapState>
+ <spirit:name><<remap_name>></spirit:name>
+ <spirit:description>Remap state <<remap_name>></spirit:description>
+ <spirit:remapPorts>
+//---------------------------- << start remap_bit_ipxact >> -------------------------------
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="<<top_remap_bit>>"><<top_remap_bitvalue>></spirit:remapPort>
+//---------------------------- << end remap_bit_ipxact >> -------------------------------
+ </spirit:remapPorts>
+ </spirit:remapState>
+//------------------------------ << end remap_state_ipxact >> -------------------------
+
+ </spirit:remapStates>
+
+//----------------------------- << end remap_used >> --------------------------------
+ <spirit:addressSpaces>
+//---------------------------------------- << start out >> ----------------------------------------
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_AS</spirit:name>
+ <spirit:description><<mi_name>> address space</spirit:description>
+ <spirit:range><<address_space_range>></spirit:range>
+ <spirit:width><<data_v>></spirit:width>
+ <spirit:segments>
+//---------------------------------------- << start segments >> ----------------------------------------
+ <spirit:segment>
+ <spirit:name><<mi_name>>_<<segment_name>></spirit:name>
+ <spirit:addressOffset><<segment_offset>></spirit:addressOffset>
+ <spirit:range><<segment_range>></spirit:range>
+ </spirit:segment>
+//---------------------------------------- << end segments >> ----------------------------------------
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+//---------------------------------------- << end out >> ----------------------------------------
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+//---------------------------------------- << start in >> ----------------------------------------
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave_<<si_name>>_MM</spirit:name>
+ <spirit:description><<si_name>> memory map</spirit:description>
+
+//----------------------------- << start addr_map_ipxact >> ---------------------------
+//----------------------------- << start addr_region_ipxact >> ------------------------
+//----------------------------- << start remap_static >> ------------------------
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master_<<mi_name>>"
+ spirit:segmentRef="<<mi_name>>_<<base_address>>_<<end_address>>">
+ <!-- Address_region <<address_map>> -->
+//---------------------------- << start remap_used >> -------------------------------
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_<<base_address>>_0_state_always_SM</spirit:name>
+//---------------------------- << end remap_used >> -------------------------------
+//---------------------------- << start no_remap_used >> -------------------------------
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_<<base_address>>_0_state_default_SM</spirit:name>
+//---------------------------- << end no_remap_used >> -------------------------------
+ <spirit:baseAddress><<base_address>></spirit:baseAddress>
+ </spirit:subspaceMap>
+
+//----------------------------- << end remap_static >> ------------------------
+//------------------------------ << end addr_region_ipxact >> -------------------------
+//----------------------------- << end addr_map_ipxact >> -----------------------------
+//---------------------------- << start remap_used >> -------------------------------
+//----------------------------- << start remap_state_ipxact >> -------------------------
+//----------------------------- << start addr_remap_and_normal_all_this_remap >> -------------------------
+ <spirit:memoryRemap spirit:state="<<remap_name>>">
+ <spirit:name>AHBLiteInitiator_Slave_<<si_name>>_<<remap_name>>_remap_MM</spirit:name>
+ <spirit:description><<si_name>> <<remap_name>> remap</spirit:description>
+//----------------------------- << start remap_region_ipxact >> -----------------------
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master_<<mi_name>>"
+ spirit:segmentRef="<<mi_name>>_<<base_address>>_<<end_address>>">
+ <!-- <<region_type>> address_region <<address_map>> -->
+ <spirit:name>AHBLiteTarget_Master_<<mi_name>>_<<base_address>>_0_state_<<remap_name>>_SM</spirit:name>
+ <spirit:baseAddress><<base_address>></spirit:baseAddress>
+ </spirit:subspaceMap>
+//------------------------------ << end remap_region_ipxact >> -------------------------
+ </spirit:memoryRemap>
+
+//----------------------------- << end addr_remap_and_normal_all_this_remap >> ---------------------------
+//----------------------------- << end remap_state_ipxact >> -------------------------
+//---------------------------- << end remap_used >> -------------------------------
+ </spirit:memoryMap>
+
+//----------------------------------------- << end in >> ------------------------------------------
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description><<component_name>> bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName><<component_name>></spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+//----------------------------------------- << start in >> ------------------------------------------
+ <spirit:port>
+ <spirit:name>HADDR<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<addr>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<prot>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HAUSER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//----------------------------------------- << end in >> ----------------------------------------
+
+ <!-- Input signals of Master interfaces -->
+
+//----------------------------------------- << start out >> ----------------------------------------
+ <spirit:port>
+ <spirit:name>HRDATA<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HRUSER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//----------------------------------------- << end out >> ----------------------------------------
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+//---------------------------------------- << start out >> --------------------------------------
+ <spirit:port>
+ <spirit:name>HSEL<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<addr>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<prot>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HAUSER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER<<mi_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//---------------------------------------- << end out >> ----------------------------------------
+
+ <!-- Output signals of Slave interfaces -->
+
+//---------------------------------------- << start in >> ----------------------------------------
+ <spirit:port>
+ <spirit:name>HRDATA<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<data>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << start user >> -------------------------------------
+ <spirit:port>
+ <spirit:name>HRUSER<<si_name>></spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left><<user>></spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+//---------------------------------------- << end user >> ---------------------------------------
+//---------------------------------------- << end in >> ----------------------------------------
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for <<component_name>></spirit:description>
+//-------------------------------------- << start file >> ---------------------------------------
+ <spirit:file>
+ <spirit:name><<verilog_to_ipxact_path>>/<<filename>>.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+//-------------------------------------- << start topfile >> ---------------------------------------
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+//-------------------------------------- << end topfile >> ---------------------------------------
+ </spirit:file>
+//--------------------------------------- << end file >> ----------------------------------------
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description><<component_name>></spirit:description>
+
+</spirit:component>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/soclabs_ahb32_4x7.log b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/soclabs_ahb32_4x7.log
new file mode 100644
index 0000000000000000000000000000000000000000..234a6205c3ad90614089c82f5f288702527e6ffc
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/soclabs_ahb32_4x7.log
@@ -0,0 +1,74 @@
+
+==============================================================
+= The confidential and proprietary information contained in this file may
+= only be used by a person authorised under and to the extent permitted
+= by a subsisting licensing agreement from Arm Limited or its affiliates.
+=
+= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
+= ALL RIGHTS RESERVED
+=
+= This entire notice must be reproduced on all copies of this file
+= and copies of this file may only be made by a person if such person is
+= permitted to do so under the terms of a subsisting license agreement
+= from Arm Limited or its affiliates.
+=
+= BuildBusMatrix.pl
+=
+= Run Date : 10/02/2023 10:12:02
+==============================================================
+
+Script accepted the following parameters:
+
+ - Configuration file : 'xml/soclabs_ahb32_4x7.xml'
+ - Top-level name : 'soclabs_4x7_AhbMatrix'
+ - Slave interfaces : 4
+ - Master interfaces : 7
+ - Architecture type : 'ahb2'
+ - Arbitration scheme : 'burst'
+ - Address map : user defined
+ - Connectivity mapping : _adp -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
+ _dma -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
+ _dma2 -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
+ _cpu -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9
+ - Connectivity type : full
+ - Routing data width : 32
+ - Routing address width : 32
+ - User signal width : 2
+ - Timescales : yes (default)
+ - Configuration directory : './verilog/built'
+ - Source directory : './verilog/src'
+ - IPXact target directory : 'ipxact/built'
+ - IPXact source directory : 'ipxact/src'
+ - Overwrite mode : enabled
+
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v' file...
+
+Deleting the 'ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml' file...
+Deleting the 'ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml' file...
+
+Creating the bus matrix variant...
+
+ - Rendering 'soclabs_4x7_AhbMatrix_lite.xml'
+ - Rendering 'soclabs_4x7_MatrixDecode_adp.v'
+ - Rendering 'soclabs_4x7_AhbMatrix.v'
+ - Rendering 'soclabs_4x7_MatrixDecode_dma2.v'
+ - Rendering 'soclabs_4x7_MasterInput.v'
+ - Rendering 'soclabs_4x7_AhbMatrix_lite.v'
+ - Rendering 'soclabs_4x7_MatrixDecode_dma.v'
+ - Rendering 'soclabs_4x7_SlaveOutput.v'
+ - Rendering 'soclabs_4x7_AhbMatrix_default_slave.v'
+ - Rendering 'soclabs_4x7_AhbMatrix.xml'
+ - Rendering 'soclabs_4x7_Arbiter.v'
+ - Rendering 'soclabs_4x7_MatrixDecode_cpu.v'
+
+Done!
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
new file mode 100644
index 0000000000000000000000000000000000000000..f08683229a182ee231c8fbbbbf7ebcb6cf19f758
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
@@ -0,0 +1,2151 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : BusMatrix is the top-level which connects together
+// the required Input Stages, MatrixDecodes, Output
+// Stages and Output Arbitration blocks.
+//
+// Supports the following configured options:
+//
+// - Architecture type 'ahb2',
+// - 4 slave ports (connecting to masters),
+// - 7 master ports (connecting to slaves),
+// - Routing address width of 32 bits,
+// - Routing data width of 32 bits,
+// - xUSER signal width of 2 bits,
+// - Arbiter type 'burst',
+// - Connectivity mapping:
+// S<0..3> -> M<0..6>,
+// - Connectivity type 'full'.
+//
+//------------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_AhbMatrix (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // System address remapping control
+ REMAP,
+
+ // Input port SI0 (inputs from master 0)
+ HSEL_adp,
+ HADDR_adp,
+ HTRANS_adp,
+ HWRITE_adp,
+ HSIZE_adp,
+ HBURST_adp,
+ HPROT_adp,
+ HMASTER_adp,
+ HWDATA_adp,
+ HMASTLOCK_adp,
+ HREADY_adp,
+ HAUSER_adp,
+ HWUSER_adp,
+
+ // Input port SI1 (inputs from master 1)
+ HSEL_dma,
+ HADDR_dma,
+ HTRANS_dma,
+ HWRITE_dma,
+ HSIZE_dma,
+ HBURST_dma,
+ HPROT_dma,
+ HMASTER_dma,
+ HWDATA_dma,
+ HMASTLOCK_dma,
+ HREADY_dma,
+ HAUSER_dma,
+ HWUSER_dma,
+
+ // Input port SI2 (inputs from master 2)
+ HSEL_dma2,
+ HADDR_dma2,
+ HTRANS_dma2,
+ HWRITE_dma2,
+ HSIZE_dma2,
+ HBURST_dma2,
+ HPROT_dma2,
+ HMASTER_dma2,
+ HWDATA_dma2,
+ HMASTLOCK_dma2,
+ HREADY_dma2,
+ HAUSER_dma2,
+ HWUSER_dma2,
+
+ // Input port SI3 (inputs from master 3)
+ HSEL_cpu,
+ HADDR_cpu,
+ HTRANS_cpu,
+ HWRITE_cpu,
+ HSIZE_cpu,
+ HBURST_cpu,
+ HPROT_cpu,
+ HMASTER_cpu,
+ HWDATA_cpu,
+ HMASTLOCK_cpu,
+ HREADY_cpu,
+ HAUSER_cpu,
+ HWUSER_cpu,
+
+ // Output port MI0 (inputs from slave 0)
+ HRDATA_rom1,
+ HREADYOUT_rom1,
+ HRESP_rom1,
+ HRUSER_rom1,
+
+ // Output port MI1 (inputs from slave 1)
+ HRDATA_ram2,
+ HREADYOUT_ram2,
+ HRESP_ram2,
+ HRUSER_ram2,
+
+ // Output port MI2 (inputs from slave 2)
+ HRDATA_ram3,
+ HREADYOUT_ram3,
+ HRESP_ram3,
+ HRUSER_ram3,
+
+ // Output port MI3 (inputs from slave 3)
+ HRDATA_sys,
+ HREADYOUT_sys,
+ HRESP_sys,
+ HRUSER_sys,
+
+ // Output port MI4 (inputs from slave 4)
+ HRDATA_ram8,
+ HREADYOUT_ram8,
+ HRESP_ram8,
+ HRUSER_ram8,
+
+ // Output port MI5 (inputs from slave 5)
+ HRDATA_ram9,
+ HREADYOUT_ram9,
+ HRESP_ram9,
+ HRUSER_ram9,
+
+ // Output port MI6 (inputs from slave 6)
+ HRDATA_exp,
+ HREADYOUT_exp,
+ HRESP_exp,
+ HRUSER_exp,
+
+ // Scan test dummy signals; not connected until scan insertion
+ SCANENABLE, // Scan Test Mode Enable
+ SCANINHCLK, // Scan Chain Input
+
+
+ // Output port MI0 (outputs to slave 0)
+ HSEL_rom1,
+ HADDR_rom1,
+ HTRANS_rom1,
+ HWRITE_rom1,
+ HSIZE_rom1,
+ HBURST_rom1,
+ HPROT_rom1,
+ HMASTER_rom1,
+ HWDATA_rom1,
+ HMASTLOCK_rom1,
+ HREADYMUX_rom1,
+ HAUSER_rom1,
+ HWUSER_rom1,
+
+ // Output port MI1 (outputs to slave 1)
+ HSEL_ram2,
+ HADDR_ram2,
+ HTRANS_ram2,
+ HWRITE_ram2,
+ HSIZE_ram2,
+ HBURST_ram2,
+ HPROT_ram2,
+ HMASTER_ram2,
+ HWDATA_ram2,
+ HMASTLOCK_ram2,
+ HREADYMUX_ram2,
+ HAUSER_ram2,
+ HWUSER_ram2,
+
+ // Output port MI2 (outputs to slave 2)
+ HSEL_ram3,
+ HADDR_ram3,
+ HTRANS_ram3,
+ HWRITE_ram3,
+ HSIZE_ram3,
+ HBURST_ram3,
+ HPROT_ram3,
+ HMASTER_ram3,
+ HWDATA_ram3,
+ HMASTLOCK_ram3,
+ HREADYMUX_ram3,
+ HAUSER_ram3,
+ HWUSER_ram3,
+
+ // Output port MI3 (outputs to slave 3)
+ HSEL_sys,
+ HADDR_sys,
+ HTRANS_sys,
+ HWRITE_sys,
+ HSIZE_sys,
+ HBURST_sys,
+ HPROT_sys,
+ HMASTER_sys,
+ HWDATA_sys,
+ HMASTLOCK_sys,
+ HREADYMUX_sys,
+ HAUSER_sys,
+ HWUSER_sys,
+
+ // Output port MI4 (outputs to slave 4)
+ HSEL_ram8,
+ HADDR_ram8,
+ HTRANS_ram8,
+ HWRITE_ram8,
+ HSIZE_ram8,
+ HBURST_ram8,
+ HPROT_ram8,
+ HMASTER_ram8,
+ HWDATA_ram8,
+ HMASTLOCK_ram8,
+ HREADYMUX_ram8,
+ HAUSER_ram8,
+ HWUSER_ram8,
+
+ // Output port MI5 (outputs to slave 5)
+ HSEL_ram9,
+ HADDR_ram9,
+ HTRANS_ram9,
+ HWRITE_ram9,
+ HSIZE_ram9,
+ HBURST_ram9,
+ HPROT_ram9,
+ HMASTER_ram9,
+ HWDATA_ram9,
+ HMASTLOCK_ram9,
+ HREADYMUX_ram9,
+ HAUSER_ram9,
+ HWUSER_ram9,
+
+ // Output port MI6 (outputs to slave 6)
+ HSEL_exp,
+ HADDR_exp,
+ HTRANS_exp,
+ HWRITE_exp,
+ HSIZE_exp,
+ HBURST_exp,
+ HPROT_exp,
+ HMASTER_exp,
+ HWDATA_exp,
+ HMASTLOCK_exp,
+ HREADYMUX_exp,
+ HAUSER_exp,
+ HWUSER_exp,
+
+ // Input port SI0 (outputs to master 0)
+ HRDATA_adp,
+ HREADYOUT_adp,
+ HRESP_adp,
+ HRUSER_adp,
+
+ // Input port SI1 (outputs to master 1)
+ HRDATA_dma,
+ HREADYOUT_dma,
+ HRESP_dma,
+ HRUSER_dma,
+
+ // Input port SI2 (outputs to master 2)
+ HRDATA_dma2,
+ HREADYOUT_dma2,
+ HRESP_dma2,
+ HRUSER_dma2,
+
+ // Input port SI3 (outputs to master 3)
+ HRDATA_cpu,
+ HREADYOUT_cpu,
+ HRESP_cpu,
+ HRUSER_cpu,
+
+ // Scan test dummy signals; not connected until scan insertion
+ SCANOUTHCLK // Scan Chain Output
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // System address remapping control
+ input [3:0] REMAP; // REMAP input
+
+ // Input port SI0 (inputs from master 0)
+ input HSEL_adp; // Slave Select
+ input [31:0] HADDR_adp; // Address bus
+ input [1:0] HTRANS_adp; // Transfer type
+ input HWRITE_adp; // Transfer direction
+ input [2:0] HSIZE_adp; // Transfer size
+ input [2:0] HBURST_adp; // Burst type
+ input [3:0] HPROT_adp; // Protection control
+ input [3:0] HMASTER_adp; // Master select
+ input [31:0] HWDATA_adp; // Write data
+ input HMASTLOCK_adp; // Locked Sequence
+ input HREADY_adp; // Transfer done
+ input [1:0] HAUSER_adp; // Address USER signals
+ input [1:0] HWUSER_adp; // Write-data USER signals
+
+ // Input port SI1 (inputs from master 1)
+ input HSEL_dma; // Slave Select
+ input [31:0] HADDR_dma; // Address bus
+ input [1:0] HTRANS_dma; // Transfer type
+ input HWRITE_dma; // Transfer direction
+ input [2:0] HSIZE_dma; // Transfer size
+ input [2:0] HBURST_dma; // Burst type
+ input [3:0] HPROT_dma; // Protection control
+ input [3:0] HMASTER_dma; // Master select
+ input [31:0] HWDATA_dma; // Write data
+ input HMASTLOCK_dma; // Locked Sequence
+ input HREADY_dma; // Transfer done
+ input [1:0] HAUSER_dma; // Address USER signals
+ input [1:0] HWUSER_dma; // Write-data USER signals
+
+ // Input port SI2 (inputs from master 2)
+ input HSEL_dma2; // Slave Select
+ input [31:0] HADDR_dma2; // Address bus
+ input [1:0] HTRANS_dma2; // Transfer type
+ input HWRITE_dma2; // Transfer direction
+ input [2:0] HSIZE_dma2; // Transfer size
+ input [2:0] HBURST_dma2; // Burst type
+ input [3:0] HPROT_dma2; // Protection control
+ input [3:0] HMASTER_dma2; // Master select
+ input [31:0] HWDATA_dma2; // Write data
+ input HMASTLOCK_dma2; // Locked Sequence
+ input HREADY_dma2; // Transfer done
+ input [1:0] HAUSER_dma2; // Address USER signals
+ input [1:0] HWUSER_dma2; // Write-data USER signals
+
+ // Input port SI3 (inputs from master 3)
+ input HSEL_cpu; // Slave Select
+ input [31:0] HADDR_cpu; // Address bus
+ input [1:0] HTRANS_cpu; // Transfer type
+ input HWRITE_cpu; // Transfer direction
+ input [2:0] HSIZE_cpu; // Transfer size
+ input [2:0] HBURST_cpu; // Burst type
+ input [3:0] HPROT_cpu; // Protection control
+ input [3:0] HMASTER_cpu; // Master select
+ input [31:0] HWDATA_cpu; // Write data
+ input HMASTLOCK_cpu; // Locked Sequence
+ input HREADY_cpu; // Transfer done
+ input [1:0] HAUSER_cpu; // Address USER signals
+ input [1:0] HWUSER_cpu; // Write-data USER signals
+
+ // Output port MI0 (inputs from slave 0)
+ input [31:0] HRDATA_rom1; // Read data bus
+ input HREADYOUT_rom1; // HREADY feedback
+ input [1:0] HRESP_rom1; // Transfer response
+ input [1:0] HRUSER_rom1; // Read-data USER signals
+
+ // Output port MI1 (inputs from slave 1)
+ input [31:0] HRDATA_ram2; // Read data bus
+ input HREADYOUT_ram2; // HREADY feedback
+ input [1:0] HRESP_ram2; // Transfer response
+ input [1:0] HRUSER_ram2; // Read-data USER signals
+
+ // Output port MI2 (inputs from slave 2)
+ input [31:0] HRDATA_ram3; // Read data bus
+ input HREADYOUT_ram3; // HREADY feedback
+ input [1:0] HRESP_ram3; // Transfer response
+ input [1:0] HRUSER_ram3; // Read-data USER signals
+
+ // Output port MI3 (inputs from slave 3)
+ input [31:0] HRDATA_sys; // Read data bus
+ input HREADYOUT_sys; // HREADY feedback
+ input [1:0] HRESP_sys; // Transfer response
+ input [1:0] HRUSER_sys; // Read-data USER signals
+
+ // Output port MI4 (inputs from slave 4)
+ input [31:0] HRDATA_ram8; // Read data bus
+ input HREADYOUT_ram8; // HREADY feedback
+ input [1:0] HRESP_ram8; // Transfer response
+ input [1:0] HRUSER_ram8; // Read-data USER signals
+
+ // Output port MI5 (inputs from slave 5)
+ input [31:0] HRDATA_ram9; // Read data bus
+ input HREADYOUT_ram9; // HREADY feedback
+ input [1:0] HRESP_ram9; // Transfer response
+ input [1:0] HRUSER_ram9; // Read-data USER signals
+
+ // Output port MI6 (inputs from slave 6)
+ input [31:0] HRDATA_exp; // Read data bus
+ input HREADYOUT_exp; // HREADY feedback
+ input [1:0] HRESP_exp; // Transfer response
+ input [1:0] HRUSER_exp; // Read-data USER signals
+
+ // Scan test dummy signals; not connected until scan insertion
+ input SCANENABLE; // Scan enable signal
+ input SCANINHCLK; // HCLK scan input
+
+
+ // Output port MI0 (outputs to slave 0)
+ output HSEL_rom1; // Slave Select
+ output [31:0] HADDR_rom1; // Address bus
+ output [1:0] HTRANS_rom1; // Transfer type
+ output HWRITE_rom1; // Transfer direction
+ output [2:0] HSIZE_rom1; // Transfer size
+ output [2:0] HBURST_rom1; // Burst type
+ output [3:0] HPROT_rom1; // Protection control
+ output [3:0] HMASTER_rom1; // Master select
+ output [31:0] HWDATA_rom1; // Write data
+ output HMASTLOCK_rom1; // Locked Sequence
+ output HREADYMUX_rom1; // Transfer done
+ output [1:0] HAUSER_rom1; // Address USER signals
+ output [1:0] HWUSER_rom1; // Write-data USER signals
+
+ // Output port MI1 (outputs to slave 1)
+ output HSEL_ram2; // Slave Select
+ output [31:0] HADDR_ram2; // Address bus
+ output [1:0] HTRANS_ram2; // Transfer type
+ output HWRITE_ram2; // Transfer direction
+ output [2:0] HSIZE_ram2; // Transfer size
+ output [2:0] HBURST_ram2; // Burst type
+ output [3:0] HPROT_ram2; // Protection control
+ output [3:0] HMASTER_ram2; // Master select
+ output [31:0] HWDATA_ram2; // Write data
+ output HMASTLOCK_ram2; // Locked Sequence
+ output HREADYMUX_ram2; // Transfer done
+ output [1:0] HAUSER_ram2; // Address USER signals
+ output [1:0] HWUSER_ram2; // Write-data USER signals
+
+ // Output port MI2 (outputs to slave 2)
+ output HSEL_ram3; // Slave Select
+ output [31:0] HADDR_ram3; // Address bus
+ output [1:0] HTRANS_ram3; // Transfer type
+ output HWRITE_ram3; // Transfer direction
+ output [2:0] HSIZE_ram3; // Transfer size
+ output [2:0] HBURST_ram3; // Burst type
+ output [3:0] HPROT_ram3; // Protection control
+ output [3:0] HMASTER_ram3; // Master select
+ output [31:0] HWDATA_ram3; // Write data
+ output HMASTLOCK_ram3; // Locked Sequence
+ output HREADYMUX_ram3; // Transfer done
+ output [1:0] HAUSER_ram3; // Address USER signals
+ output [1:0] HWUSER_ram3; // Write-data USER signals
+
+ // Output port MI3 (outputs to slave 3)
+ output HSEL_sys; // Slave Select
+ output [31:0] HADDR_sys; // Address bus
+ output [1:0] HTRANS_sys; // Transfer type
+ output HWRITE_sys; // Transfer direction
+ output [2:0] HSIZE_sys; // Transfer size
+ output [2:0] HBURST_sys; // Burst type
+ output [3:0] HPROT_sys; // Protection control
+ output [3:0] HMASTER_sys; // Master select
+ output [31:0] HWDATA_sys; // Write data
+ output HMASTLOCK_sys; // Locked Sequence
+ output HREADYMUX_sys; // Transfer done
+ output [1:0] HAUSER_sys; // Address USER signals
+ output [1:0] HWUSER_sys; // Write-data USER signals
+
+ // Output port MI4 (outputs to slave 4)
+ output HSEL_ram8; // Slave Select
+ output [31:0] HADDR_ram8; // Address bus
+ output [1:0] HTRANS_ram8; // Transfer type
+ output HWRITE_ram8; // Transfer direction
+ output [2:0] HSIZE_ram8; // Transfer size
+ output [2:0] HBURST_ram8; // Burst type
+ output [3:0] HPROT_ram8; // Protection control
+ output [3:0] HMASTER_ram8; // Master select
+ output [31:0] HWDATA_ram8; // Write data
+ output HMASTLOCK_ram8; // Locked Sequence
+ output HREADYMUX_ram8; // Transfer done
+ output [1:0] HAUSER_ram8; // Address USER signals
+ output [1:0] HWUSER_ram8; // Write-data USER signals
+
+ // Output port MI5 (outputs to slave 5)
+ output HSEL_ram9; // Slave Select
+ output [31:0] HADDR_ram9; // Address bus
+ output [1:0] HTRANS_ram9; // Transfer type
+ output HWRITE_ram9; // Transfer direction
+ output [2:0] HSIZE_ram9; // Transfer size
+ output [2:0] HBURST_ram9; // Burst type
+ output [3:0] HPROT_ram9; // Protection control
+ output [3:0] HMASTER_ram9; // Master select
+ output [31:0] HWDATA_ram9; // Write data
+ output HMASTLOCK_ram9; // Locked Sequence
+ output HREADYMUX_ram9; // Transfer done
+ output [1:0] HAUSER_ram9; // Address USER signals
+ output [1:0] HWUSER_ram9; // Write-data USER signals
+
+ // Output port MI6 (outputs to slave 6)
+ output HSEL_exp; // Slave Select
+ output [31:0] HADDR_exp; // Address bus
+ output [1:0] HTRANS_exp; // Transfer type
+ output HWRITE_exp; // Transfer direction
+ output [2:0] HSIZE_exp; // Transfer size
+ output [2:0] HBURST_exp; // Burst type
+ output [3:0] HPROT_exp; // Protection control
+ output [3:0] HMASTER_exp; // Master select
+ output [31:0] HWDATA_exp; // Write data
+ output HMASTLOCK_exp; // Locked Sequence
+ output HREADYMUX_exp; // Transfer done
+ output [1:0] HAUSER_exp; // Address USER signals
+ output [1:0] HWUSER_exp; // Write-data USER signals
+
+ // Input port SI0 (outputs to master 0)
+ output [31:0] HRDATA_adp; // Read data bus
+ output HREADYOUT_adp; // HREADY feedback
+ output [1:0] HRESP_adp; // Transfer response
+ output [1:0] HRUSER_adp; // Read-data USER signals
+
+ // Input port SI1 (outputs to master 1)
+ output [31:0] HRDATA_dma; // Read data bus
+ output HREADYOUT_dma; // HREADY feedback
+ output [1:0] HRESP_dma; // Transfer response
+ output [1:0] HRUSER_dma; // Read-data USER signals
+
+ // Input port SI2 (outputs to master 2)
+ output [31:0] HRDATA_dma2; // Read data bus
+ output HREADYOUT_dma2; // HREADY feedback
+ output [1:0] HRESP_dma2; // Transfer response
+ output [1:0] HRUSER_dma2; // Read-data USER signals
+
+ // Input port SI3 (outputs to master 3)
+ output [31:0] HRDATA_cpu; // Read data bus
+ output HREADYOUT_cpu; // HREADY feedback
+ output [1:0] HRESP_cpu; // Transfer response
+ output [1:0] HRUSER_cpu; // Read-data USER signals
+
+ // Scan test dummy signals; not connected until scan insertion
+ output SCANOUTHCLK; // Scan Chain Output
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // System address remapping control
+ wire [3:0] REMAP; // REMAP signal
+
+ // Input Port SI0
+ wire HSEL_adp; // Slave Select
+ wire [31:0] HADDR_adp; // Address bus
+ wire [1:0] HTRANS_adp; // Transfer type
+ wire HWRITE_adp; // Transfer direction
+ wire [2:0] HSIZE_adp; // Transfer size
+ wire [2:0] HBURST_adp; // Burst type
+ wire [3:0] HPROT_adp; // Protection control
+ wire [3:0] HMASTER_adp; // Master select
+ wire [31:0] HWDATA_adp; // Write data
+ wire HMASTLOCK_adp; // Locked Sequence
+ wire HREADY_adp; // Transfer done
+
+ wire [31:0] HRDATA_adp; // Read data bus
+ wire HREADYOUT_adp; // HREADY feedback
+ wire [1:0] HRESP_adp; // Transfer response
+ wire [1:0] HAUSER_adp; // Address USER signals
+ wire [1:0] HWUSER_adp; // Write-data USER signals
+ wire [1:0] HRUSER_adp; // Read-data USER signals
+
+ // Input Port SI1
+ wire HSEL_dma; // Slave Select
+ wire [31:0] HADDR_dma; // Address bus
+ wire [1:0] HTRANS_dma; // Transfer type
+ wire HWRITE_dma; // Transfer direction
+ wire [2:0] HSIZE_dma; // Transfer size
+ wire [2:0] HBURST_dma; // Burst type
+ wire [3:0] HPROT_dma; // Protection control
+ wire [3:0] HMASTER_dma; // Master select
+ wire [31:0] HWDATA_dma; // Write data
+ wire HMASTLOCK_dma; // Locked Sequence
+ wire HREADY_dma; // Transfer done
+
+ wire [31:0] HRDATA_dma; // Read data bus
+ wire HREADYOUT_dma; // HREADY feedback
+ wire [1:0] HRESP_dma; // Transfer response
+ wire [1:0] HAUSER_dma; // Address USER signals
+ wire [1:0] HWUSER_dma; // Write-data USER signals
+ wire [1:0] HRUSER_dma; // Read-data USER signals
+
+ // Input Port SI2
+ wire HSEL_dma2; // Slave Select
+ wire [31:0] HADDR_dma2; // Address bus
+ wire [1:0] HTRANS_dma2; // Transfer type
+ wire HWRITE_dma2; // Transfer direction
+ wire [2:0] HSIZE_dma2; // Transfer size
+ wire [2:0] HBURST_dma2; // Burst type
+ wire [3:0] HPROT_dma2; // Protection control
+ wire [3:0] HMASTER_dma2; // Master select
+ wire [31:0] HWDATA_dma2; // Write data
+ wire HMASTLOCK_dma2; // Locked Sequence
+ wire HREADY_dma2; // Transfer done
+
+ wire [31:0] HRDATA_dma2; // Read data bus
+ wire HREADYOUT_dma2; // HREADY feedback
+ wire [1:0] HRESP_dma2; // Transfer response
+ wire [1:0] HAUSER_dma2; // Address USER signals
+ wire [1:0] HWUSER_dma2; // Write-data USER signals
+ wire [1:0] HRUSER_dma2; // Read-data USER signals
+
+ // Input Port SI3
+ wire HSEL_cpu; // Slave Select
+ wire [31:0] HADDR_cpu; // Address bus
+ wire [1:0] HTRANS_cpu; // Transfer type
+ wire HWRITE_cpu; // Transfer direction
+ wire [2:0] HSIZE_cpu; // Transfer size
+ wire [2:0] HBURST_cpu; // Burst type
+ wire [3:0] HPROT_cpu; // Protection control
+ wire [3:0] HMASTER_cpu; // Master select
+ wire [31:0] HWDATA_cpu; // Write data
+ wire HMASTLOCK_cpu; // Locked Sequence
+ wire HREADY_cpu; // Transfer done
+
+ wire [31:0] HRDATA_cpu; // Read data bus
+ wire HREADYOUT_cpu; // HREADY feedback
+ wire [1:0] HRESP_cpu; // Transfer response
+ wire [1:0] HAUSER_cpu; // Address USER signals
+ wire [1:0] HWUSER_cpu; // Write-data USER signals
+ wire [1:0] HRUSER_cpu; // Read-data USER signals
+
+ // Output Port MI0
+ wire HSEL_rom1; // Slave Select
+ wire [31:0] HADDR_rom1; // Address bus
+ wire [1:0] HTRANS_rom1; // Transfer type
+ wire HWRITE_rom1; // Transfer direction
+ wire [2:0] HSIZE_rom1; // Transfer size
+ wire [2:0] HBURST_rom1; // Burst type
+ wire [3:0] HPROT_rom1; // Protection control
+ wire [3:0] HMASTER_rom1; // Master select
+ wire [31:0] HWDATA_rom1; // Write data
+ wire HMASTLOCK_rom1; // Locked Sequence
+ wire HREADYMUX_rom1; // Transfer done
+
+ wire [31:0] HRDATA_rom1; // Read data bus
+ wire HREADYOUT_rom1; // HREADY feedback
+ wire [1:0] HRESP_rom1; // Transfer response
+ wire [1:0] HAUSER_rom1; // Address USER signals
+ wire [1:0] HWUSER_rom1; // Write-data USER signals
+ wire [1:0] HRUSER_rom1; // Read-data USER signals
+
+ // Output Port MI1
+ wire HSEL_ram2; // Slave Select
+ wire [31:0] HADDR_ram2; // Address bus
+ wire [1:0] HTRANS_ram2; // Transfer type
+ wire HWRITE_ram2; // Transfer direction
+ wire [2:0] HSIZE_ram2; // Transfer size
+ wire [2:0] HBURST_ram2; // Burst type
+ wire [3:0] HPROT_ram2; // Protection control
+ wire [3:0] HMASTER_ram2; // Master select
+ wire [31:0] HWDATA_ram2; // Write data
+ wire HMASTLOCK_ram2; // Locked Sequence
+ wire HREADYMUX_ram2; // Transfer done
+
+ wire [31:0] HRDATA_ram2; // Read data bus
+ wire HREADYOUT_ram2; // HREADY feedback
+ wire [1:0] HRESP_ram2; // Transfer response
+ wire [1:0] HAUSER_ram2; // Address USER signals
+ wire [1:0] HWUSER_ram2; // Write-data USER signals
+ wire [1:0] HRUSER_ram2; // Read-data USER signals
+
+ // Output Port MI2
+ wire HSEL_ram3; // Slave Select
+ wire [31:0] HADDR_ram3; // Address bus
+ wire [1:0] HTRANS_ram3; // Transfer type
+ wire HWRITE_ram3; // Transfer direction
+ wire [2:0] HSIZE_ram3; // Transfer size
+ wire [2:0] HBURST_ram3; // Burst type
+ wire [3:0] HPROT_ram3; // Protection control
+ wire [3:0] HMASTER_ram3; // Master select
+ wire [31:0] HWDATA_ram3; // Write data
+ wire HMASTLOCK_ram3; // Locked Sequence
+ wire HREADYMUX_ram3; // Transfer done
+
+ wire [31:0] HRDATA_ram3; // Read data bus
+ wire HREADYOUT_ram3; // HREADY feedback
+ wire [1:0] HRESP_ram3; // Transfer response
+ wire [1:0] HAUSER_ram3; // Address USER signals
+ wire [1:0] HWUSER_ram3; // Write-data USER signals
+ wire [1:0] HRUSER_ram3; // Read-data USER signals
+
+ // Output Port MI3
+ wire HSEL_sys; // Slave Select
+ wire [31:0] HADDR_sys; // Address bus
+ wire [1:0] HTRANS_sys; // Transfer type
+ wire HWRITE_sys; // Transfer direction
+ wire [2:0] HSIZE_sys; // Transfer size
+ wire [2:0] HBURST_sys; // Burst type
+ wire [3:0] HPROT_sys; // Protection control
+ wire [3:0] HMASTER_sys; // Master select
+ wire [31:0] HWDATA_sys; // Write data
+ wire HMASTLOCK_sys; // Locked Sequence
+ wire HREADYMUX_sys; // Transfer done
+
+ wire [31:0] HRDATA_sys; // Read data bus
+ wire HREADYOUT_sys; // HREADY feedback
+ wire [1:0] HRESP_sys; // Transfer response
+ wire [1:0] HAUSER_sys; // Address USER signals
+ wire [1:0] HWUSER_sys; // Write-data USER signals
+ wire [1:0] HRUSER_sys; // Read-data USER signals
+
+ // Output Port MI4
+ wire HSEL_ram8; // Slave Select
+ wire [31:0] HADDR_ram8; // Address bus
+ wire [1:0] HTRANS_ram8; // Transfer type
+ wire HWRITE_ram8; // Transfer direction
+ wire [2:0] HSIZE_ram8; // Transfer size
+ wire [2:0] HBURST_ram8; // Burst type
+ wire [3:0] HPROT_ram8; // Protection control
+ wire [3:0] HMASTER_ram8; // Master select
+ wire [31:0] HWDATA_ram8; // Write data
+ wire HMASTLOCK_ram8; // Locked Sequence
+ wire HREADYMUX_ram8; // Transfer done
+
+ wire [31:0] HRDATA_ram8; // Read data bus
+ wire HREADYOUT_ram8; // HREADY feedback
+ wire [1:0] HRESP_ram8; // Transfer response
+ wire [1:0] HAUSER_ram8; // Address USER signals
+ wire [1:0] HWUSER_ram8; // Write-data USER signals
+ wire [1:0] HRUSER_ram8; // Read-data USER signals
+
+ // Output Port MI5
+ wire HSEL_ram9; // Slave Select
+ wire [31:0] HADDR_ram9; // Address bus
+ wire [1:0] HTRANS_ram9; // Transfer type
+ wire HWRITE_ram9; // Transfer direction
+ wire [2:0] HSIZE_ram9; // Transfer size
+ wire [2:0] HBURST_ram9; // Burst type
+ wire [3:0] HPROT_ram9; // Protection control
+ wire [3:0] HMASTER_ram9; // Master select
+ wire [31:0] HWDATA_ram9; // Write data
+ wire HMASTLOCK_ram9; // Locked Sequence
+ wire HREADYMUX_ram9; // Transfer done
+
+ wire [31:0] HRDATA_ram9; // Read data bus
+ wire HREADYOUT_ram9; // HREADY feedback
+ wire [1:0] HRESP_ram9; // Transfer response
+ wire [1:0] HAUSER_ram9; // Address USER signals
+ wire [1:0] HWUSER_ram9; // Write-data USER signals
+ wire [1:0] HRUSER_ram9; // Read-data USER signals
+
+ // Output Port MI6
+ wire HSEL_exp; // Slave Select
+ wire [31:0] HADDR_exp; // Address bus
+ wire [1:0] HTRANS_exp; // Transfer type
+ wire HWRITE_exp; // Transfer direction
+ wire [2:0] HSIZE_exp; // Transfer size
+ wire [2:0] HBURST_exp; // Burst type
+ wire [3:0] HPROT_exp; // Protection control
+ wire [3:0] HMASTER_exp; // Master select
+ wire [31:0] HWDATA_exp; // Write data
+ wire HMASTLOCK_exp; // Locked Sequence
+ wire HREADYMUX_exp; // Transfer done
+
+ wire [31:0] HRDATA_exp; // Read data bus
+ wire HREADYOUT_exp; // HREADY feedback
+ wire [1:0] HRESP_exp; // Transfer response
+ wire [1:0] HAUSER_exp; // Address USER signals
+ wire [1:0] HWUSER_exp; // Write-data USER signals
+ wire [1:0] HRUSER_exp; // Read-data USER signals
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Bus-switch input SI0
+ wire i_sel0; // HSEL signal
+ wire [31:0] i_addr0; // HADDR signal
+ wire [1:0] i_trans0; // HTRANS signal
+ wire i_write0; // HWRITE signal
+ wire [2:0] i_size0; // HSIZE signal
+ wire [2:0] i_burst0; // HBURST signal
+ wire [3:0] i_prot0; // HPROTS signal
+ wire [3:0] i_master0; // HMASTER signal
+ wire i_mastlock0; // HMASTLOCK signal
+ wire i_active0; // Active signal
+ wire i_held_tran0; // HeldTran signal
+ wire i_readyout0; // Readyout signal
+ wire [1:0] i_resp0; // Response signal
+ wire [1:0] i_auser0; // HAUSER signal
+
+ // Bus-switch input SI1
+ wire i_sel1; // HSEL signal
+ wire [31:0] i_addr1; // HADDR signal
+ wire [1:0] i_trans1; // HTRANS signal
+ wire i_write1; // HWRITE signal
+ wire [2:0] i_size1; // HSIZE signal
+ wire [2:0] i_burst1; // HBURST signal
+ wire [3:0] i_prot1; // HPROTS signal
+ wire [3:0] i_master1; // HMASTER signal
+ wire i_mastlock1; // HMASTLOCK signal
+ wire i_active1; // Active signal
+ wire i_held_tran1; // HeldTran signal
+ wire i_readyout1; // Readyout signal
+ wire [1:0] i_resp1; // Response signal
+ wire [1:0] i_auser1; // HAUSER signal
+
+ // Bus-switch input SI2
+ wire i_sel2; // HSEL signal
+ wire [31:0] i_addr2; // HADDR signal
+ wire [1:0] i_trans2; // HTRANS signal
+ wire i_write2; // HWRITE signal
+ wire [2:0] i_size2; // HSIZE signal
+ wire [2:0] i_burst2; // HBURST signal
+ wire [3:0] i_prot2; // HPROTS signal
+ wire [3:0] i_master2; // HMASTER signal
+ wire i_mastlock2; // HMASTLOCK signal
+ wire i_active2; // Active signal
+ wire i_held_tran2; // HeldTran signal
+ wire i_readyout2; // Readyout signal
+ wire [1:0] i_resp2; // Response signal
+ wire [1:0] i_auser2; // HAUSER signal
+
+ // Bus-switch input SI3
+ wire i_sel3; // HSEL signal
+ wire [31:0] i_addr3; // HADDR signal
+ wire [1:0] i_trans3; // HTRANS signal
+ wire i_write3; // HWRITE signal
+ wire [2:0] i_size3; // HSIZE signal
+ wire [2:0] i_burst3; // HBURST signal
+ wire [3:0] i_prot3; // HPROTS signal
+ wire [3:0] i_master3; // HMASTER signal
+ wire i_mastlock3; // HMASTLOCK signal
+ wire i_active3; // Active signal
+ wire i_held_tran3; // HeldTran signal
+ wire i_readyout3; // Readyout signal
+ wire [1:0] i_resp3; // Response signal
+ wire [1:0] i_auser3; // HAUSER signal
+
+ // Bus-switch SI0 to MI0 signals
+ wire i_sel0to0; // Routing selection signal
+ wire i_active0to0; // Active signal
+
+ // Bus-switch SI0 to MI1 signals
+ wire i_sel0to1; // Routing selection signal
+ wire i_active0to1; // Active signal
+
+ // Bus-switch SI0 to MI2 signals
+ wire i_sel0to2; // Routing selection signal
+ wire i_active0to2; // Active signal
+
+ // Bus-switch SI0 to MI3 signals
+ wire i_sel0to3; // Routing selection signal
+ wire i_active0to3; // Active signal
+
+ // Bus-switch SI0 to MI4 signals
+ wire i_sel0to4; // Routing selection signal
+ wire i_active0to4; // Active signal
+
+ // Bus-switch SI0 to MI5 signals
+ wire i_sel0to5; // Routing selection signal
+ wire i_active0to5; // Active signal
+
+ // Bus-switch SI0 to MI6 signals
+ wire i_sel0to6; // Routing selection signal
+ wire i_active0to6; // Active signal
+
+ // Bus-switch SI1 to MI0 signals
+ wire i_sel1to0; // Routing selection signal
+ wire i_active1to0; // Active signal
+
+ // Bus-switch SI1 to MI1 signals
+ wire i_sel1to1; // Routing selection signal
+ wire i_active1to1; // Active signal
+
+ // Bus-switch SI1 to MI2 signals
+ wire i_sel1to2; // Routing selection signal
+ wire i_active1to2; // Active signal
+
+ // Bus-switch SI1 to MI3 signals
+ wire i_sel1to3; // Routing selection signal
+ wire i_active1to3; // Active signal
+
+ // Bus-switch SI1 to MI4 signals
+ wire i_sel1to4; // Routing selection signal
+ wire i_active1to4; // Active signal
+
+ // Bus-switch SI1 to MI5 signals
+ wire i_sel1to5; // Routing selection signal
+ wire i_active1to5; // Active signal
+
+ // Bus-switch SI1 to MI6 signals
+ wire i_sel1to6; // Routing selection signal
+ wire i_active1to6; // Active signal
+
+ // Bus-switch SI2 to MI0 signals
+ wire i_sel2to0; // Routing selection signal
+ wire i_active2to0; // Active signal
+
+ // Bus-switch SI2 to MI1 signals
+ wire i_sel2to1; // Routing selection signal
+ wire i_active2to1; // Active signal
+
+ // Bus-switch SI2 to MI2 signals
+ wire i_sel2to2; // Routing selection signal
+ wire i_active2to2; // Active signal
+
+ // Bus-switch SI2 to MI3 signals
+ wire i_sel2to3; // Routing selection signal
+ wire i_active2to3; // Active signal
+
+ // Bus-switch SI2 to MI4 signals
+ wire i_sel2to4; // Routing selection signal
+ wire i_active2to4; // Active signal
+
+ // Bus-switch SI2 to MI5 signals
+ wire i_sel2to5; // Routing selection signal
+ wire i_active2to5; // Active signal
+
+ // Bus-switch SI2 to MI6 signals
+ wire i_sel2to6; // Routing selection signal
+ wire i_active2to6; // Active signal
+
+ // Bus-switch SI3 to MI0 signals
+ wire i_sel3to0; // Routing selection signal
+ wire i_active3to0; // Active signal
+
+ // Bus-switch SI3 to MI1 signals
+ wire i_sel3to1; // Routing selection signal
+ wire i_active3to1; // Active signal
+
+ // Bus-switch SI3 to MI2 signals
+ wire i_sel3to2; // Routing selection signal
+ wire i_active3to2; // Active signal
+
+ // Bus-switch SI3 to MI3 signals
+ wire i_sel3to3; // Routing selection signal
+ wire i_active3to3; // Active signal
+
+ // Bus-switch SI3 to MI4 signals
+ wire i_sel3to4; // Routing selection signal
+ wire i_active3to4; // Active signal
+
+ // Bus-switch SI3 to MI5 signals
+ wire i_sel3to5; // Routing selection signal
+ wire i_active3to5; // Active signal
+
+ // Bus-switch SI3 to MI6 signals
+ wire i_sel3to6; // Routing selection signal
+ wire i_active3to6; // Active signal
+
+ wire i_hready_mux__rom1; // Internal HREADYMUXM for MI0
+ wire i_hready_mux__ram2; // Internal HREADYMUXM for MI1
+ wire i_hready_mux__ram3; // Internal HREADYMUXM for MI2
+ wire i_hready_mux__sys; // Internal HREADYMUXM for MI3
+ wire i_hready_mux__ram8; // Internal HREADYMUXM for MI4
+ wire i_hready_mux__ram9; // Internal HREADYMUXM for MI5
+ wire i_hready_mux__exp; // Internal HREADYMUXM for MI6
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+ // Input stage for SI0
+ soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_0 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL_adp),
+ .HADDRS (HADDR_adp),
+ .HTRANSS (HTRANS_adp),
+ .HWRITES (HWRITE_adp),
+ .HSIZES (HSIZE_adp),
+ .HBURSTS (HBURST_adp),
+ .HPROTS (HPROT_adp),
+ .HMASTERS (HMASTER_adp),
+ .HMASTLOCKS (HMASTLOCK_adp),
+ .HREADYS (HREADY_adp),
+ .HAUSERS (HAUSER_adp),
+
+ // Internal Response
+ .active_ip (i_active0),
+ .readyout_ip (i_readyout0),
+ .resp_ip (i_resp0),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT_adp),
+ .HRESPS (HRESP_adp),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel0),
+ .addr_ip (i_addr0),
+ .auser_ip (i_auser0),
+ .trans_ip (i_trans0),
+ .write_ip (i_write0),
+ .size_ip (i_size0),
+ .burst_ip (i_burst0),
+ .prot_ip (i_prot0),
+ .master_ip (i_master0),
+ .mastlock_ip (i_mastlock0),
+ .held_tran_ip (i_held_tran0)
+
+ );
+
+
+ // Input stage for SI1
+ soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_1 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL_dma),
+ .HADDRS (HADDR_dma),
+ .HTRANSS (HTRANS_dma),
+ .HWRITES (HWRITE_dma),
+ .HSIZES (HSIZE_dma),
+ .HBURSTS (HBURST_dma),
+ .HPROTS (HPROT_dma),
+ .HMASTERS (HMASTER_dma),
+ .HMASTLOCKS (HMASTLOCK_dma),
+ .HREADYS (HREADY_dma),
+ .HAUSERS (HAUSER_dma),
+
+ // Internal Response
+ .active_ip (i_active1),
+ .readyout_ip (i_readyout1),
+ .resp_ip (i_resp1),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT_dma),
+ .HRESPS (HRESP_dma),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel1),
+ .addr_ip (i_addr1),
+ .auser_ip (i_auser1),
+ .trans_ip (i_trans1),
+ .write_ip (i_write1),
+ .size_ip (i_size1),
+ .burst_ip (i_burst1),
+ .prot_ip (i_prot1),
+ .master_ip (i_master1),
+ .mastlock_ip (i_mastlock1),
+ .held_tran_ip (i_held_tran1)
+
+ );
+
+
+ // Input stage for SI2
+ soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_2 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL_dma2),
+ .HADDRS (HADDR_dma2),
+ .HTRANSS (HTRANS_dma2),
+ .HWRITES (HWRITE_dma2),
+ .HSIZES (HSIZE_dma2),
+ .HBURSTS (HBURST_dma2),
+ .HPROTS (HPROT_dma2),
+ .HMASTERS (HMASTER_dma2),
+ .HMASTLOCKS (HMASTLOCK_dma2),
+ .HREADYS (HREADY_dma2),
+ .HAUSERS (HAUSER_dma2),
+
+ // Internal Response
+ .active_ip (i_active2),
+ .readyout_ip (i_readyout2),
+ .resp_ip (i_resp2),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT_dma2),
+ .HRESPS (HRESP_dma2),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel2),
+ .addr_ip (i_addr2),
+ .auser_ip (i_auser2),
+ .trans_ip (i_trans2),
+ .write_ip (i_write2),
+ .size_ip (i_size2),
+ .burst_ip (i_burst2),
+ .prot_ip (i_prot2),
+ .master_ip (i_master2),
+ .mastlock_ip (i_mastlock2),
+ .held_tran_ip (i_held_tran2)
+
+ );
+
+
+ // Input stage for SI3
+ soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_3 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL_cpu),
+ .HADDRS (HADDR_cpu),
+ .HTRANSS (HTRANS_cpu),
+ .HWRITES (HWRITE_cpu),
+ .HSIZES (HSIZE_cpu),
+ .HBURSTS (HBURST_cpu),
+ .HPROTS (HPROT_cpu),
+ .HMASTERS (HMASTER_cpu),
+ .HMASTLOCKS (HMASTLOCK_cpu),
+ .HREADYS (HREADY_cpu),
+ .HAUSERS (HAUSER_cpu),
+
+ // Internal Response
+ .active_ip (i_active3),
+ .readyout_ip (i_readyout3),
+ .resp_ip (i_resp3),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT_cpu),
+ .HRESPS (HRESP_cpu),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel3),
+ .addr_ip (i_addr3),
+ .auser_ip (i_auser3),
+ .trans_ip (i_trans3),
+ .write_ip (i_write3),
+ .size_ip (i_size3),
+ .burst_ip (i_burst3),
+ .prot_ip (i_prot3),
+ .master_ip (i_master3),
+ .mastlock_ip (i_mastlock3),
+ .held_tran_ip (i_held_tran3)
+
+ );
+
+
+ // Matrix decoder for SI0
+ soclabs_4x7_MatrixDecode_adp u_soclabs_4x7_matrixdecode_adp (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Internal address remapping control
+ .remapping_dec ( REMAP[0] ),
+
+ // Signals from Input stage SI0
+ .HREADYS (HREADY_adp),
+ .sel_dec (i_sel0),
+ .decode_addr_dec (i_addr0[31:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans0),
+
+ // Control/Response for Output Stage MI0
+ .active_dec0 (i_active0to0),
+ .readyout_dec0 (i_hready_mux__rom1),
+ .resp_dec0 (HRESP_rom1),
+ .rdata_dec0 (HRDATA_rom1),
+ .ruser_dec0 (HRUSER_rom1),
+
+ // Control/Response for Output Stage MI1
+ .active_dec1 (i_active0to1),
+ .readyout_dec1 (i_hready_mux__ram2),
+ .resp_dec1 (HRESP_ram2),
+ .rdata_dec1 (HRDATA_ram2),
+ .ruser_dec1 (HRUSER_ram2),
+
+ // Control/Response for Output Stage MI2
+ .active_dec2 (i_active0to2),
+ .readyout_dec2 (i_hready_mux__ram3),
+ .resp_dec2 (HRESP_ram3),
+ .rdata_dec2 (HRDATA_ram3),
+ .ruser_dec2 (HRUSER_ram3),
+
+ // Control/Response for Output Stage MI3
+ .active_dec3 (i_active0to3),
+ .readyout_dec3 (i_hready_mux__sys),
+ .resp_dec3 (HRESP_sys),
+ .rdata_dec3 (HRDATA_sys),
+ .ruser_dec3 (HRUSER_sys),
+
+ // Control/Response for Output Stage MI4
+ .active_dec4 (i_active0to4),
+ .readyout_dec4 (i_hready_mux__ram8),
+ .resp_dec4 (HRESP_ram8),
+ .rdata_dec4 (HRDATA_ram8),
+ .ruser_dec4 (HRUSER_ram8),
+
+ // Control/Response for Output Stage MI5
+ .active_dec5 (i_active0to5),
+ .readyout_dec5 (i_hready_mux__ram9),
+ .resp_dec5 (HRESP_ram9),
+ .rdata_dec5 (HRDATA_ram9),
+ .ruser_dec5 (HRUSER_ram9),
+
+ // Control/Response for Output Stage MI6
+ .active_dec6 (i_active0to6),
+ .readyout_dec6 (i_hready_mux__exp),
+ .resp_dec6 (HRESP_exp),
+ .rdata_dec6 (HRDATA_exp),
+ .ruser_dec6 (HRUSER_exp),
+
+ .sel_dec0 (i_sel0to0),
+ .sel_dec1 (i_sel0to1),
+ .sel_dec2 (i_sel0to2),
+ .sel_dec3 (i_sel0to3),
+ .sel_dec4 (i_sel0to4),
+ .sel_dec5 (i_sel0to5),
+ .sel_dec6 (i_sel0to6),
+
+ .active_dec (i_active0),
+ .HREADYOUTS (i_readyout0),
+ .HRESPS (i_resp0),
+ .HRUSERS (HRUSER_adp),
+ .HRDATAS (HRDATA_adp)
+
+ );
+
+
+ // Matrix decoder for SI1
+ soclabs_4x7_MatrixDecode_dma u_soclabs_4x7_matrixdecode_dma (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Signals from Input stage SI1
+ .HREADYS (HREADY_dma),
+ .sel_dec (i_sel1),
+ .decode_addr_dec (i_addr1[31:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans1),
+
+ // Control/Response for Output Stage MI0
+ .active_dec0 (i_active1to0),
+ .readyout_dec0 (i_hready_mux__rom1),
+ .resp_dec0 (HRESP_rom1),
+ .rdata_dec0 (HRDATA_rom1),
+ .ruser_dec0 (HRUSER_rom1),
+
+ // Control/Response for Output Stage MI1
+ .active_dec1 (i_active1to1),
+ .readyout_dec1 (i_hready_mux__ram2),
+ .resp_dec1 (HRESP_ram2),
+ .rdata_dec1 (HRDATA_ram2),
+ .ruser_dec1 (HRUSER_ram2),
+
+ // Control/Response for Output Stage MI2
+ .active_dec2 (i_active1to2),
+ .readyout_dec2 (i_hready_mux__ram3),
+ .resp_dec2 (HRESP_ram3),
+ .rdata_dec2 (HRDATA_ram3),
+ .ruser_dec2 (HRUSER_ram3),
+
+ // Control/Response for Output Stage MI3
+ .active_dec3 (i_active1to3),
+ .readyout_dec3 (i_hready_mux__sys),
+ .resp_dec3 (HRESP_sys),
+ .rdata_dec3 (HRDATA_sys),
+ .ruser_dec3 (HRUSER_sys),
+
+ // Control/Response for Output Stage MI4
+ .active_dec4 (i_active1to4),
+ .readyout_dec4 (i_hready_mux__ram8),
+ .resp_dec4 (HRESP_ram8),
+ .rdata_dec4 (HRDATA_ram8),
+ .ruser_dec4 (HRUSER_ram8),
+
+ // Control/Response for Output Stage MI5
+ .active_dec5 (i_active1to5),
+ .readyout_dec5 (i_hready_mux__ram9),
+ .resp_dec5 (HRESP_ram9),
+ .rdata_dec5 (HRDATA_ram9),
+ .ruser_dec5 (HRUSER_ram9),
+
+ // Control/Response for Output Stage MI6
+ .active_dec6 (i_active1to6),
+ .readyout_dec6 (i_hready_mux__exp),
+ .resp_dec6 (HRESP_exp),
+ .rdata_dec6 (HRDATA_exp),
+ .ruser_dec6 (HRUSER_exp),
+
+ .sel_dec0 (i_sel1to0),
+ .sel_dec1 (i_sel1to1),
+ .sel_dec2 (i_sel1to2),
+ .sel_dec3 (i_sel1to3),
+ .sel_dec4 (i_sel1to4),
+ .sel_dec5 (i_sel1to5),
+ .sel_dec6 (i_sel1to6),
+
+ .active_dec (i_active1),
+ .HREADYOUTS (i_readyout1),
+ .HRESPS (i_resp1),
+ .HRUSERS (HRUSER_dma),
+ .HRDATAS (HRDATA_dma)
+
+ );
+
+
+ // Matrix decoder for SI2
+ soclabs_4x7_MatrixDecode_dma2 u_soclabs_4x7_matrixdecode_dma2 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Signals from Input stage SI2
+ .HREADYS (HREADY_dma2),
+ .sel_dec (i_sel2),
+ .decode_addr_dec (i_addr2[31:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans2),
+
+ // Control/Response for Output Stage MI0
+ .active_dec0 (i_active2to0),
+ .readyout_dec0 (i_hready_mux__rom1),
+ .resp_dec0 (HRESP_rom1),
+ .rdata_dec0 (HRDATA_rom1),
+ .ruser_dec0 (HRUSER_rom1),
+
+ // Control/Response for Output Stage MI1
+ .active_dec1 (i_active2to1),
+ .readyout_dec1 (i_hready_mux__ram2),
+ .resp_dec1 (HRESP_ram2),
+ .rdata_dec1 (HRDATA_ram2),
+ .ruser_dec1 (HRUSER_ram2),
+
+ // Control/Response for Output Stage MI2
+ .active_dec2 (i_active2to2),
+ .readyout_dec2 (i_hready_mux__ram3),
+ .resp_dec2 (HRESP_ram3),
+ .rdata_dec2 (HRDATA_ram3),
+ .ruser_dec2 (HRUSER_ram3),
+
+ // Control/Response for Output Stage MI3
+ .active_dec3 (i_active2to3),
+ .readyout_dec3 (i_hready_mux__sys),
+ .resp_dec3 (HRESP_sys),
+ .rdata_dec3 (HRDATA_sys),
+ .ruser_dec3 (HRUSER_sys),
+
+ // Control/Response for Output Stage MI4
+ .active_dec4 (i_active2to4),
+ .readyout_dec4 (i_hready_mux__ram8),
+ .resp_dec4 (HRESP_ram8),
+ .rdata_dec4 (HRDATA_ram8),
+ .ruser_dec4 (HRUSER_ram8),
+
+ // Control/Response for Output Stage MI5
+ .active_dec5 (i_active2to5),
+ .readyout_dec5 (i_hready_mux__ram9),
+ .resp_dec5 (HRESP_ram9),
+ .rdata_dec5 (HRDATA_ram9),
+ .ruser_dec5 (HRUSER_ram9),
+
+ // Control/Response for Output Stage MI6
+ .active_dec6 (i_active2to6),
+ .readyout_dec6 (i_hready_mux__exp),
+ .resp_dec6 (HRESP_exp),
+ .rdata_dec6 (HRDATA_exp),
+ .ruser_dec6 (HRUSER_exp),
+
+ .sel_dec0 (i_sel2to0),
+ .sel_dec1 (i_sel2to1),
+ .sel_dec2 (i_sel2to2),
+ .sel_dec3 (i_sel2to3),
+ .sel_dec4 (i_sel2to4),
+ .sel_dec5 (i_sel2to5),
+ .sel_dec6 (i_sel2to6),
+
+ .active_dec (i_active2),
+ .HREADYOUTS (i_readyout2),
+ .HRESPS (i_resp2),
+ .HRUSERS (HRUSER_dma2),
+ .HRDATAS (HRDATA_dma2)
+
+ );
+
+
+ // Matrix decoder for SI3
+ soclabs_4x7_MatrixDecode_cpu u_soclabs_4x7_matrixdecode_cpu (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Internal address remapping control
+ .remapping_dec ( REMAP[0] ),
+
+ // Signals from Input stage SI3
+ .HREADYS (HREADY_cpu),
+ .sel_dec (i_sel3),
+ .decode_addr_dec (i_addr3[31:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans3),
+
+ // Control/Response for Output Stage MI0
+ .active_dec0 (i_active3to0),
+ .readyout_dec0 (i_hready_mux__rom1),
+ .resp_dec0 (HRESP_rom1),
+ .rdata_dec0 (HRDATA_rom1),
+ .ruser_dec0 (HRUSER_rom1),
+
+ // Control/Response for Output Stage MI1
+ .active_dec1 (i_active3to1),
+ .readyout_dec1 (i_hready_mux__ram2),
+ .resp_dec1 (HRESP_ram2),
+ .rdata_dec1 (HRDATA_ram2),
+ .ruser_dec1 (HRUSER_ram2),
+
+ // Control/Response for Output Stage MI2
+ .active_dec2 (i_active3to2),
+ .readyout_dec2 (i_hready_mux__ram3),
+ .resp_dec2 (HRESP_ram3),
+ .rdata_dec2 (HRDATA_ram3),
+ .ruser_dec2 (HRUSER_ram3),
+
+ // Control/Response for Output Stage MI3
+ .active_dec3 (i_active3to3),
+ .readyout_dec3 (i_hready_mux__sys),
+ .resp_dec3 (HRESP_sys),
+ .rdata_dec3 (HRDATA_sys),
+ .ruser_dec3 (HRUSER_sys),
+
+ // Control/Response for Output Stage MI4
+ .active_dec4 (i_active3to4),
+ .readyout_dec4 (i_hready_mux__ram8),
+ .resp_dec4 (HRESP_ram8),
+ .rdata_dec4 (HRDATA_ram8),
+ .ruser_dec4 (HRUSER_ram8),
+
+ // Control/Response for Output Stage MI5
+ .active_dec5 (i_active3to5),
+ .readyout_dec5 (i_hready_mux__ram9),
+ .resp_dec5 (HRESP_ram9),
+ .rdata_dec5 (HRDATA_ram9),
+ .ruser_dec5 (HRUSER_ram9),
+
+ // Control/Response for Output Stage MI6
+ .active_dec6 (i_active3to6),
+ .readyout_dec6 (i_hready_mux__exp),
+ .resp_dec6 (HRESP_exp),
+ .rdata_dec6 (HRDATA_exp),
+ .ruser_dec6 (HRUSER_exp),
+
+ .sel_dec0 (i_sel3to0),
+ .sel_dec1 (i_sel3to1),
+ .sel_dec2 (i_sel3to2),
+ .sel_dec3 (i_sel3to3),
+ .sel_dec4 (i_sel3to4),
+ .sel_dec5 (i_sel3to5),
+ .sel_dec6 (i_sel3to6),
+
+ .active_dec (i_active3),
+ .HREADYOUTS (i_readyout3),
+ .HRESPS (i_resp3),
+ .HRUSERS (HRUSER_cpu),
+ .HRDATAS (HRDATA_cpu)
+
+ );
+
+
+ // Output stage for MI0
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_0 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to0),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to0),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to0),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to0),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_rom1),
+
+ .active_op0 (i_active0to0),
+ .active_op1 (i_active1to0),
+ .active_op2 (i_active2to0),
+ .active_op3 (i_active3to0),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_rom1),
+ .HADDRM (HADDR_rom1),
+ .HAUSERM (HAUSER_rom1),
+ .HTRANSM (HTRANS_rom1),
+ .HWRITEM (HWRITE_rom1),
+ .HSIZEM (HSIZE_rom1),
+ .HBURSTM (HBURST_rom1),
+ .HPROTM (HPROT_rom1),
+ .HMASTERM (HMASTER_rom1),
+ .HMASTLOCKM (HMASTLOCK_rom1),
+ .HREADYMUXM (i_hready_mux__rom1),
+ .HWUSERM (HWUSER_rom1),
+ .HWDATAM (HWDATA_rom1)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_rom1 = i_hready_mux__rom1;
+
+
+ // Output stage for MI1
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_1 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to1),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to1),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to1),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to1),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_ram2),
+
+ .active_op0 (i_active0to1),
+ .active_op1 (i_active1to1),
+ .active_op2 (i_active2to1),
+ .active_op3 (i_active3to1),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_ram2),
+ .HADDRM (HADDR_ram2),
+ .HAUSERM (HAUSER_ram2),
+ .HTRANSM (HTRANS_ram2),
+ .HWRITEM (HWRITE_ram2),
+ .HSIZEM (HSIZE_ram2),
+ .HBURSTM (HBURST_ram2),
+ .HPROTM (HPROT_ram2),
+ .HMASTERM (HMASTER_ram2),
+ .HMASTLOCKM (HMASTLOCK_ram2),
+ .HREADYMUXM (i_hready_mux__ram2),
+ .HWUSERM (HWUSER_ram2),
+ .HWDATAM (HWDATA_ram2)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_ram2 = i_hready_mux__ram2;
+
+
+ // Output stage for MI2
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_2 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to2),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to2),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to2),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to2),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_ram3),
+
+ .active_op0 (i_active0to2),
+ .active_op1 (i_active1to2),
+ .active_op2 (i_active2to2),
+ .active_op3 (i_active3to2),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_ram3),
+ .HADDRM (HADDR_ram3),
+ .HAUSERM (HAUSER_ram3),
+ .HTRANSM (HTRANS_ram3),
+ .HWRITEM (HWRITE_ram3),
+ .HSIZEM (HSIZE_ram3),
+ .HBURSTM (HBURST_ram3),
+ .HPROTM (HPROT_ram3),
+ .HMASTERM (HMASTER_ram3),
+ .HMASTLOCKM (HMASTLOCK_ram3),
+ .HREADYMUXM (i_hready_mux__ram3),
+ .HWUSERM (HWUSER_ram3),
+ .HWDATAM (HWDATA_ram3)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_ram3 = i_hready_mux__ram3;
+
+
+ // Output stage for MI3
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_3 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to3),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to3),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to3),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to3),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_sys),
+
+ .active_op0 (i_active0to3),
+ .active_op1 (i_active1to3),
+ .active_op2 (i_active2to3),
+ .active_op3 (i_active3to3),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_sys),
+ .HADDRM (HADDR_sys),
+ .HAUSERM (HAUSER_sys),
+ .HTRANSM (HTRANS_sys),
+ .HWRITEM (HWRITE_sys),
+ .HSIZEM (HSIZE_sys),
+ .HBURSTM (HBURST_sys),
+ .HPROTM (HPROT_sys),
+ .HMASTERM (HMASTER_sys),
+ .HMASTLOCKM (HMASTLOCK_sys),
+ .HREADYMUXM (i_hready_mux__sys),
+ .HWUSERM (HWUSER_sys),
+ .HWDATAM (HWDATA_sys)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_sys = i_hready_mux__sys;
+
+
+ // Output stage for MI4
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_4 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to4),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to4),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to4),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to4),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_ram8),
+
+ .active_op0 (i_active0to4),
+ .active_op1 (i_active1to4),
+ .active_op2 (i_active2to4),
+ .active_op3 (i_active3to4),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_ram8),
+ .HADDRM (HADDR_ram8),
+ .HAUSERM (HAUSER_ram8),
+ .HTRANSM (HTRANS_ram8),
+ .HWRITEM (HWRITE_ram8),
+ .HSIZEM (HSIZE_ram8),
+ .HBURSTM (HBURST_ram8),
+ .HPROTM (HPROT_ram8),
+ .HMASTERM (HMASTER_ram8),
+ .HMASTLOCKM (HMASTLOCK_ram8),
+ .HREADYMUXM (i_hready_mux__ram8),
+ .HWUSERM (HWUSER_ram8),
+ .HWDATAM (HWDATA_ram8)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_ram8 = i_hready_mux__ram8;
+
+
+ // Output stage for MI5
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_5 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to5),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to5),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to5),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to5),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_ram9),
+
+ .active_op0 (i_active0to5),
+ .active_op1 (i_active1to5),
+ .active_op2 (i_active2to5),
+ .active_op3 (i_active3to5),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_ram9),
+ .HADDRM (HADDR_ram9),
+ .HAUSERM (HAUSER_ram9),
+ .HTRANSM (HTRANS_ram9),
+ .HWRITEM (HWRITE_ram9),
+ .HSIZEM (HSIZE_ram9),
+ .HBURSTM (HBURST_ram9),
+ .HPROTM (HPROT_ram9),
+ .HMASTERM (HMASTER_ram9),
+ .HMASTLOCKM (HMASTLOCK_ram9),
+ .HREADYMUXM (i_hready_mux__ram9),
+ .HWUSERM (HWUSER_ram9),
+ .HWDATAM (HWDATA_ram9)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_ram9 = i_hready_mux__ram9;
+
+
+ // Output stage for MI6
+ soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_6 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to6),
+ .addr_op0 (i_addr0),
+ .auser_op0 (i_auser0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_adp),
+ .wuser_op0 (HWUSER_adp),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to6),
+ .addr_op1 (i_addr1),
+ .auser_op1 (i_auser1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_dma),
+ .wuser_op1 (HWUSER_dma),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to6),
+ .addr_op2 (i_addr2),
+ .auser_op2 (i_auser2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_dma2),
+ .wuser_op2 (HWUSER_dma2),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to6),
+ .addr_op3 (i_addr3),
+ .auser_op3 (i_auser3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .wuser_op3 (HWUSER_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_exp),
+
+ .active_op0 (i_active0to6),
+ .active_op1 (i_active1to6),
+ .active_op2 (i_active2to6),
+ .active_op3 (i_active3to6),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_exp),
+ .HADDRM (HADDR_exp),
+ .HAUSERM (HAUSER_exp),
+ .HTRANSM (HTRANS_exp),
+ .HWRITEM (HWRITE_exp),
+ .HSIZEM (HSIZE_exp),
+ .HBURSTM (HBURST_exp),
+ .HPROTM (HPROT_exp),
+ .HMASTERM (HMASTER_exp),
+ .HMASTLOCKM (HMASTLOCK_exp),
+ .HREADYMUXM (i_hready_mux__exp),
+ .HWUSERM (HWUSER_exp),
+ .HWDATAM (HWDATA_exp)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_exp = i_hready_mux__exp;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
new file mode 100644
index 0000000000000000000000000000000000000000..8f241850ebb4fba1340ebbbc967f40c39e0e3a64
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
@@ -0,0 +1,140 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+// -----------------------------------------------------------------------------
+// Abstract : Default slave used to drive the slave response signals
+// when there are no other slaves selected.
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_AhbMatrix_default_slave (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // AHB control input signals
+ HSEL,
+ HTRANS,
+ HREADY,
+
+ // AHB control output signals
+ HREADYOUT,
+ HRESP
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // AHB control input signals
+ input HSEL; // Slave Select
+ input [1:0] HTRANS; // Transfer type
+ input HREADY; // Transfer done
+
+ // AHB control output signals
+ output HREADYOUT; // HREADY feedback
+ output [1:0] HRESP; // Transfer response
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HRESP transfer response signal encoding
+`define RSP_OKAY 2'b00 // OKAY response
+`define RSP_ERROR 2'b01 // ERROR response
+`define RSP_RETRY 2'b10 // RETRY response
+`define RSP_SPLIT 2'b11 // SPLIT response
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // AHB control input signals
+ wire HSEL; // Slave Select
+ wire [1:0] HTRANS; // Transfer type
+ wire HREADY; // Transfer done
+
+ // AHB control output signals
+ wire HREADYOUT; // HREADY feedback
+ wire [1:0] HRESP; // Transfer response
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ wire invalid; // Set during invalid transfer
+ wire hready_next; // Controls generation of HREADYOUT output
+ reg i_hreadyout; // HREADYOUT register
+ wire [1:0] hresp_next; // Generated response
+ reg [1:0] i_hresp; // HRESP register
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+ assign invalid = ( HREADY & HSEL & HTRANS[1] );
+ assign hready_next = i_hreadyout ? ~invalid : 1'b1 ;
+ assign hresp_next = invalid ? `RSP_ERROR : `RSP_OKAY;
+
+ always @(negedge HRESETn or posedge HCLK)
+ begin : p_resp_seq
+ if (~HRESETn)
+ begin
+ i_hreadyout <= 1'b1;
+ i_hresp <= `RSP_OKAY;
+ end
+ else
+ begin
+ i_hreadyout <= hready_next;
+
+ if (i_hreadyout)
+ i_hresp <= hresp_next;
+ end
+ end
+
+ // Drive outputs with internal versions
+ assign HREADYOUT = i_hreadyout;
+ assign HRESP = i_hresp;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
new file mode 100644
index 0000000000000000000000000000000000000000..bd81ad5d8ac258c05fc09aac4d571a8d90e97eae
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
@@ -0,0 +1,985 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : BusMatrixLite is a wrapper module that wraps around
+// the BusMatrix module to give AHB Lite compliant
+// slave and master interfaces.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_AhbMatrix_lite (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // System Address Remap control
+ REMAP,
+
+ // Input port SI0 (inputs from master 0)
+ HADDR_adp,
+ HTRANS_adp,
+ HWRITE_adp,
+ HSIZE_adp,
+ HBURST_adp,
+ HPROT_adp,
+ HWDATA_adp,
+ HMASTLOCK_adp,
+ HAUSER_adp,
+ HWUSER_adp,
+
+ // Input port SI1 (inputs from master 1)
+ HADDR_dma,
+ HTRANS_dma,
+ HWRITE_dma,
+ HSIZE_dma,
+ HBURST_dma,
+ HPROT_dma,
+ HWDATA_dma,
+ HMASTLOCK_dma,
+ HAUSER_dma,
+ HWUSER_dma,
+
+ // Input port SI2 (inputs from master 2)
+ HADDR_dma2,
+ HTRANS_dma2,
+ HWRITE_dma2,
+ HSIZE_dma2,
+ HBURST_dma2,
+ HPROT_dma2,
+ HWDATA_dma2,
+ HMASTLOCK_dma2,
+ HAUSER_dma2,
+ HWUSER_dma2,
+
+ // Input port SI3 (inputs from master 3)
+ HADDR_cpu,
+ HTRANS_cpu,
+ HWRITE_cpu,
+ HSIZE_cpu,
+ HBURST_cpu,
+ HPROT_cpu,
+ HWDATA_cpu,
+ HMASTLOCK_cpu,
+ HAUSER_cpu,
+ HWUSER_cpu,
+
+ // Output port MI0 (inputs from slave 0)
+ HRDATA_rom1,
+ HREADYOUT_rom1,
+ HRESP_rom1,
+ HRUSER_rom1,
+
+ // Output port MI1 (inputs from slave 1)
+ HRDATA_ram2,
+ HREADYOUT_ram2,
+ HRESP_ram2,
+ HRUSER_ram2,
+
+ // Output port MI2 (inputs from slave 2)
+ HRDATA_ram3,
+ HREADYOUT_ram3,
+ HRESP_ram3,
+ HRUSER_ram3,
+
+ // Output port MI3 (inputs from slave 3)
+ HRDATA_sys,
+ HREADYOUT_sys,
+ HRESP_sys,
+ HRUSER_sys,
+
+ // Output port MI4 (inputs from slave 4)
+ HRDATA_ram8,
+ HREADYOUT_ram8,
+ HRESP_ram8,
+ HRUSER_ram8,
+
+ // Output port MI5 (inputs from slave 5)
+ HRDATA_ram9,
+ HREADYOUT_ram9,
+ HRESP_ram9,
+ HRUSER_ram9,
+
+ // Output port MI6 (inputs from slave 6)
+ HRDATA_exp,
+ HREADYOUT_exp,
+ HRESP_exp,
+ HRUSER_exp,
+
+ // Scan test dummy signals; not connected until scan insertion
+ SCANENABLE, // Scan Test Mode Enable
+ SCANINHCLK, // Scan Chain Input
+
+
+ // Output port MI0 (outputs to slave 0)
+ HSEL_rom1,
+ HADDR_rom1,
+ HTRANS_rom1,
+ HWRITE_rom1,
+ HSIZE_rom1,
+ HBURST_rom1,
+ HPROT_rom1,
+ HWDATA_rom1,
+ HMASTLOCK_rom1,
+ HREADYMUX_rom1,
+ HAUSER_rom1,
+ HWUSER_rom1,
+
+ // Output port MI1 (outputs to slave 1)
+ HSEL_ram2,
+ HADDR_ram2,
+ HTRANS_ram2,
+ HWRITE_ram2,
+ HSIZE_ram2,
+ HBURST_ram2,
+ HPROT_ram2,
+ HWDATA_ram2,
+ HMASTLOCK_ram2,
+ HREADYMUX_ram2,
+ HAUSER_ram2,
+ HWUSER_ram2,
+
+ // Output port MI2 (outputs to slave 2)
+ HSEL_ram3,
+ HADDR_ram3,
+ HTRANS_ram3,
+ HWRITE_ram3,
+ HSIZE_ram3,
+ HBURST_ram3,
+ HPROT_ram3,
+ HWDATA_ram3,
+ HMASTLOCK_ram3,
+ HREADYMUX_ram3,
+ HAUSER_ram3,
+ HWUSER_ram3,
+
+ // Output port MI3 (outputs to slave 3)
+ HSEL_sys,
+ HADDR_sys,
+ HTRANS_sys,
+ HWRITE_sys,
+ HSIZE_sys,
+ HBURST_sys,
+ HPROT_sys,
+ HWDATA_sys,
+ HMASTLOCK_sys,
+ HREADYMUX_sys,
+ HAUSER_sys,
+ HWUSER_sys,
+
+ // Output port MI4 (outputs to slave 4)
+ HSEL_ram8,
+ HADDR_ram8,
+ HTRANS_ram8,
+ HWRITE_ram8,
+ HSIZE_ram8,
+ HBURST_ram8,
+ HPROT_ram8,
+ HWDATA_ram8,
+ HMASTLOCK_ram8,
+ HREADYMUX_ram8,
+ HAUSER_ram8,
+ HWUSER_ram8,
+
+ // Output port MI5 (outputs to slave 5)
+ HSEL_ram9,
+ HADDR_ram9,
+ HTRANS_ram9,
+ HWRITE_ram9,
+ HSIZE_ram9,
+ HBURST_ram9,
+ HPROT_ram9,
+ HWDATA_ram9,
+ HMASTLOCK_ram9,
+ HREADYMUX_ram9,
+ HAUSER_ram9,
+ HWUSER_ram9,
+
+ // Output port MI6 (outputs to slave 6)
+ HSEL_exp,
+ HADDR_exp,
+ HTRANS_exp,
+ HWRITE_exp,
+ HSIZE_exp,
+ HBURST_exp,
+ HPROT_exp,
+ HWDATA_exp,
+ HMASTLOCK_exp,
+ HREADYMUX_exp,
+ HAUSER_exp,
+ HWUSER_exp,
+
+ // Input port SI0 (outputs to master 0)
+ HRDATA_adp,
+ HREADY_adp,
+ HRESP_adp,
+ HRUSER_adp,
+
+ // Input port SI1 (outputs to master 1)
+ HRDATA_dma,
+ HREADY_dma,
+ HRESP_dma,
+ HRUSER_dma,
+
+ // Input port SI2 (outputs to master 2)
+ HRDATA_dma2,
+ HREADY_dma2,
+ HRESP_dma2,
+ HRUSER_dma2,
+
+ // Input port SI3 (outputs to master 3)
+ HRDATA_cpu,
+ HREADY_cpu,
+ HRESP_cpu,
+ HRUSER_cpu,
+
+ // Scan test dummy signals; not connected until scan insertion
+ SCANOUTHCLK // Scan Chain Output
+
+ );
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // System Address Remap control
+ input [3:0] REMAP; // System Address REMAP control
+
+ // Input port SI0 (inputs from master 0)
+ input [31:0] HADDR_adp; // Address bus
+ input [1:0] HTRANS_adp; // Transfer type
+ input HWRITE_adp; // Transfer direction
+ input [2:0] HSIZE_adp; // Transfer size
+ input [2:0] HBURST_adp; // Burst type
+ input [3:0] HPROT_adp; // Protection control
+ input [31:0] HWDATA_adp; // Write data
+ input HMASTLOCK_adp; // Locked Sequence
+ input [1:0] HAUSER_adp; // Address USER signals
+ input [1:0] HWUSER_adp; // Write-data USER signals
+
+ // Input port SI1 (inputs from master 1)
+ input [31:0] HADDR_dma; // Address bus
+ input [1:0] HTRANS_dma; // Transfer type
+ input HWRITE_dma; // Transfer direction
+ input [2:0] HSIZE_dma; // Transfer size
+ input [2:0] HBURST_dma; // Burst type
+ input [3:0] HPROT_dma; // Protection control
+ input [31:0] HWDATA_dma; // Write data
+ input HMASTLOCK_dma; // Locked Sequence
+ input [1:0] HAUSER_dma; // Address USER signals
+ input [1:0] HWUSER_dma; // Write-data USER signals
+
+ // Input port SI2 (inputs from master 2)
+ input [31:0] HADDR_dma2; // Address bus
+ input [1:0] HTRANS_dma2; // Transfer type
+ input HWRITE_dma2; // Transfer direction
+ input [2:0] HSIZE_dma2; // Transfer size
+ input [2:0] HBURST_dma2; // Burst type
+ input [3:0] HPROT_dma2; // Protection control
+ input [31:0] HWDATA_dma2; // Write data
+ input HMASTLOCK_dma2; // Locked Sequence
+ input [1:0] HAUSER_dma2; // Address USER signals
+ input [1:0] HWUSER_dma2; // Write-data USER signals
+
+ // Input port SI3 (inputs from master 3)
+ input [31:0] HADDR_cpu; // Address bus
+ input [1:0] HTRANS_cpu; // Transfer type
+ input HWRITE_cpu; // Transfer direction
+ input [2:0] HSIZE_cpu; // Transfer size
+ input [2:0] HBURST_cpu; // Burst type
+ input [3:0] HPROT_cpu; // Protection control
+ input [31:0] HWDATA_cpu; // Write data
+ input HMASTLOCK_cpu; // Locked Sequence
+ input [1:0] HAUSER_cpu; // Address USER signals
+ input [1:0] HWUSER_cpu; // Write-data USER signals
+
+ // Output port MI0 (inputs from slave 0)
+ input [31:0] HRDATA_rom1; // Read data bus
+ input HREADYOUT_rom1; // HREADY feedback
+ input HRESP_rom1; // Transfer response
+ input [1:0] HRUSER_rom1; // Read-data USER signals
+
+ // Output port MI1 (inputs from slave 1)
+ input [31:0] HRDATA_ram2; // Read data bus
+ input HREADYOUT_ram2; // HREADY feedback
+ input HRESP_ram2; // Transfer response
+ input [1:0] HRUSER_ram2; // Read-data USER signals
+
+ // Output port MI2 (inputs from slave 2)
+ input [31:0] HRDATA_ram3; // Read data bus
+ input HREADYOUT_ram3; // HREADY feedback
+ input HRESP_ram3; // Transfer response
+ input [1:0] HRUSER_ram3; // Read-data USER signals
+
+ // Output port MI3 (inputs from slave 3)
+ input [31:0] HRDATA_sys; // Read data bus
+ input HREADYOUT_sys; // HREADY feedback
+ input HRESP_sys; // Transfer response
+ input [1:0] HRUSER_sys; // Read-data USER signals
+
+ // Output port MI4 (inputs from slave 4)
+ input [31:0] HRDATA_ram8; // Read data bus
+ input HREADYOUT_ram8; // HREADY feedback
+ input HRESP_ram8; // Transfer response
+ input [1:0] HRUSER_ram8; // Read-data USER signals
+
+ // Output port MI5 (inputs from slave 5)
+ input [31:0] HRDATA_ram9; // Read data bus
+ input HREADYOUT_ram9; // HREADY feedback
+ input HRESP_ram9; // Transfer response
+ input [1:0] HRUSER_ram9; // Read-data USER signals
+
+ // Output port MI6 (inputs from slave 6)
+ input [31:0] HRDATA_exp; // Read data bus
+ input HREADYOUT_exp; // HREADY feedback
+ input HRESP_exp; // Transfer response
+ input [1:0] HRUSER_exp; // Read-data USER signals
+
+ // Scan test dummy signals; not connected until scan insertion
+ input SCANENABLE; // Scan enable signal
+ input SCANINHCLK; // HCLK scan input
+
+
+ // Output port MI0 (outputs to slave 0)
+ output HSEL_rom1; // Slave Select
+ output [31:0] HADDR_rom1; // Address bus
+ output [1:0] HTRANS_rom1; // Transfer type
+ output HWRITE_rom1; // Transfer direction
+ output [2:0] HSIZE_rom1; // Transfer size
+ output [2:0] HBURST_rom1; // Burst type
+ output [3:0] HPROT_rom1; // Protection control
+ output [31:0] HWDATA_rom1; // Write data
+ output HMASTLOCK_rom1; // Locked Sequence
+ output HREADYMUX_rom1; // Transfer done
+ output [1:0] HAUSER_rom1; // Address USER signals
+ output [1:0] HWUSER_rom1; // Write-data USER signals
+
+ // Output port MI1 (outputs to slave 1)
+ output HSEL_ram2; // Slave Select
+ output [31:0] HADDR_ram2; // Address bus
+ output [1:0] HTRANS_ram2; // Transfer type
+ output HWRITE_ram2; // Transfer direction
+ output [2:0] HSIZE_ram2; // Transfer size
+ output [2:0] HBURST_ram2; // Burst type
+ output [3:0] HPROT_ram2; // Protection control
+ output [31:0] HWDATA_ram2; // Write data
+ output HMASTLOCK_ram2; // Locked Sequence
+ output HREADYMUX_ram2; // Transfer done
+ output [1:0] HAUSER_ram2; // Address USER signals
+ output [1:0] HWUSER_ram2; // Write-data USER signals
+
+ // Output port MI2 (outputs to slave 2)
+ output HSEL_ram3; // Slave Select
+ output [31:0] HADDR_ram3; // Address bus
+ output [1:0] HTRANS_ram3; // Transfer type
+ output HWRITE_ram3; // Transfer direction
+ output [2:0] HSIZE_ram3; // Transfer size
+ output [2:0] HBURST_ram3; // Burst type
+ output [3:0] HPROT_ram3; // Protection control
+ output [31:0] HWDATA_ram3; // Write data
+ output HMASTLOCK_ram3; // Locked Sequence
+ output HREADYMUX_ram3; // Transfer done
+ output [1:0] HAUSER_ram3; // Address USER signals
+ output [1:0] HWUSER_ram3; // Write-data USER signals
+
+ // Output port MI3 (outputs to slave 3)
+ output HSEL_sys; // Slave Select
+ output [31:0] HADDR_sys; // Address bus
+ output [1:0] HTRANS_sys; // Transfer type
+ output HWRITE_sys; // Transfer direction
+ output [2:0] HSIZE_sys; // Transfer size
+ output [2:0] HBURST_sys; // Burst type
+ output [3:0] HPROT_sys; // Protection control
+ output [31:0] HWDATA_sys; // Write data
+ output HMASTLOCK_sys; // Locked Sequence
+ output HREADYMUX_sys; // Transfer done
+ output [1:0] HAUSER_sys; // Address USER signals
+ output [1:0] HWUSER_sys; // Write-data USER signals
+
+ // Output port MI4 (outputs to slave 4)
+ output HSEL_ram8; // Slave Select
+ output [31:0] HADDR_ram8; // Address bus
+ output [1:0] HTRANS_ram8; // Transfer type
+ output HWRITE_ram8; // Transfer direction
+ output [2:0] HSIZE_ram8; // Transfer size
+ output [2:0] HBURST_ram8; // Burst type
+ output [3:0] HPROT_ram8; // Protection control
+ output [31:0] HWDATA_ram8; // Write data
+ output HMASTLOCK_ram8; // Locked Sequence
+ output HREADYMUX_ram8; // Transfer done
+ output [1:0] HAUSER_ram8; // Address USER signals
+ output [1:0] HWUSER_ram8; // Write-data USER signals
+
+ // Output port MI5 (outputs to slave 5)
+ output HSEL_ram9; // Slave Select
+ output [31:0] HADDR_ram9; // Address bus
+ output [1:0] HTRANS_ram9; // Transfer type
+ output HWRITE_ram9; // Transfer direction
+ output [2:0] HSIZE_ram9; // Transfer size
+ output [2:0] HBURST_ram9; // Burst type
+ output [3:0] HPROT_ram9; // Protection control
+ output [31:0] HWDATA_ram9; // Write data
+ output HMASTLOCK_ram9; // Locked Sequence
+ output HREADYMUX_ram9; // Transfer done
+ output [1:0] HAUSER_ram9; // Address USER signals
+ output [1:0] HWUSER_ram9; // Write-data USER signals
+
+ // Output port MI6 (outputs to slave 6)
+ output HSEL_exp; // Slave Select
+ output [31:0] HADDR_exp; // Address bus
+ output [1:0] HTRANS_exp; // Transfer type
+ output HWRITE_exp; // Transfer direction
+ output [2:0] HSIZE_exp; // Transfer size
+ output [2:0] HBURST_exp; // Burst type
+ output [3:0] HPROT_exp; // Protection control
+ output [31:0] HWDATA_exp; // Write data
+ output HMASTLOCK_exp; // Locked Sequence
+ output HREADYMUX_exp; // Transfer done
+ output [1:0] HAUSER_exp; // Address USER signals
+ output [1:0] HWUSER_exp; // Write-data USER signals
+
+ // Input port SI0 (outputs to master 0)
+ output [31:0] HRDATA_adp; // Read data bus
+ output HREADY_adp; // HREADY feedback
+ output HRESP_adp; // Transfer response
+ output [1:0] HRUSER_adp; // Read-data USER signals
+
+ // Input port SI1 (outputs to master 1)
+ output [31:0] HRDATA_dma; // Read data bus
+ output HREADY_dma; // HREADY feedback
+ output HRESP_dma; // Transfer response
+ output [1:0] HRUSER_dma; // Read-data USER signals
+
+ // Input port SI2 (outputs to master 2)
+ output [31:0] HRDATA_dma2; // Read data bus
+ output HREADY_dma2; // HREADY feedback
+ output HRESP_dma2; // Transfer response
+ output [1:0] HRUSER_dma2; // Read-data USER signals
+
+ // Input port SI3 (outputs to master 3)
+ output [31:0] HRDATA_cpu; // Read data bus
+ output HREADY_cpu; // HREADY feedback
+ output HRESP_cpu; // Transfer response
+ output [1:0] HRUSER_cpu; // Read-data USER signals
+
+ // Scan test dummy signals; not connected until scan insertion
+ output SCANOUTHCLK; // Scan Chain Output
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // System Address Remap control
+ wire [3:0] REMAP; // System REMAP signal
+
+ // Input Port SI0
+ wire [31:0] HADDR_adp; // Address bus
+ wire [1:0] HTRANS_adp; // Transfer type
+ wire HWRITE_adp; // Transfer direction
+ wire [2:0] HSIZE_adp; // Transfer size
+ wire [2:0] HBURST_adp; // Burst type
+ wire [3:0] HPROT_adp; // Protection control
+ wire [31:0] HWDATA_adp; // Write data
+ wire HMASTLOCK_adp; // Locked Sequence
+
+ wire [31:0] HRDATA_adp; // Read data bus
+ wire HREADY_adp; // HREADY feedback
+ wire HRESP_adp; // Transfer response
+ wire [1:0] HAUSER_adp; // Address USER signals
+ wire [1:0] HWUSER_adp; // Write-data USER signals
+ wire [1:0] HRUSER_adp; // Read-data USER signals
+
+ // Input Port SI1
+ wire [31:0] HADDR_dma; // Address bus
+ wire [1:0] HTRANS_dma; // Transfer type
+ wire HWRITE_dma; // Transfer direction
+ wire [2:0] HSIZE_dma; // Transfer size
+ wire [2:0] HBURST_dma; // Burst type
+ wire [3:0] HPROT_dma; // Protection control
+ wire [31:0] HWDATA_dma; // Write data
+ wire HMASTLOCK_dma; // Locked Sequence
+
+ wire [31:0] HRDATA_dma; // Read data bus
+ wire HREADY_dma; // HREADY feedback
+ wire HRESP_dma; // Transfer response
+ wire [1:0] HAUSER_dma; // Address USER signals
+ wire [1:0] HWUSER_dma; // Write-data USER signals
+ wire [1:0] HRUSER_dma; // Read-data USER signals
+
+ // Input Port SI2
+ wire [31:0] HADDR_dma2; // Address bus
+ wire [1:0] HTRANS_dma2; // Transfer type
+ wire HWRITE_dma2; // Transfer direction
+ wire [2:0] HSIZE_dma2; // Transfer size
+ wire [2:0] HBURST_dma2; // Burst type
+ wire [3:0] HPROT_dma2; // Protection control
+ wire [31:0] HWDATA_dma2; // Write data
+ wire HMASTLOCK_dma2; // Locked Sequence
+
+ wire [31:0] HRDATA_dma2; // Read data bus
+ wire HREADY_dma2; // HREADY feedback
+ wire HRESP_dma2; // Transfer response
+ wire [1:0] HAUSER_dma2; // Address USER signals
+ wire [1:0] HWUSER_dma2; // Write-data USER signals
+ wire [1:0] HRUSER_dma2; // Read-data USER signals
+
+ // Input Port SI3
+ wire [31:0] HADDR_cpu; // Address bus
+ wire [1:0] HTRANS_cpu; // Transfer type
+ wire HWRITE_cpu; // Transfer direction
+ wire [2:0] HSIZE_cpu; // Transfer size
+ wire [2:0] HBURST_cpu; // Burst type
+ wire [3:0] HPROT_cpu; // Protection control
+ wire [31:0] HWDATA_cpu; // Write data
+ wire HMASTLOCK_cpu; // Locked Sequence
+
+ wire [31:0] HRDATA_cpu; // Read data bus
+ wire HREADY_cpu; // HREADY feedback
+ wire HRESP_cpu; // Transfer response
+ wire [1:0] HAUSER_cpu; // Address USER signals
+ wire [1:0] HWUSER_cpu; // Write-data USER signals
+ wire [1:0] HRUSER_cpu; // Read-data USER signals
+
+ // Output Port MI0
+ wire HSEL_rom1; // Slave Select
+ wire [31:0] HADDR_rom1; // Address bus
+ wire [1:0] HTRANS_rom1; // Transfer type
+ wire HWRITE_rom1; // Transfer direction
+ wire [2:0] HSIZE_rom1; // Transfer size
+ wire [2:0] HBURST_rom1; // Burst type
+ wire [3:0] HPROT_rom1; // Protection control
+ wire [31:0] HWDATA_rom1; // Write data
+ wire HMASTLOCK_rom1; // Locked Sequence
+ wire HREADYMUX_rom1; // Transfer done
+
+ wire [31:0] HRDATA_rom1; // Read data bus
+ wire HREADYOUT_rom1; // HREADY feedback
+ wire HRESP_rom1; // Transfer response
+ wire [1:0] HAUSER_rom1; // Address USER signals
+ wire [1:0] HWUSER_rom1; // Write-data USER signals
+ wire [1:0] HRUSER_rom1; // Read-data USER signals
+
+ // Output Port MI1
+ wire HSEL_ram2; // Slave Select
+ wire [31:0] HADDR_ram2; // Address bus
+ wire [1:0] HTRANS_ram2; // Transfer type
+ wire HWRITE_ram2; // Transfer direction
+ wire [2:0] HSIZE_ram2; // Transfer size
+ wire [2:0] HBURST_ram2; // Burst type
+ wire [3:0] HPROT_ram2; // Protection control
+ wire [31:0] HWDATA_ram2; // Write data
+ wire HMASTLOCK_ram2; // Locked Sequence
+ wire HREADYMUX_ram2; // Transfer done
+
+ wire [31:0] HRDATA_ram2; // Read data bus
+ wire HREADYOUT_ram2; // HREADY feedback
+ wire HRESP_ram2; // Transfer response
+ wire [1:0] HAUSER_ram2; // Address USER signals
+ wire [1:0] HWUSER_ram2; // Write-data USER signals
+ wire [1:0] HRUSER_ram2; // Read-data USER signals
+
+ // Output Port MI2
+ wire HSEL_ram3; // Slave Select
+ wire [31:0] HADDR_ram3; // Address bus
+ wire [1:0] HTRANS_ram3; // Transfer type
+ wire HWRITE_ram3; // Transfer direction
+ wire [2:0] HSIZE_ram3; // Transfer size
+ wire [2:0] HBURST_ram3; // Burst type
+ wire [3:0] HPROT_ram3; // Protection control
+ wire [31:0] HWDATA_ram3; // Write data
+ wire HMASTLOCK_ram3; // Locked Sequence
+ wire HREADYMUX_ram3; // Transfer done
+
+ wire [31:0] HRDATA_ram3; // Read data bus
+ wire HREADYOUT_ram3; // HREADY feedback
+ wire HRESP_ram3; // Transfer response
+ wire [1:0] HAUSER_ram3; // Address USER signals
+ wire [1:0] HWUSER_ram3; // Write-data USER signals
+ wire [1:0] HRUSER_ram3; // Read-data USER signals
+
+ // Output Port MI3
+ wire HSEL_sys; // Slave Select
+ wire [31:0] HADDR_sys; // Address bus
+ wire [1:0] HTRANS_sys; // Transfer type
+ wire HWRITE_sys; // Transfer direction
+ wire [2:0] HSIZE_sys; // Transfer size
+ wire [2:0] HBURST_sys; // Burst type
+ wire [3:0] HPROT_sys; // Protection control
+ wire [31:0] HWDATA_sys; // Write data
+ wire HMASTLOCK_sys; // Locked Sequence
+ wire HREADYMUX_sys; // Transfer done
+
+ wire [31:0] HRDATA_sys; // Read data bus
+ wire HREADYOUT_sys; // HREADY feedback
+ wire HRESP_sys; // Transfer response
+ wire [1:0] HAUSER_sys; // Address USER signals
+ wire [1:0] HWUSER_sys; // Write-data USER signals
+ wire [1:0] HRUSER_sys; // Read-data USER signals
+
+ // Output Port MI4
+ wire HSEL_ram8; // Slave Select
+ wire [31:0] HADDR_ram8; // Address bus
+ wire [1:0] HTRANS_ram8; // Transfer type
+ wire HWRITE_ram8; // Transfer direction
+ wire [2:0] HSIZE_ram8; // Transfer size
+ wire [2:0] HBURST_ram8; // Burst type
+ wire [3:0] HPROT_ram8; // Protection control
+ wire [31:0] HWDATA_ram8; // Write data
+ wire HMASTLOCK_ram8; // Locked Sequence
+ wire HREADYMUX_ram8; // Transfer done
+
+ wire [31:0] HRDATA_ram8; // Read data bus
+ wire HREADYOUT_ram8; // HREADY feedback
+ wire HRESP_ram8; // Transfer response
+ wire [1:0] HAUSER_ram8; // Address USER signals
+ wire [1:0] HWUSER_ram8; // Write-data USER signals
+ wire [1:0] HRUSER_ram8; // Read-data USER signals
+
+ // Output Port MI5
+ wire HSEL_ram9; // Slave Select
+ wire [31:0] HADDR_ram9; // Address bus
+ wire [1:0] HTRANS_ram9; // Transfer type
+ wire HWRITE_ram9; // Transfer direction
+ wire [2:0] HSIZE_ram9; // Transfer size
+ wire [2:0] HBURST_ram9; // Burst type
+ wire [3:0] HPROT_ram9; // Protection control
+ wire [31:0] HWDATA_ram9; // Write data
+ wire HMASTLOCK_ram9; // Locked Sequence
+ wire HREADYMUX_ram9; // Transfer done
+
+ wire [31:0] HRDATA_ram9; // Read data bus
+ wire HREADYOUT_ram9; // HREADY feedback
+ wire HRESP_ram9; // Transfer response
+ wire [1:0] HAUSER_ram9; // Address USER signals
+ wire [1:0] HWUSER_ram9; // Write-data USER signals
+ wire [1:0] HRUSER_ram9; // Read-data USER signals
+
+ // Output Port MI6
+ wire HSEL_exp; // Slave Select
+ wire [31:0] HADDR_exp; // Address bus
+ wire [1:0] HTRANS_exp; // Transfer type
+ wire HWRITE_exp; // Transfer direction
+ wire [2:0] HSIZE_exp; // Transfer size
+ wire [2:0] HBURST_exp; // Burst type
+ wire [3:0] HPROT_exp; // Protection control
+ wire [31:0] HWDATA_exp; // Write data
+ wire HMASTLOCK_exp; // Locked Sequence
+ wire HREADYMUX_exp; // Transfer done
+
+ wire [31:0] HRDATA_exp; // Read data bus
+ wire HREADYOUT_exp; // HREADY feedback
+ wire HRESP_exp; // Transfer response
+ wire [1:0] HAUSER_exp; // Address USER signals
+ wire [1:0] HWUSER_exp; // Write-data USER signals
+ wire [1:0] HRUSER_exp; // Read-data USER signals
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire [3:0] tie_hi_4;
+ wire tie_hi;
+ wire tie_low;
+ wire [1:0] i_hresp_adp;
+ wire [1:0] i_hresp_dma;
+ wire [1:0] i_hresp_dma2;
+ wire [1:0] i_hresp_cpu;
+
+ wire [3:0] i_hmaster_rom1;
+ wire [1:0] i_hresp_rom1;
+ wire [3:0] i_hmaster_ram2;
+ wire [1:0] i_hresp_ram2;
+ wire [3:0] i_hmaster_ram3;
+ wire [1:0] i_hresp_ram3;
+ wire [3:0] i_hmaster_sys;
+ wire [1:0] i_hresp_sys;
+ wire [3:0] i_hmaster_ram8;
+ wire [1:0] i_hresp_ram8;
+ wire [3:0] i_hmaster_ram9;
+ wire [1:0] i_hresp_ram9;
+ wire [3:0] i_hmaster_exp;
+ wire [1:0] i_hresp_exp;
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+ assign tie_hi = 1'b1;
+ assign tie_hi_4 = 4'b1111;
+ assign tie_low = 1'b0;
+
+
+ assign HRESP_adp = i_hresp_adp[0];
+
+ assign HRESP_dma = i_hresp_dma[0];
+
+ assign HRESP_dma2 = i_hresp_dma2[0];
+
+ assign HRESP_cpu = i_hresp_cpu[0];
+
+ assign i_hresp_rom1 = {{1{tie_low}}, HRESP_rom1};
+ assign i_hresp_ram2 = {{1{tie_low}}, HRESP_ram2};
+ assign i_hresp_ram3 = {{1{tie_low}}, HRESP_ram3};
+ assign i_hresp_sys = {{1{tie_low}}, HRESP_sys};
+ assign i_hresp_ram8 = {{1{tie_low}}, HRESP_ram8};
+ assign i_hresp_ram9 = {{1{tie_low}}, HRESP_ram9};
+ assign i_hresp_exp = {{1{tie_low}}, HRESP_exp};
+
+// BusMatrix instance
+ soclabs_4x7_AhbMatrix usoclabs_4x7_AhbMatrix (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .REMAP (REMAP),
+
+ // Input port SI0 signals
+ .HSEL_adp (tie_hi),
+ .HADDR_adp (HADDR_adp),
+ .HTRANS_adp (HTRANS_adp),
+ .HWRITE_adp (HWRITE_adp),
+ .HSIZE_adp (HSIZE_adp),
+ .HBURST_adp (HBURST_adp),
+ .HPROT_adp (HPROT_adp),
+ .HWDATA_adp (HWDATA_adp),
+ .HMASTLOCK_adp (HMASTLOCK_adp),
+ .HMASTER_adp (tie_hi_4),
+ .HREADY_adp (HREADY_adp),
+ .HAUSER_adp (HAUSER_adp),
+ .HWUSER_adp (HWUSER_adp),
+ .HRDATA_adp (HRDATA_adp),
+ .HREADYOUT_adp (HREADY_adp),
+ .HRESP_adp (i_hresp_adp),
+ .HRUSER_adp (HRUSER_adp),
+
+ // Input port SI1 signals
+ .HSEL_dma (tie_hi),
+ .HADDR_dma (HADDR_dma),
+ .HTRANS_dma (HTRANS_dma),
+ .HWRITE_dma (HWRITE_dma),
+ .HSIZE_dma (HSIZE_dma),
+ .HBURST_dma (HBURST_dma),
+ .HPROT_dma (HPROT_dma),
+ .HWDATA_dma (HWDATA_dma),
+ .HMASTLOCK_dma (HMASTLOCK_dma),
+ .HMASTER_dma (tie_hi_4),
+ .HREADY_dma (HREADY_dma),
+ .HAUSER_dma (HAUSER_dma),
+ .HWUSER_dma (HWUSER_dma),
+ .HRDATA_dma (HRDATA_dma),
+ .HREADYOUT_dma (HREADY_dma),
+ .HRESP_dma (i_hresp_dma),
+ .HRUSER_dma (HRUSER_dma),
+
+ // Input port SI2 signals
+ .HSEL_dma2 (tie_hi),
+ .HADDR_dma2 (HADDR_dma2),
+ .HTRANS_dma2 (HTRANS_dma2),
+ .HWRITE_dma2 (HWRITE_dma2),
+ .HSIZE_dma2 (HSIZE_dma2),
+ .HBURST_dma2 (HBURST_dma2),
+ .HPROT_dma2 (HPROT_dma2),
+ .HWDATA_dma2 (HWDATA_dma2),
+ .HMASTLOCK_dma2 (HMASTLOCK_dma2),
+ .HMASTER_dma2 (tie_hi_4),
+ .HREADY_dma2 (HREADY_dma2),
+ .HAUSER_dma2 (HAUSER_dma2),
+ .HWUSER_dma2 (HWUSER_dma2),
+ .HRDATA_dma2 (HRDATA_dma2),
+ .HREADYOUT_dma2 (HREADY_dma2),
+ .HRESP_dma2 (i_hresp_dma2),
+ .HRUSER_dma2 (HRUSER_dma2),
+
+ // Input port SI3 signals
+ .HSEL_cpu (tie_hi),
+ .HADDR_cpu (HADDR_cpu),
+ .HTRANS_cpu (HTRANS_cpu),
+ .HWRITE_cpu (HWRITE_cpu),
+ .HSIZE_cpu (HSIZE_cpu),
+ .HBURST_cpu (HBURST_cpu),
+ .HPROT_cpu (HPROT_cpu),
+ .HWDATA_cpu (HWDATA_cpu),
+ .HMASTLOCK_cpu (HMASTLOCK_cpu),
+ .HMASTER_cpu (tie_hi_4),
+ .HREADY_cpu (HREADY_cpu),
+ .HAUSER_cpu (HAUSER_cpu),
+ .HWUSER_cpu (HWUSER_cpu),
+ .HRDATA_cpu (HRDATA_cpu),
+ .HREADYOUT_cpu (HREADY_cpu),
+ .HRESP_cpu (i_hresp_cpu),
+ .HRUSER_cpu (HRUSER_cpu),
+
+
+ // Output port MI0 signals
+ .HSEL_rom1 (HSEL_rom1),
+ .HADDR_rom1 (HADDR_rom1),
+ .HTRANS_rom1 (HTRANS_rom1),
+ .HWRITE_rom1 (HWRITE_rom1),
+ .HSIZE_rom1 (HSIZE_rom1),
+ .HBURST_rom1 (HBURST_rom1),
+ .HPROT_rom1 (HPROT_rom1),
+ .HWDATA_rom1 (HWDATA_rom1),
+ .HMASTER_rom1 (i_hmaster_rom1),
+ .HMASTLOCK_rom1 (HMASTLOCK_rom1),
+ .HREADYMUX_rom1 (HREADYMUX_rom1),
+ .HAUSER_rom1 (HAUSER_rom1),
+ .HWUSER_rom1 (HWUSER_rom1),
+ .HRDATA_rom1 (HRDATA_rom1),
+ .HREADYOUT_rom1 (HREADYOUT_rom1),
+ .HRESP_rom1 (i_hresp_rom1),
+ .HRUSER_rom1 (HRUSER_rom1),
+
+ // Output port MI1 signals
+ .HSEL_ram2 (HSEL_ram2),
+ .HADDR_ram2 (HADDR_ram2),
+ .HTRANS_ram2 (HTRANS_ram2),
+ .HWRITE_ram2 (HWRITE_ram2),
+ .HSIZE_ram2 (HSIZE_ram2),
+ .HBURST_ram2 (HBURST_ram2),
+ .HPROT_ram2 (HPROT_ram2),
+ .HWDATA_ram2 (HWDATA_ram2),
+ .HMASTER_ram2 (i_hmaster_ram2),
+ .HMASTLOCK_ram2 (HMASTLOCK_ram2),
+ .HREADYMUX_ram2 (HREADYMUX_ram2),
+ .HAUSER_ram2 (HAUSER_ram2),
+ .HWUSER_ram2 (HWUSER_ram2),
+ .HRDATA_ram2 (HRDATA_ram2),
+ .HREADYOUT_ram2 (HREADYOUT_ram2),
+ .HRESP_ram2 (i_hresp_ram2),
+ .HRUSER_ram2 (HRUSER_ram2),
+
+ // Output port MI2 signals
+ .HSEL_ram3 (HSEL_ram3),
+ .HADDR_ram3 (HADDR_ram3),
+ .HTRANS_ram3 (HTRANS_ram3),
+ .HWRITE_ram3 (HWRITE_ram3),
+ .HSIZE_ram3 (HSIZE_ram3),
+ .HBURST_ram3 (HBURST_ram3),
+ .HPROT_ram3 (HPROT_ram3),
+ .HWDATA_ram3 (HWDATA_ram3),
+ .HMASTER_ram3 (i_hmaster_ram3),
+ .HMASTLOCK_ram3 (HMASTLOCK_ram3),
+ .HREADYMUX_ram3 (HREADYMUX_ram3),
+ .HAUSER_ram3 (HAUSER_ram3),
+ .HWUSER_ram3 (HWUSER_ram3),
+ .HRDATA_ram3 (HRDATA_ram3),
+ .HREADYOUT_ram3 (HREADYOUT_ram3),
+ .HRESP_ram3 (i_hresp_ram3),
+ .HRUSER_ram3 (HRUSER_ram3),
+
+ // Output port MI3 signals
+ .HSEL_sys (HSEL_sys),
+ .HADDR_sys (HADDR_sys),
+ .HTRANS_sys (HTRANS_sys),
+ .HWRITE_sys (HWRITE_sys),
+ .HSIZE_sys (HSIZE_sys),
+ .HBURST_sys (HBURST_sys),
+ .HPROT_sys (HPROT_sys),
+ .HWDATA_sys (HWDATA_sys),
+ .HMASTER_sys (i_hmaster_sys),
+ .HMASTLOCK_sys (HMASTLOCK_sys),
+ .HREADYMUX_sys (HREADYMUX_sys),
+ .HAUSER_sys (HAUSER_sys),
+ .HWUSER_sys (HWUSER_sys),
+ .HRDATA_sys (HRDATA_sys),
+ .HREADYOUT_sys (HREADYOUT_sys),
+ .HRESP_sys (i_hresp_sys),
+ .HRUSER_sys (HRUSER_sys),
+
+ // Output port MI4 signals
+ .HSEL_ram8 (HSEL_ram8),
+ .HADDR_ram8 (HADDR_ram8),
+ .HTRANS_ram8 (HTRANS_ram8),
+ .HWRITE_ram8 (HWRITE_ram8),
+ .HSIZE_ram8 (HSIZE_ram8),
+ .HBURST_ram8 (HBURST_ram8),
+ .HPROT_ram8 (HPROT_ram8),
+ .HWDATA_ram8 (HWDATA_ram8),
+ .HMASTER_ram8 (i_hmaster_ram8),
+ .HMASTLOCK_ram8 (HMASTLOCK_ram8),
+ .HREADYMUX_ram8 (HREADYMUX_ram8),
+ .HAUSER_ram8 (HAUSER_ram8),
+ .HWUSER_ram8 (HWUSER_ram8),
+ .HRDATA_ram8 (HRDATA_ram8),
+ .HREADYOUT_ram8 (HREADYOUT_ram8),
+ .HRESP_ram8 (i_hresp_ram8),
+ .HRUSER_ram8 (HRUSER_ram8),
+
+ // Output port MI5 signals
+ .HSEL_ram9 (HSEL_ram9),
+ .HADDR_ram9 (HADDR_ram9),
+ .HTRANS_ram9 (HTRANS_ram9),
+ .HWRITE_ram9 (HWRITE_ram9),
+ .HSIZE_ram9 (HSIZE_ram9),
+ .HBURST_ram9 (HBURST_ram9),
+ .HPROT_ram9 (HPROT_ram9),
+ .HWDATA_ram9 (HWDATA_ram9),
+ .HMASTER_ram9 (i_hmaster_ram9),
+ .HMASTLOCK_ram9 (HMASTLOCK_ram9),
+ .HREADYMUX_ram9 (HREADYMUX_ram9),
+ .HAUSER_ram9 (HAUSER_ram9),
+ .HWUSER_ram9 (HWUSER_ram9),
+ .HRDATA_ram9 (HRDATA_ram9),
+ .HREADYOUT_ram9 (HREADYOUT_ram9),
+ .HRESP_ram9 (i_hresp_ram9),
+ .HRUSER_ram9 (HRUSER_ram9),
+
+ // Output port MI6 signals
+ .HSEL_exp (HSEL_exp),
+ .HADDR_exp (HADDR_exp),
+ .HTRANS_exp (HTRANS_exp),
+ .HWRITE_exp (HWRITE_exp),
+ .HSIZE_exp (HSIZE_exp),
+ .HBURST_exp (HBURST_exp),
+ .HPROT_exp (HPROT_exp),
+ .HWDATA_exp (HWDATA_exp),
+ .HMASTER_exp (i_hmaster_exp),
+ .HMASTLOCK_exp (HMASTLOCK_exp),
+ .HREADYMUX_exp (HREADYMUX_exp),
+ .HAUSER_exp (HAUSER_exp),
+ .HWUSER_exp (HWUSER_exp),
+ .HRDATA_exp (HRDATA_exp),
+ .HREADYOUT_exp (HREADYOUT_exp),
+ .HRESP_exp (i_hresp_exp),
+ .HRUSER_exp (HRUSER_exp),
+
+
+ // Scan test dummy signals; not connected until scan insertion
+ .SCANENABLE (SCANENABLE),
+ .SCANINHCLK (SCANINHCLK),
+ .SCANOUTHCLK (SCANOUTHCLK)
+ );
+
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
new file mode 100644
index 0000000000000000000000000000000000000000..f5eb286e8a5de73ef740ef8d4985c467c7791a06
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
@@ -0,0 +1,330 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has full connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_Arbiter (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
new file mode 100644
index 0000000000000000000000000000000000000000..c7ff01a0248933069f675602eea6a6edcb245cfe
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
@@ -0,0 +1,473 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Input Stage is used to hold a pending transfer
+// when the required output stage is not available.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_MasterInput (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Input Port Address/Control Signals
+ HSELS,
+ HADDRS,
+ HAUSERS,
+ HTRANSS,
+ HWRITES,
+ HSIZES,
+ HBURSTS,
+ HPROTS,
+ HMASTERS,
+ HMASTLOCKS,
+ HREADYS,
+
+ // Internal Response
+ active_ip,
+ readyout_ip,
+ resp_ip,
+
+ // Input Port Response
+ HREADYOUTS,
+ HRESPS,
+
+ // Internal Address/Control Signals
+ sel_ip,
+ addr_ip,
+ auser_ip,
+ trans_ip,
+ write_ip,
+ size_ip,
+ burst_ip,
+ prot_ip,
+ master_ip,
+ mastlock_ip,
+ held_tran_ip
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+ input HSELS; // Slave Select from AHB
+ input [31:0] HADDRS; // Address bus from AHB
+ input [1:0] HAUSERS; // Additional user adress bus
+ input [1:0] HTRANSS; // Transfer type from AHB
+ input HWRITES; // Transfer direction from AHB
+ input [2:0] HSIZES; // Transfer size from AHB
+ input [2:0] HBURSTS; // Burst type from AHB
+ input [3:0] HPROTS; // Protection control from AHB
+ input [3:0] HMASTERS; // Master number from AHB
+ input HMASTLOCKS; // Locked Sequence from AHB
+ input HREADYS; // Transfer done from AHB
+ input active_ip; // active_ip signal
+ input readyout_ip; // HREADYOUT input
+ input [1:0] resp_ip; // HRESP input
+
+ output HREADYOUTS; // HREADY feedback to AHB
+ output [1:0] HRESPS; // Transfer response to AHB
+ output sel_ip; // HSEL output
+ output [31:0] addr_ip; // HADDR output
+ output [1:0] auser_ip; // HAUSER output
+ output [1:0] trans_ip; // HTRANS output
+ output write_ip; // HWRITE output
+ output [2:0] size_ip; // HSIZE output
+ output [2:0] burst_ip; // HBURST output
+ output [3:0] prot_ip; // HPROT output
+ output [3:0] master_ip; // HMASTER output
+ output mastlock_ip; // HMASTLOCK output
+ output held_tran_ip; // Holding register active flag
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle Transfer
+`define TRN_BUSY 2'b01 // Busy Transfer
+`define TRN_NONSEQ 2'b10 // Nonsequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single BURST
+`define BUR_INCR 3'b001 // Incremental BURSTS
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat incr
+`define BUR_WRAP16 3'b110 // 16-beat wrap
+`define BUR_INCR16 3'b111 // 16-beat incr
+
+// HRESP signal encoding
+`define RSP_OKAY 2'b00 // OKAY response
+`define RSP_ERROR 2'b01 // ERROR response
+`define RSP_RETRY 2'b10 // RETRY response
+`define RSP_SPLIT 2'b11 // SPLIT response
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+ wire HSELS; // Slave Select from AHB
+ wire [31:0] HADDRS; // Address bus from AHB
+ wire [1:0] HAUSERS; // Additional user adress bus
+ wire [1:0] HTRANSS; // Transfer type from AHB
+ wire HWRITES; // Transfer direction from AHB
+ wire [2:0] HSIZES; // Transfer size from AHB
+ wire [2:0] HBURSTS; // Burst type from AHB
+ wire [3:0] HPROTS; // Protection control from AHB
+ wire [3:0] HMASTERS; // Master number from AHB
+ wire HMASTLOCKS; // Locked Sequence from AHB
+ wire HREADYS; // Transfer done from AHB
+ reg HREADYOUTS; // HREADY feedback to AHB
+ reg [1:0] HRESPS; // Transfer response to AHB
+ reg sel_ip; // HSEL output
+ reg [31:0] addr_ip; // HADDR output
+ reg [1:0] auser_ip; // HAUSER output
+ wire [1:0] trans_ip; // HTRANS output
+ reg write_ip; // HWRITE output
+ reg [2:0] size_ip; // HSIZE output
+ wire [2:0] burst_ip; // HBURST output
+ reg [3:0] prot_ip; // HPROT output
+ reg [3:0] master_ip; // HMASTER output
+ reg mastlock_ip; // HMASTLOCK output
+ wire held_tran_ip; // Holding register active flag
+ wire active_ip; // active_ip signal
+ wire readyout_ip; // HREADYOUT input
+ wire [1:0] resp_ip; // HRESP input
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ wire load_reg; // Holding register load flag
+ wire pend_tran; // An active transfer cannot complete
+ reg pend_tran_reg; // Registered version of pend_tran
+ wire addr_valid; // Indicates address phase of
+ // valid transfer
+ reg data_valid; // Indicates data phase of
+ // valid transfer
+ reg [1:0] reg_trans; // Registered HTRANSS
+ reg [31:0] reg_addr; // Registered HADDRS
+ reg [1:0] reg_auser;
+ reg reg_write; // Registered HWRITES
+ reg [2:0] reg_size; // Registered HSIZES
+ reg [2:0] reg_burst; // Registered HBURSTS
+ reg [3:0] reg_prot; // Registered HPROTS
+ reg [3:0] reg_master; // Registerd HMASTERS
+ reg reg_mastlock; // Registered HMASTLOCKS
+ reg [1:0] transb; // HTRANS output used for burst information
+ reg [1:0] trans_int; // HTRANS output
+ reg [2:0] burst_int; // HBURST output
+ reg [3:0] offset_addr; // Address offset for boundary logic
+ reg [3:0] check_addr; // Address check for wrapped bursts
+ reg burst_override; // Registered burst_override_next
+ wire burst_override_next; // Indicates burst has been over-ridden
+ reg bound; // Registered version of bound_next
+ wire bound_next; // Indicates boundary wrapping
+ wire bound_en; // Clock-enable for bound register
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Holding Registers
+// -----------------------------------------------------------------------------
+// Each input port has a holding register associated with it and a mux to
+// select between the register and the direct input path. The control of
+// the mux is done simply by selecting the holding register when it is loaded
+// with a pending transfer, otherwise the straight through path is used.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_holding_reg_seq1
+ if (~HRESETn)
+ begin
+ reg_trans <= 2'b00;
+ reg_addr <= {32{1'b0}};
+ reg_auser <= {2{1'b0}};
+ reg_write <= 1'b0 ;
+ reg_size <= 3'b000;
+ reg_burst <= 3'b000;
+ reg_prot <= {4{1'b0}};
+ reg_master <= 4'b0000;
+ reg_mastlock <= 1'b0 ;
+ end
+ else
+ if (load_reg)
+ begin
+ reg_trans <= HTRANSS;
+ reg_addr <= HADDRS;
+ reg_auser <= HAUSERS;
+ reg_write <= HWRITES;
+ reg_size <= HSIZES;
+ reg_burst <= HBURSTS;
+ reg_prot <= HPROTS;
+ reg_master <= HMASTERS;
+ reg_mastlock <= HMASTLOCKS;
+ end
+ end
+
+ // addr_valid indicates the address phase of an active (non-BUSY/IDLE)
+ // transfer to this slave port
+ assign addr_valid = ( HSELS & HTRANSS[1] );
+
+ // The holding register is loaded whenever there is a transfer on the input
+ // port which is validated by active HREADYS
+ assign load_reg = ( addr_valid & HREADYS );
+
+ // data_valid register
+ // addr_valid indicates the data phase of an active (non-BUSY/IDLE)
+ // transfer to this slave port. A valid response (HREADY, HRESP) must be
+ // generated
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_valid
+ if (~HRESETn)
+ data_valid <= 1'b0;
+ else
+ if (HREADYS)
+ data_valid <= addr_valid;
+ end
+
+// -----------------------------------------------------------------------------
+// Generate HeldTran
+// -----------------------------------------------------------------------------
+// The HeldTran signal is used to indicate when there is an active transfer
+// being presented to the output stage, either passing straight through or from
+// the holding register.
+
+ // pend_tran indicates that an active transfer presented to this
+ // slave cannot complete immediately. It is always set after the
+ // load_reg signal has been active. When set, it is cleared when the
+ // transfer is being driven onto the selected slave (as indicated by
+ // active_ip being high) and HREADY from the selected slave is high.
+ assign pend_tran = (load_reg & (~active_ip)) ? 1'b1 :
+ (active_ip & readyout_ip) ? 1'b0 : pend_tran_reg;
+
+ // pend_tran_reg indicates that an active transfer was accepted by the input
+ // stage,but not by the output stage, and so the holding registers should be
+ // used
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_pend_tran_reg
+ if (~HRESETn)
+ pend_tran_reg <= 1'b0;
+ else
+ pend_tran_reg <= pend_tran;
+ end
+
+ // held_tran_ip indicates an active transfer, and is held whilst that transfer is
+ // in the holding registers. It passes to the output stage where it acts as
+ // a request line to the arbitration scheme
+ assign held_tran_ip = (load_reg | pend_tran_reg);
+
+ // The output from this stage is selected from the holding register when
+ // there is a held transfer. Otherwise the direct path is used.
+
+ always @ ( pend_tran_reg or HSELS or HTRANSS or HADDRS or HWRITES or
+ HSIZES or HBURSTS or HPROTS or HMASTERS or HMASTLOCKS or
+ HAUSERS or reg_auser or
+ reg_addr or reg_write or reg_size or reg_burst or reg_prot or
+ reg_master or reg_mastlock
+ )
+ begin : p_mux_comb
+ if (~pend_tran_reg)
+ begin
+ sel_ip = HSELS;
+ trans_int = HTRANSS;
+ addr_ip = HADDRS;
+ auser_ip = HAUSERS;
+ write_ip = HWRITES;
+ size_ip = HSIZES;
+ burst_int = HBURSTS;
+ prot_ip = HPROTS;
+ master_ip = HMASTERS;
+ mastlock_ip = HMASTLOCKS;
+ end
+ else
+ begin
+ sel_ip = 1'b1;
+ trans_int = `TRN_NONSEQ;
+ addr_ip = reg_addr;
+ auser_ip = reg_auser;
+ write_ip = reg_write;
+ size_ip = reg_size;
+ burst_int = reg_burst;
+ prot_ip = reg_prot;
+ master_ip = reg_master;
+ mastlock_ip = reg_mastlock;
+ end
+ end
+
+ // The transb output is used to select the correct Burst value when completing
+ // an interrupted defined-lenght burst.
+
+ always @ (pend_tran_reg or HTRANSS or reg_trans)
+ begin : p_transb_comb
+ if (~pend_tran_reg)
+ transb = HTRANSS;
+ else
+ transb = reg_trans;
+ end // block: p_transb_comb
+
+
+ // Convert SEQ->NONSEQ and BUSY->IDLE when an address boundary is crossed
+ // whilst the burst type is being over-ridden, i.e. when completing an
+ // interrupted wrapping burst.
+ assign trans_ip = (burst_override & bound) ? {trans_int[1], 1'b0}
+ : trans_int;
+
+ assign burst_ip = (burst_override & (transb != `TRN_NONSEQ)) ? `BUR_INCR
+ : burst_int;
+
+// -----------------------------------------------------------------------------
+// HREADYOUT Generation
+// -----------------------------------------------------------------------------
+// There are three possible sources for the HREADYOUT signal.
+// - It is driven LOW when there is a held transfer.
+// - It is driven HIGH when not Selected or for Idle/Busy transfers.
+// - At all other times it is driven from the appropriate shared
+// slave.
+
+ always @ (data_valid or pend_tran_reg or readyout_ip or resp_ip)
+ begin : p_ready_comb
+ if (~data_valid)
+ begin
+ HREADYOUTS = 1'b1;
+ HRESPS = `RSP_OKAY;
+ end
+ else if (pend_tran_reg)
+ begin
+ HREADYOUTS = 1'b0;
+ HRESPS = `RSP_OKAY;
+ end
+ else
+ begin
+ HREADYOUTS = readyout_ip;
+ HRESPS = resp_ip;
+ end
+ end // block: p_ready_comb
+
+// -----------------------------------------------------------------------------
+// Early Burst Termination
+// -----------------------------------------------------------------------------
+// There are times when the output stage will switch to another input port
+// without allowing the current burst to complete. In these cases the HTRANS
+// and HBURST signals need to be overriden to ensure that the transfers
+// reaching the output port meet the AHB specification.
+
+ assign burst_override_next = ( (HTRANSS == `TRN_NONSEQ) |
+ (HTRANSS == `TRN_IDLE) ) ? 1'b0
+ : ( (HTRANSS ==`TRN_SEQ) &
+ load_reg &
+ (~active_ip) ) ? 1'b1
+ : burst_override;
+
+ // burst_override register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_overrideseq
+ if (~HRESETn)
+ burst_override <= 1'b0;
+ else
+ if (HREADYS)
+ burst_override <= burst_override_next;
+ end // block: p_burst_overrideseq
+
+// -----------------------------------------------------------------------------
+// Boundary Checking Logic
+// -----------------------------------------------------------------------------
+ // offset_addr
+ always @ (HADDRS or HSIZES)
+ begin : p_offset_addr_comb
+ case (HSIZES)
+ 3'b000 : offset_addr = HADDRS[3:0];
+ 3'b001 : offset_addr = HADDRS[4:1];
+ 3'b010 : offset_addr = HADDRS[5:2];
+ 3'b011 : offset_addr = HADDRS[6:3];
+
+ 3'b100, 3'b101, 3'b110, 3'b111 :
+ offset_addr = HADDRS[3:0]; // Sizes >= 128-bits are not supported
+
+ default : offset_addr = 4'bxxxx;
+ endcase
+ end
+
+ // check_addr
+ always @ (offset_addr or HBURSTS)
+ begin : p_check_addr_comb
+ case (HBURSTS)
+ `BUR_WRAP4 : begin
+ check_addr[1:0] = offset_addr[1:0];
+ check_addr[3:2] = 2'b11;
+ end
+
+ `BUR_WRAP8 : begin
+ check_addr[2:0] = offset_addr[2:0];
+ check_addr[3] = 1'b1;
+ end
+
+ `BUR_WRAP16 :
+ check_addr[3:0] = offset_addr[3:0];
+
+ `BUR_SINGLE, `BUR_INCR, `BUR_INCR4, `BUR_INCR8, `BUR_INCR16 :
+ check_addr[3:0] = 4'b0000;
+
+ default : check_addr[3:0] = 4'bxxxx;
+ endcase
+ end
+
+ assign bound_next = ( check_addr == 4'b1111 );
+
+ assign bound_en = ( HTRANSS[1] & HREADYS );
+
+ // bound register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_bound_seq
+ if (~HRESETn)
+ bound <= 1'b0;
+ else
+ if (bound_en)
+ bound <= bound_next;
+ end
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
new file mode 100644
index 0000000000000000000000000000000000000000..dad3668a66c9b50da68807874c39ffdb45ce25fd
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
@@ -0,0 +1,630 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has full connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_MatrixDecode_adp (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Internal address remapping control
+ remapping_dec,
+
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+ // Bus-switch output 0
+ active_dec0,
+ readyout_dec0,
+ resp_dec0,
+ rdata_dec0,
+ ruser_dec0,
+
+ // Bus-switch output 1
+ active_dec1,
+ readyout_dec1,
+ resp_dec1,
+ rdata_dec1,
+ ruser_dec1,
+
+ // Bus-switch output 2
+ active_dec2,
+ readyout_dec2,
+ resp_dec2,
+ rdata_dec2,
+ ruser_dec2,
+
+ // Bus-switch output 3
+ active_dec3,
+ readyout_dec3,
+ resp_dec3,
+ rdata_dec3,
+ ruser_dec3,
+
+ // Bus-switch output 4
+ active_dec4,
+ readyout_dec4,
+ resp_dec4,
+ rdata_dec4,
+ ruser_dec4,
+
+ // Bus-switch output 5
+ active_dec5,
+ readyout_dec5,
+ resp_dec5,
+ rdata_dec5,
+ ruser_dec5,
+
+ // Bus-switch output 6
+ active_dec6,
+ readyout_dec6,
+ resp_dec6,
+ rdata_dec6,
+ ruser_dec6,
+
+ // Output port selection signals
+ sel_dec0,
+ sel_dec1,
+ sel_dec2,
+ sel_dec3,
+ sel_dec4,
+ sel_dec5,
+ sel_dec6,
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+ HRUSERS,
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // Internal address remapping control
+ input [0:0] remapping_dec; // Internal remap signal
+
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [31:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ input active_dec0; // Output stage MI0 active_dec signal
+ input readyout_dec0; // HREADYOUT input
+ input [1:0] resp_dec0; // HRESP input
+ input [31:0] rdata_dec0; // HRDATA input
+ input [1:0] ruser_dec0; // HRUSER input
+
+ // Bus-switch output MI1
+ input active_dec1; // Output stage MI1 active_dec signal
+ input readyout_dec1; // HREADYOUT input
+ input [1:0] resp_dec1; // HRESP input
+ input [31:0] rdata_dec1; // HRDATA input
+ input [1:0] ruser_dec1; // HRUSER input
+
+ // Bus-switch output MI2
+ input active_dec2; // Output stage MI2 active_dec signal
+ input readyout_dec2; // HREADYOUT input
+ input [1:0] resp_dec2; // HRESP input
+ input [31:0] rdata_dec2; // HRDATA input
+ input [1:0] ruser_dec2; // HRUSER input
+
+ // Bus-switch output MI3
+ input active_dec3; // Output stage MI3 active_dec signal
+ input readyout_dec3; // HREADYOUT input
+ input [1:0] resp_dec3; // HRESP input
+ input [31:0] rdata_dec3; // HRDATA input
+ input [1:0] ruser_dec3; // HRUSER input
+
+ // Bus-switch output MI4
+ input active_dec4; // Output stage MI4 active_dec signal
+ input readyout_dec4; // HREADYOUT input
+ input [1:0] resp_dec4; // HRESP input
+ input [31:0] rdata_dec4; // HRDATA input
+ input [1:0] ruser_dec4; // HRUSER input
+
+ // Bus-switch output MI5
+ input active_dec5; // Output stage MI5 active_dec signal
+ input readyout_dec5; // HREADYOUT input
+ input [1:0] resp_dec5; // HRESP input
+ input [31:0] rdata_dec5; // HRDATA input
+ input [1:0] ruser_dec5; // HRUSER input
+
+ // Bus-switch output MI6
+ input active_dec6; // Output stage MI6 active_dec signal
+ input readyout_dec6; // HREADYOUT input
+ input [1:0] resp_dec6; // HRESP input
+ input [31:0] rdata_dec6; // HRDATA input
+ input [1:0] ruser_dec6; // HRUSER input
+
+ // Output port selection signals
+ output sel_dec0; // HSEL output
+ output sel_dec1; // HSEL output
+ output sel_dec2; // HSEL output
+ output sel_dec3; // HSEL output
+ output sel_dec4; // HSEL output
+ output sel_dec5; // HSEL output
+ output sel_dec6; // HSEL output
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [1:0] HRESPS; // Transfer response
+ output [1:0] HRUSERS; // User read Data
+ output [31:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+ // Internal address remapping control
+ wire [0:0] remapping_dec; // Internal remap signal
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [31:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ wire active_dec0; // active_dec signal
+ wire readyout_dec0; // HREADYOUT input
+ wire [1:0] resp_dec0; // HRESP input
+ wire [31:0] rdata_dec0; // HRDATA input
+ wire [1:0] ruser_dec0; // HRUSER input
+ reg sel_dec0; // HSEL output
+
+ // Bus-switch output MI1
+ wire active_dec1; // active_dec signal
+ wire readyout_dec1; // HREADYOUT input
+ wire [1:0] resp_dec1; // HRESP input
+ wire [31:0] rdata_dec1; // HRDATA input
+ wire [1:0] ruser_dec1; // HRUSER input
+ reg sel_dec1; // HSEL output
+
+ // Bus-switch output MI2
+ wire active_dec2; // active_dec signal
+ wire readyout_dec2; // HREADYOUT input
+ wire [1:0] resp_dec2; // HRESP input
+ wire [31:0] rdata_dec2; // HRDATA input
+ wire [1:0] ruser_dec2; // HRUSER input
+ reg sel_dec2; // HSEL output
+
+ // Bus-switch output MI3
+ wire active_dec3; // active_dec signal
+ wire readyout_dec3; // HREADYOUT input
+ wire [1:0] resp_dec3; // HRESP input
+ wire [31:0] rdata_dec3; // HRDATA input
+ wire [1:0] ruser_dec3; // HRUSER input
+ reg sel_dec3; // HSEL output
+
+ // Bus-switch output MI4
+ wire active_dec4; // active_dec signal
+ wire readyout_dec4; // HREADYOUT input
+ wire [1:0] resp_dec4; // HRESP input
+ wire [31:0] rdata_dec4; // HRDATA input
+ wire [1:0] ruser_dec4; // HRUSER input
+ reg sel_dec4; // HSEL output
+
+ // Bus-switch output MI5
+ wire active_dec5; // active_dec signal
+ wire readyout_dec5; // HREADYOUT input
+ wire [1:0] resp_dec5; // HRESP input
+ wire [31:0] rdata_dec5; // HRDATA input
+ wire [1:0] ruser_dec5; // HRUSER input
+ reg sel_dec5; // HSEL output
+
+ // Bus-switch output MI6
+ wire active_dec6; // active_dec signal
+ wire readyout_dec6; // HREADYOUT input
+ wire [1:0] resp_dec6; // HRESP input
+ wire [31:0] rdata_dec6; // HRDATA input
+ wire [1:0] ruser_dec6; // HRUSER input
+ reg sel_dec6; // HSEL output
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [1:0] HRESPS; // Combinatorial HRESPS signal
+ reg [1:0] HRUSERS;
+ reg [31:0] HRDATAS; // Read data bus
+
+ reg [3:0] addr_out_port; // Address output ports
+ reg [3:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[31:10], which is not a hex character boundary
+
+ always @ (
+ decode_addr_dec or
+ remapping_dec or data_out_port or trans_dec
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+ case (remapping_dec) // Composition: REMAP[0]
+ 1'b0 : begin
+ // Unmoved address region 0x00000000-0x0fffffff
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+ // Static address region 0x10000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+ end
+
+ 1'b1 : begin
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[0]
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Unmoved address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+ // Static address region 0x10000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+ end
+
+ default : addr_out_port = {4{1'bx}};
+ endcase
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+ sel_dec0 = 1'b0;
+ sel_dec1 = 1'b0;
+ sel_dec2 = 1'b0;
+ sel_dec3 = 1'b0;
+ sel_dec4 = 1'b0;
+ sel_dec5 = 1'b0;
+ sel_dec6 = 1'b0;
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+ 4'b0000 : sel_dec0 = 1'b1;
+ 4'b0001 : sel_dec1 = 1'b1;
+ 4'b0010 : sel_dec2 = 1'b1;
+ 4'b0011 : sel_dec3 = 1'b1;
+ 4'b0100 : sel_dec4 = 1'b1;
+ 4'b0101 : sel_dec5 = 1'b1;
+ 4'b0110 : sel_dec6 = 1'b1;
+ 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+ sel_dec0 = 1'bx;
+ sel_dec1 = 1'bx;
+ sel_dec2 = 1'bx;
+ sel_dec3 = 1'bx;
+ sel_dec4 = 1'bx;
+ sel_dec5 = 1'bx;
+ sel_dec6 = 1'bx;
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+ active_dec0 or
+ active_dec1 or
+ active_dec2 or
+ active_dec3 or
+ active_dec4 or
+ active_dec5 or
+ active_dec6 or
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+ 4'b0000 : active_dec = active_dec0;
+ 4'b0001 : active_dec = active_dec1;
+ 4'b0010 : active_dec = active_dec2;
+ 4'b0011 : active_dec = active_dec3;
+ 4'b0100 : active_dec = active_dec4;
+ 4'b0101 : active_dec = active_dec5;
+ 4'b0110 : active_dec = active_dec6;
+ 4'b1000 : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= 4'b1000;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= 4'b1000;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+ readyout_dec0 or
+ readyout_dec1 or
+ readyout_dec2 or
+ readyout_dec3 or
+ readyout_dec4 or
+ readyout_dec5 or
+ readyout_dec6 or
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+ 4'b0000 : HREADYOUTS = readyout_dec0;
+ 4'b0001 : HREADYOUTS = readyout_dec1;
+ 4'b0010 : HREADYOUTS = readyout_dec2;
+ 4'b0011 : HREADYOUTS = readyout_dec3;
+ 4'b0100 : HREADYOUTS = readyout_dec4;
+ 4'b0101 : HREADYOUTS = readyout_dec5;
+ 4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+ resp_dec0 or
+ resp_dec1 or
+ resp_dec2 or
+ resp_dec3 or
+ resp_dec4 or
+ resp_dec5 or
+ resp_dec6 or
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+ 4'b0000 : HRESPS = resp_dec0;
+ 4'b0001 : HRESPS = resp_dec1;
+ 4'b0010 : HRESPS = resp_dec2;
+ 4'b0011 : HRESPS = resp_dec3;
+ 4'b0100 : HRESPS = resp_dec4;
+ 4'b0101 : HRESPS = resp_dec5;
+ 4'b0110 : HRESPS = resp_dec6;
+ 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+ rdata_dec0 or
+ rdata_dec1 or
+ rdata_dec2 or
+ rdata_dec3 or
+ rdata_dec4 or
+ rdata_dec5 or
+ rdata_dec6 or
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+ 4'b0000 : HRDATAS = rdata_dec0;
+ 4'b0001 : HRDATAS = rdata_dec1;
+ 4'b0010 : HRDATAS = rdata_dec2;
+ 4'b0011 : HRDATAS = rdata_dec3;
+ 4'b0100 : HRDATAS = rdata_dec4;
+ 4'b0101 : HRDATAS = rdata_dec5;
+ 4'b0110 : HRDATAS = rdata_dec6;
+ 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ default : HRDATAS = {32{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+
+ // HRUSERS output decode
+ always @ (
+ ruser_dec0 or
+ ruser_dec1 or
+ ruser_dec2 or
+ ruser_dec3 or
+ ruser_dec4 or
+ ruser_dec5 or
+ ruser_dec6 or
+ data_out_port
+ )
+ begin : p_ruser_comb
+ case (data_out_port)
+ 4'b0000 : HRUSERS = ruser_dec0;
+ 4'b0001 : HRUSERS = ruser_dec1;
+ 4'b0010 : HRUSERS = ruser_dec2;
+ 4'b0011 : HRUSERS = ruser_dec3;
+ 4'b0100 : HRUSERS = ruser_dec4;
+ 4'b0101 : HRUSERS = ruser_dec5;
+ 4'b0110 : HRUSERS = ruser_dec6;
+ 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
+ default : HRUSERS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_ruser_comb
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
new file mode 100644
index 0000000000000000000000000000000000000000..9e2b72d04a99cc3de014dbb458c5ec5d2cb0a676
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
@@ -0,0 +1,630 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has full connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_MatrixDecode_cpu (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Internal address remapping control
+ remapping_dec,
+
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+ // Bus-switch output 0
+ active_dec0,
+ readyout_dec0,
+ resp_dec0,
+ rdata_dec0,
+ ruser_dec0,
+
+ // Bus-switch output 1
+ active_dec1,
+ readyout_dec1,
+ resp_dec1,
+ rdata_dec1,
+ ruser_dec1,
+
+ // Bus-switch output 2
+ active_dec2,
+ readyout_dec2,
+ resp_dec2,
+ rdata_dec2,
+ ruser_dec2,
+
+ // Bus-switch output 3
+ active_dec3,
+ readyout_dec3,
+ resp_dec3,
+ rdata_dec3,
+ ruser_dec3,
+
+ // Bus-switch output 4
+ active_dec4,
+ readyout_dec4,
+ resp_dec4,
+ rdata_dec4,
+ ruser_dec4,
+
+ // Bus-switch output 5
+ active_dec5,
+ readyout_dec5,
+ resp_dec5,
+ rdata_dec5,
+ ruser_dec5,
+
+ // Bus-switch output 6
+ active_dec6,
+ readyout_dec6,
+ resp_dec6,
+ rdata_dec6,
+ ruser_dec6,
+
+ // Output port selection signals
+ sel_dec0,
+ sel_dec1,
+ sel_dec2,
+ sel_dec3,
+ sel_dec4,
+ sel_dec5,
+ sel_dec6,
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+ HRUSERS,
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // Internal address remapping control
+ input [0:0] remapping_dec; // Internal remap signal
+
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [31:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ input active_dec0; // Output stage MI0 active_dec signal
+ input readyout_dec0; // HREADYOUT input
+ input [1:0] resp_dec0; // HRESP input
+ input [31:0] rdata_dec0; // HRDATA input
+ input [1:0] ruser_dec0; // HRUSER input
+
+ // Bus-switch output MI1
+ input active_dec1; // Output stage MI1 active_dec signal
+ input readyout_dec1; // HREADYOUT input
+ input [1:0] resp_dec1; // HRESP input
+ input [31:0] rdata_dec1; // HRDATA input
+ input [1:0] ruser_dec1; // HRUSER input
+
+ // Bus-switch output MI2
+ input active_dec2; // Output stage MI2 active_dec signal
+ input readyout_dec2; // HREADYOUT input
+ input [1:0] resp_dec2; // HRESP input
+ input [31:0] rdata_dec2; // HRDATA input
+ input [1:0] ruser_dec2; // HRUSER input
+
+ // Bus-switch output MI3
+ input active_dec3; // Output stage MI3 active_dec signal
+ input readyout_dec3; // HREADYOUT input
+ input [1:0] resp_dec3; // HRESP input
+ input [31:0] rdata_dec3; // HRDATA input
+ input [1:0] ruser_dec3; // HRUSER input
+
+ // Bus-switch output MI4
+ input active_dec4; // Output stage MI4 active_dec signal
+ input readyout_dec4; // HREADYOUT input
+ input [1:0] resp_dec4; // HRESP input
+ input [31:0] rdata_dec4; // HRDATA input
+ input [1:0] ruser_dec4; // HRUSER input
+
+ // Bus-switch output MI5
+ input active_dec5; // Output stage MI5 active_dec signal
+ input readyout_dec5; // HREADYOUT input
+ input [1:0] resp_dec5; // HRESP input
+ input [31:0] rdata_dec5; // HRDATA input
+ input [1:0] ruser_dec5; // HRUSER input
+
+ // Bus-switch output MI6
+ input active_dec6; // Output stage MI6 active_dec signal
+ input readyout_dec6; // HREADYOUT input
+ input [1:0] resp_dec6; // HRESP input
+ input [31:0] rdata_dec6; // HRDATA input
+ input [1:0] ruser_dec6; // HRUSER input
+
+ // Output port selection signals
+ output sel_dec0; // HSEL output
+ output sel_dec1; // HSEL output
+ output sel_dec2; // HSEL output
+ output sel_dec3; // HSEL output
+ output sel_dec4; // HSEL output
+ output sel_dec5; // HSEL output
+ output sel_dec6; // HSEL output
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [1:0] HRESPS; // Transfer response
+ output [1:0] HRUSERS; // User read Data
+ output [31:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+ // Internal address remapping control
+ wire [0:0] remapping_dec; // Internal remap signal
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [31:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ wire active_dec0; // active_dec signal
+ wire readyout_dec0; // HREADYOUT input
+ wire [1:0] resp_dec0; // HRESP input
+ wire [31:0] rdata_dec0; // HRDATA input
+ wire [1:0] ruser_dec0; // HRUSER input
+ reg sel_dec0; // HSEL output
+
+ // Bus-switch output MI1
+ wire active_dec1; // active_dec signal
+ wire readyout_dec1; // HREADYOUT input
+ wire [1:0] resp_dec1; // HRESP input
+ wire [31:0] rdata_dec1; // HRDATA input
+ wire [1:0] ruser_dec1; // HRUSER input
+ reg sel_dec1; // HSEL output
+
+ // Bus-switch output MI2
+ wire active_dec2; // active_dec signal
+ wire readyout_dec2; // HREADYOUT input
+ wire [1:0] resp_dec2; // HRESP input
+ wire [31:0] rdata_dec2; // HRDATA input
+ wire [1:0] ruser_dec2; // HRUSER input
+ reg sel_dec2; // HSEL output
+
+ // Bus-switch output MI3
+ wire active_dec3; // active_dec signal
+ wire readyout_dec3; // HREADYOUT input
+ wire [1:0] resp_dec3; // HRESP input
+ wire [31:0] rdata_dec3; // HRDATA input
+ wire [1:0] ruser_dec3; // HRUSER input
+ reg sel_dec3; // HSEL output
+
+ // Bus-switch output MI4
+ wire active_dec4; // active_dec signal
+ wire readyout_dec4; // HREADYOUT input
+ wire [1:0] resp_dec4; // HRESP input
+ wire [31:0] rdata_dec4; // HRDATA input
+ wire [1:0] ruser_dec4; // HRUSER input
+ reg sel_dec4; // HSEL output
+
+ // Bus-switch output MI5
+ wire active_dec5; // active_dec signal
+ wire readyout_dec5; // HREADYOUT input
+ wire [1:0] resp_dec5; // HRESP input
+ wire [31:0] rdata_dec5; // HRDATA input
+ wire [1:0] ruser_dec5; // HRUSER input
+ reg sel_dec5; // HSEL output
+
+ // Bus-switch output MI6
+ wire active_dec6; // active_dec signal
+ wire readyout_dec6; // HREADYOUT input
+ wire [1:0] resp_dec6; // HRESP input
+ wire [31:0] rdata_dec6; // HRDATA input
+ wire [1:0] ruser_dec6; // HRUSER input
+ reg sel_dec6; // HSEL output
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [1:0] HRESPS; // Combinatorial HRESPS signal
+ reg [1:0] HRUSERS;
+ reg [31:0] HRDATAS; // Read data bus
+
+ reg [3:0] addr_out_port; // Address output ports
+ reg [3:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[31:10], which is not a hex character boundary
+
+ always @ (
+ decode_addr_dec or
+ remapping_dec or data_out_port or trans_dec
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+ case (remapping_dec) // Composition: REMAP[0]
+ 1'b0 : begin
+ // Unmoved address region 0x00000000-0x0fffffff
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+ // Static address region 0x10000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+ end
+
+ 1'b1 : begin
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[0]
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Unmoved address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+ // Static address region 0x10000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+ end
+
+ default : addr_out_port = {4{1'bx}};
+ endcase
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+ sel_dec0 = 1'b0;
+ sel_dec1 = 1'b0;
+ sel_dec2 = 1'b0;
+ sel_dec3 = 1'b0;
+ sel_dec4 = 1'b0;
+ sel_dec5 = 1'b0;
+ sel_dec6 = 1'b0;
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+ 4'b0000 : sel_dec0 = 1'b1;
+ 4'b0001 : sel_dec1 = 1'b1;
+ 4'b0010 : sel_dec2 = 1'b1;
+ 4'b0011 : sel_dec3 = 1'b1;
+ 4'b0100 : sel_dec4 = 1'b1;
+ 4'b0101 : sel_dec5 = 1'b1;
+ 4'b0110 : sel_dec6 = 1'b1;
+ 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+ sel_dec0 = 1'bx;
+ sel_dec1 = 1'bx;
+ sel_dec2 = 1'bx;
+ sel_dec3 = 1'bx;
+ sel_dec4 = 1'bx;
+ sel_dec5 = 1'bx;
+ sel_dec6 = 1'bx;
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+ active_dec0 or
+ active_dec1 or
+ active_dec2 or
+ active_dec3 or
+ active_dec4 or
+ active_dec5 or
+ active_dec6 or
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+ 4'b0000 : active_dec = active_dec0;
+ 4'b0001 : active_dec = active_dec1;
+ 4'b0010 : active_dec = active_dec2;
+ 4'b0011 : active_dec = active_dec3;
+ 4'b0100 : active_dec = active_dec4;
+ 4'b0101 : active_dec = active_dec5;
+ 4'b0110 : active_dec = active_dec6;
+ 4'b1000 : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= 4'b1000;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= 4'b1000;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+ readyout_dec0 or
+ readyout_dec1 or
+ readyout_dec2 or
+ readyout_dec3 or
+ readyout_dec4 or
+ readyout_dec5 or
+ readyout_dec6 or
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+ 4'b0000 : HREADYOUTS = readyout_dec0;
+ 4'b0001 : HREADYOUTS = readyout_dec1;
+ 4'b0010 : HREADYOUTS = readyout_dec2;
+ 4'b0011 : HREADYOUTS = readyout_dec3;
+ 4'b0100 : HREADYOUTS = readyout_dec4;
+ 4'b0101 : HREADYOUTS = readyout_dec5;
+ 4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+ resp_dec0 or
+ resp_dec1 or
+ resp_dec2 or
+ resp_dec3 or
+ resp_dec4 or
+ resp_dec5 or
+ resp_dec6 or
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+ 4'b0000 : HRESPS = resp_dec0;
+ 4'b0001 : HRESPS = resp_dec1;
+ 4'b0010 : HRESPS = resp_dec2;
+ 4'b0011 : HRESPS = resp_dec3;
+ 4'b0100 : HRESPS = resp_dec4;
+ 4'b0101 : HRESPS = resp_dec5;
+ 4'b0110 : HRESPS = resp_dec6;
+ 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+ rdata_dec0 or
+ rdata_dec1 or
+ rdata_dec2 or
+ rdata_dec3 or
+ rdata_dec4 or
+ rdata_dec5 or
+ rdata_dec6 or
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+ 4'b0000 : HRDATAS = rdata_dec0;
+ 4'b0001 : HRDATAS = rdata_dec1;
+ 4'b0010 : HRDATAS = rdata_dec2;
+ 4'b0011 : HRDATAS = rdata_dec3;
+ 4'b0100 : HRDATAS = rdata_dec4;
+ 4'b0101 : HRDATAS = rdata_dec5;
+ 4'b0110 : HRDATAS = rdata_dec6;
+ 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ default : HRDATAS = {32{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+
+ // HRUSERS output decode
+ always @ (
+ ruser_dec0 or
+ ruser_dec1 or
+ ruser_dec2 or
+ ruser_dec3 or
+ ruser_dec4 or
+ ruser_dec5 or
+ ruser_dec6 or
+ data_out_port
+ )
+ begin : p_ruser_comb
+ case (data_out_port)
+ 4'b0000 : HRUSERS = ruser_dec0;
+ 4'b0001 : HRUSERS = ruser_dec1;
+ 4'b0010 : HRUSERS = ruser_dec2;
+ 4'b0011 : HRUSERS = ruser_dec3;
+ 4'b0100 : HRUSERS = ruser_dec4;
+ 4'b0101 : HRUSERS = ruser_dec5;
+ 4'b0110 : HRUSERS = ruser_dec6;
+ 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
+ default : HRUSERS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_ruser_comb
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
new file mode 100644
index 0000000000000000000000000000000000000000..30b9ada8a2cf5e13140351b33ed80740fecc1a13
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
@@ -0,0 +1,566 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has full connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_MatrixDecode_dma (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+ // Bus-switch output 0
+ active_dec0,
+ readyout_dec0,
+ resp_dec0,
+ rdata_dec0,
+ ruser_dec0,
+
+ // Bus-switch output 1
+ active_dec1,
+ readyout_dec1,
+ resp_dec1,
+ rdata_dec1,
+ ruser_dec1,
+
+ // Bus-switch output 2
+ active_dec2,
+ readyout_dec2,
+ resp_dec2,
+ rdata_dec2,
+ ruser_dec2,
+
+ // Bus-switch output 3
+ active_dec3,
+ readyout_dec3,
+ resp_dec3,
+ rdata_dec3,
+ ruser_dec3,
+
+ // Bus-switch output 4
+ active_dec4,
+ readyout_dec4,
+ resp_dec4,
+ rdata_dec4,
+ ruser_dec4,
+
+ // Bus-switch output 5
+ active_dec5,
+ readyout_dec5,
+ resp_dec5,
+ rdata_dec5,
+ ruser_dec5,
+
+ // Bus-switch output 6
+ active_dec6,
+ readyout_dec6,
+ resp_dec6,
+ rdata_dec6,
+ ruser_dec6,
+
+ // Output port selection signals
+ sel_dec0,
+ sel_dec1,
+ sel_dec2,
+ sel_dec3,
+ sel_dec4,
+ sel_dec5,
+ sel_dec6,
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+ HRUSERS,
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [31:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ input active_dec0; // Output stage MI0 active_dec signal
+ input readyout_dec0; // HREADYOUT input
+ input [1:0] resp_dec0; // HRESP input
+ input [31:0] rdata_dec0; // HRDATA input
+ input [1:0] ruser_dec0; // HRUSER input
+
+ // Bus-switch output MI1
+ input active_dec1; // Output stage MI1 active_dec signal
+ input readyout_dec1; // HREADYOUT input
+ input [1:0] resp_dec1; // HRESP input
+ input [31:0] rdata_dec1; // HRDATA input
+ input [1:0] ruser_dec1; // HRUSER input
+
+ // Bus-switch output MI2
+ input active_dec2; // Output stage MI2 active_dec signal
+ input readyout_dec2; // HREADYOUT input
+ input [1:0] resp_dec2; // HRESP input
+ input [31:0] rdata_dec2; // HRDATA input
+ input [1:0] ruser_dec2; // HRUSER input
+
+ // Bus-switch output MI3
+ input active_dec3; // Output stage MI3 active_dec signal
+ input readyout_dec3; // HREADYOUT input
+ input [1:0] resp_dec3; // HRESP input
+ input [31:0] rdata_dec3; // HRDATA input
+ input [1:0] ruser_dec3; // HRUSER input
+
+ // Bus-switch output MI4
+ input active_dec4; // Output stage MI4 active_dec signal
+ input readyout_dec4; // HREADYOUT input
+ input [1:0] resp_dec4; // HRESP input
+ input [31:0] rdata_dec4; // HRDATA input
+ input [1:0] ruser_dec4; // HRUSER input
+
+ // Bus-switch output MI5
+ input active_dec5; // Output stage MI5 active_dec signal
+ input readyout_dec5; // HREADYOUT input
+ input [1:0] resp_dec5; // HRESP input
+ input [31:0] rdata_dec5; // HRDATA input
+ input [1:0] ruser_dec5; // HRUSER input
+
+ // Bus-switch output MI6
+ input active_dec6; // Output stage MI6 active_dec signal
+ input readyout_dec6; // HREADYOUT input
+ input [1:0] resp_dec6; // HRESP input
+ input [31:0] rdata_dec6; // HRDATA input
+ input [1:0] ruser_dec6; // HRUSER input
+
+ // Output port selection signals
+ output sel_dec0; // HSEL output
+ output sel_dec1; // HSEL output
+ output sel_dec2; // HSEL output
+ output sel_dec3; // HSEL output
+ output sel_dec4; // HSEL output
+ output sel_dec5; // HSEL output
+ output sel_dec6; // HSEL output
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [1:0] HRESPS; // Transfer response
+ output [1:0] HRUSERS; // User read Data
+ output [31:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [31:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ wire active_dec0; // active_dec signal
+ wire readyout_dec0; // HREADYOUT input
+ wire [1:0] resp_dec0; // HRESP input
+ wire [31:0] rdata_dec0; // HRDATA input
+ wire [1:0] ruser_dec0; // HRUSER input
+ reg sel_dec0; // HSEL output
+
+ // Bus-switch output MI1
+ wire active_dec1; // active_dec signal
+ wire readyout_dec1; // HREADYOUT input
+ wire [1:0] resp_dec1; // HRESP input
+ wire [31:0] rdata_dec1; // HRDATA input
+ wire [1:0] ruser_dec1; // HRUSER input
+ reg sel_dec1; // HSEL output
+
+ // Bus-switch output MI2
+ wire active_dec2; // active_dec signal
+ wire readyout_dec2; // HREADYOUT input
+ wire [1:0] resp_dec2; // HRESP input
+ wire [31:0] rdata_dec2; // HRDATA input
+ wire [1:0] ruser_dec2; // HRUSER input
+ reg sel_dec2; // HSEL output
+
+ // Bus-switch output MI3
+ wire active_dec3; // active_dec signal
+ wire readyout_dec3; // HREADYOUT input
+ wire [1:0] resp_dec3; // HRESP input
+ wire [31:0] rdata_dec3; // HRDATA input
+ wire [1:0] ruser_dec3; // HRUSER input
+ reg sel_dec3; // HSEL output
+
+ // Bus-switch output MI4
+ wire active_dec4; // active_dec signal
+ wire readyout_dec4; // HREADYOUT input
+ wire [1:0] resp_dec4; // HRESP input
+ wire [31:0] rdata_dec4; // HRDATA input
+ wire [1:0] ruser_dec4; // HRUSER input
+ reg sel_dec4; // HSEL output
+
+ // Bus-switch output MI5
+ wire active_dec5; // active_dec signal
+ wire readyout_dec5; // HREADYOUT input
+ wire [1:0] resp_dec5; // HRESP input
+ wire [31:0] rdata_dec5; // HRDATA input
+ wire [1:0] ruser_dec5; // HRUSER input
+ reg sel_dec5; // HSEL output
+
+ // Bus-switch output MI6
+ wire active_dec6; // active_dec signal
+ wire readyout_dec6; // HREADYOUT input
+ wire [1:0] resp_dec6; // HRESP input
+ wire [31:0] rdata_dec6; // HRDATA input
+ wire [1:0] ruser_dec6; // HRUSER input
+ reg sel_dec6; // HSEL output
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [1:0] HRESPS; // Combinatorial HRESPS signal
+ reg [1:0] HRUSERS;
+ reg [31:0] HRDATAS; // Read data bus
+
+ reg [3:0] addr_out_port; // Address output ports
+ reg [3:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[31:10], which is not a hex character boundary
+
+ always @ (
+ decode_addr_dec or data_out_port or trans_dec
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+ // Address region 0x10000000-0x1fffffff
+ if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+ // Address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+ sel_dec0 = 1'b0;
+ sel_dec1 = 1'b0;
+ sel_dec2 = 1'b0;
+ sel_dec3 = 1'b0;
+ sel_dec4 = 1'b0;
+ sel_dec5 = 1'b0;
+ sel_dec6 = 1'b0;
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+ 4'b0000 : sel_dec0 = 1'b1;
+ 4'b0001 : sel_dec1 = 1'b1;
+ 4'b0010 : sel_dec2 = 1'b1;
+ 4'b0011 : sel_dec3 = 1'b1;
+ 4'b0100 : sel_dec4 = 1'b1;
+ 4'b0101 : sel_dec5 = 1'b1;
+ 4'b0110 : sel_dec6 = 1'b1;
+ 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+ sel_dec0 = 1'bx;
+ sel_dec1 = 1'bx;
+ sel_dec2 = 1'bx;
+ sel_dec3 = 1'bx;
+ sel_dec4 = 1'bx;
+ sel_dec5 = 1'bx;
+ sel_dec6 = 1'bx;
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+ active_dec0 or
+ active_dec1 or
+ active_dec2 or
+ active_dec3 or
+ active_dec4 or
+ active_dec5 or
+ active_dec6 or
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+ 4'b0000 : active_dec = active_dec0;
+ 4'b0001 : active_dec = active_dec1;
+ 4'b0010 : active_dec = active_dec2;
+ 4'b0011 : active_dec = active_dec3;
+ 4'b0100 : active_dec = active_dec4;
+ 4'b0101 : active_dec = active_dec5;
+ 4'b0110 : active_dec = active_dec6;
+ 4'b1000 : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= 4'b1000;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= 4'b1000;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+ readyout_dec0 or
+ readyout_dec1 or
+ readyout_dec2 or
+ readyout_dec3 or
+ readyout_dec4 or
+ readyout_dec5 or
+ readyout_dec6 or
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+ 4'b0000 : HREADYOUTS = readyout_dec0;
+ 4'b0001 : HREADYOUTS = readyout_dec1;
+ 4'b0010 : HREADYOUTS = readyout_dec2;
+ 4'b0011 : HREADYOUTS = readyout_dec3;
+ 4'b0100 : HREADYOUTS = readyout_dec4;
+ 4'b0101 : HREADYOUTS = readyout_dec5;
+ 4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+ resp_dec0 or
+ resp_dec1 or
+ resp_dec2 or
+ resp_dec3 or
+ resp_dec4 or
+ resp_dec5 or
+ resp_dec6 or
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+ 4'b0000 : HRESPS = resp_dec0;
+ 4'b0001 : HRESPS = resp_dec1;
+ 4'b0010 : HRESPS = resp_dec2;
+ 4'b0011 : HRESPS = resp_dec3;
+ 4'b0100 : HRESPS = resp_dec4;
+ 4'b0101 : HRESPS = resp_dec5;
+ 4'b0110 : HRESPS = resp_dec6;
+ 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+ rdata_dec0 or
+ rdata_dec1 or
+ rdata_dec2 or
+ rdata_dec3 or
+ rdata_dec4 or
+ rdata_dec5 or
+ rdata_dec6 or
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+ 4'b0000 : HRDATAS = rdata_dec0;
+ 4'b0001 : HRDATAS = rdata_dec1;
+ 4'b0010 : HRDATAS = rdata_dec2;
+ 4'b0011 : HRDATAS = rdata_dec3;
+ 4'b0100 : HRDATAS = rdata_dec4;
+ 4'b0101 : HRDATAS = rdata_dec5;
+ 4'b0110 : HRDATAS = rdata_dec6;
+ 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ default : HRDATAS = {32{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+
+ // HRUSERS output decode
+ always @ (
+ ruser_dec0 or
+ ruser_dec1 or
+ ruser_dec2 or
+ ruser_dec3 or
+ ruser_dec4 or
+ ruser_dec5 or
+ ruser_dec6 or
+ data_out_port
+ )
+ begin : p_ruser_comb
+ case (data_out_port)
+ 4'b0000 : HRUSERS = ruser_dec0;
+ 4'b0001 : HRUSERS = ruser_dec1;
+ 4'b0010 : HRUSERS = ruser_dec2;
+ 4'b0011 : HRUSERS = ruser_dec3;
+ 4'b0100 : HRUSERS = ruser_dec4;
+ 4'b0101 : HRUSERS = ruser_dec5;
+ 4'b0110 : HRUSERS = ruser_dec6;
+ 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
+ default : HRUSERS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_ruser_comb
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
new file mode 100644
index 0000000000000000000000000000000000000000..d80c2801cf81512c7e5bf257d9baac108dc80f70
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
@@ -0,0 +1,566 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has full connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_MatrixDecode_dma2 (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+ // Bus-switch output 0
+ active_dec0,
+ readyout_dec0,
+ resp_dec0,
+ rdata_dec0,
+ ruser_dec0,
+
+ // Bus-switch output 1
+ active_dec1,
+ readyout_dec1,
+ resp_dec1,
+ rdata_dec1,
+ ruser_dec1,
+
+ // Bus-switch output 2
+ active_dec2,
+ readyout_dec2,
+ resp_dec2,
+ rdata_dec2,
+ ruser_dec2,
+
+ // Bus-switch output 3
+ active_dec3,
+ readyout_dec3,
+ resp_dec3,
+ rdata_dec3,
+ ruser_dec3,
+
+ // Bus-switch output 4
+ active_dec4,
+ readyout_dec4,
+ resp_dec4,
+ rdata_dec4,
+ ruser_dec4,
+
+ // Bus-switch output 5
+ active_dec5,
+ readyout_dec5,
+ resp_dec5,
+ rdata_dec5,
+ ruser_dec5,
+
+ // Bus-switch output 6
+ active_dec6,
+ readyout_dec6,
+ resp_dec6,
+ rdata_dec6,
+ ruser_dec6,
+
+ // Output port selection signals
+ sel_dec0,
+ sel_dec1,
+ sel_dec2,
+ sel_dec3,
+ sel_dec4,
+ sel_dec5,
+ sel_dec6,
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+ HRUSERS,
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [31:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ input active_dec0; // Output stage MI0 active_dec signal
+ input readyout_dec0; // HREADYOUT input
+ input [1:0] resp_dec0; // HRESP input
+ input [31:0] rdata_dec0; // HRDATA input
+ input [1:0] ruser_dec0; // HRUSER input
+
+ // Bus-switch output MI1
+ input active_dec1; // Output stage MI1 active_dec signal
+ input readyout_dec1; // HREADYOUT input
+ input [1:0] resp_dec1; // HRESP input
+ input [31:0] rdata_dec1; // HRDATA input
+ input [1:0] ruser_dec1; // HRUSER input
+
+ // Bus-switch output MI2
+ input active_dec2; // Output stage MI2 active_dec signal
+ input readyout_dec2; // HREADYOUT input
+ input [1:0] resp_dec2; // HRESP input
+ input [31:0] rdata_dec2; // HRDATA input
+ input [1:0] ruser_dec2; // HRUSER input
+
+ // Bus-switch output MI3
+ input active_dec3; // Output stage MI3 active_dec signal
+ input readyout_dec3; // HREADYOUT input
+ input [1:0] resp_dec3; // HRESP input
+ input [31:0] rdata_dec3; // HRDATA input
+ input [1:0] ruser_dec3; // HRUSER input
+
+ // Bus-switch output MI4
+ input active_dec4; // Output stage MI4 active_dec signal
+ input readyout_dec4; // HREADYOUT input
+ input [1:0] resp_dec4; // HRESP input
+ input [31:0] rdata_dec4; // HRDATA input
+ input [1:0] ruser_dec4; // HRUSER input
+
+ // Bus-switch output MI5
+ input active_dec5; // Output stage MI5 active_dec signal
+ input readyout_dec5; // HREADYOUT input
+ input [1:0] resp_dec5; // HRESP input
+ input [31:0] rdata_dec5; // HRDATA input
+ input [1:0] ruser_dec5; // HRUSER input
+
+ // Bus-switch output MI6
+ input active_dec6; // Output stage MI6 active_dec signal
+ input readyout_dec6; // HREADYOUT input
+ input [1:0] resp_dec6; // HRESP input
+ input [31:0] rdata_dec6; // HRDATA input
+ input [1:0] ruser_dec6; // HRUSER input
+
+ // Output port selection signals
+ output sel_dec0; // HSEL output
+ output sel_dec1; // HSEL output
+ output sel_dec2; // HSEL output
+ output sel_dec3; // HSEL output
+ output sel_dec4; // HSEL output
+ output sel_dec5; // HSEL output
+ output sel_dec6; // HSEL output
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [1:0] HRESPS; // Transfer response
+ output [1:0] HRUSERS; // User read Data
+ output [31:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [31:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ wire active_dec0; // active_dec signal
+ wire readyout_dec0; // HREADYOUT input
+ wire [1:0] resp_dec0; // HRESP input
+ wire [31:0] rdata_dec0; // HRDATA input
+ wire [1:0] ruser_dec0; // HRUSER input
+ reg sel_dec0; // HSEL output
+
+ // Bus-switch output MI1
+ wire active_dec1; // active_dec signal
+ wire readyout_dec1; // HREADYOUT input
+ wire [1:0] resp_dec1; // HRESP input
+ wire [31:0] rdata_dec1; // HRDATA input
+ wire [1:0] ruser_dec1; // HRUSER input
+ reg sel_dec1; // HSEL output
+
+ // Bus-switch output MI2
+ wire active_dec2; // active_dec signal
+ wire readyout_dec2; // HREADYOUT input
+ wire [1:0] resp_dec2; // HRESP input
+ wire [31:0] rdata_dec2; // HRDATA input
+ wire [1:0] ruser_dec2; // HRUSER input
+ reg sel_dec2; // HSEL output
+
+ // Bus-switch output MI3
+ wire active_dec3; // active_dec signal
+ wire readyout_dec3; // HREADYOUT input
+ wire [1:0] resp_dec3; // HRESP input
+ wire [31:0] rdata_dec3; // HRDATA input
+ wire [1:0] ruser_dec3; // HRUSER input
+ reg sel_dec3; // HSEL output
+
+ // Bus-switch output MI4
+ wire active_dec4; // active_dec signal
+ wire readyout_dec4; // HREADYOUT input
+ wire [1:0] resp_dec4; // HRESP input
+ wire [31:0] rdata_dec4; // HRDATA input
+ wire [1:0] ruser_dec4; // HRUSER input
+ reg sel_dec4; // HSEL output
+
+ // Bus-switch output MI5
+ wire active_dec5; // active_dec signal
+ wire readyout_dec5; // HREADYOUT input
+ wire [1:0] resp_dec5; // HRESP input
+ wire [31:0] rdata_dec5; // HRDATA input
+ wire [1:0] ruser_dec5; // HRUSER input
+ reg sel_dec5; // HSEL output
+
+ // Bus-switch output MI6
+ wire active_dec6; // active_dec signal
+ wire readyout_dec6; // HREADYOUT input
+ wire [1:0] resp_dec6; // HRESP input
+ wire [31:0] rdata_dec6; // HRDATA input
+ wire [1:0] ruser_dec6; // HRUSER input
+ reg sel_dec6; // HSEL output
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [1:0] HRESPS; // Combinatorial HRESPS signal
+ reg [1:0] HRUSERS;
+ reg [31:0] HRDATAS; // Read data bus
+
+ reg [3:0] addr_out_port; // Address output ports
+ reg [3:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[31:10], which is not a hex character boundary
+
+ always @ (
+ decode_addr_dec or data_out_port or trans_dec
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+ // Address region 0x10000000-0x1fffffff
+ if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+ // Address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+ sel_dec0 = 1'b0;
+ sel_dec1 = 1'b0;
+ sel_dec2 = 1'b0;
+ sel_dec3 = 1'b0;
+ sel_dec4 = 1'b0;
+ sel_dec5 = 1'b0;
+ sel_dec6 = 1'b0;
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+ 4'b0000 : sel_dec0 = 1'b1;
+ 4'b0001 : sel_dec1 = 1'b1;
+ 4'b0010 : sel_dec2 = 1'b1;
+ 4'b0011 : sel_dec3 = 1'b1;
+ 4'b0100 : sel_dec4 = 1'b1;
+ 4'b0101 : sel_dec5 = 1'b1;
+ 4'b0110 : sel_dec6 = 1'b1;
+ 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+ sel_dec0 = 1'bx;
+ sel_dec1 = 1'bx;
+ sel_dec2 = 1'bx;
+ sel_dec3 = 1'bx;
+ sel_dec4 = 1'bx;
+ sel_dec5 = 1'bx;
+ sel_dec6 = 1'bx;
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+ active_dec0 or
+ active_dec1 or
+ active_dec2 or
+ active_dec3 or
+ active_dec4 or
+ active_dec5 or
+ active_dec6 or
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+ 4'b0000 : active_dec = active_dec0;
+ 4'b0001 : active_dec = active_dec1;
+ 4'b0010 : active_dec = active_dec2;
+ 4'b0011 : active_dec = active_dec3;
+ 4'b0100 : active_dec = active_dec4;
+ 4'b0101 : active_dec = active_dec5;
+ 4'b0110 : active_dec = active_dec6;
+ 4'b1000 : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= 4'b1000;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= 4'b1000;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+ readyout_dec0 or
+ readyout_dec1 or
+ readyout_dec2 or
+ readyout_dec3 or
+ readyout_dec4 or
+ readyout_dec5 or
+ readyout_dec6 or
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+ 4'b0000 : HREADYOUTS = readyout_dec0;
+ 4'b0001 : HREADYOUTS = readyout_dec1;
+ 4'b0010 : HREADYOUTS = readyout_dec2;
+ 4'b0011 : HREADYOUTS = readyout_dec3;
+ 4'b0100 : HREADYOUTS = readyout_dec4;
+ 4'b0101 : HREADYOUTS = readyout_dec5;
+ 4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+ resp_dec0 or
+ resp_dec1 or
+ resp_dec2 or
+ resp_dec3 or
+ resp_dec4 or
+ resp_dec5 or
+ resp_dec6 or
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+ 4'b0000 : HRESPS = resp_dec0;
+ 4'b0001 : HRESPS = resp_dec1;
+ 4'b0010 : HRESPS = resp_dec2;
+ 4'b0011 : HRESPS = resp_dec3;
+ 4'b0100 : HRESPS = resp_dec4;
+ 4'b0101 : HRESPS = resp_dec5;
+ 4'b0110 : HRESPS = resp_dec6;
+ 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+ rdata_dec0 or
+ rdata_dec1 or
+ rdata_dec2 or
+ rdata_dec3 or
+ rdata_dec4 or
+ rdata_dec5 or
+ rdata_dec6 or
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+ 4'b0000 : HRDATAS = rdata_dec0;
+ 4'b0001 : HRDATAS = rdata_dec1;
+ 4'b0010 : HRDATAS = rdata_dec2;
+ 4'b0011 : HRDATAS = rdata_dec3;
+ 4'b0100 : HRDATAS = rdata_dec4;
+ 4'b0101 : HRDATAS = rdata_dec5;
+ 4'b0110 : HRDATAS = rdata_dec6;
+ 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ default : HRDATAS = {32{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+
+ // HRUSERS output decode
+ always @ (
+ ruser_dec0 or
+ ruser_dec1 or
+ ruser_dec2 or
+ ruser_dec3 or
+ ruser_dec4 or
+ ruser_dec5 or
+ ruser_dec6 or
+ data_out_port
+ )
+ begin : p_ruser_comb
+ case (data_out_port)
+ 4'b0000 : HRUSERS = ruser_dec0;
+ 4'b0001 : HRUSERS = ruser_dec1;
+ 4'b0010 : HRUSERS = ruser_dec2;
+ 4'b0011 : HRUSERS = ruser_dec3;
+ 4'b0100 : HRUSERS = ruser_dec4;
+ 4'b0101 : HRUSERS = ruser_dec5;
+ 4'b0110 : HRUSERS = ruser_dec6;
+ 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
+ default : HRUSERS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_ruser_comb
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
new file mode 100644
index 0000000000000000000000000000000000000000..98779fd6181c35f359350871b613f1828663fb59
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
@@ -0,0 +1,628 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has full connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+`timescale 1ns/1ps
+
+
+module soclabs_4x7_SlaveOutput (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ auser_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ wuser_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ auser_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ wuser_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ auser_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ wuser_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ auser_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ wuser_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HAUSERM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWUSERM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] auser_op0; // Port 0 HAUSER signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input [1:0] wuser_op0; // Port 0 HWUSER signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] auser_op1; // Port 1 HAUSER signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input [1:0] wuser_op1; // Port 1 HWUSER signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] auser_op2; // Port 2 HAUSER signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input [1:0] wuser_op2; // Port 2 HWUSER signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] auser_op3; // Port 3 HAUSER signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input [1:0] wuser_op3; // Port 3 HWUSER signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HAUSERM; // User Address bus
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [1:0] HWUSERM; // User data bus
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] auser_op0; // Port 0 HAUSER signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire [1:0] wuser_op0; // Port 0 HWUSER signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] auser_op1; // Port 1 HAUSER signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire [1:0] wuser_op1; // Port 1 HWUSER signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] auser_op2; // Port 2 HAUSER signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire [1:0] wuser_op2; // Port 2 HWUSER signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] auser_op3; // Port 3 HAUSER signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire [1:0] wuser_op3; // Port 3 HWUSER signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ reg [1:0] HAUSERM; // User Address bus
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [1:0] HWUSERM; // User data bus
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ soclabs_4x7_Arbiter u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ auser_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ auser_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ auser_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ auser_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ HAUSERM = {2{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ HAUSERM = auser_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ HAUSERM = auser_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ HAUSERM = auser_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ HAUSERM = auser_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ HAUSERM = {2{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+ // HWUSERM output decode
+ always @ (
+ wuser_op0 or
+ wuser_op1 or
+ wuser_op2 or
+ wuser_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_wuser_mux
+ // Default value
+ HWUSERM = {2{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWUSERM = wuser_op0;
+ 2'b01 : HWUSERM = wuser_op1;
+ 2'b10 : HWUSERM = wuser_op2;
+ 2'b11 : HWUSERM = wuser_op3;
+ default : HWUSERM = {2{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_wuser_mux
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
new file mode 100755
index 0000000000000000000000000000000000000000..013fe5916555e5156414246adc72f4a61dbd58eb
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
@@ -0,0 +1,327 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<output_arb_name>> (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ input req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [<<idw_si>>:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wire req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [<<idw_si>>:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [<<idw_si>>:0] addr_in_port_next; // D-input of addr_in_port
+ reg [<<idw_si>>:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ else if ( req_port<<in>> | ( (i_addr_in_port == <<idw_si_v>>'b<<bin_in>>) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = <<idw_si_v>>'b<<bin_in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {<<idw_si_v>>{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
new file mode 100755
index 0000000000000000000000000000000000000000..bd24a8dcdf8b8e4ca40d59eac2626b5aa661d858
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
@@ -0,0 +1,458 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<matrix_decode_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+//---------------------------- << start remap >> -------------------------------
+ // Internal address remapping control
+ remapping_dec,
+
+//----------------------------- << end remap >> --------------------------------
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch output <<out>>
+ active_dec<<out>>,
+ readyout_dec<<out>>,
+ resp_dec<<out>>,
+ rdata_dec<<out>>,
+//---------------------------- << start user >> --------------------------------
+ ruser_dec<<out>>,
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ // Output port selection signals
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ sel_dec<<out>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+//---------------------------- << start user >> --------------------------------
+ HRUSERS,
+//----------------------------- << end user >> ---------------------------------
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+//---------------------------- << start remap >> -------------------------------
+ // Internal address remapping control
+ input [<<idw_remap>>:0] remapping_dec; // Internal remap signal
+
+//----------------------------- << end remap >> --------------------------------
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [<<addr>>:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch output MI<<out>>
+ input active_dec<<out>>; // Output stage MI<<out>> active_dec signal
+ input readyout_dec<<out>>; // HREADYOUT input
+ input [<<resp>>:0] resp_dec<<out>>; // HRESP input
+ input [<<data>>:0] rdata_dec<<out>>; // HRDATA input
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] ruser_dec<<out>>; // HRUSER input
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ // Output port selection signals
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ output sel_dec<<out>>; // HSEL output
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [<<resp>>:0] HRESPS; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HRUSERS; // User read Data
+//----------------------------- << end user >> ---------------------------------
+ output [<<data>>:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+//---------------------------- << start remap >> -------------------------------
+ // Internal address remapping control
+ wire [<<idw_remap>>:0] remapping_dec; // Internal remap signal
+//----------------------------- << end remap >> --------------------------------
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [<<addr>>:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch output MI<<out>>
+ wire active_dec<<out>>; // active_dec signal
+ wire readyout_dec<<out>>; // HREADYOUT input
+ wire [<<resp>>:0] resp_dec<<out>>; // HRESP input
+ wire [<<data>>:0] rdata_dec<<out>>; // HRDATA input
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] ruser_dec<<out>>; // HRUSER input
+//----------------------------- << end user >> ---------------------------------
+ reg sel_dec<<out>>; // HSEL output
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [<<resp>>:0] HRESPS; // Combinatorial HRESPS signal
+//---------------------------- << start user >> --------------------------------
+ reg [<<user>>:0] HRUSERS;
+//----------------------------- << end user >> ---------------------------------
+ reg [<<data>>:0] HRDATAS; // Read data bus
+
+ reg [<<idw_mi>>:0] addr_out_port; // Address output ports
+ reg [<<idw_mi>>:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [<<resp>>:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ <<default_slave_name>> u_<<default_slave_name>> (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[<<addr>>:10], which is not a hex character boundary
+
+ always @ (
+//----------------------------- << start map >> --------------------------------
+ decode_addr_dec or data_out_port or trans_dec
+//----------------------------- << end map >> ----------------------------------
+//---------------------------- << start remap >> -------------------------------
+ decode_addr_dec or
+ remapping_dec or data_out_port or trans_dec
+//----------------------------- << end remap >> --------------------------------
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+//----------------------------- << start map >> --------------------------------
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start addr_map >> ---------------------------
+//----------------------------- << start addr_region >> ------------------------
+ // Address region <<address_map>>
+ <<mdelse>>if ((decode_addr_dec >= <<mem_lo>>) & (decode_addr_dec <= <<mem_hi>>))
+ addr_out_port = <<idw_mi_v>>'b0<<bin_out>>; // Select Output port MI<<out>>
+//------------------------------ << end addr_region >> -------------------------
+
+//----------------------------- << end addr_map >> -----------------------------
+//------------------------------ << end out >> ---------------------------------
+ else
+ addr_out_port = <<idw_mi_v>>'b<<dsid_bin>>; // Select the default slave
+//----------------------------- << end map >> ----------------------------------
+//---------------------------- << start remap >> -------------------------------
+ case (remapping_dec) // Composition: <<remapping_vector>>
+//----------------------------- << start remap_state >> ------------------------
+ <<idw_remap_v>>'b<<bin_remapstate>> : begin
+//----------------------------- << start remap_bit >> --------------------------
+//----------------------------- << start addr_remap >> -------------------------
+//----------------------------- << start remap_region >> -----------------------
+ // Remapped address region <<address_map>> due to REMAP[<<remapping_bit>>]
+ <<mdelse>>if ((decode_addr_dec >= <<mem_lo>>) & (decode_addr_dec <= <<mem_hi>>))
+ addr_out_port = <<idw_mi_v>>'b0<<bin_out>>; // Select Output port MI<<out>>
+
+//------------------------------ << end remap_region >> -------------------------
+//----------------------------- << end addr_remap >> ---------------------------
+//------------------------------ << end remap_bit >> ---------------------------
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start addr_map >> ---------------------------
+//----------------------------- << start addr_region >> ------------------------
+ // <<region_type>> address region <<address_map>>
+ <<mdelse>>if ((decode_addr_dec >= <<mem_lo>>) & (decode_addr_dec <= <<mem_hi>>))
+ addr_out_port = <<idw_mi_v>>'b0<<bin_out>>; // Select Output port MI<<out>>
+//------------------------------ << end addr_region >> -------------------------
+
+//----------------------------- << end addr_map >> -----------------------------
+//------------------------------ << end out >> ---------------------------------
+ else
+ addr_out_port = <<idw_mi_v>>'b<<dsid_bin>>; // Select the default slave
+ end
+
+//------------------------------ << end remap_state >> -------------------------
+ default : addr_out_port = {<<idw_mi_v>>{1'bx}};
+ endcase
+//----------------------------- << end remap >> --------------------------------
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ sel_dec<<out>> = 1'b0;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_mi_v>>'b0<<bin_out>> : sel_dec<<out>> = 1'b1;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ <<idw_mi_v>>'b<<dsid_bin>> : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ sel_dec<<out>> = 1'bx;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ active_dec<<out>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_mi_v>>'b0<<bin_out>> : active_dec = active_dec<<out>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ <<idw_mi_v>>'b<<dsid_bin>> : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= <<idw_mi_v>>'b<<dsid_bin>>;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= <<idw_mi_v>>'b<<dsid_bin>>;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ readyout_dec<<out>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_mi_v>>'b0<<bin_out>> : HREADYOUTS = readyout_dec<<out>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ <<idw_mi_v>>'b<<dsid_bin>> : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ resp_dec<<out>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_mi_v>>'b0<<bin_out>> : HRESPS = resp_dec<<out>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ <<idw_mi_v>>'b<<dsid_bin>> : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {<<resp_v>>{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ rdata_dec<<out>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_mi_v>>'b0<<bin_out>> : HRDATAS = rdata_dec<<out>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ <<idw_mi_v>>'b<<dsid_bin>> : HRDATAS = {<<data_v>>{1'b0}}; // Select the default slave
+ default : HRDATAS = {<<data_v>>{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+//---------------------------- << start user >> --------------------------------
+
+ // HRUSERS output decode
+ always @ (
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ ruser_dec<<out>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ data_out_port
+ )
+ begin : p_ruser_comb
+ case (data_out_port)
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_mi_v>>'b0<<bin_out>> : HRUSERS = ruser_dec<<out>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+ <<idw_mi_v>>'b<<dsid_bin>> : HRUSERS = {<<user_v>>{1'b0}}; // Select the default slave
+ default : HRUSERS = {<<user_v>>{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_ruser_comb
+//----------------------------- << end user >> ---------------------------------
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
new file mode 100755
index 0000000000000000000000000000000000000000..a965f5d89d07c7c502b41fe236737a64aa19588f
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
@@ -0,0 +1,141 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+// -----------------------------------------------------------------------------
+// Abstract : Default slave used to drive the slave response signals
+// when there are no other slaves selected.
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<default_slave_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // AHB control input signals
+ HSEL,
+ HTRANS,
+ HREADY,
+
+ // AHB control output signals
+ HREADYOUT,
+ HRESP
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // AHB control input signals
+ input HSEL; // Slave Select
+ input [1:0] HTRANS; // Transfer type
+ input HREADY; // Transfer done
+
+ // AHB control output signals
+ output HREADYOUT; // HREADY feedback
+ output [<<resp>>:0] HRESP; // Transfer response
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HRESP transfer response signal encoding
+`define RSP_OKAY <<resp_v>>'b<<bin_resp_okay>> // OKAY response
+`define RSP_ERROR <<resp_v>>'b<<bin_resp_error>> // ERROR response
+`define RSP_RETRY <<resp_v>>'b<<bin_resp_retry>> // RETRY response
+`define RSP_SPLIT <<resp_v>>'b<<bin_resp_split>> // SPLIT response
+//----------------------------- << start excl >> -------------------------------
+`define RSP_XFAIL <<resp_v>>'b<<bin_resp_xfail>>; // XFAIL response
+//------------------------------ << end excl >> --------------------------------
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // AHB control input signals
+ wire HSEL; // Slave Select
+ wire [1:0] HTRANS; // Transfer type
+ wire HREADY; // Transfer done
+
+ // AHB control output signals
+ wire HREADYOUT; // HREADY feedback
+ wire [<<resp>>:0] HRESP; // Transfer response
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ wire invalid; // Set during invalid transfer
+ wire hready_next; // Controls generation of HREADYOUT output
+ reg i_hreadyout; // HREADYOUT register
+ wire [<<resp>>:0] hresp_next; // Generated response
+ reg [<<resp>>:0] i_hresp; // HRESP register
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+ assign invalid = ( HREADY & HSEL & HTRANS[1] );
+ assign hready_next = i_hreadyout ? ~invalid : 1'b1 ;
+ assign hresp_next = invalid ? `RSP_ERROR : `RSP_OKAY;
+
+ always @(negedge HRESETn or posedge HCLK)
+ begin : p_resp_seq
+ if (~HRESETn)
+ begin
+ i_hreadyout <= 1'b1;
+ i_hresp <= `RSP_OKAY;
+ end
+ else
+ begin
+ i_hreadyout <= hready_next;
+
+ if (i_hreadyout)
+ i_hresp <= hresp_next;
+ end
+ end
+
+ // Drive outputs with internal versions
+ assign HREADYOUT = i_hreadyout;
+ assign HRESP = i_hresp;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
new file mode 100755
index 0000000000000000000000000000000000000000..b10b09001def56a643c500d0b8d309ca1507c6dd
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
@@ -0,0 +1,179 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<output_arb_name>> (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ input req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+
+ output [<<idw_si>>:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wire req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire HMASTLOCKM; // Locked transfer
+ wire [<<idw_si>>:0] addr_in_port; // Port address input
+ reg no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [<<idw_si>>:0] addr_in_port_next; // D-input of addr_in_port
+ reg [<<idw_si>>:0] iaddr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Port Selection
+//------------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme where input
+// port 0 is the highest priority, input port 1 is the second highest
+// priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ HSELM or HTRANSM or HMASTLOCKM or iaddr_in_port
+ )
+
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = iaddr_in_port;
+
+ if (HMASTLOCKM)
+ addr_in_port_next = iaddr_in_port;
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ else if ( req_port<<in>> | ( (iaddr_in_port == <<idw_si_v>>'b<<bin_in>>) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = <<idw_si_v>>'b<<bin_in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ else if (HSELM)
+ addr_in_port_next = iaddr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (~HRESETn)
+ begin
+ no_port <= 1'b1;
+ iaddr_in_port <= {<<idw_si_v>>{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ iaddr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = iaddr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
new file mode 100755
index 0000000000000000000000000000000000000000..747c17171283febb6f1e1a64bcb42cabd1ea7ea6
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
@@ -0,0 +1,544 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Input Stage is used to hold a pending transfer
+// when the required output stage is not available.
+//---------------------------- << start unalign >> -----------------------------
+// Supports ARMv6 AMBA extensions for unaligned access.
+//----------------------------- << end unalign >> ------------------------------
+//----------------------------- << start excl >> -------------------------------
+// Supports ARMv6 AMBA extensions for exclusive access.
+//------------------------------ << end excl >> --------------------------------
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<input_stage_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Input Port Address/Control Signals
+ HSELS,
+ HADDRS,
+//---------------------------- << start user >> --------------------------------
+ HAUSERS,
+//----------------------------- << end user >> ---------------------------------
+ HTRANSS,
+ HWRITES,
+ HSIZES,
+ HBURSTS,
+ HPROTS,
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGNS,
+ HBSTRBS,
+//----------------------------- << end unalign >> ------------------------------
+ HMASTERS,
+ HMASTLOCKS,
+ HREADYS,
+
+ // Internal Response
+ active_ip,
+ readyout_ip,
+ resp_ip,
+
+ // Input Port Response
+ HREADYOUTS,
+ HRESPS,
+
+ // Internal Address/Control Signals
+ sel_ip,
+ addr_ip,
+//---------------------------- << start user >> --------------------------------
+ auser_ip,
+//----------------------------- << end user >> ---------------------------------
+ trans_ip,
+ write_ip,
+ size_ip,
+ burst_ip,
+ prot_ip,
+//---------------------------- << start unalign >> -----------------------------
+ unalign_ip,
+ bstrb_ip,
+//----------------------------- << end unalign >> ------------------------------
+ master_ip,
+ mastlock_ip,
+ held_tran_ip
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+ input HSELS; // Slave Select from AHB
+ input [<<addr>>:0] HADDRS; // Address bus from AHB
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] HAUSERS; // Additional user adress bus
+//----------------------------- << end user >> ---------------------------------
+ input [1:0] HTRANSS; // Transfer type from AHB
+ input HWRITES; // Transfer direction from AHB
+ input [2:0] HSIZES; // Transfer size from AHB
+ input [2:0] HBURSTS; // Burst type from AHB
+ input [<<prot>>:0] HPROTS; // Protection control from AHB
+//---------------------------- << start unalign >> -----------------------------
+ input HUNALIGNS; // Unalign signal from AHB
+ input [<<bstrb>>:0] HBSTRBS; // Active Byte Lane strobes
+//----------------------------- << end unalign >> ------------------------------
+ input [3:0] HMASTERS; // Master number from AHB
+ input HMASTLOCKS; // Locked Sequence from AHB
+ input HREADYS; // Transfer done from AHB
+ input active_ip; // active_ip signal
+ input readyout_ip; // HREADYOUT input
+ input [<<resp>>:0] resp_ip; // HRESP input
+
+ output HREADYOUTS; // HREADY feedback to AHB
+ output [<<resp>>:0] HRESPS; // Transfer response to AHB
+ output sel_ip; // HSEL output
+ output [<<addr>>:0] addr_ip; // HADDR output
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] auser_ip; // HAUSER output
+//----------------------------- << end user >> ---------------------------------
+ output [1:0] trans_ip; // HTRANS output
+ output write_ip; // HWRITE output
+ output [2:0] size_ip; // HSIZE output
+ output [2:0] burst_ip; // HBURST output
+ output [<<prot>>:0] prot_ip; // HPROT output
+//---------------------------- << start unalign >> -----------------------------
+ output unalign_ip; // HUNALIGN output
+ output [<<bstrb>>:0] bstrb_ip; // HBSTRB output
+//----------------------------- << end unalign >> ------------------------------
+ output [3:0] master_ip; // HMASTER output
+ output mastlock_ip; // HMASTLOCK output
+ output held_tran_ip; // Holding register active flag
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle Transfer
+`define TRN_BUSY 2'b01 // Busy Transfer
+`define TRN_NONSEQ 2'b10 // Nonsequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single BURST
+`define BUR_INCR 3'b001 // Incremental BURSTS
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat incr
+`define BUR_WRAP16 3'b110 // 16-beat wrap
+`define BUR_INCR16 3'b111 // 16-beat incr
+
+// HRESP signal encoding
+`define RSP_OKAY <<resp_v>>'b<<bin_resp_okay>> // OKAY response
+`define RSP_ERROR <<resp_v>>'b<<bin_resp_error>> // ERROR response
+`define RSP_RETRY <<resp_v>>'b<<bin_resp_retry>> // RETRY response
+`define RSP_SPLIT <<resp_v>>'b<<bin_resp_split>> // SPLIT response
+//----------------------------- << start excl >> -------------------------------
+`define RSP_XFAIL <<resp_v>>'b<<bin_resp_xfail>>; // XFAIL response
+//------------------------------ << end excl >> --------------------------------
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+ wire HSELS; // Slave Select from AHB
+ wire [<<addr>>:0] HADDRS; // Address bus from AHB
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HAUSERS; // Additional user adress bus
+//----------------------------- << end user >> ---------------------------------
+ wire [1:0] HTRANSS; // Transfer type from AHB
+ wire HWRITES; // Transfer direction from AHB
+ wire [2:0] HSIZES; // Transfer size from AHB
+ wire [2:0] HBURSTS; // Burst type from AHB
+ wire [<<prot>>:0] HPROTS; // Protection control from AHB
+//---------------------------- << start unalign >> -----------------------------
+ wire HUNALIGNS; // Unalign signal from AHB
+ wire [<<bstrb>>:0] HBSTRBS; // Active Byte Lane strobes
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] HMASTERS; // Master number from AHB
+ wire HMASTLOCKS; // Locked Sequence from AHB
+ wire HREADYS; // Transfer done from AHB
+ reg HREADYOUTS; // HREADY feedback to AHB
+ reg [<<resp>>:0] HRESPS; // Transfer response to AHB
+ reg sel_ip; // HSEL output
+ reg [<<addr>>:0] addr_ip; // HADDR output
+//---------------------------- << start user >> --------------------------------
+ reg [<<user>>:0] auser_ip; // HAUSER output
+//----------------------------- << end user >> ---------------------------------
+ wire [1:0] trans_ip; // HTRANS output
+ reg write_ip; // HWRITE output
+ reg [2:0] size_ip; // HSIZE output
+ wire [2:0] burst_ip; // HBURST output
+ reg [<<prot>>:0] prot_ip; // HPROT output
+//---------------------------- << start unalign >> -----------------------------
+ wire unalign_ip; // HUNALIGN output
+ wire [<<bstrb>>:0] bstrb_ip; // HBSTRB output
+//----------------------------- << end unalign >> ------------------------------
+ reg [3:0] master_ip; // HMASTER output
+ reg mastlock_ip; // HMASTLOCK output
+ wire held_tran_ip; // Holding register active flag
+ wire active_ip; // active_ip signal
+ wire readyout_ip; // HREADYOUT input
+ wire [<<resp>>:0] resp_ip; // HRESP input
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ wire load_reg; // Holding register load flag
+ wire pend_tran; // An active transfer cannot complete
+ reg pend_tran_reg; // Registered version of pend_tran
+ wire addr_valid; // Indicates address phase of
+ // valid transfer
+ reg data_valid; // Indicates data phase of
+ // valid transfer
+ reg [1:0] reg_trans; // Registered HTRANSS
+ reg [<<addr>>:0] reg_addr; // Registered HADDRS
+//---------------------------- << start user >> --------------------------------
+ reg [<<user>>:0] reg_auser;
+//----------------------------- << end user >> ---------------------------------
+ reg reg_write; // Registered HWRITES
+ reg [2:0] reg_size; // Registered HSIZES
+ reg [2:0] reg_burst; // Registered HBURSTS
+ reg [<<prot>>:0] reg_prot; // Registered HPROTS
+//---------------------------- << start unalign >> -----------------------------
+ reg reg_unalign; // Registered HUNALIGNS
+ reg [<<bstrb>>:0] reg_bstrb; // Registered HBSTRBS
+//----------------------------- << end unalign >> ------------------------------
+ reg [3:0] reg_master; // Registerd HMASTERS
+ reg reg_mastlock; // Registered HMASTLOCKS
+ reg [1:0] transb; // HTRANS output used for burst information
+ reg [1:0] trans_int; // HTRANS output
+ reg [2:0] burst_int; // HBURST output
+ reg [3:0] offset_addr; // Address offset for boundary logic
+ reg [3:0] check_addr; // Address check for wrapped bursts
+ reg burst_override; // Registered burst_override_next
+ wire burst_override_next; // Indicates burst has been over-ridden
+ reg bound; // Registered version of bound_next
+ wire bound_next; // Indicates boundary wrapping
+ wire bound_en; // Clock-enable for bound register
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Holding Registers
+// -----------------------------------------------------------------------------
+// Each input port has a holding register associated with it and a mux to
+// select between the register and the direct input path. The control of
+// the mux is done simply by selecting the holding register when it is loaded
+// with a pending transfer, otherwise the straight through path is used.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_holding_reg_seq1
+ if (~HRESETn)
+ begin
+ reg_trans <= 2'b00;
+ reg_addr <= {<<addr_v>>{1'b0}};
+//---------------------------- << start user >> --------------------------------
+ reg_auser <= {<<user_v>>{1'b0}};
+//----------------------------- << end user >> ---------------------------------
+ reg_write <= 1'b0 ;
+ reg_size <= 3'b000;
+ reg_burst <= 3'b000;
+ reg_prot <= {<<prot_v>>{1'b0}};
+//---------------------------- << start unalign >> -----------------------------
+ reg_unalign <= 1'b0;
+ reg_bstrb <= {<<bstrb_v>>{1'b0}};
+//----------------------------- << end unalign >> ------------------------------
+ reg_master <= 4'b0000;
+ reg_mastlock <= 1'b0 ;
+ end
+ else
+ if (load_reg)
+ begin
+ reg_trans <= HTRANSS;
+ reg_addr <= HADDRS;
+//---------------------------- << start user >> --------------------------------
+ reg_auser <= HAUSERS;
+//----------------------------- << end user >> ---------------------------------
+ reg_write <= HWRITES;
+ reg_size <= HSIZES;
+ reg_burst <= HBURSTS;
+ reg_prot <= HPROTS;
+//---------------------------- << start unalign >> -----------------------------
+ reg_unalign <= HUNALIGNS;
+ reg_bstrb <= HBSTRBS;
+//----------------------------- << end unalign >> ------------------------------
+ reg_master <= HMASTERS;
+ reg_mastlock <= HMASTLOCKS;
+ end
+ end
+
+ // addr_valid indicates the address phase of an active (non-BUSY/IDLE)
+ // transfer to this slave port
+ assign addr_valid = ( HSELS & HTRANSS[1] );
+
+ // The holding register is loaded whenever there is a transfer on the input
+ // port which is validated by active HREADYS
+ assign load_reg = ( addr_valid & HREADYS );
+
+ // data_valid register
+ // addr_valid indicates the data phase of an active (non-BUSY/IDLE)
+ // transfer to this slave port. A valid response (HREADY, HRESP) must be
+ // generated
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_valid
+ if (~HRESETn)
+ data_valid <= 1'b0;
+ else
+ if (HREADYS)
+ data_valid <= addr_valid;
+ end
+
+// -----------------------------------------------------------------------------
+// Generate HeldTran
+// -----------------------------------------------------------------------------
+// The HeldTran signal is used to indicate when there is an active transfer
+// being presented to the output stage, either passing straight through or from
+// the holding register.
+
+ // pend_tran indicates that an active transfer presented to this
+ // slave cannot complete immediately. It is always set after the
+ // load_reg signal has been active. When set, it is cleared when the
+ // transfer is being driven onto the selected slave (as indicated by
+ // active_ip being high) and HREADY from the selected slave is high.
+ assign pend_tran = (load_reg & (~active_ip)) ? 1'b1 :
+ (active_ip & readyout_ip) ? 1'b0 : pend_tran_reg;
+
+ // pend_tran_reg indicates that an active transfer was accepted by the input
+ // stage,but not by the output stage, and so the holding registers should be
+ // used
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_pend_tran_reg
+ if (~HRESETn)
+ pend_tran_reg <= 1'b0;
+ else
+ pend_tran_reg <= pend_tran;
+ end
+
+ // held_tran_ip indicates an active transfer, and is held whilst that transfer is
+ // in the holding registers. It passes to the output stage where it acts as
+ // a request line to the arbitration scheme
+ assign held_tran_ip = (load_reg | pend_tran_reg);
+
+ // The output from this stage is selected from the holding register when
+ // there is a held transfer. Otherwise the direct path is used.
+
+ always @ ( pend_tran_reg or HSELS or HTRANSS or HADDRS or HWRITES or
+ HSIZES or HBURSTS or HPROTS or HMASTERS or HMASTLOCKS or
+//---------------------------- << start user >> --------------------------------
+ HAUSERS or reg_auser or
+//----------------------------- << end user >> ---------------------------------
+ reg_addr or reg_write or reg_size or reg_burst or reg_prot or
+ reg_master or reg_mastlock
+ )
+ begin : p_mux_comb
+ if (~pend_tran_reg)
+ begin
+ sel_ip = HSELS;
+ trans_int = HTRANSS;
+ addr_ip = HADDRS;
+//---------------------------- << start user >> --------------------------------
+ auser_ip = HAUSERS;
+//----------------------------- << end user >> ---------------------------------
+ write_ip = HWRITES;
+ size_ip = HSIZES;
+ burst_int = HBURSTS;
+ prot_ip = HPROTS;
+ master_ip = HMASTERS;
+ mastlock_ip = HMASTLOCKS;
+ end
+ else
+ begin
+ sel_ip = 1'b1;
+ trans_int = `TRN_NONSEQ;
+ addr_ip = reg_addr;
+//---------------------------- << start user >> --------------------------------
+ auser_ip = reg_auser;
+//----------------------------- << end user >> ---------------------------------
+ write_ip = reg_write;
+ size_ip = reg_size;
+ burst_int = reg_burst;
+ prot_ip = reg_prot;
+ master_ip = reg_master;
+ mastlock_ip = reg_mastlock;
+ end
+ end
+
+ // The transb output is used to select the correct Burst value when completing
+ // an interrupted defined-lenght burst.
+
+ always @ (pend_tran_reg or HTRANSS or reg_trans)
+ begin : p_transb_comb
+ if (~pend_tran_reg)
+ transb = HTRANSS;
+ else
+ transb = reg_trans;
+ end // block: p_transb_comb
+
+//---------------------------- << start unalign >> -----------------------------
+ assign unalign_ip = (pend_tran_reg) ? reg_unalign : HUNALIGNS ;
+ assign bstrb_ip = (pend_tran_reg) ? reg_bstrb : HBSTRBS ;
+//----------------------------- << end unalign >> ------------------------------
+
+ // Convert SEQ->NONSEQ and BUSY->IDLE when an address boundary is crossed
+ // whilst the burst type is being over-ridden, i.e. when completing an
+ // interrupted wrapping burst.
+ assign trans_ip = (burst_override & bound) ? {trans_int[1], 1'b0}
+ : trans_int;
+
+ assign burst_ip = (burst_override & (transb != `TRN_NONSEQ)) ? `BUR_INCR
+ : burst_int;
+
+// -----------------------------------------------------------------------------
+// HREADYOUT Generation
+// -----------------------------------------------------------------------------
+// There are three possible sources for the HREADYOUT signal.
+// - It is driven LOW when there is a held transfer.
+// - It is driven HIGH when not Selected or for Idle/Busy transfers.
+// - At all other times it is driven from the appropriate shared
+// slave.
+
+ always @ (data_valid or pend_tran_reg or readyout_ip or resp_ip)
+ begin : p_ready_comb
+ if (~data_valid)
+ begin
+ HREADYOUTS = 1'b1;
+ HRESPS = `RSP_OKAY;
+ end
+ else if (pend_tran_reg)
+ begin
+ HREADYOUTS = 1'b0;
+ HRESPS = `RSP_OKAY;
+ end
+ else
+ begin
+ HREADYOUTS = readyout_ip;
+ HRESPS = resp_ip;
+ end
+ end // block: p_ready_comb
+
+// -----------------------------------------------------------------------------
+// Early Burst Termination
+// -----------------------------------------------------------------------------
+// There are times when the output stage will switch to another input port
+// without allowing the current burst to complete. In these cases the HTRANS
+// and HBURST signals need to be overriden to ensure that the transfers
+// reaching the output port meet the AHB specification.
+
+ assign burst_override_next = ( (HTRANSS == `TRN_NONSEQ) |
+ (HTRANSS == `TRN_IDLE) ) ? 1'b0
+ : ( (HTRANSS ==`TRN_SEQ) &
+ load_reg &
+ (~active_ip) ) ? 1'b1
+ : burst_override;
+
+ // burst_override register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_overrideseq
+ if (~HRESETn)
+ burst_override <= 1'b0;
+ else
+ if (HREADYS)
+ burst_override <= burst_override_next;
+ end // block: p_burst_overrideseq
+
+// -----------------------------------------------------------------------------
+// Boundary Checking Logic
+// -----------------------------------------------------------------------------
+ // offset_addr
+ always @ (HADDRS or HSIZES)
+ begin : p_offset_addr_comb
+ case (HSIZES)
+ 3'b000 : offset_addr = HADDRS[3:0];
+ 3'b001 : offset_addr = HADDRS[4:1];
+ 3'b010 : offset_addr = HADDRS[5:2];
+ 3'b011 : offset_addr = HADDRS[6:3];
+
+ 3'b100, 3'b101, 3'b110, 3'b111 :
+ offset_addr = HADDRS[3:0]; // Sizes >= 128-bits are not supported
+
+ default : offset_addr = 4'bxxxx;
+ endcase
+ end
+
+ // check_addr
+ always @ (offset_addr or HBURSTS)
+ begin : p_check_addr_comb
+ case (HBURSTS)
+ `BUR_WRAP4 : begin
+ check_addr[1:0] = offset_addr[1:0];
+ check_addr[3:2] = 2'b11;
+ end
+
+ `BUR_WRAP8 : begin
+ check_addr[2:0] = offset_addr[2:0];
+ check_addr[3] = 1'b1;
+ end
+
+ `BUR_WRAP16 :
+ check_addr[3:0] = offset_addr[3:0];
+
+ `BUR_SINGLE, `BUR_INCR, `BUR_INCR4, `BUR_INCR8, `BUR_INCR16 :
+ check_addr[3:0] = 4'b0000;
+
+ default : check_addr[3:0] = 4'bxxxx;
+ endcase
+ end
+
+ assign bound_next = ( check_addr == 4'b1111 );
+
+ assign bound_en = ( HTRANSS[1] & HREADYS );
+
+ // bound register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_bound_seq
+ if (~HRESETn)
+ bound <= 1'b0;
+ else
+ if (bound_en)
+ bound <= bound_next;
+ end
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
new file mode 100755
index 0000000000000000000000000000000000000000..27920fe250ee30b45338affe370c9ca312ab3047
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
@@ -0,0 +1,538 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity,
+// and has a <<arbiter_type>> arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<output_stage_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Port <<in>> Signals
+ sel_op<<in>>,
+ addr_op<<in>>,
+//---------------------------- << start user >> --------------------------------
+ auser_op<<in>>,
+//----------------------------- << end user >> ---------------------------------
+ trans_op<<in>>,
+ write_op<<in>>,
+ size_op<<in>>,
+ burst_op<<in>>,
+ prot_op<<in>>,
+//---------------------------- << start unalign >> -----------------------------
+ unalign_op<<in>>,
+ bstrb_op<<in>>,
+//----------------------------- << end unalign >> ------------------------------
+ master_op<<in>>,
+ mastlock_op<<in>>,
+ wdata_op<<in>>,
+//---------------------------- << start user >> --------------------------------
+ wuser_op<<in>>,
+//----------------------------- << end user >> ---------------------------------
+ held_tran_op<<in>>,
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ // Slave read data and response
+ HREADYOUTM,
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ active_op<<in>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+//---------------------------- << start user >> --------------------------------
+ HAUSERM,
+//----------------------------- << end user >> ---------------------------------
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGNM,
+ HBSTRBM,
+//----------------------------- << end unalign >> ------------------------------
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+//---------------------------- << start user >> --------------------------------
+ HWUSERM,
+//----------------------------- << end user >> ---------------------------------
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch input <<in>>
+ input sel_op<<in>>; // Port <<in>> HSEL signal
+ input [<<addr>>:0] addr_op<<in>>; // Port <<in>> HADDR signal
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] auser_op<<in>>; // Port <<in>> HAUSER signal
+//----------------------------- << end user >> ---------------------------------
+ input [1:0] trans_op<<in>>; // Port <<in>> HTRANS signal
+ input write_op<<in>>; // Port <<in>> HWRITE signal
+ input [2:0] size_op<<in>>; // Port <<in>> HSIZE signal
+ input [2:0] burst_op<<in>>; // Port <<in>> HBURST signal
+ input [<<prot>>:0] prot_op<<in>>; // Port <<in>> HPROT signal
+//---------------------------- << start unalign >> -----------------------------
+ input unalign_op<<in>>; // Port <<in>> HUNALIGN signal
+ input [<<bstrb>>:0] bstrb_op<<in>>; // Port <<in>> HBSTRB signal
+//----------------------------- << end unalign >> ------------------------------
+ input [3:0] master_op<<in>>; // Port <<in>> HMASTER signal
+ input mastlock_op<<in>>; // Port <<in>> HMASTLOCK signal
+ input [<<data>>:0] wdata_op<<in>>; // Port <<in>> HWDATA signal
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] wuser_op<<in>>; // Port <<in>> HWUSER signal
+//----------------------------- << end user >> ---------------------------------
+ input held_tran_op<<in>>; // Port <<in>> HeldTran signal
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ input HREADYOUTM; // HREADY feedback
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ output active_op<<in>>; // Port <<in>> Active signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [<<addr>>:0] HADDRM; // Address
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HAUSERM; // User Address bus
+//----------------------------- << end user >> ---------------------------------
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [<<prot>>:0] HPROTM; // Protection control
+//---------------------------- << start unalign >> -----------------------------
+ output HUNALIGNM; // Unaligned transfer
+ output [<<bstrb>>:0] HBSTRBM; // Byte Lane strobe signal
+//----------------------------- << end unalign >> ------------------------------
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HWUSERM; // User data bus
+//----------------------------- << end user >> ---------------------------------
+ output [<<data>>:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch input <<in>>
+ wire sel_op<<in>>; // Port <<in>> HSEL signal
+ wire [<<addr>>:0] addr_op<<in>>; // Port <<in>> HADDR signal
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] auser_op<<in>>; // Port <<in>> HAUSER signal
+//----------------------------- << end user >> ---------------------------------
+ wire [1:0] trans_op<<in>>; // Port <<in>> HTRANS signal
+ wire write_op<<in>>; // Port <<in>> HWRITE signal
+ wire [2:0] size_op<<in>>; // Port <<in>> HSIZE signal
+ wire [2:0] burst_op<<in>>; // Port <<in>> HBURST signal
+ wire [<<prot>>:0] prot_op<<in>>; // Port <<in>> HPROT signal
+//---------------------------- << start unalign >> -----------------------------
+ wire unalign_op<<in>>; // Port <<in>> HUNALIGN signal
+ wire [<<bstrb>>:0] bstrb_op<<in>>; // Port <<in>> HBSTRB signal
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] master_op<<in>>; // Port <<in>> HMASTER signal
+ wire mastlock_op<<in>>; // Port <<in>> HMASTLOCK signal
+ wire [<<data>>:0] wdata_op<<in>>; // Port <<in>> HWDATA signal
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] wuser_op<<in>>; // Port <<in>> HWUSER signal
+//----------------------------- << end user >> ---------------------------------
+ wire held_tran_op<<in>>; // Port <<in>> HeldTran signal
+ reg active_op<<in>>; // Port <<in>> Active signal
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [<<addr>>:0] HADDRM; // Address
+//---------------------------- << start user >> --------------------------------
+ reg [<<user>>:0] HAUSERM; // User Address bus
+//----------------------------- << end user >> ---------------------------------
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [<<prot>>:0] HPROTM; // Protection control
+//---------------------------- << start unalign >> -----------------------------
+ reg HUNALIGNM; // Unaligned transfer
+ reg [<<bstrb>>:0] HBSTRBM; // Byte Lane strobe signal
+//----------------------------- << end unalign >> ------------------------------
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+//---------------------------- << start user >> --------------------------------
+ reg [<<user>>:0] HWUSERM; // User data bus
+//----------------------------- << end user >> ---------------------------------
+ reg [<<data>>:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wire req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ wire [<<idw_si>>:0] addr_in_port; // Address input port
+ reg [<<idw_si>>:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign req_port<<in>> = held_tran_op<<in>> & sel_op<<in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Arbiter instance for resolving requests to this output stage
+ <<output_arb_name>> u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ .req_port<<in>> (req_port<<in>>),
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ active_op<<in>> = 1'b0;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_si_v>>'b<<bin_in>> : active_op<<in>> = 1'b1;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ default : begin
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ active_op<<in>> = 1'bx;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ sel_op<<in>> or addr_op<<in>> or trans_op<<in>> or write_op<<in>> or
+ size_op<<in>> or burst_op<<in>> or prot_op<<in>> or
+//---------------------------- << start unalign >> -----------------------------
+ unalign_op<<in>> or bstrb_op<<in>> or
+//----------------------------- << end unalign >> ------------------------------
+//---------------------------- << start user >> --------------------------------
+ auser_op<<in>> or
+//----------------------------- << end user >> ---------------------------------
+ master_op<<in>> or mastlock_op<<in>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {<<addr_v>>{1'b0}};
+//---------------------------- << start user >> --------------------------------
+ HAUSERM = {<<user_v>>{1'b0}};
+//----------------------------- << end user >> ---------------------------------
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {<<prot_v>>{1'b0}};
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGNM = 1'b0;
+ HBSTRBM = {<<bstrb_v>>{1'b0}};
+//----------------------------- << end unalign >> ------------------------------
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch input <<in>>
+ <<idw_si_v>>'b<<bin_in>> :
+ begin
+ i_hselm = sel_op<<in>>;
+ HADDRM = addr_op<<in>>;
+//---------------------------- << start user >> --------------------------------
+ HAUSERM = auser_op<<in>>;
+//----------------------------- << end user >> ---------------------------------
+ i_htransm = trans_op<<in>>;
+ HWRITEM = write_op<<in>>;
+ HSIZEM = size_op<<in>>;
+ i_hburstm = burst_op<<in>>;
+ HPROTM = prot_op<<in>>;
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGNM = unalign_op<<in>>;
+ HBSTRBM = bstrb_op<<in>>;
+//----------------------------- << end unalign >> ------------------------------
+ HMASTERM = master_op<<in>>;
+ i_hmastlockm= mastlock_op<<in>>;
+ end // case: 4'b<<bin_in>>
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {<<addr_v>>{1'bx}};
+//---------------------------- << start user >> --------------------------------
+ HAUSERM = {<<user_v>>{1'bx}};
+//----------------------------- << end user >> ---------------------------------
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {<<prot_v>>{1'bx}};
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGNM = 1'bx;
+ HBSTRBM = {<<bstrb_v>>{1'bx}};
+//----------------------------- << end unalign >> ------------------------------
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+//------------------------------ << start rrin >> ------------------------------
+//------------------------------ << end rrin >> ------------------------------ used to get a valid port number for the reset of data_port
+ data_in_port <= <<idw_si_v>>'b<<bin_rrin>>;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wdata_op<<in>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {<<data_v>>{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_si_v>>'b<<bin_in>> : HWDATAM = wdata_op<<in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ default : HWDATAM = {<<data_v>>{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+//---------------------------- << start user >> --------------------------------
+ // HWUSERM output decode
+ always @ (
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wuser_op<<in>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ data_in_port or wdata_phase
+ )
+ begin : p_wuser_mux
+ // Default value
+ HWUSERM = {<<user_v>>{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<idw_si_v>>'b<<bin_in>> : HWUSERM = wuser_op<<in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ default : HWUSERM = {<<user_v>>{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_wuser_mux
+//----------------------------- << end user >> ---------------------------------
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
new file mode 100755
index 0000000000000000000000000000000000000000..5108798c5acf8aa82a2fb16f9c85105a98d654f4
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
@@ -0,0 +1,375 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<output_arb_name>> (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ input req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [<<idw_si>>:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wire req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [<<idw_si>>:0] addr_in_port; // Address input port
+ wire no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [<<idw_si>>:0] next_addr_in_port; // D-input of addr_in_port
+ reg next_no_port; // D-input of no_port
+ reg [<<idw_si>>:0] i_addr_in_port; // Internal version of addr_in_port
+ reg i_no_port; // Internal version of no_port
+
+ // Burst counter logic
+ reg [3:0] next_burst_remain; // D-input of reg_burst_remain
+ reg [3:0] reg_burst_remain; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // INCR burst logic
+ reg [1:0] reg_early_term_count; // Counts number of INCR bursts terminated
+ // earlier than 4-beats or early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_remain indicates the number of transfers remaining in the
+// current fixed length burst after the current transfer.
+// reg_burst_hold is set when transfers remain in a burst and causes the arbitration
+// to be held in the current cycle
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_remain or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_remain_comb
+ // Force the Burst logic to reset if this port is de-selected. This would
+ // otherwise cause problems in several situations, e.g.:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (~HSELM)
+ begin
+ next_burst_remain = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_remain = 4'd15;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_remain = 4'd7;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_remain = 4'd3;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_INCR : begin
+ next_burst_remain = 4'd3;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR
+
+ `BUR_SINGLE : begin
+ next_burst_remain = 4'd0;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_remain = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_remain = 4'd0;
+ end
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ if (reg_burst_remain == 4'd1) // this was last one remaining
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_remain = 4'd0;
+ end
+ else
+ begin
+ next_burst_hold = reg_burst_hold;
+ if (reg_burst_remain != 4'd0)
+ next_burst_remain = reg_burst_remain - 4'b1;
+ else
+ next_burst_remain = 4'd0;
+ end
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_remain = reg_burst_remain;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_remain = 4'd0;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_remain = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_remain_comb
+
+
+ // reg_early_term_count counts the number of bursts which have terminated
+ // earlier than the defined arbitration point: this is primarily
+ // intended to detect back-to-back INCR bursts which are less than 4
+ // beats long or early terminated bursts by another interconnect.
+ // If such bursts are not counted then theoretically a
+ // sequence of e.g. 3-beat INCR bursts from a master would lock the
+ // arbitration scheme indefinitely.
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (~HRESETn)
+ begin
+ reg_burst_remain <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_remain <= next_burst_remain;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a round-robin scheme.
+// For example if port 1 is currently in use then the arbiter will first check
+// if port 2 requires access, then it checks port 3, then port 4 etc. When
+// port 2 is currently in use it will check port 3 first then port 4 and
+// all remaining ports, before finally checking port 1.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>> or
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ HMASTLOCKM or next_burst_hold or HSELM or i_no_port or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for next_no_port and next_addr_in_port
+ next_no_port = 1'b0;
+ next_addr_in_port = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ next_addr_in_port = i_addr_in_port;
+ else if (i_no_port)
+ begin
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ <<rrelse>>if (req_port<<in>>)
+ next_addr_in_port = <<idw_si_v>>'b<<bin_in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end in >> ----------------------------------
+ else
+ next_no_port = 1'b1;
+ end
+ else
+ case (i_addr_in_port)
+//------------------------------ << start rrin >> ------------------------------
+ <<idw_si_v>>'b<<bin_rrin>> : begin
+//------------------------------ << start rridx >> -----------------------------
+ <<rrelse>>if (req_port<<rridx>>)
+ next_addr_in_port = <<idw_si_v>>'b<<bin_rridx>>;
+//------------------------------ << end rridx >> -------------------------------
+ else if (HSELM)
+ next_addr_in_port = <<idw_si_v>>'b<<bin_rrin>>;
+ else
+ next_no_port = 1'b1;
+ end
+
+//------------------------------ << end rrin >> --------------------------------
+ default : begin
+ next_addr_in_port = {<<idw_si_v>>{1'bx}};
+ next_no_port = 1'bx;
+ end
+ endcase
+ end
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (~HRESETn)
+ begin
+ i_no_port <= 1'b1;
+ i_addr_in_port <= {<<idw_si_v>>{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ i_no_port <= next_no_port;
+ i_addr_in_port <= next_addr_in_port;
+ end
+ end
+
+ // Drive outputs with internal versions
+ assign addr_in_port = i_addr_in_port;
+ assign no_port = i_no_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
new file mode 100755
index 0000000000000000000000000000000000000000..5719c83b1b2d6ee47cdf1202f1ed421e291327be
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
@@ -0,0 +1,160 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is normally used to determine
+// which of the input stages will be given access to
+// the shared slave. However, for this output port, only
+// one sparse connection is declared and arbitration
+// is simplified to a 'grant when requested' function.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity and the
+// <<arbiter_type>> arbiter scheme has been overridden for this
+// instance only.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<output_arb_name>> (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ req_port<<in>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ input req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+
+ output [<<idw_si>>:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wire req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire HMASTLOCKM; // Locked transfer
+ wire [<<idw_si>>:0] addr_in_port; // Port address input
+ reg no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire [<<idw_si>>:0] addr_in_port_next; // D-input of addr_in_port
+ reg [<<idw_si>>:0] iaddr_in_port; // Internal version of addr_in_port
+ wire no_port_next; // D-input of no_port
+ wire request; // Slave port request
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Port Selection
+//------------------------------------------------------------------------------
+// The single output 'arbitration' function looks at the request to use the
+// output port and grants it appropriately. The input port will remain granted
+// if it is performing IDLE transfers to the selected slave. If this is not
+// the case then the no_port signal will be asserted which indicates that the
+// input port should be deselected.
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign request = req_port<<in>> | ( (iaddr_in_port == <<idw_si_v>>'b<<bin_in>>) & HSELM &
+ (HTRANSM != 2'b00) );
+
+ assign no_port_next = ! ( HMASTLOCKM | request | HSELM );
+ assign addr_in_port_next = ( request & !HMASTLOCKM ) ? <<idw_si_v>>'b<<bin_in>> : iaddr_in_port;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (~HRESETn)
+ begin
+ no_port <= 1'b1;
+ iaddr_in_port <= {<<idw_si_v>>{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ iaddr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = iaddr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
new file mode 100755
index 0000000000000000000000000000000000000000..3aa50647215e1d766c1d17d970fbfd02a5ffd17e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
@@ -0,0 +1,416 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output. However, for this
+// output port, only one sparse connection is declared
+// and muxing is simplified.
+//
+// Notes : The bus matrix has <<connectivity>> connectivity and the
+// standard output stage has been overridden for this
+// instance only.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<output_stage_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Port <<in>> Signals
+ sel_op<<in>>,
+ addr_op<<in>>,
+//---------------------------- << start user >> --------------------------------
+ auser_op<<in>>,
+//----------------------------- << end user >> ---------------------------------
+ trans_op<<in>>,
+ write_op<<in>>,
+ size_op<<in>>,
+ burst_op<<in>>,
+ prot_op<<in>>,
+//---------------------------- << start unalign >> -----------------------------
+ unalign_op<<in>>,
+ bstrb_op<<in>>,
+//----------------------------- << end unalign >> ------------------------------
+ master_op<<in>>,
+ mastlock_op<<in>>,
+ wdata_op<<in>>,
+//---------------------------- << start user >> --------------------------------
+ wuser_op<<in>>,
+//----------------------------- << end user >> ---------------------------------
+ held_tran_op<<in>>,
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ // Slave read data and response
+ HREADYOUTM,
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ active_op<<in>>,
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Slave addr_opess/Control Signals
+ HSELM,
+ HADDRM,
+//---------------------------- << start user >> --------------------------------
+ HAUSERM,
+//----------------------------- << end user >> ---------------------------------
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGNM,
+ HBSTRBM,
+//----------------------------- << end unalign >> ------------------------------
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+//---------------------------- << start user >> --------------------------------
+ HWUSERM,
+//----------------------------- << end user >> ---------------------------------
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch input <<in>>
+ input sel_op<<in>>; // Port <<in>> HSEL signal
+ input [<<addr>>:0] addr_op<<in>>; // Port <<in>> HADDR signal
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] auser_op<<in>>; // Port <<in>> HAUSER signal
+//----------------------------- << end user >> ---------------------------------
+ input [1:0] trans_op<<in>>; // Port <<in>> HTRANS signal
+ input write_op<<in>>; // Port <<in>> HWRITE signal
+ input [2:0] size_op<<in>>; // Port <<in>> HSIZE signal
+ input [2:0] burst_op<<in>>; // Port <<in>> HBURST signal
+ input [<<prot>>:0] prot_op<<in>>; // Port <<in>> HPROT signal
+//---------------------------- << start unalign >> -----------------------------
+ input unalign_op<<in>>; // Port <<in>> HUNALIGN signal
+ input [<<bstrb>>:0] bstrb_op<<in>>; // Port <<in>> HBSTRB signal
+//----------------------------- << end unalign >> ------------------------------
+ input [3:0] master_op<<in>>; // Port <<in>> HMASTER signal
+ input mastlock_op<<in>>; // Port <<in>> HMASTLOCK signal
+ input [<<data>>:0] wdata_op<<in>>; // Port <<in>> HWDATA signal
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] wuser_op<<in>>; // Port <<in>> HWUSER signal
+//----------------------------- << end user >> ---------------------------------
+ input held_tran_op<<in>>; // Port <<in>> held_tran_op signal
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ input HREADYOUTM; // HREADY feedback
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ output active_op<<in>>; // Port <<in>> active_op signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Slave addr_opess/Control Signals
+ output HSELM; // Slave select line
+ output [<<addr>>:0] HADDRM; // addr_opess
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HAUSERM; // User addr_opess bus
+//----------------------------- << end user >> ---------------------------------
+ output [1:0] HTRANSM; // trans_opfer type
+ output HWRITEM; // trans_opfer direction
+ output [2:0] HSIZEM; // trans_opfer size
+ output [2:0] HBURSTM; // burst_op type
+ output [<<prot>>:0] HPROTM; // prot_opection control
+//---------------------------- << start unalign >> -----------------------------
+ output HUNALIGNM; // unalign_oped transfer
+ output [<<bstrb>>:0] HBSTRBM; // Byte Lane strobe signal
+//----------------------------- << end unalign >> ------------------------------
+ output [3:0] HMASTERM; // master_op ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // trans_opfer done
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HWUSERM; // User data bus
+//----------------------------- << end user >> ---------------------------------
+ output [<<data>>:0] HWDATAM; // write_op data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch input <<in>>
+ wire sel_op<<in>>; // Port <<in>> HSEL signal
+ wire [<<addr>>:0] addr_op<<in>>; // Port <<in>> HADDR signal
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] auser_op<<in>>; // Port <<in>> HAUSER signal
+//----------------------------- << end user >> ---------------------------------
+ wire [1:0] trans_op<<in>>; // Port <<in>> HTRANS signal
+ wire write_op<<in>>; // Port <<in>> HWRITE signal
+ wire [2:0] size_op<<in>>; // Port <<in>> HSIZE signal
+ wire [2:0] burst_op<<in>>; // Port <<in>> HBURST signal
+ wire [<<prot>>:0] prot_op<<in>>; // Port <<in>> HPROT signal
+//---------------------------- << start unalign >> -----------------------------
+ wire unalign_op<<in>>; // Port <<in>> HUNALIGN signal
+ wire [<<bstrb>>:0] bstrb_op<<in>>; // Port <<in>> HBSTRB signal
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] master_op<<in>>; // Port <<in>> HMASTER signal
+ wire mastlock_op<<in>>; // Port <<in>> HMASTLOCK signal
+ wire [<<data>>:0] wdata_op<<in>>; // Port <<in>> HWDATA signal
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] wuser_op<<in>>; // Port <<in>> HWUSER signal
+//----------------------------- << end user >> ---------------------------------
+ wire held_tran_op<<in>>; // Port <<in>> held_tran_op signal
+ wire active_op<<in>>; // Port <<in>> active_op signal
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+ // Slave addr_opess/Control Signals
+ wire HSELM; // Slave select line
+ wire [<<addr>>:0] HADDRM; // addr_opess
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HAUSERM; // User addr_opess bus
+//----------------------------- << end user >> ---------------------------------
+ wire [1:0] HTRANSM; // trans_opfer type
+ wire HWRITEM; // trans_opfer direction
+ wire [2:0] HSIZEM; // trans_opfer size
+ wire [2:0] HBURSTM; // burst_op type
+ wire [<<prot>>:0] HPROTM; // prot_opection control
+//---------------------------- << start unalign >> -----------------------------
+ wire HUNALIGNM; // unalign_oped transfer
+ wire [<<bstrb>>:0] HBSTRBM; // Byte Lane strobe signal
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] HMASTERM; // master_op ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // trans_opfer done
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HWUSERM; // User data bus
+//----------------------------- << end user >> ---------------------------------
+ wire [<<data>>:0] HWDATAM; // write_op data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ wire req_port<<in>>; // Port <<in>> request signal
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ wire [<<idw_si>>:0] addr_in_port; // addr_opess input port
+ reg [<<idw_si>>:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ wire i_hselm; // Internal HSELM
+ wire [1:0] i_htransm; // Internal HTRANSM
+ wire [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ wire i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port sel_opection
+// -----------------------------------------------------------------------------
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign req_port<<in>> = held_tran_op<<in>> & sel_op<<in>>;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // Dummy arbiter instance for granting requests to this output stage
+ <<output_arb_name>> u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ .req_port<<in>> (req_port<<in>>),
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // active_op signal combinatorial decode
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign active_op<<in>> = (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // addr_opess/control output decode
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign i_hselm = (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & sel_op<<in>> & !no_port;
+ assign HADDRM = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? addr_op<<in>> : {<<addr_v>>{1'b0}};
+//---------------------------- << start user >> --------------------------------
+ assign HAUSERM = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? auser_op<<in>> : {<<user_v>>{1'b0}};
+//----------------------------- << end user >> ---------------------------------
+ assign i_htransm = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? trans_op<<in>> : 2'b00;
+ assign HWRITEM = (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & write_op<<in>> & !no_port;
+ assign HSIZEM = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? size_op<<in>> : 3'b000;
+ assign i_hburstm = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? burst_op<<in>> : 3'b000;
+ assign HPROTM = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? prot_op<<in>> : {<<prot_v>>{1'b0}};
+//---------------------------- << start unalign >> -----------------------------
+ assign HUNALIGNM = (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & unalign_op<<in>> & !no_port;
+ assign HBSTRBM = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? bstrb_op<<in>> : {<<bstrb_v>>{1'b0}};
+//----------------------------- << end unalign >> ------------------------------
+ assign HMASTERM = ( (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & !no_port ) ? master_op<<in>> : 4'b0000;
+ assign i_hmastlockm = (addr_in_port == <<idw_si_v>>'b<<bin_in>>) & mastlock_op<<in>> & !no_port;
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (!HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (!HRESETn)
+ data_in_port <= {<<idw_si_v>>{1'b0}};
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign HWDATAM = wdata_phase ? wdata_op<<in>> : {<<data_v>>{1'b0}};
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+
+//---------------------------- << start user >> --------------------------------
+ // HWUSERM output decode
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ assign HWUSERM = wdata_phase ? wuser_op<<in>> : {<<user_v>>{1'b0}};
+//------------------------------ << end connection >> --------------------------
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << end user >> ---------------------------------
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (!HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
new file mode 100755
index 0000000000000000000000000000000000000000..669eb9a018632b442bb22f67b9d4367d20419708
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
@@ -0,0 +1,526 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : BusMatrix is the top-level which connects together
+// the required Input Stages, MatrixDecodes, Output
+// Stages and Output Arbitration blocks.
+//
+// Supports the following configured options:
+//
+// - Architecture type '<<architecture_type>>',
+// - <<total_si>> slave ports (connecting to masters),
+// - <<total_mi>> master ports (connecting to slaves),
+// - Routing address width of <<addr_v>> bits,
+// - Routing data width of <<data_v>> bits,
+//----------------------------- << start user >> -------------------------------
+// - xUSER signal width of <<user_v>> bits,
+//------------------------------ << end user >> --------------------------------
+//---------------------------- << start unalign >> -----------------------------
+// - ARMv6 AMBA extensions for unaligned access,
+//----------------------------- << end unalign >> ------------------------------
+//----------------------------- << start excl >> -------------------------------
+// - ARMv6 AMBA extensions for exclusive access,
+//------------------------------ << end excl >> --------------------------------
+// - Arbiter type '<<arbiter_type>>',
+// - Connectivity mapping:
+// <<mappings>>,
+// - Connectivity type '<<connectivity>>'.
+//
+//------------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<bus_matrix_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // System address remapping control
+ REMAP,
+
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (inputs from master <<in>>)
+ HSEL<<si_name>>,
+ HADDR<<si_name>>,
+ HTRANS<<si_name>>,
+ HWRITE<<si_name>>,
+ HSIZE<<si_name>>,
+ HBURST<<si_name>>,
+ HPROT<<si_name>>,
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGN<<si_name>>,
+ HBSTRB<<si_name>>,
+//----------------------------- << end unalign >> ------------------------------
+ HMASTER<<si_name>>,
+ HWDATA<<si_name>>,
+ HMASTLOCK<<si_name>>,
+ HREADY<<si_name>>,
+//---------------------------- << start user >> --------------------------------
+ HAUSER<<si_name>>,
+ HWUSER<<si_name>>,
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (inputs from slave <<out>>)
+ HRDATA<<mi_name>>,
+ HREADYOUT<<mi_name>>,
+ HRESP<<mi_name>>,
+//---------------------------- << start user >> ------------------------------
+ HRUSER<<mi_name>>,
+//----------------------------- << end user >> -------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ SCANENABLE, // Scan Test Mode Enable
+ SCANINHCLK, // Scan Chain Input
+
+
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (outputs to slave <<out>>)
+ HSEL<<mi_name>>,
+ HADDR<<mi_name>>,
+ HTRANS<<mi_name>>,
+ HWRITE<<mi_name>>,
+ HSIZE<<mi_name>>,
+ HBURST<<mi_name>>,
+ HPROT<<mi_name>>,
+//---------------------------- << start unalign >> -----------------------------
+ HUNALIGN<<mi_name>>,
+ HBSTRB<<mi_name>>,
+//----------------------------- << end unalign >> ------------------------------
+ HMASTER<<mi_name>>,
+ HWDATA<<mi_name>>,
+ HMASTLOCK<<mi_name>>,
+ HREADYMUX<<mi_name>>,
+//---------------------------- << start user >> --------------------------------
+ HAUSER<<mi_name>>,
+ HWUSER<<mi_name>>,
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (outputs to master <<in>>)
+ HRDATA<<si_name>>,
+ HREADYOUT<<si_name>>,
+ HRESP<<si_name>>,
+//---------------------------- << start user >> ------------------------------
+ HRUSER<<si_name>>,
+//----------------------------- << end user >> -------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ SCANOUTHCLK // Scan Chain Output
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // System address remapping control
+ input [3:0] REMAP; // REMAP input
+
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (inputs from master <<in>>)
+ input HSEL<<si_name>>; // Slave Select
+ input [<<addr>>:0] HADDR<<si_name>>; // Address bus
+ input [1:0] HTRANS<<si_name>>; // Transfer type
+ input HWRITE<<si_name>>; // Transfer direction
+ input [2:0] HSIZE<<si_name>>; // Transfer size
+ input [2:0] HBURST<<si_name>>; // Burst type
+ input [<<prot>>:0] HPROT<<si_name>>; // Protection control
+//---------------------------- << start unalign >> -----------------------------
+ input HUNALIGN<<si_name>>; // Unalign signal
+ input [<<bstrb>>:0] HBSTRB<<si_name>>; // Byte strobes
+//----------------------------- << end unalign >> ------------------------------
+ input [3:0] HMASTER<<si_name>>; // Master select
+ input [<<data>>:0] HWDATA<<si_name>>; // Write data
+ input HMASTLOCK<<si_name>>; // Locked Sequence
+ input HREADY<<si_name>>; // Transfer done
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] HAUSER<<si_name>>; // Address USER signals
+ input [<<user>>:0] HWUSER<<si_name>>; // Write-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (inputs from slave <<out>>)
+ input [<<data>>:0] HRDATA<<mi_name>>; // Read data bus
+ input HREADYOUT<<mi_name>>; // HREADY feedback
+ input [<<resp>>:0] HRESP<<mi_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] HRUSER<<mi_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ input SCANENABLE; // Scan enable signal
+ input SCANINHCLK; // HCLK scan input
+
+
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (outputs to slave <<out>>)
+ output HSEL<<mi_name>>; // Slave Select
+ output [<<addr>>:0] HADDR<<mi_name>>; // Address bus
+ output [1:0] HTRANS<<mi_name>>; // Transfer type
+ output HWRITE<<mi_name>>; // Transfer direction
+ output [2:0] HSIZE<<mi_name>>; // Transfer size
+ output [2:0] HBURST<<mi_name>>; // Burst type
+ output [<<prot>>:0] HPROT<<mi_name>>; // Protection control
+//---------------------------- << start unalign >> -----------------------------
+ output HUNALIGN<<mi_name>>; // Unalign signal
+ output [<<bstrb>>:0] HBSTRB<<mi_name>>; // Byte strobes
+//----------------------------- << end unalign >> ------------------------------
+ output [3:0] HMASTER<<mi_name>>; // Master select
+ output [<<data>>:0] HWDATA<<mi_name>>; // Write data
+ output HMASTLOCK<<mi_name>>; // Locked Sequence
+ output HREADYMUX<<mi_name>>; // Transfer done
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HAUSER<<mi_name>>; // Address USER signals
+ output [<<user>>:0] HWUSER<<mi_name>>; // Write-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (outputs to master <<in>>)
+ output [<<data>>:0] HRDATA<<si_name>>; // Read data bus
+ output HREADYOUT<<si_name>>; // HREADY feedback
+ output [<<resp>>:0] HRESP<<si_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HRUSER<<si_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ output SCANOUTHCLK; // Scan Chain Output
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // System address remapping control
+ wire [3:0] REMAP; // REMAP signal
+
+//------------------------------ << start in >> --------------------------------
+ // Input Port SI<<in>>
+ wire HSEL<<si_name>>; // Slave Select
+ wire [<<addr>>:0] HADDR<<si_name>>; // Address bus
+ wire [1:0] HTRANS<<si_name>>; // Transfer type
+ wire HWRITE<<si_name>>; // Transfer direction
+ wire [2:0] HSIZE<<si_name>>; // Transfer size
+ wire [2:0] HBURST<<si_name>>; // Burst type
+ wire [<<prot>>:0] HPROT<<si_name>>; // Protection control
+//---------------------------- << start unalign >> -----------------------------
+ wire HUNALIGN<<si_name>>; // Unalign signal
+ wire [<<bstrb>>:0] HBSTRB<<si_name>>; // Byte strobes
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] HMASTER<<si_name>>; // Master select
+ wire [<<data>>:0] HWDATA<<si_name>>; // Write data
+ wire HMASTLOCK<<si_name>>; // Locked Sequence
+ wire HREADY<<si_name>>; // Transfer done
+
+ wire [<<data>>:0] HRDATA<<si_name>>; // Read data bus
+ wire HREADYOUT<<si_name>>; // HREADY feedback
+ wire [<<resp>>:0] HRESP<<si_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HAUSER<<si_name>>; // Address USER signals
+ wire [<<user>>:0] HWUSER<<si_name>>; // Write-data USER signals
+ wire [<<user>>:0] HRUSER<<si_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output Port MI<<out>>
+ wire HSEL<<mi_name>>; // Slave Select
+ wire [<<addr>>:0] HADDR<<mi_name>>; // Address bus
+ wire [1:0] HTRANS<<mi_name>>; // Transfer type
+ wire HWRITE<<mi_name>>; // Transfer direction
+ wire [2:0] HSIZE<<mi_name>>; // Transfer size
+ wire [2:0] HBURST<<mi_name>>; // Burst type
+ wire [<<prot>>:0] HPROT<<mi_name>>; // Protection control
+//---------------------------- << start unalign >> -----------------------------
+ wire HUNALIGN<<mi_name>>; // Unalign signal
+ wire [<<bstrb>>:0] HBSTRB<<mi_name>>; // Byte strobes
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] HMASTER<<mi_name>>; // Master select
+ wire [<<data>>:0] HWDATA<<mi_name>>; // Write data
+ wire HMASTLOCK<<mi_name>>; // Locked Sequence
+ wire HREADYMUX<<mi_name>>; // Transfer done
+
+ wire [<<data>>:0] HRDATA<<mi_name>>; // Read data bus
+ wire HREADYOUT<<mi_name>>; // HREADY feedback
+ wire [<<resp>>:0] HRESP<<mi_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HAUSER<<mi_name>>; // Address USER signals
+ wire [<<user>>:0] HWUSER<<mi_name>>; // Write-data USER signals
+ wire [<<user>>:0] HRUSER<<mi_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+//----------------------------- << start in >> ---------------------------------
+
+ // Bus-switch input SI<<in>>
+ wire i_sel<<in>>; // HSEL signal
+ wire [<<addr>>:0] i_addr<<in>>; // HADDR signal
+ wire [1:0] i_trans<<in>>; // HTRANS signal
+ wire i_write<<in>>; // HWRITE signal
+ wire [2:0] i_size<<in>>; // HSIZE signal
+ wire [2:0] i_burst<<in>>; // HBURST signal
+ wire [<<prot>>:0] i_prot<<in>>; // HPROTS signal
+//---------------------------- << start unalign >> -----------------------------
+ wire i_unalign<<in>>; // HUNALIGN signal
+ wire [<<bstrb>>:0] i_bstrb<<in>>; // HBSTRB signal
+//----------------------------- << end unalign >> ------------------------------
+ wire [3:0] i_master<<in>>; // HMASTER signal
+ wire i_mastlock<<in>>; // HMASTLOCK signal
+ wire i_active<<in>>; // Active signal
+ wire i_held_tran<<in>>; // HeldTran signal
+ wire i_readyout<<in>>; // Readyout signal
+ wire [<<resp>>:0] i_resp<<in>>; // Response signal
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] i_auser<<in>>; // HAUSER signal
+//----------------------------- << end user >> ---------------------------------
+//------------------------------ << end in >> ----------------------------------
+
+//----------------------------- << start in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Bus-switch SI<<in>> to MI<<out>> signals
+ wire i_sel<<in>>to<<out>>; // Routing selection signal
+ wire i_active<<in>>to<<out>>; // Active signal
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+//------------------------------ << end in >> ----------------------------------
+//----------------------------- << start out >> --------------------------------
+ wire i_hready_mux_<<mi_name_lc>>; // Internal HREADYMUXM for MI<<out>>
+//------------------------------ << end out >> ---------------------------------
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//----------------------------- << start in >> ---------------------------------
+ // Input stage for SI<<in>>
+ <<input_stage_name>> u_<<input_stage_name>>_<<in>> (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL<<si_name>>),
+ .HADDRS (HADDR<<si_name>>),
+ .HTRANSS (HTRANS<<si_name>>),
+ .HWRITES (HWRITE<<si_name>>),
+ .HSIZES (HSIZE<<si_name>>),
+ .HBURSTS (HBURST<<si_name>>),
+ .HPROTS (HPROT<<si_name>>),
+//---------------------------- << start unalign >> -----------------------------
+ .HUNALIGNS (HUNALIGN<<si_name>>),
+ .HBSTRBS (HBSTRB<<si_name>>),
+//----------------------------- << end unalign >> ------------------------------
+ .HMASTERS (HMASTER<<si_name>>),
+ .HMASTLOCKS (HMASTLOCK<<si_name>>),
+ .HREADYS (HREADY<<si_name>>),
+//---------------------------- << start user >> --------------------------------
+ .HAUSERS (HAUSER<<si_name>>),
+//----------------------------- << end user >> ---------------------------------
+
+ // Internal Response
+ .active_ip (i_active<<in>>),
+ .readyout_ip (i_readyout<<in>>),
+ .resp_ip (i_resp<<in>>),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT<<si_name>>),
+ .HRESPS (HRESP<<si_name>>),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel<<in>>),
+ .addr_ip (i_addr<<in>>),
+//---------------------------- << start user >> --------------------------------
+ .auser_ip (i_auser<<in>>),
+//----------------------------- << end user >> ---------------------------------
+ .trans_ip (i_trans<<in>>),
+ .write_ip (i_write<<in>>),
+ .size_ip (i_size<<in>>),
+ .burst_ip (i_burst<<in>>),
+ .prot_ip (i_prot<<in>>),
+//---------------------------- << start unalign >> -----------------------------
+ .unalign_ip (i_unalign<<in>>),
+ .bstrb_ip (i_bstrb<<in>>),
+//----------------------------- << end unalign >> ------------------------------
+ .master_ip (i_master<<in>>),
+ .mastlock_ip (i_mastlock<<in>>),
+ .held_tran_ip (i_held_tran<<in>>)
+
+ );
+
+
+//------------------------------ << end in >> ----------------------------------
+//------------------------------ << start in >> --------------------------------
+ // Matrix decoder for SI<<in>>
+ <<matrix_decode_name>> u_<<matrix_decode_name_lc>> (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+//---------------------------- << start remap >> -------------------------------
+ // Internal address remapping control
+ .remapping_dec ( <<remapping_vector>> ),
+
+//----------------------------- << end remap >> --------------------------------
+ // Signals from Input stage SI<<in>>
+ .HREADYS (HREADY<<si_name>>),
+ .sel_dec (i_sel<<in>>),
+ .decode_addr_dec (i_addr<<in>>[<<addr>>:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans<<in>>),
+
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Control/Response for Output Stage MI<<out>>
+ .active_dec<<out>> (i_active<<in>>to<<out>>),
+ .readyout_dec<<out>> (i_hready_mux_<<mi_name_lc>>),
+ .resp_dec<<out>> (HRESP<<mi_name>>),
+ .rdata_dec<<out>> (HRDATA<<mi_name>>),
+//---------------------------- << start user >> --------------------------------
+ .ruser_dec<<out>> (HRUSER<<mi_name>>),
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ .sel_dec<<out>> (i_sel<<in>>to<<out>>),
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end out >> ---------------------------------
+
+ .active_dec (i_active<<in>>),
+ .HREADYOUTS (i_readyout<<in>>),
+ .HRESPS (i_resp<<in>>),
+//---------------------------- << start user >> --------------------------------
+ .HRUSERS (HRUSER<<si_name>>),
+//----------------------------- << end user >> ---------------------------------
+ .HRDATAS (HRDATA<<si_name>>)
+
+ );
+
+
+//------------------------------ << end in >> ----------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output stage for MI<<out>>
+ <<output_stage_name>> u_<<output_stage_name_lc>>_<<out>> (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ // Port <<in>> Signals
+ .sel_op<<in>> (i_sel<<in>>to<<out>>),
+ .addr_op<<in>> (i_addr<<in>>),
+//---------------------------- << start user >> --------------------------------
+ .auser_op<<in>> (i_auser<<in>>),
+//----------------------------- << end user >> ---------------------------------
+ .trans_op<<in>> (i_trans<<in>>),
+ .write_op<<in>> (i_write<<in>>),
+ .size_op<<in>> (i_size<<in>>),
+ .burst_op<<in>> (i_burst<<in>>),
+ .prot_op<<in>> (i_prot<<in>>),
+//---------------------------- << start unalign >> -----------------------------
+ .unalign_op<<in>> (i_unalign<<in>>),
+ .bstrb_op<<in>> (i_bstrb<<in>>),
+//----------------------------- << end unalign >> ------------------------------
+ .master_op<<in>> (i_master<<in>>),
+ .mastlock_op<<in>> (i_mastlock<<in>>),
+ .wdata_op<<in>> (HWDATA<<si_name>>),
+//---------------------------- << start user >> --------------------------------
+ .wuser_op<<in>> (HWUSER<<si_name>>),
+//----------------------------- << end user >> ---------------------------------
+ .held_tran_op<<in>> (i_held_tran<<in>>),
+
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end in >> ----------------------------------
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT<<mi_name>>),
+
+//------------------------------ << start in >> --------------------------------
+//----------------------------- << start connection >> -------------------------
+ .active_op<<in>> (i_active<<in>>to<<out>>),
+//------------------------------ << end connection >> --------------------------
+//------------------------------ << end in >> ----------------------------------
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL<<mi_name>>),
+ .HADDRM (HADDR<<mi_name>>),
+//---------------------------- << start user >> --------------------------------
+ .HAUSERM (HAUSER<<mi_name>>),
+//----------------------------- << end user >> ---------------------------------
+ .HTRANSM (HTRANS<<mi_name>>),
+ .HWRITEM (HWRITE<<mi_name>>),
+ .HSIZEM (HSIZE<<mi_name>>),
+ .HBURSTM (HBURST<<mi_name>>),
+ .HPROTM (HPROT<<mi_name>>),
+//---------------------------- << start unalign >> -----------------------------
+ .HUNALIGNM (HUNALIGN<<mi_name>>),
+ .HBSTRBM (HBSTRB<<mi_name>>),
+//----------------------------- << end unalign >> ------------------------------
+ .HMASTERM (HMASTER<<mi_name>>),
+ .HMASTLOCKM (HMASTLOCK<<mi_name>>),
+ .HREADYMUXM (i_hready_mux_<<mi_name_lc>>),
+//---------------------------- << start user >> --------------------------------
+ .HWUSERM (HWUSER<<mi_name>>),
+//----------------------------- << end user >> ---------------------------------
+ .HWDATAM (HWDATA<<mi_name>>)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX<<mi_name>> = i_hready_mux_<<mi_name_lc>>;
+
+
+//------------------------------ << end out >> ---------------------------------
+endmodule
+
+// --================================= End ===================================--
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
new file mode 100755
index 0000000000000000000000000000000000000000..44f8be46c9b3cf4d666fea95ca9f4b3e1202b705
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
@@ -0,0 +1,340 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : BusMatrixLite is a wrapper module that wraps around
+// the BusMatrix module to give AHB Lite compliant
+// slave and master interfaces.
+//
+//-----------------------------------------------------------------------------
+
+<<timescale_directive>>
+
+module <<component_name>> (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // System Address Remap control
+ REMAP,
+
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (inputs from master <<in>>)
+ HADDR<<si_name>>,
+ HTRANS<<si_name>>,
+ HWRITE<<si_name>>,
+ HSIZE<<si_name>>,
+ HBURST<<si_name>>,
+ HPROT<<si_name>>,
+ HWDATA<<si_name>>,
+ HMASTLOCK<<si_name>>,
+//---------------------------- << start user >> --------------------------------
+ HAUSER<<si_name>>,
+ HWUSER<<si_name>>,
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (inputs from slave <<out>>)
+ HRDATA<<mi_name>>,
+ HREADYOUT<<mi_name>>,
+ HRESP<<mi_name>>,
+//---------------------------- << start user >> ------------------------------
+ HRUSER<<mi_name>>,
+//----------------------------- << end user >> -------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ SCANENABLE, // Scan Test Mode Enable
+ SCANINHCLK, // Scan Chain Input
+
+
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (outputs to slave <<out>>)
+ HSEL<<mi_name>>,
+ HADDR<<mi_name>>,
+ HTRANS<<mi_name>>,
+ HWRITE<<mi_name>>,
+ HSIZE<<mi_name>>,
+ HBURST<<mi_name>>,
+ HPROT<<mi_name>>,
+ HWDATA<<mi_name>>,
+ HMASTLOCK<<mi_name>>,
+ HREADYMUX<<mi_name>>,
+//---------------------------- << start user >> --------------------------------
+ HAUSER<<mi_name>>,
+ HWUSER<<mi_name>>,
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (outputs to master <<in>>)
+ HRDATA<<si_name>>,
+ HREADY<<si_name>>,
+ HRESP<<si_name>>,
+//---------------------------- << start user >> ------------------------------
+ HRUSER<<si_name>>,
+//----------------------------- << end user >> -------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ SCANOUTHCLK // Scan Chain Output
+
+ );
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // System Address Remap control
+ input [3:0] REMAP; // System Address REMAP control
+
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (inputs from master <<in>>)
+ input [<<addr>>:0] HADDR<<si_name>>; // Address bus
+ input [1:0] HTRANS<<si_name>>; // Transfer type
+ input HWRITE<<si_name>>; // Transfer direction
+ input [2:0] HSIZE<<si_name>>; // Transfer size
+ input [2:0] HBURST<<si_name>>; // Burst type
+ input [<<prot>>:0] HPROT<<si_name>>; // Protection control
+ input [<<data>>:0] HWDATA<<si_name>>; // Write data
+ input HMASTLOCK<<si_name>>; // Locked Sequence
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] HAUSER<<si_name>>; // Address USER signals
+ input [<<user>>:0] HWUSER<<si_name>>; // Write-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (inputs from slave <<out>>)
+ input [<<data>>:0] HRDATA<<mi_name>>; // Read data bus
+ input HREADYOUT<<mi_name>>; // HREADY feedback
+ input HRESP<<mi_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ input [<<user>>:0] HRUSER<<mi_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ input SCANENABLE; // Scan enable signal
+ input SCANINHCLK; // HCLK scan input
+
+
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> (outputs to slave <<out>>)
+ output HSEL<<mi_name>>; // Slave Select
+ output [<<addr>>:0] HADDR<<mi_name>>; // Address bus
+ output [1:0] HTRANS<<mi_name>>; // Transfer type
+ output HWRITE<<mi_name>>; // Transfer direction
+ output [2:0] HSIZE<<mi_name>>; // Transfer size
+ output [2:0] HBURST<<mi_name>>; // Burst type
+ output [<<prot>>:0] HPROT<<mi_name>>; // Protection control
+ output [<<data>>:0] HWDATA<<mi_name>>; // Write data
+ output HMASTLOCK<<mi_name>>; // Locked Sequence
+ output HREADYMUX<<mi_name>>; // Transfer done
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HAUSER<<mi_name>>; // Address USER signals
+ output [<<user>>:0] HWUSER<<mi_name>>; // Write-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> (outputs to master <<in>>)
+ output [<<data>>:0] HRDATA<<si_name>>; // Read data bus
+ output HREADY<<si_name>>; // HREADY feedback
+ output HRESP<<si_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ output [<<user>>:0] HRUSER<<si_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+ // Scan test dummy signals; not connected until scan insertion
+ output SCANOUTHCLK; // Scan Chain Output
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // System Address Remap control
+ wire [3:0] REMAP; // System REMAP signal
+
+//------------------------------ << start in >> --------------------------------
+ // Input Port SI<<in>>
+ wire [<<addr>>:0] HADDR<<si_name>>; // Address bus
+ wire [1:0] HTRANS<<si_name>>; // Transfer type
+ wire HWRITE<<si_name>>; // Transfer direction
+ wire [2:0] HSIZE<<si_name>>; // Transfer size
+ wire [2:0] HBURST<<si_name>>; // Burst type
+ wire [<<prot>>:0] HPROT<<si_name>>; // Protection control
+ wire [<<data>>:0] HWDATA<<si_name>>; // Write data
+ wire HMASTLOCK<<si_name>>; // Locked Sequence
+
+ wire [<<data>>:0] HRDATA<<si_name>>; // Read data bus
+ wire HREADY<<si_name>>; // HREADY feedback
+ wire HRESP<<si_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HAUSER<<si_name>>; // Address USER signals
+ wire [<<user>>:0] HWUSER<<si_name>>; // Write-data USER signals
+ wire [<<user>>:0] HRUSER<<si_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+//----------------------------- << start out >> --------------------------------
+ // Output Port MI<<out>>
+ wire HSEL<<mi_name>>; // Slave Select
+ wire [<<addr>>:0] HADDR<<mi_name>>; // Address bus
+ wire [1:0] HTRANS<<mi_name>>; // Transfer type
+ wire HWRITE<<mi_name>>; // Transfer direction
+ wire [2:0] HSIZE<<mi_name>>; // Transfer size
+ wire [2:0] HBURST<<mi_name>>; // Burst type
+ wire [<<prot>>:0] HPROT<<mi_name>>; // Protection control
+ wire [<<data>>:0] HWDATA<<mi_name>>; // Write data
+ wire HMASTLOCK<<mi_name>>; // Locked Sequence
+ wire HREADYMUX<<mi_name>>; // Transfer done
+
+ wire [<<data>>:0] HRDATA<<mi_name>>; // Read data bus
+ wire HREADYOUT<<mi_name>>; // HREADY feedback
+ wire HRESP<<mi_name>>; // Transfer response
+//---------------------------- << start user >> --------------------------------
+ wire [<<user>>:0] HAUSER<<mi_name>>; // Address USER signals
+ wire [<<user>>:0] HWUSER<<mi_name>>; // Write-data USER signals
+ wire [<<user>>:0] HRUSER<<mi_name>>; // Read-data USER signals
+//----------------------------- << end user >> ---------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire [3:0] tie_hi_4;
+ wire tie_hi;
+ wire tie_low;
+//------------------------------ << start in >> --------------------------------
+ wire [<<resp>>:0] i_hresp<<si_name>>;
+//------------------------------- << end in >> ---------------------------------
+
+//----------------------------- << start out >> --------------------------------
+ wire [3:0] i_hmaster<<mi_name>>;
+ wire [<<resp>>:0] i_hresp<<mi_name>>;
+//------------------------------ << end out >> ---------------------------------
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+ assign tie_hi = 1'b1;
+ assign tie_hi_4 = 4'b1111;
+ assign tie_low = 1'b0;
+
+//------------------------------ << start in >> --------------------------------
+
+ assign HRESP<<si_name>> = i_hresp<<si_name>>[0];
+//------------------------------- << end in >> ---------------------------------
+
+//----------------------------- << start out >> --------------------------------
+ assign i_hresp<<mi_name>> = {{<<resp>>{tie_low}}, HRESP<<mi_name>>};
+//------------------------------ << end out >> ---------------------------------
+
+// BusMatrix instance
+ <<bus_matrix_name>> u<<bus_matrix_name>> (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .REMAP (REMAP),
+
+//------------------------------ << start in >> --------------------------------
+ // Input port SI<<in>> signals
+ .HSEL<<si_name>> (tie_hi),
+ .HADDR<<si_name>> (HADDR<<si_name>>),
+ .HTRANS<<si_name>> (HTRANS<<si_name>>),
+ .HWRITE<<si_name>> (HWRITE<<si_name>>),
+ .HSIZE<<si_name>> (HSIZE<<si_name>>),
+ .HBURST<<si_name>> (HBURST<<si_name>>),
+ .HPROT<<si_name>> (HPROT<<si_name>>),
+//---------------------------- << start unalign >> -----------------------------
+ .HUNALIGN<<si_name>> (tie_low),
+ .HBSTRB<<si_name>> ({(<<bstrb>>+1){tie_low}}),
+//----------------------------- << end unalign >> ------------------------------
+ .HWDATA<<si_name>> (HWDATA<<si_name>>),
+ .HMASTLOCK<<si_name>> (HMASTLOCK<<si_name>>),
+ .HMASTER<<si_name>> (tie_hi_4),
+ .HREADY<<si_name>> (HREADY<<si_name>>),
+//---------------------------- << start user >> --------------------------------
+ .HAUSER<<si_name>> (HAUSER<<si_name>>),
+ .HWUSER<<si_name>> (HWUSER<<si_name>>),
+//----------------------------- << end user >> ---------------------------------
+ .HRDATA<<si_name>> (HRDATA<<si_name>>),
+ .HREADYOUT<<si_name>> (HREADY<<si_name>>),
+ .HRESP<<si_name>> (i_hresp<<si_name>>),
+//---------------------------- << start user >> ------------------------------
+ .HRUSER<<si_name>> (HRUSER<<si_name>>),
+//----------------------------- << end user >> -------------------------------
+
+//------------------------------- << end in >> ---------------------------------
+
+//----------------------------- << start out >> --------------------------------
+ // Output port MI<<out>> signals
+ .HSEL<<mi_name>> (HSEL<<mi_name>>),
+ .HADDR<<mi_name>> (HADDR<<mi_name>>),
+ .HTRANS<<mi_name>> (HTRANS<<mi_name>>),
+ .HWRITE<<mi_name>> (HWRITE<<mi_name>>),
+ .HSIZE<<mi_name>> (HSIZE<<mi_name>>),
+ .HBURST<<mi_name>> (HBURST<<mi_name>>),
+ .HPROT<<mi_name>> (HPROT<<mi_name>>),
+//---------------------------- << start unalign >> -----------------------------
+ .HUNALIGN<<mi_name>> ( /* open */ ),
+ .HBSTRB<<mi_name>> ( /* open */ ),
+//----------------------------- << end unalign >> ------------------------------
+ .HWDATA<<mi_name>> (HWDATA<<mi_name>>),
+ .HMASTER<<mi_name>> (i_hmaster<<mi_name>>),
+ .HMASTLOCK<<mi_name>> (HMASTLOCK<<mi_name>>),
+ .HREADYMUX<<mi_name>> (HREADYMUX<<mi_name>>),
+//---------------------------- << start user >> --------------------------------
+ .HAUSER<<mi_name>> (HAUSER<<mi_name>>),
+ .HWUSER<<mi_name>> (HWUSER<<mi_name>>),
+//----------------------------- << end user >> ---------------------------------
+ .HRDATA<<mi_name>> (HRDATA<<mi_name>>),
+ .HREADYOUT<<mi_name>> (HREADYOUT<<mi_name>>),
+ .HRESP<<mi_name>> (i_hresp<<mi_name>>),
+//---------------------------- << start user >> ------------------------------
+ .HRUSER<<mi_name>> (HRUSER<<mi_name>>),
+//----------------------------- << end user >> -------------------------------
+
+//------------------------------ << end out >> ---------------------------------
+
+ // Scan test dummy signals; not connected until scan insertion
+ .SCANENABLE (SCANENABLE),
+ .SCANINHCLK (SCANINHCLK),
+ .SCANOUTHCLK (SCANOUTHCLK)
+ );
+
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_full.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_full.xml
new file mode 100755
index 0000000000000000000000000000000000000000..63fec5db2a916195a8330005302785c75a64b214
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_full.xml
@@ -0,0 +1,85 @@
+<?xml version="1.0" encoding="iso-8859-1" ?>
+
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file -->
+<!-- may only be used by a person authorised under and to the extent -->
+<!-- permitted by a subsisting licensing agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2013 Arm Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person -->
+<!-- is permitted to do so under the terms of a subsisting license -->
+<!-- agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Version and Release Control Information: -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : Example XML file, defining an interconnect for -->
+<!-- 2 AHB Masters and 3 AHB Slaves. -->
+<!-- -->
+<!-- Note : This information will overwrite parameters -->
+<!-- specified on the command line -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<cfgfile>
+
+ <!-- - - - - *** DO NOT MODIFY ABOVE THIS LINE *** - - - - - - - - - - - -->
+
+ <!-- Global definitions -->
+
+ <architecture_version>ahb2</architecture_version>
+ <arbitration_scheme>round</arbitration_scheme>
+ <routing_data_width>32</routing_data_width>
+ <routing_address_width>32</routing_address_width>
+ <user_signal_width>32</user_signal_width>
+ <bus_matrix_name>cmsdk_MyBusMatrixName</bus_matrix_name>
+ <input_stage_name>cmsdk_MyInputName</input_stage_name>
+ <matrix_decode_name>cmsdk_MyDecoderName</matrix_decode_name>
+ <output_arbiter_name>cmsdk_MyArbiterName</output_arbiter_name>
+ <output_stage_name>cmsdk_MyOutputName</output_stage_name>
+
+
+ <!-- Slave interface definitions -->
+
+ <slave_interface name="S0">
+ <sparse_connect interface="M0"/>
+ <sparse_connect interface= "M1"/>
+ <sparse_connect interface= "M2"/>
+ <address_region interface="M0" mem_lo="00000000" mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="M0" mem_lo="20000000" mem_hi="2fffffff" remapping='none'/>
+ <address_region interface="M1" mem_lo="30000000" mem_hi="4fffffff" remapping='none'/>
+ <address_region interface="M2" mem_lo="50000000" mem_hi="5fffffff" remapping='none'/>
+ <remap_region interface="M0" mem_lo="00000000" mem_hi="0000ffff" bit="0"/>
+ </slave_interface>
+
+
+ <slave_interface name="S1">
+ <sparse_connect interface="M0"/>
+ <sparse_connect interface="M1"/>
+ <sparse_connect interface="M2"/>
+ <address_region interface="M0" mem_lo="00000000" mem_hi="2fffffff" remapping='none'/>
+ <address_region interface="M1" mem_lo="30000000" mem_hi="4fffffff" remapping='none'/>
+ <address_region interface="M1" mem_lo="50000000" mem_hi="7fffffff" remapping='none'/>
+ <remap_region interface="M1" mem_lo="00000000" mem_hi="0001ffff" bit="0"/>
+ <address_region interface="M2" mem_lo="80000000" mem_hi="9fffffff" remapping='none'/>
+ </slave_interface>
+
+
+ <!-- Master interface definitions -->
+
+ <master_interface name="M0"/>
+ <master_interface name="M1"/>
+ <master_interface name="M2"/>
+
+ <!-- - - - - *** DO NOT MODIFY BELOW THIS LINE *** - - - - - - - - - - - -->
+
+</cfgfile>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_sparse.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_sparse.xml
new file mode 100755
index 0000000000000000000000000000000000000000..ae3bf3cd733ef65e0915aec8ea7bedbd44434721
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_sparse.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="iso-8859-1" ?>
+
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file -->
+<!-- may only be used by a person authorised under and to the extent -->
+<!-- permitted by a subsisting licensing agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person -->
+<!-- is permitted to do so under the terms of a subsisting license -->
+<!-- agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Version and Release Control Information: -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : Example XML file, defining an interconnect for -->
+<!-- 2 AHB Masters and 3 AHB Slaves. -->
+<!-- -->
+<!-- Note : This information will overwrite parameters -->
+<!-- specified on the command line -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<cfgfile>
+
+ <!-- - - - - *** DO NOT MODIFY ABOVE THIS LINE *** - - - - - - - - - - - -->
+
+ <!-- Global definitions -->
+
+ <architecture_version>v6</architecture_version>
+ <arbitration_scheme>fixed</arbitration_scheme>
+ <routing_data_width>32</routing_data_width>
+ <routing_address_width>32</routing_address_width>
+ <user_signal_width>32</user_signal_width>
+ <bus_matrix_name>cmsdk_MyBusMatrixName</bus_matrix_name>
+ <input_stage_name>cmsdk_MyInputName</input_stage_name>
+ <matrix_decode_name>cmsdk_MyDecoderName</matrix_decode_name>
+ <output_arbiter_name>cmsdk_MyArbiterName</output_arbiter_name>
+ <output_stage_name>cmsdk_MyOutputName</output_stage_name>
+
+
+ <!-- Slave interface definitions -->
+
+ <slave_interface name="S0">
+ <sparse_connect interface="M0"/>
+ <sparse_connect interface= "M1"/>
+ <address_region interface="M0" mem_lo="00000000" mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="M0" mem_lo="20000000" mem_hi="2fffffff" remapping='none'/>
+ <address_region interface="M1" mem_lo="30000000" mem_hi="4fffffff" remapping='none'/>
+ <remap_region interface="M0" mem_lo="00000000" mem_hi="0000ffff" bit="0"/>
+ </slave_interface>
+
+
+ <slave_interface name="S1">
+ <sparse_connect interface="M1"/>
+ <sparse_connect interface="M2"/>
+ <address_region interface="M1" mem_lo="30000000" mem_hi="4fffffff" remapping='none'/>
+ <address_region interface="M1" mem_lo="50000000" mem_hi="7fffffff" remapping='none'/>
+ <remap_region interface="M1" mem_lo="00000000" mem_hi="0001ffff" bit="0"/>
+ <address_region interface="M2" mem_lo="80000000" mem_hi="9fffffff" remapping='none'/>
+ </slave_interface>
+
+
+ <!-- Master interface definitions -->
+
+ <master_interface name="M0"/>
+ <master_interface name="M1"/>
+ <master_interface name="M2"/>
+
+ <!-- - - - - *** DO NOT MODIFY BELOW THIS LINE *** - - - - - - - - - - - -->
+
+</cfgfile>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b1ddc80c117821e2174ec12d18de2336f0a78f60
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="iso-8859-1" ?>
+
+<!--//----------------------------------------------------------------------------- -->
+<!--// customised interconnect specification for ADP/DMA/ Cortex-M0 controller -->
+<!--// -->
+<!--// Contributors -->
+<!--// -->
+<!--// David Flynn (d.w.flynn@soton.ac.uk) -->
+<!--// -->
+<!--// Copyright (C) 2023, SoC Labs (www.soclabs.org) -->
+<!--//----------------------------------------------------------------------------- -->
+
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file -->
+<!-- may only be used by a person authorised under and to the extent -->
+<!-- permitted by a subsisting licensing agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2013 Arm Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person -->
+<!-- is permitted to do so under the terms of a subsisting license -->
+<!-- agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Version and Release Control Information: -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : based on Example XML file, defining an interconnect for -->
+<!-- (was 2 AHB Masters and 3 AHB Slaves.) -->
+<!-- 5 AHB subordinates and 3 AHB controllers -->
+<!-- -->
+<!-- Note : This information will overwrite parameters -->
+<!-- specified on the command line -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<cfgfile>
+
+ <!-- - - - - *** DO NOT MODIFY ABOVE THIS LINE *** - - - - - - - - - - - -->
+
+ <!-- Global definitions -->
+
+ <architecture_version>ahb2</architecture_version>
+ <arbitration_scheme>burst</arbitration_scheme>
+ <routing_data_width>32</routing_data_width>
+ <routing_address_width>32</routing_address_width>
+ <user_signal_width>2</user_signal_width>
+ <bus_matrix_name>soclabs_4x7_AhbMatrix</bus_matrix_name>
+ <input_stage_name>soclabs_4x7_MasterInput</input_stage_name>
+ <matrix_decode_name>soclabs_4x7_MatrixDecode</matrix_decode_name>
+ <output_arbiter_name>soclabs_4x7_Arbiter</output_arbiter_name>
+ <output_stage_name>soclabs_4x7_SlaveOutput</output_stage_name>
+
+
+ <!-- Slave interface definitions -->
+
+ <slave_interface name="_adp">
+ <sparse_connect interface="_rom1"/>
+ <sparse_connect interface="_ram2"/>
+ <sparse_connect interface="_ram3"/>
+ <sparse_connect interface="_sys"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_ram8"/>
+ <sparse_connect interface="_ram9"/>
+ <address_region interface="_rom1" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
+ <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ <address_region interface="_sys" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
+ <remap_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ </slave_interface>
+
+ <slave_interface name="_dma">
+ <sparse_connect interface="_rom1"/>
+ <sparse_connect interface="_ram2"/>
+ <sparse_connect interface="_ram3"/>
+ <sparse_connect interface="_sys"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_ram8"/>
+ <sparse_connect interface="_ram9"/>
+ <address_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ </slave_interface>
+
+ <slave_interface name="_dma2">
+ <sparse_connect interface="_rom1"/>
+ <sparse_connect interface="_ram2"/>
+ <sparse_connect interface="_ram3"/>
+ <sparse_connect interface="_sys"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_ram8"/>
+ <sparse_connect interface="_ram9"/>
+ <address_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ </slave_interface>
+
+ <slave_interface name="_cpu">
+ <sparse_connect interface="_rom1"/>
+ <sparse_connect interface="_ram2"/>
+ <sparse_connect interface="_ram3"/>
+ <sparse_connect interface="_sys"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_ram8"/>
+ <sparse_connect interface="_ram9"/>
+ <address_region interface="_rom1" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
+ <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ <address_region interface="_sys" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
+ <remap_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ </slave_interface>
+
+ <!-- Master interface definitions -->
+
+ <master_interface name="_rom1"/>
+ <master_interface name="_ram2"/>
+ <master_interface name="_ram3"/>
+ <master_interface name="_sys"/>
+ <master_interface name="_ram8"/>
+ <master_interface name="_ram9"/>
+ <master_interface name="_exp"/>
+
+ <!-- - - - - *** DO NOT MODIFY BELOW THIS LINE *** - - - - - - - - - - - -->
+
+</cfgfile>
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
new file mode 100644
index 0000000000000000000000000000000000000000..fe5fd48dcaf9b696041d165129a3ae72241c4dfb
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -0,0 +1,1583 @@
+//-----------------------------------------------------------------------------
+// customised top-level Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+
+module nanosoc_chip
+ (
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+ input wire xtal_clk_i,
+ output wire xtal_clk_o,
+ input wire nrst_i,
+ input wire [15:0] p0_i, // level-shifted input from pad
+ output wire [15:0] p0_o, // output port drive
+ output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
+ input wire [15:0] p1_i, // level-shifted input from pad
+ output wire [15:0] p1_o, // output port drive
+ output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
+
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+ input wire ntrst_i,
+ input wire tdi_i,
+ output wire tdo_o,
+`endif
+ input wire swdio_i,
+ output wire swdio_o,
+ output wire swdio_e,
+ output wire swdio_z,
+ input wire swdclk_i
+ );
+
+localparam CLKGATE_PRESENT = 0;
+localparam DMA_CHANNEL_NUM = 1;
+localparam INCLUDE_DMA = 1;
+localparam CORTEX_M0 = 1;
+
+//------------------------------------
+// CMSDK internal wire naming preserved
+
+ wire xtal_clk_in = xtal_clk_i;
+ wire xtal_clk_out;
+ wire pll_clk;
+ wire CLK;
+
+ assign xtal_clk_o = xtal_clk_out;
+ wire nrst_in = nrst_i;
+ wire [15:0] p0_in; // level-shifted input from pad
+ wire [15:0] p0_out; // output port drive
+ wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
+
+ wire [15:0] p1_in; // level-shifted input from pad
+ wire [15:0] p1_out; // output port drive
+ wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_in_mux; // level-shifted input from pad
+ wire [15:0] p1_out_mux; // output port drive
+ wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
+
+ wire swdio_in;
+ wire swdio_out;
+ wire swdio_out_en;
+ wire swdio_out_nen;
+ wire swdclk_in;
+
+ wire ft_clk_o;
+ wire ft_ssn_o;
+ wire ft_miso_i;
+ wire ft_miosio_o;
+ wire ft_miosio_e;
+ wire ft_miosio_z;
+ wire ft_miosio_i;
+
+ // --------------------------------------------------------------------------------
+ // Port-0 IO pad driver mapping
+ // --------------------------------------------------------------------------------
+
+ assign p0_in = p0_i; // level-shifted input from pad
+ assign p0_o = p0_out; // output port drive
+ assign p0_e = p0_out_en; // active high output drive enable (pad tech dependent)
+ assign p0_z = p0_out_nen; // active low output drive enable (pad tech dependent)
+
+
+ // --------------------------------------------------------------------------------
+ // Port-1 IO pad driver mapping
+ // --------------------------------------------------------------------------------
+
+// modify p1_mux [3:0] for ft1248 interface
+// assign p1_in_mux[3:0] = p1_i[3:0]; // IO MUX controlled bidirectionals
+// assign p1_o[3:0] = p1_out_mux[3:0];
+// assign p1_e[3:0] = p1_out_en_mux[3:0];
+// assign p1_z[3:0] = p1_out_nen_mux[3:0];
+
+ assign ft_miso_i = p1_i[0]; // FT_MISO INPUT pad configuration
+ assign p1_in_mux[0] = p1_i[0];
+ assign p1_o[0] = 1'b0;
+ assign p1_e[0] = 1'b0;
+ assign p1_z[0] = 1'b1;
+
+ assign p1_in_mux[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
+ assign p1_o[1] = ft_clk_o;
+ assign p1_e[1] = 1'b1;
+ assign p1_z[1] = 1'b0;
+
+ assign ft_miosio_i = p1_i[2]; // FT_MIOSIO INOUT pad configuration
+ assign p1_in_mux[2] = p1_i[2];
+ assign p1_o[2] = ft_miosio_o;
+ assign p1_e[2] = ft_miosio_e;
+ assign p1_z[2] = ft_miosio_z;
+
+ assign p1_in_mux[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
+ assign p1_o[3] = ft_ssn_o;
+ assign p1_e[3] = 1'b1;
+ assign p1_z[3] = 1'b0;
+
+ assign p1_in_mux[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
+ assign p1_o[15:4] = p1_out_mux[15:4];
+ assign p1_e[15:4] = p1_out_en_mux[15:4];
+ assign p1_z[15:4] = p1_out_nen_mux[15:4];
+
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+
+
+//----------------------------------------
+// SOC clock and reset management
+//----------------------------------------
+//
+
+ wire PORESETn;// Power on reset
+ wire HRESETn; // AHB reset
+ wire PRESETn; // APB and peripheral reset
+ wire DBGRESETn; // Debug system reset
+ wire FCLK; // Free running system clock
+ wire HCLK; // System clock from PMU
+ wire DCLK;
+ wire SCLK;
+ wire PCLK; // Peripheral clock
+ wire PCLKG; // Gated PCLK for APB
+ wire PCLKEN; // Clock divider for AHB to APB bridge
+ wire APBACTIVE;
+ // event signals
+ wire TXEV;
+ wire RXEV;
+ wire nTRST; // JTAG - Test reset (active low)
+ wire SWDI; // JTAG/SWD - TMS / SWD data input
+ wire SWCLK; // JTAG/SWD - TCK / SWCLK
+ wire SWDO; // SWD - SWD data output
+ wire SWDOEN; // SWD - SWD data output enable
+ wire SYSRESETREQ; // processor system reset request
+ wire WDOGRESETREQ; // watchdog system reset request
+ wire HRESETREQ; // Combined system reset request
+ wire cmsdk_SYSRESETREQ; // Combined system reset request
+ wire clk_ctrl_sys_reset_req;
+ wire PMUHRESETREQ;
+ wire PMUDBGRESETREQ;
+ wire LOCKUP;
+ wire LOCKUPRESET;
+ wire SLEEPING;
+ wire GATEHCLK; // Processor status - safe to gate HCLK
+ wire WAKEUP; // Wake up request from WIC
+ wire WICENREQ; // WIC enable request from PMU
+ wire WICENACK; // WIC enable ack to PMU
+ wire PMUENABLE;
+ wire CDBGPWRUPREQ; // Debug Power Up request to PMU
+ wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
+ wire SLEEPHOLDREQn; // Sleep extension request from PMU
+ wire SLEEPHOLDACKn; // Sleep extension request to PMU wire SLEEPING;
+ wire SYSPWRDOWNACK;
+ wire DBGPWRDOWNACK;
+ wire SYSPWRDOWN;
+ wire DBGPWRDOWN;
+ wire SYSISOLATEn;
+ wire SYSRETAINn;
+ wire DBGISOLATEn;
+ wire SLEEPDEEP;
+ wire ADPRESETREQ;
+ // Scan test dummy signals; not connected until scan insertion
+ wire TESTMODE; // Test mode enable signal (override synchronizers etc)
+ wire SCANENABLE; // Scan enable signal
+ wire SCANINHCLK; // HCLK scan input
+ wire SCANOUTHCLK; // Scan Chain wire
+
+// not required for FPGA
+ assign TESTMODE = 1'b0;
+ assign SCANENABLE = 1'b0;
+ assign SCANINHCLK = 1'b0;
+ assign SCANOUTHCLK = 1'b0;
+
+// Technology-specific PLL/Frequecy synthesizer would generate
+// CLK, FCLK (Free running system clock)
+// from
+// xtal_clk_in
+
+ assign pll_clk = xtal_clk_in; // default to no PLL
+
+ assign CLK = (TESTMODE) ? xtal_clk_in : pll_clk;
+
+
+//? assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
+ assign HCLK = FCLK;
+
+ // System Reset request can be from processor or watchdog
+ // or when lockup happens and the control flag is set.
+ assign cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
+ ADPRESETREQ |
+ (LOCKUP & LOCKUPRESET);
+ assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
+
+ // Clock controller to generate reset and clock signals
+ cmsdk_mcu_clkctrl
+ #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
+ u_cmsdk_mcu_clkctrl(
+ // inputs
+ .XTAL1 (CLK),
+ .NRST (nrst_in),
+
+ .APBACTIVE (APBACTIVE),
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP),
+ .LOCKUP (LOCKUP),
+ .LOCKUPRESET (LOCKUPRESET),
+ .SYSRESETREQ (clk_ctrl_sys_reset_req),
+ .DBGRESETREQ (PMUDBGRESETREQ),
+ .CGBYPASS (TESTMODE),
+ .RSTBYPASS (TESTMODE),
+
+ // outputs
+ .XTAL2 (xtal_clk_out),
+
+ .FCLK (FCLK),
+
+ .PCLK (PCLK),
+ .PCLKG (PCLKG),
+ .PCLKEN (PCLKEN),
+//?`ifdef CORTEX_M0DESIGNSTART
+//? .PORESETn (PORESETn), // for cm0 designstart
+//? .HRESETn (HRESETn), // for cm0 designstart
+//?`endif
+ .PRESETn (PRESETn)
+ );
+
+ wire gated_hclk;
+ wire gated_dclk;
+ wire gated_sclk;
+
+ cortexm0_rst_ctl u_rst_ctl
+ (// Inputs
+ .GLOBALRESETn (nrst_in),
+ .FCLK (FCLK),
+ .HCLK (HCLK), //gated_hclk),
+ .DCLK (DCLK), //gated_dclk),
+ .SYSRESETREQ (cmsdk_SYSRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .RSTBYPASS (1'b0),
+ .SE (1'b0),
+
+ // Outputs
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .HRESETREQ (HRESETREQ));
+
+
+ // Cortex-M0 Power management unit
+ cortexm0_pmu u_cortexm0_pmu
+ ( // Inputs
+ .FCLK (FCLK),
+ .PORESETn (PORESETn),
+ .HRESETREQ (cmsdk_SYSRESETREQ), // from processor / watchdog
+ .PMUENABLE (PMUENABLE), // from System Controller
+ .WICENACK (WICENACK), // from WIC in integration
+
+ .WAKEUP (WAKEUP), // from WIC in integration
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .SLEEPDEEP (SLEEPDEEP),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .GATEHCLK (GATEHCLK),
+ .SYSPWRDOWNACK (SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (DBGPWRDOWNACK),
+ .CGBYPASS (TESTMODE),
+
+ // Outputs
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SCLK (gated_sclk),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .SYSISOLATEn (SYSISOLATEn),
+ .SYSRETAINn (SYSRETAINn),
+ .SYSPWRDOWN (SYSPWRDOWN),
+ .DBGISOLATEn (DBGISOLATEn),
+ .DBGPWRDOWN (DBGPWRDOWN),
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ)
+ );
+
+ // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
+ assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
+ assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
+ assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;
+
+
+ // In this example system, power control takes place immediately.
+ // In a real circuit you might need to add delays in the next two
+ // signal assignments for correct operation.
+ assign SYSPWRDOWNACK = SYSPWRDOWN;
+ assign DBGPWRDOWNACK = DBGPWRDOWN;
+
+ wire exp_penable;
+ wire exp_pwrite;
+ wire [11:0] exp_paddr;
+ wire [31:0] exp_pwdata;
+ wire exp12_psel;
+ wire exp12_pready;
+ wire exp12_pslverr;
+ wire [31:0] exp12_prdata;
+ wire exp13_psel;
+ wire exp13_pready;
+ wire exp13_pslverr;
+ wire [31:0] exp13_prdata;
+ wire exp14_psel;
+ wire exp14_pready;
+ wire exp14_pslverr;
+ wire [31:0] exp14_prdata;
+ wire exp15_psel;
+ wire exp15_pready;
+ wire exp15_pslverr;
+ wire [31:0] exp15_prdata;
+
+
+ // internal peripheral signals
+ wire uart0_rxd;
+ wire uart0_txd;
+ wire uart0_txen;
+ wire uart1_rxd;
+ wire uart1_txd;
+ wire uart1_txen;
+ wire uart2_rxd;
+ wire uart2_txd;
+ wire uart2_txen;
+ wire timer0_extin;
+ wire timer1_extin;
+
+ wire [15:0] p0_altfunc;
+
+ wire [15:0] p1_altfunc;
+
+
+// -----------------------------------------------------------------------------
+// AHB Interconnect declarations
+// Upper-case AMBA naming convention maintained
+// -----------------------------------------------------------------------------
+
+ // System Address Remap control
+ wire [3:0] REMAP; // System Address REMAP control, bit-0 set on POR
+ wire ROM_MAP;
+
+ // Manager port SI0 (inputs from master 0)
+ wire [31:0] HADDR_adp; // Address bus
+ wire [1:0] HTRANS_adp; // Transfer type
+ wire HWRITE_adp; // Transfer direction
+ wire [2:0] HSIZE_adp; // Transfer size
+ wire [2:0] HBURST_adp; // Burst type
+ wire [3:0] HPROT_adp; // Protection control
+ wire [31:0] HWDATA_adp; // Write data
+ wire HMASTLOCK_adp; // Locked Sequence
+ wire [1:0] HAUSER_adp; // Address USER signals
+ wire [1:0] HWUSER_adp; // Write-data USER signals
+ // Manager port SI0 (outputs to master 0)
+ wire [31:0] HRDATA_adp; // Read data bus
+ wire HREADY_adp; // HREADY feedback
+ wire HRESP_adp; // Transfer response
+ wire [1:0] HRUSER_adp; // Read-data USER signals
+
+ // Manager port SI1 (inputs from master 1)
+ wire [31:0] HADDR_dma; // Address bus
+ wire [1:0] HTRANS_dma; // Transfer type
+ wire HWRITE_dma; // Transfer direction
+ wire [2:0] HSIZE_dma; // Transfer size
+ wire [2:0] HBURST_dma; // Burst type
+ wire [3:0] HPROT_dma; // Protection control
+ wire [31:0] HWDATA_dma; // Write data
+ wire HMASTLOCK_dma; // Locked Sequence
+ wire [1:0] HAUSER_dma; // Address USER signals
+ wire [1:0] HWUSER_dma; // Write-data USER signals
+ // Manager port SI1 (outputs to master 1)
+ wire [31:0] HRDATA_dma; // Read data bus
+ wire HREADY_dma; // HREADY feedback
+ wire HRESP_dma; // Transfer response
+ wire [1:0] HRUSER_dma; // Read-data USER signals
+
+ // Manager port SI2 (inputs from master 2)
+ wire [31:0] HADDR_dma2; // Address bus
+ wire [1:0] HTRANS_dma2; // Transfer type
+ wire HWRITE_dma2; // Transfer direction
+ wire [2:0] HSIZE_dma2; // Transfer size
+ wire [2:0] HBURST_dma2; // Burst type
+ wire [3:0] HPROT_dma2; // Protection control
+ wire [31:0] HWDATA_dma2; // Write data
+ wire HMASTLOCK_dma2; // Locked Sequence
+ wire [1:0] HAUSER_dma2; // Address USER signals
+ wire [1:0] HWUSER_dma2; // Write-data USER signals
+ // Manager port SI2 (outputs to master 2)
+ wire [31:0] HRDATA_dma2; // Read data bus
+ wire HREADY_dma2; // HREADY feedback
+ wire HRESP_dma2; // Transfer response
+ wire [1:0] HRUSER_dma2; // Read-data USER signals
+
+ // Manager port SI3 (inputs from master 3)
+ wire [31:0] HADDR_cpu; // Address bus
+ wire [1:0] HTRANS_cpu; // Transfer type
+ wire HWRITE_cpu; // Transfer direction
+ wire [2:0] HSIZE_cpu; // Transfer size
+ wire [2:0] HBURST_cpu; // Burst type
+ wire [3:0] HPROT_cpu; // Protection control
+ wire [31:0] HWDATA_cpu; // Write data
+ wire HMASTLOCK_cpu; // Locked Sequence
+ wire [1:0] HAUSER_cpu; // Address USER signals
+ wire [1:0] HWUSER_cpu; // Write-data USER signals
+ // Manager port SI3 (outputs to master 3)
+ wire [31:0] HRDATA_cpu; // Read data bus
+ wire HREADY_cpu; // HREADY feedback
+ wire HRESP_cpu; // Transfer response
+ wire [1:0] HRUSER_cpu; // Read-data USER signals
+
+ // Subordinate port MI0 (outputs to slave 0)
+ wire HSEL_rom1; // Slave Select
+ wire [31:0] HADDR_rom1; // Address bus
+ wire [1:0] HTRANS_rom1; // Transfer type
+ wire HWRITE_rom1; // Transfer direction
+ wire [2:0] HSIZE_rom1; // Transfer size
+ wire [2:0] HBURST_rom1; // Burst type
+ wire [3:0] HPROT_rom1; // Protection control
+ wire [31:0] HWDATA_rom1; // Write data
+ wire HMASTLOCK_rom1; // Locked Sequence
+ wire HREADYMUX_rom1; // Transfer done
+ wire [1:0] HAUSER_rom1; // Address USER signals
+ wire [1:0] HWUSER_rom1; // Write-data USER signals
+ // Subordinate port MI0 (inputs from slave 0)
+ wire [31:0] HRDATA_rom1; // Read data bus
+ wire HREADYOUT_rom1; // HREADY feedback
+ wire HRESP_rom1; // Transfer response
+ wire [1:0] HRUSER_rom1; // Read-data USER signals
+
+ // Subordinate port MI1 (outputs to slave 1)
+ wire HSEL_ram2; // Slave Select
+ wire [31:0] HADDR_ram2; // Address bus
+ wire [1:0] HTRANS_ram2; // Transfer type
+ wire HWRITE_ram2; // Transfer direction
+ wire [2:0] HSIZE_ram2; // Transfer size
+ wire [2:0] HBURST_ram2; // Burst type
+ wire [3:0] HPROT_ram2; // Protection control
+ wire [31:0] HWDATA_ram2; // Write data
+ wire HMASTLOCK_ram2; // Locked Sequence
+ wire HREADYMUX_ram2; // Transfer done
+ wire [1:0] HAUSER_ram2; // Address USER signals
+ wire [1:0] HWUSER_ram2; // Write-data USER signals
+ // Subordinate port MI1 (inputs from slave 1)
+ wire [31:0] HRDATA_ram2; // Read data bus
+ wire HREADYOUT_ram2; // HREADY feedback
+ wire HRESP_ram2; // Transfer response
+ wire [1:0] HRUSER_ram2; // Read-data USER signals
+
+ // Subordinate port MI2 (outputs to slave 2)
+ wire HSEL_ram3; // Slave Select
+ wire [31:0] HADDR_ram3; // Address bus
+ wire [1:0] HTRANS_ram3; // Transfer type
+ wire HWRITE_ram3; // Transfer direction
+ wire [2:0] HSIZE_ram3; // Transfer size
+ wire [2:0] HBURST_ram3; // Burst type
+ wire [3:0] HPROT_ram3; // Protection control
+ wire [31:0] HWDATA_ram3; // Write data
+ wire HMASTLOCK_ram3; // Locked Sequence
+ wire HREADYMUX_ram3; // Transfer done
+ wire [1:0] HAUSER_ram3; // Address USER signals
+ wire [1:0] HWUSER_ram3; // Write-data USER signals
+ // Subordinate port MI2 (inputs from slave 2)
+ wire [31:0] HRDATA_ram3; // Read data bus
+ wire HREADYOUT_ram3; // HREADY feedback
+ wire HRESP_ram3; // Transfer response
+ wire [1:0] HRUSER_ram3; // Read-data USER signals
+
+ // Subordinate port MI3 (outputs to slave 3)
+ wire HSEL_sys; // Slave Select
+ wire [31:0] HADDR_sys; // Address bus
+ wire [1:0] HTRANS_sys; // Transfer type
+ wire HWRITE_sys; // Transfer direction
+ wire [2:0] HSIZE_sys; // Transfer size
+ wire [2:0] HBURST_sys; // Burst type
+ wire [3:0] HPROT_sys; // Protection control
+ wire [31:0] HWDATA_sys; // Write data
+ wire HMASTLOCK_sys; // Locked Sequence
+ wire HREADYMUX_sys; // Transfer done
+ wire [1:0] HAUSER_sys; // Address USER signals
+ wire [1:0] HWUSER_sys; // Write-data USER signals
+ // Subordinate port MI3 (inputs from slave 3)
+ wire [31:0] HRDATA_sys; // Read data bus
+ wire HREADYOUT_sys; // HREADY feedback
+ wire HRESP_sys; // Transfer response
+ wire [1:0] HRUSER_sys; // Read-data USER signals
+
+ // Subordinate port MI4 (outputs to slave 4)
+ wire HSEL_ram8; // Slave Select
+ wire [31:0] HADDR_ram8; // Address bus
+ wire [1:0] HTRANS_ram8; // Transfer type
+ wire HWRITE_ram8; // Transfer direction
+ wire [2:0] HSIZE_ram8; // Transfer size
+ wire [2:0] HBURST_ram8; // Burst type
+ wire [3:0] HPROT_ram8; // Protection control
+ wire [31:0] HWDATA_ram8; // Write data
+ wire HMASTLOCK_ram8; // Locked Sequence
+ wire HREADYMUX_ram8; // Transfer done
+ wire [1:0] HAUSER_ram8; // Address USER signals
+ wire [1:0] HWUSER_ram8; // Write-data USER signals
+ // Subordinate port MI4 (inputs from slave 4)
+ wire [31:0] HRDATA_ram8; // Read data bus
+ wire HREADYOUT_ram8; // HREADY feedback
+ wire HRESP_ram8; // Transfer response
+ wire [1:0] HRUSER_ram8; // Read-data USER signals
+
+ // Subordinate port MI5 (outputs to slave 5)
+ wire HSEL_ram9; // Slave Select
+ wire [31:0] HADDR_ram9; // Address bus
+ wire [1:0] HTRANS_ram9; // Transfer type
+ wire HWRITE_ram9; // Transfer direction
+ wire [2:0] HSIZE_ram9; // Transfer size
+ wire [2:0] HBURST_ram9; // Burst type
+ wire [3:0] HPROT_ram9; // Protection control
+ wire [31:0] HWDATA_ram9; // Write data
+ wire HMASTLOCK_ram9; // Locked Sequence
+ wire HREADYMUX_ram9; // Transfer done
+ wire [1:0] HAUSER_ram9; // Address USER signals
+ wire [1:0] HWUSER_ram9; // Write-data USER signals
+ // Subordinate port MI5 (inputs from slave 5)
+ wire [31:0] HRDATA_ram9; // Read data bus
+ wire HREADYOUT_ram9; // HREADY feedback
+ wire HRESP_ram9; // Transfer response
+ wire [1:0] HRUSER_ram9; // Read-data USER signals
+
+ // Subordinate port MI6 (outputs to slave 6)
+ wire HSEL_exp; // Slave Select
+ wire [31:0] HADDR_exp; // Address bus
+ wire [1:0] HTRANS_exp; // Transfer type
+ wire HWRITE_exp; // Transfer direction
+ wire [2:0] HSIZE_exp; // Transfer size
+ wire [2:0] HBURST_exp; // Burst type
+ wire [3:0] HPROT_exp; // Protection control
+ wire [31:0] HWDATA_exp; // Write data
+ wire HMASTLOCK_exp; // Locked Sequence
+ wire HREADYMUX_exp; // Transfer done
+ wire [1:0] HAUSER_exp; // Address USER signals
+ wire [1:0] HWUSER_exp; // Write-data USER signals
+ // Subordinate port MI5 (inputs from slave 5)
+ wire [31:0] HRDATA_exp; // Read data bus
+ wire HREADYOUT_exp; // HREADY feedback
+ wire HRESP_exp; // Transfer response
+ wire [1:0] HRUSER_exp; // Read-data USER signals
+
+
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Interconnect matrix
+// 4 AHB-lite managers, 7 AHB-lite layer interfaces
+//------------------------------------------------------------------------------
+
+// BusMatrix instance
+ soclabs_4x7_AhbMatrix_lite
+ u_soclabs_4x7_AhbMatrix_lite (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .REMAP (REMAP),
+
+ // Input port SI0 signals
+ .HADDR_adp (HADDR_adp),
+ .HTRANS_adp (HTRANS_adp),
+ .HWRITE_adp (HWRITE_adp),
+ .HSIZE_adp (HSIZE_adp),
+ .HBURST_adp (HBURST_adp),
+ .HPROT_adp (HPROT_adp),
+ .HWDATA_adp (HWDATA_adp),
+ .HMASTLOCK_adp (HMASTLOCK_adp),
+ .HREADY_adp (HREADY_adp),
+ .HAUSER_adp (HAUSER_adp),
+ .HWUSER_adp (HWUSER_adp),
+ .HRDATA_adp (HRDATA_adp),
+ .HRESP_adp (HRESP_adp),
+ .HRUSER_adp (HRUSER_adp),
+
+ // Input port SI1 signals
+ .HADDR_dma (HADDR_dma),
+ .HTRANS_dma (HTRANS_dma),
+ .HWRITE_dma (HWRITE_dma),
+ .HSIZE_dma (HSIZE_dma),
+ .HBURST_dma (HBURST_dma),
+ .HPROT_dma (HPROT_dma),
+ .HWDATA_dma (HWDATA_dma),
+ .HMASTLOCK_dma (HMASTLOCK_dma),
+ .HREADY_dma (HREADY_dma),
+ .HAUSER_dma (HAUSER_dma),
+ .HWUSER_dma (HWUSER_dma),
+ .HRDATA_dma (HRDATA_dma),
+ .HRESP_dma (HRESP_dma),
+ .HRUSER_dma (HRUSER_dma),
+
+ // Input port SI2 signals
+ .HADDR_dma2 (HADDR_dma2),
+ .HTRANS_dma2 (HTRANS_dma2),
+ .HWRITE_dma2 (HWRITE_dma2),
+ .HSIZE_dma2 (HSIZE_dma2),
+ .HBURST_dma2 (HBURST_dma2),
+ .HPROT_dma2 (HPROT_dma2),
+ .HWDATA_dma2 (HWDATA_dma2),
+ .HMASTLOCK_dma2 (HMASTLOCK_dma2),
+ .HREADY_dma2 (HREADY_dma2),
+ .HAUSER_dma2 (HAUSER_dma2),
+ .HWUSER_dma2 (HWUSER_dma2),
+ .HRDATA_dma2 (HRDATA_dma2),
+ .HRESP_dma2 (HRESP_dma2),
+ .HRUSER_dma2 (HRUSER_dma2),
+
+ // Input port SI3 signals
+ .HADDR_cpu (HADDR_cpu),
+ .HTRANS_cpu (HTRANS_cpu),
+ .HWRITE_cpu (HWRITE_cpu),
+ .HSIZE_cpu (HSIZE_cpu),
+ .HBURST_cpu (HBURST_cpu),
+ .HPROT_cpu (HPROT_cpu),
+ .HWDATA_cpu (HWDATA_cpu),
+ .HMASTLOCK_cpu (HMASTLOCK_cpu),
+ .HREADY_cpu (HREADY_cpu),
+ .HAUSER_cpu (HAUSER_cpu),
+ .HWUSER_cpu (HWUSER_cpu),
+ .HRDATA_cpu (HRDATA_cpu),
+ .HRESP_cpu (HRESP_cpu),
+ .HRUSER_cpu (HRUSER_cpu),
+
+ // Output port MI0 signals
+ .HSEL_rom1 (HSEL_rom1),
+ .HADDR_rom1 (HADDR_rom1),
+ .HTRANS_rom1 (HTRANS_rom1),
+ .HWRITE_rom1 (HWRITE_rom1),
+ .HSIZE_rom1 (HSIZE_rom1),
+ .HBURST_rom1 (HBURST_rom1),
+ .HPROT_rom1 (HPROT_rom1),
+ .HWDATA_rom1 (HWDATA_rom1),
+ .HMASTLOCK_rom1 (HMASTLOCK_rom1),
+ .HREADYMUX_rom1 (HREADYMUX_rom1),
+ .HAUSER_rom1 (HAUSER_rom1),
+ .HWUSER_rom1 (HWUSER_rom1),
+ .HRDATA_rom1 (HRDATA_rom1),
+ .HREADYOUT_rom1 (HREADYOUT_rom1),
+ .HRESP_rom1 (HRESP_rom1),
+ .HRUSER_rom1 (HRUSER_rom1),
+
+ // Output port MI1 signals
+ .HSEL_ram2 (HSEL_ram2),
+ .HADDR_ram2 (HADDR_ram2),
+ .HTRANS_ram2 (HTRANS_ram2),
+ .HWRITE_ram2 (HWRITE_ram2),
+ .HSIZE_ram2 (HSIZE_ram2),
+ .HBURST_ram2 (HBURST_ram2),
+ .HPROT_ram2 (HPROT_ram2),
+ .HWDATA_ram2 (HWDATA_ram2),
+ .HMASTLOCK_ram2 (HMASTLOCK_ram2),
+ .HREADYMUX_ram2 (HREADYMUX_ram2),
+ .HAUSER_ram2 (HAUSER_ram2),
+ .HWUSER_ram2 (HWUSER_ram2),
+ .HRDATA_ram2 (HRDATA_ram2),
+ .HREADYOUT_ram2 (HREADYOUT_ram2),
+ .HRESP_ram2 (HRESP_ram2),
+ .HRUSER_ram2 (HRUSER_ram2),
+
+ // Output port MI2 signals
+ .HSEL_ram3 (HSEL_ram3),
+ .HADDR_ram3 (HADDR_ram3),
+ .HTRANS_ram3 (HTRANS_ram3),
+ .HWRITE_ram3 (HWRITE_ram3),
+ .HSIZE_ram3 (HSIZE_ram3),
+ .HBURST_ram3 (HBURST_ram3),
+ .HPROT_ram3 (HPROT_ram3),
+ .HWDATA_ram3 (HWDATA_ram3),
+ .HMASTLOCK_ram3 (HMASTLOCK_ram3),
+ .HREADYMUX_ram3 (HREADYMUX_ram3),
+ .HAUSER_ram3 (HAUSER_ram3),
+ .HWUSER_ram3 (HWUSER_ram3),
+ .HRDATA_ram3 (HRDATA_ram3),
+ .HREADYOUT_ram3 (HREADYOUT_ram3),
+ .HRESP_ram3 (HRESP_ram3),
+ .HRUSER_ram3 (HRUSER_ram3),
+
+ // Output port MI3 signals
+ .HSEL_sys (HSEL_sys),
+ .HADDR_sys (HADDR_sys),
+ .HTRANS_sys (HTRANS_sys),
+ .HWRITE_sys (HWRITE_sys),
+ .HSIZE_sys (HSIZE_sys),
+ .HBURST_sys (HBURST_sys),
+ .HPROT_sys (HPROT_sys),
+ .HWDATA_sys (HWDATA_sys),
+ .HMASTLOCK_sys (HMASTLOCK_sys),
+ .HREADYMUX_sys (HREADYMUX_sys),
+ .HAUSER_sys (HAUSER_sys),
+ .HWUSER_sys (HWUSER_sys),
+ .HRDATA_sys (HRDATA_sys),
+ .HREADYOUT_sys (HREADYOUT_sys),
+ .HRESP_sys (HRESP_sys),
+ .HRUSER_sys (HRUSER_sys),
+
+ // Output port MI4 signals
+ .HSEL_ram8 (HSEL_ram8),
+ .HADDR_ram8 (HADDR_ram8),
+ .HTRANS_ram8 (HTRANS_ram8),
+ .HWRITE_ram8 (HWRITE_ram8),
+ .HSIZE_ram8 (HSIZE_ram8),
+ .HBURST_ram8 (HBURST_ram8),
+ .HPROT_ram8 (HPROT_ram8),
+ .HWDATA_ram8 (HWDATA_ram8),
+ .HMASTLOCK_ram8 (HMASTLOCK_ram8),
+ .HREADYMUX_ram8 (HREADYMUX_ram8),
+ .HAUSER_ram8 (HAUSER_ram8),
+ .HWUSER_ram8 (HWUSER_ram8),
+ .HRDATA_ram8 (HRDATA_ram8),
+ .HREADYOUT_ram8 (HREADYOUT_ram8),
+ .HRESP_ram8 (HRESP_ram8),
+ .HRUSER_ram8 (HRUSER_ram8),
+
+ // Output port MI5 signals
+ .HSEL_ram9 (HSEL_ram9),
+ .HADDR_ram9 (HADDR_ram9),
+ .HTRANS_ram9 (HTRANS_ram9),
+ .HWRITE_ram9 (HWRITE_ram9),
+ .HSIZE_ram9 (HSIZE_ram9),
+ .HBURST_ram9 (HBURST_ram9),
+ .HPROT_ram9 (HPROT_ram9),
+ .HWDATA_ram9 (HWDATA_ram9),
+ .HMASTLOCK_ram9 (HMASTLOCK_ram9),
+ .HREADYMUX_ram9 (HREADYMUX_ram9),
+ .HAUSER_ram9 (HAUSER_ram9),
+ .HWUSER_ram9 (HWUSER_ram9),
+ .HRDATA_ram9 (HRDATA_ram9),
+ .HREADYOUT_ram9 (HREADYOUT_ram9),
+ .HRESP_ram9 (HRESP_ram9),
+ .HRUSER_ram9 (HRUSER_ram9),
+
+ // Output port MI6 signals
+ .HSEL_exp (HSEL_exp),
+ .HADDR_exp (HADDR_exp),
+ .HTRANS_exp (HTRANS_exp),
+ .HWRITE_exp (HWRITE_exp),
+ .HSIZE_exp (HSIZE_exp),
+ .HBURST_exp (HBURST_exp),
+ .HPROT_exp (HPROT_exp),
+ .HWDATA_exp (HWDATA_exp),
+ .HMASTLOCK_exp (HMASTLOCK_exp),
+ .HREADYMUX_exp (HREADYMUX_exp),
+ .HAUSER_exp (HAUSER_exp),
+ .HWUSER_exp (HWUSER_exp),
+ .HRDATA_exp (HRDATA_exp),
+ .HREADYOUT_exp (HREADYOUT_exp),
+ .HRESP_exp (HRESP_exp),
+ .HRUSER_exp (HRUSER_exp),
+
+ // Scan test dummy signals; not connected until scan insertion
+ .SCANENABLE (SCANENABLE),
+ .SCANINHCLK (SCANINHCLK),
+ .SCANOUTHCLK (SCANOUTHCLK)
+ );
+
+
+//----------------------------------------
+// Boot ROM "rom1" firmware
+// mapped 0x10000000-0x1fffffff
+// and on REMAP[0]
+// mapped 0x00000000-0x0000ffff
+//----------------------------------------
+
+ahb_bootrom
+// #(.AW(10) ) // 1K bytes ROM
+ u_ahb_bootloader (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_rom1),
+ .HADDR (HADDR_rom1[ 9:0]),
+ .HTRANS (HTRANS_rom1),
+ .HSIZE (HSIZE_rom1),
+ .HWRITE (HWRITE_rom1),
+ .HWDATA (HWDATA_rom1),
+ .HREADY (HREADYMUX_rom1),
+ .HREADYOUT (HREADYOUT_rom1),
+ .HRDATA (HRDATA_rom1),
+ .HRESP (HRESP_rom1)
+ );
+
+//----------------------------------------
+// CODE/DATA "ram2"
+// mapped 0x20000000-0x2fffffff
+//----------------------------------------
+
+//localparam AWRAM2 = 9; // 512B
+//localparam AWRAM2 = 10; // 1024B
+localparam AWRAM2 = 14; // 16KB
+//localparam AWRAM2 = 16; // 64KB
+ wire [AWRAM2-3:0] addr_ram2;
+ wire [31:0] wdata_ram2;
+ wire [31:0] rdata_ram2;
+ wire [3:0] wen_ram2;
+ wire cs_ram2;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(.AW(AWRAM2)) u_ahb_to_sram2
+ (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_ram2), // AHB inputs
+ .HADDR (HADDR_ram2[AWRAM2-1:0]),
+ .HTRANS (HTRANS_ram2),
+ .HSIZE (HSIZE_ram2),
+ .HWRITE (HWRITE_ram2),
+ .HWDATA (HWDATA_ram2),
+ .HREADY (HREADYMUX_ram2),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_ram2), // Outputs
+ .HRDATA (HRDATA_ram2),
+ .HRESP (HRESP_ram2),
+
+ // SRAM input
+ .SRAMRDATA (rdata_ram2),
+ // SRAM Outputs
+ .SRAMADDR (addr_ram2),
+ .SRAMWDATA (wdata_ram2),
+ .SRAMWEN (wen_ram2),
+ .SRAMCS (cs_ram2)
+ );
+
+ // SRAM model
+// cmsdk_fpga_sram #(.AW(AWRAM2)) u_fpga_ram2
+ cmsdk_fpga_rom #(.AW(AWRAM2), .filename("../rtl_sim/image.hex") ) u_fpga_ram2
+ (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_ram2),
+ .WDATA (wdata_ram2),
+ .WREN (wen_ram2),
+ .CS (cs_ram2),
+ // SRAM Output
+ .RDATA (rdata_ram2)
+ );
+
+
+//----------------------------------------
+// DATA "ram3"
+// mapped 0x30000000-0x3fffffff
+//----------------------------------------
+
+//localparam AWRAM3 = 9; // 512B
+//localparam AWRAM3 = 10; // 1024B
+localparam AWRAM3 = 14; // 16KB
+//localparam AWRAM3 = 16; // 64KB
+ wire [AWRAM3-3:0] addr_ram3;
+ wire [31:0] wdata_ram3;
+ wire [31:0] rdata_ram3;
+ wire [3:0] wen_ram3;
+ wire cs_ram3;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(.AW(AWRAM3)) u_ahb_to_sram3
+ (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_ram3), // AHB inputs
+ .HADDR (HADDR_ram3[AWRAM3-1:0]),
+ .HTRANS (HTRANS_ram3),
+ .HSIZE (HSIZE_ram3),
+ .HWRITE (HWRITE_ram3),
+ .HWDATA (HWDATA_ram3),
+ .HREADY (HREADYMUX_ram3),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_ram3), // Outputs
+ .HRDATA (HRDATA_ram3),
+ .HRESP (HRESP_ram3),
+
+ // SRAM input
+ .SRAMRDATA (rdata_ram3),
+ // SRAM Outputs
+ .SRAMADDR (addr_ram3),
+ .SRAMWDATA (wdata_ram3),
+ .SRAMWEN (wen_ram3),
+ .SRAMCS (cs_ram3)
+ );
+
+ // SRAM model
+ cmsdk_fpga_sram #(.AW(AWRAM3)) u_fpga_ram3
+ (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_ram3),
+ .WDATA (wdata_ram3),
+ .WREN (wen_ram3),
+ .CS (cs_ram3),
+ // SRAM Output
+ .RDATA (rdata_ram3)
+ );
+
+//----------------------------------------
+// Expansion/DMA "ram8,ram9" RAM instances
+//----------------------------------------
+
+//localparam AWRAM8 = 9; // 512B
+//localparam AWRAM8 = 10; // 1024B
+localparam AWRAM8 = 14; // 16KB
+//localparam AWRAM8 = 16; // 64KB
+ wire [AWRAM8-3:0] addr_ram8;
+ wire [31:0] wdata_ram8;
+ wire [31:0] rdata_ram8;
+ wire [3:0] wen_ram8;
+ wire cs_ram8;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(.AW(AWRAM8)) u_ahb_to_sram8
+ (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_ram8), // AHB inputs
+ .HADDR (HADDR_ram8[AWRAM8-1:0]),
+ .HTRANS (HTRANS_ram8),
+ .HSIZE (HSIZE_ram8),
+ .HWRITE (HWRITE_ram8),
+ .HWDATA (HWDATA_ram8),
+ .HREADY (HREADYMUX_ram8),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_ram8), // Outputs
+ .HRDATA (HRDATA_ram8),
+ .HRESP (HRESP_ram8),
+
+ // SRAM input
+ .SRAMRDATA (rdata_ram8),
+ // SRAM Outputs
+ .SRAMADDR (addr_ram8),
+ .SRAMWDATA (wdata_ram8),
+ .SRAMWEN (wen_ram8),
+ .SRAMCS (cs_ram8)
+ );
+
+ // SRAM model
+ cmsdk_fpga_sram #(.AW(AWRAM8)) u_fpga_ram8
+ (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_ram8),
+ .WDATA (wdata_ram8),
+ .WREN (wen_ram8),
+ .CS (cs_ram8),
+ // SRAM Output
+ .RDATA (rdata_ram8)
+ );
+
+// instandiate expansion RAM instance to appear at 0x90000000
+//localparam AWRAM9 = 9; // 512B
+//localparam AWRAM9 = 10; // 1024B
+localparam AWRAM9 = 14; // 16KB
+//localparam AWRAM9 = 16; // 64KB
+ wire [AWRAM9-3:0] addr_ram9;
+ wire [31:0] wdata_ram9;
+ wire [31:0] rdata_ram9;
+ wire [3:0] wen_ram9;
+ wire cs_ram9;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(.AW(AWRAM9)) u_ahb_to_sram9
+ (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_ram9), // AHB inputs
+ .HADDR (HADDR_ram9[AWRAM9-1:0]),
+ .HTRANS (HTRANS_ram9),
+ .HSIZE (HSIZE_ram9),
+ .HWRITE (HWRITE_ram9),
+ .HWDATA (HWDATA_ram9),
+ .HREADY (HREADYMUX_ram9),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_ram9), // Outputs
+ .HRDATA (HRDATA_ram9),
+ .HRESP (HRESP_ram9),
+
+ // SRAM input
+ .SRAMRDATA (rdata_ram9),
+ // SRAM Outputs
+ .SRAMADDR (addr_ram9),
+ .SRAMWDATA (wdata_ram9),
+ .SRAMWEN (wen_ram9),
+ .SRAMCS (cs_ram9)
+ );
+
+ // SRAM model
+ cmsdk_fpga_sram #(.AW(AWRAM9)) u_fpga_ram9
+ (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_ram9),
+ .WDATA (wdata_ram9),
+ .WREN (wen_ram9),
+ .CS (cs_ram9),
+ // SRAM Output
+ .RDATA (rdata_ram9)
+ );
+
+// assign [31:0] HRDATA_ram8 = 32'hdead8888; // Read data bus
+// assign HREADYOUT_ram8 = 1'b1; // HREADY feedback
+// assign HRESP_ram8 = 1'b0; // Transfer response
+// assign [1:0] HRUSER_ram8 = 00; // Read-data USER signals
+//
+// assign [31:0] HRDATA_ram9 = 32'hdead9999; // Read data bus
+// assign HREADYOUT_ram9 = 1'b1; // HREADY feedback
+// assign HRESP_ram9 = 1'b0; // Transfer response
+// assign [1:0] HRUSER_ram9 = 00; // Read-data USER signals
+
+
+//----------------------------------------
+// ADP ASCII DEBUG PROTOCOL controller
+// AHB MANAGER 0
+//----------------------------------------
+
+ // -------------------------------
+ // ADP engine stream and control interfaces
+ // -------------------------------
+
+ wire comio_tx_ready;
+ wire [7:0] comio_tx_data8;
+ wire comio_tx_valid;
+
+ wire comio_rx_ready;
+ wire [7:0] comio_rx_data8;
+ wire comio_rx_valid;
+
+ wire stdio_tx_ready;
+ wire [7:0] stdio_tx_data8;
+ wire stdio_tx_valid;
+
+ wire stdio_rx_ready;
+ wire [7:0] stdio_rx_data8;
+ wire stdio_rx_valid;
+
+ wire [7:0] adp_gpo8;
+ wire [7:0] adp_gpi8;
+
+ assign adp_gpi8 = adp_gpo8;
+ assign ADPRESETREQ = adp_gpo8[0];
+
+ // DMA controller present
+ ADPcontrol_v1_0 u_ADP (
+ // Clock and Reset
+ .ahb_hclk (HCLK),
+ .ahb_hresetn (HRESETn),
+ // DMA Control
+ .com_rx_tready (comio_rx_ready),
+ .com_rx_tdata (comio_rx_data8),
+ .com_rx_tvalid (comio_rx_valid),
+ .com_tx_tready (comio_tx_ready),
+ .com_tx_tdata (comio_tx_data8),
+ .com_tx_tvalid (comio_tx_valid),
+ .stdio_rx_tready (stdio_rx_ready),
+ .stdio_rx_tdata (stdio_rx_data8),
+ .stdio_rx_tvalid (stdio_rx_valid),
+ .stdio_tx_tready (stdio_tx_ready),
+ .stdio_tx_tdata (stdio_tx_data8),
+ .stdio_tx_tvalid (stdio_tx_valid),
+ .gpo8 (adp_gpo8),
+ .gpi8 (adp_gpi8),
+ // AHB-Lite Master Interface
+ .ahb_hready (HREADY_adp),
+ .ahb_hresp (HRESP_adp),
+ .ahb_hrdata (HRDATA_adp),
+ .ahb_htrans (HTRANS_adp),
+ .ahb_hwrite (HWRITE_adp),
+ .ahb_haddr (HADDR_adp),
+ .ahb_hsize (HSIZE_adp),
+ .ahb_hburst (HBURST_adp),
+ .ahb_hmastlock (HMASTLOCK_adp),
+ .ahb_hprot (HPROT_adp),
+ .ahb_hwdata (HWDATA_adp)
+ );
+ assign HAUSER_adp [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_adp [1:0] = 2'b00; // Write-data USER signals
+
+ cmsdk_apb_usrt u_apb_usrt_com (
+ .PCLK (PCLK), // Peripheral clock
+ .PCLKG (PCLKG), // Gated PCLK for bus
+ .PRESETn (PRESETn), // Reset
+
+ .PSEL (exp14_psel), // APB interface inputs
+ .PADDR (exp_paddr[11:2]),
+ .PENABLE (exp_penable),
+ .PWRITE (exp_pwrite),
+ .PWDATA (exp_pwdata),
+
+ .PRDATA (exp14_prdata), // APB interface outputs
+ .PREADY (exp14_pready),
+ .PSLVERR (exp14_pslverr),
+
+ .ECOREVNUM (4'h0),// Engineering-change-order revision bits
+
+ .TX_VALID_o (stdio_rx_valid),
+ .TX_DATA8_o (stdio_rx_data8),
+ .TX_READY_i (stdio_rx_ready),
+
+ .RX_VALID_i (stdio_tx_valid),
+ .RX_DATA8_i (stdio_tx_data8),
+ .RX_READY_o (stdio_tx_ready),
+
+ .TXINT ( ), // Transmit Interrupt
+ .RXINT ( ), // Receive Interrupt
+ .TXOVRINT ( ), // Transmit Overrun Interrupt
+ .RXOVRINT ( ), // Receive Overrun Interrupt
+ .UARTINT ( ) // Combined Interrupt
+ );
+
+ wire [7:0] ft_clkdiv = 8'd03;
+
+ ft1248_streamio_v1_0 #
+ (.FT1248_WIDTH (1),
+ .FT1248_CLKON(0) )
+ u_ftdio_com (
+ .clk (HCLK),
+ .resetn (HRESETn),
+ .ft_clkdiv (ft_clkdiv ),
+ .ft_clk_o (ft_clk_o ),
+ .ft_ssn_o (ft_ssn_o ),
+ .ft_miso_i (ft_miso_i ),
+ .ft_miosio_o (ft_miosio_o ),
+ .ft_miosio_e (ft_miosio_e ),
+ .ft_miosio_z (ft_miosio_z ),
+ .ft_miosio_i (ft_miosio_i ),
+ .rxd_tready (comio_tx_ready),
+ .rxd_tdata (comio_tx_data8),
+ .rxd_tvalid (comio_tx_valid),
+ .rxd_tlast (1'b0),
+ .txd_tready (comio_rx_ready),
+ .txd_tdata (comio_rx_data8),
+ .txd_tvalid (comio_rx_valid),
+ .txd_tlast ( )
+ );
+
+
+//----------------------------------------
+// DIRECT MEMORY ACCESS controller
+// AHB MANAGER 1
+//----------------------------------------
+
+ // DMA interface not used in this example system
+ wire [DMA_CHANNEL_NUM-1:0] dma230_tie0; // tie off signal.
+
+ assign dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
+
+ // DMA done per channel
+ wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
+ wire dmac_done;
+ wire dmac_err;
+
+ ///generate if (INCLUDE_DMA != 0) begin : gen_dma
+ // DMA controller present
+ pl230_udma u_pl230_udma (
+ // Clock and Reset
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+ // DMA Control
+ .dma_req (dma230_tie0),
+ .dma_sreq (dma230_tie0),
+ .dma_waitonreq (dma230_tie0),
+ .dma_stall (1'b0),
+ .dma_active (),
+ .dma_done (dma230_done_ch),
+ .dma_err (dmac_err),
+ // AHB-Lite Master Interface
+ .hready (HREADY_dma),
+ .hresp (HRESP_dma),
+ .hrdata (HRDATA_dma),
+ .htrans (HTRANS_dma),
+ .hwrite (HWRITE_dma),
+ .haddr (HADDR_dma),
+ .hsize (HSIZE_dma),
+ .hburst (HBURST_dma),
+ .hmastlock (HMASTLOCK_dma),
+ .hprot (HPROT_dma),
+ .hwdata (HWDATA_dma),
+ // APB Slave Interface
+ .pclken (PCLKEN),
+ .psel (exp15_psel),
+ .pen (exp_penable),
+ .pwrite (exp_pwrite),
+ .paddr (exp_paddr[11:0]),
+ .pwdata (exp_pwdata[31:0]),
+ .prdata (exp15_prdata)
+ );
+
+ assign exp15_pready = 1'b1;
+ assign exp15_pslverr = 1'b0;
+ assign dmac_done = |dma230_done_ch; // OR all the DMA done together
+
+/* end else begin : gen_no_pl230_udma
+ // DMA controller not present
+ assign HADDR_dma [31:0] = 32'ha2a2a2a2; // Address bus
+ assign HTRANS_dma [1:0] = 2'b00; // Transfer type
+ assign HWRITE_dma = 1'b0; // Transfer direction
+ assign HSIZE_dma [2:0] = 3'b010; // Transfer size
+ assign HBURST_dma [2:0] = 3'b001; // Burst type
+ assign HPROT_dma [3:0] = 4'b0010; // Protection control
+ assign HWDATA_dma [31:0] = 32'hd2d2d2d2; // Write data
+ assign HMASTLOCK_dma = 1'b0; // Locked Sequence
+ assign HAUSER_dma [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_dma [1:0] = 2'b00; // Write-data USER signals
+
+ assign dmac_done = 1'b0;
+ assign dmac_err = 1'b0;
+ assign exp15_pready = 1'b1;
+ assign exp15_pslverr = 1'b0;
+ assign exp15_prdata = 32'h00000000;
+ assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
+
+ end endgenerate
+*/
+
+//----------------------------------------
+// DIRECT MEMORY ACCESS controller 2
+// AHB MANAGER 2
+//----------------------------------------
+
+ // Manager port SI2 (inputs from master 2)
+ assign HADDR_dma2 [31:0] = 32'ha2a2a2a2; // Address bus
+ assign HTRANS_dma2 [1:0] = 2'b00; // Transfer type
+ assign HWRITE_dma2 = 1'b0; // Transfer direction
+ assign HSIZE_dma2 [2:0] = 3'b010; // Transfer size
+ assign HBURST_dma2 [2:0] = 3'b000; // Burst type
+ assign HPROT_dma2 [3:0] = 4'b0010; // Protection control
+ assign HWDATA_dma2 [31:0] = 32'hd2d2d2d2; // Write data
+ assign HMASTLOCK_dma2 = 1'b0; // Locked Sequence
+ assign HAUSER_dma2 [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_dma2 [1:0] = 2'b00; // Write-data USER signals
+
+//----------------------------------------
+// CORTEX-M0 CPU controller
+// AHB MANAGER 3
+//----------------------------------------
+
+ wire SYS_NMI; // Watchdog nin-maskable interrupt
+ wire [31:0] SYS_APB_IRQ; // APB subsystem IRQs
+ wire [15:0] SYS_GPIO0_IRQ; // GPIO-0 IRQs
+ wire [15:0] SYS_GPIO1_IRQ; // GPIO-1 IRQs
+
+ wire gpio0_combintr;
+ wire gpio1_combintr;
+ assign gpio0_combintr = |SYS_GPIO0_IRQ[15:0];
+ assign gpio1_combintr = |SYS_GPIO1_IRQ[15:0];
+
+ wire intnmi_cm0;
+ wire [31:0] intisr_cm0;
+
+// match interrupts to CMSDK for validation code reuse
+
+ assign intnmi_cm0 = SYS_NMI;
+ assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
+ assign intisr_cm0[ 6] = SYS_APB_IRQ[ 6] | gpio0_combintr;
+ assign intisr_cm0[ 7] = SYS_APB_IRQ[ 7] | gpio1_combintr;
+ assign intisr_cm0[14: 8] = SYS_APB_IRQ[14: 8];
+ assign intisr_cm0[15] = SYS_APB_IRQ[15] | dmac_done | dmac_err;
+ assign intisr_cm0[31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
+
+ assign HAUSER_cpu [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_cpu [1:0] = 2'b00; // Write-data USER signals
+
+
+ // Cortex-M0 integration level
+ nanosoc_cpu
+ u_nanosoc_cpu (
+ .HCLK (HCLK),
+ .FCLK (FCLK),
+ .DCLK (DCLK),
+ .SCLK (SCLK),
+ .HRESETn (HRESETn),
+ .PORESETn (PORESETn),
+ .DBGRESETn (DBGRESETn),
+ .RSTBYPASS (TESTMODE),
+ .DFTSE (SCANENABLE),
+ // AHB port
+ .HADDR (HADDR_cpu),
+ .HTRANS (HTRANS_cpu),
+ .HWRITE (HWRITE_cpu),
+ .HSIZE (HSIZE_cpu),
+ .HBURST (HBURST_cpu),
+ .HPROT (HPROT_cpu),
+ .HWDATA (HWDATA_cpu),
+ .HMASTLOCK (HMASTLOCK_cpu),
+ .HREADY (HREADY_cpu),
+// .HAUSER (HAUSER_cpu),
+// .HWUSER (HWUSER_cpu),
+ .HRDATA (HRDATA_cpu),
+ .HRESP (HRESP_cpu),
+// .HRUSER (HRUSER_cpu),
+ // sideband signals
+ .NMI (intnmi_cm0), // Non-maskable interrupt input
+ .IRQ (intisr_cm0[31:0]), // Interrupt request inputs
+ .TXEV (TXEV), // Event output (SEV executed)
+ .RXEV (RXEV), // Event input
+ // MISCELLANEOUS ---------------------
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP),
+ .WAKEUP (WAKEUP ), // Wake up request from WIC
+ .WICENREQ (WICENREQ ), // WIC enable request from PMU
+ .WICENACK (WICENACK ), // WIC enable ack to PMU
+ .LOCKUP (LOCKUP), // Core is locked-up
+ .GATEHCLK (GATEHCLK),
+ .SYSRESETREQ (SYSRESETREQ), // System reset request
+ .WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
+ .ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
+
+ // Debug - JTAG or Serial wire
+ // inputs
+ .SWDI (SWDI),
+ .SWCLK (SWCLK),
+ // outputs
+ .SWDO (SWDO),
+ .SWDOEN (SWDOEN)
+ );
+
+ assign RXEV = dmac_done; // Generate event when a DMA operation completed.
+
+
+//------------------------------------
+// internal wires
+
+ assign p0_out_nen = ~p0_out_en; //active low pad drive option
+ assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
+
+
+ // Common AHB signals
+ wire [31:0] HADDR;
+ wire [1:0] HTRANS;
+ wire [2:0] HSIZE;
+ wire HWRITE;
+ wire [31:0] HWDATA;
+ wire HREADY;
+
+ localparam BASEADDR_GPIO0 = 32'h4001_0000;
+ localparam BASEADDR_GPIO1 = 32'h4001_1000;
+ localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
+
+ nanosoc_sysio
+ u_nanosoc_sysio (
+ .FCLK (FCLK ), // free-running clock
+ .PORESETn (PORESETn ), // Power-On-Reset (active-low)
+ .TESTMODE (TESTMODE ), // Test-mode override for testability
+ .HCLK (HCLK ), // AHB interconnect clock
+ .HRESETn (HRESETn ), // AHB interconnect reset (active-low)
+ // Common AHB signals
+ .HSEL (HSEL_sys ),
+ .HADDR (HADDR_sys ),
+ .HBURST (HBURST_sys ),
+ .HMASTLOCK (HMASTLOCK_sys),
+ .HPROT (HPROT_sys ),
+ .HSIZE (HSIZE_sys ),
+ .HTRANS (HTRANS_sys ),
+ .HWDATA (HWDATA_sys ),
+ .HWRITE (HWRITE_sys ),
+ .HREADY (HREADYMUX_sys),
+ .HRDATA (HRDATA_sys ),
+ .HRESP (HRESP_sys ),
+ .HREADYOUT (HREADYOUT_sys),
+ // APB clocking
+ .PCLK (PCLK ),
+ .PCLKG (PCLKG ),
+ .PRESETn (PRESETn ),
+ .PCLKEN (PCLKEN ),
+ // APB expansion select outputs
+ .exp12_psel (exp12_psel ),
+ .exp13_psel (exp13_psel ),
+ .exp14_psel (exp14_psel ),
+ .exp15_psel (exp15_psel ),
+ .exp_pwdata (exp_pwdata ),
+ .exp_paddr (exp_paddr ),
+ .exp_pwrite (exp_pwrite ),
+ .exp_penable (exp_penable ),
+ // APB expansion interface inputs
+ .exp12_prdata (exp12_prdata ),
+ .exp12_pready (exp12_pready ),
+ .exp12_pslverr (exp12_pslverr),
+ .exp13_prdata (exp13_prdata ),
+ .exp13_pready (exp13_pready ),
+ .exp13_pslverr (exp13_pslverr),
+ .exp14_prdata (exp14_prdata ),
+ .exp14_pready (exp14_pready ),
+ .exp14_pslverr (exp14_pslverr),
+ .exp15_prdata (exp15_prdata ),
+ .exp15_pready (exp15_pready ),
+ .exp15_pslverr (exp15_pslverr),
+ // CPU sideband signalling
+ .SYS_NMI (SYS_NMI ),
+ .SYS_APB_IRQ (SYS_APB_IRQ ),
+ // CPU specific power/reset control
+ .REMAP_CTRL (ROM_MAP ),
+ .APBACTIVE (APBACTIVE ),
+ .SYSRESETREQ (SYSRESETREQ ),
+ .WDOGRESETREQ (WDOGRESETREQ ),
+ .LOCKUP (LOCKUP ),
+ .LOCKUPRESET (LOCKUPRESET ),
+ .PMUENABLE (PMUENABLE ),
+ // chip IO
+ .SYS_GPIO0_IRQ (SYS_GPIO0_IRQ ),
+ .SYS_GPIO1_IRQ (SYS_GPIO1_IRQ ),
+ // IO signalling
+ .uart0_rxd (uart0_rxd ),
+ .uart0_txd (uart0_txd ),
+ .uart0_txen (uart0_txen ),
+ .uart1_rxd (uart1_rxd ),
+ .uart1_txd (uart1_txd ),
+ .uart1_txen (uart1_txen ),
+ .uart2_rxd (uart2_rxd ),
+ .uart2_txd (uart2_txd ),
+ .uart2_txen (uart2_txen ),
+ .timer0_extin (timer0_extin ),
+ .timer1_extin (timer1_extin ),
+ // GPIO port signalling
+ .p0_in (p0_in ),
+ .p0_out (p0_out ),
+ .p0_outen (p0_out_en ),
+ .p0_altfunc (p0_altfunc ),
+
+ .p1_in (p1_in ),
+ .p1_out (p1_out ),
+ .p1_outen (p1_out_en ),
+ .p1_altfunc (p1_altfunc )
+ );
+
+ assign REMAP[3] = 1'b0;
+ assign REMAP[2] = 1'b0;
+ assign REMAP[1] = 1'b0;
+ assign REMAP[0] =!ROM_MAP;
+
+ assign exp12_pready = 1'b1;
+ assign exp13_pready = 1'b1;
+
+ // Internal Debug signals
+ wire i_trst_n;
+ wire i_swditms;
+ wire i_swclktck;
+ wire i_tdi;
+ wire i_tdo;
+ wire i_tdoen_n;
+ wire i_swdo;
+ wire i_swdoen;
+
+ // Serial wire debug is used. nTRST, TDI and TDO are not needed
+
+
+//----------------------------------------
+// I/O port pin muxing and tristate
+//----------------------------------------
+
+
+ assign i_swclktck = swdclk_in;
+ assign i_swditms = swdio_in;
+ assign swdio_out = i_swdo;
+ assign swdio_out_en = i_swdoen;
+ assign swdio_out_nen = !i_swdoen;
+
+ assign swdclk_in = swdclk_i;
+ assign swdio_in = swdio_i;
+
+ assign swdio_o = swdio_out;
+ assign swdio_e = swdio_out_en;
+ assign swdio_z = swdio_out_nen;
+
+ cmsdk_mcu_pin_mux
+ u_pin_mux (
+ // UART
+ .uart0_rxd (uart0_rxd),
+ .uart0_txd (uart0_txd),
+ .uart0_txen (uart0_txen),
+ .uart1_rxd (uart1_rxd),
+ .uart1_txd (uart1_txd),
+ .uart1_txen (uart1_txen),
+ .uart2_rxd (uart2_rxd),
+ .uart2_txd (uart2_txd),
+ .uart2_txen (uart2_txen),
+
+ // Timer
+ .timer0_extin (timer0_extin),
+ .timer1_extin (timer1_extin),
+
+
+ // IO Ports
+ .p0_in ( ), // was (p0_in) now from pad inputs),
+ .p0_out (p0_out),
+ .p0_outen (p0_out_en),
+ .p0_altfunc (p0_altfunc),
+
+ .p1_in ( ), // was(p1_in) now from pad inputs),
+ .p1_out (p1_out),
+ .p1_outen (p1_out_en),
+ .p1_altfunc (p1_altfunc),
+
+ // Debug
+ .i_trst_n (i_trst_n),
+ .i_swditms ( ), //i_swditms),
+ .i_swclktck ( ), //i_swclktck),
+ .i_tdi (i_tdi),
+ .i_tdo (i_tdo),
+ .i_tdoen_n (i_tdoen_n),
+ .i_swdo (i_swdo),
+ .i_swdoen (i_swdoen),
+
+ // IO pads
+ .p1_out_mux (p1_out_mux),
+ .p1_out_en_mux (p1_out_en_mux),
+ .P0 ( ), //P0),
+ .P1 ( ), //P1),
+
+ .nTRST (nTRST), // Not needed if serial-wire debug is used
+ .TDI (1'b0), // Not needed if serial-wire debug is used
+ .SWDIOTMS ( ), //SWDIOTMS),
+ .SWCLKTCK ( ), //SWCLKTCK),
+ .TDO ( ) // Not needed if serial-wire debug is used
+
+ );
+
+endmodule
+
+
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip_pads.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip_pads.v
new file mode 100644
index 0000000000000000000000000000000000000000..e994acb80d19c0dd2e7754bb0d080b262cb5fc3d
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip_pads.v
@@ -0,0 +1,406 @@
+//-----------------------------------------------------------------------------
+// customised top-level Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+
+module nanosoc_chip_pads (
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+ inout wire XTAL1, // input
+ inout wire XTAL2, // output
+ inout wire NRST, // active low reset
+ inout wire [15:0] P0,
+ inout wire [15:0] P1,
+ inout wire SWDIOTMS,
+ inout wire SWCLKTCK);
+
+
+//------------------------------------
+// internal wires
+
+ wire xtal_clk_i;
+ wire xtal_clk_o;
+ wire nrst_i;
+ wire [15:0] p0_i; // level-shifted input from pad
+ wire [15:0] p0_o; // output port drive
+ wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_i; // level-shifted input from pad
+ wire [15:0] p1_o; // output port drive
+ wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
+
+ wire swdio_i;
+ wire swdio_o;
+ wire swdio_e;
+ wire swdio_z;
+ wire swdclk_i;
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0 nanosoc Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip
+ u_nanosoc_chip (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+`endif
+ .xtal_clk_i(xtal_clk_i),
+ .xtal_clk_o(xtal_clk_o),
+ .nrst_i(nrst_i),
+ .p0_i(p0_i), // level-shifted input from pad
+ .p0_o(p0_o), // output port drive
+ .p0_e(p0_e), // active high output drive enable (pad tech dependent)
+ .p0_z(p0_z), // active low output drive enable (pad tech dependent)
+ .p1_i(p1_i), // level-shifted input from pad
+ .p1_o(p1_o), // output port drive
+ .p1_e(p1_e), // active high output drive enable (pad tech dependent)
+ .p1_z(p1_z), // active low output drive enable (pad tech dependent)
+ .swdio_i(swdio_i),
+ .swdio_o(swdio_o),
+ .swdio_e(swdio_e),
+ .swdio_z(swdio_z),
+ .swdclk_i(swdclk_i)
+ );
+
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+ // --------------------------------------------------------------------------------
+ // IO pad (GLIB Generic Library napping)
+ // --------------------------------------------------------------------------------
+
+`ifdef POWER_PINS
+// Pad IO power supplies
+
+PAD_VDDIO uPAD_VDDIO_1(
+ .PAD(VDDIO)
+ );
+
+PAD_VSSIO uPAD_VSSIO_1(
+ .PAD(VSSIO)
+ );
+
+// Core power supplies
+
+PAD_VDDSOC uPAD_VDD_1(
+ .PAD(VDD)
+ );
+
+PAD_VSS uPAD_VSS_1(
+ .PAD(VSS)
+ );
+`endif
+
+// Clock, Reset and Serial Wire Debug ports
+
+PAD_INOUT8MA_NOE uPAD_XTAL_I (
+ .PAD (XTAL1),
+ .O (tielo),
+ .I (xtal_clk_i),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_XTAL_O (
+ .PAD (XTAL2),
+ .O (xtal_clk_o),
+ .I ( ),
+ .NOE (tielo)
+ );
+
+PAD_INOUT8MA_NOE uPAD_NRST_I (
+ .PAD (NRST),
+ .O (tielo),
+ .I (nrst_i),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_SWDIO_I (
+ .PAD (SWDIOTMS),
+ .O (swdio_o),
+ .I (swdio_i),
+ .NOE (swdio_z)
+ );
+
+PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
+ .PAD (SWCLKTCK),
+ .O (tielo),
+ .I (swdclk_i),
+ .NOE (tiehi)
+ );
+
+// GPI.I Port 0 x 16
+
+PAD_INOUT8MA_NOE uPAD_P0_00 (
+ .PAD (P0[00]),
+ .O (p0_o[00]),
+ .I (p0_i[00]),
+ .NOE (p0_z[00])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_01 (
+ .PAD (P0[01]),
+ .O (p0_o[01]),
+ .I (p0_i[01]),
+ .NOE (p0_z[01])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_02 (
+ .PAD (P0[02]),
+ .O (p0_o[02]),
+ .I (p0_i[02]),
+ .NOE (p0_z[02])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_03 (
+ .PAD (P0[03]),
+ .O (p0_o[03]),
+ .I (p0_i[03]),
+ .NOE (p0_z[03])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_04 (
+ .PAD (P0[04]),
+ .O (p0_o[04]),
+ .I (p0_i[04]),
+ .NOE (p0_z[04])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_05 (
+ .PAD (P0[05]),
+ .O (p0_o[05]),
+ .I (p0_i[05]),
+ .NOE (p0_z[05])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_06 (
+ .PAD (P0[06]),
+ .O (p0_o[06]),
+ .I (p0_i[06]),
+ .NOE (p0_z[06])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_07 (
+ .PAD (P0[07]),
+ .O (p0_o[07]),
+ .I (p0_i[07]),
+ .NOE (p0_z[07])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_08 (
+ .PAD (P0[08]),
+ .O (p0_o[08]),
+ .I (p0_i[08]),
+ .NOE (p0_z[08])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_09 (
+ .PAD (P0[09]),
+ .O (p0_o[09]),
+ .I (p0_i[09]),
+ .NOE (p0_z[09])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_10 (
+ .PAD (P0[10]),
+ .O (p0_o[10]),
+ .I (p0_i[10]),
+ .NOE (p0_z[10])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_11 (
+ .PAD (P0[11]),
+ .O (p0_o[11]),
+ .I (p0_i[11]),
+ .NOE (p0_z[11])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_12 (
+ .PAD (P0[12]),
+ .O (p0_o[12]),
+ .I (p0_i[12]),
+ .NOE (p0_z[12])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_13 (
+ .PAD (P0[13]),
+ .O (p0_o[13]),
+ .I (p0_i[13]),
+ .NOE (p0_z[13])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_14 (
+ .PAD (P0[14]),
+ .O (p0_o[14]),
+ .I (p0_i[14]),
+ .NOE (p0_z[14])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_15 (
+ .PAD (P0[15]),
+ .O (p0_o[15]),
+ .I (p0_i[15]),
+ .NOE (p0_z[15])
+ );
+
+// GPI.I Port 1 x 16
+
+PAD_INOUT8MA_NOE uPAD_P1_00 (
+ .PAD (P1[00]),
+ .O (p1_o[00]),
+ .I (p1_i[00]),
+ .NOE (p1_z[00])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_01 (
+ .PAD (P1[01]),
+ .O (p1_o[01]),
+ .I (p1_i[01]),
+ .NOE (p1_z[01])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_02 (
+ .PAD (P1[02]),
+ .O (p1_o[02]),
+ .I (p1_i[02]),
+ .NOE (p1_z[02])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_03 (
+ .PAD (P1[03]),
+ .O (p1_o[03]),
+ .I (p1_i[03]),
+ .NOE (p1_z[03])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_04 (
+ .PAD (P1[04]),
+ .O (p1_o[04]),
+ .I (p1_i[04]),
+ .NOE (p1_z[04])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_05 (
+ .PAD (P1[05]),
+ .O (p1_o[05]),
+ .I (p1_i[05]),
+ .NOE (p1_z[05])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_06 (
+ .PAD (P1[06]),
+ .O (p1_o[06]),
+ .I (p1_i[06]),
+ .NOE (p1_z[06])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_07 (
+ .PAD (P1[07]),
+ .O (p1_o[07]),
+ .I (p1_i[07]),
+ .NOE (p1_z[07])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_08 (
+ .PAD (P1[08]),
+ .O (p1_o[08]),
+ .I (p1_i[08]),
+ .NOE (p1_z[08])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_09 (
+ .PAD (P1[09]),
+ .O (p1_o[09]),
+ .I (p1_i[09]),
+ .NOE (p1_z[09])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_10 (
+ .PAD (P1[10]),
+ .O (p1_o[10]),
+ .I (p1_i[10]),
+ .NOE (p1_z[10])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_11 (
+ .PAD (P1[11]),
+ .O (p1_o[11]),
+ .I (p1_i[11]),
+ .NOE (p1_z[11])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_12 (
+ .PAD (P1[12]),
+ .O (p1_o[12]),
+ .I (p1_i[12]),
+ .NOE (p1_z[12])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_13 (
+ .PAD (P1[13]),
+ .O (p1_o[13]),
+ .I (p1_i[13]),
+ .NOE (p1_z[13])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_14 (
+ .PAD (P1[14]),
+ .O (p1_o[14]),
+ .I (p1_i[14]),
+ .NOE (p1_z[14])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_15 (
+ .PAD (P1[15]),
+ .O (p1_o[15]),
+ .I (p1_i[15]),
+ .NOE (p1_z[15])
+ );
+
+endmodule
+
+
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
new file mode 100644
index 0000000000000000000000000000000000000000..c6185eaf5a763140dec6299ebc1989081e71e82e
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
@@ -0,0 +1,250 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : System level design for the example Cortex-M0 system
+//-----------------------------------------------------------------------------
+
+module nanosoc_cpu #(
+ parameter CLKGATE_PRESENT = 0,
+ parameter BE = 0, // 1: Big endian 0: little endian
+ parameter BKPT = 4, // Number of breakpoint comparators
+ parameter DBG = 1, // Debug configuration
+ parameter NUMIRQ = 32, // NUM of IRQ
+ parameter SMUL = 0, // Multiplier configuration
+ parameter SYST = 1, // SysTick
+ parameter WIC = 1, // Wake-up interrupt controller support
+ parameter WICLINES = 34, // Supported WIC lines
+ parameter WPT = 2, // Number of DWT comparators
+ parameter RESET_ALL_REGS = 0, // Do not reset all registers
+ parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
+ )
+ (
+ input wire HCLK, // (HCLK master)
+ input wire FCLK, // Free running clock
+ input wire SCLK, // System clock
+ input wire HRESETn, // AHB and System reset
+ input wire PORESETn, // Power on reset
+ input wire DCLK, // Debug clock
+ input wire DBGRESETn, // Debug reset
+ input wire RSTBYPASS, // Reset by pass (for testing)
+ input wire DFTSE, // Reset by pass (for testing)
+
+ // AHB Lite port
+ output wire [31:0] HADDR, // Address bus
+ output wire [1:0] HTRANS, // Transfer type
+ output wire HWRITE, // Transfer direction
+ output wire [2:0] HSIZE, // Transfer size
+ output wire [2:0] HBURST, // Burst type
+ output wire [3:0] HPROT, // Protection control
+ output wire [31:0] HWDATA, // Write data
+ output wire HMASTLOCK, // Locked Sequence
+// output wire [1:0] HAUSER, // Address USER signals
+// output wire [1:0] HWUSER, // Write-data USER signals
+ input wire [31:0] HRDATA, // Read data bus
+ input wire HREADY, // HREADY feedback
+ input wire HRESP, // Transfer response
+// input wire [1:0] HRUSER, // Read-data USER signals
+
+ // Sideband CPU signalling
+ input wire NMI, // Non-Maskable Interrupt request
+ input wire [31:0] IRQ, // Maskable Interrupt requests
+ output wire TXEV, // Send Event (SEV) output
+ input wire RXEV, // Receive Event input
+ output wire SLEEPING, // Processor status - sleeping
+ output wire SLEEPDEEP, // Processor status - deep sleep
+ output wire GATEHCLK, // Wake up request from WIC
+ output wire LOCKUP, // Wake up request from WIC
+ output wire WAKEUP, // Wake up request from WIC
+ input wire WICENREQ, // WIC enable request from PMU
+ output wire WICENACK, // WIC enable ack to PMU
+ input wire SYSRESETREQ, // System reset request
+ input wire WDOGRESETREQ, // Watchdog reset request
+ input wire ADPRESETREQ, // ADP Debug reset request
+
+ // Serial-Wire Debug
+ input wire SWDI, // SWD data input
+ input wire SWCLK, // SWD clock
+ output wire SWDO, // SWD data output
+ output wire SWDOEN); // SWD data output enable
+
+
+ // -------------------------------
+ // Internal signals
+ // -------------------------------
+
+ // clock, reset, and power control
+
+ wire [33:0] WICSENSE;
+
+ wire APBACTIVE; // APB bus active (for clock gating of PCLKG)
+ wire LOCKUPRESET; // System Controller cfg - reset if lockup
+ wire PMUENABLE; // System Controller cfg - Enable PMU
+
+ wire CDBGPWRUPREQ; // Debug Power Up request to PMU
+ wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
+ wire SLEEPHOLDREQn; // Sleep extension request from PMU
+ wire SLEEPHOLDACKn; // Sleep extension request to PMU
+
+
+ // SysTick timer signals
+ wire STCLKEN;
+ wire [25:0] STCALIB;
+
+ // Processor debug signals
+ wire DBGRESTART;
+ wire DBGRESTARTED;
+ wire EDBGRQ;
+
+ // Processor status
+ wire HALTED;
+ wire [2:0] CODEHINTDE;
+ wire SPECHTRANS;
+ wire CODENSEQ;
+ wire SHAREABLE;
+
+ // Cortex-M0 integration level
+ CORTEXM0INTEGRATION
+ #(.ACG (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RAR (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT)) // Number of DWT comparators
+
+ u_cortex_m0_integration (
+ // System inputs
+ .FCLK (FCLK), // FCLK
+ .SCLK (SCLK), // SCLK generated from PMU
+ .HCLK (HCLK), // HCLK generated from PMU
+ .DCLK (DCLK), // DCLK generated from PMU
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .RSTBYPASS (RSTBYPASS),
+ .SE (DFTSE),
+
+ // Power management inputs
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+
+ // Power management outputs
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .WICENACK (WICENACK),
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .WAKEUP (WAKEUP),
+ .WICSENSE (WICSENSE),
+ .GATEHCLK (GATEHCLK),
+ .SYSRESETREQ (SYSRESETREQ),
+
+ // System bus
+ .HADDR (HADDR ),
+ .HTRANS (HTRANS ),
+ .HSIZE (HSIZE ),
+ .HBURST (HBURST ),
+ .HPROT (HPROT ),
+ .HMASTLOCK (HMASTLOCK ),
+ .HWRITE (HWRITE ),
+ .HWDATA (HWDATA ),
+ .HRDATA (HRDATA ),
+ .HREADY (HREADY ),
+ .HRESP (HRESP ),
+ .HMASTER ( ),
+
+ .CODEHINTDE (CODEHINTDE),
+ .SPECHTRANS (SPECHTRANS),
+ .CODENSEQ (CODENSEQ),
+
+ // Interrupts
+ .IRQ (IRQ[31:0]),
+ .NMI (NMI),
+ .IRQLATENCY (8'h00),
+
+ .ECOREVNUM (28'h0),
+ // Systick
+ .STCLKEN (STCLKEN),
+ .STCALIB (STCALIB),
+
+ // Debug - JTAG or Serial wire
+ // inputs
+ .nTRST (1'b1),
+ .SWDITMS (SWDI),
+ .SWCLKTCK (SWCLK),
+ .TDI (1'b0),
+ // outputs
+ .TDO ( ),
+ .nTDOEN ( ),
+ .SWDO (SWDO),
+ .SWDOEN (SWDOEN),
+
+ .DBGRESTART (DBGRESTART),
+ .DBGRESTARTED (DBGRESTARTED),
+
+ // Event communication
+ .TXEV (TXEV),
+ .RXEV (RXEV),
+ .EDBGRQ (EDBGRQ),
+ // Status output
+ .HALTED (HALTED),
+ .LOCKUP (LOCKUP),
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP)
+ );
+
+ // Unused debug feature
+ assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
+ assign EDBGRQ = 1'b0; // multi-core synchronous halt request
+
+ // -------------------------------
+ // SysTick signals
+ // -------------------------------
+ cmsdk_mcu_stclkctrl
+ #(.DIV_RATIO (18'd01000))
+ u_cmsdk_mcu_stclkctrl (
+ .FCLK (FCLK),
+ .SYSRESETn (HRESETn),
+
+ .STCLKEN (STCLKEN),
+ .STCALIB (STCALIB)
+ );
+
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sys_ahb_decode.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sys_ahb_decode.v
new file mode 100644
index 0000000000000000000000000000000000000000..9bea4ac9e1b96428e54c1ccd27f57ce4c88d4309
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sys_ahb_decode.v
@@ -0,0 +1,100 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2012-07-31 11:15:58 +0100 (Tue, 31 Jul 2012) $
+//
+// Revision : $Revision: 217031 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : This module performs the address decode of the HADDR from the
+// CPU and generates the HSELs' for each of the target peripherals.
+// Also performs address decode for MTB
+//-----------------------------------------------------------------------------
+//
+
+module nanosoc_sys_ahb_decode #(
+ // GPIO0 peripheral base address
+ parameter BASEADDR_GPIO0 = 32'h4001_0000,
+ // GPIO1 peripheral base address
+ parameter BASEADDR_GPIO1 = 32'h4001_1000,
+ // GPIO1 peripheral base address
+ parameter BASEADDR_SYSCTRL = 32'h4001_f000,
+
+ // Location of the System ROM Table.
+ parameter BASEADDR_SYSROMTABLE = 32'hf000_0000
+ )
+ (
+ // System Address
+ input wire hsel,
+ input wire [31:0] haddr,
+
+ // Peripheral Selection
+ output wire apbsys_hsel,
+ output wire gpio0_hsel,
+ output wire gpio1_hsel,
+ output wire sysctrl_hsel,
+ output wire sysrom_hsel,
+
+ // Default slave
+ output wire defslv_hsel
+ );
+
+
+
+ // AHB address decode
+ // 0x40000000 - 0x4000FFFF : APB subsystem
+ // 0x40010000 - 0x40010FFF : AHB peripherals (GPIO0)
+ // 0x40011000 - 0x40011FFF : AHB peripherals (GPIO1)
+ // 0x4001F000 - 0x4001FFFF : AHB peripherals (SYS control)
+ // 0xF0000000 - 0xF0000FFF : System ROM Table
+
+ // ----------------------------------------------------------
+ // Peripheral Selection decode logic
+ // ----------------------------------------------------------
+
+ assign apbsys_hsel = hsel & (haddr[31:16]==16'h4000); // 0x40000000
+ assign gpio0_hsel = hsel & (haddr[31:12]==
+ BASEADDR_GPIO0[31:12]); // 0x40010000
+ assign gpio1_hsel = hsel & (haddr[31:12]==
+ BASEADDR_GPIO1[31:12]); // 0x40011000
+ assign sysctrl_hsel = hsel & (haddr[31:12]==
+ BASEADDR_SYSCTRL[31:12]); // 0x4001F000
+ assign sysrom_hsel = hsel & (haddr[31:12]==
+ BASEADDR_SYSROMTABLE[31:12]); // 0xF0000000
+
+ // ----------------------------------------------------------
+ // Default slave decode logic
+ // ----------------------------------------------------------
+
+ assign defslv_hsel = ~(apbsys_hsel |
+ gpio0_hsel | gpio1_hsel |
+ sysctrl_hsel | sysrom_hsel
+ );
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
new file mode 100644
index 0000000000000000000000000000000000000000..456a2b6c41c27fc370fd557485a6b8d841ce6677
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
@@ -0,0 +1,493 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : System level design for the example Cortex-M0 system
+//-----------------------------------------------------------------------------
+
+module nanosoc_sysio
+(
+ input wire FCLK, // Free-running system clock
+ input wire PORESETn, // Power-On-Reset reset (active-low)
+ input wire TESTMODE, // Reset bypass in scan test
+// AHB interface
+ input wire HCLK, // AHB clock
+ input wire HRESETn, // AHB reset (active-low)
+ input wire HSEL, // AHB region select
+ input wire [31:0] HADDR, // AHB address
+ input wire [ 2:0] HBURST, // AHB burst
+ input wire HMASTLOCK, // AHB lock
+ input wire [ 3:0] HPROT, // AHB prot
+ input wire [ 2:0] HSIZE, // AHB size
+ input wire [ 1:0] HTRANS, // AHB transfer
+ input wire [31:0] HWDATA, // AHB write data
+ input wire HWRITE, // AHB write
+ input wire HREADY, // AHB ready
+ output wire [31:0] HRDATA, // AHB read-data
+ output wire HRESP, // AHB response
+ output wire HREADYOUT, // AHB ready out
+ // APB clocking control
+ input wire PCLK, // Peripheral clock
+ input wire PCLKG, // Gated Peripheral bus clock
+ input wire PRESETn, // Peripheral system and APB reset
+ input wire PCLKEN, // Clock divide control for AHB to APB bridge
+ // APB external Slave Interface
+ output wire exp12_psel,
+ output wire exp13_psel,
+ output wire exp14_psel,
+ output wire exp15_psel,
+ output wire exp_penable,
+ output wire exp_pwrite,
+ output wire [11:0] exp_paddr,
+ output wire [31:0] exp_pwdata,
+ input wire [31:0] exp12_prdata,
+ input wire exp12_pready,
+ input wire exp12_pslverr,
+ input wire [31:0] exp13_prdata,
+ input wire exp13_pready,
+ input wire exp13_pslverr,
+ input wire [31:0] exp14_prdata,
+ input wire exp14_pready,
+ input wire exp14_pslverr,
+ input wire [31:0] exp15_prdata,
+ input wire exp15_pready,
+ input wire exp15_pslverr,
+
+ // CPU sideband signalling
+ output wire SYS_NMI, // watchdog_interrupt;
+ output wire [31:0] SYS_APB_IRQ, // apbsubsys_interrupt;
+ output wire [15:0] SYS_GPIO0_IRQ, // GPIO 0 irqs
+ output wire [15:0] SYS_GPIO1_IRQ, // GPIO 0 irqs
+
+ // CPU power/reset control
+ output wire REMAP_CTRL, // REMAP control bit
+ output wire APBACTIVE, // APB bus active (for clock gating of PCLKG)
+ output wire SYSRESETREQ, // Processor control - system reset request
+ output wire WDOGRESETREQ, // Watchdog reset request
+ input wire LOCKUP, // Processor status - Locked up
+ output wire LOCKUPRESET, // System Controller cfg - reset if lockup
+ output wire PMUENABLE, // System Controller cfg - Enable PMU
+
+ // IO signalling
+ input wire uart0_rxd, // Uart 0 receive data
+ output wire uart0_txd, // Uart 0 transmit data
+ output wire uart0_txen, // Uart 0 transmit data enable
+ input wire uart1_rxd, // Uart 1 receive data
+ output wire uart1_txd, // Uart 1 transmit data
+ output wire uart1_txen, // Uart 1 transmit data enable
+ input wire uart2_rxd, // Uart 2 receive data
+ output wire uart2_txd, // Uart 2 transmit data
+ output wire uart2_txen, // Uart 2 transmit data enable
+ input wire timer0_extin, // Timer 0 external input
+ input wire timer1_extin, // Timer 1 external input
+
+ // GPIO
+ input wire [15:0] p0_in, // GPIO 0 inputs
+ output wire [15:0] p0_out, // GPIO 0 outputs
+ output wire [15:0] p0_outen, // GPIO 0 output enables
+ output wire [15:0] p0_altfunc, // GPIO 0 alternate function (pin mux)
+ input wire [15:0] p1_in, // GPIO 1 inputs
+ output wire [15:0] p1_out, // GPIO 1 outputs
+ output wire [15:0] p1_outen, // GPIO 1 output enables
+ output wire [15:0] p1_altfunc // GPIO 1 alternate function (pin mux)
+);
+
+
+ localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
+ localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
+ localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
+ localparam BE = 0;
+
+ // ------------------------------------------------------------
+ // Local wires
+ // ------------------------------------------------------------
+
+ wire defslv_hsel; // AHB default slave signals
+ wire defslv_hreadyout;
+ wire [31:0] defslv_hrdata;
+ wire defslv_hresp;
+
+ wire apbsys_hsel; // APB subsystem AHB interface signals
+ wire apbsys_hreadyout;
+ wire [31:0] apbsys_hrdata;
+ wire apbsys_hresp;
+
+ wire gpio0_hsel; // AHB GPIO bus interface signals
+ wire gpio0_hreadyout;
+ wire [31:0] gpio0_hrdata;
+ wire gpio0_hresp;
+
+ wire gpio1_hsel; // AHB GPIO bus interface signals
+ wire gpio1_hreadyout;
+ wire [31:0] gpio1_hrdata;
+ wire gpio1_hresp;
+
+ wire sysctrl_hsel; // System control bus interface signals
+ wire sysctrl_hreadyout;
+ wire [31:0] sysctrl_hrdata;
+ wire sysctrl_hresp;
+
+ // System ROM Table
+ wire sysrom_hsel; // AHB to System ROM Table - select
+ wire sysrom_hreadyout;
+ wire [31:0] sysrom_hrdata;
+ wire sysrom_hresp;
+
+
+ // AHB address decode
+ nanosoc_sys_ahb_decode #(
+ .BASEADDR_GPIO0 (BASEADDR_GPIO0),
+ .BASEADDR_GPIO1 (BASEADDR_GPIO1),
+ .BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
+ )
+ u_addr_decode (
+ // System Address
+ .hsel (HSEL),
+ .haddr (HADDR),
+ .apbsys_hsel (apbsys_hsel),
+ .gpio0_hsel (gpio0_hsel),
+ .gpio1_hsel (gpio1_hsel),
+ .sysctrl_hsel (sysctrl_hsel),
+ .sysrom_hsel (sysrom_hsel),
+ .defslv_hsel (defslv_hsel)
+ );
+
+ // AHB slave multiplexer
+ cmsdk_ahb_slave_mux #(
+ .PORT0_ENABLE (1), // APB subsystem bridge
+ .PORT1_ENABLE (1), // GPIO Port 0
+ .PORT2_ENABLE (1), // GPIO Port 1
+ .PORT3_ENABLE (1), // SYS control
+ .PORT4_ENABLE (1), // SYS ROM table
+ .PORT5_ENABLE (1), // default
+ .PORT6_ENABLE (0),
+ .PORT7_ENABLE (0),
+ .PORT8_ENABLE (0),
+ .PORT9_ENABLE (0),
+ .DW (32)
+ )
+ u_ahb_slave_mux_sys_bus (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HREADY (HREADY),
+ .HSEL0 (apbsys_hsel), // Input Port 0
+ .HREADYOUT0 (apbsys_hreadyout),
+ .HRESP0 (apbsys_hresp),
+ .HRDATA0 (apbsys_hrdata),
+ .HSEL1 (gpio0_hsel), // Input Port 1
+ .HREADYOUT1 (gpio0_hreadyout),
+ .HRESP1 (gpio0_hresp),
+ .HRDATA1 (gpio0_hrdata),
+ .HSEL2 (gpio1_hsel), // Input Port 2
+ .HREADYOUT2 (gpio1_hreadyout),
+ .HRESP2 (gpio1_hresp),
+ .HRDATA2 (gpio1_hrdata),
+ .HSEL3 (sysctrl_hsel), // Input Port 3
+ .HREADYOUT3 (sysctrl_hreadyout),
+ .HRESP3 (sysctrl_hresp),
+ .HRDATA3 (sysctrl_hrdata),
+ .HSEL4 (sysrom_hsel), // Input Port 4
+ .HREADYOUT4 (sysrom_hreadyout),
+ .HRESP4 (sysrom_hresp),
+ .HRDATA4 (sysrom_hrdata),
+ .HSEL5 (defslv_hsel), // Input Port 5
+ .HREADYOUT5 (defslv_hreadyout),
+ .HRESP5 (defslv_hresp),
+ .HRDATA5 (defslv_hrdata),
+ .HSEL6 (1'b0), // Input Port 6
+ .HREADYOUT6 (defslv_hreadyout),
+ .HRESP6 (defslv_hresp),
+ .HRDATA6 (defslv_hrdata),
+ .HSEL7 (1'b0), // Input Port 7
+ .HREADYOUT7 (defslv_hreadyout),
+ .HRESP7 (defslv_hresp),
+ .HRDATA7 (defslv_hrdata),
+ .HSEL8 (1'b0), // Input Port 8
+ .HREADYOUT8 (defslv_hreadyout),
+ .HRESP8 (defslv_hresp),
+ .HRDATA8 (defslv_hrdata),
+ .HSEL9 (1'b0), // Input Port 9
+ .HREADYOUT9 (defslv_hreadyout),
+ .HRESP9 (defslv_hresp),
+ .HRDATA9 (defslv_hrdata),
+
+ .HREADYOUT (HREADYOUT), // Outputs
+ .HRESP (HRESP),
+ .HRDATA (HRDATA)
+ );
+
+ // Default slave
+ cmsdk_ahb_default_slave u_ahb_default_slave_1 (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (defslv_hsel),
+ .HTRANS (HTRANS),
+ .HREADY (HREADY),
+ .HREADYOUT (defslv_hreadyout),
+ .HRESP (defslv_hresp)
+ );
+
+ assign defslv_hrdata = 32'h00000000; // Default slave do not have read data
+
+ // -------------------------------
+ // System ROM Table
+ // -------------------------------
+ cmsdk_ahb_cs_rom_table
+ #(//.JEPID (),
+ //.JEPCONTINUATION (),
+ //.PARTNUMBER (),
+ //.REVISION (),
+ .BASE (BASEADDR_SYSROMTABLE),
+ // Entry 0 = Cortex-M0+ Processor
+ .ENTRY0BASEADDR (32'hE00FF000),
+ .ENTRY0PRESENT (1'b1),
+ // Entry 1 = CoreSight MTB-M0+
+ .ENTRY1BASEADDR (32'hF0200000),
+ .ENTRY1PRESENT (0))
+ u_system_rom_table
+ (//Outputs
+ .HRDATA (sysrom_hrdata[31:0]),
+ .HREADYOUT (sysrom_hreadyout),
+ .HRESP (sysrom_hresp),
+ //Inputs
+ .HCLK (HCLK),
+ .HSEL (sysrom_hsel),
+ .HADDR (HADDR[31:0]),
+ .HBURST (HBURST[2:0]),
+ .HMASTLOCK (HMASTLOCK),
+ .HPROT (HPROT[3:0]),
+ .HSIZE (HSIZE[2:0]),
+ .HTRANS (HTRANS[1:0]),
+ .HWDATA (HWDATA[31:0]),
+ .HWRITE (HWRITE),
+ .HREADY (HREADY),
+ .ECOREVNUM (4'h0));
+
+ // -------------------------------
+ // Peripherals
+ // -------------------------------
+
+ cmsdk_mcu_sysctrl #(.BE (BE))
+ u_cmsdk_mcu_sysctrl
+ (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .FCLK (FCLK),
+ .PORESETn (PORESETn),
+ .HSEL (sysctrl_hsel),
+ .HREADY (HREADY),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HADDR (HADDR[11:0]),
+ .HWDATA (HWDATA),
+ // AHB Outputs
+ .HREADYOUT (sysctrl_hreadyout),
+ .HRESP (sysctrl_hresp),
+ .HRDATA (sysctrl_hrdata),
+ // Reset information
+ .SYSRESETREQ (SYSRESETREQ),
+ .WDOGRESETREQ (WDOGRESETREQ),
+ .LOCKUP (LOCKUP),
+ // Engineering-change-order revision bits
+ .ECOREVNUM (4'h0),
+ // System control signals
+ .REMAP (REMAP_CTRL),
+ .PMUENABLE (PMUENABLE),
+ .LOCKUPRESET (LOCKUPRESET)
+ );
+
+ // GPIO is driven from the AHB
+ cmsdk_ahb_gpio #(
+ .ALTERNATE_FUNC_MASK (16'h0000), // No pin muxing for Port #0
+ .ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
+ .BE (BE)
+ )
+ u_ahb_gpio_0 (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .FCLK (FCLK),
+ .HSEL (gpio0_hsel),
+ .HREADY (HREADY),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HADDR (HADDR[11:0]),
+ .HWDATA (HWDATA),
+ // AHB Outputs
+ .HREADYOUT (gpio0_hreadyout),
+ .HRESP (gpio0_hresp),
+ .HRDATA (gpio0_hrdata),
+
+ .ECOREVNUM (4'h0),// Engineering-change-order revision bits
+
+ .PORTIN (p0_in), // GPIO Interface inputs
+ .PORTOUT (p0_out), // GPIO Interface outputs
+ .PORTEN (p0_outen),
+ .PORTFUNC (p0_altfunc), // Alternate function control
+
+ .GPIOINT (SYS_GPIO0_IRQ[15:0]), // Interrupt outputs
+ .COMBINT ( )
+ );
+
+
+ cmsdk_ahb_gpio #(
+ .ALTERNATE_FUNC_MASK (16'h002A), // pin muxing for Port #1
+ .ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
+ .BE (BE)
+ )
+ u_ahb_gpio_1 (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .FCLK (FCLK),
+ .HSEL (gpio1_hsel),
+ .HREADY (HREADY),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HADDR (HADDR[11:0]),
+ .HWDATA (HWDATA),
+ // AHB Outputs
+ .HREADYOUT (gpio1_hreadyout),
+ .HRESP (gpio1_hresp),
+ .HRDATA (gpio1_hrdata),
+
+ .ECOREVNUM (4'h0),// Engineering-change-order revision bits
+
+ .PORTIN (p1_in), // GPIO Interface inputs
+ .PORTOUT (p1_out), // GPIO Interface outputs
+ .PORTEN (p1_outen),
+ .PORTFUNC (p1_altfunc), // Alternate function control
+
+ .GPIOINT (SYS_GPIO1_IRQ[15:0]), // Interrupt outputs
+ .COMBINT ( )
+ );
+
+ // APB subsystem for timers, UARTs
+ cmsdk_apb_subsystem #(
+ .APB_EXT_PORT12_ENABLE (1),
+ .APB_EXT_PORT13_ENABLE (1),
+ .APB_EXT_PORT14_ENABLE (1),
+ .APB_EXT_PORT15_ENABLE (1),
+ .INCLUDE_IRQ_SYNCHRONIZER(0),
+ .INCLUDE_APB_TEST_SLAVE (1),
+ .INCLUDE_APB_TIMER0 (1), // Include simple timer #0
+ .INCLUDE_APB_TIMER1 (1), // Include simple timer #1
+ .INCLUDE_APB_DUALTIMER0 (1), // Include dual timer module
+ .INCLUDE_APB_UART0 (1), // Include simple UART #0
+ .INCLUDE_APB_UART1 (1), // Include simple UART #1
+ .INCLUDE_APB_UART2 (1), // Include simple UART #2.
+ .INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
+ .BE (BE)
+ )
+ u_apb_subsystem(
+
+ // AHB interface for AHB to APB bridge
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .HSEL (apbsys_hsel),
+ .HADDR (HADDR[15:0]),
+ .HTRANS (HTRANS[1:0]),
+ .HWRITE (HWRITE),
+ .HSIZE (HSIZE),
+ .HPROT (HPROT),
+ .HREADY (HREADY),
+ .HWDATA (HWDATA[31:0]),
+
+ .HREADYOUT (apbsys_hreadyout),
+ .HRDATA (apbsys_hrdata),
+ .HRESP (apbsys_hresp),
+
+ // APB clock and reset
+ .PCLK (PCLK),
+ .PCLKG (PCLKG),
+ .PCLKEN (PCLKEN),
+ .PRESETn (PRESETn),
+
+ // APB extension ports
+ .PADDR (exp_paddr[11:0]),
+ .PWRITE (exp_pwrite),
+ .PWDATA (exp_pwdata[31:0]),
+ .PENABLE (exp_penable),
+
+ .ext12_psel (exp12_psel),
+ .ext13_psel (exp13_psel),
+ .ext14_psel (exp14_psel),
+ .ext15_psel (exp15_psel),
+
+ // Input from APB devices on APB expansion ports
+ .ext12_prdata (exp12_prdata),
+ .ext12_pready (exp12_pready),
+ .ext12_pslverr (exp12_pslverr),
+ .ext13_prdata (exp13_prdata),
+ .ext13_pready (exp13_pready),
+ .ext13_pslverr (exp13_pslverr),
+ .ext14_prdata (exp14_prdata),
+ .ext14_pready (exp14_pready),
+ .ext14_pslverr (exp14_pslverr),
+ .ext15_prdata (exp15_prdata),
+ .ext15_pready (exp15_pready),
+ .ext15_pslverr (exp15_pslverr),
+
+ .APBACTIVE (APBACTIVE), // Status Output for clock gating
+
+ // Peripherals
+ // UART
+ .uart0_rxd (uart0_rxd),
+ .uart0_txd (uart0_txd),
+ .uart0_txen (uart0_txen),
+
+ .uart1_rxd (uart1_rxd),
+ .uart1_txd (uart1_txd),
+ .uart1_txen (uart1_txen),
+
+ .uart2_rxd (uart2_rxd),
+ .uart2_txd (uart2_txd),
+ .uart2_txen (uart2_txen),
+
+ // Timer
+ .timer0_extin (timer0_extin),
+ .timer1_extin (timer1_extin),
+
+ // Interrupt outputs
+ .apbsubsys_interrupt (SYS_APB_IRQ),
+ .watchdog_interrupt (SYS_NMI),
+ // reset output
+ .watchdog_reset (WDOGRESETREQ)
+ );
+
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/pl230_defs.v b/Cortex-M0/nanosoc/systems/mcu/verilog/pl230_defs.v
new file mode 100644
index 0000000000000000000000000000000000000000..c061b99bcddb90d59d4bd00a4a06094364f70c39
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/pl230_defs.v
@@ -0,0 +1,189 @@
+//-----------------------------------------------------------------------------
+// customised example Cortex-M0 controller DMA230 configuration
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+// (C) COPYRIGHT 2006-2007 ARM Limited.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+// File Name : pl230_defs.v
+// Checked In : $Date: 2007-06-06 21:55:22 +0530 (Wed, 06 Jun 2007) $
+// Revision : $Revision: 13823 $
+// State : $state: PL230-DE-98007-r0p0-02rel0 $
+//
+//-----------------------------------------------------------------------------
+// Purpose : Peripheral specific macro definitions
+//
+//-----------------------------------------------------------------------------
+
+
+`ifdef ARM_TIMESCALE_DEFINED
+ `timescale 1ns/1ps
+`endif
+
+// Set the number of channels implemented
+`define PL230_CHNLS 1
+`define PL230_CHNL_BITS 1
+//`define PL230_ONE_CHNL
+
+// Include Integration Test Logic
+`define PL230_INCLUDE_TEST
+
+
+// AHB Interface
+`define PL230_AHB_TRANS_IDLE 2'b00
+`define PL230_AHB_TRANS_NONSEQ 2'b10
+`define PL230_AHB_READ 1'b0
+`define PL230_AHB_WRITE 1'b1
+`define PL230_AHB_SIZE_BYTE 3'b000
+`define PL230_AHB_SIZE_HWORD 3'b001
+`define PL230_AHB_SIZE_WORD 3'b010
+
+// PrimeCell Configuration
+`define PL230_PERIPH_ID_0 8'h30
+`define PL230_PERIPH_ID_1 8'hB2
+`define PL230_PERIPH_ID_2 8'h0B
+`define PL230_PERIPH_ID_3 8'h00
+`define PL230_PERIPH_ID_4 8'h04
+`define PL230_PCELL_ID_0 8'h0D
+`define PL230_PCELL_ID_1 8'hF0
+`define PL230_PCELL_ID_2 8'h05
+`define PL230_PCELL_ID_3 8'hB1
+
+// Memory Mapped Registers
+// Controller Configuration Registers
+`define PL230_ADDR_DMA_STATUS 12'h000
+`define PL230_ADDR_DMA_CFG 12'h004
+`define PL230_ADDR_CTRL_BASE_PTR 12'h008
+`define PL230_ADDR_ALT_CTRL_BASE_PTR 12'h00C
+`define PL230_ADDR_DMA_WAITONREQ_STATUS 12'h010
+`define PL230_ADDR_CHNL_SW_REQUEST 12'h014
+`define PL230_ADDR_CHNL_USEBURST_SET 12'h018
+`define PL230_ADDR_CHNL_USEBURST_CLR 12'h01C
+`define PL230_ADDR_CHNL_REQ_MASK_SET 12'h020
+`define PL230_ADDR_CHNL_REQ_MASK_CLR 12'h024
+`define PL230_ADDR_CHNL_ENABLE_SET 12'h028
+`define PL230_ADDR_CHNL_ENABLE_CLR 12'h02C
+`define PL230_ADDR_CHNL_PRI_ALT_SET 12'h030
+`define PL230_ADDR_CHNL_PRI_ALT_CLR 12'h034
+`define PL230_ADDR_CHNL_PRIORITY_SET 12'h038
+`define PL230_ADDR_CHNL_PRIORITY_CLR 12'h03C
+// Reserved 12'h040
+// Reserved 12'h044
+// Reserved 12'h048
+`define PL230_ADDR_ERR_CLR 12'h04C
+// Integration Test Registers
+`define PL230_ADDR_INTEGRATION_CFG 12'hE00
+// Reserved 12'hE04
+`define PL230_ADDR_STALL_STATUS 12'hE08
+// Reserved 12'hE0C
+`define PL230_ADDR_DMA_REQ_STATUS 12'hE10
+// Reserved 12'hE14
+`define PL230_ADDR_DMA_SREQ_STATUS 12'hE18
+// Reserved 12'hE1C
+`define PL230_ADDR_DMA_DONE_SET 12'hE20
+`define PL230_ADDR_DMA_DONE_CLR 12'hE24
+`define PL230_ADDR_DMA_ACTIVE_SET 12'hE28
+`define PL230_ADDR_DMA_ACTIVE_CLR 12'hE2C
+// Reserved 12'hE30
+// Reserved 12'hE34
+// Reserved 12'hE38
+// Reserved 12'hE3C
+// Reserved 12'hE40
+// Reserved 12'hE44
+`define PL230_ADDR_ERR_SET 12'hE48
+// Reserved 12'hE4C
+// PrimeCell Configuration Registers
+`define PL230_ADDR_PERIPH_ID_4 12'hFD0
+// Reserved 12'hFD4
+// Reserved 12'hFD8
+// Reserved 12'hFDC
+`define PL230_ADDR_PERIPH_ID_0 12'hFE0
+`define PL230_ADDR_PERIPH_ID_1 12'hFE4
+`define PL230_ADDR_PERIPH_ID_2 12'hFE8
+`define PL230_ADDR_PERIPH_ID_3 12'hFEC
+`define PL230_ADDR_PCELL_ID_0 12'hFF0
+`define PL230_ADDR_PCELL_ID_1 12'hFF4
+`define PL230_ADDR_PCELL_ID_2 12'hFF8
+`define PL230_ADDR_PCELL_ID_3 12'hFFC
+
+
+// Bit vector definitions for channel_cfg
+`define PL230_CHANNEL_CFG_BITS 20
+// Destination address increment
+`define PL230_CHANNEL_CFG_DST_INC channel_cfg[19:18]
+`define PL230_HRDATA_DST_INC hrdata[31:30]
+// Destination transfer size
+// Source and destination sizes must match
+// so the same bits as the src_size are used
+`define PL230_CHANNEL_CFG_DST_SIZE channel_cfg[15:14]
+`define PL230_HRDATA_DST_SIZE hrdata[29:28]
+// Source address increment
+`define PL230_CHANNEL_CFG_SRC_INC channel_cfg[17:16]
+`define PL230_HRDATA_SRC_INC hrdata[27:26]
+// Source transfer size
+`define PL230_CHANNEL_CFG_SRC_SIZE channel_cfg[15:14]
+`define PL230_HRDATA_SRC_SIZE hrdata[25:24]
+// Destination AHB protection control
+`define PL230_CHANNEL_CFG_DST_PROT_CTRL channel_cfg[13:11]
+`define PL230_HRDATA_DST_PROT_CTRL hrdata[23:21]
+// Source AHB protection control
+`define PL230_CHANNEL_CFG_SRC_PROT_CTRL channel_cfg[10:8]
+`define PL230_HRDATA_SRC_PROT_CTRL hrdata[20:18]
+// Power of two transactions per request
+`define PL230_CHANNEL_CFG_R channel_cfg[7:4]
+`define PL230_HRDATA_R hrdata[17:14]
+// Number of bits in the N counter - hrdata[13:4]
+`define PL230_N_COUNT_BITS 10
+// Lsb bit offset for n_minus_1
+`define PL230_N_COUNT_OFFSET 4
+// Set chnl_useburst_status
+`define PL230_CHANNEL_CFG_NEXT_USEBURST channel_cfg[3]
+`define PL230_HRDATA_NEXT_USEBURST hrdata[3]
+// DMA cycle control
+`define PL230_CHANNEL_CFG_CYCLE_CTRL channel_cfg[2:0]
+`define PL230_HRDATA_CYCLE_CTRL hrdata[2:0]
+
+
+// Number of bits for the statemachine
+`define PL230_STATE_BITS 4
+// Statemachine state encoding
+`define PL230_ST_IDLE 4'h0
+`define PL230_ST_RD_CTRL 4'h1
+`define PL230_ST_RD_SPTR 4'h2
+`define PL230_ST_RD_DPTR 4'h3
+`define PL230_ST_RD_SDAT 4'h4
+`define PL230_ST_WR_DDAT 4'h5
+`define PL230_ST_WAIT 4'h6
+`define PL230_ST_WR_CTRL 4'h7
+`define PL230_ST_STALL 4'h8
+`define PL230_ST_DONE 4'h9
+`define PL230_ST_PSGP 4'hA
+`define PL230_ST_RESVD_0 4'hB
+`define PL230_ST_RESVD_1 4'hC
+`define PL230_ST_RESVD_2 4'hD
+`define PL230_ST_RESVD_3 4'hE
+`define PL230_ST_RESVD_4 4'hF
+
+`define PL230_SIZE_BYTE 2'b00
+`define PL230_SIZE_HWORD 2'b01
+`define PL230_SIZE_WORD 2'b10
+`define PL230_SIZE_RESVD 2'b11
+
+// pl230_defs.v end
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
new file mode 100644
index 0000000000000000000000000000000000000000..19fedd8fe3198575610d620c36c7bd1b1ac889f0
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
@@ -0,0 +1,571 @@
+//-----------------------------------------------------------------------------
+// customised example Cortex-M0 controller testbench with CPU trace for RTL or netlist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Testbench for the Cortex-M0 example system
+//-----------------------------------------------------------------------------
+//
+`timescale 1ns/1ps
+
+module tb_cmsdk_mcu;
+
+ wire XTAL1; // crystal pin 1
+ wire XTAL2; // crystal pin 2
+ wire NRST; // active low reset
+
+ wire [15:0] P0; // Port 0
+ wire [15:0] P1; // Port 1
+
+ wire VDDIO;
+ wire VSSIO;
+ wire VDD;
+ wire VSS;
+
+ //Debug tester signals
+ wire nTRST;
+ wire TDI;
+ wire SWDIOTMS;
+ wire SWCLKTCK;
+ wire TDO;
+
+ wire PCLK; // Clock for UART capture device
+ wire [5:0] debug_command; // used to drive debug tester
+ wire debug_running; // indicate debug test is running
+ wire debug_err; // indicate debug test has error
+
+ wire debug_test_en1;
+ wire debug_test_en2;
+ wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
+ // This signal is controlled by software,
+ // Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
+ // the command, use "UartPutc((char) 0x11)" to send debug test
+ // enable command, use "UartPutc((char) 0x12)" to send debug test
+ // disable command. Refer to tb_uart_capture.v file for detail
+ assign debug_test_en = debug_test_en1 | debug_test_en2; // FT1248 or UART2 control
+
+ //-----------------------------------------
+ // System options
+
+`define MEM_INIT 1;
+localparam BE=0;
+`define ARM_CMSDK_INCLUDE_DEBUG_TESTER 1
+
+SROM_Ax32
+ #(.ADDRWIDTH (8),
+ .filename ("bootloader.hex"),
+ .romgen (1)
+ )
+ u_BOOTROM (
+ .CLK(XTAL1),
+ .ADDR(8'h0),
+ .SEL(1'b0),
+ .RDATA( )
+ );
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0/Cortex-M0+ Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip_pads
+ u_nanosoc_chip_pads (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+`endif
+ .XTAL1 (XTAL1), // input
+ .XTAL2 (XTAL2), // output
+ .NRST (NRST), // active low reset
+ .P0 (P0),
+ .P1 (P1),
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+ .nTRST (nTRST), // Not needed if serial-wire debug is used
+ .TDI (TDI), // Not needed if serial-wire debug is used
+ .TDO (TDO), // Not needed if serial-wire debug is used
+`endif
+ .SWDIOTMS (SWDIOTMS),
+ .SWCLKTCK (SWCLKTCK)
+ );
+
+ // --------------------------------------------------------------------------------
+ // Source for clock and reset
+ // --------------------------------------------------------------------------------
+ cmsdk_clkreset u_cmsdk_clkreset(
+ .CLK (XTAL1),
+ .NRST (NRST)
+ );
+
+ // Pullup to suppress X-inputs
+ pullup(P0[ 0]);
+ pullup(P0[ 1]);
+ pullup(P0[ 2]);
+ pullup(P0[ 3]);
+ pullup(P0[ 4]);
+ pullup(P0[ 5]);
+ pullup(P0[ 6]);
+ pullup(P0[ 7]);
+ pullup(P0[ 8]);
+ pullup(P0[ 9]);
+ pullup(P0[10]);
+ pullup(P0[11]);
+ pullup(P0[12]);
+ pullup(P0[13]);
+ pullup(P0[14]);
+ pullup(P0[15]);
+
+ pullup(P1[ 0]);
+ pullup(P1[ 1]);
+ pullup(P1[ 2]);
+ pullup(P1[ 3]);
+ pullup(P1[ 4]);
+ pullup(P1[ 5]);
+ pullup(P1[ 6]);
+ pullup(P1[ 7]);
+ pullup(P1[ 8]);
+ pullup(P1[ 9]);
+ pullup(P1[10]);
+ pullup(P1[11]);
+ pullup(P1[12]);
+ pullup(P1[13]);
+ pullup(P1[14]);
+ pullup(P1[15]);
+
+ // --------------------------------------------------------------------------------
+ // UART output capture
+ // --------------------------------------------------------------------------------
+`ifdef ARM_CMSDK_SLOWSPEED_PCLK
+ // If PCLK is running at slower speed, the UART output will also be slower
+ assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
+`else
+ assign PCLK = XTAL1;
+`endif
+
+ // --------------------------------------------------------------------------------
+ // external UART phase lock to (known) baud rate
+
+// seem unable to use the following (due to generate instance naming?)
+// wire baudx16_clk = u_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_apb_subsystem.u_apb_uart_2.BAUDTICK;
+
+// 2000000/208 = 9615 baud (+0.16%)
+// 208 / 16
+`define BAUDPROG 130
+
+ reg [7:0] bauddiv;
+ wire baudclken = (bauddiv == 8'b00000000);
+
+ always @(negedge NRST or posedge PCLK)
+ if (!NRST)
+ bauddiv <=0;
+ else
+ bauddiv <= (baudclken) ? (`BAUDPROG-1) : (bauddiv -1) ; // count down of BAUDPROG
+
+ wire baudx16_clk = bauddiv[7]; //prefer:// !baudclken;
+
+ wire UARTXD = P1[5];
+ reg UARTXD_del;
+ always @(negedge NRST or posedge baudx16_clk)
+ if (!NRST)
+ UARTXD_del <= 1'b0;
+ else
+ UARTXD_del <= UARTXD; // delay one BAUD_TICK-time
+
+ wire UARTXD_edge = UARTXD_del ^ UARTXD; // edge detect
+
+ reg [3:0] pllq;
+ always @(negedge NRST or posedge baudx16_clk)
+ if (!NRST)
+ pllq[3:0] <= 4'b0000; // phase lock ready for Q[3] to go high
+ else
+ if (UARTXD_edge)
+ pllq[3:0] <= 4'b0110; // sync to mid bit-time
+ else
+ pllq[3:0] <= pllq[3:0] - 1; // count down divide-by-16
+
+ wire baud_clk = pllq[3];
+
+reg baud_clk_del;
+ always @(negedge NRST or posedge PCLK)
+ if (!NRST)
+ baud_clk_del <= 1'b1;
+ else
+ baud_clk_del <= baud_clk;
+
+ // --------------------------------------------------------------------------------
+ // set FASTMODE true if UART simulation mode is programmed
+ wire FASTMODE = 1'b0;
+ wire uart_clk = (FASTMODE) ? PCLK : baud_clk; //(baud_clk & !baud_clk_del);
+
+
+ cmsdk_uart_capture #(.LOGFILENAME("uart2.log"))
+ u_cmsdk_uart_capture(
+ .RESETn (NRST),
+ .CLK (uart_clk), //PCLK),
+ .RXD (UARTXD), // UART 2 use for StdOut
+ .DEBUG_TESTER_ENABLE (debug_test_en2),
+ .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
+ .AUXCTRL ()
+ );
+
+ // --------------------------------------------------------------------------------
+ // FTDI IO capture
+ // --------------------------------------------------------------------------------
+
+ // UART connection cross over for UART test
+// assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
+// assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
+
+wire ft_clk_out = P1[1];
+wire ft_miso_in;
+assign P1[0] = ft_miso_in;
+wire ft_ssn_out = P1[3];
+
+// bufif0 (P1[2], ft_miosio_i, ft_miosio_z);
+wire ft_clk2uart;
+wire ft_rxd2uart;
+wire ft_txd2uart;
+
+ cmsdk_ft1248x1_adpio // #(.ADPFILENAME("ADPFILENAME.log"))
+ u_ft1248_adpio(
+ .ft_clk_i (ft_clk_out),
+ .ft_ssn_i (ft_ssn_out),
+ .ft_miso_o (ft_miso_in),
+ .ft_miosio_io (P1[2]),
+
+ .FTDI_CLK2UART_o (ft_clk2uart),
+ .FTDI_OP2UART_o (ft_rxd2uart),
+ .FTDI_IP2UART_o (ft_txd2uart)
+ );
+
+ cmsdk_uart_capture #(.LOGFILENAME("ft1248_op.log"))
+ u_cmsdk_uart_capture1(
+ .RESETn (NRST),
+ .CLK (ft_clk2uart),
+ .RXD (ft_rxd2uart),
+ .DEBUG_TESTER_ENABLE (debug_test_en1),
+ .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
+ .AUXCTRL ()
+ );
+
+ cmsdk_uart_capture #(.LOGFILENAME("ft1248_ip.log"))
+ u_cmsdk_uart_capture2(
+ .RESETn (NRST),
+ .CLK (ft_clk2uart),
+ .RXD (ft_txd2uart),
+ .DEBUG_TESTER_ENABLE ( ),
+ .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
+ .AUXCTRL ()
+ );
+
+
+
+ // --------------------------------------------------------------------------------
+ // Tracking CPU with Tarmac trace support
+ // --------------------------------------------------------------------------------
+
+
+`ifdef CORTEX_M0
+`ifdef USE_TARMAC
+
+`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_cpu.u_cortex_m0_integration.u_cortexm0
+
+ CORTEXM0
+ #(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
+ .DBG(1), .NUMIRQ(32), .RAR(1), .SMUL(0),
+ .SYST(1), .WIC(1), .WICLINES(34), .WPT(2))
+ u_cortexm0_track
+ (
+ // Outputs
+ .HADDR ( ),
+ .HBURST ( ),
+ .HMASTLOCK ( ),
+ .HPROT ( ),
+ .HSIZE ( ),
+ .HTRANS ( ),
+ .HWDATA ( ),
+ .HWRITE ( ),
+ .HMASTER ( ),
+ .SLVRDATA ( ),
+ .SLVREADY ( ),
+ .SLVRESP ( ),
+ .DBGRESTARTED ( ),
+ .HALTED ( ),
+ .TXEV ( ),
+ .LOCKUP ( ),
+ .SYSRESETREQ ( ),
+ .CODENSEQ ( ),
+ .CODEHINTDE ( ),
+ .SPECHTRANS ( ),
+ .SLEEPING ( ),
+ .SLEEPDEEP ( ),
+ .SLEEPHOLDACKn ( ),
+ .WICDSACKn ( ),
+ .WICMASKISR ( ),
+ .WICMASKNMI ( ),
+ .WICMASKRXEV ( ),
+ .WICLOAD ( ),
+ .WICCLEAR ( ),
+ // Inputs
+ .SCLK (`ARM_CM0IK_PATH.SCLK),
+ .HCLK (`ARM_CM0IK_PATH.HCLK),
+ .DCLK (`ARM_CM0IK_PATH.DCLK),
+ .DBGRESETn (`ARM_CM0IK_PATH.DBGRESETn),
+ .HRESETn (`ARM_CM0IK_PATH.HRESETn),
+ .HRDATA (`ARM_CM0IK_PATH.HRDATA[31:0]),
+ .HREADY (`ARM_CM0IK_PATH.HREADY),
+ .HRESP (`ARM_CM0IK_PATH.HRESP),
+ .SLVADDR (`ARM_CM0IK_PATH.SLVADDR[31:0]),
+ .SLVSIZE (`ARM_CM0IK_PATH.SLVSIZE[1:0]),
+ .SLVTRANS (`ARM_CM0IK_PATH.SLVTRANS[1:0]),
+ .SLVWDATA (`ARM_CM0IK_PATH.SLVWDATA[31:0]),
+ .SLVWRITE (`ARM_CM0IK_PATH.SLVWRITE),
+ .DBGRESTART (`ARM_CM0IK_PATH.DBGRESTART),
+ .EDBGRQ (`ARM_CM0IK_PATH.EDBGRQ),
+ .NMI (`ARM_CM0IK_PATH.NMI),
+ .IRQ (`ARM_CM0IK_PATH.IRQ[31:0]),
+ .RXEV (`ARM_CM0IK_PATH.RXEV),
+ .STCALIB (`ARM_CM0IK_PATH.STCALIB[25:0]),
+ .STCLKEN (`ARM_CM0IK_PATH.STCLKEN),
+ .IRQLATENCY (`ARM_CM0IK_PATH.IRQLATENCY[7:0]),
+ .ECOREVNUM (`ARM_CM0IK_PATH.ECOREVNUM[19:0]),
+ .SLEEPHOLDREQn (`ARM_CM0IK_PATH.SLEEPHOLDREQn),
+ .WICDSREQn (`ARM_CM0IK_PATH.WICDSREQn),
+ .SE (`ARM_CM0IK_PATH.SE));
+
+`define ARM_CM0IK_TRACK u_cortexm0_track
+ cm0_tarmac #(.LOGFILENAME("tarmac0.log"))
+ u_tarmac_track
+ (.enable_i (1'b1),
+
+ .hclk_i (`ARM_CM0IK_TRACK.HCLK),
+ .hready_i (`ARM_CM0IK_TRACK.HREADY),
+ .haddr_i (`ARM_CM0IK_TRACK.HADDR[31:0]),
+ .hprot_i (`ARM_CM0IK_TRACK.HPROT[3:0]),
+ .hsize_i (`ARM_CM0IK_TRACK.HSIZE[2:0]),
+ .hwrite_i (`ARM_CM0IK_TRACK.HWRITE),
+ .htrans_i (`ARM_CM0IK_TRACK.HTRANS[1:0]),
+ .hresetn_i (`ARM_CM0IK_TRACK.HRESETn),
+ .hresp_i (`ARM_CM0IK_TRACK.HRESP),
+ .hrdata_i (`ARM_CM0IK_TRACK.HRDATA[31:0]),
+ .hwdata_i (`ARM_CM0IK_TRACK.HWDATA[31:0]),
+ .lockup_i (`ARM_CM0IK_TRACK.LOCKUP),
+ .halted_i (`ARM_CM0IK_TRACK.HALTED),
+ .codehintde_i (`ARM_CM0IK_TRACK.CODEHINTDE[2:0]),
+ .codenseq_i (`ARM_CM0IK_TRACK.CODENSEQ),
+
+ .hdf_req_i (`ARM_CM0IK_TRACK.u_top.u_sys.ctl_hdf_request),
+ .int_taken_i (`ARM_CM0IK_TRACK.u_top.u_sys.dec_int_taken_o),
+ .int_return_i (`ARM_CM0IK_TRACK.u_top.u_sys.dec_int_return_o),
+ .int_pend_i (`ARM_CM0IK_TRACK.u_top.u_sys.nvm_int_pend),
+ .pend_num_i (`ARM_CM0IK_TRACK.u_top.u_sys.nvm_int_pend_num[5:0]),
+ .ipsr_i (`ARM_CM0IK_TRACK.u_top.u_sys.psr_ipsr[5:0]),
+
+ .ex_last_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_ex_last),
+ .iaex_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_iaex_en),
+ .reg_waddr_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_wr_addr[3:0]),
+ .reg_write_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_wr_en),
+ .xpsr_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_xpsr_en),
+ .fe_addr_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_fe_addr[30:0]),
+ .int_delay_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_int_delay),
+ .special_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_op_special),
+ .opcode_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_opcode[15:0]),
+ .reg_wdata_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.psr_gpr_wdata[31:0]),
+
+ .atomic_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.atomic),
+ .atomic_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.atomic_nxt),
+ .dabort_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.data_abort),
+ .ex_last_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.ex_last_nxt),
+ .int_preempt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.int_preempt),
+
+ .psp_sel_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_gpr.psp_sel),
+ .xpsr_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_gpr.xpsr[31:0]),
+
+ .iaex_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.iaex[30:0]),
+ .iaex_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.iaex_nxt[30:0]),
+ .opcode_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.ibuf_de_nxt[15:0]),
+ .delay_count_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.ibuf_lo[13:6]),
+ .tbit_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.tbit_en),
+
+ .cflag_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.cflag_ena),
+ .ipsr_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.ipsr_ena),
+ .nzflag_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.nzflag_ena),
+ .vflag_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.vflag_ena)
+ );
+
+`endif // USE_TARMAC
+`endif // CORTEX_M0
+
+ // --------------------------------------------------------------------------------
+ // Debug tester connection -
+ // --------------------------------------------------------------------------------
+
+ `ifdef CORTEX_M0DESIGNSTART
+ // No debug connection for Cortex-M0 DesignStart
+ assign nTRST = NRST;
+ assign TDI = 1'b1;
+ assign SWDIOTMS = 1'b1;
+ assign SWCLKTCK = 1'b1;
+
+ bufif1 (P0[31-16], debug_running, debug_test_en);
+ bufif1 (P0[30-16], debug_err, debug_test_en);
+
+ pullup (debug_running);
+ pullup (debug_err);
+
+ `else
+ `ifdef ARM_CMSDK_INCLUDE_DEBUG_TESTER
+
+ // Add pullups and pulldowns on Debug Interface
+
+ pullup (nTRST);
+ pullup (TDI);
+ pullup (TDO);
+ pullup (SWDIOTMS);
+ pulldown (SWCLKTCK);
+
+
+ //connect to P0 for debug command and status pin
+ //add pulldown to debug command and debug status signals
+ // to give default value 0;
+ pulldown(debug_command[5]);
+ pulldown(debug_command[4]);
+ pulldown(debug_command[3]);
+ pulldown(debug_command[2]);
+ pulldown(debug_command[1]);
+ pulldown(debug_command[0]);
+
+ pulldown(debug_running);
+ pulldown(debug_err);
+
+ //Tristate logic for GPIO connection
+ bufif1 (debug_command[5], P0[29-16], debug_test_en);
+ bufif1 (debug_command[4], P0[28-16], debug_test_en);
+ bufif1 (debug_command[3], P0[27-16], debug_test_en);
+ bufif1 (debug_command[2], P0[26-16], debug_test_en);
+ bufif1 (debug_command[1], P0[25-16], debug_test_en);
+ bufif1 (debug_command[0], P0[24-16], debug_test_en);
+
+ bufif1 (P0[31-16], debug_running, debug_test_en);
+ bufif1 (P0[30-16], debug_err, debug_test_en);
+
+
+ cmsdk_debug_tester #(.ROM_MEMFILE((BE==1) ? "debugtester_be.hex" : "debugtester_le.hex"))
+ u_cmsdk_debug_tester
+ (
+ // Clock and Reset
+ .CLK (XTAL1),
+ .PORESETn (NRST),
+
+ // Command Interface
+ .DBGCMD (debug_command[5:0]),
+ .DBGRUNNING (debug_running),
+ .DBGERROR (debug_err),
+
+ // Trace Interface
+ .TRACECLK (1'b0),
+ .TRACEDATA (4'h0),
+ .SWV (1'b0),
+
+ // Debug Interface
+ .TDO (TDO),
+ .nTRST (nTRST),
+ .SWCLKTCK (SWCLKTCK),
+ .TDI (TDI),
+ .SWDIOTMS (SWDIOTMS)
+ );
+
+
+ `else
+ assign nTRST = NRST;
+ assign TDI = 1'b1;
+ assign SWDIOTMS = 1'b1;
+ assign SWCLKTCK = 1'b1;
+
+ bufif1 (P0[31-16], debug_running, debug_test_en);
+ bufif1 (P0[30-16], debug_err, debug_test_en);
+
+ pullup(debug_running);
+ pullup(debug_err);
+
+ `endif
+ `endif
+
+ // --------------------------------------------------------------------------------
+ // Misc
+ // --------------------------------------------------------------------------------
+
+ // Format for time reporting
+ initial $timeformat(-9, 0, " ns", 0);
+
+ // Configuration checks
+ initial begin
+`ifdef CORTEX_M0DESIGNSTART
+`ifdef CORTEX_M0
+ $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0 are set. Please use only one.");
+ $stop;
+`endif
+`endif
+`ifdef CORTEX_M0DESIGNSTART
+`ifdef CORTEX_M0PLUS
+ $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0PLUS are set. Please use only one.");
+ $stop;
+`endif
+`endif
+`ifdef CORTEX_M0
+`ifdef CORTEX_M0PLUS
+ $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : Both CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
+ $stop;
+`endif
+`endif
+`ifdef CORTEX_M0DESIGNSTART
+`ifdef CORTEX_M0
+`ifdef CORTEX_M0PLUS
+ $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : All of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
+ $stop;
+`endif
+`endif
+`endif
+`ifdef CORTEX_M0
+`else
+`ifdef CORTEX_M0PLUS
+`else
+`ifdef CORTEX_M0DESIGNSTART
+`else
+ $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : None of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please select one.");
+ $stop;
+`endif
+`endif
+`endif
+
+ end
+endmodule
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc b/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc
new file mode 100644
index 0000000000000000000000000000000000000000..3e9c2037311f5110a5225592d21b186344e42680
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc
@@ -0,0 +1,145 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: $
+//
+// Revision : $Revision: $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Cortex-M0 example system
+//-----------------------------------------------------------------------------
+//
+// ================= MCU System options ===============
+// Option to select Cortex-M0+ processor in example system
++define+CORTEX_M0
+
+// =================== Tarmac Logging =================
++define+USE_TARMAC
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ================= Top level file ===================
+../verilog/tb_nanosoc.v
++incdir+../verilog
++incdir+/../verilog/soclabs_4x7_AhbMatrix
+-y ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
+
+// ============= GLIB Generic Library path =============
+../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+../../../../../GLIB/pads/verilog/PAD_VDDIO.v
+../../../../../GLIB/pads/verilog/PAD_VSSIO.v
+../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
+../../../../../GLIB/pads/verilog/PAD_VSS.v
+../../../../../GLIB/mem/verilog/SROM_Ax32.v
+
+// ================= Testbench path ===================
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
+
+// ============= MCU Module search path =============
+-y ../verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
+
+
+//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
+/// upgrade to AAA 'rel2' version
++incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+../verilog/pl230_defs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
+
+../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
+../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
+../verilog/cmsdk_apb_usrt.v
+
+// ============= Cortex-M0 Module search path =============
+
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog
+
+
+// ============= Cortex-M0 Include file search path =============
+
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog
+
+
+
+// =============Debug tester Include file search path =============
+
+
+// ============= OVL support libraries =============
+//+define+ASSERT_ON
+//+define+OVL_ASSERT_ON
+//+define+ARM_ASSERT_ON
+//+define+ARM_AHB_ASSERT_ON
+//+define+ARM_APB_ASSERT_ON
+//+define+ARM_CMSDK_ASSERT_ON
+
+// ============= Verification components =============
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/
+
+///+incdir+/arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl
+///-y /arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc b/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc
new file mode 100644
index 0000000000000000000000000000000000000000..f32853f70582b2ce34aca5a8e545663a1f4b2bac
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc
@@ -0,0 +1,120 @@
+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: $
+//
+// Revision : $Revision: $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Cortex-M0 example system
+//-----------------------------------------------------------------------------
+//
+// ================= MCU System options ===============
+// Option to select Cortex-M0+ processor in example system
++define+CORTEX_M0
+
+// =================== Tarmac Logging =================
++define+USE_TARMAC
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ================= Top level file ===================
+../verilog/tb_nanosoc.v
++incdir+../verilog
++incdir+/../verilog/soclabs_4x7_AhbMatrix
+-y ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
+
+// ================= Testbench path ===================
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
+
+// ============= GLIB Generic Library path =============
+../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+../../../../../GLIB/pads/verilog/PAD_VDDIO.v
+../../../../../GLIB/pads/verilog/PAD_VSSIO.v
+../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
+../../../../../GLIB/pads/verilog/PAD_VSS.v
+../../../../../GLIB/mem/verilog/SROM_Ax32.v
+
+// ============= IPLIB soclabs IP Library path =============
+../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
+../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
+../verilog/cmsdk_apb_usrt.v
+
+// ============= MCU Module search path =============
+-y ../verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
+-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog
+//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
+
+//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
+/// upgrade to AAA 'rel2' version
++incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+../verilog/pl230_defs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
+
+// ============= Cortex-M0 Module search path =============
+// guts of core not exposed, periphery only
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers
+-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog
+
+// ============= Cortex-M0 Include file search path =============
+// guts of core not exposed, periphery only
+
++incdi+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers
++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog
+
diff --git a/FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v b/FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v
new file mode 100644
index 0000000000000000000000000000000000000000..fa92fec42cf177510654b4a581f9af3749d38eef
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -0,0 +1,37 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+ // Inouts
+ PAD,
+ // Outputs
+ I,
+ // Inputs
+ O,
+ NOE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input NOE;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O(I),
+ .IO(PAD),
+ .I(O),
+ .T(NOE)
+ );
+
+endmodule // PAD_INOUT8MA_NOE
diff --git a/FPGALIB/pads/verilog/PAD_VDDIO.v b/FPGALIB/pads/verilog/PAD_VDDIO.v
new file mode 100644
index 0000000000000000000000000000000000000000..4fd7137e498cde9cef4ac9785cdef6d08349e69a
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VDDIO.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VDDIO
diff --git a/FPGALIB/pads/verilog/PAD_VDDSOC.v b/FPGALIB/pads/verilog/PAD_VDDSOC.v
new file mode 100644
index 0000000000000000000000000000000000000000..80f6a7200ee52de65784474c930ba65f8a9059be
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VDDSOC.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDSOC (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VDDSOC
diff --git a/FPGALIB/pads/verilog/PAD_VSS.v b/FPGALIB/pads/verilog/PAD_VSS.v
new file mode 100644
index 0000000000000000000000000000000000000000..046a389e5e39745459318e03888398083d2da29e
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VSS.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VSS
diff --git a/FPGALIB/pads/verilog/PAD_VSSIO.v b/FPGALIB/pads/verilog/PAD_VSSIO.v
new file mode 100644
index 0000000000000000000000000000000000000000..6bfb333db8746e7658ad4e719462e68538d60732
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VSSIO.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VSSIO
diff --git a/GLIB/mem/verilog/SROM_Ax32.v b/GLIB/mem/verilog/SROM_Ax32.v
new file mode 100644
index 0000000000000000000000000000000000000000..f2c3a9a576a89fe1f23305ed7e2921ad4c3ebb2b
--- /dev/null
+++ b/GLIB/mem/verilog/SROM_Ax32.v
@@ -0,0 +1,127 @@
+//-----------------------------------------------------------------------------
+//
+// Synthesizable byte-write addressible R/W (random-access) memory
+//
+// Synchronous data write, flow-though (non-pipeline registered) read data
+//
+// Auto-gernerates a synthesizable verilog ROM design
+// and binary text file for custom ROM via programming
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SROM_Ax32
+ #(parameter ADDRWIDTH = 10,
+ parameter filename = "rom32.hex",
+ parameter romgen = 0
+ )
+ (input wire CLK,
+ input wire [ADDRWIDTH-1:0] ADDR, //Address Input
+ input wire SEL, //Select (active-high)
+ output wire [31:0] RDATA); //Read Data
+
+ localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
+ localparam romgenfile = "bootrom.v";
+ localparam bingenfile = "bootrom.bintxt";
+
+ // Reg declarations
+ reg [7:0] rombyte0 [0:MEMDEPTH];
+ reg [7:0] rombyte1 [0:MEMDEPTH];
+ reg [7:0] rombyte2 [0:MEMDEPTH];
+ reg [7:0] rombyte3 [0:MEMDEPTH];
+
+ reg [ADDRWIDTH-1:0] addr_r; // registered Address for read access
+
+// optional simulation RAM_INIT option to suppress 'X' initial contents
+`ifdef MEM_INIT
+ reg [7:0] fileimage [((4<<ADDRWIDTH)-1):0];
+ function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction
+ integer fd; // file descriptor for file output
+ integer fd2; // file descriptor for file 2 output
+ integer i;
+ reg [39:0] today [0:1];
+
+initial
+ begin
+ $system("date +%y%m%d%H%M >date_file"); //format yymmdd
+ $readmemh("date_file", today);
+ $display("data_file: %x", today[0]);
+
+ for (i=0; i<= MEMDEPTH; i=i+1) begin
+ rombyte0[i] <= 8'he5;
+ rombyte1[i] <= 8'he5;
+ rombyte2[i] <= 8'he5;
+ rombyte3[i] <= 8'he5;
+ end
+ if (filename != "") begin
+ $readmemh(filename, fileimage);
+ for (i = 0; i <= MEMDEPTH; i=i+1) begin
+ rombyte0[i] <= fileimage[(i<<2)+0];
+ rombyte1[i] <= fileimage[(i<<2)+1];
+ rombyte2[i] <= fileimage[(i<<2)+2];
+ rombyte3[i] <= fileimage[(i<<2)+3];
+ end
+ end
+ if (romgen != 0)
+ begin
+ fd = $fopen(romgenfile);
+ fd2 = $fopen(bingenfile);
+ if ((fd == 0) || (fd2 == 0)) begin
+ $display("rom32gen: Error, zero returned in response to $fopen\n");
+ end
+ else begin
+ $display(fd,"rom32gen: Generating output file\n");
+ $fwrite(fd,"//------------------------------------------------------------------------------------\n");
+ $fwrite(fd,"// customised auto-generated synthesizable ROM module abstraction\n");
+ $fwrite(fd,"// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.\n");
+ $fwrite(fd,"//\n");
+ $fwrite(fd,"// Contributors\n");
+ $fwrite(fd,"//\n");
+ $fwrite(fd,"// David Flynn (d.w.flynn@soton.ac.uk)\n");
+ $fwrite(fd,"// Date: %x\n", today[0]);
+ $fwrite(fd,"// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)\n");
+ $fwrite(fd,"//------------------------------------------------------------------------------------\n");
+ $fwrite(fd,"module bootrom (\n");
+ $fwrite(fd," input wire CLK,\n");
+ $fwrite(fd," input wire EN,\n");
+ $fwrite(fd," input wire [%0d:2] ADDR,\n", ADDRWIDTH+1);
+ $fwrite(fd," output reg [31:0] RDATA );\n");
+ $fwrite(fd,"reg [%0d:2] addr_r;\n", ADDRWIDTH+1);
+ $fwrite(fd,"always @(posedge CLK) if (EN) addr_r <= ADDR;\n");
+ $fwrite(fd,"always @(addr_r)");
+ $fwrite(fd," case(addr_r[%0d:2]) \n", ADDRWIDTH+1);
+ if (ADDRWIDTH > 8)
+ for (i = 0; i < 4 << (ADDRWIDTH); i=i+4) begin
+ $fwrite(fd," %2d'h%3x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i );
+ $fwrite(fd2,"%32b\n",NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}));
+ end
+ else
+ for (i = 0; i < 4 << (ADDRWIDTH); i=i+4) begin
+ $fwrite(fd," %2d'h%2x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i );
+ $fwrite(fd2,"%32b\n",NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}));
+ end
+ $fwrite(fd," default : RDATA <=32'h0;\n");
+ $fwrite(fd," endcase\n");
+ $fwrite(fd,"endmodule\n");
+ $fclose(fd);
+ $fclose(fd2);
+ end
+ end
+ end
+`endif
+
+// synchonous address and control
+
+ always @(posedge CLK) // update on any byte lane read
+ if (SEL)
+ addr_r <= ADDR[ADDRWIDTH-1:0];
+
+ assign RDATA = {rombyte3[addr_r],rombyte2[addr_r],rombyte1[addr_r],rombyte0[addr_r]};
+
+endmodule
diff --git a/GLIB/pads/verilog/GLIB_PADLIB.v b/GLIB/pads/verilog/GLIB_PADLIB.v
new file mode 100755
index 0000000000000000000000000000000000000000..bc10d2b212b1da281703606bffebda2e2b57e292
--- /dev/null
+++ b/GLIB/pads/verilog/GLIB_PADLIB.v
@@ -0,0 +1,139 @@
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ NOE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input NOE;
+
+`ifdef BEHAVIORAL_PADS
+ assign I = PAD;
+ assign PAD = ~NOE ? O : 1'bz;
+`else
+ bufif1 #2 (PAD, O, ~NOE);
+ buf #1 (I, PAD);
+ always @(PAD)
+ begin
+ if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+ $display("%t ++BUS CONFLICT++ : %m", $realtime);
+ end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_NOE
+
+module PAD_INOUT8MA_OE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ OE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input OE;
+`ifdef BEHAVIORAL_PADS
+ assign I = PAD;
+ assign PAD = OE ? O : 1'bz;
+`else
+ bufif1 #2 (PAD, O, OE);
+ buf #1 (I, PAD);
+
+ always @(PAD)
+ begin
+ if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+ $display("%t ++BUS CONFLICT++ : %m", $realtime);
+ end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_OE
+
+module PAD_VDDIO (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VDDIO
+
+module PAD_VSSIO (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VSSSIO
+
+// core logic supply rails (1V0, 0V)
+module PAD_VDDSOC (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VDDSOC
+
+module PAD_VSS (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VSS
+
+// VDDISOL
+module PAD_ANALOG (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_ANALOG
+
+`ifdef TSMC_PADS
+
+// VDDSOC
+module PVDD1CDG (
+ inout wire VDD
+ );
+endmodule // PVDD1CDG
+
+//VDDIO
+module PVDD2CDG (
+ inout wire VDDPST
+ );
+endmodule // PVDD2CDG
+
+module PVDD2POC (
+ inout wire VDDPST
+ );
+endmodule // PVDD2CDG
+
+module PVSS3CDG (
+ inout wire VSS
+ );
+endmodule // PVSS3CDG
+
+// VDDISOL
+module PVDD1ANA (
+ inout wire AVDD
+ );
+endmodule // PVDD1ANA
+
+
+module PCORNER ( ); endmodule
+module PFILLER20 ( ); endmodule
+module PFILLER1 ( ); endmodule
+module PFILLER0005 ( ); endmodule
+
+module PAD60LU ( ); endmodule
+
+`endif
diff --git a/GLIB/pads/verilog/PAD_ANALOG.v b/GLIB/pads/verilog/PAD_ANALOG.v
new file mode 100644
index 0000000000000000000000000000000000000000..2715fb3dbe5a03fcbdc5641d138495b7ce6bcdf3
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_ANALOG.v
@@ -0,0 +1,18 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+// VDDISOL
+module PAD_ANALOG (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_ANALOG
diff --git a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
new file mode 100644
index 0000000000000000000000000000000000000000..42123e8d7ac8f9b825dadceaba8b8019ea0acf0e
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -0,0 +1,39 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ NOE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input NOE;
+
+`ifdef BEHAVIORAL_PADS
+ assign I = PAD;
+ assign PAD = ~NOE ? O : 1'bz;
+`else
+ bufif1 #2 (PAD, O, ~NOE);
+ buf #1 (I, PAD);
+ always @(PAD)
+ begin
+ if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+ $display("%t ++BUS CONFLICT++ : %m", $realtime);
+ end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_NOE
diff --git a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
new file mode 100644
index 0000000000000000000000000000000000000000..12d3009903039b310860a697a0430744825d05a1
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
@@ -0,0 +1,39 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_OE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ OE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input OE;
+`ifdef BEHAVIORAL_PADS
+ assign I = PAD;
+ assign PAD = OE ? O : 1'bz;
+`else
+ bufif1 #2 (PAD, O, OE);
+ buf #1 (I, PAD);
+
+ always @(PAD)
+ begin
+ if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+ $display("%t ++BUS CONFLICT++ : %m", $realtime);
+ end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_OE
diff --git a/GLIB/pads/verilog/PAD_VDDIO.v b/GLIB/pads/verilog/PAD_VDDIO.v
new file mode 100644
index 0000000000000000000000000000000000000000..e8eda5907a536d3ecbbc2e0a2b48d1640f1f6f0b
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_VDDIO.v
@@ -0,0 +1,18 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b1;
+ endmodule // PAD_VDDIO
diff --git a/GLIB/pads/verilog/PAD_VDDSOC.v b/GLIB/pads/verilog/PAD_VDDSOC.v
new file mode 100644
index 0000000000000000000000000000000000000000..02de9e9c8bdc45477849c9c28cc9cc1126742c32
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_VDDSOC.v
@@ -0,0 +1,19 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+// core logic supply rails (1V0, 0V)
+module PAD_VDDSOC (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b1;
+endmodule // PAD_VDDSOC
diff --git a/GLIB/pads/verilog/PAD_VSS.v b/GLIB/pads/verilog/PAD_VSS.v
new file mode 100644
index 0000000000000000000000000000000000000000..ea07cca68af27e30110d1e9352d2bac02557bed4
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_VSS.v
@@ -0,0 +1,18 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b0;
+endmodule // PAD_VSS
diff --git a/GLIB/pads/verilog/PAD_VSSIO.v b/GLIB/pads/verilog/PAD_VSSIO.v
new file mode 100644
index 0000000000000000000000000000000000000000..42d9edbf93686652d35da854b080124a32473132
--- /dev/null
+++ b/GLIB/pads/verilog/PAD_VSSIO.v
@@ -0,0 +1,19 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b0;
+endmodule // PAD_VSSIO
+
diff --git a/IPLIB/ADPcontrol_v1_0/ADPcontrol_adv__mangled.v b/IPLIB/ADPcontrol_v1_0/ADPcontrol_adv__mangled.v
new file mode 100755
index 0000000000000000000000000000000000000000..2699f10d2938e96772c2484350d19f1ea17731b0
--- /dev/null
+++ b/IPLIB/ADPcontrol_v1_0/ADPcontrol_adv__mangled.v
@@ -0,0 +1,7744 @@
+//
+// A joint work commissioned on behalf of SoC Labs.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Obfuscated RTL
+//
+// Copyright (C) 2021-2, SoC Labs (www.soclabs.org)
+//
+
+/*
+ instances: 0
+ nodes: 3002 (0)
+ node widths: 3242 (0)
+ process: 281 (0)
+ contassign: 2769 (0)
+ ports: 27 (0)
+*/
+
+/* Source file "tokens.v", line 14 */
+module ADPcontrol(ahb_hclk, ahb_hresetn, com_rx_tready, com_rx_tdata,
+ com_rx_tvalid, com_tx_tvalid, com_tx_tdata, com_tx_tready,
+ stdio_rx_tready, stdio_rx_tdata, stdio_rx_tvalid, stdio_tx_tvalid,
+ stdio_tx_tdata, stdio_tx_tready, gpo8, gpi8, ahb_haddr, ahb_hburst,
+ ahb_hmastlock, ahb_hprot, ahb_hsize, ahb_htrans, ahb_hwdata, ahb_hwrite,
+ ahb_hrdata, ahb_hready, ahb_hresp);
+
+ input [7:0] com_rx_tdata;
+ output [7:0] com_tx_tdata;
+ input [7:0] stdio_rx_tdata;
+ output [7:0] stdio_tx_tdata;
+ output [7:0] gpo8;
+ input [7:0] gpi8;
+ output [31:0] ahb_haddr;
+ output [2:0] ahb_hburst;
+ output [3:0] ahb_hprot;
+ output [2:0] ahb_hsize;
+ output [1:0] ahb_htrans;
+ output [31:0] ahb_hwdata;
+ input [31:0] ahb_hrdata;
+ input ahb_hclk;
+ input ahb_hresetn;
+ input com_rx_tvalid;
+ input com_tx_tready;
+ input stdio_rx_tvalid;
+ input stdio_tx_tready;
+ input ahb_hready;
+ input ahb_hresp;
+ output com_rx_tready;
+ output com_tx_tvalid;
+ output stdio_rx_tready;
+ output stdio_tx_tvalid;
+ output ahb_hmastlock;
+ output ahb_hwrite;
+
+ wire Xzpfh7;
+ wire O0qfh7;
+ wire F1qfh7;
+ wire W1qfh7;
+ wire N2qfh7;
+ wire E3qfh7;
+ wire V3qfh7;
+ wire M4qfh7;
+ wire D5qfh7;
+ wire U5qfh7;
+ wire L6qfh7;
+ wire C7qfh7;
+ wire T7qfh7;
+ wire K8qfh7;
+ wire B9qfh7;
+ wire S9qfh7;
+ wire Jaqfh7;
+ wire Abqfh7;
+ wire Rbqfh7;
+ wire Icqfh7;
+ wire Zcqfh7;
+ wire Qdqfh7;
+ wire Heqfh7;
+ wire Yeqfh7;
+ wire Pfqfh7;
+ wire Ggqfh7;
+ wire Xgqfh7;
+ wire Ohqfh7;
+ wire Fiqfh7;
+ wire Wiqfh7;
+ wire Njqfh7;
+ wire Ekqfh7;
+ wire Vkqfh7;
+ wire Mlqfh7;
+ wire Dmqfh7;
+ wire Umqfh7;
+ wire Lnqfh7;
+ wire Coqfh7;
+ wire Toqfh7;
+ wire Kpqfh7;
+ wire Bqqfh7;
+ wire Sqqfh7;
+ wire Jrqfh7;
+ wire Asqfh7;
+ wire Rsqfh7;
+ wire Itqfh7;
+ wire Ztqfh7;
+ wire Quqfh7;
+ wire Hvqfh7;
+ wire Yvqfh7;
+ wire Pwqfh7;
+ wire Gxqfh7;
+ wire Xxqfh7;
+ wire Oyqfh7;
+ wire Fzqfh7;
+ wire Wzqfh7;
+ wire N0rfh7;
+ wire E1rfh7;
+ wire V1rfh7;
+ wire M2rfh7;
+ wire D3rfh7;
+ wire U3rfh7;
+ wire L4rfh7;
+ wire C5rfh7;
+ wire T5rfh7;
+ wire K6rfh7;
+ wire B7rfh7;
+ wire S7rfh7;
+ wire J8rfh7;
+ wire A9rfh7;
+ wire R9rfh7;
+ wire Iarfh7;
+ wire Zarfh7;
+ wire Qbrfh7;
+ wire Hcrfh7;
+ wire Ycrfh7;
+ wire Pdrfh7;
+ wire Gerfh7;
+ wire Xerfh7;
+ wire Ofrfh7;
+ wire Fgrfh7;
+ wire Wgrfh7;
+ wire Nhrfh7;
+ wire Eirfh7;
+ wire Virfh7;
+ wire Mjrfh7;
+ wire Dkrfh7;
+ wire Ukrfh7;
+ wire Llrfh7;
+ wire Cmrfh7;
+ wire Tmrfh7;
+ wire Knrfh7;
+ wire Borfh7;
+ wire Sorfh7;
+ wire Jprfh7;
+ wire Aqrfh7;
+ wire Rqrfh7;
+ wire Irrfh7;
+ wire Zrrfh7;
+ wire Qsrfh7;
+ wire Htrfh7;
+ wire Ytrfh7;
+ wire Purfh7;
+ wire Gvrfh7;
+ wire Xvrfh7;
+ wire Owrfh7;
+ wire Fxrfh7;
+ wire Wxrfh7;
+ wire Nyrfh7;
+ wire Ezrfh7;
+ wire Vzrfh7;
+ wire M0sfh7;
+ wire D1sfh7;
+ wire U1sfh7;
+ wire L2sfh7;
+ wire C3sfh7;
+ wire T3sfh7;
+ wire K4sfh7;
+ wire B5sfh7;
+ wire R5sfh7;
+ wire H6sfh7;
+ wire X6sfh7;
+ wire N7sfh7;
+ wire D8sfh7;
+ wire T8sfh7;
+ wire J9sfh7;
+ wire Z9sfh7;
+ wire Pasfh7;
+ wire Fbsfh7;
+ wire Vbsfh7;
+ wire Lcsfh7;
+ wire Bdsfh7;
+ wire Rdsfh7;
+ wire Hesfh7;
+ wire Xesfh7;
+ wire Nfsfh7;
+ wire Dgsfh7;
+ wire Tgsfh7;
+ wire Jhsfh7;
+ wire Zhsfh7;
+ wire Pisfh7;
+ wire Fjsfh7;
+ wire Vjsfh7;
+ wire Lksfh7;
+ wire Blsfh7;
+ wire Rlsfh7;
+ wire Hmsfh7;
+ wire Xmsfh7;
+ wire Nnsfh7;
+ wire Dosfh7;
+ wire Tosfh7;
+ wire Jpsfh7;
+ wire Zpsfh7;
+ wire Pqsfh7;
+ wire Frsfh7;
+ wire Vrsfh7;
+ wire Lssfh7;
+ wire Btsfh7;
+ wire Rtsfh7;
+ wire Husfh7;
+ wire Xusfh7;
+ wire Nvsfh7;
+ wire Dwsfh7;
+ wire Twsfh7;
+ wire Jxsfh7;
+ wire Zxsfh7;
+ wire Pysfh7;
+ wire Fzsfh7;
+ wire Vzsfh7;
+ wire L0tfh7;
+ wire B1tfh7;
+ wire R1tfh7;
+ wire H2tfh7;
+ wire X2tfh7;
+ wire N3tfh7;
+ wire D4tfh7;
+ wire T4tfh7;
+ wire J5tfh7;
+ wire Z5tfh7;
+ wire P6tfh7;
+ wire F7tfh7;
+ wire V7tfh7;
+ wire L8tfh7;
+ wire B9tfh7;
+ wire R9tfh7;
+ wire Patfh7;
+ wire Obtfh7;
+ wire Tbtfh7;
+ wire Ybtfh7;
+ wire Dctfh7;
+ wire Jctfh7;
+ wire Pctfh7;
+ wire Vctfh7;
+ wire Bdtfh7;
+ wire Hdtfh7;
+ wire Ndtfh7;
+ wire Tdtfh7;
+ wire Zdtfh7;
+ wire Fetfh7;
+ wire Letfh7;
+ wire Retfh7;
+ wire Xetfh7;
+ wire Dftfh7;
+ wire Jftfh7;
+ wire Pftfh7;
+ wire Vftfh7;
+ wire Bgtfh7;
+ wire Hgtfh7;
+ wire Ngtfh7;
+ wire Tgtfh7;
+ wire Zgtfh7;
+ wire Fhtfh7;
+ wire Lhtfh7;
+ wire Rhtfh7;
+ wire Xhtfh7;
+ wire Ditfh7;
+ wire Jitfh7;
+ wire Pitfh7;
+ wire Vitfh7;
+ wire Bjtfh7;
+ wire Hjtfh7;
+ wire Njtfh7;
+ wire Tjtfh7;
+ wire Zjtfh7;
+ wire Fktfh7;
+ wire Lktfh7;
+ wire Rktfh7;
+ wire Xktfh7;
+ wire Dltfh7;
+ wire Jltfh7;
+ wire Pltfh7;
+ wire Vltfh7;
+ wire Bmtfh7;
+ wire Hmtfh7;
+ wire Nmtfh7;
+ wire Tmtfh7;
+ wire Zmtfh7;
+ wire Fntfh7;
+ wire Lntfh7;
+ wire Rntfh7;
+ wire Xntfh7;
+ wire Dotfh7;
+ wire Jotfh7;
+ wire Potfh7;
+ wire Votfh7;
+ wire Bptfh7;
+ wire Hptfh7;
+ wire Nptfh7;
+ wire Tptfh7;
+ wire Zptfh7;
+ wire Fqtfh7;
+ wire Lqtfh7;
+ wire Rqtfh7;
+ wire Xqtfh7;
+ wire Drtfh7;
+ wire Jrtfh7;
+ wire Prtfh7;
+ wire Vrtfh7;
+ wire Bstfh7;
+ wire Hstfh7;
+ wire Nstfh7;
+ wire Tstfh7;
+ wire Zstfh7;
+ wire Fttfh7;
+ wire Lttfh7;
+ wire Rttfh7;
+ wire Xttfh7;
+ wire Dutfh7;
+ wire Jutfh7;
+ wire Putfh7;
+ wire Vutfh7;
+ wire Bvtfh7;
+ wire Hvtfh7;
+ wire Nvtfh7;
+ wire Tvtfh7;
+ wire Zvtfh7;
+ wire Fwtfh7;
+ wire Lwtfh7;
+ wire Rwtfh7;
+ wire Xwtfh7;
+ wire Dxtfh7;
+ wire Jxtfh7;
+ wire Pxtfh7;
+ wire Vxtfh7;
+ wire Bytfh7;
+ wire Hytfh7;
+ wire Nytfh7;
+ wire Tytfh7;
+ wire Zytfh7;
+ wire Fztfh7;
+ wire Lztfh7;
+ wire Rztfh7;
+ wire Xztfh7;
+ wire D0ufh7;
+ wire J0ufh7;
+ wire P0ufh7;
+ wire V0ufh7;
+ wire B1ufh7;
+ wire H1ufh7;
+ wire N1ufh7;
+ wire T1ufh7;
+ wire Z1ufh7;
+ wire F2ufh7;
+ wire L2ufh7;
+ wire R2ufh7;
+ wire X2ufh7;
+ wire D3ufh7;
+ wire J3ufh7;
+ wire P3ufh7;
+ wire V3ufh7;
+ wire B4ufh7;
+ wire H4ufh7;
+ wire N4ufh7;
+ wire T4ufh7;
+ wire Z4ufh7;
+ wire F5ufh7;
+ wire L5ufh7;
+ wire R5ufh7;
+ wire X5ufh7;
+ wire D6ufh7;
+ wire J6ufh7;
+ wire P6ufh7;
+ wire V6ufh7;
+ wire B7ufh7;
+ wire H7ufh7;
+ wire N7ufh7;
+ wire T7ufh7;
+ wire Z7ufh7;
+ wire F8ufh7;
+ wire L8ufh7;
+ wire R8ufh7;
+ wire X8ufh7;
+ wire D9ufh7;
+ wire J9ufh7;
+ wire P9ufh7;
+ wire V9ufh7;
+ wire Baufh7;
+ wire Haufh7;
+ wire Naufh7;
+ wire Taufh7;
+ wire Zaufh7;
+ wire Fbufh7;
+ wire Lbufh7;
+ wire Rbufh7;
+ wire Xbufh7;
+ wire Dcufh7;
+ wire Jcufh7;
+ wire Pcufh7;
+ wire Vcufh7;
+ wire Bdufh7;
+ wire Hdufh7;
+ wire Ndufh7;
+ wire Tdufh7;
+ wire Zdufh7;
+ wire Feufh7;
+ wire Leufh7;
+ wire Reufh7;
+ wire Xeufh7;
+ wire Dfufh7;
+ wire Jfufh7;
+ wire Pfufh7;
+ wire Vfufh7;
+ wire Bgufh7;
+ wire Hgufh7;
+ wire Ngufh7;
+ wire Tgufh7;
+ wire Zgufh7;
+ wire Fhufh7;
+ wire Lhufh7;
+ wire Rhufh7;
+ wire Xhufh7;
+ wire Diufh7;
+ wire Jiufh7;
+ wire Piufh7;
+ wire Viufh7;
+ wire Bjufh7;
+ wire Hjufh7;
+ wire Njufh7;
+ wire Tjufh7;
+ wire Zjufh7;
+ wire Fkufh7;
+ wire Lkufh7;
+ wire Rkufh7;
+ wire Xkufh7;
+ wire Dlufh7;
+ wire Jlufh7;
+ wire Plufh7;
+ wire Vlufh7;
+ wire Bmufh7;
+ wire Hmufh7;
+ wire Nmufh7;
+ wire Tmufh7;
+ wire Zmufh7;
+ wire Fnufh7;
+ wire Lnufh7;
+ wire Rnufh7;
+ wire Xnufh7;
+ wire Doufh7;
+ wire Joufh7;
+ wire Poufh7;
+ wire Voufh7;
+ wire Bpufh7;
+ wire Hpufh7;
+ wire Npufh7;
+ wire Tpufh7;
+ wire Zpufh7;
+ wire Fqufh7;
+ wire Lqufh7;
+ wire Rqufh7;
+ wire Xqufh7;
+ wire Drufh7;
+ wire Jrufh7;
+ wire Prufh7;
+ wire Vrufh7;
+ wire Bsufh7;
+ wire Hsufh7;
+ wire Nsufh7;
+ wire Tsufh7;
+ wire Zsufh7;
+ wire Ftufh7;
+ wire Ltufh7;
+ wire Rtufh7;
+ wire Xtufh7;
+ wire Duufh7;
+ wire Juufh7;
+ wire Puufh7;
+ wire Vuufh7;
+ wire Bvufh7;
+ wire Hvufh7;
+ wire Nvufh7;
+ wire Tvufh7;
+ wire Zvufh7;
+ wire Fwufh7;
+ wire Lwufh7;
+ wire Rwufh7;
+ wire Xwufh7;
+ wire Dxufh7;
+ wire Jxufh7;
+ wire Pxufh7;
+ wire Vxufh7;
+ wire Byufh7;
+ wire Hyufh7;
+ wire Nyufh7;
+ wire Tyufh7;
+ wire Zyufh7;
+ wire Fzufh7;
+ wire Lzufh7;
+ wire Rzufh7;
+ wire Xzufh7;
+ wire D0vfh7;
+ wire J0vfh7;
+ wire P0vfh7;
+ wire V0vfh7;
+ wire B1vfh7;
+ wire H1vfh7;
+ wire N1vfh7;
+ wire T1vfh7;
+ wire Z1vfh7;
+ wire F2vfh7;
+ wire L2vfh7;
+ wire R2vfh7;
+ wire X2vfh7;
+ wire D3vfh7;
+ wire J3vfh7;
+ wire P3vfh7;
+ wire V3vfh7;
+ wire B4vfh7;
+ wire H4vfh7;
+ wire N4vfh7;
+ wire T4vfh7;
+ wire Z4vfh7;
+ wire F5vfh7;
+ wire L5vfh7;
+ wire R5vfh7;
+ wire X5vfh7;
+ wire D6vfh7;
+ wire J6vfh7;
+ wire P6vfh7;
+ wire V6vfh7;
+ wire B7vfh7;
+ wire H7vfh7;
+ wire N7vfh7;
+ wire T7vfh7;
+ wire Z7vfh7;
+ wire F8vfh7;
+ wire L8vfh7;
+ wire R8vfh7;
+ wire X8vfh7;
+ wire D9vfh7;
+ wire J9vfh7;
+ wire P9vfh7;
+ wire V9vfh7;
+ wire Bavfh7;
+ wire Havfh7;
+ wire Navfh7;
+ wire Tavfh7;
+ wire Zavfh7;
+ wire Fbvfh7;
+ wire Lbvfh7;
+ wire Rbvfh7;
+ wire Xbvfh7;
+ wire Dcvfh7;
+ wire Jcvfh7;
+ wire Pcvfh7;
+ wire Vcvfh7;
+ wire Bdvfh7;
+ wire Hdvfh7;
+ wire Ndvfh7;
+ wire Tdvfh7;
+ wire Zdvfh7;
+ wire Fevfh7;
+ wire Levfh7;
+ wire Revfh7;
+ wire Xevfh7;
+ wire Dfvfh7;
+ wire Jfvfh7;
+ wire Pfvfh7;
+ wire Vfvfh7;
+ wire Bgvfh7;
+ wire Hgvfh7;
+ wire Ngvfh7;
+ wire Tgvfh7;
+ wire Zgvfh7;
+ wire Fhvfh7;
+ wire Lhvfh7;
+ wire Rhvfh7;
+ wire Xhvfh7;
+ wire Divfh7;
+ wire Jivfh7;
+ wire Pivfh7;
+ wire Vivfh7;
+ wire Bjvfh7;
+ wire Hjvfh7;
+ wire Njvfh7;
+ wire Tjvfh7;
+ wire Zjvfh7;
+ wire Fkvfh7;
+ wire Lkvfh7;
+ wire Rkvfh7;
+ wire Xkvfh7;
+ wire Dlvfh7;
+ wire Jlvfh7;
+ wire Plvfh7;
+ wire Vlvfh7;
+ wire Bmvfh7;
+ wire Hmvfh7;
+ wire Nmvfh7;
+ wire Tmvfh7;
+ wire Zmvfh7;
+ wire Fnvfh7;
+ wire Lnvfh7;
+ wire Rnvfh7;
+ wire Xnvfh7;
+ wire Dovfh7;
+ wire Jovfh7;
+ wire Povfh7;
+ wire Vovfh7;
+ wire Bpvfh7;
+ wire Hpvfh7;
+ wire Npvfh7;
+ wire Tpvfh7;
+ wire Zpvfh7;
+ wire Fqvfh7;
+ wire Lqvfh7;
+ wire Rqvfh7;
+ wire Xqvfh7;
+ wire Drvfh7;
+ wire Jrvfh7;
+ wire Prvfh7;
+ wire Vrvfh7;
+ wire Bsvfh7;
+ wire Hsvfh7;
+ wire Nsvfh7;
+ wire Tsvfh7;
+ wire Zsvfh7;
+ wire Ftvfh7;
+ wire Ltvfh7;
+ wire Rtvfh7;
+ wire Xtvfh7;
+ wire Duvfh7;
+ wire Juvfh7;
+ wire Puvfh7;
+ wire Vuvfh7;
+ wire Bvvfh7;
+ wire Hvvfh7;
+ wire Nvvfh7;
+ wire Tvvfh7;
+ wire Zvvfh7;
+ wire Fwvfh7;
+ wire Lwvfh7;
+ wire Rwvfh7;
+ wire Xwvfh7;
+ wire Dxvfh7;
+ wire Jxvfh7;
+ wire Pxvfh7;
+ wire Vxvfh7;
+ wire Byvfh7;
+ wire Hyvfh7;
+ wire Nyvfh7;
+ wire Tyvfh7;
+ wire Zyvfh7;
+ wire Fzvfh7;
+ wire Lzvfh7;
+ wire Rzvfh7;
+ wire Xzvfh7;
+ wire D0wfh7;
+ wire J0wfh7;
+ wire P0wfh7;
+ wire V0wfh7;
+ wire B1wfh7;
+ wire H1wfh7;
+ wire N1wfh7;
+ wire T1wfh7;
+ wire Z1wfh7;
+ wire F2wfh7;
+ wire L2wfh7;
+ wire R2wfh7;
+ wire X2wfh7;
+ wire D3wfh7;
+ wire J3wfh7;
+ wire P3wfh7;
+ wire V3wfh7;
+ wire B4wfh7;
+ wire H4wfh7;
+ wire N4wfh7;
+ wire T4wfh7;
+ wire Z4wfh7;
+ wire F5wfh7;
+ wire L5wfh7;
+ wire R5wfh7;
+ wire X5wfh7;
+ wire D6wfh7;
+ wire J6wfh7;
+ wire P6wfh7;
+ wire V6wfh7;
+ wire B7wfh7;
+ wire H7wfh7;
+ wire N7wfh7;
+ wire T7wfh7;
+ wire Z7wfh7;
+ wire F8wfh7;
+ wire L8wfh7;
+ wire R8wfh7;
+ wire X8wfh7;
+ wire D9wfh7;
+ wire J9wfh7;
+ wire P9wfh7;
+ wire V9wfh7;
+ wire Bawfh7;
+ wire Hawfh7;
+ wire Nawfh7;
+ wire Tawfh7;
+ wire Zawfh7;
+ wire Fbwfh7;
+ wire Lbwfh7;
+ wire Rbwfh7;
+ wire Xbwfh7;
+ wire Dcwfh7;
+ wire Jcwfh7;
+ wire Pcwfh7;
+ wire Vcwfh7;
+ wire Bdwfh7;
+ wire Hdwfh7;
+ wire Ndwfh7;
+ wire Tdwfh7;
+ wire Zdwfh7;
+ wire Fewfh7;
+ wire Lewfh7;
+ wire Rewfh7;
+ wire Xewfh7;
+ wire Dfwfh7;
+ wire Jfwfh7;
+ wire Pfwfh7;
+ wire Vfwfh7;
+ wire Bgwfh7;
+ wire Hgwfh7;
+ wire Ngwfh7;
+ wire Tgwfh7;
+ wire Zgwfh7;
+ wire Fhwfh7;
+ wire Lhwfh7;
+ wire Rhwfh7;
+ wire Xhwfh7;
+ wire Diwfh7;
+ wire Jiwfh7;
+ wire Piwfh7;
+ wire Viwfh7;
+ wire Bjwfh7;
+ wire Hjwfh7;
+ wire Njwfh7;
+ wire Tjwfh7;
+ wire Zjwfh7;
+ wire Fkwfh7;
+ wire Lkwfh7;
+ wire Rkwfh7;
+ wire Xkwfh7;
+ wire Dlwfh7;
+ wire Jlwfh7;
+ wire Plwfh7;
+ wire Vlwfh7;
+ wire Bmwfh7;
+ wire Hmwfh7;
+ wire Nmwfh7;
+ wire Tmwfh7;
+ wire Zmwfh7;
+ wire Fnwfh7;
+ wire Lnwfh7;
+ wire Rnwfh7;
+ wire Xnwfh7;
+ wire Dowfh7;
+ wire Jowfh7;
+ wire Powfh7;
+ wire Vowfh7;
+ wire Bpwfh7;
+ wire Hpwfh7;
+ wire Npwfh7;
+ wire Tpwfh7;
+ wire Zpwfh7;
+ wire Fqwfh7;
+ wire Lqwfh7;
+ wire Rqwfh7;
+ wire Xqwfh7;
+ wire Drwfh7;
+ wire Jrwfh7;
+ wire Prwfh7;
+ wire Vrwfh7;
+ wire Bswfh7;
+ wire Hswfh7;
+ wire Nswfh7;
+ wire Tswfh7;
+ wire Zswfh7;
+ wire Ftwfh7;
+ wire Ltwfh7;
+ wire Rtwfh7;
+ wire Xtwfh7;
+ wire Duwfh7;
+ wire Juwfh7;
+ wire Puwfh7;
+ wire Vuwfh7;
+ wire Bvwfh7;
+ wire Hvwfh7;
+ wire Nvwfh7;
+ wire Tvwfh7;
+ wire Zvwfh7;
+ wire Fwwfh7;
+ wire Lwwfh7;
+ wire Rwwfh7;
+ wire Xwwfh7;
+ wire Dxwfh7;
+ wire Jxwfh7;
+ wire Pxwfh7;
+ wire Vxwfh7;
+ wire Bywfh7;
+ wire Hywfh7;
+ wire Nywfh7;
+ wire Tywfh7;
+ wire Zywfh7;
+ wire Fzwfh7;
+ wire Lzwfh7;
+ wire Rzwfh7;
+ wire Xzwfh7;
+ wire D0xfh7;
+ wire J0xfh7;
+ wire P0xfh7;
+ wire V0xfh7;
+ wire B1xfh7;
+ wire H1xfh7;
+ wire N1xfh7;
+ wire T1xfh7;
+ wire Z1xfh7;
+ wire F2xfh7;
+ wire L2xfh7;
+ wire R2xfh7;
+ wire X2xfh7;
+ wire D3xfh7;
+ wire J3xfh7;
+ wire P3xfh7;
+ wire V3xfh7;
+ wire B4xfh7;
+ wire H4xfh7;
+ wire N4xfh7;
+ wire T4xfh7;
+ wire Z4xfh7;
+ wire F5xfh7;
+ wire L5xfh7;
+ wire R5xfh7;
+ wire X5xfh7;
+ wire D6xfh7;
+ wire J6xfh7;
+ wire P6xfh7;
+ wire V6xfh7;
+ wire B7xfh7;
+ wire H7xfh7;
+ wire N7xfh7;
+ wire T7xfh7;
+ wire Z7xfh7;
+ wire F8xfh7;
+ wire L8xfh7;
+ wire R8xfh7;
+ wire X8xfh7;
+ wire D9xfh7;
+ wire J9xfh7;
+ wire P9xfh7;
+ wire V9xfh7;
+ wire Baxfh7;
+ wire Haxfh7;
+ wire Naxfh7;
+ wire Taxfh7;
+ wire Zaxfh7;
+ wire Fbxfh7;
+ wire Lbxfh7;
+ wire Rbxfh7;
+ wire Xbxfh7;
+ wire Dcxfh7;
+ wire Jcxfh7;
+ wire Pcxfh7;
+ wire Vcxfh7;
+ wire Bdxfh7;
+ wire Hdxfh7;
+ wire Ndxfh7;
+ wire Tdxfh7;
+ wire Zdxfh7;
+ wire Fexfh7;
+ wire Lexfh7;
+ wire Rexfh7;
+ wire Xexfh7;
+ wire Dfxfh7;
+ wire Jfxfh7;
+ wire Pfxfh7;
+ wire Vfxfh7;
+ wire Bgxfh7;
+ wire Hgxfh7;
+ wire Ngxfh7;
+ wire Tgxfh7;
+ wire Zgxfh7;
+ wire Fhxfh7;
+ wire Lhxfh7;
+ wire Rhxfh7;
+ wire Xhxfh7;
+ wire Dixfh7;
+ wire Jixfh7;
+ wire Pixfh7;
+ wire Vixfh7;
+ wire Bjxfh7;
+ wire Hjxfh7;
+ wire Njxfh7;
+ wire Tjxfh7;
+ wire Zjxfh7;
+ wire Fkxfh7;
+ wire Lkxfh7;
+ wire Rkxfh7;
+ wire Xkxfh7;
+ wire Dlxfh7;
+ wire Jlxfh7;
+ wire Plxfh7;
+ wire Vlxfh7;
+ wire Bmxfh7;
+ wire Hmxfh7;
+ wire Nmxfh7;
+ wire Tmxfh7;
+ wire Zmxfh7;
+ wire Fnxfh7;
+ wire Lnxfh7;
+ wire Rnxfh7;
+ wire Xnxfh7;
+ wire Doxfh7;
+ wire Joxfh7;
+ wire Poxfh7;
+ wire Voxfh7;
+ wire Bpxfh7;
+ wire Hpxfh7;
+ wire Npxfh7;
+ wire Tpxfh7;
+ wire Zpxfh7;
+ wire Fqxfh7;
+ wire Lqxfh7;
+ wire Rqxfh7;
+ wire Xqxfh7;
+ wire Drxfh7;
+ wire Jrxfh7;
+ wire Prxfh7;
+ wire Vrxfh7;
+ wire Bsxfh7;
+ wire Hsxfh7;
+ wire Nsxfh7;
+ wire Tsxfh7;
+ wire Zsxfh7;
+ wire Ftxfh7;
+ wire Ltxfh7;
+ wire Rtxfh7;
+ wire Xtxfh7;
+ wire Duxfh7;
+ wire Juxfh7;
+ wire Puxfh7;
+ wire Vuxfh7;
+ wire Bvxfh7;
+ wire Hvxfh7;
+ wire Nvxfh7;
+ wire Tvxfh7;
+ wire Zvxfh7;
+ wire Fwxfh7;
+ wire Lwxfh7;
+ wire Rwxfh7;
+ wire Xwxfh7;
+ wire Dxxfh7;
+ wire Jxxfh7;
+ wire Pxxfh7;
+ wire Vxxfh7;
+ wire Byxfh7;
+ wire Hyxfh7;
+ wire Nyxfh7;
+ wire Tyxfh7;
+ wire Zyxfh7;
+ wire Fzxfh7;
+ wire Lzxfh7;
+ wire Rzxfh7;
+ wire Xzxfh7;
+ wire D0yfh7;
+ wire J0yfh7;
+ wire P0yfh7;
+ wire V0yfh7;
+ wire B1yfh7;
+ wire H1yfh7;
+ wire N1yfh7;
+ wire T1yfh7;
+ wire Z1yfh7;
+ wire F2yfh7;
+ wire L2yfh7;
+ wire R2yfh7;
+ wire X2yfh7;
+ wire D3yfh7;
+ wire J3yfh7;
+ wire P3yfh7;
+ wire V3yfh7;
+ wire B4yfh7;
+ wire H4yfh7;
+ wire N4yfh7;
+ wire T4yfh7;
+ wire Z4yfh7;
+ wire F5yfh7;
+ wire L5yfh7;
+ wire R5yfh7;
+ wire X5yfh7;
+ wire D6yfh7;
+ wire J6yfh7;
+ wire P6yfh7;
+ wire V6yfh7;
+ wire B7yfh7;
+ wire H7yfh7;
+ wire N7yfh7;
+ wire T7yfh7;
+ wire Z7yfh7;
+ wire F8yfh7;
+ wire L8yfh7;
+ wire R8yfh7;
+ wire X8yfh7;
+ wire D9yfh7;
+ wire J9yfh7;
+ wire P9yfh7;
+ wire V9yfh7;
+ wire Bayfh7;
+ wire Hayfh7;
+ wire Nayfh7;
+ wire Tayfh7;
+ wire Zayfh7;
+ wire Fbyfh7;
+ wire Lbyfh7;
+ wire Rbyfh7;
+ wire Xbyfh7;
+ wire Dcyfh7;
+ wire Jcyfh7;
+ wire Pcyfh7;
+ wire Vcyfh7;
+ wire Bdyfh7;
+ wire Hdyfh7;
+ wire Ndyfh7;
+ wire Tdyfh7;
+ wire Zdyfh7;
+ wire Feyfh7;
+ wire Leyfh7;
+ wire Reyfh7;
+ wire Xeyfh7;
+ wire Dfyfh7;
+ wire Jfyfh7;
+ wire Pfyfh7;
+ wire Vfyfh7;
+ wire Bgyfh7;
+ wire Hgyfh7;
+ wire Ngyfh7;
+ wire Tgyfh7;
+ wire Zgyfh7;
+ wire Fhyfh7;
+ wire Lhyfh7;
+ wire Rhyfh7;
+ wire Xhyfh7;
+ wire Diyfh7;
+ wire Jiyfh7;
+ wire Piyfh7;
+ wire Viyfh7;
+ wire Bjyfh7;
+ wire Hjyfh7;
+ wire Njyfh7;
+ wire Tjyfh7;
+ wire Zjyfh7;
+ wire Fkyfh7;
+ wire Lkyfh7;
+ wire Rkyfh7;
+ wire Xkyfh7;
+ wire Dlyfh7;
+ wire Jlyfh7;
+ wire Plyfh7;
+ wire Vlyfh7;
+ wire Bmyfh7;
+ wire Hmyfh7;
+ wire Nmyfh7;
+ wire Tmyfh7;
+ wire Zmyfh7;
+ wire Fnyfh7;
+ wire Lnyfh7;
+ wire Rnyfh7;
+ wire Xnyfh7;
+ wire Doyfh7;
+ wire Joyfh7;
+ wire Poyfh7;
+ wire Voyfh7;
+ wire Bpyfh7;
+ wire Hpyfh7;
+ wire Npyfh7;
+ wire Tpyfh7;
+ wire Zpyfh7;
+ wire Fqyfh7;
+ wire Lqyfh7;
+ wire Rqyfh7;
+ wire Xqyfh7;
+ wire Dryfh7;
+ wire Jryfh7;
+ wire Pryfh7;
+ wire Vryfh7;
+ wire Bsyfh7;
+ wire Hsyfh7;
+ wire Nsyfh7;
+ wire Tsyfh7;
+ wire Zsyfh7;
+ wire Ftyfh7;
+ wire Ltyfh7;
+ wire Rtyfh7;
+ wire Xtyfh7;
+ wire Duyfh7;
+ wire Juyfh7;
+ wire Puyfh7;
+ wire Vuyfh7;
+ wire Bvyfh7;
+ wire Hvyfh7;
+ wire Nvyfh7;
+ wire Tvyfh7;
+ wire Zvyfh7;
+ wire Fwyfh7;
+ wire Lwyfh7;
+ wire Rwyfh7;
+ wire Xwyfh7;
+ wire Dxyfh7;
+ wire Jxyfh7;
+ wire Pxyfh7;
+ wire Vxyfh7;
+ wire Byyfh7;
+ wire Hyyfh7;
+ wire Nyyfh7;
+ wire Tyyfh7;
+ wire Zyyfh7;
+ wire Fzyfh7;
+ wire Lzyfh7;
+ wire Rzyfh7;
+ wire Xzyfh7;
+ wire D0zfh7;
+ wire J0zfh7;
+ wire P0zfh7;
+ wire V0zfh7;
+ wire B1zfh7;
+ wire H1zfh7;
+ wire N1zfh7;
+ wire T1zfh7;
+ wire Z1zfh7;
+ wire F2zfh7;
+ wire L2zfh7;
+ wire R2zfh7;
+ wire X2zfh7;
+ wire D3zfh7;
+ wire J3zfh7;
+ wire P3zfh7;
+ wire V3zfh7;
+ wire B4zfh7;
+ wire H4zfh7;
+ wire N4zfh7;
+ wire T4zfh7;
+ wire Z4zfh7;
+ wire F5zfh7;
+ wire L5zfh7;
+ wire R5zfh7;
+ wire X5zfh7;
+ wire D6zfh7;
+ wire J6zfh7;
+ wire P6zfh7;
+ wire V6zfh7;
+ wire B7zfh7;
+ wire H7zfh7;
+ wire N7zfh7;
+ wire T7zfh7;
+ wire Z7zfh7;
+ wire F8zfh7;
+ wire L8zfh7;
+ wire R8zfh7;
+ wire X8zfh7;
+ wire D9zfh7;
+ wire J9zfh7;
+ wire P9zfh7;
+ wire V9zfh7;
+ wire Bazfh7;
+ wire Hazfh7;
+ wire Nazfh7;
+ wire Tazfh7;
+ wire Zazfh7;
+ wire Fbzfh7;
+ wire Lbzfh7;
+ wire Rbzfh7;
+ wire Xbzfh7;
+ wire Dczfh7;
+ wire Jczfh7;
+ wire Pczfh7;
+ wire Vczfh7;
+ wire Bdzfh7;
+ wire Hdzfh7;
+ wire Ndzfh7;
+ wire Tdzfh7;
+ wire Zdzfh7;
+ wire Fezfh7;
+ wire Lezfh7;
+ wire Rezfh7;
+ wire Xezfh7;
+ wire Dfzfh7;
+ wire Jfzfh7;
+ wire Pfzfh7;
+ wire Vfzfh7;
+ wire Bgzfh7;
+ wire Hgzfh7;
+ wire Ngzfh7;
+ wire Tgzfh7;
+ wire Zgzfh7;
+ wire Fhzfh7;
+ wire Lhzfh7;
+ wire Rhzfh7;
+ wire Xhzfh7;
+ wire Dizfh7;
+ wire Jizfh7;
+ wire Pizfh7;
+ wire Vizfh7;
+ wire Bjzfh7;
+ wire Hjzfh7;
+ wire Njzfh7;
+ wire Tjzfh7;
+ wire Zjzfh7;
+ wire Fkzfh7;
+ wire Lkzfh7;
+ wire Rkzfh7;
+ wire Xkzfh7;
+ wire Dlzfh7;
+ wire Jlzfh7;
+ wire Plzfh7;
+ wire Vlzfh7;
+ wire Bmzfh7;
+ wire Hmzfh7;
+ wire Nmzfh7;
+ wire Tmzfh7;
+ wire Zmzfh7;
+ wire Fnzfh7;
+ wire Lnzfh7;
+ wire Rnzfh7;
+ wire Xnzfh7;
+ wire Dozfh7;
+ wire Jozfh7;
+ wire Pozfh7;
+ wire Vozfh7;
+ wire Bpzfh7;
+ wire Hpzfh7;
+ wire Npzfh7;
+ wire Tpzfh7;
+ wire Zpzfh7;
+ wire Fqzfh7;
+ wire Lqzfh7;
+ wire Rqzfh7;
+ wire Xqzfh7;
+ wire Drzfh7;
+ wire Jrzfh7;
+ wire Przfh7;
+ wire Vrzfh7;
+ wire Bszfh7;
+ wire Hszfh7;
+ wire Nszfh7;
+ wire Tszfh7;
+ wire Zszfh7;
+ wire Ftzfh7;
+ wire Ltzfh7;
+ wire Rtzfh7;
+ wire Xtzfh7;
+ wire Duzfh7;
+ wire Juzfh7;
+ wire Puzfh7;
+ wire Vuzfh7;
+ wire Bvzfh7;
+ wire Hvzfh7;
+ wire Nvzfh7;
+ wire Tvzfh7;
+ wire Zvzfh7;
+ wire Fwzfh7;
+ wire Lwzfh7;
+ wire Rwzfh7;
+ wire Xwzfh7;
+ wire Dxzfh7;
+ wire Jxzfh7;
+ wire Pxzfh7;
+ wire Vxzfh7;
+ wire Byzfh7;
+ wire Hyzfh7;
+ wire Nyzfh7;
+ wire Tyzfh7;
+ wire Zyzfh7;
+ wire Fzzfh7;
+ wire Lzzfh7;
+ wire Rzzfh7;
+ wire Xzzfh7;
+ wire D00gh7;
+ wire J00gh7;
+ wire P00gh7;
+ wire V00gh7;
+ wire B10gh7;
+ wire H10gh7;
+ wire N10gh7;
+ wire T10gh7;
+ wire Z10gh7;
+ wire F20gh7;
+ wire L20gh7;
+ wire R20gh7;
+ wire X20gh7;
+ wire D30gh7;
+ wire J30gh7;
+ wire P30gh7;
+ wire V30gh7;
+ wire B40gh7;
+ wire H40gh7;
+ wire N40gh7;
+ wire T40gh7;
+ wire Z40gh7;
+ wire F50gh7;
+ wire L50gh7;
+ wire R50gh7;
+ wire X50gh7;
+ wire D60gh7;
+ wire J60gh7;
+ wire P60gh7;
+ wire V60gh7;
+ wire B70gh7;
+ wire H70gh7;
+ wire N70gh7;
+ wire T70gh7;
+ wire Z70gh7;
+ wire F80gh7;
+ wire L80gh7;
+ wire R80gh7;
+ wire X80gh7;
+ wire D90gh7;
+ wire J90gh7;
+ wire P90gh7;
+ wire V90gh7;
+ wire Ba0gh7;
+ wire Ha0gh7;
+ wire Na0gh7;
+ wire Ta0gh7;
+ wire Za0gh7;
+ wire Fb0gh7;
+ wire Lb0gh7;
+ wire Rb0gh7;
+ wire Xb0gh7;
+ wire Dc0gh7;
+ wire Jc0gh7;
+ wire Pc0gh7;
+ wire Vc0gh7;
+ wire Bd0gh7;
+ wire Hd0gh7;
+ wire Nd0gh7;
+ wire Td0gh7;
+ wire Zd0gh7;
+ wire Fe0gh7;
+ wire Le0gh7;
+ wire Re0gh7;
+ wire Xe0gh7;
+ wire Df0gh7;
+ wire Jf0gh7;
+ wire Pf0gh7;
+ wire Vf0gh7;
+ wire Bg0gh7;
+ wire Hg0gh7;
+ wire Ng0gh7;
+ wire Tg0gh7;
+ wire Zg0gh7;
+ wire Fh0gh7;
+ wire Lh0gh7;
+ wire Rh0gh7;
+ wire Xh0gh7;
+ wire Di0gh7;
+ wire Ji0gh7;
+ wire Pi0gh7;
+ wire Vi0gh7;
+ wire Bj0gh7;
+ wire Hj0gh7;
+ wire Nj0gh7;
+ wire Tj0gh7;
+ wire Zj0gh7;
+ wire Fk0gh7;
+ wire Lk0gh7;
+ wire Rk0gh7;
+ wire Xk0gh7;
+ wire Dl0gh7;
+ wire Jl0gh7;
+ wire Pl0gh7;
+ wire Vl0gh7;
+ wire Bm0gh7;
+ wire Hm0gh7;
+ wire Nm0gh7;
+ wire Tm0gh7;
+ wire Zm0gh7;
+ wire Fn0gh7;
+ wire Ln0gh7;
+ wire Rn0gh7;
+ wire Xn0gh7;
+ wire Do0gh7;
+ wire Jo0gh7;
+ wire Po0gh7;
+ wire Vo0gh7;
+ wire Bp0gh7;
+ wire Hp0gh7;
+ wire Np0gh7;
+ wire Tp0gh7;
+ wire Zp0gh7;
+ wire Fq0gh7;
+ wire Lq0gh7;
+ wire Rq0gh7;
+ wire Xq0gh7;
+ wire Dr0gh7;
+ wire Jr0gh7;
+ wire Pr0gh7;
+ wire Vr0gh7;
+ wire Bs0gh7;
+ wire Hs0gh7;
+ wire Ns0gh7;
+ wire Ts0gh7;
+ wire Zs0gh7;
+ wire Ft0gh7;
+ wire Lt0gh7;
+ wire Rt0gh7;
+ wire Xt0gh7;
+ wire Du0gh7;
+ wire Ju0gh7;
+ wire Pu0gh7;
+ wire Vu0gh7;
+ wire Bv0gh7;
+ wire Hv0gh7;
+ wire Nv0gh7;
+ wire Tv0gh7;
+ wire Zv0gh7;
+ wire Fw0gh7;
+ wire Lw0gh7;
+ wire Rw0gh7;
+ wire Xw0gh7;
+ wire Dx0gh7;
+ wire Jx0gh7;
+ wire Px0gh7;
+ wire Vx0gh7;
+ wire By0gh7;
+ wire Hy0gh7;
+ wire Ny0gh7;
+ wire Ty0gh7;
+ wire Zy0gh7;
+ wire Fz0gh7;
+ wire Lz0gh7;
+ wire Rz0gh7;
+ wire Xz0gh7;
+ wire D01gh7;
+ wire J01gh7;
+ wire P01gh7;
+ wire V01gh7;
+ wire B11gh7;
+ wire H11gh7;
+ wire N11gh7;
+ wire T11gh7;
+ wire Z11gh7;
+ wire F21gh7;
+ wire L21gh7;
+ wire R21gh7;
+ wire X21gh7;
+ wire D31gh7;
+ wire J31gh7;
+ wire P31gh7;
+ wire V31gh7;
+ wire B41gh7;
+ wire H41gh7;
+ wire N41gh7;
+ wire T41gh7;
+ wire Z41gh7;
+ wire F51gh7;
+ wire L51gh7;
+ wire R51gh7;
+ wire X51gh7;
+ wire D61gh7;
+ wire J61gh7;
+ wire P61gh7;
+ wire V61gh7;
+ wire B71gh7;
+ wire H71gh7;
+ wire N71gh7;
+ wire T71gh7;
+ wire Z71gh7;
+ wire F81gh7;
+ wire L81gh7;
+ wire R81gh7;
+ wire X81gh7;
+ wire D91gh7;
+ wire J91gh7;
+ wire P91gh7;
+ wire V91gh7;
+ wire Ba1gh7;
+ wire Ha1gh7;
+ wire Na1gh7;
+ wire Ta1gh7;
+ wire Za1gh7;
+ wire Fb1gh7;
+ wire Lb1gh7;
+ wire Rb1gh7;
+ wire Xb1gh7;
+ wire Dc1gh7;
+ wire Jc1gh7;
+ wire Pc1gh7;
+ wire Vc1gh7;
+ wire Bd1gh7;
+ wire Hd1gh7;
+ wire Nd1gh7;
+ wire Td1gh7;
+ wire Zd1gh7;
+ wire Fe1gh7;
+ wire Le1gh7;
+ wire Re1gh7;
+ wire Xe1gh7;
+ wire Df1gh7;
+ wire Jf1gh7;
+ wire Pf1gh7;
+ wire Vf1gh7;
+ wire Bg1gh7;
+ wire Hg1gh7;
+ wire Ng1gh7;
+ wire Tg1gh7;
+ wire Zg1gh7;
+ wire Fh1gh7;
+ wire Lh1gh7;
+ wire Rh1gh7;
+ wire Xh1gh7;
+ wire Di1gh7;
+ wire Ji1gh7;
+ wire Pi1gh7;
+ wire Vi1gh7;
+ wire Bj1gh7;
+ wire Hj1gh7;
+ wire Nj1gh7;
+ wire Tj1gh7;
+ wire Zj1gh7;
+ wire Fk1gh7;
+ wire Lk1gh7;
+ wire Rk1gh7;
+ wire Xk1gh7;
+ wire Dl1gh7;
+ wire Jl1gh7;
+ wire Pl1gh7;
+ wire Vl1gh7;
+ wire Bm1gh7;
+ wire Hm1gh7;
+ wire Nm1gh7;
+ wire Tm1gh7;
+ wire Zm1gh7;
+ wire Fn1gh7;
+ wire Ln1gh7;
+ wire Rn1gh7;
+ wire Xn1gh7;
+ wire Do1gh7;
+ wire Jo1gh7;
+ wire Po1gh7;
+ wire Vo1gh7;
+ wire Bp1gh7;
+ wire Hp1gh7;
+ wire Np1gh7;
+ wire Tp1gh7;
+ wire Zp1gh7;
+ wire Fq1gh7;
+ wire Lq1gh7;
+ wire Rq1gh7;
+ wire Xq1gh7;
+ wire Dr1gh7;
+ wire Jr1gh7;
+ wire Pr1gh7;
+ wire Vr1gh7;
+ wire Bs1gh7;
+ wire Hs1gh7;
+ wire Ns1gh7;
+ wire Ts1gh7;
+ wire Zs1gh7;
+ wire Ft1gh7;
+ wire Lt1gh7;
+ wire Rt1gh7;
+ wire Xt1gh7;
+ wire Du1gh7;
+ wire Ju1gh7;
+ wire Pu1gh7;
+ wire Vu1gh7;
+ wire Bv1gh7;
+ wire Hv1gh7;
+ wire Nv1gh7;
+ wire Tv1gh7;
+ wire Zv1gh7;
+ wire Fw1gh7;
+ wire Lw1gh7;
+ wire Rw1gh7;
+ wire Xw1gh7;
+ wire Dx1gh7;
+ wire Jx1gh7;
+ wire Px1gh7;
+ wire Vx1gh7;
+ wire By1gh7;
+ wire Hy1gh7;
+ wire Ny1gh7;
+ wire Ty1gh7;
+ wire Zy1gh7;
+ wire Fz1gh7;
+ wire Lz1gh7;
+ wire Rz1gh7;
+ wire Xz1gh7;
+ wire D02gh7;
+ wire J02gh7;
+ wire P02gh7;
+ wire V02gh7;
+ wire B12gh7;
+ wire H12gh7;
+ wire N12gh7;
+ wire T12gh7;
+ wire Z12gh7;
+ wire F22gh7;
+ wire L22gh7;
+ wire R22gh7;
+ wire X22gh7;
+ wire D32gh7;
+ wire J32gh7;
+ wire P32gh7;
+ wire V32gh7;
+ wire B42gh7;
+ wire H42gh7;
+ wire N42gh7;
+ wire T42gh7;
+ wire Z42gh7;
+ wire F52gh7;
+ wire L52gh7;
+ wire R52gh7;
+ wire X52gh7;
+ wire D62gh7;
+ wire J62gh7;
+ wire P62gh7;
+ wire V62gh7;
+ wire B72gh7;
+ wire H72gh7;
+ wire N72gh7;
+ wire T72gh7;
+ wire Z72gh7;
+ wire F82gh7;
+ wire L82gh7;
+ wire R82gh7;
+ wire X82gh7;
+ wire D92gh7;
+ wire J92gh7;
+ wire P92gh7;
+ wire V92gh7;
+ wire Ba2gh7;
+ wire Ha2gh7;
+ wire Na2gh7;
+ wire Ta2gh7;
+ wire Za2gh7;
+ wire Fb2gh7;
+ wire Lb2gh7;
+ wire Rb2gh7;
+ wire Xb2gh7;
+ wire Dc2gh7;
+ wire Jc2gh7;
+ wire Pc2gh7;
+ wire Vc2gh7;
+ wire Bd2gh7;
+ wire Hd2gh7;
+ wire Nd2gh7;
+ wire Td2gh7;
+ wire Zd2gh7;
+ wire Fe2gh7;
+ wire Le2gh7;
+ wire Re2gh7;
+ wire Xe2gh7;
+ wire Df2gh7;
+ wire Jf2gh7;
+ wire Pf2gh7;
+ wire Vf2gh7;
+ wire Bg2gh7;
+ wire Hg2gh7;
+ wire Ng2gh7;
+ wire Tg2gh7;
+ wire Zg2gh7;
+ wire Fh2gh7;
+ wire Lh2gh7;
+ wire Rh2gh7;
+ wire Xh2gh7;
+ wire Di2gh7;
+ wire Ji2gh7;
+ wire Pi2gh7;
+ wire Vi2gh7;
+ wire Bj2gh7;
+ wire Hj2gh7;
+ wire Nj2gh7;
+ wire Tj2gh7;
+ wire Zj2gh7;
+ wire Fk2gh7;
+ wire Lk2gh7;
+ wire Rk2gh7;
+ wire Xk2gh7;
+ wire Dl2gh7;
+ wire Jl2gh7;
+ wire Pl2gh7;
+ wire Vl2gh7;
+ wire Bm2gh7;
+ wire Hm2gh7;
+ wire Nm2gh7;
+ wire Tm2gh7;
+ wire Zm2gh7;
+ wire Fn2gh7;
+ wire Ln2gh7;
+ wire Rn2gh7;
+ wire Xn2gh7;
+ wire Do2gh7;
+ wire Jo2gh7;
+ wire Po2gh7;
+ wire Vo2gh7;
+ wire Bp2gh7;
+ wire Hp2gh7;
+ wire Np2gh7;
+ wire Tp2gh7;
+ wire Zp2gh7;
+ wire Fq2gh7;
+ wire Lq2gh7;
+ wire Rq2gh7;
+ wire Xq2gh7;
+ wire Dr2gh7;
+ wire Jr2gh7;
+ wire Pr2gh7;
+ wire Vr2gh7;
+ wire Bs2gh7;
+ wire Hs2gh7;
+ wire Ns2gh7;
+ wire Ts2gh7;
+ wire Zs2gh7;
+ wire Ft2gh7;
+ wire Lt2gh7;
+ wire Rt2gh7;
+ wire Xt2gh7;
+ wire Du2gh7;
+ wire Ju2gh7;
+ wire Pu2gh7;
+ wire Vu2gh7;
+ wire Bv2gh7;
+ wire Hv2gh7;
+ wire Nv2gh7;
+ wire Tv2gh7;
+ wire Zv2gh7;
+ wire Fw2gh7;
+ wire Lw2gh7;
+ wire Rw2gh7;
+ wire Xw2gh7;
+ wire Dx2gh7;
+ wire Jx2gh7;
+ wire Px2gh7;
+ wire Vx2gh7;
+ wire By2gh7;
+ wire Hy2gh7;
+ wire Ny2gh7;
+ wire Ty2gh7;
+ wire Zy2gh7;
+ wire Fz2gh7;
+ wire Lz2gh7;
+ wire Rz2gh7;
+ wire Xz2gh7;
+ wire D03gh7;
+ wire J03gh7;
+ wire P03gh7;
+ wire V03gh7;
+ wire B13gh7;
+ wire H13gh7;
+ wire N13gh7;
+ wire T13gh7;
+ wire Z13gh7;
+ wire F23gh7;
+ wire L23gh7;
+ wire R23gh7;
+ wire X23gh7;
+ wire D33gh7;
+ wire J33gh7;
+ wire P33gh7;
+ wire V33gh7;
+ wire B43gh7;
+ wire H43gh7;
+ wire N43gh7;
+ wire T43gh7;
+ wire Z43gh7;
+ wire F53gh7;
+ wire L53gh7;
+ wire R53gh7;
+ wire X53gh7;
+ wire D63gh7;
+ wire J63gh7;
+ wire P63gh7;
+ wire V63gh7;
+ wire B73gh7;
+ wire H73gh7;
+ wire N73gh7;
+ wire T73gh7;
+ wire Z73gh7;
+ wire F83gh7;
+ wire L83gh7;
+ wire R83gh7;
+ wire X83gh7;
+ wire D93gh7;
+ wire J93gh7;
+ wire P93gh7;
+ wire V93gh7;
+ wire Ba3gh7;
+ wire Ha3gh7;
+ wire Na3gh7;
+ wire Ta3gh7;
+ wire Za3gh7;
+ wire Fb3gh7;
+ wire Lb3gh7;
+ wire Rb3gh7;
+ wire Xb3gh7;
+ wire Dc3gh7;
+ wire Jc3gh7;
+ wire Pc3gh7;
+ wire Vc3gh7;
+ wire Bd3gh7;
+ wire Hd3gh7;
+ wire Nd3gh7;
+ wire Td3gh7;
+ wire Zd3gh7;
+ wire Fe3gh7;
+ wire Le3gh7;
+ wire Re3gh7;
+ wire Xe3gh7;
+ wire Df3gh7;
+ wire Jf3gh7;
+ wire Pf3gh7;
+ wire Vf3gh7;
+ wire Bg3gh7;
+ wire Hg3gh7;
+ wire Ng3gh7;
+ wire Tg3gh7;
+ wire Zg3gh7;
+ wire Fh3gh7;
+ wire Lh3gh7;
+ wire Rh3gh7;
+ wire Xh3gh7;
+ wire Di3gh7;
+ wire Ji3gh7;
+ wire Pi3gh7;
+ wire Vi3gh7;
+ wire Bj3gh7;
+ wire Hj3gh7;
+ wire Nj3gh7;
+ wire Tj3gh7;
+ wire Zj3gh7;
+ wire Fk3gh7;
+ wire Lk3gh7;
+ wire Rk3gh7;
+ wire Xk3gh7;
+ wire Dl3gh7;
+ wire Jl3gh7;
+ wire Pl3gh7;
+ wire Vl3gh7;
+ wire Bm3gh7;
+ wire Hm3gh7;
+ wire Nm3gh7;
+ wire Tm3gh7;
+ wire Zm3gh7;
+ wire Fn3gh7;
+ wire Ln3gh7;
+ wire Rn3gh7;
+ wire Xn3gh7;
+ wire Do3gh7;
+ wire Jo3gh7;
+ wire Po3gh7;
+ wire Vo3gh7;
+ wire Bp3gh7;
+ wire Hp3gh7;
+ wire Np3gh7;
+ wire Tp3gh7;
+ wire Zp3gh7;
+ wire Fq3gh7;
+ wire Lq3gh7;
+ wire Rq3gh7;
+ wire Xq3gh7;
+ wire Dr3gh7;
+ wire Jr3gh7;
+ wire Pr3gh7;
+ wire Vr3gh7;
+ wire Bs3gh7;
+ wire Hs3gh7;
+ wire Ns3gh7;
+ wire Ts3gh7;
+ wire Zs3gh7;
+ wire Ft3gh7;
+ wire Lt3gh7;
+ wire Rt3gh7;
+ wire Xt3gh7;
+ wire Du3gh7;
+ wire Ju3gh7;
+ wire Pu3gh7;
+ wire Vu3gh7;
+ wire Bv3gh7;
+ wire Hv3gh7;
+ wire Nv3gh7;
+ wire Tv3gh7;
+ wire Zv3gh7;
+ wire Fw3gh7;
+ wire Lw3gh7;
+ wire Rw3gh7;
+ wire Xw3gh7;
+ wire Dx3gh7;
+ wire Jx3gh7;
+ wire Px3gh7;
+ wire Vx3gh7;
+ wire By3gh7;
+ wire Hy3gh7;
+ wire Ny3gh7;
+ wire Ty3gh7;
+ wire Zy3gh7;
+ wire Fz3gh7;
+ wire Lz3gh7;
+ wire Rz3gh7;
+ wire Xz3gh7;
+ wire D04gh7;
+ wire J04gh7;
+ wire P04gh7;
+ wire V04gh7;
+ wire B14gh7;
+ wire H14gh7;
+ wire N14gh7;
+ wire T14gh7;
+ wire Z14gh7;
+ wire F24gh7;
+ wire L24gh7;
+ wire R24gh7;
+ wire X24gh7;
+ wire D34gh7;
+ wire J34gh7;
+ wire P34gh7;
+ wire V34gh7;
+ wire B44gh7;
+ wire H44gh7;
+ wire N44gh7;
+ wire T44gh7;
+ wire Z44gh7;
+ wire F54gh7;
+ wire L54gh7;
+ wire R54gh7;
+ wire X54gh7;
+ wire D64gh7;
+ wire J64gh7;
+ wire P64gh7;
+ wire V64gh7;
+ wire B74gh7;
+ wire H74gh7;
+ wire N74gh7;
+ wire T74gh7;
+ wire Z74gh7;
+ wire F84gh7;
+ wire L84gh7;
+ wire R84gh7;
+ wire X84gh7;
+ wire D94gh7;
+ wire J94gh7;
+ wire P94gh7;
+ wire V94gh7;
+ wire Ba4gh7;
+ wire Ha4gh7;
+ wire Na4gh7;
+ wire Ta4gh7;
+ wire Za4gh7;
+ wire Fb4gh7;
+ wire Lb4gh7;
+ wire Rb4gh7;
+ wire Xb4gh7;
+ wire Dc4gh7;
+ wire Jc4gh7;
+ wire Pc4gh7;
+ wire Vc4gh7;
+ wire Bd4gh7;
+ wire Hd4gh7;
+ wire Nd4gh7;
+ wire Td4gh7;
+ wire Zd4gh7;
+ wire Fe4gh7;
+ wire Le4gh7;
+ wire Re4gh7;
+ wire Xe4gh7;
+ wire Df4gh7;
+ wire Jf4gh7;
+ wire Pf4gh7;
+ wire Vf4gh7;
+ wire Bg4gh7;
+ wire Hg4gh7;
+ wire Ng4gh7;
+ wire Tg4gh7;
+ wire Zg4gh7;
+ wire Fh4gh7;
+ wire Lh4gh7;
+ wire Rh4gh7;
+ wire Xh4gh7;
+ wire Di4gh7;
+ wire Ji4gh7;
+ wire Pi4gh7;
+ wire Vi4gh7;
+ wire Bj4gh7;
+ wire Hj4gh7;
+ wire Nj4gh7;
+ wire Tj4gh7;
+ wire Zj4gh7;
+ wire Fk4gh7;
+ wire Lk4gh7;
+ wire Rk4gh7;
+ wire Xk4gh7;
+ wire Dl4gh7;
+ wire Jl4gh7;
+ wire Pl4gh7;
+ wire Vl4gh7;
+ wire Bm4gh7;
+ wire Hm4gh7;
+ wire Nm4gh7;
+ wire Tm4gh7;
+ wire Zm4gh7;
+ wire Fn4gh7;
+ wire Ln4gh7;
+ wire Rn4gh7;
+ wire Xn4gh7;
+ wire Do4gh7;
+ wire Jo4gh7;
+ wire Po4gh7;
+ wire Vo4gh7;
+ wire Bp4gh7;
+ wire Hp4gh7;
+ wire Np4gh7;
+ wire Tp4gh7;
+ wire Zp4gh7;
+ wire Fq4gh7;
+ wire Lq4gh7;
+ wire Rq4gh7;
+ wire Xq4gh7;
+ wire Dr4gh7;
+ wire Jr4gh7;
+ wire Pr4gh7;
+ wire Vr4gh7;
+ wire Bs4gh7;
+ wire Hs4gh7;
+ wire Ns4gh7;
+ wire Ts4gh7;
+ wire Zs4gh7;
+ wire Ft4gh7;
+ wire Lt4gh7;
+ wire Rt4gh7;
+ wire Xt4gh7;
+ wire Du4gh7;
+ wire Ju4gh7;
+ wire Pu4gh7;
+ wire Vu4gh7;
+ wire Bv4gh7;
+ wire Hv4gh7;
+ wire Nv4gh7;
+ wire Tv4gh7;
+ wire Zv4gh7;
+ wire Fw4gh7;
+ wire Lw4gh7;
+ wire Rw4gh7;
+ wire Xw4gh7;
+ wire Dx4gh7;
+ wire Jx4gh7;
+ wire Px4gh7;
+ wire Vx4gh7;
+ wire By4gh7;
+ wire Hy4gh7;
+ wire Ny4gh7;
+ wire Ty4gh7;
+ wire Zy4gh7;
+ wire Fz4gh7;
+ wire Lz4gh7;
+ wire Rz4gh7;
+ wire Xz4gh7;
+ wire D05gh7;
+ wire J05gh7;
+ wire P05gh7;
+ wire V05gh7;
+ wire B15gh7;
+ wire H15gh7;
+ wire N15gh7;
+ wire T15gh7;
+ wire Z15gh7;
+ wire F25gh7;
+ wire L25gh7;
+ wire R25gh7;
+ wire X25gh7;
+ wire D35gh7;
+ wire J35gh7;
+ wire P35gh7;
+ wire V35gh7;
+ wire B45gh7;
+ wire H45gh7;
+ wire N45gh7;
+ wire T45gh7;
+ wire Z45gh7;
+ wire F55gh7;
+ wire L55gh7;
+ wire R55gh7;
+ wire X55gh7;
+ wire D65gh7;
+ wire J65gh7;
+ wire P65gh7;
+ wire V65gh7;
+ wire B75gh7;
+ wire H75gh7;
+ wire N75gh7;
+ wire T75gh7;
+ wire Z75gh7;
+ wire F85gh7;
+ wire L85gh7;
+ wire R85gh7;
+ wire X85gh7;
+ wire D95gh7;
+ wire J95gh7;
+ wire P95gh7;
+ wire V95gh7;
+ wire Ba5gh7;
+ wire Ha5gh7;
+ wire Na5gh7;
+ wire Ta5gh7;
+ wire Za5gh7;
+ wire Fb5gh7;
+ wire Lb5gh7;
+ wire Rb5gh7;
+ wire Xb5gh7;
+ wire Dc5gh7;
+ wire Jc5gh7;
+ wire Pc5gh7;
+ wire Vc5gh7;
+ wire Bd5gh7;
+ wire Hd5gh7;
+ wire Nd5gh7;
+ wire Td5gh7;
+ wire Zd5gh7;
+ wire Fe5gh7;
+ wire Le5gh7;
+ wire Re5gh7;
+ wire Xe5gh7;
+ wire Df5gh7;
+ wire Jf5gh7;
+ wire Pf5gh7;
+ wire Vf5gh7;
+ wire Bg5gh7;
+ wire Hg5gh7;
+ wire Ng5gh7;
+ wire Tg5gh7;
+ wire Zg5gh7;
+ wire Fh5gh7;
+ wire Lh5gh7;
+ wire Rh5gh7;
+ wire Xh5gh7;
+ wire Di5gh7;
+ wire Ji5gh7;
+ wire Pi5gh7;
+ wire Vi5gh7;
+ wire Bj5gh7;
+ wire Hj5gh7;
+ wire Nj5gh7;
+ wire Tj5gh7;
+ wire Zj5gh7;
+ wire Fk5gh7;
+ wire Lk5gh7;
+ wire Rk5gh7;
+ wire Xk5gh7;
+ wire Dl5gh7;
+ wire Jl5gh7;
+ wire Pl5gh7;
+ wire Vl5gh7;
+ wire Bm5gh7;
+ wire Hm5gh7;
+ wire Nm5gh7;
+ wire Tm5gh7;
+ wire Zm5gh7;
+ wire Fn5gh7;
+ wire Ln5gh7;
+ wire Rn5gh7;
+ wire Xn5gh7;
+ wire Do5gh7;
+ wire Jo5gh7;
+ wire Po5gh7;
+ wire Vo5gh7;
+ wire Bp5gh7;
+ wire Hp5gh7;
+ wire Np5gh7;
+ wire Tp5gh7;
+ wire Zp5gh7;
+ wire Fq5gh7;
+ wire Lq5gh7;
+ wire Rq5gh7;
+ wire Xq5gh7;
+ wire Dr5gh7;
+ wire Jr5gh7;
+ wire Pr5gh7;
+ wire Vr5gh7;
+ wire Bs5gh7;
+ wire Hs5gh7;
+ wire Ns5gh7;
+ wire Ts5gh7;
+ wire Zs5gh7;
+ wire Ft5gh7;
+ wire Lt5gh7;
+ wire Rt5gh7;
+ wire Xt5gh7;
+ wire Du5gh7;
+ wire Ju5gh7;
+ wire Pu5gh7;
+ wire Vu5gh7;
+ wire Bv5gh7;
+ wire Hv5gh7;
+ wire Nv5gh7;
+ wire Tv5gh7;
+ wire Zv5gh7;
+ wire Fw5gh7;
+ wire Lw5gh7;
+ wire Rw5gh7;
+ wire Xw5gh7;
+ wire Dx5gh7;
+ wire Jx5gh7;
+ wire Px5gh7;
+ wire Vx5gh7;
+ wire By5gh7;
+ wire Hy5gh7;
+ wire Ny5gh7;
+ wire Ty5gh7;
+ wire Zy5gh7;
+ wire Fz5gh7;
+ wire Lz5gh7;
+ wire Rz5gh7;
+ wire Xz5gh7;
+ wire D06gh7;
+ wire J06gh7;
+ wire P06gh7;
+ wire V06gh7;
+ wire B16gh7;
+ wire H16gh7;
+ wire N16gh7;
+ wire T16gh7;
+ wire Z16gh7;
+ wire F26gh7;
+ wire L26gh7;
+ wire R26gh7;
+ wire X26gh7;
+ wire D36gh7;
+ wire J36gh7;
+ wire P36gh7;
+ wire V36gh7;
+ wire B46gh7;
+ wire H46gh7;
+ wire N46gh7;
+ wire T46gh7;
+ wire Z46gh7;
+ wire F56gh7;
+ wire L56gh7;
+ wire R56gh7;
+ wire X56gh7;
+ wire D66gh7;
+ wire J66gh7;
+ wire P66gh7;
+ wire V66gh7;
+ wire B76gh7;
+ wire H76gh7;
+ wire N76gh7;
+ wire T76gh7;
+ wire Z76gh7;
+ wire F86gh7;
+ wire L86gh7;
+ wire R86gh7;
+ wire X86gh7;
+ wire D96gh7;
+ wire J96gh7;
+ wire P96gh7;
+ wire V96gh7;
+ wire Ba6gh7;
+ wire Ha6gh7;
+ wire Na6gh7;
+ wire Ta6gh7;
+ wire Za6gh7;
+ wire Fb6gh7;
+ wire Lb6gh7;
+ wire Rb6gh7;
+ wire Xb6gh7;
+ wire Dc6gh7;
+ wire Jc6gh7;
+ wire Pc6gh7;
+ wire Vc6gh7;
+ wire Bd6gh7;
+ wire Hd6gh7;
+ wire Nd6gh7;
+ wire Td6gh7;
+ wire Zd6gh7;
+ wire Fe6gh7;
+ wire Le6gh7;
+ wire Re6gh7;
+ wire Xe6gh7;
+ wire Df6gh7;
+ wire Jf6gh7;
+ wire Pf6gh7;
+ wire Vf6gh7;
+ wire Bg6gh7;
+ wire Hg6gh7;
+ wire Ng6gh7;
+ wire Tg6gh7;
+ wire Zg6gh7;
+ wire Fh6gh7;
+ wire Lh6gh7;
+ wire Rh6gh7;
+ wire Xh6gh7;
+ wire Di6gh7;
+ wire Ji6gh7;
+ wire Pi6gh7;
+ wire Vi6gh7;
+ wire Bj6gh7;
+ wire Hj6gh7;
+ wire Nj6gh7;
+ wire Tj6gh7;
+ wire Zj6gh7;
+ wire Fk6gh7;
+ wire Lk6gh7;
+ wire Rk6gh7;
+ wire Xk6gh7;
+ wire Dl6gh7;
+ wire Jl6gh7;
+ wire Pl6gh7;
+ wire Vl6gh7;
+ wire Bm6gh7;
+ wire Hm6gh7;
+ wire Nm6gh7;
+ wire Tm6gh7;
+ wire Zm6gh7;
+ wire Fn6gh7;
+ wire Ln6gh7;
+ wire Rn6gh7;
+ wire Xn6gh7;
+ wire Do6gh7;
+ wire Jo6gh7;
+ wire Po6gh7;
+ wire Vo6gh7;
+ wire Bp6gh7;
+ wire Hp6gh7;
+ wire Np6gh7;
+ wire Tp6gh7;
+ wire Zp6gh7;
+ wire Fq6gh7;
+ wire Lq6gh7;
+ wire Rq6gh7;
+ wire Xq6gh7;
+ wire Dr6gh7;
+ wire Jr6gh7;
+ wire Pr6gh7;
+ wire Vr6gh7;
+ wire Bs6gh7;
+ wire Hs6gh7;
+ wire Ns6gh7;
+ wire Ts6gh7;
+ wire Zs6gh7;
+ wire Ft6gh7;
+ wire Lt6gh7;
+ wire Rt6gh7;
+ wire Xt6gh7;
+ wire Du6gh7;
+ wire Ju6gh7;
+ wire Pu6gh7;
+ wire Vu6gh7;
+ wire Bv6gh7;
+ wire Hv6gh7;
+ wire Nv6gh7;
+ wire Tv6gh7;
+ wire Zv6gh7;
+ wire Fw6gh7;
+ wire Lw6gh7;
+ wire Rw6gh7;
+ wire Xw6gh7;
+ wire Dx6gh7;
+ wire Jx6gh7;
+ wire Px6gh7;
+ wire Vx6gh7;
+ wire By6gh7;
+ wire Hy6gh7;
+ wire Ny6gh7;
+ wire Ty6gh7;
+ wire Zy6gh7;
+ wire Fz6gh7;
+ wire Lz6gh7;
+ wire Rz6gh7;
+ wire Xz6gh7;
+ wire D07gh7;
+ wire J07gh7;
+ wire P07gh7;
+ wire V07gh7;
+ wire B17gh7;
+ wire H17gh7;
+ wire N17gh7;
+ wire T17gh7;
+ wire Z17gh7;
+ wire F27gh7;
+ wire L27gh7;
+ wire R27gh7;
+ wire X27gh7;
+ wire D37gh7;
+ wire J37gh7;
+ wire P37gh7;
+ wire V37gh7;
+ wire B47gh7;
+ wire H47gh7;
+ wire N47gh7;
+ wire T47gh7;
+ wire Z47gh7;
+ wire F57gh7;
+ wire L57gh7;
+ wire R57gh7;
+ wire X57gh7;
+ wire D67gh7;
+ wire J67gh7;
+ wire P67gh7;
+ wire V67gh7;
+ wire B77gh7;
+ wire H77gh7;
+ wire N77gh7;
+ wire T77gh7;
+ wire Z77gh7;
+ wire F87gh7;
+ wire L87gh7;
+ wire R87gh7;
+ wire X87gh7;
+ wire D97gh7;
+ wire J97gh7;
+ wire P97gh7;
+ wire V97gh7;
+ wire Ba7gh7;
+ wire Ha7gh7;
+ wire Na7gh7;
+ wire Ta7gh7;
+ wire Za7gh7;
+ wire Fb7gh7;
+ wire Lb7gh7;
+ wire Rb7gh7;
+ wire Xb7gh7;
+ wire Dc7gh7;
+ wire Jc7gh7;
+ wire Pc7gh7;
+ wire Vc7gh7;
+ wire Bd7gh7;
+ wire Hd7gh7;
+ wire Nd7gh7;
+ wire Td7gh7;
+ wire Zd7gh7;
+ wire Fe7gh7;
+ wire Le7gh7;
+ wire Re7gh7;
+ wire Xe7gh7;
+ wire Df7gh7;
+ wire Jf7gh7;
+ wire Pf7gh7;
+ wire Vf7gh7;
+ wire Bg7gh7;
+ wire Hg7gh7;
+ wire Ng7gh7;
+ wire Tg7gh7;
+ wire Zg7gh7;
+ wire Fh7gh7;
+ wire Lh7gh7;
+ wire Rh7gh7;
+ wire Xh7gh7;
+ wire Di7gh7;
+ wire Ji7gh7;
+ wire Pi7gh7;
+ wire Vi7gh7;
+ wire Bj7gh7;
+ wire Hj7gh7;
+ wire Nj7gh7;
+ wire Tj7gh7;
+ wire Zj7gh7;
+ wire Fk7gh7;
+ wire Lk7gh7;
+ wire Rk7gh7;
+ wire Xk7gh7;
+ wire Dl7gh7;
+ wire Jl7gh7;
+ wire Pl7gh7;
+ wire Vl7gh7;
+ wire Bm7gh7;
+ wire Hm7gh7;
+ wire Nm7gh7;
+ wire Tm7gh7;
+ wire Zm7gh7;
+ wire Fn7gh7;
+ wire Ln7gh7;
+ wire Rn7gh7;
+ wire Xn7gh7;
+ wire Do7gh7;
+ wire Jo7gh7;
+ wire Po7gh7;
+ wire Vo7gh7;
+ wire Bp7gh7;
+ wire Hp7gh7;
+ wire Np7gh7;
+ wire Tp7gh7;
+ wire Zp7gh7;
+ wire Fq7gh7;
+ wire Lq7gh7;
+ wire Rq7gh7;
+ wire Xq7gh7;
+ wire Dr7gh7;
+ wire Jr7gh7;
+ wire Pr7gh7;
+ wire Vr7gh7;
+ wire Bs7gh7;
+ wire Hs7gh7;
+ wire Ns7gh7;
+ wire Ts7gh7;
+ wire Zs7gh7;
+ wire Ft7gh7;
+ wire Lt7gh7;
+ wire Rt7gh7;
+ wire Xt7gh7;
+ wire Du7gh7;
+ wire Ju7gh7;
+ wire Pu7gh7;
+ wire Vu7gh7;
+ wire Bv7gh7;
+ wire Hv7gh7;
+ wire Nv7gh7;
+ wire Tv7gh7;
+ wire Zv7gh7;
+ wire Fw7gh7;
+ wire Lw7gh7;
+ wire Rw7gh7;
+ wire Xw7gh7;
+ wire Dx7gh7;
+ wire Jx7gh7;
+ wire Px7gh7;
+ wire Vx7gh7;
+ wire By7gh7;
+ wire Hy7gh7;
+ wire Ny7gh7;
+ wire Ty7gh7;
+ wire Zy7gh7;
+ wire Fz7gh7;
+ wire Lz7gh7;
+ wire Rz7gh7;
+ wire Xz7gh7;
+ wire D08gh7;
+ wire J08gh7;
+ wire P08gh7;
+ wire V08gh7;
+ wire B18gh7;
+ wire H18gh7;
+ wire N18gh7;
+ wire T18gh7;
+ wire Z18gh7;
+ wire F28gh7;
+ wire L28gh7;
+ wire R28gh7;
+ wire X28gh7;
+ wire D38gh7;
+ wire J38gh7;
+ wire P38gh7;
+ wire V38gh7;
+ wire B48gh7;
+ wire H48gh7;
+ wire N48gh7;
+ wire T48gh7;
+ wire Z48gh7;
+ wire F58gh7;
+ wire L58gh7;
+ wire R58gh7;
+ wire X58gh7;
+ wire D68gh7;
+ wire J68gh7;
+ wire P68gh7;
+ wire V68gh7;
+ wire B78gh7;
+ wire H78gh7;
+ wire N78gh7;
+ wire T78gh7;
+ wire Z78gh7;
+ wire F88gh7;
+ wire L88gh7;
+ wire R88gh7;
+ wire X88gh7;
+ wire D98gh7;
+ wire J98gh7;
+ wire P98gh7;
+ wire V98gh7;
+ wire Ba8gh7;
+ wire Ha8gh7;
+ wire Na8gh7;
+ wire Ta8gh7;
+ wire Za8gh7;
+ wire Fb8gh7;
+ wire Lb8gh7;
+ wire Rb8gh7;
+ wire Xb8gh7;
+ wire Dc8gh7;
+ wire Jc8gh7;
+ wire Pc8gh7;
+ wire Vc8gh7;
+ wire Bd8gh7;
+ wire Hd8gh7;
+ wire Nd8gh7;
+ wire Td8gh7;
+ wire Zd8gh7;
+ wire Fe8gh7;
+ wire Le8gh7;
+ wire Re8gh7;
+ wire Xe8gh7;
+ wire Df8gh7;
+ wire Jf8gh7;
+ wire Pf8gh7;
+ wire Vf8gh7;
+ wire Bg8gh7;
+ wire Hg8gh7;
+ wire Ng8gh7;
+ wire Tg8gh7;
+ wire Zg8gh7;
+ wire Fh8gh7;
+ wire Lh8gh7;
+ wire Rh8gh7;
+ wire Xh8gh7;
+ wire Di8gh7;
+ wire Ji8gh7;
+ wire Pi8gh7;
+ wire Vi8gh7;
+ wire Bj8gh7;
+ wire Hj8gh7;
+ wire Nj8gh7;
+ wire Tj8gh7;
+ wire Zj8gh7;
+ wire Fk8gh7;
+ wire Lk8gh7;
+ wire Rk8gh7;
+ wire Xk8gh7;
+ wire Dl8gh7;
+ wire Jl8gh7;
+ wire Pl8gh7;
+ wire Vl8gh7;
+ wire Bm8gh7;
+ wire Hm8gh7;
+ wire Nm8gh7;
+ wire Tm8gh7;
+ wire Zm8gh7;
+ wire Fn8gh7;
+ wire Ln8gh7;
+ wire Rn8gh7;
+ wire Xn8gh7;
+ wire Do8gh7;
+ wire Jo8gh7;
+ wire Po8gh7;
+ wire Vo8gh7;
+ wire Bp8gh7;
+ wire Hp8gh7;
+ wire Np8gh7;
+ wire Tp8gh7;
+ wire Zp8gh7;
+ wire Fq8gh7;
+ wire Lq8gh7;
+ wire Rq8gh7;
+ wire Xq8gh7;
+ wire Dr8gh7;
+ wire Jr8gh7;
+ wire Pr8gh7;
+ wire Vr8gh7;
+ wire Bs8gh7;
+ wire Hs8gh7;
+ wire Ns8gh7;
+ wire Ts8gh7;
+ wire Zs8gh7;
+ wire Ft8gh7;
+ wire Lt8gh7;
+ wire Rt8gh7;
+ wire Xt8gh7;
+ wire Du8gh7;
+ wire Ju8gh7;
+ wire Pu8gh7;
+ wire Vu8gh7;
+ wire Bv8gh7;
+ wire Hv8gh7;
+ wire Nv8gh7;
+ wire Tv8gh7;
+ wire Zv8gh7;
+ wire Fw8gh7;
+ wire Lw8gh7;
+ wire Rw8gh7;
+ wire Xw8gh7;
+ wire Dx8gh7;
+ wire Jx8gh7;
+ wire Px8gh7;
+ wire Vx8gh7;
+ wire By8gh7;
+ wire Hy8gh7;
+ wire Ny8gh7;
+ wire Ty8gh7;
+ wire Zy8gh7;
+ wire Fz8gh7;
+ wire Lz8gh7;
+ wire Rz8gh7;
+ wire Xz8gh7;
+ wire D09gh7;
+ wire J09gh7;
+ wire P09gh7;
+ wire V09gh7;
+ wire B19gh7;
+ wire H19gh7;
+ wire N19gh7;
+ wire T19gh7;
+ wire Z19gh7;
+ wire F29gh7;
+ wire L29gh7;
+ wire R29gh7;
+ wire X29gh7;
+ wire D39gh7;
+ wire J39gh7;
+ wire P39gh7;
+ wire V39gh7;
+ wire B49gh7;
+ wire H49gh7;
+ wire N49gh7;
+ wire T49gh7;
+ wire Z49gh7;
+ wire F59gh7;
+ wire L59gh7;
+ wire R59gh7;
+ wire X59gh7;
+ wire D69gh7;
+ wire J69gh7;
+ wire P69gh7;
+ wire V69gh7;
+ wire B79gh7;
+ wire H79gh7;
+ wire N79gh7;
+ wire T79gh7;
+ wire Z79gh7;
+ wire F89gh7;
+ wire L89gh7;
+ wire R89gh7;
+ wire X89gh7;
+ wire D99gh7;
+ wire J99gh7;
+ wire P99gh7;
+ wire V99gh7;
+ wire Ba9gh7;
+ wire Ha9gh7;
+ wire Na9gh7;
+ wire Ta9gh7;
+ wire Za9gh7;
+ wire Fb9gh7;
+ wire Lb9gh7;
+ wire Rb9gh7;
+ wire Xb9gh7;
+ wire Dc9gh7;
+ wire Jc9gh7;
+ wire Pc9gh7;
+ wire Vc9gh7;
+ wire Bd9gh7;
+ wire Hd9gh7;
+ wire [31:0] Nd9gh7;
+ reg Ie9gh7;
+ reg If9gh7;
+ reg Ng9gh7;
+ reg Ph9gh7;
+ reg Ri9gh7;
+ reg Tj9gh7;
+ reg Wk9gh7;
+ reg Wl9gh7;
+ reg Zm9gh7;
+ reg Bo9gh7;
+ reg Dp9gh7;
+ reg Fq9gh7;
+ reg Ir9gh7;
+ reg Ls9gh7;
+ reg Lt9gh7;
+ reg Ou9gh7;
+ reg Pv9gh7;
+ reg Rw9gh7;
+ reg Tx9gh7;
+ reg Wy9gh7;
+ reg Zz9gh7;
+ reg C1agh7;
+ reg F2agh7;
+ reg I3agh7;
+ reg L4agh7;
+ reg O5agh7;
+ reg R6agh7;
+ reg U7agh7;
+ reg U8agh7;
+ reg X9agh7;
+ reg Abagh7;
+ reg Wbagh7;
+ reg Zcagh7;
+ reg Ceagh7;
+ reg Efagh7;
+ reg Ggagh7;
+ reg Jhagh7;
+ reg Miagh7;
+ reg Pjagh7;
+ reg Skagh7;
+ reg Vlagh7;
+ reg Ymagh7;
+ reg Boagh7;
+ reg Epagh7;
+ reg Eqagh7;
+ reg Eragh7;
+ reg Esagh7;
+ reg Etagh7;
+ reg Euagh7;
+ reg Evagh7;
+ reg Ewagh7;
+ reg Hxagh7;
+ reg Kyagh7;
+ reg Nzagh7;
+ reg Q0bgh7;
+ reg T1bgh7;
+ reg W2bgh7;
+ reg Z3bgh7;
+ reg C5bgh7;
+ reg F6bgh7;
+ reg H7bgh7;
+ reg K8bgh7;
+ reg N9bgh7;
+ reg Pabgh7;
+ reg Rbbgh7;
+ reg Ucbgh7;
+ reg Xdbgh7;
+ reg Afbgh7;
+ reg Dgbgh7;
+ reg Ghbgh7;
+ reg Iibgh7;
+ reg Kjbgh7;
+ reg Nkbgh7;
+ reg Plbgh7;
+ reg Rmbgh7;
+ reg Tnbgh7;
+ reg Vobgh7;
+ reg Wpbgh7;
+ reg Xqbgh7;
+ reg Yrbgh7;
+ reg Zsbgh7;
+ reg Bubgh7;
+ reg Cvbgh7;
+ reg Dwbgh7;
+ reg Dxbgh7;
+ reg Fybgh7;
+ reg Gzbgh7;
+ reg H0cgh7;
+ reg H1cgh7;
+ reg H2cgh7;
+ reg J3cgh7;
+ reg K4cgh7;
+ reg N5cgh7;
+ reg P6cgh7;
+ reg S7cgh7;
+ reg U8cgh7;
+ reg X9cgh7;
+ reg Zacgh7;
+ reg Cccgh7;
+ reg Edcgh7;
+ reg Hecgh7;
+ reg Jfcgh7;
+ reg Kgcgh7;
+ reg Mhcgh7;
+ reg Nicgh7;
+ reg Pjcgh7;
+ reg Qkcgh7;
+ reg Slcgh7;
+ reg Tmcgh7;
+ reg Vncgh7;
+ reg Wocgh7;
+ reg Ypcgh7;
+ reg Zqcgh7;
+ reg Zrcgh7;
+ reg Btcgh7;
+ reg Cucgh7;
+ reg Fvcgh7;
+ reg Hwcgh7;
+ reg Kxcgh7;
+ reg Mycgh7;
+ reg Pzcgh7;
+ reg R0dgh7;
+ reg U1dgh7;
+ reg W2dgh7;
+ reg Z3dgh7;
+ reg B5dgh7;
+ reg C6dgh7;
+ reg E7dgh7;
+ reg F8dgh7;
+ reg H9dgh7;
+ reg Iadgh7;
+ reg Kbdgh7;
+ reg Lcdgh7;
+ reg Nddgh7;
+ reg Oedgh7;
+ reg Qfdgh7;
+ reg Rgdgh7;
+ reg Rhdgh7;
+ reg Tidgh7;
+ reg Ujdgh7;
+ reg Xkdgh7;
+ reg Zldgh7;
+ reg Cndgh7;
+ reg Eodgh7;
+ reg Hpdgh7;
+ reg Jqdgh7;
+ reg Mrdgh7;
+ reg Osdgh7;
+ reg Rtdgh7;
+ reg Tudgh7;
+ reg Wvdgh7;
+ reg Ywdgh7;
+ reg Zxdgh7;
+ reg Bzdgh7;
+ reg C0egh7;
+ reg E1egh7;
+ reg F2egh7;
+ reg H3egh7;
+ reg I4egh7;
+ reg K5egh7;
+ reg L6egh7;
+ reg N7egh7;
+ reg O8egh7;
+ reg Q9egh7;
+ reg Raegh7;
+ reg Rbegh7;
+ reg Scegh7;
+ reg Udegh7;
+ reg Veegh7;
+ reg Xfegh7;
+ reg Ygegh7;
+ reg Aiegh7;
+ reg Bjegh7;
+ reg Dkegh7;
+ reg Elegh7;
+ reg Gmegh7;
+ reg Hnegh7;
+ reg Joegh7;
+ reg Jpegh7;
+ reg Kqegh7;
+ reg Kregh7;
+ reg Ksegh7;
+ reg Ktegh7;
+ reg Kuegh7;
+ reg Kvegh7;
+ reg Kwegh7;
+ reg Kxegh7;
+ reg Kyegh7;
+ reg Lzegh7;
+ reg O0fgh7;
+ reg P1fgh7;
+ reg S2fgh7;
+ reg V3fgh7;
+ reg X4fgh7;
+ reg Z5fgh7;
+ reg B7fgh7;
+ reg D8fgh7;
+ reg H9fgh7;
+ reg Hafgh7;
+ reg Lbfgh7;
+ reg Pcfgh7;
+ reg Tdfgh7;
+ reg Xefgh7;
+ reg Bgfgh7;
+ reg Fhfgh7;
+ reg Jifgh7;
+ reg Ojfgh7;
+ reg Tkfgh7;
+ reg Ylfgh7;
+ reg Dnfgh7;
+ reg Iofgh7;
+ reg Npfgh7;
+ reg Sqfgh7;
+ reg Yrfgh7;
+ reg Etfgh7;
+ reg Kufgh7;
+ reg Qvfgh7;
+ reg Wwfgh7;
+ reg Cyfgh7;
+ reg Izfgh7;
+ reg O0ggh7;
+ reg U1ggh7;
+ reg A3ggh7;
+ reg G4ggh7;
+ reg M5ggh7;
+ reg S6ggh7;
+ reg Y7ggh7;
+ reg E9ggh7;
+ reg Kaggh7;
+ reg Qbggh7;
+ reg Wcggh7;
+ reg Ceggh7;
+ reg Ifggh7;
+ reg Ogggh7;
+ reg Phggh7;
+ reg Uiggh7;
+ reg Yjggh7;
+ reg Ykggh7;
+ reg Ylggh7;
+ reg Enggh7;
+ reg Foggh7;
+ reg Hpggh7;
+ reg Jqggh7;
+ reg Lrggh7;
+ reg Nsggh7;
+ reg Ptggh7;
+ reg Ruggh7;
+ reg Tvggh7;
+ reg Vwggh7;
+ reg Xxggh7;
+ reg Azggh7;
+ reg D0hgh7;
+ reg G1hgh7;
+ reg J2hgh7;
+ reg M3hgh7;
+ reg P4hgh7;
+ reg S5hgh7;
+ reg V6hgh7;
+ reg Y7hgh7;
+ reg B9hgh7;
+ reg Eahgh7;
+ reg Hbhgh7;
+ reg Kchgh7;
+ reg Ndhgh7;
+ reg Qehgh7;
+ reg Tfhgh7;
+ reg Wghgh7;
+ reg Zhhgh7;
+ reg Cjhgh7;
+ reg Fkhgh7;
+ reg Ilhgh7;
+ reg Lmhgh7;
+ reg Mnhgh7;
+ reg Mohgh7;
+ reg Rphgh7;
+ reg Vqhgh7;
+ reg Zrhgh7;
+ reg Dthgh7;
+ reg Huhgh7;
+ reg Lvhgh7;
+ reg Pwhgh7;
+ wire [33:0] Txhgh7;
+ wire [33:0] Wyhgh7;
+
+ assign ahb_hburst[2] = 1'b0;
+ assign ahb_hburst[1] = 1'b0;
+ assign ahb_hmastlock = 1'b0;
+ assign ahb_hprot[3] = 1'b0;
+ assign ahb_hprot[2] = 1'b0;
+ assign ahb_hsize[2] = 1'b0;
+ assign ahb_hsize[0] = 1'b0;
+ assign ahb_htrans[0] = 1'b0;
+ assign ahb_hburst[0] = 1'b1;
+ assign ahb_hprot[1] = 1'b1;
+ assign ahb_hprot[0] = 1'b1;
+ assign ahb_hsize[1] = 1'b1;
+ assign Hd9gh7 = (!Ie9gh7);
+ assign ahb_hwdata[0] = If9gh7;
+ assign Jltfh7 = (!If9gh7);
+ assign Bd9gh7 = (!Ng9gh7);
+ assign Vc9gh7 = (!Ph9gh7);
+ assign Nd9gh7[1] = Ri9gh7;
+ assign Hgtfh7 = (!Ri9gh7);
+ assign Nv8gh7 = (!Tj9gh7);
+ assign com_rx_tready = Wk9gh7;
+ assign Xw8gh7 = (!Wl9gh7);
+ assign Fz8gh7 = (!Zm9gh7);
+ assign Ty8gh7 = (!Bo9gh7);
+ assign Pc9gh7 = (!Dp9gh7);
+ assign By8gh7 = (!Fq9gh7);
+ assign Vu8gh7 = (!Ir9gh7);
+ assign com_tx_tvalid = Ls9gh7;
+ assign Lz8gh7 = (!Lt9gh7);
+ assign ahb_haddr[0] = Ou9gh7;
+ assign Jc9gh7 = (!Pv9gh7);
+ assign Dc9gh7 = (!Rw9gh7);
+ assign Bv8gh7 = (!Tx9gh7);
+ assign Hv8gh7 = (!Wy9gh7);
+ assign Ft8gh7 = (!Zz9gh7);
+ assign Jx8gh7 = (!C1agh7);
+ assign P09gh7 = (!F2agh7);
+ assign Xz8gh7 = (!I3agh7);
+ assign N19gh7 = (!L4agh7);
+ assign Xt8gh7 = (!O5agh7);
+ assign Xb9gh7 = (!R6agh7);
+ assign stdio_rx_tready = U7agh7;
+ assign Hy8gh7 = (!U8agh7);
+ assign Rz8gh7 = (!X9agh7);
+ assign Fe8gh7 = (!Abagh7);
+ assign V09gh7 = (!Wbagh7);
+ assign Lw8gh7 = (!Zcagh7);
+ assign Lt8gh7 = (!Ceagh7);
+ assign Rt8gh7 = (!Efagh7);
+ assign Fw8gh7 = (!Ggagh7);
+ assign L29gh7 = (!Jhagh7);
+ assign D09gh7 = (!Miagh7);
+ assign Zv8gh7 = (!Pjagh7);
+ assign Dx8gh7 = (!Skagh7);
+ assign Tv8gh7 = (!Vlagh7);
+ assign Ju8gh7 = (!Ymagh7);
+ assign Pu8gh7 = (!Boagh7);
+ assign Rb9gh7 = (!Epagh7);
+ assign Zd8gh7 = (!Eqagh7);
+ assign Lb9gh7 = (!Eragh7);
+ assign Fb9gh7 = (!Esagh7);
+ assign Za9gh7 = (!Etagh7);
+ assign Ta9gh7 = (!Euagh7);
+ assign Na9gh7 = (!Evagh7);
+ assign Ha9gh7 = (!Ewagh7);
+ assign B19gh7 = (!Hxagh7);
+ assign Ba9gh7 = (!Kyagh7);
+ assign H19gh7 = (!Nzagh7);
+ assign F29gh7 = (!Q0bgh7);
+ assign Du8gh7 = (!T1bgh7);
+ assign T19gh7 = (!W2bgh7);
+ assign V99gh7 = (!Z3bgh7);
+ assign Z19gh7 = (!C5bgh7);
+ assign R9tfh7 = F6bgh7;
+ assign ahb_hwrite = H7bgh7;
+ assign J09gh7 = (!K8bgh7);
+ assign P99gh7 = (!N9bgh7);
+ assign J99gh7 = (!Pabgh7);
+ assign D99gh7 = (!Rbbgh7);
+ assign X89gh7 = (!Ucbgh7);
+ assign R89gh7 = (!Xdbgh7);
+ assign L89gh7 = (!Afbgh7);
+ assign F89gh7 = (!Dgbgh7);
+ assign ahb_haddr[29] = Ghbgh7;
+ assign ahb_haddr[31] = Iibgh7;
+ assign Z79gh7 = (!Kjbgh7);
+ assign ahb_haddr[25] = Nkbgh7;
+ assign ahb_haddr[21] = Plbgh7;
+ assign ahb_haddr[17] = Rmbgh7;
+ assign ahb_haddr[13] = Tnbgh7;
+ assign ahb_haddr[9] = Vobgh7;
+ assign ahb_haddr[5] = Wpbgh7;
+ assign ahb_haddr[4] = Xqbgh7;
+ assign ahb_haddr[1] = Yrbgh7;
+ assign T79gh7 = (!Zsbgh7);
+ assign ahb_haddr[2] = Bubgh7;
+ assign Tp8gh7 = (!Cvbgh7);
+ assign Np8gh7 = (!Dwbgh7);
+ assign N79gh7 = (!Dxbgh7);
+ assign ahb_haddr[3] = Fybgh7;
+ assign Df8gh7 = (!Gzbgh7);
+ assign Xe8gh7 = (!H0cgh7);
+ assign Tm8gh7 = (!H1cgh7);
+ assign H79gh7 = (!H2cgh7);
+ assign ahb_haddr[8] = J3cgh7;
+ assign B79gh7 = (!K4cgh7);
+ assign ahb_haddr[12] = N5cgh7;
+ assign V69gh7 = (!P6cgh7);
+ assign ahb_haddr[16] = S7cgh7;
+ assign P69gh7 = (!U8cgh7);
+ assign ahb_haddr[20] = X9cgh7;
+ assign J69gh7 = (!Zacgh7);
+ assign ahb_haddr[24] = Cccgh7;
+ assign D69gh7 = (!Edcgh7);
+ assign ahb_haddr[28] = Hecgh7;
+ assign Rn8gh7 = (!Jfcgh7);
+ assign Xn8gh7 = (!Kgcgh7);
+ assign Do8gh7 = (!Mhcgh7);
+ assign Jo8gh7 = (!Nicgh7);
+ assign Fn8gh7 = (!Pjcgh7);
+ assign Ln8gh7 = (!Qkcgh7);
+ assign Po8gh7 = (!Slcgh7);
+ assign Vo8gh7 = (!Tmcgh7);
+ assign Hm8gh7 = (!Vncgh7);
+ assign Nm8gh7 = (!Wocgh7);
+ assign Zm8gh7 = (!Ypcgh7);
+ assign Vf8gh7 = (!Zqcgh7);
+ assign X59gh7 = (!Zrcgh7);
+ assign ahb_haddr[7] = Btcgh7;
+ assign R59gh7 = (!Cucgh7);
+ assign ahb_haddr[11] = Fvcgh7;
+ assign L59gh7 = (!Hwcgh7);
+ assign ahb_haddr[15] = Kxcgh7;
+ assign F59gh7 = (!Mycgh7);
+ assign ahb_haddr[19] = Pzcgh7;
+ assign Z49gh7 = (!R0dgh7);
+ assign ahb_haddr[23] = U1dgh7;
+ assign T49gh7 = (!W2dgh7);
+ assign ahb_haddr[27] = Z3dgh7;
+ assign Lk8gh7 = (!B5dgh7);
+ assign Rk8gh7 = (!C6dgh7);
+ assign Nj8gh7 = (!E7dgh7);
+ assign Tj8gh7 = (!F8dgh7);
+ assign Pi8gh7 = (!H9dgh7);
+ assign Vi8gh7 = (!Iadgh7);
+ assign Rh8gh7 = (!Kbdgh7);
+ assign Xh8gh7 = (!Lcdgh7);
+ assign Tg8gh7 = (!Nddgh7);
+ assign Zg8gh7 = (!Oedgh7);
+ assign Bg8gh7 = (!Qfdgh7);
+ assign Zp8gh7 = (!Rgdgh7);
+ assign N49gh7 = (!Rhdgh7);
+ assign ahb_haddr[6] = Tidgh7;
+ assign H49gh7 = (!Ujdgh7);
+ assign ahb_haddr[10] = Xkdgh7;
+ assign B49gh7 = (!Zldgh7);
+ assign ahb_haddr[14] = Cndgh7;
+ assign V39gh7 = (!Eodgh7);
+ assign ahb_haddr[18] = Hpdgh7;
+ assign P39gh7 = (!Jqdgh7);
+ assign ahb_haddr[22] = Mrdgh7;
+ assign J39gh7 = (!Osdgh7);
+ assign ahb_haddr[26] = Rtdgh7;
+ assign D39gh7 = (!Tudgh7);
+ assign ahb_haddr[30] = Wvdgh7;
+ assign Ts8gh7 = (!Ywdgh7);
+ assign Zs8gh7 = (!Zxdgh7);
+ assign Hs8gh7 = (!Bzdgh7);
+ assign Ns8gh7 = (!C0egh7);
+ assign Vr8gh7 = (!E1egh7);
+ assign Bs8gh7 = (!F2egh7);
+ assign Jr8gh7 = (!H3egh7);
+ assign Pr8gh7 = (!I4egh7);
+ assign Xq8gh7 = (!K5egh7);
+ assign Dr8gh7 = (!L6egh7);
+ assign Lq8gh7 = (!N7egh7);
+ assign Rq8gh7 = (!O8egh7);
+ assign Fq8gh7 = (!Q9egh7);
+ assign Vl8gh7 = (!Raegh7);
+ assign Jl8gh7 = (!Rbegh7);
+ assign Pl8gh7 = (!Scegh7);
+ assign Xk8gh7 = (!Udegh7);
+ assign Dl8gh7 = (!Veegh7);
+ assign Zj8gh7 = (!Xfegh7);
+ assign Fk8gh7 = (!Ygegh7);
+ assign Bj8gh7 = (!Aiegh7);
+ assign Hj8gh7 = (!Bjegh7);
+ assign Di8gh7 = (!Dkegh7);
+ assign Ji8gh7 = (!Elegh7);
+ assign Fh8gh7 = (!Gmegh7);
+ assign Lh8gh7 = (!Hnegh7);
+ assign Hg8gh7 = (!Joegh7);
+ assign Ng8gh7 = (!Jpegh7);
+ assign gpo8[7] = Kqegh7;
+ assign Fktfh7 = (!Kqegh7);
+ assign gpo8[6] = Kregh7;
+ assign Zjtfh7 = (!Kregh7);
+ assign gpo8[4] = Ksegh7;
+ assign Njtfh7 = (!Ksegh7);
+ assign gpo8[3] = Ktegh7;
+ assign Hjtfh7 = (!Ktegh7);
+ assign gpo8[2] = Kuegh7;
+ assign Bjtfh7 = (!Kuegh7);
+ assign gpo8[1] = Kvegh7;
+ assign Vitfh7 = (!Kvegh7);
+ assign Jf8gh7 = (!Kwegh7);
+ assign gpo8[5] = Kxegh7;
+ assign Tjtfh7 = (!Kxegh7);
+ assign Pf8gh7 = (!Kyegh7);
+ assign Patfh7 = Lzegh7;
+ assign R29gh7 = (!O0fgh7);
+ assign Rw8gh7 = (!P1fgh7);
+ assign X29gh7 = (!S2fgh7);
+ assign Vx8gh7 = (!V3fgh7);
+ assign Ny8gh7 = (!X4fgh7);
+ assign Px8gh7 = (!Z5fgh7);
+ assign Zy8gh7 = (!B7fgh7);
+ assign com_tx_tdata[7] = D8fgh7;
+ assign stdio_tx_tvalid = H9fgh7;
+ assign stdio_tx_tdata[7] = Hafgh7;
+ assign stdio_tx_tdata[6] = Lbfgh7;
+ assign stdio_tx_tdata[5] = Pcfgh7;
+ assign stdio_tx_tdata[4] = Tdfgh7;
+ assign stdio_tx_tdata[3] = Xefgh7;
+ assign stdio_tx_tdata[2] = Bgfgh7;
+ assign stdio_tx_tdata[1] = Fhfgh7;
+ assign ahb_hwdata[2] = Jifgh7;
+ assign Vltfh7 = (!Jifgh7);
+ assign ahb_hwdata[3] = Ojfgh7;
+ assign Bmtfh7 = (!Ojfgh7);
+ assign ahb_hwdata[5] = Tkfgh7;
+ assign Nmtfh7 = (!Tkfgh7);
+ assign ahb_hwdata[6] = Ylfgh7;
+ assign Tmtfh7 = (!Ylfgh7);
+ assign ahb_hwdata[7] = Dnfgh7;
+ assign Zmtfh7 = (!Dnfgh7);
+ assign ahb_hwdata[8] = Iofgh7;
+ assign Fntfh7 = (!Iofgh7);
+ assign ahb_hwdata[9] = Npfgh7;
+ assign Lntfh7 = (!Npfgh7);
+ assign ahb_hwdata[10] = Sqfgh7;
+ assign Rntfh7 = (!Sqfgh7);
+ assign ahb_hwdata[11] = Yrfgh7;
+ assign Xntfh7 = (!Yrfgh7);
+ assign ahb_hwdata[12] = Etfgh7;
+ assign Dotfh7 = (!Etfgh7);
+ assign ahb_hwdata[13] = Kufgh7;
+ assign Jotfh7 = (!Kufgh7);
+ assign ahb_hwdata[14] = Qvfgh7;
+ assign Potfh7 = (!Qvfgh7);
+ assign ahb_hwdata[15] = Wwfgh7;
+ assign Votfh7 = (!Wwfgh7);
+ assign ahb_hwdata[17] = Cyfgh7;
+ assign Hptfh7 = (!Cyfgh7);
+ assign ahb_hwdata[18] = Izfgh7;
+ assign Nptfh7 = (!Izfgh7);
+ assign ahb_hwdata[19] = O0ggh7;
+ assign Tptfh7 = (!O0ggh7);
+ assign ahb_hwdata[20] = U1ggh7;
+ assign Zptfh7 = (!U1ggh7);
+ assign ahb_hwdata[21] = A3ggh7;
+ assign Fqtfh7 = (!A3ggh7);
+ assign ahb_hwdata[22] = G4ggh7;
+ assign Lqtfh7 = (!G4ggh7);
+ assign ahb_hwdata[23] = M5ggh7;
+ assign Rqtfh7 = (!M5ggh7);
+ assign ahb_hwdata[24] = S6ggh7;
+ assign Xqtfh7 = (!S6ggh7);
+ assign ahb_hwdata[25] = Y7ggh7;
+ assign Drtfh7 = (!Y7ggh7);
+ assign ahb_hwdata[26] = E9ggh7;
+ assign Jrtfh7 = (!E9ggh7);
+ assign ahb_hwdata[27] = Kaggh7;
+ assign Prtfh7 = (!Kaggh7);
+ assign ahb_hwdata[28] = Qbggh7;
+ assign Vrtfh7 = (!Qbggh7);
+ assign ahb_hwdata[29] = Wcggh7;
+ assign Bstfh7 = (!Wcggh7);
+ assign ahb_hwdata[30] = Ceggh7;
+ assign Hstfh7 = (!Ceggh7);
+ assign ahb_hwdata[31] = Ifggh7;
+ assign Nstfh7 = (!Ifggh7);
+ assign Bm8gh7 = (!Ogggh7);
+ assign ahb_hwdata[4] = Phggh7;
+ assign Hmtfh7 = (!Phggh7);
+ assign stdio_tx_tdata[0] = Uiggh7;
+ assign Bp8gh7 = (!Yjggh7);
+ assign gpo8[0] = Ykggh7;
+ assign Pitfh7 = (!Ykggh7);
+ assign ahb_hwdata[16] = Ylggh7;
+ assign Bptfh7 = (!Ylggh7);
+ assign Hp8gh7 = (!Enggh7);
+ assign Nd9gh7[0] = Foggh7;
+ assign Bsufh7 = (!Foggh7);
+ assign Nd9gh7[2] = Hpggh7;
+ assign Vctfh7 = (!Hpggh7);
+ assign Nd9gh7[3] = Jqggh7;
+ assign Ndtfh7 = (!Jqggh7);
+ assign Nd9gh7[4] = Lrggh7;
+ assign Tdtfh7 = (!Lrggh7);
+ assign Nd9gh7[5] = Nsggh7;
+ assign Zdtfh7 = (!Nsggh7);
+ assign Nd9gh7[6] = Ptggh7;
+ assign Fetfh7 = (!Ptggh7);
+ assign Nd9gh7[7] = Ruggh7;
+ assign Letfh7 = (!Ruggh7);
+ assign Nd9gh7[8] = Tvggh7;
+ assign Retfh7 = (!Tvggh7);
+ assign Nd9gh7[9] = Vwggh7;
+ assign Xetfh7 = (!Vwggh7);
+ assign Nd9gh7[10] = Xxggh7;
+ assign Jitfh7 = (!Xxggh7);
+ assign Nd9gh7[11] = Azggh7;
+ assign Xhtfh7 = (!Azggh7);
+ assign Nd9gh7[12] = D0hgh7;
+ assign Ditfh7 = (!D0hgh7);
+ assign Nd9gh7[13] = G1hgh7;
+ assign Zgtfh7 = (!G1hgh7);
+ assign Nd9gh7[14] = J2hgh7;
+ assign Fhtfh7 = (!J2hgh7);
+ assign Nd9gh7[15] = M3hgh7;
+ assign Lhtfh7 = (!M3hgh7);
+ assign Nd9gh7[16] = P4hgh7;
+ assign Rhtfh7 = (!P4hgh7);
+ assign Nd9gh7[17] = S5hgh7;
+ assign Ngtfh7 = (!S5hgh7);
+ assign Nd9gh7[18] = V6hgh7;
+ assign Tgtfh7 = (!V6hgh7);
+ assign Nd9gh7[19] = Y7hgh7;
+ assign Bgtfh7 = (!Y7hgh7);
+ assign Nd9gh7[20] = B9hgh7;
+ assign Pftfh7 = (!B9hgh7);
+ assign Nd9gh7[21] = Eahgh7;
+ assign Vftfh7 = (!Eahgh7);
+ assign Nd9gh7[22] = Hbhgh7;
+ assign Dftfh7 = (!Hbhgh7);
+ assign Nd9gh7[23] = Kchgh7;
+ assign Jftfh7 = (!Kchgh7);
+ assign Nd9gh7[24] = Ndhgh7;
+ assign Obtfh7 = (!Ndhgh7);
+ assign Nd9gh7[25] = Qehgh7;
+ assign Tbtfh7 = (!Qehgh7);
+ assign Nd9gh7[26] = Tfhgh7;
+ assign Ybtfh7 = (!Tfhgh7);
+ assign Nd9gh7[27] = Wghgh7;
+ assign Dctfh7 = (!Wghgh7);
+ assign Nd9gh7[28] = Zhhgh7;
+ assign Jctfh7 = (!Zhhgh7);
+ assign Nd9gh7[29] = Cjhgh7;
+ assign Pctfh7 = (!Cjhgh7);
+ assign Nd9gh7[30] = Fkhgh7;
+ assign Bdtfh7 = (!Fkhgh7);
+ assign Nd9gh7[31] = Ilhgh7;
+ assign Hdtfh7 = (!Ilhgh7);
+ assign Re8gh7 = (!Lmhgh7);
+ assign Le8gh7 = (!Mnhgh7);
+ assign ahb_hwdata[1] = Mohgh7;
+ assign Pltfh7 = (!Mohgh7);
+ assign com_tx_tdata[5] = Rphgh7;
+ assign com_tx_tdata[4] = Vqhgh7;
+ assign com_tx_tdata[3] = Zrhgh7;
+ assign com_tx_tdata[1] = Dthgh7;
+ assign Lktfh7 = (!Dthgh7);
+ assign com_tx_tdata[6] = Huhgh7;
+ assign Rktfh7 = (!Huhgh7);
+ assign com_tx_tdata[2] = Lvhgh7;
+ assign com_tx_tdata[0] = Pwhgh7;
+ assign Txhgh7 = ({Nd9gh7, 1'b0} - {{1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, Tosfh7}, 1'b0});
+ assign {B5sfh7, R5sfh7, H6sfh7, X6sfh7, N7sfh7, D8sfh7, T8sfh7, J9sfh7,
+ Z9sfh7, Pasfh7, Fbsfh7, Vbsfh7, Lcsfh7, Bdsfh7, Rdsfh7, Hesfh7,
+ Xesfh7, Nfsfh7, Dgsfh7, Tgsfh7, Jhsfh7, Zhsfh7, Pisfh7, Fjsfh7,
+ Vjsfh7, Lksfh7, Blsfh7, Rlsfh7, Hmsfh7, Xmsfh7, Nnsfh7, Dosfh7}
+ = Txhgh7[33:1];
+ assign Wyhgh7 = ({ahb_haddr, 1'b0} + {{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, B9tfh7, 1'b0, 1'b0}, 1'b1});
+ assign {Jpsfh7, Zpsfh7, Pqsfh7, Frsfh7, Vrsfh7, Lssfh7, Btsfh7, Rtsfh7,
+ Husfh7, Xusfh7, Nvsfh7, Dwsfh7, Twsfh7, Jxsfh7, Zxsfh7, Pysfh7,
+ Fzsfh7, Vzsfh7, L0tfh7, B1tfh7, R1tfh7, H2tfh7, X2tfh7, N3tfh7,
+ D4tfh7, T4tfh7, J5tfh7, Z5tfh7, P6tfh7, F7tfh7, V7tfh7, L8tfh7}
+ = Wyhgh7[33:1];
+ assign Duufh7 = (!Juufh7);
+ assign Juufh7 = (!ahb_hresetn);
+ assign Puufh7 = (!Vuufh7);
+ assign Vuufh7 = (!ahb_hclk);
+ assign Xtufh7 = (~(Bvufh7 & Hvufh7));
+ assign Hvufh7 = (~(stdio_tx_tdata[7] & Nvufh7));
+ assign Bvufh7 = (Tvufh7 & Zvufh7);
+ assign Zvufh7 = (~(com_rx_tdata[7] & Fwufh7));
+ assign Tvufh7 = (~(Lwufh7 & Rwufh7));
+ assign Rtufh7 = (~(Xwufh7 & Dxufh7));
+ assign Dxufh7 = (~(stdio_tx_tdata[6] & Nvufh7));
+ assign Xwufh7 = (Jxufh7 & Pxufh7);
+ assign Pxufh7 = (~(com_rx_tdata[6] & Fwufh7));
+ assign Jxufh7 = (~(Lwufh7 & Vxufh7));
+ assign Ltufh7 = (~(Byufh7 & Hyufh7));
+ assign Hyufh7 = (~(stdio_tx_tdata[5] & Nvufh7));
+ assign Byufh7 = (Nyufh7 & Tyufh7);
+ assign Tyufh7 = (~(com_rx_tdata[5] & Fwufh7));
+ assign Nyufh7 = (~(Lwufh7 & Zyufh7));
+ assign Ftufh7 = (~(Fzufh7 & Lzufh7));
+ assign Lzufh7 = (~(stdio_tx_tdata[4] & Nvufh7));
+ assign Fzufh7 = (Rzufh7 & Xzufh7);
+ assign Xzufh7 = (~(Fwufh7 & com_rx_tdata[4]));
+ assign Rzufh7 = (~(Lwufh7 & D0vfh7));
+ assign Zsufh7 = (~(J0vfh7 & P0vfh7));
+ assign P0vfh7 = (~(stdio_tx_tdata[3] & Nvufh7));
+ assign J0vfh7 = (V0vfh7 & B1vfh7);
+ assign B1vfh7 = (~(Fwufh7 & com_rx_tdata[3]));
+ assign V0vfh7 = (~(Lwufh7 & H1vfh7));
+ assign Tsufh7 = (~(N1vfh7 & T1vfh7));
+ assign T1vfh7 = (~(stdio_tx_tdata[2] & Nvufh7));
+ assign N1vfh7 = (Z1vfh7 & F2vfh7);
+ assign F2vfh7 = (~(com_rx_tdata[2] & Fwufh7));
+ assign Z1vfh7 = (~(Lwufh7 & L2vfh7));
+ assign Nsufh7 = (~(R2vfh7 & X2vfh7));
+ assign X2vfh7 = (~(stdio_tx_tdata[1] & Nvufh7));
+ assign R2vfh7 = (D3vfh7 & J3vfh7);
+ assign J3vfh7 = (~(Fwufh7 & com_rx_tdata[1]));
+ assign D3vfh7 = (~(Lwufh7 & P3vfh7));
+ assign Hsufh7 = (~(V3vfh7 & B4vfh7));
+ assign B4vfh7 = (~(stdio_tx_tdata[0] & Nvufh7));
+ assign V3vfh7 = (H4vfh7 & N4vfh7);
+ assign N4vfh7 = (~(Fwufh7 & com_rx_tdata[0]));
+ assign Fwufh7 = (~(Nvufh7 | T4vfh7));
+ assign H4vfh7 = (~(Lwufh7 & Z4vfh7));
+ assign Lwufh7 = (~(F5vfh7 | Nvufh7));
+ assign Nvufh7 = (~(L5vfh7 & stdio_tx_tready));
+ assign L5vfh7 = (Duufh7 & R5vfh7);
+ assign R5vfh7 = (X5vfh7 | D6vfh7);
+ assign Prufh7 = (~(J6vfh7 & P6vfh7));
+ assign J6vfh7 = (B7vfh7 ? V6vfh7 : Rb9gh7);
+ assign Jrufh7 = (B7vfh7 ? com_rx_tdata[7] : H7vfh7);
+ assign H7vfh7 = (!Zd8gh7);
+ assign Drufh7 = (B7vfh7 ? com_rx_tdata[6] : N7vfh7);
+ assign Xqufh7 = (~(T7vfh7 & P6vfh7));
+ assign T7vfh7 = (B7vfh7 ? Z7vfh7 : Fb9gh7);
+ assign Rqufh7 = (B7vfh7 ? com_rx_tdata[3] : F8vfh7);
+ assign Lqufh7 = (~(L8vfh7 & P6vfh7));
+ assign L8vfh7 = (B7vfh7 ? R8vfh7 : Ta9gh7);
+ assign Fqufh7 = (~(X8vfh7 & P6vfh7));
+ assign P6vfh7 = (~(D9vfh7 & B7vfh7));
+ assign X8vfh7 = (B7vfh7 ? J9vfh7 : Na9gh7);
+ assign B7vfh7 = (~(P9vfh7 & V9vfh7));
+ assign Zpufh7 = (Havfh7 ? ahb_hwrite : Bavfh7);
+ assign Bavfh7 = (~(Navfh7 & Tavfh7));
+ assign Navfh7 = (Zavfh7 & Fbvfh7);
+ assign Zavfh7 = (Lbvfh7 | Rbvfh7);
+ assign Tpufh7 = (~(Xbvfh7 & Dcvfh7));
+ assign Dcvfh7 = (Jcvfh7 & Pcvfh7);
+ assign Pcvfh7 = (~(Vcvfh7 & Bdvfh7));
+ assign Jcvfh7 = (Hdvfh7 & Ndvfh7);
+ assign Hdvfh7 = (~(Tdvfh7 & Zdvfh7));
+ assign Xbvfh7 = (Fevfh7 & Levfh7);
+ assign Levfh7 = (~(Revfh7 & ahb_haddr[31]));
+ assign Fevfh7 = (Xevfh7 & Dfvfh7);
+ assign Dfvfh7 = (~(Jfvfh7 & Pfvfh7));
+ assign Xevfh7 = (Vfvfh7 | Pl8gh7);
+ assign Npufh7 = (~(Bgvfh7 & Hgvfh7));
+ assign Hgvfh7 = (Ngvfh7 & Tgvfh7);
+ assign Tgvfh7 = (~(Jfvfh7 & Zgvfh7));
+ assign Ngvfh7 = (Fhvfh7 & Ndvfh7);
+ assign Fhvfh7 = (~(Lhvfh7 & Rhvfh7));
+ assign Lhvfh7 = (com_rx_tdata[0] ? Divfh7 : Xhvfh7);
+ assign Divfh7 = (~(Jivfh7 & Pivfh7));
+ assign Xhvfh7 = (Vivfh7 & Bjvfh7);
+ assign Bgvfh7 = (Hjvfh7 & Njvfh7);
+ assign Njvfh7 = (~(Revfh7 & ahb_haddr[0]));
+ assign Hjvfh7 = (Tjvfh7 & Zjvfh7);
+ assign Zjvfh7 = (~(Fkvfh7 & Z4vfh7));
+ assign Tjvfh7 = (Vfvfh7 | Hp8gh7);
+ assign Hpufh7 = (~(Lkvfh7 & Rkvfh7));
+ assign Rkvfh7 = (Xkvfh7 & Dlvfh7);
+ assign Dlvfh7 = (~(Vcvfh7 & Jlvfh7));
+ assign Xkvfh7 = (Plvfh7 & Ndvfh7);
+ assign Plvfh7 = (~(Tdvfh7 & Vlvfh7));
+ assign Lkvfh7 = (Bmvfh7 & Hmvfh7);
+ assign Hmvfh7 = (~(Revfh7 & ahb_haddr[30]));
+ assign Bmvfh7 = (Nmvfh7 & Tmvfh7);
+ assign Tmvfh7 = (~(Jfvfh7 & Zmvfh7));
+ assign Nmvfh7 = (Vfvfh7 | Zs8gh7);
+ assign Bpufh7 = (~(Fnvfh7 & Lnvfh7));
+ assign Lnvfh7 = (Rnvfh7 & Xnvfh7);
+ assign Xnvfh7 = (~(Vcvfh7 & Dovfh7));
+ assign Rnvfh7 = (Jovfh7 & Ndvfh7);
+ assign Jovfh7 = (~(Tdvfh7 & Povfh7));
+ assign Fnvfh7 = (Vovfh7 & Bpvfh7);
+ assign Bpvfh7 = (~(Revfh7 & ahb_haddr[29]));
+ assign Vovfh7 = (Hpvfh7 & Npvfh7);
+ assign Npvfh7 = (~(Jfvfh7 & Tpvfh7));
+ assign Hpvfh7 = (Vfvfh7 | Dl8gh7);
+ assign Voufh7 = (~(Zpvfh7 & Fqvfh7));
+ assign Fqvfh7 = (Lqvfh7 & Rqvfh7);
+ assign Rqvfh7 = (~(Vcvfh7 & Xqvfh7));
+ assign Lqvfh7 = (Drvfh7 & Ndvfh7);
+ assign Drvfh7 = (~(Tdvfh7 & Jrvfh7));
+ assign Zpvfh7 = (Prvfh7 & Vrvfh7);
+ assign Vrvfh7 = (~(Revfh7 & ahb_haddr[28]));
+ assign Prvfh7 = (Bsvfh7 & Hsvfh7);
+ assign Hsvfh7 = (~(Jfvfh7 & Nsvfh7));
+ assign Bsvfh7 = (Vfvfh7 | Xn8gh7);
+ assign Poufh7 = (~(Tsvfh7 & Zsvfh7));
+ assign Zsvfh7 = (Ftvfh7 & Ltvfh7);
+ assign Ltvfh7 = (~(Vcvfh7 & Zdvfh7));
+ assign Ftvfh7 = (Rtvfh7 & Ndvfh7);
+ assign Rtvfh7 = (~(Tdvfh7 & Xtvfh7));
+ assign Tsvfh7 = (Duvfh7 & Juvfh7);
+ assign Juvfh7 = (~(Revfh7 & ahb_haddr[27]));
+ assign Duvfh7 = (Puvfh7 & Vuvfh7);
+ assign Vuvfh7 = (~(Jfvfh7 & Bvvfh7));
+ assign Puvfh7 = (Vfvfh7 | Rk8gh7);
+ assign Joufh7 = (~(Hvvfh7 & Nvvfh7));
+ assign Nvvfh7 = (Tvvfh7 & Zvvfh7);
+ assign Zvvfh7 = (~(Vcvfh7 & Vlvfh7));
+ assign Tvvfh7 = (Fwvfh7 & Ndvfh7);
+ assign Fwvfh7 = (~(Tdvfh7 & Lwvfh7));
+ assign Hvvfh7 = (Rwvfh7 & Xwvfh7);
+ assign Xwvfh7 = (~(Revfh7 & ahb_haddr[26]));
+ assign Rwvfh7 = (Dxvfh7 & Jxvfh7);
+ assign Jxvfh7 = (~(Jfvfh7 & Pxvfh7));
+ assign Dxvfh7 = (Vfvfh7 | Ns8gh7);
+ assign Doufh7 = (~(Vxvfh7 & Byvfh7));
+ assign Byvfh7 = (Hyvfh7 & Nyvfh7);
+ assign Nyvfh7 = (~(Vcvfh7 & Povfh7));
+ assign Hyvfh7 = (Tyvfh7 & Ndvfh7);
+ assign Tyvfh7 = (~(Tdvfh7 & Zyvfh7));
+ assign Vxvfh7 = (Fzvfh7 & Lzvfh7);
+ assign Lzvfh7 = (~(Revfh7 & ahb_haddr[25]));
+ assign Fzvfh7 = (Rzvfh7 & Xzvfh7);
+ assign Xzvfh7 = (~(Jfvfh7 & D0wfh7));
+ assign Rzvfh7 = (Vfvfh7 | Fk8gh7);
+ assign Xnufh7 = (~(J0wfh7 & P0wfh7));
+ assign P0wfh7 = (V0wfh7 & B1wfh7);
+ assign B1wfh7 = (~(Vcvfh7 & Jrvfh7));
+ assign V0wfh7 = (H1wfh7 & Ndvfh7);
+ assign H1wfh7 = (~(Tdvfh7 & N1wfh7));
+ assign J0wfh7 = (T1wfh7 & Z1wfh7);
+ assign Z1wfh7 = (~(Revfh7 & ahb_haddr[24]));
+ assign T1wfh7 = (F2wfh7 & L2wfh7);
+ assign L2wfh7 = (~(Jfvfh7 & R2wfh7));
+ assign F2wfh7 = (Vfvfh7 | Jo8gh7);
+ assign Rnufh7 = (~(X2wfh7 & D3wfh7));
+ assign D3wfh7 = (J3wfh7 & P3wfh7);
+ assign P3wfh7 = (~(Vcvfh7 & Xtvfh7));
+ assign J3wfh7 = (V3wfh7 & Ndvfh7);
+ assign V3wfh7 = (~(Tdvfh7 & B4wfh7));
+ assign X2wfh7 = (H4wfh7 & N4wfh7);
+ assign N4wfh7 = (~(Revfh7 & ahb_haddr[23]));
+ assign H4wfh7 = (T4wfh7 & Z4wfh7);
+ assign Z4wfh7 = (~(Jfvfh7 & F5wfh7));
+ assign T4wfh7 = (Vfvfh7 | Tj8gh7);
+ assign Lnufh7 = (~(L5wfh7 & R5wfh7));
+ assign R5wfh7 = (X5wfh7 & D6wfh7);
+ assign D6wfh7 = (~(Vcvfh7 & Lwvfh7));
+ assign X5wfh7 = (J6wfh7 & Ndvfh7);
+ assign J6wfh7 = (~(Tdvfh7 & P6wfh7));
+ assign L5wfh7 = (V6wfh7 & B7wfh7);
+ assign B7wfh7 = (~(Revfh7 & ahb_haddr[22]));
+ assign V6wfh7 = (H7wfh7 & N7wfh7);
+ assign N7wfh7 = (~(Jfvfh7 & T7wfh7));
+ assign H7wfh7 = (Vfvfh7 | Bs8gh7);
+ assign Fnufh7 = (~(Z7wfh7 & F8wfh7));
+ assign F8wfh7 = (L8wfh7 & R8wfh7);
+ assign R8wfh7 = (~(Vcvfh7 & Zyvfh7));
+ assign L8wfh7 = (X8wfh7 & Ndvfh7);
+ assign X8wfh7 = (~(Tdvfh7 & D9wfh7));
+ assign Z7wfh7 = (J9wfh7 & P9wfh7);
+ assign P9wfh7 = (~(Revfh7 & ahb_haddr[21]));
+ assign J9wfh7 = (V9wfh7 & Bawfh7);
+ assign Bawfh7 = (~(Jfvfh7 & Hawfh7));
+ assign V9wfh7 = (Vfvfh7 | Hj8gh7);
+ assign Zmufh7 = (~(Nawfh7 & Tawfh7));
+ assign Tawfh7 = (Zawfh7 & Fbwfh7);
+ assign Fbwfh7 = (~(Vcvfh7 & N1wfh7));
+ assign Zawfh7 = (Lbwfh7 & Ndvfh7);
+ assign Lbwfh7 = (~(Tdvfh7 & Rbwfh7));
+ assign Nawfh7 = (Xbwfh7 & Dcwfh7);
+ assign Dcwfh7 = (~(Revfh7 & ahb_haddr[20]));
+ assign Xbwfh7 = (Jcwfh7 & Pcwfh7);
+ assign Pcwfh7 = (~(Jfvfh7 & Vcwfh7));
+ assign Jcwfh7 = (Vfvfh7 | Ln8gh7);
+ assign Tmufh7 = (~(Bdwfh7 & Hdwfh7));
+ assign Hdwfh7 = (Ndwfh7 & Tdwfh7);
+ assign Tdwfh7 = (~(Vcvfh7 & B4wfh7));
+ assign Ndwfh7 = (Zdwfh7 & Ndvfh7);
+ assign Zdwfh7 = (~(Tdvfh7 & Fewfh7));
+ assign Bdwfh7 = (Lewfh7 & Rewfh7);
+ assign Rewfh7 = (~(Revfh7 & ahb_haddr[19]));
+ assign Lewfh7 = (Xewfh7 & Dfwfh7);
+ assign Dfwfh7 = (~(Jfvfh7 & Jfwfh7));
+ assign Xewfh7 = (Vfvfh7 | Vi8gh7);
+ assign Nmufh7 = (~(Pfwfh7 & Vfwfh7));
+ assign Vfwfh7 = (Bgwfh7 & Hgwfh7);
+ assign Hgwfh7 = (~(Vcvfh7 & P6wfh7));
+ assign Bgwfh7 = (Ngwfh7 & Ndvfh7);
+ assign Ngwfh7 = (~(Tdvfh7 & Tgwfh7));
+ assign Pfwfh7 = (Zgwfh7 & Fhwfh7);
+ assign Fhwfh7 = (~(Revfh7 & ahb_haddr[18]));
+ assign Zgwfh7 = (Lhwfh7 & Rhwfh7);
+ assign Rhwfh7 = (~(Jfvfh7 & Xhwfh7));
+ assign Lhwfh7 = (Vfvfh7 | Pr8gh7);
+ assign Hmufh7 = (~(Diwfh7 & Jiwfh7));
+ assign Jiwfh7 = (Piwfh7 & Viwfh7);
+ assign Viwfh7 = (~(Vcvfh7 & D9wfh7));
+ assign Piwfh7 = (Bjwfh7 & Ndvfh7);
+ assign Bjwfh7 = (~(Tdvfh7 & Hjwfh7));
+ assign Diwfh7 = (Njwfh7 & Tjwfh7);
+ assign Tjwfh7 = (~(Revfh7 & ahb_haddr[17]));
+ assign Njwfh7 = (Zjwfh7 & Fkwfh7);
+ assign Fkwfh7 = (~(Jfvfh7 & Lkwfh7));
+ assign Zjwfh7 = (Vfvfh7 | Ji8gh7);
+ assign Bmufh7 = (~(Rkwfh7 & Xkwfh7));
+ assign Xkwfh7 = (Dlwfh7 & Jlwfh7);
+ assign Jlwfh7 = (~(Vcvfh7 & Rbwfh7));
+ assign Dlwfh7 = (Plwfh7 & Ndvfh7);
+ assign Plwfh7 = (~(Tdvfh7 & Vlwfh7));
+ assign Rkwfh7 = (Bmwfh7 & Hmwfh7);
+ assign Hmwfh7 = (~(Revfh7 & ahb_haddr[16]));
+ assign Bmwfh7 = (Nmwfh7 & Tmwfh7);
+ assign Tmwfh7 = (~(Jfvfh7 & Zmwfh7));
+ assign Nmwfh7 = (Vfvfh7 | Vo8gh7);
+ assign Vlufh7 = (~(Fnwfh7 & Lnwfh7));
+ assign Lnwfh7 = (Rnwfh7 & Xnwfh7);
+ assign Xnwfh7 = (~(Vcvfh7 & Fewfh7));
+ assign Rnwfh7 = (Dowfh7 & Ndvfh7);
+ assign Dowfh7 = (~(Tdvfh7 & Jowfh7));
+ assign Fnwfh7 = (Powfh7 & Vowfh7);
+ assign Vowfh7 = (~(Revfh7 & ahb_haddr[15]));
+ assign Powfh7 = (Bpwfh7 & Hpwfh7);
+ assign Hpwfh7 = (~(Jfvfh7 & Npwfh7));
+ assign Bpwfh7 = (Vfvfh7 | Xh8gh7);
+ assign Plufh7 = (~(Tpwfh7 & Zpwfh7));
+ assign Zpwfh7 = (Fqwfh7 & Lqwfh7);
+ assign Lqwfh7 = (~(Vcvfh7 & Tgwfh7));
+ assign Fqwfh7 = (Rqwfh7 & Ndvfh7);
+ assign Rqwfh7 = (~(Tdvfh7 & Xqwfh7));
+ assign Tpwfh7 = (Drwfh7 & Jrwfh7);
+ assign Jrwfh7 = (~(Revfh7 & ahb_haddr[14]));
+ assign Drwfh7 = (Prwfh7 & Vrwfh7);
+ assign Vrwfh7 = (~(Jfvfh7 & Bswfh7));
+ assign Prwfh7 = (Vfvfh7 | Dr8gh7);
+ assign Jlufh7 = (~(Hswfh7 & Nswfh7));
+ assign Nswfh7 = (Tswfh7 & Zswfh7);
+ assign Zswfh7 = (~(Vcvfh7 & Hjwfh7));
+ assign Tswfh7 = (Ftwfh7 & Ndvfh7);
+ assign Ftwfh7 = (~(Tdvfh7 & Ltwfh7));
+ assign Hswfh7 = (Rtwfh7 & Xtwfh7);
+ assign Xtwfh7 = (~(Revfh7 & ahb_haddr[13]));
+ assign Rtwfh7 = (Duwfh7 & Juwfh7);
+ assign Juwfh7 = (~(Jfvfh7 & Puwfh7));
+ assign Duwfh7 = (Vfvfh7 | Lh8gh7);
+ assign Dlufh7 = (~(Vuwfh7 & Bvwfh7));
+ assign Bvwfh7 = (Hvwfh7 & Nvwfh7);
+ assign Nvwfh7 = (~(Vcvfh7 & Vlwfh7));
+ assign Hvwfh7 = (Tvwfh7 & Ndvfh7);
+ assign Tvwfh7 = (~(Tdvfh7 & Zvwfh7));
+ assign Vuwfh7 = (Fwwfh7 & Lwwfh7);
+ assign Lwwfh7 = (~(Revfh7 & ahb_haddr[12]));
+ assign Fwwfh7 = (Rwwfh7 & Xwwfh7);
+ assign Xwwfh7 = (~(Jfvfh7 & Dxwfh7));
+ assign Rwwfh7 = (Vfvfh7 | Nm8gh7);
+ assign Xkufh7 = (~(Jxwfh7 & Pxwfh7));
+ assign Pxwfh7 = (Vxwfh7 & Bywfh7);
+ assign Bywfh7 = (~(Vcvfh7 & Jowfh7));
+ assign Vxwfh7 = (Hywfh7 & Ndvfh7);
+ assign Hywfh7 = (~(Tdvfh7 & Rwufh7));
+ assign Jxwfh7 = (Nywfh7 & Tywfh7);
+ assign Tywfh7 = (~(Revfh7 & ahb_haddr[11]));
+ assign Nywfh7 = (Zywfh7 & Fzwfh7);
+ assign Fzwfh7 = (~(Jfvfh7 & Lzwfh7));
+ assign Zywfh7 = (Vfvfh7 | Zg8gh7);
+ assign Rkufh7 = (~(Rzwfh7 & Xzwfh7));
+ assign Xzwfh7 = (D0xfh7 & J0xfh7);
+ assign J0xfh7 = (~(Vcvfh7 & Xqwfh7));
+ assign D0xfh7 = (P0xfh7 & Ndvfh7);
+ assign P0xfh7 = (~(Tdvfh7 & Vxufh7));
+ assign Rzwfh7 = (V0xfh7 & B1xfh7);
+ assign B1xfh7 = (~(Revfh7 & ahb_haddr[10]));
+ assign V0xfh7 = (H1xfh7 & N1xfh7);
+ assign N1xfh7 = (~(Jfvfh7 & T1xfh7));
+ assign H1xfh7 = (Vfvfh7 | Rq8gh7);
+ assign Lkufh7 = (~(Z1xfh7 & F2xfh7));
+ assign F2xfh7 = (L2xfh7 & R2xfh7);
+ assign R2xfh7 = (~(Vcvfh7 & Ltwfh7));
+ assign L2xfh7 = (X2xfh7 & Ndvfh7);
+ assign X2xfh7 = (~(Tdvfh7 & Zyufh7));
+ assign Z1xfh7 = (D3xfh7 & J3xfh7);
+ assign J3xfh7 = (~(Revfh7 & ahb_haddr[9]));
+ assign D3xfh7 = (P3xfh7 & V3xfh7);
+ assign V3xfh7 = (~(Jfvfh7 & B4xfh7));
+ assign P3xfh7 = (Vfvfh7 | Ng8gh7);
+ assign Fkufh7 = (~(H4xfh7 & N4xfh7));
+ assign N4xfh7 = (T4xfh7 & Z4xfh7);
+ assign Z4xfh7 = (~(Vcvfh7 & Zvwfh7));
+ assign T4xfh7 = (F5xfh7 & Ndvfh7);
+ assign F5xfh7 = (~(Tdvfh7 & D0vfh7));
+ assign H4xfh7 = (L5xfh7 & R5xfh7);
+ assign R5xfh7 = (~(Revfh7 & ahb_haddr[8]));
+ assign L5xfh7 = (X5xfh7 & D6xfh7);
+ assign D6xfh7 = (~(Jfvfh7 & J6xfh7));
+ assign X5xfh7 = (Vfvfh7 | Zm8gh7);
+ assign Zjufh7 = (~(P6xfh7 & V6xfh7));
+ assign V6xfh7 = (B7xfh7 & H7xfh7);
+ assign H7xfh7 = (~(Vcvfh7 & Rwufh7));
+ assign B7xfh7 = (N7xfh7 & Ndvfh7);
+ assign N7xfh7 = (~(Tdvfh7 & H1vfh7));
+ assign P6xfh7 = (T7xfh7 & Z7xfh7);
+ assign Z7xfh7 = (~(Revfh7 & ahb_haddr[7]));
+ assign T7xfh7 = (F8xfh7 & L8xfh7);
+ assign L8xfh7 = (~(Jfvfh7 & R8xfh7));
+ assign F8xfh7 = (Vfvfh7 | Bg8gh7);
+ assign Tjufh7 = (~(X8xfh7 & D9xfh7));
+ assign D9xfh7 = (J9xfh7 & P9xfh7);
+ assign P9xfh7 = (~(Vcvfh7 & Vxufh7));
+ assign J9xfh7 = (V9xfh7 & Ndvfh7);
+ assign V9xfh7 = (~(Tdvfh7 & L2vfh7));
+ assign X8xfh7 = (Baxfh7 & Haxfh7);
+ assign Haxfh7 = (~(Revfh7 & ahb_haddr[6]));
+ assign Baxfh7 = (Naxfh7 & Taxfh7);
+ assign Taxfh7 = (~(Jfvfh7 & Zaxfh7));
+ assign Naxfh7 = (Vfvfh7 | Fq8gh7);
+ assign Njufh7 = (~(Fbxfh7 & Lbxfh7));
+ assign Lbxfh7 = (Rbxfh7 & Xbxfh7);
+ assign Xbxfh7 = (~(Vcvfh7 & Zyufh7));
+ assign Rbxfh7 = (Dcxfh7 & Ndvfh7);
+ assign Dcxfh7 = (~(Tdvfh7 & P3vfh7));
+ assign Fbxfh7 = (Jcxfh7 & Pcxfh7);
+ assign Pcxfh7 = (~(Revfh7 & ahb_haddr[5]));
+ assign Jcxfh7 = (Vcxfh7 & Bdxfh7);
+ assign Bdxfh7 = (~(Jfvfh7 & Hdxfh7));
+ assign Vcxfh7 = (Vfvfh7 | Pf8gh7);
+ assign Hjufh7 = (~(Ndxfh7 & Tdxfh7));
+ assign Tdxfh7 = (Zdxfh7 & Fexfh7);
+ assign Fexfh7 = (~(Vcvfh7 & D0vfh7));
+ assign Vcvfh7 = (~(Lexfh7 & Rexfh7));
+ assign Rexfh7 = (~(Xexfh7 & Dfxfh7));
+ assign Zdxfh7 = (Jfxfh7 & Ndvfh7);
+ assign Jfxfh7 = (~(Tdvfh7 & Z4vfh7));
+ assign Tdvfh7 = (Rhvfh7 & Pfxfh7);
+ assign Pfxfh7 = (Vfxfh7 | Bgxfh7);
+ assign Ndxfh7 = (Hgxfh7 & Ngxfh7);
+ assign Ngxfh7 = (~(Revfh7 & ahb_haddr[4]));
+ assign Hgxfh7 = (Tgxfh7 & Zgxfh7);
+ assign Zgxfh7 = (~(Jfvfh7 & Fhxfh7));
+ assign Tgxfh7 = (Vfvfh7 | Bm8gh7);
+ assign Bjufh7 = (~(Lhxfh7 & Rhxfh7));
+ assign Rhxfh7 = (Xhxfh7 & Dixfh7);
+ assign Dixfh7 = (~(Jfvfh7 & Jixfh7));
+ assign Xhxfh7 = (Pixfh7 & Ndvfh7);
+ assign Pixfh7 = (~(Rhvfh7 & Vfxfh7));
+ assign Vfxfh7 = (~(Vixfh7 & Bjxfh7));
+ assign Vixfh7 = (Hjxfh7 & Jivfh7);
+ assign Jivfh7 = (~(Njxfh7 & Tjxfh7));
+ assign Njxfh7 = (Zjxfh7 & com_rx_tdata[3]);
+ assign Lhxfh7 = (Fkxfh7 & Lkxfh7);
+ assign Lkxfh7 = (~(Revfh7 & ahb_haddr[3]));
+ assign Fkxfh7 = (Rkxfh7 & Xkxfh7);
+ assign Xkxfh7 = (~(Fkvfh7 & H1vfh7));
+ assign Rkxfh7 = (Vfvfh7 | Df8gh7);
+ assign Viufh7 = (~(Dlxfh7 & Jlxfh7));
+ assign Jlxfh7 = (Plxfh7 & Vlxfh7);
+ assign Vlxfh7 = (~(Jfvfh7 & Bmxfh7));
+ assign Plxfh7 = (Hmxfh7 & Ndvfh7);
+ assign Hmxfh7 = (~(Rhvfh7 & Nmxfh7));
+ assign Nmxfh7 = (~(Bjxfh7 & Tmxfh7));
+ assign Tmxfh7 = (~(com_rx_tdata[2] & Zmxfh7));
+ assign Zmxfh7 = (~(Pivfh7 & Fnxfh7));
+ assign Fnxfh7 = (~(Vivfh7 & J9vfh7));
+ assign Pivfh7 = (!Bgxfh7);
+ assign Bjxfh7 = (~(Lnxfh7 & Vivfh7));
+ assign Lnxfh7 = (Rnxfh7 & Bjvfh7);
+ assign Rnxfh7 = (R8vfh7 ^ V6vfh7);
+ assign Dlxfh7 = (Xnxfh7 & Doxfh7);
+ assign Doxfh7 = (~(Revfh7 & ahb_haddr[2]));
+ assign Xnxfh7 = (Joxfh7 & Poxfh7);
+ assign Poxfh7 = (~(Fkvfh7 & L2vfh7));
+ assign Joxfh7 = (Vfvfh7 | Tp8gh7);
+ assign Piufh7 = (~(Voxfh7 & Bpxfh7));
+ assign Bpxfh7 = (Hpxfh7 & Npxfh7);
+ assign Npxfh7 = (~(Jfvfh7 & Tpxfh7));
+ assign Jfvfh7 = (Zpxfh7 & Fqxfh7);
+ assign Zpxfh7 = (Lqxfh7 & Rqxfh7);
+ assign Hpxfh7 = (Xqxfh7 & Ndvfh7);
+ assign Ndvfh7 = (Drxfh7 | Jrxfh7);
+ assign Xqxfh7 = (~(Rhvfh7 & Prxfh7));
+ assign Prxfh7 = (~(Hjxfh7 & Vrxfh7));
+ assign Vrxfh7 = (~(Bgxfh7 & com_rx_tdata[1]));
+ assign Bgxfh7 = (Tjxfh7 & Bsxfh7);
+ assign Tjxfh7 = (Hsxfh7 & com_rx_tdata[5]);
+ assign Hsxfh7 = (~(Z7vfh7 | com_rx_tdata[6]));
+ assign Hjxfh7 = (~(Nsxfh7 & Vivfh7));
+ assign Vivfh7 = (Tsxfh7 & com_rx_tdata[6]);
+ assign Tsxfh7 = (Bsxfh7 & Z7vfh7);
+ assign Nsxfh7 = (~(Zsxfh7 | Ftxfh7));
+ assign Zsxfh7 = (V6vfh7 & J9vfh7);
+ assign Voxfh7 = (Ltxfh7 & Rtxfh7);
+ assign Rtxfh7 = (~(Revfh7 & ahb_haddr[1]));
+ assign Revfh7 = (~(Xtxfh7 | Jrxfh7));
+ assign Ltxfh7 = (Duxfh7 & Juxfh7);
+ assign Juxfh7 = (~(Fkvfh7 & P3vfh7));
+ assign Fkvfh7 = (~(Lexfh7 & Puxfh7));
+ assign Puxfh7 = (~(Rhvfh7 & Dfxfh7));
+ assign Dfxfh7 = (~(Vuxfh7 & Bvxfh7));
+ assign Bvxfh7 = (~(Hvxfh7 | Nvxfh7));
+ assign Vuxfh7 = (Tvxfh7 & Zvxfh7);
+ assign Zvxfh7 = (~(Z7vfh7 & Fwxfh7));
+ assign Fwxfh7 = (~(Lwxfh7 & Rwxfh7));
+ assign Rwxfh7 = (com_rx_tdata[6] ? Dxxfh7 : Xwxfh7);
+ assign Dxxfh7 = (~(Zjxfh7 & V6vfh7));
+ assign Xwxfh7 = (~(com_rx_tdata[0] & Bsxfh7));
+ assign Lwxfh7 = (Jxxfh7 & Pxxfh7);
+ assign Pxxfh7 = (~(Ftxfh7 & com_rx_tdata[2]));
+ assign Jxxfh7 = (~(com_rx_tdata[5] & com_rx_tdata[3]));
+ assign Tvxfh7 = (com_rx_tdata[6] ? Byxfh7 : Vxxfh7);
+ assign Byxfh7 = (Bsxfh7 ? Z7vfh7 : V6vfh7);
+ assign Vxxfh7 = (~(Hyxfh7 | Nyxfh7));
+ assign Hyxfh7 = (Z7vfh7 & Bjvfh7);
+ assign Rhvfh7 = (Tyxfh7 & Xexfh7);
+ assign Tyxfh7 = (~(Jrxfh7 | com_rx_tdata[7]));
+ assign Lexfh7 = (Zyxfh7 & Fzxfh7);
+ assign Fzxfh7 = (~(Lzxfh7 | Jrxfh7));
+ assign Jrxfh7 = (Rzxfh7 & Xzxfh7);
+ assign Xzxfh7 = (D0yfh7 & V9vfh7);
+ assign Rzxfh7 = (J0yfh7 & P0yfh7);
+ assign P0yfh7 = (~(Xexfh7 & V0yfh7));
+ assign J0yfh7 = (Xtxfh7 | B1yfh7);
+ assign Zyxfh7 = (H1yfh7 & N1yfh7);
+ assign H1yfh7 = (~(Xexfh7 & com_rx_tdata[7]));
+ assign Duxfh7 = (Vfvfh7 | Re8gh7);
+ assign Vfvfh7 = (~(T1yfh7 & Lqxfh7));
+ assign T1yfh7 = (Z1yfh7 & Rqxfh7);
+ assign Jiufh7 = (!F2yfh7);
+ assign F2yfh7 = (N1yfh7 ? Hp8gh7 : Jc9gh7);
+ assign Diufh7 = (!L2yfh7);
+ assign L2yfh7 = (N1yfh7 ? Zs8gh7 : D39gh7);
+ assign Xhufh7 = (!R2yfh7);
+ assign R2yfh7 = (N1yfh7 ? Dl8gh7 : F89gh7);
+ assign Rhufh7 = (!X2yfh7);
+ assign X2yfh7 = (N1yfh7 ? Xn8gh7 : D69gh7);
+ assign Lhufh7 = (!D3yfh7);
+ assign D3yfh7 = (N1yfh7 ? Rk8gh7 : T49gh7);
+ assign Fhufh7 = (!J3yfh7);
+ assign J3yfh7 = (N1yfh7 ? Ns8gh7 : J39gh7);
+ assign Zgufh7 = (!P3yfh7);
+ assign P3yfh7 = (N1yfh7 ? Fk8gh7 : L89gh7);
+ assign Tgufh7 = (!V3yfh7);
+ assign V3yfh7 = (N1yfh7 ? Jo8gh7 : J69gh7);
+ assign Ngufh7 = (!B4yfh7);
+ assign B4yfh7 = (N1yfh7 ? Tj8gh7 : Z49gh7);
+ assign Hgufh7 = (!H4yfh7);
+ assign H4yfh7 = (N1yfh7 ? Bs8gh7 : P39gh7);
+ assign Bgufh7 = (!N4yfh7);
+ assign N4yfh7 = (N1yfh7 ? Hj8gh7 : R89gh7);
+ assign Vfufh7 = (!T4yfh7);
+ assign T4yfh7 = (N1yfh7 ? Ln8gh7 : P69gh7);
+ assign Pfufh7 = (!Z4yfh7);
+ assign Z4yfh7 = (N1yfh7 ? Vi8gh7 : F59gh7);
+ assign Jfufh7 = (!F5yfh7);
+ assign F5yfh7 = (N1yfh7 ? Pr8gh7 : V39gh7);
+ assign Dfufh7 = (!L5yfh7);
+ assign L5yfh7 = (N1yfh7 ? Ji8gh7 : X89gh7);
+ assign Xeufh7 = (!R5yfh7);
+ assign R5yfh7 = (N1yfh7 ? Vo8gh7 : V69gh7);
+ assign Reufh7 = (!X5yfh7);
+ assign X5yfh7 = (N1yfh7 ? Xh8gh7 : L59gh7);
+ assign Leufh7 = (!D6yfh7);
+ assign D6yfh7 = (N1yfh7 ? Dr8gh7 : B49gh7);
+ assign Feufh7 = (!J6yfh7);
+ assign J6yfh7 = (N1yfh7 ? Lh8gh7 : D99gh7);
+ assign Zdufh7 = (!P6yfh7);
+ assign P6yfh7 = (N1yfh7 ? Nm8gh7 : B79gh7);
+ assign Tdufh7 = (!V6yfh7);
+ assign V6yfh7 = (N1yfh7 ? Zg8gh7 : R59gh7);
+ assign Ndufh7 = (!B7yfh7);
+ assign B7yfh7 = (N1yfh7 ? Rq8gh7 : H49gh7);
+ assign Hdufh7 = (!H7yfh7);
+ assign H7yfh7 = (N1yfh7 ? Ng8gh7 : J99gh7);
+ assign Bdufh7 = (!N7yfh7);
+ assign N7yfh7 = (N1yfh7 ? Zm8gh7 : H79gh7);
+ assign Vcufh7 = (!T7yfh7);
+ assign T7yfh7 = (N1yfh7 ? Bg8gh7 : X59gh7);
+ assign Pcufh7 = (!Z7yfh7);
+ assign Z7yfh7 = (N1yfh7 ? Fq8gh7 : N49gh7);
+ assign Jcufh7 = (!F8yfh7);
+ assign F8yfh7 = (N1yfh7 ? Pf8gh7 : P99gh7);
+ assign Dcufh7 = (!L8yfh7);
+ assign L8yfh7 = (N1yfh7 ? Bm8gh7 : Dc9gh7);
+ assign Xbufh7 = (!R8yfh7);
+ assign R8yfh7 = (N1yfh7 ? Df8gh7 : N79gh7);
+ assign Rbufh7 = (!X8yfh7);
+ assign X8yfh7 = (D9yfh7 ? T79gh7 : Tp8gh7);
+ assign Lbufh7 = (!J9yfh7);
+ assign J9yfh7 = (N1yfh7 ? Re8gh7 : Vc9gh7);
+ assign N1yfh7 = (!D9yfh7);
+ assign Fbufh7 = (P9yfh7 ? Zgvfh7 : Z4vfh7);
+ assign Zaufh7 = (P9yfh7 ? Zmvfh7 : Jlvfh7);
+ assign Taufh7 = (P9yfh7 ? Tpvfh7 : Dovfh7);
+ assign Naufh7 = (P9yfh7 ? Nsvfh7 : Xqvfh7);
+ assign Haufh7 = (P9yfh7 ? Bvvfh7 : Zdvfh7);
+ assign Baufh7 = (P9yfh7 ? Pxvfh7 : Vlvfh7);
+ assign V9ufh7 = (P9yfh7 ? D0wfh7 : Povfh7);
+ assign P9ufh7 = (P9yfh7 ? R2wfh7 : Jrvfh7);
+ assign J9ufh7 = (P9yfh7 ? F5wfh7 : Xtvfh7);
+ assign D9ufh7 = (P9yfh7 ? T7wfh7 : Lwvfh7);
+ assign X8ufh7 = (P9yfh7 ? Hawfh7 : Zyvfh7);
+ assign R8ufh7 = (P9yfh7 ? Vcwfh7 : N1wfh7);
+ assign L8ufh7 = (P9yfh7 ? Jfwfh7 : B4wfh7);
+ assign F8ufh7 = (P9yfh7 ? Xhwfh7 : P6wfh7);
+ assign Z7ufh7 = (P9yfh7 ? Lkwfh7 : D9wfh7);
+ assign T7ufh7 = (P9yfh7 ? Zmwfh7 : Rbwfh7);
+ assign N7ufh7 = (P9yfh7 ? Npwfh7 : Fewfh7);
+ assign H7ufh7 = (P9yfh7 ? Bswfh7 : Tgwfh7);
+ assign B7ufh7 = (P9yfh7 ? Puwfh7 : Hjwfh7);
+ assign V6ufh7 = (P9yfh7 ? Dxwfh7 : Vlwfh7);
+ assign P6ufh7 = (P9yfh7 ? Lzwfh7 : Jowfh7);
+ assign J6ufh7 = (P9yfh7 ? T1xfh7 : Xqwfh7);
+ assign D6ufh7 = (P9yfh7 ? B4xfh7 : Ltwfh7);
+ assign X5ufh7 = (P9yfh7 ? J6xfh7 : Zvwfh7);
+ assign R5ufh7 = (P9yfh7 ? R8xfh7 : Rwufh7);
+ assign L5ufh7 = (P9yfh7 ? Zaxfh7 : Vxufh7);
+ assign F5ufh7 = (P9yfh7 ? Hdxfh7 : Zyufh7);
+ assign Z4ufh7 = (P9yfh7 ? Fhxfh7 : D0vfh7);
+ assign T4ufh7 = (P9yfh7 ? Jixfh7 : H1vfh7);
+ assign N4ufh7 = (P9yfh7 ? Bmxfh7 : L2vfh7);
+ assign P9yfh7 = (!Lzxfh7);
+ assign H4ufh7 = (Lzxfh7 ? P3vfh7 : Tpxfh7);
+ assign B4ufh7 = (~(V9yfh7 & Bayfh7));
+ assign Bayfh7 = (Hayfh7 | Vitfh7);
+ assign Hayfh7 = (Nayfh7 & Tayfh7);
+ assign Tayfh7 = (~(Vc9gh7 & Zayfh7));
+ assign V9yfh7 = (~(Fbyfh7 & P3vfh7));
+ assign V3ufh7 = (~(Lbyfh7 & Rbyfh7));
+ assign Rbyfh7 = (Xbyfh7 | Pitfh7);
+ assign Xbyfh7 = (Nayfh7 & Dcyfh7);
+ assign Dcyfh7 = (~(Jc9gh7 & Zayfh7));
+ assign Lbyfh7 = (~(Fbyfh7 & Z4vfh7));
+ assign P3ufh7 = (~(Jcyfh7 & Pcyfh7));
+ assign Pcyfh7 = (Vcyfh7 | Bjtfh7);
+ assign Vcyfh7 = (Nayfh7 & Bdyfh7);
+ assign Bdyfh7 = (~(T79gh7 & Zayfh7));
+ assign Jcyfh7 = (~(Fbyfh7 & L2vfh7));
+ assign J3ufh7 = (~(Hdyfh7 & Ndyfh7));
+ assign Ndyfh7 = (Tdyfh7 | Hjtfh7);
+ assign Tdyfh7 = (Nayfh7 & Zdyfh7);
+ assign Zdyfh7 = (~(N79gh7 & Zayfh7));
+ assign Hdyfh7 = (~(Fbyfh7 & H1vfh7));
+ assign D3ufh7 = (~(Feyfh7 & Leyfh7));
+ assign Leyfh7 = (Reyfh7 | Njtfh7);
+ assign Reyfh7 = (Nayfh7 & Xeyfh7);
+ assign Xeyfh7 = (~(Dc9gh7 & Zayfh7));
+ assign Feyfh7 = (~(Fbyfh7 & D0vfh7));
+ assign X2ufh7 = (~(Dfyfh7 & Jfyfh7));
+ assign Jfyfh7 = (Pfyfh7 | Tjtfh7);
+ assign Pfyfh7 = (Nayfh7 & Vfyfh7);
+ assign Vfyfh7 = (~(P99gh7 & Zayfh7));
+ assign Dfyfh7 = (~(Fbyfh7 & Zyufh7));
+ assign R2ufh7 = (~(Bgyfh7 & Hgyfh7));
+ assign Hgyfh7 = (Ngyfh7 | Zjtfh7);
+ assign Ngyfh7 = (Nayfh7 & Tgyfh7);
+ assign Tgyfh7 = (~(N49gh7 & Zayfh7));
+ assign Bgyfh7 = (~(Fbyfh7 & Vxufh7));
+ assign L2ufh7 = (~(Zgyfh7 & Fhyfh7));
+ assign Fhyfh7 = (Lhyfh7 | Fktfh7);
+ assign Lhyfh7 = (Nayfh7 & Rhyfh7);
+ assign Rhyfh7 = (~(X59gh7 & Zayfh7));
+ assign Nayfh7 = (Xhyfh7 & Sorfh7);
+ assign Xhyfh7 = (Diyfh7 & Zvwfh7);
+ assign Zgyfh7 = (~(Fbyfh7 & Rwufh7));
+ assign Fbyfh7 = (Jiyfh7 & Sorfh7);
+ assign Jiyfh7 = (Diyfh7 & Ltwfh7);
+ assign F2ufh7 = (!Piyfh7);
+ assign Piyfh7 = (D9yfh7 ? Z79gh7 : Pl8gh7);
+ assign D9yfh7 = (Viyfh7 & Bjyfh7);
+ assign Viyfh7 = (Z1yfh7 & B1yfh7);
+ assign Z1yfh7 = (!Hjyfh7);
+ assign Z1ufh7 = (Lzxfh7 ? Bdvfh7 : Pfvfh7);
+ assign Lzxfh7 = (Njyfh7 & Fqxfh7);
+ assign Njyfh7 = (Rqxfh7 & B1yfh7);
+ assign T1ufh7 = (!Tjyfh7);
+ assign Tjyfh7 = (Fkyfh7 ? Jltfh7 : Zjyfh7);
+ assign Zjyfh7 = (Lkyfh7 & Rkyfh7);
+ assign Rkyfh7 = (Xkyfh7 & Dlyfh7);
+ assign Dlyfh7 = (~(ahb_hrdata[0] & Jlyfh7));
+ assign Xkyfh7 = (Plyfh7 | Jc9gh7);
+ assign Lkyfh7 = (Vlyfh7 & Bmyfh7);
+ assign Bmyfh7 = (~(Hmyfh7 & Zgvfh7));
+ assign Vlyfh7 = (~(Nmyfh7 & com_rx_tdata[0]));
+ assign N1ufh7 = (!Tmyfh7);
+ assign Tmyfh7 = (Fkyfh7 ? Pltfh7 : Zmyfh7);
+ assign Zmyfh7 = (Fnyfh7 & Lnyfh7);
+ assign Lnyfh7 = (Rnyfh7 & Xnyfh7);
+ assign Xnyfh7 = (~(ahb_hrdata[1] & Jlyfh7));
+ assign Rnyfh7 = (Plyfh7 | Vc9gh7);
+ assign Fnyfh7 = (Doyfh7 & Joyfh7);
+ assign Joyfh7 = (~(Hmyfh7 & Tpxfh7));
+ assign Doyfh7 = (~(Nmyfh7 & com_rx_tdata[1]));
+ assign H1ufh7 = (!Poyfh7);
+ assign Poyfh7 = (Fkyfh7 ? Vltfh7 : Voyfh7);
+ assign Voyfh7 = (Bpyfh7 & Hpyfh7);
+ assign Hpyfh7 = (Npyfh7 & Tpyfh7);
+ assign Tpyfh7 = (~(ahb_hrdata[2] & Jlyfh7));
+ assign Npyfh7 = (Plyfh7 | T79gh7);
+ assign Bpyfh7 = (Zpyfh7 & Fqyfh7);
+ assign Fqyfh7 = (~(Hmyfh7 & Bmxfh7));
+ assign Bmxfh7 = (!Np8gh7);
+ assign Zpyfh7 = (~(Nmyfh7 & com_rx_tdata[2]));
+ assign B1ufh7 = (!Lqyfh7);
+ assign Lqyfh7 = (Fkyfh7 ? Bmtfh7 : Rqyfh7);
+ assign Rqyfh7 = (Xqyfh7 & Dryfh7);
+ assign Dryfh7 = (Jryfh7 & Pryfh7);
+ assign Pryfh7 = (~(ahb_hrdata[3] & Jlyfh7));
+ assign Jryfh7 = (Plyfh7 | N79gh7);
+ assign Xqyfh7 = (Vryfh7 & Bsyfh7);
+ assign Bsyfh7 = (~(Hmyfh7 & Jixfh7));
+ assign Vryfh7 = (~(Nmyfh7 & com_rx_tdata[3]));
+ assign V0ufh7 = (!Hsyfh7);
+ assign Hsyfh7 = (Fkyfh7 ? Hmtfh7 : Nsyfh7);
+ assign Nsyfh7 = (Tsyfh7 & Zsyfh7);
+ assign Zsyfh7 = (Ftyfh7 & Ltyfh7);
+ assign Ltyfh7 = (~(ahb_hrdata[4] & Jlyfh7));
+ assign Ftyfh7 = (Plyfh7 | Dc9gh7);
+ assign Tsyfh7 = (Rtyfh7 & Xtyfh7);
+ assign Xtyfh7 = (~(Hmyfh7 & Fhxfh7));
+ assign Rtyfh7 = (~(Nmyfh7 & com_rx_tdata[4]));
+ assign P0ufh7 = (!Duyfh7);
+ assign Duyfh7 = (Fkyfh7 ? Nmtfh7 : Juyfh7);
+ assign Fkyfh7 = (!Puyfh7);
+ assign Juyfh7 = (Vuyfh7 & Bvyfh7);
+ assign Bvyfh7 = (Hvyfh7 & Nvyfh7);
+ assign Nvyfh7 = (~(ahb_hrdata[5] & Jlyfh7));
+ assign Hvyfh7 = (Plyfh7 | P99gh7);
+ assign Vuyfh7 = (Tvyfh7 & Zvyfh7);
+ assign Zvyfh7 = (~(Hmyfh7 & Hdxfh7));
+ assign Tvyfh7 = (~(Nmyfh7 & com_rx_tdata[5]));
+ assign J0ufh7 = (!Fwyfh7);
+ assign Fwyfh7 = (Puyfh7 ? Lwyfh7 : Tmtfh7);
+ assign Lwyfh7 = (Rwyfh7 & Xwyfh7);
+ assign Xwyfh7 = (Dxyfh7 & Jxyfh7);
+ assign Jxyfh7 = (~(ahb_hrdata[6] & Jlyfh7));
+ assign Dxyfh7 = (Plyfh7 | N49gh7);
+ assign Rwyfh7 = (Pxyfh7 & Vxyfh7);
+ assign Vxyfh7 = (~(Hmyfh7 & Zaxfh7));
+ assign Pxyfh7 = (~(Nmyfh7 & com_rx_tdata[6]));
+ assign D0ufh7 = (!Byyfh7);
+ assign Byyfh7 = (Puyfh7 ? Hyyfh7 : Zmtfh7);
+ assign Puyfh7 = (~(Nyyfh7 & Tyyfh7));
+ assign Hyyfh7 = (Zyyfh7 & Fzyfh7);
+ assign Fzyfh7 = (Lzyfh7 & Rzyfh7);
+ assign Rzyfh7 = (~(ahb_hrdata[7] & Jlyfh7));
+ assign Lzyfh7 = (Plyfh7 | X59gh7);
+ assign Zyyfh7 = (Xzyfh7 & D0zfh7);
+ assign D0zfh7 = (~(Hmyfh7 & R8xfh7));
+ assign Xzyfh7 = (~(Nmyfh7 & com_rx_tdata[7]));
+ assign Xztfh7 = (V0zfh7 ? P0zfh7 : J0zfh7);
+ assign J0zfh7 = (~(B1zfh7 & H1zfh7));
+ assign H1zfh7 = (N1zfh7 & T1zfh7);
+ assign T1zfh7 = (~(ahb_hrdata[8] & Jlyfh7));
+ assign N1zfh7 = (Z1zfh7 | H79gh7);
+ assign B1zfh7 = (F2zfh7 & L2zfh7);
+ assign L2zfh7 = (~(Hmyfh7 & J6xfh7));
+ assign F2zfh7 = (~(R2zfh7 & com_rx_tdata[0]));
+ assign Rztfh7 = (V0zfh7 ? D3zfh7 : X2zfh7);
+ assign X2zfh7 = (~(J3zfh7 & P3zfh7));
+ assign P3zfh7 = (V3zfh7 & B4zfh7);
+ assign B4zfh7 = (~(ahb_hrdata[9] & Jlyfh7));
+ assign V3zfh7 = (Z1zfh7 | J99gh7);
+ assign J3zfh7 = (H4zfh7 & N4zfh7);
+ assign N4zfh7 = (~(Hmyfh7 & B4xfh7));
+ assign H4zfh7 = (~(R2zfh7 & com_rx_tdata[1]));
+ assign Lztfh7 = (V0zfh7 ? Z4zfh7 : T4zfh7);
+ assign T4zfh7 = (~(F5zfh7 & L5zfh7));
+ assign L5zfh7 = (R5zfh7 & X5zfh7);
+ assign X5zfh7 = (~(ahb_hrdata[10] & Jlyfh7));
+ assign R5zfh7 = (Z1zfh7 | H49gh7);
+ assign F5zfh7 = (D6zfh7 & J6zfh7);
+ assign J6zfh7 = (~(Hmyfh7 & T1xfh7));
+ assign D6zfh7 = (~(R2zfh7 & com_rx_tdata[2]));
+ assign Fztfh7 = (V0zfh7 ? V6zfh7 : P6zfh7);
+ assign P6zfh7 = (~(B7zfh7 & H7zfh7));
+ assign H7zfh7 = (N7zfh7 & T7zfh7);
+ assign T7zfh7 = (~(ahb_hrdata[11] & Jlyfh7));
+ assign N7zfh7 = (Z1zfh7 | R59gh7);
+ assign B7zfh7 = (Z7zfh7 & F8zfh7);
+ assign F8zfh7 = (~(Hmyfh7 & Lzwfh7));
+ assign Z7zfh7 = (~(R2zfh7 & com_rx_tdata[3]));
+ assign Zytfh7 = (V0zfh7 ? R8zfh7 : L8zfh7);
+ assign L8zfh7 = (~(X8zfh7 & D9zfh7));
+ assign D9zfh7 = (J9zfh7 & P9zfh7);
+ assign P9zfh7 = (~(ahb_hrdata[12] & Jlyfh7));
+ assign J9zfh7 = (Z1zfh7 | B79gh7);
+ assign X8zfh7 = (V9zfh7 & Bazfh7);
+ assign Bazfh7 = (~(Hmyfh7 & Dxwfh7));
+ assign V9zfh7 = (~(R2zfh7 & com_rx_tdata[4]));
+ assign Tytfh7 = (V0zfh7 ? Nazfh7 : Hazfh7);
+ assign Hazfh7 = (~(Tazfh7 & Zazfh7));
+ assign Zazfh7 = (Fbzfh7 & Lbzfh7);
+ assign Lbzfh7 = (~(ahb_hrdata[13] & Jlyfh7));
+ assign Fbzfh7 = (Z1zfh7 | D99gh7);
+ assign Tazfh7 = (Rbzfh7 & Xbzfh7);
+ assign Xbzfh7 = (~(Hmyfh7 & Puwfh7));
+ assign Rbzfh7 = (~(R2zfh7 & com_rx_tdata[5]));
+ assign Nytfh7 = (V0zfh7 ? Jczfh7 : Dczfh7);
+ assign Dczfh7 = (~(Pczfh7 & Vczfh7));
+ assign Vczfh7 = (Bdzfh7 & Hdzfh7);
+ assign Hdzfh7 = (~(ahb_hrdata[14] & Jlyfh7));
+ assign Bdzfh7 = (Z1zfh7 | B49gh7);
+ assign Pczfh7 = (Ndzfh7 & Tdzfh7);
+ assign Tdzfh7 = (~(Hmyfh7 & Bswfh7));
+ assign Ndzfh7 = (~(R2zfh7 & com_rx_tdata[6]));
+ assign Hytfh7 = (V0zfh7 ? Fezfh7 : Zdzfh7);
+ assign V0zfh7 = (Nyyfh7 & Lezfh7);
+ assign Lezfh7 = (~(R2zfh7 & Rezfh7));
+ assign Zdzfh7 = (~(Xezfh7 & Dfzfh7));
+ assign Dfzfh7 = (Jfzfh7 & Pfzfh7);
+ assign Pfzfh7 = (~(ahb_hrdata[15] & Jlyfh7));
+ assign Jfzfh7 = (Z1zfh7 | L59gh7);
+ assign Xezfh7 = (Vfzfh7 & Bgzfh7);
+ assign Bgzfh7 = (~(Hmyfh7 & Npwfh7));
+ assign Vfzfh7 = (~(R2zfh7 & com_rx_tdata[7]));
+ assign Bytfh7 = (Tgzfh7 ? Ngzfh7 : Hgzfh7);
+ assign Hgzfh7 = (~(Zgzfh7 & Fhzfh7));
+ assign Fhzfh7 = (Lhzfh7 & Rhzfh7);
+ assign Rhzfh7 = (Xhzfh7 | Pitfh7);
+ assign Lhzfh7 = (Dizfh7 & Jizfh7);
+ assign Jizfh7 = (~(ahb_hrdata[16] & Jlyfh7));
+ assign Dizfh7 = (~(Pizfh7 & Rbwfh7));
+ assign Zgzfh7 = (Vizfh7 & Bjzfh7);
+ assign Bjzfh7 = (~(Hmyfh7 & Zmwfh7));
+ assign Vizfh7 = (~(Hjzfh7 & com_rx_tdata[0]));
+ assign Vxtfh7 = (Tgzfh7 ? Tjzfh7 : Njzfh7);
+ assign Njzfh7 = (~(Zjzfh7 & Fkzfh7));
+ assign Fkzfh7 = (Lkzfh7 & Rkzfh7);
+ assign Rkzfh7 = (Xhzfh7 | Vitfh7);
+ assign Lkzfh7 = (Xkzfh7 & Dlzfh7);
+ assign Dlzfh7 = (~(ahb_hrdata[17] & Jlyfh7));
+ assign Xkzfh7 = (~(Pizfh7 & D9wfh7));
+ assign Zjzfh7 = (Jlzfh7 & Plzfh7);
+ assign Plzfh7 = (~(Hmyfh7 & Lkwfh7));
+ assign Jlzfh7 = (~(Hjzfh7 & com_rx_tdata[1]));
+ assign Pxtfh7 = (Tgzfh7 ? Bmzfh7 : Vlzfh7);
+ assign Vlzfh7 = (~(Hmzfh7 & Nmzfh7));
+ assign Nmzfh7 = (Tmzfh7 & Zmzfh7);
+ assign Zmzfh7 = (Xhzfh7 | Bjtfh7);
+ assign Tmzfh7 = (Fnzfh7 & Lnzfh7);
+ assign Lnzfh7 = (~(ahb_hrdata[18] & Jlyfh7));
+ assign Fnzfh7 = (~(Pizfh7 & P6wfh7));
+ assign Hmzfh7 = (Rnzfh7 & Xnzfh7);
+ assign Xnzfh7 = (~(Hmyfh7 & Xhwfh7));
+ assign Rnzfh7 = (~(Hjzfh7 & com_rx_tdata[2]));
+ assign Jxtfh7 = (Tgzfh7 ? Jozfh7 : Dozfh7);
+ assign Dozfh7 = (~(Pozfh7 & Vozfh7));
+ assign Vozfh7 = (Bpzfh7 & Hpzfh7);
+ assign Hpzfh7 = (Xhzfh7 | Hjtfh7);
+ assign Bpzfh7 = (Npzfh7 & Tpzfh7);
+ assign Tpzfh7 = (~(ahb_hrdata[19] & Jlyfh7));
+ assign Npzfh7 = (~(Pizfh7 & B4wfh7));
+ assign Pozfh7 = (Zpzfh7 & Fqzfh7);
+ assign Fqzfh7 = (~(Hmyfh7 & Jfwfh7));
+ assign Zpzfh7 = (~(Hjzfh7 & com_rx_tdata[3]));
+ assign Dxtfh7 = (Tgzfh7 ? Rqzfh7 : Lqzfh7);
+ assign Lqzfh7 = (~(Xqzfh7 & Drzfh7));
+ assign Drzfh7 = (Jrzfh7 & Przfh7);
+ assign Przfh7 = (Xhzfh7 | Njtfh7);
+ assign Jrzfh7 = (Vrzfh7 & Bszfh7);
+ assign Bszfh7 = (~(ahb_hrdata[20] & Jlyfh7));
+ assign Vrzfh7 = (~(Pizfh7 & N1wfh7));
+ assign Xqzfh7 = (Hszfh7 & Nszfh7);
+ assign Nszfh7 = (~(Hmyfh7 & Vcwfh7));
+ assign Hszfh7 = (~(Hjzfh7 & com_rx_tdata[4]));
+ assign Xwtfh7 = (Tgzfh7 ? Zszfh7 : Tszfh7);
+ assign Tszfh7 = (~(Ftzfh7 & Ltzfh7));
+ assign Ltzfh7 = (Rtzfh7 & Xtzfh7);
+ assign Xtzfh7 = (Xhzfh7 | Tjtfh7);
+ assign Rtzfh7 = (Duzfh7 & Juzfh7);
+ assign Juzfh7 = (~(ahb_hrdata[21] & Jlyfh7));
+ assign Duzfh7 = (~(Pizfh7 & Zyvfh7));
+ assign Ftzfh7 = (Puzfh7 & Vuzfh7);
+ assign Vuzfh7 = (~(Hmyfh7 & Hawfh7));
+ assign Puzfh7 = (~(Hjzfh7 & com_rx_tdata[5]));
+ assign Rwtfh7 = (Tgzfh7 ? Hvzfh7 : Bvzfh7);
+ assign Bvzfh7 = (~(Nvzfh7 & Tvzfh7));
+ assign Tvzfh7 = (Zvzfh7 & Fwzfh7);
+ assign Fwzfh7 = (Xhzfh7 | Zjtfh7);
+ assign Zvzfh7 = (Lwzfh7 & Rwzfh7);
+ assign Rwzfh7 = (~(ahb_hrdata[22] & Jlyfh7));
+ assign Lwzfh7 = (~(Pizfh7 & Lwvfh7));
+ assign Nvzfh7 = (Xwzfh7 & Dxzfh7);
+ assign Dxzfh7 = (~(Hmyfh7 & T7wfh7));
+ assign Xwzfh7 = (~(Hjzfh7 & com_rx_tdata[6]));
+ assign Lwtfh7 = (Tgzfh7 ? Pxzfh7 : Jxzfh7);
+ assign Tgzfh7 = (Nyyfh7 & Vxzfh7);
+ assign Vxzfh7 = (~(Hjzfh7 & Rezfh7));
+ assign Jxzfh7 = (~(Byzfh7 & Hyzfh7));
+ assign Hyzfh7 = (Nyzfh7 & Tyzfh7);
+ assign Tyzfh7 = (Xhzfh7 | Fktfh7);
+ assign Nyzfh7 = (Zyzfh7 & Fzzfh7);
+ assign Fzzfh7 = (~(ahb_hrdata[23] & Jlyfh7));
+ assign Zyzfh7 = (~(Pizfh7 & Xtvfh7));
+ assign Byzfh7 = (Lzzfh7 & Rzzfh7);
+ assign Rzzfh7 = (~(Hmyfh7 & F5wfh7));
+ assign Lzzfh7 = (~(Hjzfh7 & com_rx_tdata[7]));
+ assign Fwtfh7 = (J00gh7 ? D00gh7 : Xzzfh7);
+ assign Xzzfh7 = (~(P00gh7 & V00gh7));
+ assign V00gh7 = (B10gh7 & H10gh7);
+ assign H10gh7 = (~(gpi8[0] & N10gh7));
+ assign B10gh7 = (T10gh7 & Z10gh7);
+ assign Z10gh7 = (~(ahb_hrdata[24] & Jlyfh7));
+ assign T10gh7 = (~(Pizfh7 & Jrvfh7));
+ assign P00gh7 = (F20gh7 & L20gh7);
+ assign L20gh7 = (~(Hmyfh7 & R2wfh7));
+ assign F20gh7 = (~(R20gh7 & com_rx_tdata[0]));
+ assign Zvtfh7 = (J00gh7 ? D30gh7 : X20gh7);
+ assign X20gh7 = (~(J30gh7 & P30gh7));
+ assign P30gh7 = (V30gh7 & B40gh7);
+ assign B40gh7 = (~(gpi8[1] & N10gh7));
+ assign V30gh7 = (H40gh7 & N40gh7);
+ assign N40gh7 = (~(ahb_hrdata[25] & Jlyfh7));
+ assign H40gh7 = (~(Pizfh7 & Povfh7));
+ assign J30gh7 = (T40gh7 & Z40gh7);
+ assign Z40gh7 = (~(Hmyfh7 & D0wfh7));
+ assign T40gh7 = (~(R20gh7 & com_rx_tdata[1]));
+ assign Tvtfh7 = (J00gh7 ? L50gh7 : F50gh7);
+ assign F50gh7 = (~(R50gh7 & X50gh7));
+ assign X50gh7 = (D60gh7 & J60gh7);
+ assign J60gh7 = (~(gpi8[2] & N10gh7));
+ assign D60gh7 = (P60gh7 & V60gh7);
+ assign V60gh7 = (~(ahb_hrdata[26] & Jlyfh7));
+ assign P60gh7 = (~(Pizfh7 & Vlvfh7));
+ assign R50gh7 = (B70gh7 & H70gh7);
+ assign H70gh7 = (~(Hmyfh7 & Pxvfh7));
+ assign B70gh7 = (~(R20gh7 & com_rx_tdata[2]));
+ assign Nvtfh7 = (J00gh7 ? T70gh7 : N70gh7);
+ assign N70gh7 = (~(Z70gh7 & F80gh7));
+ assign F80gh7 = (L80gh7 & R80gh7);
+ assign R80gh7 = (~(gpi8[3] & N10gh7));
+ assign L80gh7 = (X80gh7 & D90gh7);
+ assign D90gh7 = (~(ahb_hrdata[27] & Jlyfh7));
+ assign X80gh7 = (~(Pizfh7 & Zdvfh7));
+ assign Z70gh7 = (J90gh7 & P90gh7);
+ assign P90gh7 = (~(Hmyfh7 & Bvvfh7));
+ assign J90gh7 = (~(R20gh7 & com_rx_tdata[3]));
+ assign Hvtfh7 = (J00gh7 ? Ba0gh7 : V90gh7);
+ assign V90gh7 = (~(Ha0gh7 & Na0gh7));
+ assign Na0gh7 = (Ta0gh7 & Za0gh7);
+ assign Za0gh7 = (~(gpi8[4] & N10gh7));
+ assign Ta0gh7 = (Fb0gh7 & Lb0gh7);
+ assign Lb0gh7 = (~(ahb_hrdata[28] & Jlyfh7));
+ assign Fb0gh7 = (~(Pizfh7 & Xqvfh7));
+ assign Ha0gh7 = (Rb0gh7 & Xb0gh7);
+ assign Xb0gh7 = (~(Hmyfh7 & Nsvfh7));
+ assign Rb0gh7 = (~(R20gh7 & com_rx_tdata[4]));
+ assign Bvtfh7 = (J00gh7 ? Jc0gh7 : Dc0gh7);
+ assign Dc0gh7 = (~(Pc0gh7 & Vc0gh7));
+ assign Vc0gh7 = (Bd0gh7 & Hd0gh7);
+ assign Hd0gh7 = (~(gpi8[5] & N10gh7));
+ assign Bd0gh7 = (Nd0gh7 & Td0gh7);
+ assign Td0gh7 = (~(ahb_hrdata[29] & Jlyfh7));
+ assign Nd0gh7 = (~(Pizfh7 & Dovfh7));
+ assign Pc0gh7 = (Zd0gh7 & Fe0gh7);
+ assign Fe0gh7 = (~(Hmyfh7 & Tpvfh7));
+ assign Zd0gh7 = (~(R20gh7 & com_rx_tdata[5]));
+ assign Vutfh7 = (J00gh7 ? Re0gh7 : Le0gh7);
+ assign Le0gh7 = (~(Xe0gh7 & Df0gh7));
+ assign Df0gh7 = (Jf0gh7 & Pf0gh7);
+ assign Pf0gh7 = (~(gpi8[6] & N10gh7));
+ assign Jf0gh7 = (Vf0gh7 & Bg0gh7);
+ assign Bg0gh7 = (~(ahb_hrdata[30] & Jlyfh7));
+ assign Vf0gh7 = (~(Pizfh7 & Jlvfh7));
+ assign Xe0gh7 = (Hg0gh7 & Ng0gh7);
+ assign Ng0gh7 = (~(Hmyfh7 & Zmvfh7));
+ assign Hg0gh7 = (~(R20gh7 & com_rx_tdata[6]));
+ assign Putfh7 = (J00gh7 ? Zg0gh7 : Tg0gh7);
+ assign J00gh7 = (Nyyfh7 & Fh0gh7);
+ assign Fh0gh7 = (~(R20gh7 & Rezfh7));
+ assign Nyyfh7 = (Lh0gh7 & Rh0gh7);
+ assign Rh0gh7 = (Xh0gh7 & Di0gh7);
+ assign Lh0gh7 = (Ji0gh7 & Pi0gh7);
+ assign Pi0gh7 = (~(Vi0gh7 & Jlyfh7));
+ assign Tg0gh7 = (~(Bj0gh7 & Hj0gh7));
+ assign Hj0gh7 = (Nj0gh7 & Tj0gh7);
+ assign Tj0gh7 = (~(gpi8[7] & N10gh7));
+ assign Nj0gh7 = (Zj0gh7 & Fk0gh7);
+ assign Fk0gh7 = (~(ahb_hrdata[31] & Jlyfh7));
+ assign Jlyfh7 = (!Lk0gh7);
+ assign Zj0gh7 = (~(Pizfh7 & Bdvfh7));
+ assign Bj0gh7 = (Rk0gh7 & Xk0gh7);
+ assign Xk0gh7 = (~(Hmyfh7 & Pfvfh7));
+ assign Hmyfh7 = (!Xh0gh7);
+ assign Rk0gh7 = (~(R20gh7 & com_rx_tdata[7]));
+ assign R20gh7 = (!Dl0gh7);
+ assign Jutfh7 = (Pl0gh7 ? com_tx_tdata[0] : Jl0gh7);
+ assign Jl0gh7 = (~(Vl0gh7 & Bm0gh7));
+ assign Bm0gh7 = (Hm0gh7 & Nm0gh7);
+ assign Nm0gh7 = (Tm0gh7 & Zm0gh7);
+ assign Zm0gh7 = (Fn0gh7 & Ln0gh7);
+ assign Fn0gh7 = (Rn0gh7 & Xn0gh7);
+ assign Tm0gh7 = (Do0gh7 & Xhzfh7);
+ assign Hm0gh7 = (Jo0gh7 & Po0gh7);
+ assign Po0gh7 = (Vo0gh7 & Bp0gh7);
+ assign Bp0gh7 = (~(Hp0gh7 & Np0gh7));
+ assign Np0gh7 = (~(Tp0gh7 & Zp0gh7));
+ assign Zp0gh7 = (~(Fq0gh7 & D3zfh7));
+ assign D3zfh7 = (!Lntfh7);
+ assign Tp0gh7 = (~(Lq0gh7 & P0zfh7));
+ assign P0zfh7 = (!Fntfh7);
+ assign Vo0gh7 = (Rq0gh7 & Xq0gh7);
+ assign Jo0gh7 = (Dr0gh7 & Jr0gh7);
+ assign Jr0gh7 = (~(Pr0gh7 & Vr0gh7));
+ assign Vr0gh7 = (~(Bs0gh7 & Hs0gh7));
+ assign Hs0gh7 = (Ns0gh7 | Hmtfh7);
+ assign Bs0gh7 = (Ts0gh7 | Nmtfh7);
+ assign Dr0gh7 = (~(Zs0gh7 & Ft0gh7));
+ assign Ft0gh7 = (~(Lt0gh7 & Rt0gh7));
+ assign Rt0gh7 = (Xt0gh7 | Pltfh7);
+ assign Xt0gh7 = (!Du0gh7);
+ assign Lt0gh7 = (~(Ju0gh7 & Pu0gh7));
+ assign Vl0gh7 = (Vu0gh7 & Bv0gh7);
+ assign Bv0gh7 = (Hv0gh7 & Nv0gh7);
+ assign Nv0gh7 = (Tv0gh7 & Zv0gh7);
+ assign Zv0gh7 = (~(Fw0gh7 & Lw0gh7));
+ assign Lw0gh7 = (~(Rw0gh7 & Xw0gh7));
+ assign Xw0gh7 = (~(Dx0gh7 & D30gh7));
+ assign D30gh7 = (!Drtfh7);
+ assign Rw0gh7 = (~(Jx0gh7 & D00gh7));
+ assign D00gh7 = (!Xqtfh7);
+ assign Tv0gh7 = (Px0gh7 & Vx0gh7);
+ assign Vx0gh7 = (~(By0gh7 & Hy0gh7));
+ assign Hy0gh7 = (~(Ny0gh7 & Ty0gh7));
+ assign Ty0gh7 = (~(Zy0gh7 & Nazfh7));
+ assign Nazfh7 = (!Jotfh7);
+ assign Ny0gh7 = (~(Fz0gh7 & R8zfh7));
+ assign R8zfh7 = (!Dotfh7);
+ assign Px0gh7 = (~(Lz0gh7 & Rz0gh7));
+ assign Rz0gh7 = (~(Xz0gh7 & D01gh7));
+ assign D01gh7 = (~(J01gh7 & Tjzfh7));
+ assign Tjzfh7 = (!Hptfh7);
+ assign Xz0gh7 = (~(P01gh7 & Ngzfh7));
+ assign Ngzfh7 = (!Bptfh7);
+ assign Hv0gh7 = (V01gh7 & B11gh7);
+ assign B11gh7 = (~(H11gh7 & N11gh7));
+ assign N11gh7 = (~(T11gh7 & Z11gh7));
+ assign Z11gh7 = (~(F21gh7 & Zszfh7));
+ assign Zszfh7 = (!Fqtfh7);
+ assign T11gh7 = (~(L21gh7 & Rqzfh7));
+ assign Rqzfh7 = (!Zptfh7);
+ assign V01gh7 = (~(R21gh7 & X21gh7));
+ assign X21gh7 = (~(D31gh7 & J31gh7));
+ assign J31gh7 = (~(P31gh7 & Jc0gh7));
+ assign Jc0gh7 = (!Bstfh7);
+ assign D31gh7 = (~(V31gh7 & Ba0gh7));
+ assign Ba0gh7 = (!Vrtfh7);
+ assign Vu0gh7 = (B41gh7 & H41gh7);
+ assign H41gh7 = (N41gh7 & T41gh7);
+ assign T41gh7 = (~(stdio_rx_tdata[0] & Z41gh7));
+ assign N41gh7 = (F51gh7 & L51gh7);
+ assign L51gh7 = (R51gh7 | Rb9gh7);
+ assign B41gh7 = (~(X51gh7 | D61gh7));
+ assign Dutfh7 = (J61gh7 & P61gh7);
+ assign P61gh7 = (~(V61gh7 & B71gh7));
+ assign B71gh7 = (H71gh7 & N71gh7);
+ assign N71gh7 = (T71gh7 & Z71gh7);
+ assign Z71gh7 = (F81gh7 & L81gh7);
+ assign F81gh7 = (~(R81gh7 & R21gh7));
+ assign R81gh7 = (~(P31gh7 | Bstfh7));
+ assign T71gh7 = (X81gh7 & D91gh7);
+ assign D91gh7 = (~(J91gh7 & By0gh7));
+ assign J91gh7 = (~(Zy0gh7 | Jotfh7));
+ assign X81gh7 = (~(P91gh7 & Zs0gh7));
+ assign P91gh7 = (~(Du0gh7 | Pltfh7));
+ assign H71gh7 = (V91gh7 & Ba1gh7);
+ assign Ba1gh7 = (~(Ha1gh7 & Lz0gh7));
+ assign Ha1gh7 = (~(J01gh7 | Hptfh7));
+ assign V91gh7 = (Na1gh7 & Ta1gh7);
+ assign Ta1gh7 = (~(Za1gh7 & Hp0gh7));
+ assign Za1gh7 = (~(Fq0gh7 | Lntfh7));
+ assign Na1gh7 = (~(Fb1gh7 & H11gh7));
+ assign Fb1gh7 = (~(F21gh7 | Fqtfh7));
+ assign V61gh7 = (Lb1gh7 & Rb1gh7);
+ assign Rb1gh7 = (Xb1gh7 & Dc1gh7);
+ assign Dc1gh7 = (~(Jc1gh7 & Pizfh7));
+ assign Jc1gh7 = (~(Na9gh7 & Lbvfh7));
+ assign Xb1gh7 = (Pc1gh7 & Vc1gh7);
+ assign Vc1gh7 = (~(Bd1gh7 & Fw0gh7));
+ assign Bd1gh7 = (~(Dx0gh7 | Drtfh7));
+ assign Pc1gh7 = (~(Hd1gh7 & Pr0gh7));
+ assign Hd1gh7 = (~(Nd1gh7 | Nmtfh7));
+ assign Lb1gh7 = (Td1gh7 & Zd1gh7);
+ assign Td1gh7 = (Fe1gh7 & Le1gh7);
+ assign Le1gh7 = (~(stdio_rx_tdata[1] & Z41gh7));
+ assign J61gh7 = (~(Lktfh7 & Pl0gh7));
+ assign Xttfh7 = (Pl0gh7 ? com_tx_tdata[2] : Re1gh7);
+ assign Re1gh7 = (~(Xe1gh7 & Df1gh7));
+ assign Df1gh7 = (Jf1gh7 & Pf1gh7);
+ assign Pf1gh7 = (Vf1gh7 & Bg1gh7);
+ assign Bg1gh7 = (~(Hg1gh7 & Hp0gh7));
+ assign Hg1gh7 = (~(Ng1gh7 | Rntfh7));
+ assign Vf1gh7 = (Tg1gh7 & Xq0gh7);
+ assign Tg1gh7 = (~(Zg1gh7 & Zs0gh7));
+ assign Zg1gh7 = (~(Fh1gh7 | Vltfh7));
+ assign Jf1gh7 = (Lh1gh7 & Rh1gh7);
+ assign Rh1gh7 = (~(Xh1gh7 & H11gh7));
+ assign Xh1gh7 = (~(Di1gh7 | Lqtfh7));
+ assign Lh1gh7 = (Ji1gh7 & Pi1gh7);
+ assign Pi1gh7 = (~(Vi1gh7 & By0gh7));
+ assign Vi1gh7 = (~(Bj1gh7 | Potfh7));
+ assign Ji1gh7 = (~(Hj1gh7 & Lz0gh7));
+ assign Hj1gh7 = (~(Nj1gh7 | Nptfh7));
+ assign Xe1gh7 = (Tj1gh7 & Zj1gh7);
+ assign Zj1gh7 = (Fk1gh7 & Lk1gh7);
+ assign Lk1gh7 = (~(Rk1gh7 & Pr0gh7));
+ assign Rk1gh7 = (~(Xk1gh7 | Tmtfh7));
+ assign Fk1gh7 = (Dl1gh7 & Jl1gh7);
+ assign Jl1gh7 = (~(Pl1gh7 & Fw0gh7));
+ assign Pl1gh7 = (~(Vl1gh7 | Jrtfh7));
+ assign Dl1gh7 = (~(Bm1gh7 & R21gh7));
+ assign Bm1gh7 = (~(Hm1gh7 | Hstfh7));
+ assign Tj1gh7 = (Nm1gh7 & Tm1gh7);
+ assign Nm1gh7 = (Zm1gh7 & Fn1gh7);
+ assign Fn1gh7 = (R51gh7 | Ta9gh7);
+ assign Zm1gh7 = (~(stdio_rx_tdata[2] & Z41gh7));
+ assign Rttfh7 = (Pl0gh7 ? com_tx_tdata[3] : Ln1gh7);
+ assign Ln1gh7 = (~(Rn1gh7 & Xn1gh7));
+ assign Xn1gh7 = (Do1gh7 & Jo1gh7);
+ assign Jo1gh7 = (Po1gh7 & Vo1gh7);
+ assign Vo1gh7 = (L81gh7 & Lbvfh7);
+ assign Po1gh7 = (Bp1gh7 & Hp1gh7);
+ assign Bp1gh7 = (~(Np1gh7 & Tp1gh7));
+ assign Np1gh7 = (~(Zp1gh7 | Zmtfh7));
+ assign Do1gh7 = (Fq1gh7 & Lq1gh7);
+ assign Lq1gh7 = (~(Rq1gh7 & Xq1gh7));
+ assign Rq1gh7 = (~(Dr1gh7 | Bmtfh7));
+ assign Fq1gh7 = (Jr1gh7 & Pr1gh7);
+ assign Pr1gh7 = (~(Vr1gh7 & Bs1gh7));
+ assign Vr1gh7 = (R21gh7 & Zg0gh7);
+ assign Jr1gh7 = (~(Hs1gh7 & Ns1gh7));
+ assign Hs1gh7 = (By0gh7 & Fezfh7);
+ assign Rn1gh7 = (Ts1gh7 & Zs1gh7);
+ assign Zs1gh7 = (Ft1gh7 & Lt1gh7);
+ assign Lt1gh7 = (Rt1gh7 & Xt1gh7);
+ assign Xt1gh7 = (~(Du1gh7 & Ju1gh7));
+ assign Du1gh7 = (Hp0gh7 & V6zfh7);
+ assign Rt1gh7 = (~(Pu1gh7 & Vu1gh7));
+ assign Pu1gh7 = (H11gh7 & Pxzfh7);
+ assign Ft1gh7 = (Bv1gh7 & Hv1gh7);
+ assign Hv1gh7 = (~(Nv1gh7 & Tv1gh7));
+ assign Nv1gh7 = (Lz0gh7 & Jozfh7);
+ assign Bv1gh7 = (~(Zv1gh7 & Fw1gh7));
+ assign Zv1gh7 = (Fw0gh7 & T70gh7);
+ assign Ts1gh7 = (Lw1gh7 & Rw1gh7);
+ assign Lw1gh7 = (Xw1gh7 & Dx1gh7);
+ assign Dx1gh7 = (R51gh7 | Za9gh7);
+ assign Xw1gh7 = (~(stdio_rx_tdata[3] & Z41gh7));
+ assign Lttfh7 = (Pl0gh7 ? com_tx_tdata[4] : Jx1gh7);
+ assign Jx1gh7 = (~(Px1gh7 & Vx1gh7));
+ assign Vx1gh7 = (By1gh7 & Hy1gh7);
+ assign Hy1gh7 = (Ny1gh7 & Ty1gh7);
+ assign Ty1gh7 = (Do0gh7 & Zy1gh7);
+ assign Ny1gh7 = (Hp1gh7 & Fz1gh7);
+ assign By1gh7 = (Lz1gh7 & Rz1gh7);
+ assign Rz1gh7 = (Xz1gh7 & D02gh7);
+ assign D02gh7 = (~(R21gh7 & V31gh7));
+ assign V31gh7 = (!J02gh7);
+ assign Xz1gh7 = (~(By0gh7 & Fz0gh7));
+ assign Fz0gh7 = (!P02gh7);
+ assign Lz1gh7 = (V02gh7 & B12gh7);
+ assign B12gh7 = (Zp1gh7 | Ns0gh7);
+ assign V02gh7 = (~(Zs0gh7 & Ju0gh7));
+ assign Px1gh7 = (H12gh7 & N12gh7);
+ assign N12gh7 = (T12gh7 & Z12gh7);
+ assign Z12gh7 = (F22gh7 & L22gh7);
+ assign L22gh7 = (~(Hp0gh7 & Lq0gh7));
+ assign Lq0gh7 = (!R22gh7);
+ assign F22gh7 = (~(H11gh7 & L21gh7));
+ assign L21gh7 = (!X22gh7);
+ assign T12gh7 = (D32gh7 & J32gh7);
+ assign J32gh7 = (~(Lz0gh7 & P01gh7));
+ assign P01gh7 = (!P32gh7);
+ assign D32gh7 = (~(Fw0gh7 & Jx0gh7));
+ assign Jx0gh7 = (!V32gh7);
+ assign H12gh7 = (B42gh7 & Tm1gh7);
+ assign Tm1gh7 = (H42gh7 & N42gh7);
+ assign H42gh7 = (L81gh7 & Xn0gh7);
+ assign B42gh7 = (T42gh7 & Z42gh7);
+ assign Z42gh7 = (R51gh7 | Fb9gh7);
+ assign T42gh7 = (~(stdio_rx_tdata[4] & Z41gh7));
+ assign Fttfh7 = (Pl0gh7 ? com_tx_tdata[5] : F52gh7);
+ assign F52gh7 = (~(L52gh7 & R52gh7));
+ assign R52gh7 = (X52gh7 & D62gh7);
+ assign D62gh7 = (~(stdio_rx_tdata[5] & Z41gh7));
+ assign X52gh7 = (Rq0gh7 & J62gh7);
+ assign L52gh7 = (N42gh7 & P62gh7);
+ assign N42gh7 = (V62gh7 & F51gh7);
+ assign F51gh7 = (Lbvfh7 | B72gh7);
+ assign Zstfh7 = (H72gh7 & N72gh7);
+ assign N72gh7 = (~(T72gh7 & Z72gh7));
+ assign Z72gh7 = (F82gh7 & L82gh7);
+ assign L82gh7 = (R82gh7 & X82gh7);
+ assign X82gh7 = (Hp1gh7 & Xn0gh7);
+ assign R82gh7 = (D92gh7 & J92gh7);
+ assign J92gh7 = (~(J02gh7 & R21gh7));
+ assign J02gh7 = (~(Nstfh7 | Bs1gh7));
+ assign Bs1gh7 = (Hstfh7 & Bstfh7);
+ assign D92gh7 = (~(P02gh7 & By0gh7));
+ assign P02gh7 = (~(Votfh7 | Ns1gh7));
+ assign Ns1gh7 = (Potfh7 & Jotfh7);
+ assign F82gh7 = (P92gh7 & V92gh7);
+ assign V92gh7 = (~(R22gh7 & Hp0gh7));
+ assign R22gh7 = (~(Xntfh7 | Ju1gh7));
+ assign Ju1gh7 = (Rntfh7 & Lntfh7);
+ assign P92gh7 = (Ba2gh7 & Ha2gh7);
+ assign Ha2gh7 = (~(Ns0gh7 & Pr0gh7));
+ assign Ns0gh7 = (~(Zmtfh7 | Tp1gh7));
+ assign Tp1gh7 = (Tmtfh7 & Nmtfh7);
+ assign Ba2gh7 = (Ju0gh7 | Dr1gh7);
+ assign Ju0gh7 = (Bmtfh7 | Xq1gh7);
+ assign Xq1gh7 = (Vltfh7 & Pltfh7);
+ assign T72gh7 = (Na2gh7 & Ta2gh7);
+ assign Ta2gh7 = (Za2gh7 & Fb2gh7);
+ assign Fb2gh7 = (~(V32gh7 & Fw0gh7));
+ assign V32gh7 = (~(Prtfh7 | Fw1gh7));
+ assign Fw1gh7 = (Jrtfh7 & Drtfh7);
+ assign Za2gh7 = (Lb2gh7 & Rb2gh7);
+ assign Rb2gh7 = (~(X22gh7 & H11gh7));
+ assign X22gh7 = (~(Rqtfh7 | Vu1gh7));
+ assign Vu1gh7 = (Lqtfh7 & Fqtfh7);
+ assign Lb2gh7 = (~(P32gh7 & Lz0gh7));
+ assign P32gh7 = (~(Tptfh7 | Tv1gh7));
+ assign Tv1gh7 = (Nptfh7 & Hptfh7);
+ assign Na2gh7 = (Xb2gh7 & Zd1gh7);
+ assign Zd1gh7 = (Dc2gh7 & Jc2gh7);
+ assign Jc2gh7 = (Pc2gh7 & Vc2gh7);
+ assign Vc2gh7 = (Ln0gh7 & Rn0gh7);
+ assign Rn0gh7 = (~(Bd2gh7 & R21gh7));
+ assign R21gh7 = (!Hd2gh7);
+ assign Bd2gh7 = (Hm1gh7 & Re0gh7);
+ assign Re0gh7 = (!Hstfh7);
+ assign Hm1gh7 = (Bstfh7 & P31gh7);
+ assign P31gh7 = (Vrtfh7 & Zg0gh7);
+ assign Zg0gh7 = (!Nstfh7);
+ assign Ln0gh7 = (~(Nd2gh7 & Hp0gh7));
+ assign Nd2gh7 = (Ng1gh7 & Z4zfh7);
+ assign Z4zfh7 = (!Rntfh7);
+ assign Ng1gh7 = (Lntfh7 & Fq0gh7);
+ assign Fq0gh7 = (Fntfh7 & V6zfh7);
+ assign V6zfh7 = (!Xntfh7);
+ assign Pc2gh7 = (Xhzfh7 & Zy1gh7);
+ assign Dc2gh7 = (Td2gh7 & Zd2gh7);
+ assign Zd2gh7 = (~(D61gh7 | Fe2gh7));
+ assign D61gh7 = (~(Le2gh7 & Re2gh7));
+ assign Re2gh7 = (~(Xe2gh7 & Fw0gh7));
+ assign Xe2gh7 = (Vl1gh7 & L50gh7);
+ assign L50gh7 = (!Jrtfh7);
+ assign Vl1gh7 = (Drtfh7 & Dx0gh7);
+ assign Dx0gh7 = (Xqtfh7 & T70gh7);
+ assign T70gh7 = (!Prtfh7);
+ assign Le2gh7 = (Df2gh7 & Jf2gh7);
+ assign Jf2gh7 = (~(Pf2gh7 & Lz0gh7));
+ assign Pf2gh7 = (Nj1gh7 & Bmzfh7);
+ assign Bmzfh7 = (!Nptfh7);
+ assign Nj1gh7 = (Hptfh7 & J01gh7);
+ assign J01gh7 = (Bptfh7 & Jozfh7);
+ assign Jozfh7 = (!Tptfh7);
+ assign Df2gh7 = (~(Vf2gh7 & H11gh7));
+ assign H11gh7 = (!Bg2gh7);
+ assign Vf2gh7 = (Di1gh7 & Hvzfh7);
+ assign Hvzfh7 = (!Lqtfh7);
+ assign Di1gh7 = (Fqtfh7 & F21gh7);
+ assign F21gh7 = (Zptfh7 & Pxzfh7);
+ assign Pxzfh7 = (!Rqtfh7);
+ assign Td2gh7 = (~(Pl0gh7 | X51gh7));
+ assign X51gh7 = (~(Hg2gh7 & Ng2gh7));
+ assign Ng2gh7 = (~(Tg2gh7 & Pr0gh7));
+ assign Tg2gh7 = (Xk1gh7 & Zg2gh7);
+ assign Zg2gh7 = (!Tmtfh7);
+ assign Xk1gh7 = (Nmtfh7 & Nd1gh7);
+ assign Nd1gh7 = (!Ts0gh7);
+ assign Ts0gh7 = (~(Hmtfh7 & Fh2gh7));
+ assign Fh2gh7 = (!Zmtfh7);
+ assign Hg2gh7 = (Lh2gh7 & Rh2gh7);
+ assign Rh2gh7 = (~(Xh2gh7 & Zs0gh7));
+ assign Xh2gh7 = (Fh1gh7 & Di2gh7);
+ assign Di2gh7 = (!Vltfh7);
+ assign Fh1gh7 = (Pltfh7 & Du0gh7);
+ assign Du0gh7 = (~(Pu0gh7 | Bmtfh7));
+ assign Pu0gh7 = (!Jltfh7);
+ assign Lh2gh7 = (~(Ji2gh7 & By0gh7));
+ assign Ji2gh7 = (Bj1gh7 & Jczfh7);
+ assign Jczfh7 = (!Potfh7);
+ assign Bj1gh7 = (Jotfh7 & Zy0gh7);
+ assign Zy0gh7 = (Dotfh7 & Fezfh7);
+ assign Fezfh7 = (!Votfh7);
+ assign Xb2gh7 = (Pi2gh7 & Vi2gh7);
+ assign Vi2gh7 = (R51gh7 | Lb9gh7);
+ assign Pi2gh7 = (~(stdio_rx_tdata[6] & Z41gh7));
+ assign H72gh7 = (~(Rktfh7 & Pl0gh7));
+ assign Tstfh7 = (Pl0gh7 ? com_tx_tdata[7] : Bj2gh7);
+ assign Pl0gh7 = (~(Duufh7 & Hj2gh7));
+ assign Hj2gh7 = (~(Nj2gh7 & Tj2gh7));
+ assign Tj2gh7 = (Zj2gh7 | Fk2gh7);
+ assign Bj2gh7 = (stdio_rx_tdata[7] & Z41gh7);
+ assign Dltfh7 = (ahb_hready ? ahb_htrans[1] : Lk2gh7);
+ assign Xktfh7 = (Rk2gh7 & Xk2gh7);
+ assign Rk2gh7 = (~(Dl2gh7 & Jl2gh7));
+ assign ahb_htrans[1] = (~(Lk2gh7 | R29gh7));
+ assign Lk2gh7 = (!Hd9gh7);
+ assign Xzpfh7 = (~(Pl2gh7 & Vl2gh7));
+ assign Vl2gh7 = (Tyyfh7 & Bm2gh7);
+ assign Pl2gh7 = (Hm2gh7 & Xh0gh7);
+ assign O0qfh7 = (~(Nm2gh7 & Tm2gh7));
+ assign Tm2gh7 = (~(Zm2gh7 & Bdvfh7));
+ assign Nm2gh7 = (~(Jpsfh7 & Fn2gh7));
+ assign F1qfh7 = (~(Ln2gh7 & Rn2gh7));
+ assign Rn2gh7 = (~(Zm2gh7 & Jlvfh7));
+ assign Ln2gh7 = (~(Zpsfh7 & Fn2gh7));
+ assign W1qfh7 = (~(Xn2gh7 & Do2gh7));
+ assign Do2gh7 = (~(Zm2gh7 & Dovfh7));
+ assign Xn2gh7 = (~(Pqsfh7 & Fn2gh7));
+ assign N2qfh7 = (~(Jo2gh7 & Po2gh7));
+ assign Po2gh7 = (~(Zm2gh7 & Xqvfh7));
+ assign Jo2gh7 = (~(Frsfh7 & Fn2gh7));
+ assign E3qfh7 = (~(Vo2gh7 & Bp2gh7));
+ assign Bp2gh7 = (~(Zm2gh7 & Zdvfh7));
+ assign Vo2gh7 = (~(Vrsfh7 & Fn2gh7));
+ assign V3qfh7 = (~(Hp2gh7 & Np2gh7));
+ assign Np2gh7 = (~(Zm2gh7 & Vlvfh7));
+ assign Hp2gh7 = (~(Lssfh7 & Fn2gh7));
+ assign M4qfh7 = (~(Tp2gh7 & Zp2gh7));
+ assign Zp2gh7 = (~(Zm2gh7 & Povfh7));
+ assign Tp2gh7 = (~(Btsfh7 & Fn2gh7));
+ assign D5qfh7 = (~(Fq2gh7 & Lq2gh7));
+ assign Lq2gh7 = (~(Zm2gh7 & Jrvfh7));
+ assign Fq2gh7 = (~(Rtsfh7 & Fn2gh7));
+ assign U5qfh7 = (~(Rq2gh7 & Xq2gh7));
+ assign Xq2gh7 = (~(Zm2gh7 & Xtvfh7));
+ assign Rq2gh7 = (~(Husfh7 & Fn2gh7));
+ assign L6qfh7 = (~(Dr2gh7 & Jr2gh7));
+ assign Jr2gh7 = (~(Zm2gh7 & Lwvfh7));
+ assign Dr2gh7 = (~(Xusfh7 & Fn2gh7));
+ assign C7qfh7 = (~(Pr2gh7 & Vr2gh7));
+ assign Vr2gh7 = (~(Zm2gh7 & Zyvfh7));
+ assign Pr2gh7 = (~(Nvsfh7 & Fn2gh7));
+ assign T7qfh7 = (~(Bs2gh7 & Hs2gh7));
+ assign Hs2gh7 = (~(Zm2gh7 & N1wfh7));
+ assign Bs2gh7 = (~(Dwsfh7 & Fn2gh7));
+ assign K8qfh7 = (~(Ns2gh7 & Ts2gh7));
+ assign Ts2gh7 = (~(Zm2gh7 & B4wfh7));
+ assign Ns2gh7 = (~(Twsfh7 & Fn2gh7));
+ assign B9qfh7 = (~(Zs2gh7 & Ft2gh7));
+ assign Ft2gh7 = (~(Zm2gh7 & P6wfh7));
+ assign Zs2gh7 = (~(Jxsfh7 & Fn2gh7));
+ assign S9qfh7 = (~(Lt2gh7 & Rt2gh7));
+ assign Rt2gh7 = (~(Zm2gh7 & D9wfh7));
+ assign Lt2gh7 = (~(Zxsfh7 & Fn2gh7));
+ assign Jaqfh7 = (~(Xt2gh7 & Du2gh7));
+ assign Du2gh7 = (~(Zm2gh7 & Rbwfh7));
+ assign Xt2gh7 = (~(Pysfh7 & Fn2gh7));
+ assign Abqfh7 = (~(Ju2gh7 & Pu2gh7));
+ assign Pu2gh7 = (~(Zm2gh7 & Fewfh7));
+ assign Ju2gh7 = (~(Fzsfh7 & Fn2gh7));
+ assign Rbqfh7 = (~(Vu2gh7 & Bv2gh7));
+ assign Bv2gh7 = (~(Zm2gh7 & Tgwfh7));
+ assign Vu2gh7 = (~(Vzsfh7 & Fn2gh7));
+ assign Icqfh7 = (~(Hv2gh7 & Nv2gh7));
+ assign Nv2gh7 = (~(Zm2gh7 & Hjwfh7));
+ assign Hv2gh7 = (~(L0tfh7 & Fn2gh7));
+ assign Zcqfh7 = (~(Tv2gh7 & Zv2gh7));
+ assign Zv2gh7 = (~(Zm2gh7 & Vlwfh7));
+ assign Tv2gh7 = (~(B1tfh7 & Fn2gh7));
+ assign Qdqfh7 = (~(Fw2gh7 & Lw2gh7));
+ assign Lw2gh7 = (~(Zm2gh7 & Jowfh7));
+ assign Fw2gh7 = (~(R1tfh7 & Fn2gh7));
+ assign Heqfh7 = (~(Rw2gh7 & Xw2gh7));
+ assign Xw2gh7 = (~(Zm2gh7 & Xqwfh7));
+ assign Rw2gh7 = (~(H2tfh7 & Fn2gh7));
+ assign Yeqfh7 = (~(Dx2gh7 & Jx2gh7));
+ assign Jx2gh7 = (~(Zm2gh7 & Ltwfh7));
+ assign Dx2gh7 = (~(X2tfh7 & Fn2gh7));
+ assign Pfqfh7 = (~(Px2gh7 & Vx2gh7));
+ assign Vx2gh7 = (~(Zm2gh7 & Zvwfh7));
+ assign Px2gh7 = (~(N3tfh7 & Fn2gh7));
+ assign Ggqfh7 = (~(By2gh7 & Hy2gh7));
+ assign Hy2gh7 = (~(Zm2gh7 & Rwufh7));
+ assign By2gh7 = (~(D4tfh7 & Fn2gh7));
+ assign Xgqfh7 = (~(Ny2gh7 & Ty2gh7));
+ assign Ty2gh7 = (~(Zm2gh7 & Vxufh7));
+ assign Ny2gh7 = (~(T4tfh7 & Fn2gh7));
+ assign Ohqfh7 = (~(Zy2gh7 & Fz2gh7));
+ assign Fz2gh7 = (~(Zm2gh7 & Zyufh7));
+ assign Zy2gh7 = (~(J5tfh7 & Fn2gh7));
+ assign Fiqfh7 = (~(Lz2gh7 & Rz2gh7));
+ assign Rz2gh7 = (~(Zm2gh7 & D0vfh7));
+ assign Lz2gh7 = (~(Z5tfh7 & Fn2gh7));
+ assign Wiqfh7 = (~(Xz2gh7 & D03gh7));
+ assign D03gh7 = (~(Zm2gh7 & H1vfh7));
+ assign Xz2gh7 = (~(P6tfh7 & Fn2gh7));
+ assign Njqfh7 = (~(J03gh7 & P03gh7));
+ assign P03gh7 = (~(Zm2gh7 & L2vfh7));
+ assign J03gh7 = (~(F7tfh7 & Fn2gh7));
+ assign Ekqfh7 = (~(V03gh7 & B13gh7));
+ assign B13gh7 = (~(Zm2gh7 & P3vfh7));
+ assign V03gh7 = (~(V7tfh7 & Fn2gh7));
+ assign Vkqfh7 = (~(H13gh7 & N13gh7));
+ assign N13gh7 = (~(Zm2gh7 & Z4vfh7));
+ assign Zm2gh7 = (~(Xtxfh7 | Lqxfh7));
+ assign Lqxfh7 = (!B1yfh7);
+ assign H13gh7 = (~(L8tfh7 & Fn2gh7));
+ assign Fn2gh7 = (~(T13gh7 & Z13gh7));
+ assign Z13gh7 = (F23gh7 & L23gh7);
+ assign L23gh7 = (R23gh7 & X23gh7);
+ assign R23gh7 = (D33gh7 & J33gh7);
+ assign F23gh7 = (P33gh7 & R51gh7);
+ assign P33gh7 = (Xhzfh7 & B1yfh7);
+ assign B1yfh7 = (~(V33gh7 & B43gh7));
+ assign B43gh7 = (H43gh7 & N43gh7);
+ assign N43gh7 = (T43gh7 & Z43gh7);
+ assign Z43gh7 = (F53gh7 & L53gh7);
+ assign L53gh7 = (Vlvfh7 & Jlvfh7);
+ assign Jlvfh7 = (!D39gh7);
+ assign Vlvfh7 = (!J39gh7);
+ assign F53gh7 = (P6wfh7 & Lwvfh7);
+ assign Lwvfh7 = (!P39gh7);
+ assign P6wfh7 = (!V39gh7);
+ assign T43gh7 = (R53gh7 & X53gh7);
+ assign X53gh7 = (Xqwfh7 & Tgwfh7);
+ assign Tgwfh7 = (!B49gh7);
+ assign Xqwfh7 = (!H49gh7);
+ assign R53gh7 = (Zdvfh7 & Vxufh7);
+ assign Vxufh7 = (!N49gh7);
+ assign Zdvfh7 = (!T49gh7);
+ assign H43gh7 = (D63gh7 & J63gh7);
+ assign J63gh7 = (P63gh7 & V63gh7);
+ assign V63gh7 = (B4wfh7 & Xtvfh7);
+ assign Xtvfh7 = (!Z49gh7);
+ assign B4wfh7 = (!F59gh7);
+ assign P63gh7 = (Jowfh7 & Fewfh7);
+ assign Fewfh7 = (!L59gh7);
+ assign Jowfh7 = (!R59gh7);
+ assign D63gh7 = (B73gh7 & H73gh7);
+ assign H73gh7 = (Xqvfh7 & Rwufh7);
+ assign Rwufh7 = (!X59gh7);
+ assign Xqvfh7 = (!D69gh7);
+ assign B73gh7 = (N1wfh7 & Jrvfh7);
+ assign Jrvfh7 = (!J69gh7);
+ assign N1wfh7 = (!P69gh7);
+ assign V33gh7 = (N73gh7 & T73gh7);
+ assign T73gh7 = (Z73gh7 & F83gh7);
+ assign F83gh7 = (L83gh7 & R83gh7);
+ assign R83gh7 = (Vlwfh7 & Rbwfh7);
+ assign Rbwfh7 = (!V69gh7);
+ assign Vlwfh7 = (!B79gh7);
+ assign L83gh7 = (H1vfh7 & Zvwfh7);
+ assign Zvwfh7 = (!H79gh7);
+ assign H1vfh7 = (!N79gh7);
+ assign Z73gh7 = (X83gh7 & D93gh7);
+ assign D93gh7 = (Bdvfh7 & L2vfh7);
+ assign L2vfh7 = (!T79gh7);
+ assign Bdvfh7 = (!Z79gh7);
+ assign X83gh7 = (Povfh7 & Dovfh7);
+ assign Dovfh7 = (!F89gh7);
+ assign Povfh7 = (!L89gh7);
+ assign N73gh7 = (J93gh7 & P93gh7);
+ assign P93gh7 = (V93gh7 & Ba3gh7);
+ assign Ba3gh7 = (D9wfh7 & Zyvfh7);
+ assign Zyvfh7 = (!R89gh7);
+ assign D9wfh7 = (!X89gh7);
+ assign V93gh7 = (Ltwfh7 & Hjwfh7);
+ assign Hjwfh7 = (!D99gh7);
+ assign Ltwfh7 = (!J99gh7);
+ assign J93gh7 = (Ha3gh7 & Na3gh7);
+ assign Na3gh7 = (D0vfh7 & Zyufh7);
+ assign Zyufh7 = (!P99gh7);
+ assign D0vfh7 = (!Dc9gh7);
+ assign Ha3gh7 = (P3vfh7 & Z4vfh7);
+ assign Z4vfh7 = (!Jc9gh7);
+ assign P3vfh7 = (!Vc9gh7);
+ assign T13gh7 = (Ta3gh7 & Za3gh7);
+ assign Za3gh7 = (Fb3gh7 & Lb3gh7);
+ assign Fb3gh7 = (~(Rb3gh7 | Fe2gh7));
+ assign Ta3gh7 = (Xb3gh7 & Dc3gh7);
+ assign Xb3gh7 = (Lk0gh7 & Jc3gh7);
+ assign Jc3gh7 = (!Pc3gh7);
+ assign Lk0gh7 = (~(Vc3gh7 | Bd3gh7));
+ assign Mlqfh7 = (~(Havfh7 & Hd3gh7));
+ assign Havfh7 = (Nd3gh7 & Td3gh7);
+ assign Td3gh7 = (!Vrufh7);
+ assign Vrufh7 = (~(Zd3gh7 & Fe3gh7));
+ assign Fe3gh7 = (Le3gh7 & Tyyfh7);
+ assign Le3gh7 = (Di0gh7 & Re3gh7);
+ assign Zd3gh7 = (Xe3gh7 & Xh0gh7);
+ assign Dmqfh7 = (~(Df3gh7 & Jf3gh7));
+ assign Jf3gh7 = (~(B5sfh7 & Pf3gh7));
+ assign Df3gh7 = (Vf3gh7 | Z79gh7);
+ assign Umqfh7 = (~(Bg3gh7 & Hg3gh7));
+ assign Hg3gh7 = (~(R5sfh7 & Pf3gh7));
+ assign Bg3gh7 = (Vf3gh7 | D39gh7);
+ assign Lnqfh7 = (~(Ng3gh7 & Tg3gh7));
+ assign Tg3gh7 = (~(H6sfh7 & Pf3gh7));
+ assign Ng3gh7 = (Vf3gh7 | F89gh7);
+ assign Coqfh7 = (~(Zg3gh7 & Fh3gh7));
+ assign Fh3gh7 = (~(X6sfh7 & Pf3gh7));
+ assign Zg3gh7 = (Vf3gh7 | D69gh7);
+ assign Toqfh7 = (~(Lh3gh7 & Rh3gh7));
+ assign Rh3gh7 = (~(N7sfh7 & Pf3gh7));
+ assign Lh3gh7 = (Vf3gh7 | T49gh7);
+ assign Kpqfh7 = (~(Xh3gh7 & Di3gh7));
+ assign Di3gh7 = (~(D8sfh7 & Pf3gh7));
+ assign Xh3gh7 = (Vf3gh7 | J39gh7);
+ assign Bqqfh7 = (~(Ji3gh7 & Pi3gh7));
+ assign Pi3gh7 = (~(T8sfh7 & Pf3gh7));
+ assign Ji3gh7 = (Vf3gh7 | L89gh7);
+ assign Sqqfh7 = (~(Vi3gh7 & Bj3gh7));
+ assign Bj3gh7 = (~(J9sfh7 & Pf3gh7));
+ assign Vi3gh7 = (Vf3gh7 | J69gh7);
+ assign Jrqfh7 = (~(Hj3gh7 & Nj3gh7));
+ assign Nj3gh7 = (~(Z9sfh7 & Pf3gh7));
+ assign Hj3gh7 = (Vf3gh7 | Z49gh7);
+ assign Asqfh7 = (~(Tj3gh7 & Zj3gh7));
+ assign Zj3gh7 = (~(Pasfh7 & Pf3gh7));
+ assign Tj3gh7 = (Vf3gh7 | P39gh7);
+ assign Rsqfh7 = (~(Fk3gh7 & Lk3gh7));
+ assign Lk3gh7 = (~(Fbsfh7 & Pf3gh7));
+ assign Fk3gh7 = (Vf3gh7 | R89gh7);
+ assign Itqfh7 = (~(Rk3gh7 & Xk3gh7));
+ assign Xk3gh7 = (~(Vbsfh7 & Pf3gh7));
+ assign Rk3gh7 = (Vf3gh7 | P69gh7);
+ assign Ztqfh7 = (~(Dl3gh7 & Jl3gh7));
+ assign Jl3gh7 = (~(Lcsfh7 & Pf3gh7));
+ assign Dl3gh7 = (Vf3gh7 | F59gh7);
+ assign Quqfh7 = (~(Pl3gh7 & Vl3gh7));
+ assign Vl3gh7 = (~(Bdsfh7 & Pf3gh7));
+ assign Pl3gh7 = (Vf3gh7 | V39gh7);
+ assign Hvqfh7 = (~(Bm3gh7 & Hm3gh7));
+ assign Hm3gh7 = (~(Rdsfh7 & Pf3gh7));
+ assign Bm3gh7 = (Vf3gh7 | X89gh7);
+ assign Yvqfh7 = (~(Nm3gh7 & Tm3gh7));
+ assign Tm3gh7 = (~(Hesfh7 & Pf3gh7));
+ assign Nm3gh7 = (Vf3gh7 | V69gh7);
+ assign Pwqfh7 = (~(Zm3gh7 & Fn3gh7));
+ assign Fn3gh7 = (~(Xesfh7 & Pf3gh7));
+ assign Zm3gh7 = (Vf3gh7 | L59gh7);
+ assign Gxqfh7 = (~(Ln3gh7 & Rn3gh7));
+ assign Rn3gh7 = (~(Nfsfh7 & Pf3gh7));
+ assign Ln3gh7 = (Vf3gh7 | B49gh7);
+ assign Xxqfh7 = (~(Xn3gh7 & Do3gh7));
+ assign Do3gh7 = (~(Dgsfh7 & Pf3gh7));
+ assign Xn3gh7 = (Vf3gh7 | D99gh7);
+ assign Oyqfh7 = (~(Jo3gh7 & Po3gh7));
+ assign Po3gh7 = (~(Tgsfh7 & Pf3gh7));
+ assign Jo3gh7 = (Vf3gh7 | B79gh7);
+ assign Fzqfh7 = (~(Vo3gh7 & Bp3gh7));
+ assign Bp3gh7 = (~(Jhsfh7 & Pf3gh7));
+ assign Vo3gh7 = (Vf3gh7 | R59gh7);
+ assign Wzqfh7 = (~(Hp3gh7 & Np3gh7));
+ assign Np3gh7 = (~(Zhsfh7 & Pf3gh7));
+ assign Hp3gh7 = (Vf3gh7 | H49gh7);
+ assign N0rfh7 = (~(Tp3gh7 & Zp3gh7));
+ assign Zp3gh7 = (~(Pisfh7 & Pf3gh7));
+ assign Tp3gh7 = (Vf3gh7 | J99gh7);
+ assign E1rfh7 = (~(Fq3gh7 & Lq3gh7));
+ assign Lq3gh7 = (~(Fjsfh7 & Pf3gh7));
+ assign Fq3gh7 = (Vf3gh7 | H79gh7);
+ assign V1rfh7 = (~(Rq3gh7 & Xq3gh7));
+ assign Xq3gh7 = (~(Vjsfh7 & Pf3gh7));
+ assign Rq3gh7 = (Vf3gh7 | X59gh7);
+ assign M2rfh7 = (~(Dr3gh7 & Jr3gh7));
+ assign Jr3gh7 = (~(Lksfh7 & Pf3gh7));
+ assign Dr3gh7 = (Vf3gh7 | N49gh7);
+ assign D3rfh7 = (~(Pr3gh7 & Vr3gh7));
+ assign Vr3gh7 = (~(Blsfh7 & Pf3gh7));
+ assign Pr3gh7 = (Vf3gh7 | P99gh7);
+ assign U3rfh7 = (~(Bs3gh7 & Hs3gh7));
+ assign Hs3gh7 = (~(Rlsfh7 & Pf3gh7));
+ assign Bs3gh7 = (Vf3gh7 | Dc9gh7);
+ assign L4rfh7 = (~(Ns3gh7 & Ts3gh7));
+ assign Ts3gh7 = (~(Hmsfh7 & Pf3gh7));
+ assign Ns3gh7 = (Vf3gh7 | N79gh7);
+ assign C5rfh7 = (~(Zs3gh7 & Ft3gh7));
+ assign Ft3gh7 = (~(Xmsfh7 & Pf3gh7));
+ assign Zs3gh7 = (Vf3gh7 | T79gh7);
+ assign T5rfh7 = (~(Lt3gh7 & Rt3gh7));
+ assign Rt3gh7 = (~(Nnsfh7 & Pf3gh7));
+ assign Lt3gh7 = (Vf3gh7 | Vc9gh7);
+ assign K6rfh7 = (~(Xt3gh7 & Du3gh7));
+ assign Du3gh7 = (~(Dosfh7 & Pf3gh7));
+ assign Pf3gh7 = (~(Ju3gh7 & Dc3gh7));
+ assign Dc3gh7 = (Pu3gh7 & Vu3gh7);
+ assign Vu3gh7 = (Bv3gh7 & Hv3gh7);
+ assign Hv3gh7 = (Nv3gh7 & Tv3gh7);
+ assign Nv3gh7 = (Drxfh7 & Zv3gh7);
+ assign Bv3gh7 = (Fw3gh7 & Nd3gh7);
+ assign Pu3gh7 = (Lw3gh7 & Rw3gh7);
+ assign Rw3gh7 = (Xw3gh7 & Dx3gh7);
+ assign Lw3gh7 = (Tavfh7 & Jx3gh7);
+ assign Ju3gh7 = (~(Px3gh7 | Vx3gh7));
+ assign Xt3gh7 = (Vf3gh7 | Jc9gh7);
+ assign B7rfh7 = (~(By3gh7 & Hy3gh7));
+ assign Hy3gh7 = (~(stdio_tx_tready & Ny3gh7));
+ assign Ny3gh7 = (~(F5vfh7 & Ty3gh7));
+ assign S7rfh7 = (~(Zy3gh7 & Fk2gh7));
+ assign Fk2gh7 = (Fz3gh7 & Lz3gh7);
+ assign Lz3gh7 = (Rz3gh7 & Xq0gh7);
+ assign Rz3gh7 = (~(Fe8gh7 & Jl2gh7));
+ assign Fz3gh7 = (P62gh7 & Xz3gh7);
+ assign Zy3gh7 = (Nj2gh7 & D04gh7);
+ assign D04gh7 = (~(J04gh7 & Zj2gh7));
+ assign J04gh7 = (~(P04gh7 & Lb3gh7));
+ assign P04gh7 = (Xn0gh7 & Tv3gh7);
+ assign Nj2gh7 = (V04gh7 & B14gh7);
+ assign B14gh7 = (H14gh7 & N14gh7);
+ assign N14gh7 = (J62gh7 & T14gh7);
+ assign H14gh7 = (Jx3gh7 & Z14gh7);
+ assign V04gh7 = (F24gh7 & L24gh7);
+ assign L24gh7 = (R24gh7 & X24gh7);
+ assign R24gh7 = (~(D34gh7 & Z41gh7));
+ assign Z41gh7 = (!J34gh7);
+ assign F24gh7 = (P34gh7 & V34gh7);
+ assign J8rfh7 = (~(B44gh7 & H44gh7));
+ assign H44gh7 = (N44gh7 | P09gh7);
+ assign B44gh7 = (L81gh7 | Zj2gh7);
+ assign A9rfh7 = (~(T44gh7 & Z44gh7));
+ assign Z44gh7 = (F54gh7 | X29gh7);
+ assign T44gh7 = (~(L54gh7 & D34gh7));
+ assign R9rfh7 = (~(R54gh7 & X54gh7));
+ assign X54gh7 = (~(D64gh7 & J64gh7));
+ assign Iarfh7 = (~(T14gh7 & P64gh7));
+ assign P64gh7 = (V64gh7 | Xt8gh7);
+ assign T14gh7 = (~(B74gh7 & H74gh7));
+ assign H74gh7 = (~(V62gh7 | com_rx_tvalid));
+ assign B74gh7 = (stdio_rx_tvalid & com_tx_tready);
+ assign Zarfh7 = (~(N74gh7 & T74gh7));
+ assign T74gh7 = (V64gh7 | Vu8gh7);
+ assign N74gh7 = (X24gh7 & Jx3gh7);
+ assign Jx3gh7 = (~(Z74gh7 & F84gh7));
+ assign F84gh7 = (L84gh7 & R84gh7);
+ assign R84gh7 = (X84gh7 & Nd3gh7);
+ assign X84gh7 = (Tv3gh7 & Zv3gh7);
+ assign L84gh7 = (Dx3gh7 & Fw3gh7);
+ assign Z74gh7 = (D94gh7 & J94gh7);
+ assign J94gh7 = (Tavfh7 & Xw3gh7);
+ assign Tavfh7 = (P94gh7 & V94gh7);
+ assign V94gh7 = (~(Ba4gh7 | Ha4gh7));
+ assign P94gh7 = (Xh0gh7 & Na4gh7);
+ assign D94gh7 = (~(Ta4gh7 | Px3gh7));
+ assign Px3gh7 = (~(Za4gh7 & Fb4gh7));
+ assign Fb4gh7 = (Lb3gh7 & Hm2gh7);
+ assign Lb3gh7 = (Lb4gh7 & Rb4gh7);
+ assign Za4gh7 = (~(Pc3gh7 | Rq0gh7));
+ assign Rq0gh7 = (~(Xb4gh7 & Plyfh7));
+ assign Plyfh7 = (Z1zfh7 & Do0gh7);
+ assign Z1zfh7 = (~(Pizfh7 | N10gh7));
+ assign N10gh7 = (!Xhzfh7);
+ assign Pizfh7 = (~(R51gh7 & Lbvfh7));
+ assign Xb4gh7 = (~(Rb3gh7 | Bd3gh7));
+ assign Rb3gh7 = (~(Dc4gh7 & Jc4gh7));
+ assign Jc4gh7 = (Rw1gh7 & J62gh7);
+ assign Rw1gh7 = (Pc4gh7 & Vc4gh7);
+ assign Vc4gh7 = (V62gh7 & Xn0gh7);
+ assign Pc4gh7 = (Fe1gh7 & Xq0gh7);
+ assign Fe1gh7 = (Bd4gh7 & Xz3gh7);
+ assign Bd4gh7 = (T4vfh7 & F5vfh7);
+ assign Dc4gh7 = (J34gh7 & P62gh7);
+ assign P62gh7 = (Hd4gh7 & Nd4gh7);
+ assign Nd4gh7 = (Td4gh7 & Zd4gh7);
+ assign Zd4gh7 = (Fe4gh7 & Fz1gh7);
+ assign Td4gh7 = (Le4gh7 & Re4gh7);
+ assign Hd4gh7 = (Xe4gh7 & Df4gh7);
+ assign Xe4gh7 = (~(Jf4gh7 | Pf4gh7));
+ assign X24gh7 = (~(Vf4gh7 & Bg4gh7));
+ assign Bg4gh7 = (~(Hg4gh7 | Ng4gh7));
+ assign Vf4gh7 = (Tg4gh7 & Rqxfh7);
+ assign Qbrfh7 = (~(V34gh7 & Zg4gh7));
+ assign Zg4gh7 = (Fh4gh7 | Lw8gh7);
+ assign V34gh7 = (Ji0gh7 & Lh4gh7);
+ assign Lh4gh7 = (~(Bd3gh7 & Vi0gh7));
+ assign Bd3gh7 = (!Zy1gh7);
+ assign Ji0gh7 = (Rh4gh7 & Xh4gh7);
+ assign Xh4gh7 = (Di4gh7 | Ji4gh7);
+ assign Di4gh7 = (~(Fe2gh7 & stdio_tx_tready));
+ assign Fe2gh7 = (!Do0gh7);
+ assign Rh4gh7 = (R51gh7 & Xhzfh7);
+ assign Xhzfh7 = (~(Pi4gh7 & Vi4gh7));
+ assign Vi4gh7 = (Z19gh7 & Bj4gh7);
+ assign R51gh7 = (~(Hj4gh7 & Nj4gh7));
+ assign Nj4gh7 = (Tj4gh7 & Lw8gh7);
+ assign Tj4gh7 = (~(Zj4gh7 | Fw8gh7));
+ assign Hj4gh7 = (Fk4gh7 & Xb9gh7);
+ assign Hcrfh7 = (~(Lk4gh7 & Rk4gh7));
+ assign Rk4gh7 = (Xk4gh7 & Dl4gh7);
+ assign Dl4gh7 = (~(Jl4gh7 & Pl4gh7));
+ assign Pl4gh7 = (~(Vl4gh7 & Bm4gh7));
+ assign Bm4gh7 = (~(Hm4gh7 & Tg4gh7));
+ assign Hm4gh7 = (Hg4gh7 & Rqxfh7);
+ assign Vl4gh7 = (~(Bjyfh7 & Nm4gh7));
+ assign Nm4gh7 = (Tm4gh7 | Zm4gh7);
+ assign Jl4gh7 = (!Fn4gh7);
+ assign Xk4gh7 = (D0yfh7 & Xtxfh7);
+ assign Xtxfh7 = (Ln4gh7 | Rn4gh7);
+ assign Ln4gh7 = (Lbvfh7 | Xn4gh7);
+ assign D0yfh7 = (~(Rqxfh7 & Do4gh7));
+ assign Do4gh7 = (Jo4gh7 | Fqxfh7);
+ assign Fqxfh7 = (Tg4gh7 & Ng4gh7);
+ assign Jo4gh7 = (~(Hjyfh7 | Po4gh7));
+ assign Lk4gh7 = (Vo4gh7 & Bp4gh7);
+ assign Bp4gh7 = (~(Vi0gh7 & Hp4gh7));
+ assign Hp4gh7 = (~(Na4gh7 & Np4gh7));
+ assign Np4gh7 = (~(Tp4gh7 & Zp4gh7));
+ assign Vo4gh7 = (~(Fq4gh7 & Tp4gh7));
+ assign Ycrfh7 = (~(Xh0gh7 & Lq4gh7));
+ assign Lq4gh7 = (V64gh7 | Pu8gh7);
+ assign Xh0gh7 = (~(Rq4gh7 & Xq4gh7));
+ assign Rq4gh7 = (~(Dr4gh7 | Du8gh7));
+ assign Pdrfh7 = (~(Jr4gh7 & Pr4gh7));
+ assign Pr4gh7 = (~(Vr4gh7 & Bs4gh7));
+ assign Bs4gh7 = (Rqxfh7 & Fn4gh7);
+ assign Vr4gh7 = (Tg4gh7 & Hg4gh7);
+ assign Tg4gh7 = (Hs4gh7 & Ns4gh7);
+ assign Ns4gh7 = (Hjyfh7 & Ts4gh7);
+ assign Hjyfh7 = (~(Zs4gh7 & Ft4gh7));
+ assign Zs4gh7 = (Lt4gh7 & Rt4gh7);
+ assign Hs4gh7 = (~(Po4gh7 | Zm4gh7));
+ assign Jr4gh7 = (~(Xt4gh7 & Ba4gh7));
+ assign Gerfh7 = (Vc3gh7 & Vi0gh7);
+ assign Xerfh7 = (~(Nd3gh7 & Du4gh7));
+ assign Du4gh7 = (V64gh7 | Ju8gh7);
+ assign Nd3gh7 = (~(Ju4gh7 & Pu4gh7));
+ assign Pu4gh7 = (L29gh7 & Vu4gh7);
+ assign Vu4gh7 = (!Tv8gh7);
+ assign Ofrfh7 = (~(Bv4gh7 & Hv4gh7));
+ assign Hv4gh7 = (~(Nv4gh7 & Zm4gh7));
+ assign Zm4gh7 = (Rbvfh7 & Ft4gh7);
+ assign Nv4gh7 = (Bjyfh7 & Fn4gh7);
+ assign Bv4gh7 = (~(Tv4gh7 & Fq4gh7));
+ assign Tv4gh7 = (~(Tp4gh7 | Zv4gh7));
+ assign Fgrfh7 = (~(Tyyfh7 & Fw4gh7));
+ assign Fw4gh7 = (Lw4gh7 | Zv8gh7);
+ assign Tyyfh7 = (~(Nmyfh7 & Rezfh7));
+ assign Wgrfh7 = (Rw4gh7 ? Nmyfh7 : R2zfh7);
+ assign Nmyfh7 = (!Fbvfh7);
+ assign Nhrfh7 = (Rw4gh7 ? R2zfh7 : Hjzfh7);
+ assign R2zfh7 = (!Xw4gh7);
+ assign Hjzfh7 = (!Dx4gh7);
+ assign Eirfh7 = (!Jx4gh7);
+ assign Jx4gh7 = (Rezfh7 ? Dl0gh7 : Px4gh7);
+ assign Px4gh7 = (Vx4gh7 | D09gh7);
+ assign Virfh7 = (~(By4gh7 & Hy4gh7));
+ assign Hy4gh7 = (V64gh7 | Nv8gh7);
+ assign By4gh7 = (Ny4gh7 & Fw3gh7);
+ assign Ny4gh7 = (~(Xt4gh7 & Ha4gh7));
+ assign Xt4gh7 = (Vi0gh7 & Ty4gh7);
+ assign Mjrfh7 = (Zy4gh7 & Bjyfh7);
+ assign Bjyfh7 = (~(Po4gh7 | Lbvfh7));
+ assign Po4gh7 = (~(Fz4gh7 & Lz4gh7));
+ assign Fz4gh7 = (~(Rz4gh7 | B72gh7));
+ assign Rz4gh7 = (Ng4gh7 & Rt4gh7);
+ assign Zy4gh7 = (Tm4gh7 & Fn4gh7);
+ assign Fn4gh7 = (~(Xz4gh7 & D05gh7));
+ assign D05gh7 = (J05gh7 & P05gh7);
+ assign P05gh7 = (V05gh7 & T79gh7);
+ assign V05gh7 = (Vc9gh7 & Zayfh7);
+ assign Zayfh7 = (J99gh7 & Diyfh7);
+ assign Diyfh7 = (B15gh7 & H15gh7);
+ assign H15gh7 = (N15gh7 & T15gh7);
+ assign T15gh7 = (Z15gh7 & F25gh7);
+ assign F25gh7 = (L25gh7 & R89gh7);
+ assign L25gh7 = (X89gh7 & D99gh7);
+ assign Z15gh7 = (R25gh7 & Z79gh7);
+ assign R25gh7 = (F89gh7 & L89gh7);
+ assign N15gh7 = (X25gh7 & D35gh7);
+ assign D35gh7 = (J35gh7 & P69gh7);
+ assign J35gh7 = (V69gh7 & B79gh7);
+ assign X25gh7 = (D69gh7 & J69gh7);
+ assign B15gh7 = (P35gh7 & V35gh7);
+ assign V35gh7 = (B45gh7 & H45gh7);
+ assign H45gh7 = (N45gh7 & F59gh7);
+ assign N45gh7 = (L59gh7 & R59gh7);
+ assign B45gh7 = (T45gh7 & H49gh7);
+ assign T45gh7 = (T49gh7 & Z49gh7);
+ assign P35gh7 = (Z45gh7 & F55gh7);
+ assign F55gh7 = (L55gh7 & P39gh7);
+ assign L55gh7 = (V39gh7 & B49gh7);
+ assign Z45gh7 = (D39gh7 & J39gh7);
+ assign J05gh7 = (Dc9gh7 & N79gh7);
+ assign Xz4gh7 = (R55gh7 & X55gh7);
+ assign X55gh7 = (N49gh7 & P99gh7);
+ assign R55gh7 = (H79gh7 & X59gh7);
+ assign Dkrfh7 = (~(D65gh7 & J65gh7));
+ assign J65gh7 = (~(P65gh7 & D34gh7));
+ assign D65gh7 = (F54gh7 | J09gh7);
+ assign Ukrfh7 = (~(V65gh7 & B75gh7));
+ assign B75gh7 = (V64gh7 | Ft8gh7);
+ assign Llrfh7 = (~(H75gh7 & N75gh7));
+ assign N75gh7 = (~(D6vfh7 & stdio_tx_tready));
+ assign H75gh7 = (V64gh7 | L29gh7);
+ assign Cmrfh7 = (~(T75gh7 & Z75gh7));
+ assign Z75gh7 = (V64gh7 | Hv8gh7);
+ assign T75gh7 = (Zv3gh7 | F85gh7);
+ assign Tmrfh7 = (~(L85gh7 & R85gh7));
+ assign R85gh7 = (X85gh7 & D95gh7);
+ assign D95gh7 = (~(Xn4gh7 & J95gh7));
+ assign J95gh7 = (~(Lbvfh7 & P95gh7));
+ assign P95gh7 = (~(Rezfh7 & Ta4gh7));
+ assign Xn4gh7 = (!J33gh7);
+ assign X85gh7 = (~(Dl2gh7 & V95gh7));
+ assign V95gh7 = (~(Tv3gh7 & Ba5gh7));
+ assign Ba5gh7 = (~(Jl2gh7 & Xk2gh7));
+ assign Xk2gh7 = (!Fe8gh7);
+ assign L85gh7 = (~(Ha5gh7 | Na5gh7));
+ assign Na5gh7 = (~(Fh4gh7 | Lz8gh7));
+ assign Ha5gh7 = (stdio_tx_tready ? Ta5gh7 : D6vfh7);
+ assign Ta5gh7 = (~(Xw3gh7 | Ji4gh7));
+ assign Ji4gh7 = (!stdio_tx_tvalid);
+ assign D6vfh7 = (!Ty3gh7);
+ assign Ty3gh7 = (~(Za5gh7 & Rezfh7));
+ assign Za5gh7 = (~(T4vfh7 | Fb5gh7));
+ assign Knrfh7 = (~(Z14gh7 & Lb5gh7));
+ assign Lb5gh7 = (V64gh7 | F29gh7);
+ assign Z14gh7 = (~(Rb5gh7 & B72gh7));
+ assign B72gh7 = (Hg4gh7 & Na9gh7);
+ assign Hg4gh7 = (Xb5gh7 & Ft4gh7);
+ assign Xb5gh7 = (Dc5gh7 & F8vfh7);
+ assign Rb5gh7 = (Lz4gh7 & Rqxfh7);
+ assign Borfh7 = (~(Di0gh7 & Jc5gh7));
+ assign Jc5gh7 = (V64gh7 | B19gh7);
+ assign Di0gh7 = (~(Pc5gh7 & Vc5gh7));
+ assign Vc5gh7 = (Rqxfh7 & Rt4gh7);
+ assign Pc5gh7 = (Ng4gh7 & Lz4gh7);
+ assign Lz4gh7 = (Bd5gh7 & Hd5gh7);
+ assign Hd5gh7 = (~(Rbvfh7 & Nd5gh7));
+ assign Ng4gh7 = (Td5gh7 & Zd5gh7);
+ assign Sorfh7 = (Fe5gh7 & Tm4gh7);
+ assign Fe5gh7 = (Le5gh7 & Rt4gh7);
+ assign Le5gh7 = (!D33gh7);
+ assign Jprfh7 = (~(Re5gh7 & Xe5gh7));
+ assign Xe5gh7 = (V64gh7 | Z19gh7);
+ assign Re5gh7 = (~(X5vfh7 & stdio_tx_tready));
+ assign Aqrfh7 = (Df5gh7 & Jf5gh7);
+ assign Jf5gh7 = (Rqxfh7 & Nd5gh7);
+ assign Df5gh7 = (Bd5gh7 & Rbvfh7);
+ assign Bd5gh7 = (Pf5gh7 & Vf5gh7);
+ assign Pf5gh7 = (Bg5gh7 & Hg5gh7);
+ assign Bg5gh7 = (~(Tm4gh7 & Rt4gh7));
+ assign Tm4gh7 = (!Ts4gh7);
+ assign Ts4gh7 = (Ng5gh7 | Na9gh7);
+ assign Rqrfh7 = (~(Re3gh7 & Tg5gh7));
+ assign Tg5gh7 = (V64gh7 | H19gh7);
+ assign Re3gh7 = (D33gh7 | Hg5gh7);
+ assign Hg5gh7 = (~(Rbvfh7 & Zd5gh7));
+ assign Zd5gh7 = (Nd5gh7 & Zg5gh7);
+ assign Zg5gh7 = (~(Ta9gh7 & Rt4gh7));
+ assign Rbvfh7 = (Fh5gh7 & Lt4gh7);
+ assign Lt4gh7 = (~(Lh5gh7 & Rh5gh7));
+ assign Lh5gh7 = (Ta9gh7 ? Di5gh7 : Xh5gh7);
+ assign Di5gh7 = (~(Td5gh7 & Za9gh7));
+ assign Td5gh7 = (~(Fb9gh7 | Na9gh7));
+ assign Xh5gh7 = (~(Ji5gh7 & Fb9gh7));
+ assign Ji5gh7 = (Na9gh7 & F8vfh7);
+ assign F8vfh7 = (!Za9gh7);
+ assign Fh5gh7 = (~(Na9gh7 & Rh5gh7));
+ assign D33gh7 = (~(Vf5gh7 & Rqxfh7));
+ assign Rqxfh7 = (!Lbvfh7);
+ assign Lbvfh7 = (~(Pi5gh7 & Vi5gh7));
+ assign Vi5gh7 = (Bd9gh7 & Bj5gh7);
+ assign Vf5gh7 = (Rn4gh7 & J33gh7);
+ assign Rn4gh7 = (Hj5gh7 | Ng5gh7);
+ assign Ng5gh7 = (~(Nj5gh7 & Fb9gh7));
+ assign Nj5gh7 = (Nd5gh7 & Ta9gh7);
+ assign Nd5gh7 = (Tj5gh7 & Za9gh7);
+ assign Tj5gh7 = (Ft4gh7 & Rh5gh7);
+ assign Rh5gh7 = (~(Na9gh7 & Dc5gh7));
+ assign Dc5gh7 = (Zj5gh7 & Ta9gh7);
+ assign Zj5gh7 = (~(Rt4gh7 | Fb9gh7));
+ assign Ft4gh7 = (Zd8gh7 & N7vfh7);
+ assign N7vfh7 = (!Lb9gh7);
+ assign Hj5gh7 = (~(Na9gh7 & Rt4gh7));
+ assign Rt4gh7 = (!Rb9gh7);
+ assign Irrfh7 = (~(Vf3gh7 & P9vfh7));
+ assign P9vfh7 = (Vx3gh7 | Drxfh7);
+ assign Vf3gh7 = (X23gh7 | Vx3gh7);
+ assign Vx3gh7 = (~(D9vfh7 & Rezfh7));
+ assign D9vfh7 = (!Fk5gh7);
+ assign Zrrfh7 = (~(V9vfh7 & Lk5gh7));
+ assign Lk5gh7 = (V64gh7 | T19gh7);
+ assign V9vfh7 = (~(Rk5gh7 & Xk5gh7));
+ assign Rk5gh7 = (V0yfh7 & Dl5gh7);
+ assign Dl5gh7 = (~(Jl5gh7 & Zjxfh7));
+ assign V0yfh7 = (Pl5gh7 & Rezfh7);
+ assign Qsrfh7 = (~(Vl5gh7 & Bm5gh7));
+ assign Bm5gh7 = (V64gh7 | N19gh7);
+ assign Vl5gh7 = (V62gh7 | F85gh7);
+ assign Htrfh7 = (~(Hm5gh7 & Nm5gh7));
+ assign Nm5gh7 = (Fh4gh7 | Xz8gh7);
+ assign Hm5gh7 = (~(Dl2gh7 & Tm5gh7));
+ assign Ytrfh7 = (~(Zm5gh7 & Fn5gh7));
+ assign Fn5gh7 = (~(Ln5gh7 & Dl2gh7));
+ assign Ln5gh7 = (Fe8gh7 & Jl2gh7);
+ assign Jl2gh7 = (!Xn0gh7);
+ assign Zm5gh7 = (V64gh7 | V09gh7);
+ assign V64gh7 = (~(Rn5gh7 | Xn5gh7));
+ assign Purfh7 = (~(Do5gh7 & Jo5gh7));
+ assign Jo5gh7 = (Lw4gh7 | Rz8gh7);
+ assign Do5gh7 = (Xq0gh7 | Zj2gh7);
+ assign Gvrfh7 = (~(Po5gh7 & P34gh7));
+ assign P34gh7 = (Vo5gh7 & Bp5gh7);
+ assign Bp5gh7 = (~(Hp5gh7 & Fb5gh7));
+ assign Fb5gh7 = (Np5gh7 & Tp5gh7);
+ assign Tp5gh7 = (Zp5gh7 & R8vfh7);
+ assign Np5gh7 = (Fq5gh7 & com_rx_tdata[3]);
+ assign Fq5gh7 = (com_rx_tdata[1] & Hvxfh7);
+ assign Hvxfh7 = (Lq5gh7 & com_rx_tdata[4]);
+ assign Lq5gh7 = (~(V6vfh7 | com_rx_tdata[5]));
+ assign Hp5gh7 = (Rezfh7 & Rq5gh7);
+ assign Rq5gh7 = (!T4vfh7);
+ assign Vo5gh7 = (~(X5vfh7 & Xq5gh7));
+ assign Xq5gh7 = (!stdio_tx_tready);
+ assign X5vfh7 = (!F5vfh7);
+ assign F5vfh7 = (~(Dr5gh7 & Jr5gh7));
+ assign Dr5gh7 = (~(Pr5gh7 | Ba9gh7));
+ assign Po5gh7 = (Vr5gh7 & Bs5gh7);
+ assign Bs5gh7 = (Fh4gh7 | Hy8gh7);
+ assign Fh4gh7 = (~(Rn5gh7 | Hs5gh7));
+ assign Vr5gh7 = (~(Dl2gh7 & Ns5gh7));
+ assign Xvrfh7 = (~(Ts5gh7 & Zs5gh7));
+ assign Zs5gh7 = (~(Xn5gh7 & Ft5gh7));
+ assign Ts5gh7 = (~(Zs0gh7 & Dl2gh7));
+ assign Owrfh7 = (~(Lt5gh7 & Rt5gh7));
+ assign Rt5gh7 = (N44gh7 | By8gh7);
+ assign N44gh7 = (Lw4gh7 & Xt5gh7);
+ assign Xt5gh7 = (~(Zs0gh7 & Zj2gh7));
+ assign Lw4gh7 = (!Xn5gh7);
+ assign Xn5gh7 = (~(Du5gh7 & Ju5gh7));
+ assign Ju5gh7 = (Pu5gh7 & Vu5gh7);
+ assign Vu5gh7 = (By3gh7 & Bv5gh7);
+ assign By3gh7 = (~(Hv5gh7 & Nv5gh7));
+ assign Nv5gh7 = (~(Xw3gh7 & Do0gh7));
+ assign Do0gh7 = (~(Pi4gh7 & Tv5gh7));
+ assign Tv5gh7 = (~(Bj4gh7 | Z19gh7));
+ assign Pi4gh7 = (Zv5gh7 & B19gh7);
+ assign Xw3gh7 = (~(Ju4gh7 & Fw5gh7));
+ assign Fw5gh7 = (Tv8gh7 & Lw5gh7);
+ assign Ju4gh7 = (Rw5gh7 & Bv8gh7);
+ assign Hv5gh7 = (~(stdio_tx_tvalid & stdio_tx_tready));
+ assign Pu5gh7 = (Xw5gh7 & Dx5gh7);
+ assign Dx5gh7 = (~(Jx5gh7 & Zj2gh7));
+ assign Jx5gh7 = (~(Lb4gh7 & Xz3gh7));
+ assign Xz3gh7 = (!Ns5gh7);
+ assign Ns5gh7 = (~(Px5gh7 & Vx5gh7));
+ assign Vx5gh7 = (~(By5gh7 & Hy5gh7));
+ assign Hy5gh7 = (By8gh7 & Ft5gh7);
+ assign Px5gh7 = (~(Ny5gh7 & Ty5gh7));
+ assign Ny5gh7 = (~(Zy5gh7 | Vu8gh7));
+ assign Lb4gh7 = (!Tm5gh7);
+ assign Tm5gh7 = (~(Fz5gh7 & Lz5gh7));
+ assign Lz5gh7 = (~(Rz5gh7 & Xz5gh7));
+ assign Xz5gh7 = (D06gh7 & J06gh7);
+ assign D06gh7 = (~(P06gh7 | P09gh7));
+ assign P06gh7 = (!V06gh7);
+ assign Rz5gh7 = (B16gh7 & X29gh7);
+ assign Fz5gh7 = (~(H16gh7 & N16gh7));
+ assign H16gh7 = (~(T16gh7 | V09gh7));
+ assign Xw5gh7 = (Z16gh7 | Rezfh7);
+ assign Du5gh7 = (F26gh7 & L26gh7);
+ assign L26gh7 = (Xe3gh7 & Hd3gh7);
+ assign Hd3gh7 = (~(Vc3gh7 & R26gh7));
+ assign Vc3gh7 = (!Hm2gh7);
+ assign Hm2gh7 = (~(X26gh7 & Xq4gh7));
+ assign Xq4gh7 = (D36gh7 & Ty5gh7);
+ assign D36gh7 = (Vu8gh7 & Pu8gh7);
+ assign X26gh7 = (Du8gh7 & Dr4gh7);
+ assign Xe3gh7 = (J36gh7 & Bm2gh7);
+ assign Bm2gh7 = (~(R26gh7 & Zp4gh7));
+ assign Zp4gh7 = (Ha4gh7 | Ba4gh7);
+ assign Ba4gh7 = (P36gh7 & V36gh7);
+ assign V36gh7 = (B46gh7 & Du8gh7);
+ assign B46gh7 = (~(Dr4gh7 | Pu8gh7));
+ assign Dr4gh7 = (!Ju8gh7);
+ assign P36gh7 = (Ty5gh7 & Vu8gh7);
+ assign Ty5gh7 = (H46gh7 & N46gh7);
+ assign N46gh7 = (T46gh7 & Lt8gh7);
+ assign T46gh7 = (Rt8gh7 & Xt8gh7);
+ assign Ha4gh7 = (Z46gh7 & F56gh7);
+ assign Z46gh7 = (~(L56gh7 | Zv8gh7));
+ assign L56gh7 = (!R56gh7);
+ assign J36gh7 = (~(R26gh7 & X56gh7));
+ assign X56gh7 = (~(Na4gh7 & Zy1gh7));
+ assign Zy1gh7 = (~(D66gh7 & Jr5gh7));
+ assign Jr5gh7 = (J66gh7 & P66gh7);
+ assign P66gh7 = (V66gh7 & T19gh7);
+ assign V66gh7 = (V99gh7 & Bd9gh7);
+ assign J66gh7 = (B76gh7 & N16gh7);
+ assign B76gh7 = (~(H76gh7 | N76gh7));
+ assign D66gh7 = (Ba9gh7 & Pr5gh7);
+ assign Pr5gh7 = (!H19gh7);
+ assign Na4gh7 = (~(T76gh7 & Z76gh7));
+ assign Z76gh7 = (~(Bj4gh7 | B19gh7));
+ assign Bj4gh7 = (!Ha9gh7);
+ assign T76gh7 = (Zv5gh7 & Z19gh7);
+ assign Zv5gh7 = (F86gh7 & L86gh7);
+ assign L86gh7 = (R86gh7 & F29gh7);
+ assign R86gh7 = (~(H76gh7 | T16gh7));
+ assign H76gh7 = (!V09gh7);
+ assign R26gh7 = (!Vi0gh7);
+ assign F26gh7 = (~(X86gh7 | Hs5gh7));
+ assign Hs5gh7 = (~(D96gh7 & J96gh7));
+ assign J96gh7 = (~(P96gh7 & F85gh7));
+ assign P96gh7 = (~(V96gh7 & Ba6gh7));
+ assign Ba6gh7 = (Ha6gh7 | stdio_rx_tvalid);
+ assign V96gh7 = (V62gh7 | com_tx_tready);
+ assign D96gh7 = (~(Na6gh7 & Zj2gh7));
+ assign Na6gh7 = (~(Ta6gh7 & Za6gh7));
+ assign Ta6gh7 = (Fe4gh7 & Xn0gh7);
+ assign Xn0gh7 = (~(Fb6gh7 & Lb6gh7));
+ assign Lb6gh7 = (Rb6gh7 & Lz8gh7);
+ assign Rb6gh7 = (~(Xb6gh7 | Rz8gh7));
+ assign Lt5gh7 = (Zp1gh7 | Zj2gh7);
+ assign Zp1gh7 = (!Pr0gh7);
+ assign Fxrfh7 = (!Dc6gh7);
+ assign Dc6gh7 = (Dl2gh7 ? Le4gh7 : Jc6gh7);
+ assign Jc6gh7 = (Df4gh7 | Pc9gh7);
+ assign Wxrfh7 = (Zj2gh7 ? Hp0gh7 : By0gh7);
+ assign Hp0gh7 = (!Le4gh7);
+ assign Le4gh7 = (~(Pc6gh7 & Vc6gh7));
+ assign Vc6gh7 = (Bd6gh7 & Fz8gh7);
+ assign Bd6gh7 = (~(Hd6gh7 | Ty8gh7));
+ assign Pc6gh7 = (Nd6gh7 & Td6gh7);
+ assign By0gh7 = (!Re4gh7);
+ assign Nyrfh7 = (~(Zd6gh7 & Fe6gh7));
+ assign Fe6gh7 = (~(D64gh7 & Le6gh7));
+ assign D64gh7 = (~(F54gh7 & Bv5gh7));
+ assign F54gh7 = (~(Rn5gh7 | X86gh7));
+ assign X86gh7 = (~(Re6gh7 & Xe6gh7));
+ assign Xe6gh7 = (Tv3gh7 | Dl2gh7);
+ assign Tv3gh7 = (~(Df6gh7 & Jf6gh7));
+ assign Jf6gh7 = (~(Pf6gh7 & Vf6gh7));
+ assign Vf6gh7 = (~(Bg6gh7 & Hg6gh7));
+ assign Hg6gh7 = (~(Ng6gh7 | J09gh7));
+ assign Bg6gh7 = (J06gh7 & D09gh7);
+ assign Pf6gh7 = (~(Tg6gh7 & V06gh7));
+ assign Tg6gh7 = (~(Zg6gh7 | F29gh7));
+ assign Re6gh7 = (Fh6gh7 & Lh6gh7);
+ assign Lh6gh7 = (~(Rh6gh7 & Jl5gh7));
+ assign Jl5gh7 = (Xh6gh7 & Di6gh7);
+ assign Di6gh7 = (!Ji6gh7);
+ assign Ji6gh7 = (com_rx_tdata[5] ? Vi6gh7 : Pi6gh7);
+ assign Vi6gh7 = (~(V6vfh7 & Bsxfh7));
+ assign Pi6gh7 = (~(com_rx_tdata[3] & com_rx_tdata[0]));
+ assign Rh6gh7 = (Xk5gh7 & Zjxfh7);
+ assign Xk5gh7 = (!Drxfh7);
+ assign Fh6gh7 = (~(Pl5gh7 & Xexfh7));
+ assign Xexfh7 = (!X23gh7);
+ assign Rn5gh7 = (~(Bj6gh7 & Hj6gh7));
+ assign Hj6gh7 = (~(Nj6gh7 & Zj2gh7));
+ assign Nj6gh7 = (~(Tj6gh7 & Df4gh7));
+ assign Df4gh7 = (Zj6gh7 & L81gh7);
+ assign L81gh7 = (~(Fk6gh7 & B16gh7));
+ assign Fk6gh7 = (~(Lk6gh7 | X29gh7));
+ assign Lk6gh7 = (!Rk6gh7);
+ assign Zj6gh7 = (~(Pr0gh7 | Zs0gh7));
+ assign Zs0gh7 = (!Dr1gh7);
+ assign Dr1gh7 = (~(By5gh7 & Xk6gh7));
+ assign Xk6gh7 = (~(Ft5gh7 | By8gh7));
+ assign Ft5gh7 = (!Jx8gh7);
+ assign By5gh7 = (Dl6gh7 & Jl6gh7);
+ assign Pr0gh7 = (Pl6gh7 & Vl6gh7);
+ assign Vl6gh7 = (~(Bm6gh7 | Pc9gh7));
+ assign Tj6gh7 = (Xq0gh7 & Re4gh7);
+ assign Re4gh7 = (~(Hm6gh7 & Nm6gh7));
+ assign Hm6gh7 = (~(Hd6gh7 | Fz8gh7));
+ assign Xq0gh7 = (~(Pl6gh7 & Tm6gh7));
+ assign Tm6gh7 = (Pc9gh7 & Bm6gh7);
+ assign Bm6gh7 = (!Hy8gh7);
+ assign Pl6gh7 = (Dl6gh7 & Zm6gh7);
+ assign Dl6gh7 = (Fn6gh7 & Ln6gh7);
+ assign Fn6gh7 = (D09gh7 & Rn6gh7);
+ assign Bj6gh7 = (~(Pc3gh7 & Rw4gh7));
+ assign Pc3gh7 = (~(Xn6gh7 & Vx4gh7));
+ assign Xn6gh7 = (Dl0gh7 & Fbvfh7);
+ assign Zd6gh7 = (~(Lz0gh7 & Dl2gh7));
+ assign Ezrfh7 = (!Do6gh7);
+ assign Do6gh7 = (Dl2gh7 ? Bg2gh7 : Jo6gh7);
+ assign Jo6gh7 = (~(Pf4gh7 & Po6gh7));
+ assign Vzrfh7 = (!Vo6gh7);
+ assign Vo6gh7 = (Dl2gh7 ? Hp6gh7 : Bp6gh7);
+ assign Bp6gh7 = (~(Jf4gh7 & Np6gh7));
+ assign M0sfh7 = (!Tp6gh7);
+ assign Tp6gh7 = (Dl2gh7 ? Hd2gh7 : Zp6gh7);
+ assign Zp6gh7 = (~(Pf4gh7 & Fq6gh7));
+ assign Pf4gh7 = (Fw0gh7 | Lz0gh7);
+ assign Lz0gh7 = (Lq6gh7 & Rq6gh7);
+ assign Rq6gh7 = (Zy8gh7 & Po6gh7);
+ assign Po6gh7 = (!Ny8gh7);
+ assign Fw0gh7 = (!Hp6gh7);
+ assign Hp6gh7 = (~(Xq6gh7 & Dr6gh7));
+ assign Dr6gh7 = (Jr6gh7 & Fq6gh7);
+ assign Fq6gh7 = (!Vx8gh7);
+ assign D1sfh7 = (!Pr6gh7);
+ assign Pr6gh7 = (Dl2gh7 ? Hp1gh7 : Vr6gh7);
+ assign Vr6gh7 = (~(Bs6gh7 & Hs6gh7));
+ assign U1sfh7 = (!Ns6gh7);
+ assign Ns6gh7 = (Dl2gh7 ? Fz1gh7 : Ts6gh7);
+ assign Ts6gh7 = (~(Jf4gh7 & Zs6gh7));
+ assign Jf4gh7 = (Bs6gh7 | Ft6gh7);
+ assign Ft6gh7 = (!Hp1gh7);
+ assign Hp1gh7 = (~(Lt6gh7 & Rt6gh7));
+ assign Rt6gh7 = (Xt8gh7 & Zs6gh7);
+ assign Zs6gh7 = (!Rt8gh7);
+ assign Bs6gh7 = (~(Hd2gh7 & Bg2gh7));
+ assign Bg2gh7 = (~(Lq6gh7 & Xt6gh7));
+ assign Xt6gh7 = (Ny8gh7 & Np6gh7);
+ assign Np6gh7 = (!Zy8gh7);
+ assign Lq6gh7 = (Nm6gh7 & Fz8gh7);
+ assign Nm6gh7 = (Xq6gh7 & Du6gh7);
+ assign Du6gh7 = (Vx8gh7 & Ty8gh7);
+ assign Xq6gh7 = (Td6gh7 & Px8gh7);
+ assign Hd2gh7 = (~(Ju6gh7 & Pu6gh7));
+ assign Pu6gh7 = (Jr6gh7 & Hs6gh7);
+ assign Hs6gh7 = (!Px8gh7);
+ assign Ju6gh7 = (Td6gh7 & Vx8gh7);
+ assign Td6gh7 = (Vu6gh7 & Bv6gh7);
+ assign Bv6gh7 = (Hv6gh7 & Zm6gh7);
+ assign Hv6gh7 = (Nv6gh7 & Tv6gh7);
+ assign L2sfh7 = (~(Zv6gh7 & J62gh7));
+ assign J62gh7 = (~(Pi5gh7 & Fw6gh7));
+ assign Fw6gh7 = (~(Bj5gh7 | Bd9gh7));
+ assign Bj5gh7 = (!V99gh7);
+ assign Pi5gh7 = (Lw6gh7 & T19gh7);
+ assign Zv6gh7 = (Dl2gh7 ? Fe4gh7 : Rw6gh7);
+ assign Fe4gh7 = (~(Xw6gh7 & Dx6gh7));
+ assign Xw6gh7 = (Rw8gh7 & Jx6gh7);
+ assign Jx6gh7 = (!Lw8gh7);
+ assign Rw6gh7 = (Za6gh7 | Lt8gh7);
+ assign Za6gh7 = (Rb4gh7 & Fz1gh7);
+ assign Fz1gh7 = (~(Px6gh7 & Vx6gh7));
+ assign Vx6gh7 = (~(By6gh7 | Lt8gh7));
+ assign Px6gh7 = (Hy6gh7 & Rt8gh7);
+ assign C3sfh7 = (Ny6gh7 & Zv4gh7);
+ assign Zv4gh7 = (Ty6gh7 & Zy6gh7);
+ assign Zy6gh7 = (Fz6gh7 & Lz6gh7);
+ assign Lz6gh7 = (Rz6gh7 & Xz6gh7);
+ assign Xz6gh7 = (D07gh7 & J07gh7);
+ assign J07gh7 = (P07gh7 & V07gh7);
+ assign V07gh7 = (~(Pxvfh7 ^ B17gh7));
+ assign B17gh7 = (~(Ns8gh7 | Jrtfh7));
+ assign Pxvfh7 = (!Hs8gh7);
+ assign P07gh7 = (~(Xhwfh7 ^ H17gh7));
+ assign H17gh7 = (~(Pr8gh7 | Nptfh7));
+ assign Xhwfh7 = (!Jr8gh7);
+ assign D07gh7 = (N17gh7 & T17gh7);
+ assign T17gh7 = (~(T1xfh7 ^ Z17gh7));
+ assign Z17gh7 = (~(Rq8gh7 | Rntfh7));
+ assign T1xfh7 = (!Lq8gh7);
+ assign N17gh7 = (Np8gh7 ^ F27gh7);
+ assign F27gh7 = (~(Tp8gh7 | Vltfh7));
+ assign Rz6gh7 = (L27gh7 & R27gh7);
+ assign R27gh7 = (X27gh7 & D37gh7);
+ assign D37gh7 = (~(Zmwfh7 ^ J37gh7));
+ assign J37gh7 = (~(Vo8gh7 | Bptfh7));
+ assign Zmwfh7 = (!Po8gh7);
+ assign X27gh7 = (~(Nsvfh7 ^ P37gh7));
+ assign P37gh7 = (~(Xn8gh7 | Vrtfh7));
+ assign Nsvfh7 = (!Rn8gh7);
+ assign L27gh7 = (V37gh7 & B47gh7);
+ assign B47gh7 = (~(J6xfh7 ^ H47gh7));
+ assign H47gh7 = (~(Zm8gh7 | Fntfh7));
+ assign J6xfh7 = (!Tm8gh7);
+ assign V37gh7 = (~(Fhxfh7 ^ N47gh7));
+ assign N47gh7 = (~(Bm8gh7 | Hmtfh7));
+ assign Fhxfh7 = (!Vl8gh7);
+ assign Fz6gh7 = (T47gh7 & Z47gh7);
+ assign Z47gh7 = (F57gh7 & L57gh7);
+ assign L57gh7 = (R57gh7 & X57gh7);
+ assign X57gh7 = (~(Tpvfh7 ^ D67gh7));
+ assign D67gh7 = (~(Dl8gh7 | Bstfh7));
+ assign Tpvfh7 = (!Xk8gh7);
+ assign R57gh7 = (~(D0wfh7 ^ J67gh7));
+ assign J67gh7 = (~(Fk8gh7 | Drtfh7));
+ assign D0wfh7 = (!Zj8gh7);
+ assign F57gh7 = (P67gh7 & V67gh7);
+ assign V67gh7 = (~(Hawfh7 ^ B77gh7));
+ assign B77gh7 = (~(Hj8gh7 | Fqtfh7));
+ assign Hawfh7 = (!Bj8gh7);
+ assign P67gh7 = (~(Lkwfh7 ^ H77gh7));
+ assign H77gh7 = (~(Ji8gh7 | Hptfh7));
+ assign Lkwfh7 = (!Di8gh7);
+ assign T47gh7 = (N77gh7 & T77gh7);
+ assign T77gh7 = (Z77gh7 & F87gh7);
+ assign F87gh7 = (~(Puwfh7 ^ L87gh7));
+ assign L87gh7 = (~(Lh8gh7 | Jotfh7));
+ assign Puwfh7 = (!Fh8gh7);
+ assign Z77gh7 = (~(B4xfh7 ^ R87gh7));
+ assign R87gh7 = (~(Ng8gh7 | Lntfh7));
+ assign B4xfh7 = (!Hg8gh7);
+ assign N77gh7 = (X87gh7 & D97gh7);
+ assign D97gh7 = (~(Hdxfh7 ^ J97gh7));
+ assign J97gh7 = (~(Pf8gh7 | Nmtfh7));
+ assign Hdxfh7 = (!Jf8gh7);
+ assign X87gh7 = (~(Tpxfh7 ^ P97gh7));
+ assign P97gh7 = (~(Re8gh7 | Pltfh7));
+ assign Tpxfh7 = (!Le8gh7);
+ assign Ty6gh7 = (V97gh7 & Ba7gh7);
+ assign Ba7gh7 = (Ha7gh7 & Na7gh7);
+ assign Na7gh7 = (Ta7gh7 & Za7gh7);
+ assign Za7gh7 = (Fb7gh7 & Lb7gh7);
+ assign Lb7gh7 = (~(Bswfh7 ^ Rb7gh7));
+ assign Rb7gh7 = (~(Dr8gh7 | Potfh7));
+ assign Bswfh7 = (!Xq8gh7);
+ assign Fb7gh7 = (~(Vcwfh7 ^ Xb7gh7));
+ assign Xb7gh7 = (~(Ln8gh7 | Zptfh7));
+ assign Vcwfh7 = (!Fn8gh7);
+ assign Ta7gh7 = (Dc7gh7 & Jc7gh7);
+ assign Jc7gh7 = (~(Zgvfh7 ^ Pc7gh7));
+ assign Pc7gh7 = (~(Hp8gh7 | Jltfh7));
+ assign Zgvfh7 = (!Bp8gh7);
+ assign Dc7gh7 = (~(F5wfh7 ^ Vc7gh7));
+ assign Vc7gh7 = (~(Tj8gh7 | Rqtfh7));
+ assign F5wfh7 = (!Nj8gh7);
+ assign Ha7gh7 = (Bd7gh7 & Hd7gh7);
+ assign Hd7gh7 = (Nd7gh7 & Td7gh7);
+ assign Td7gh7 = (~(R8xfh7 ^ Zd7gh7));
+ assign Zd7gh7 = (~(Bg8gh7 | Zmtfh7));
+ assign R8xfh7 = (!Vf8gh7);
+ assign Nd7gh7 = (~(Npwfh7 ^ Fe7gh7));
+ assign Fe7gh7 = (~(Xh8gh7 | Votfh7));
+ assign Npwfh7 = (!Rh8gh7);
+ assign Bd7gh7 = (Le7gh7 & Re7gh7);
+ assign Re7gh7 = (~(Pfvfh7 ^ Xe7gh7));
+ assign Xe7gh7 = (~(Pl8gh7 | Nstfh7));
+ assign Pfvfh7 = (!Jl8gh7);
+ assign Le7gh7 = (~(Zmvfh7 ^ Df7gh7));
+ assign Df7gh7 = (~(Zs8gh7 | Hstfh7));
+ assign Zmvfh7 = (!Ts8gh7);
+ assign V97gh7 = (Jf7gh7 & Pf7gh7);
+ assign Pf7gh7 = (Vf7gh7 & Bg7gh7);
+ assign Bg7gh7 = (Hg7gh7 & Ng7gh7);
+ assign Ng7gh7 = (~(T7wfh7 ^ Tg7gh7));
+ assign Tg7gh7 = (~(Bs8gh7 | Lqtfh7));
+ assign T7wfh7 = (!Vr8gh7);
+ assign Hg7gh7 = (~(Zaxfh7 ^ Zg7gh7));
+ assign Zg7gh7 = (~(Fq8gh7 | Tmtfh7));
+ assign Zaxfh7 = (!Zp8gh7);
+ assign Vf7gh7 = (Fh7gh7 & Lh7gh7);
+ assign Lh7gh7 = (~(R2wfh7 ^ Rh7gh7));
+ assign Rh7gh7 = (~(Jo8gh7 | Xqtfh7));
+ assign R2wfh7 = (!Do8gh7);
+ assign Fh7gh7 = (~(Dxwfh7 ^ Xh7gh7));
+ assign Xh7gh7 = (~(Nm8gh7 | Dotfh7));
+ assign Dxwfh7 = (!Hm8gh7);
+ assign Jf7gh7 = (Di7gh7 & Ji7gh7);
+ assign Ji7gh7 = (Pi7gh7 & Vi7gh7);
+ assign Vi7gh7 = (~(Bvvfh7 ^ Bj7gh7));
+ assign Bj7gh7 = (~(Rk8gh7 | Prtfh7));
+ assign Bvvfh7 = (!Lk8gh7);
+ assign Pi7gh7 = (~(Jfwfh7 ^ Hj7gh7));
+ assign Hj7gh7 = (~(Vi8gh7 | Tptfh7));
+ assign Jfwfh7 = (!Pi8gh7);
+ assign Di7gh7 = (Nj7gh7 & Tj7gh7);
+ assign Tj7gh7 = (~(Lzwfh7 ^ Zj7gh7));
+ assign Zj7gh7 = (~(Zg8gh7 | Xntfh7));
+ assign Lzwfh7 = (!Tg8gh7);
+ assign Nj7gh7 = (~(Jixfh7 ^ Fk7gh7));
+ assign Fk7gh7 = (~(Df8gh7 | Bmtfh7));
+ assign Jixfh7 = (!Xe8gh7);
+ assign Ny6gh7 = (Fq4gh7 & Ty4gh7);
+ assign Fq4gh7 = (!Dx3gh7);
+ assign Dx3gh7 = (~(Lk7gh7 & Dx6gh7));
+ assign Dx6gh7 = (Rk7gh7 & Fk4gh7);
+ assign Rk7gh7 = (Xb9gh7 & Fw8gh7);
+ assign Lk7gh7 = (Lw8gh7 & Zj4gh7);
+ assign Zj4gh7 = (!Rw8gh7);
+ assign T3sfh7 = (~(Xk7gh7 & Dl7gh7));
+ assign Dl7gh7 = (Jl7gh7 & Pl7gh7);
+ assign Pl7gh7 = (~(Pl5gh7 & Ta4gh7));
+ assign Ta4gh7 = (!Vl7gh7);
+ assign Pl5gh7 = (Fk5gh7 & J33gh7);
+ assign J33gh7 = (~(Bm7gh7 & Hm7gh7));
+ assign Hm7gh7 = (J9vfh7 & Bsxfh7);
+ assign Bsxfh7 = (!com_rx_tdata[3]);
+ assign Bm7gh7 = (Xh6gh7 & Nyxfh7);
+ assign Nyxfh7 = (~(com_rx_tdata[5] | com_rx_tdata[0]));
+ assign Fk5gh7 = (~(Nm7gh7 & Tm7gh7));
+ assign Tm7gh7 = (Zm7gh7 & Fn7gh7);
+ assign Fn7gh7 = (~(com_rx_tdata[2] & V6vfh7));
+ assign V6vfh7 = (!com_rx_tdata[0]);
+ assign Zm7gh7 = (~(Ftxfh7 | com_rx_tdata[5]));
+ assign Ftxfh7 = (com_rx_tdata[1] & com_rx_tdata[0]);
+ assign Nm7gh7 = (Nvxfh7 & Xh6gh7);
+ assign Xh6gh7 = (Zp5gh7 & Z7vfh7);
+ assign Z7vfh7 = (!com_rx_tdata[4]);
+ assign Zp5gh7 = (~(com_rx_tdata[6] | com_rx_tdata[7]));
+ assign Nvxfh7 = (com_rx_tdata[3] & Bjvfh7);
+ assign Bjvfh7 = (!Zjxfh7);
+ assign Zjxfh7 = (J9vfh7 & R8vfh7);
+ assign R8vfh7 = (!com_rx_tdata[2]);
+ assign J9vfh7 = (!com_rx_tdata[1]);
+ assign Jl7gh7 = (Fw3gh7 & Dl0gh7);
+ assign Dl0gh7 = (~(Ln7gh7 & Hv8gh7));
+ assign Ln7gh7 = (~(Rn7gh7 | Nv8gh7));
+ assign Fw3gh7 = (~(Xn7gh7 & Do7gh7));
+ assign Do7gh7 = (~(Lw5gh7 | Bv8gh7));
+ assign Lw5gh7 = (!L29gh7);
+ assign Xn7gh7 = (Rw5gh7 & Tv8gh7);
+ assign Rw5gh7 = (Jo7gh7 & Po7gh7);
+ assign Po7gh7 = (Vo7gh7 & Bp7gh7);
+ assign Xk7gh7 = (Hp7gh7 & Vx4gh7);
+ assign Vx4gh7 = (Xw4gh7 & Dx4gh7);
+ assign Dx4gh7 = (~(Np7gh7 & Ln6gh7));
+ assign Np7gh7 = (~(Ng6gh7 | D09gh7));
+ assign Xw4gh7 = (~(Tp7gh7 & Zp7gh7));
+ assign Zp7gh7 = (Dx8gh7 & Fq7gh7);
+ assign Hp7gh7 = (Lq7gh7 & Rq7gh7);
+ assign Rq7gh7 = (~(Xq7gh7 & Rw4gh7));
+ assign Rw4gh7 = (!Rezfh7);
+ assign Rezfh7 = (com_rx_tvalid & com_rx_tready);
+ assign Xq7gh7 = (~(Z16gh7 & Fbvfh7));
+ assign Fbvfh7 = (~(Tp7gh7 & Dr7gh7));
+ assign Dr7gh7 = (~(Fq7gh7 | Dx8gh7));
+ assign Fq7gh7 = (!Xw8gh7);
+ assign Tp7gh7 = (F56gh7 & Zv8gh7);
+ assign F56gh7 = (Jr7gh7 & Pr7gh7);
+ assign Pr7gh7 = (Xb9gh7 & Vr7gh7);
+ assign Z16gh7 = (Vl7gh7 & T4vfh7);
+ assign T4vfh7 = (~(Bs7gh7 & Nv8gh7));
+ assign Bs7gh7 = (~(Rn7gh7 | Hv8gh7));
+ assign Rn7gh7 = (~(Hs7gh7 & Ft8gh7));
+ assign Hs7gh7 = (Bp7gh7 & Ns7gh7);
+ assign Vl7gh7 = (Drxfh7 & X23gh7);
+ assign X23gh7 = (~(Ts7gh7 & Zs7gh7));
+ assign Zs7gh7 = (Bd9gh7 & Ft7gh7);
+ assign Ts7gh7 = (Lw6gh7 & V99gh7);
+ assign Lw6gh7 = (~(Lt7gh7 | N76gh7));
+ assign Drxfh7 = (~(Rt7gh7 & Xt7gh7));
+ assign Xt7gh7 = (Du7gh7 & V99gh7);
+ assign Du7gh7 = (Bd9gh7 & N76gh7);
+ assign N76gh7 = (!N19gh7);
+ assign Rt7gh7 = (~(Lt7gh7 | Ft7gh7));
+ assign Ft7gh7 = (!T19gh7);
+ assign Lt7gh7 = (~(Ju7gh7 & Pu7gh7));
+ assign Pu7gh7 = (H19gh7 & Ba9gh7);
+ assign Ju7gh7 = (N16gh7 & V09gh7);
+ assign N16gh7 = (F86gh7 & Vu7gh7);
+ assign Vu7gh7 = (~(Bv7gh7 | Hv7gh7));
+ assign F86gh7 = (Df6gh7 & V06gh7);
+ assign Lq7gh7 = (F85gh7 | Ha6gh7);
+ assign Ha6gh7 = (Zv3gh7 & V62gh7);
+ assign V62gh7 = (~(Fb6gh7 & Nv7gh7));
+ assign Nv7gh7 = (Tv7gh7 & Lz8gh7);
+ assign Tv7gh7 = (Rz8gh7 & Xb6gh7);
+ assign K4sfh7 = (~(Zv7gh7 & R54gh7));
+ assign R54gh7 = (Rb4gh7 | Zj2gh7);
+ assign Zj2gh7 = (!Dl2gh7);
+ assign Dl2gh7 = (com_tx_tready & com_tx_tvalid);
+ assign Rb4gh7 = (~(Lt6gh7 & Fw7gh7));
+ assign Fw7gh7 = (Rt8gh7 & By6gh7);
+ assign By6gh7 = (!Xt8gh7);
+ assign Lt6gh7 = (Hy6gh7 & Lt8gh7);
+ assign Hy6gh7 = (H46gh7 & Lw7gh7);
+ assign H46gh7 = (Rw7gh7 & Ft8gh7);
+ assign Zv7gh7 = (Bv5gh7 & V65gh7);
+ assign V65gh7 = (Xw7gh7 | Zv3gh7);
+ assign Zv3gh7 = (~(Fb6gh7 & Dx7gh7));
+ assign Dx7gh7 = (Jx7gh7 & Rz8gh7);
+ assign Jx7gh7 = (~(Xb6gh7 | Lz8gh7));
+ assign Xb6gh7 = (!Xz8gh7);
+ assign Fb6gh7 = (Px7gh7 & Nv6gh7);
+ assign Xw7gh7 = (~(stdio_rx_tvalid & F85gh7));
+ assign F85gh7 = (!com_rx_tvalid);
+ assign Bv5gh7 = (D34gh7 | J34gh7);
+ assign J34gh7 = (~(P65gh7 | L54gh7));
+ assign L54gh7 = (Vx7gh7 & Fk4gh7);
+ assign Fk4gh7 = (Jr7gh7 & By7gh7);
+ assign By7gh7 = (Zv8gh7 & R56gh7);
+ assign Jr7gh7 = (Px7gh7 & Tv6gh7);
+ assign Px7gh7 = (Vu6gh7 & Hy7gh7);
+ assign Hy7gh7 = (Ny7gh7 & Ty7gh7);
+ assign Ty7gh7 = (Vx8gh7 & Jr6gh7);
+ assign Ny7gh7 = (Zm6gh7 & Px8gh7);
+ assign Vu6gh7 = (Zy7gh7 & Ln6gh7);
+ assign Ln6gh7 = (Fz7gh7 & Df6gh7);
+ assign Df6gh7 = (Lz7gh7 & B16gh7);
+ assign B16gh7 = (Jo7gh7 & Rz7gh7);
+ assign Rz7gh7 = (Xz7gh7 & D08gh7);
+ assign D08gh7 = (Tv8gh7 & L29gh7);
+ assign Xz7gh7 = (Bp7gh7 & Bv8gh7);
+ assign Bp7gh7 = (!J08gh7);
+ assign Jo7gh7 = (P08gh7 & Hv8gh7);
+ assign P08gh7 = (Nv8gh7 & Ft8gh7);
+ assign Lz7gh7 = (X29gh7 & P09gh7);
+ assign Fz7gh7 = (J06gh7 & J09gh7);
+ assign Zy7gh7 = (D09gh7 & Jl6gh7);
+ assign Vx7gh7 = (Vr7gh7 & J64gh7);
+ assign J64gh7 = (!Xb9gh7);
+ assign P65gh7 = (V08gh7 & Rw7gh7);
+ assign Rw7gh7 = (B18gh7 & Hv8gh7);
+ assign B18gh7 = (Nv8gh7 & Ns7gh7);
+ assign Ns7gh7 = (H18gh7 & N18gh7);
+ assign N18gh7 = (Vo7gh7 & L29gh7);
+ assign Vo7gh7 = (X29gh7 & Rk6gh7);
+ assign Rk6gh7 = (T18gh7 & P09gh7);
+ assign T18gh7 = (J06gh7 & V06gh7);
+ assign V06gh7 = (Z18gh7 & D09gh7);
+ assign Z18gh7 = (J09gh7 & F28gh7);
+ assign F28gh7 = (!Ng6gh7);
+ assign Ng6gh7 = (~(L28gh7 & Rn6gh7));
+ assign Rn6gh7 = (Nd6gh7 & R28gh7);
+ assign R28gh7 = (X28gh7 & Nv6gh7);
+ assign Nv6gh7 = (D38gh7 & J38gh7);
+ assign J38gh7 = (Vr7gh7 & R56gh7);
+ assign R56gh7 = (Xw8gh7 & Dx8gh7);
+ assign Vr7gh7 = (P38gh7 & Fw8gh7);
+ assign P38gh7 = (Lw8gh7 & Rw8gh7);
+ assign D38gh7 = (Zv8gh7 & Xb9gh7);
+ assign X28gh7 = (Tv6gh7 & Jr6gh7);
+ assign Jr6gh7 = (V38gh7 & Ty8gh7);
+ assign V38gh7 = (~(Le6gh7 | Hd6gh7));
+ assign Hd6gh7 = (~(Ny8gh7 & Zy8gh7));
+ assign Le6gh7 = (!Fz8gh7);
+ assign Tv6gh7 = (B48gh7 & Lz8gh7);
+ assign B48gh7 = (Rz8gh7 & Xz8gh7);
+ assign Nd6gh7 = (Px8gh7 & Vx8gh7);
+ assign L28gh7 = (Jl6gh7 & Zm6gh7);
+ assign Zm6gh7 = (Jx8gh7 & By8gh7);
+ assign Jl6gh7 = (Hy8gh7 & Pc9gh7);
+ assign J06gh7 = (~(Bv7gh7 | Zg6gh7));
+ assign Zg6gh7 = (~(H48gh7 & V09gh7));
+ assign H48gh7 = (~(T16gh7 | Hv7gh7));
+ assign Hv7gh7 = (~(N48gh7 & B19gh7));
+ assign N48gh7 = (Z19gh7 & Ha9gh7);
+ assign T16gh7 = (~(T48gh7 & Z48gh7));
+ assign Z48gh7 = (F58gh7 & V99gh7);
+ assign F58gh7 = (Ba9gh7 & Bd9gh7);
+ assign T48gh7 = (L58gh7 & H19gh7);
+ assign L58gh7 = (N19gh7 & T19gh7);
+ assign Bv7gh7 = (!F29gh7);
+ assign H18gh7 = (Bv8gh7 & Tv8gh7);
+ assign V08gh7 = (~(J08gh7 | Ft8gh7));
+ assign J08gh7 = (~(R58gh7 & X58gh7));
+ assign X58gh7 = (Lw7gh7 & Xt8gh7);
+ assign Lw7gh7 = (Vu8gh7 & D68gh7);
+ assign D68gh7 = (!Zy5gh7);
+ assign Zy5gh7 = (~(J68gh7 & Du8gh7));
+ assign J68gh7 = (Ju8gh7 & Pu8gh7);
+ assign R58gh7 = (Lt8gh7 & Rt8gh7);
+ assign D34gh7 = (stdio_rx_tready & stdio_rx_tvalid);
+ assign Tosfh7 = (P68gh7 & Vi0gh7);
+ assign P68gh7 = (V68gh7 & Patfh7);
+ assign V68gh7 = (~(Bsufh7 & Tp4gh7));
+ assign Tp4gh7 = (!Ty4gh7);
+ assign Ty4gh7 = (~(B78gh7 & H78gh7));
+ assign H78gh7 = (N78gh7 & T78gh7);
+ assign T78gh7 = (Z78gh7 & F88gh7);
+ assign F88gh7 = (L88gh7 & R88gh7);
+ assign R88gh7 = (Jctfh7 & Dctfh7);
+ assign L88gh7 = (Vctfh7 & Pctfh7);
+ assign Z78gh7 = (X88gh7 & D98gh7);
+ assign D98gh7 = (Hdtfh7 & Bdtfh7);
+ assign X88gh7 = (Tdtfh7 & Ndtfh7);
+ assign N78gh7 = (J98gh7 & P98gh7);
+ assign P98gh7 = (V98gh7 & Ba8gh7);
+ assign Ba8gh7 = (Fetfh7 & Zdtfh7);
+ assign V98gh7 = (Retfh7 & Letfh7);
+ assign J98gh7 = (Ha8gh7 & Na8gh7);
+ assign Na8gh7 = (Dftfh7 & Xetfh7);
+ assign Ha8gh7 = (Pftfh7 & Jftfh7);
+ assign B78gh7 = (Ta8gh7 & Za8gh7);
+ assign Za8gh7 = (Fb8gh7 & Lb8gh7);
+ assign Lb8gh7 = (Rb8gh7 & Xb8gh7);
+ assign Xb8gh7 = (Bgtfh7 & Vftfh7);
+ assign Rb8gh7 = (Ngtfh7 & Hgtfh7);
+ assign Fb8gh7 = (Dc8gh7 & Jc8gh7);
+ assign Jc8gh7 = (Zgtfh7 & Tgtfh7);
+ assign Dc8gh7 = (Lhtfh7 & Fhtfh7);
+ assign Ta8gh7 = (Pc8gh7 & Vc8gh7);
+ assign Vc8gh7 = (Bd8gh7 & Hd8gh7);
+ assign Hd8gh7 = (Xhtfh7 & Rhtfh7);
+ assign Bd8gh7 = (Jitfh7 & Ditfh7);
+ assign Pc8gh7 = (Nd8gh7 & Ybtfh7);
+ assign Nd8gh7 = (Tbtfh7 & Obtfh7);
+ assign B9tfh7 = (Vi0gh7 & R9tfh7);
+ assign Vi0gh7 = (Td8gh7 & ahb_hready);
+ assign Td8gh7 = (~(Hd9gh7 | R29gh7));
+
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ie9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ie9gh7 <= Dltfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ If9gh7 <= 1'b0;
+ end
+ else
+ begin
+ If9gh7 <= T1ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ng9gh7 <= 1'b1;
+ end
+ else
+ begin
+ Ng9gh7 <= C3sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ph9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ph9gh7 <= Piufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ri9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ri9gh7 <= T5rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tj9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Tj9gh7 <= Virfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wk9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wk9gh7 <= T3sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wl9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wl9gh7 <= Nhrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zm9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Zm9gh7 <= Nyrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Bo9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Bo9gh7 <= Wxrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Dp9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Dp9gh7 <= Fxrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Fq9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Fq9gh7 <= Owrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ir9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ir9gh7 <= Zarfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ls9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ls9gh7 <= S7rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Lt9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Lt9gh7 <= Tmrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ou9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ou9gh7 <= Vkqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Pv9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Pv9gh7 <= Npufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rw9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rw9gh7 <= Hjufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tx9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Tx9gh7 <= Mjrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wy9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wy9gh7 <= Cmrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zz9gh7 <= 1'b0;
+ end
+ else
+ begin
+ Zz9gh7 <= Ukrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ C1agh7 <= 1'b0;
+ end
+ else
+ begin
+ C1agh7 <= Xvrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ F2agh7 <= 1'b0;
+ end
+ else
+ begin
+ F2agh7 <= J8rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ I3agh7 <= 1'b0;
+ end
+ else
+ begin
+ I3agh7 <= Htrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ L4agh7 <= 1'b0;
+ end
+ else
+ begin
+ L4agh7 <= Qsrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ O5agh7 <= 1'b0;
+ end
+ else
+ begin
+ O5agh7 <= Iarfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ R6agh7 <= 1'b0;
+ end
+ else
+ begin
+ R6agh7 <= R9rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ U7agh7 <= 1'b0;
+ end
+ else
+ begin
+ U7agh7 <= K4sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ U8agh7 <= 1'b0;
+ end
+ else
+ begin
+ U8agh7 <= Gvrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ X9agh7 <= 1'b0;
+ end
+ else
+ begin
+ X9agh7 <= Purfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Abagh7 <= 1'b1;
+ end
+ else
+ begin
+ Abagh7 <= Xktfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wbagh7 <= 1'b0;
+ end
+ else
+ begin
+ Wbagh7 <= Ytrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zcagh7 <= 1'b0;
+ end
+ else
+ begin
+ Zcagh7 <= Qbrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ceagh7 <= 1'b0;
+ end
+ else
+ begin
+ Ceagh7 <= L2sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Efagh7 <= 1'b0;
+ end
+ else
+ begin
+ Efagh7 <= U1sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ggagh7 <= 1'b0;
+ end
+ else
+ begin
+ Ggagh7 <= Hcrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Jhagh7 <= 1'b0;
+ end
+ else
+ begin
+ Jhagh7 <= Llrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Miagh7 <= 1'b0;
+ end
+ else
+ begin
+ Miagh7 <= Eirfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Pjagh7 <= 1'b0;
+ end
+ else
+ begin
+ Pjagh7 <= Fgrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Skagh7 <= 1'b0;
+ end
+ else
+ begin
+ Skagh7 <= Wgrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Vlagh7 <= 1'b0;
+ end
+ else
+ begin
+ Vlagh7 <= Ofrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ymagh7 <= 1'b0;
+ end
+ else
+ begin
+ Ymagh7 <= Xerfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Boagh7 <= 1'b0;
+ end
+ else
+ begin
+ Boagh7 <= Ycrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Epagh7 <= 1'b0;
+ end
+ else
+ begin
+ Epagh7 <= Prufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Eqagh7 <= 1'b0;
+ end
+ else
+ begin
+ Eqagh7 <= Jrufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Eragh7 <= 1'b0;
+ end
+ else
+ begin
+ Eragh7 <= Drufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Esagh7 <= 1'b0;
+ end
+ else
+ begin
+ Esagh7 <= Xqufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Etagh7 <= 1'b0;
+ end
+ else
+ begin
+ Etagh7 <= Rqufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Euagh7 <= 1'b0;
+ end
+ else
+ begin
+ Euagh7 <= Lqufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Evagh7 <= 1'b0;
+ end
+ else
+ begin
+ Evagh7 <= Fqufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ewagh7 <= 1'b0;
+ end
+ else
+ begin
+ Ewagh7 <= Sorfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hxagh7 <= 1'b0;
+ end
+ else
+ begin
+ Hxagh7 <= Borfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kyagh7 <= 1'b0;
+ end
+ else
+ begin
+ Kyagh7 <= Aqrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Nzagh7 <= 1'b0;
+ end
+ else
+ begin
+ Nzagh7 <= Rqrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Q0bgh7 <= 1'b0;
+ end
+ else
+ begin
+ Q0bgh7 <= Knrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ T1bgh7 <= 1'b0;
+ end
+ else
+ begin
+ T1bgh7 <= Pdrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ W2bgh7 <= 1'b0;
+ end
+ else
+ begin
+ W2bgh7 <= Zrrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Z3bgh7 <= 1'b0;
+ end
+ else
+ begin
+ Z3bgh7 <= Irrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ C5bgh7 <= 1'b0;
+ end
+ else
+ begin
+ C5bgh7 <= Jprfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ F6bgh7 <= 1'b0;
+ end
+ else
+ begin
+ F6bgh7 <= Vrufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H7bgh7 <= 1'b0;
+ end
+ else
+ begin
+ H7bgh7 <= Zpufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ K8bgh7 <= 1'b0;
+ end
+ else
+ begin
+ K8bgh7 <= Dkrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ N9bgh7 <= 1'b0;
+ end
+ else
+ begin
+ N9bgh7 <= Njufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Pabgh7 <= 1'b0;
+ end
+ else
+ begin
+ Pabgh7 <= Lkufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rbbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Rbbgh7 <= Jlufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ucbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ucbgh7 <= Hmufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Xdbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Xdbgh7 <= Fnufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Afbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Afbgh7 <= Doufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Dgbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Dgbgh7 <= Bpufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ghbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ghbgh7 <= W1qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Iibgh7 <= 1'b0;
+ end
+ else
+ begin
+ Iibgh7 <= O0qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kjbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Kjbgh7 <= Tpufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Nkbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Nkbgh7 <= M4qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Plbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Plbgh7 <= C7qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rmbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Rmbgh7 <= S9qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tnbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Tnbgh7 <= Icqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Vobgh7 <= 1'b0;
+ end
+ else
+ begin
+ Vobgh7 <= Yeqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wpbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Wpbgh7 <= Ohqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Xqbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Xqbgh7 <= Fiqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Yrbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Yrbgh7 <= Ekqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zsbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zsbgh7 <= Viufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Bubgh7 <= 1'b0;
+ end
+ else
+ begin
+ Bubgh7 <= Njqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Cvbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Cvbgh7 <= Rbufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Dwbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Dwbgh7 <= N4ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Dxbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Dxbgh7 <= Bjufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Fybgh7 <= 1'b0;
+ end
+ else
+ begin
+ Fybgh7 <= Wiqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Gzbgh7 <= 1'b0;
+ end
+ else
+ begin
+ Gzbgh7 <= Xbufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H0cgh7 <= 1'b0;
+ end
+ else
+ begin
+ H0cgh7 <= T4ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H1cgh7 <= 1'b0;
+ end
+ else
+ begin
+ H1cgh7 <= X5ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H2cgh7 <= 1'b0;
+ end
+ else
+ begin
+ H2cgh7 <= Fkufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ J3cgh7 <= 1'b0;
+ end
+ else
+ begin
+ J3cgh7 <= Pfqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ K4cgh7 <= 1'b0;
+ end
+ else
+ begin
+ K4cgh7 <= Dlufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ N5cgh7 <= 1'b0;
+ end
+ else
+ begin
+ N5cgh7 <= Zcqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ P6cgh7 <= 1'b0;
+ end
+ else
+ begin
+ P6cgh7 <= Bmufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ S7cgh7 <= 1'b0;
+ end
+ else
+ begin
+ S7cgh7 <= Jaqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ U8cgh7 <= 1'b0;
+ end
+ else
+ begin
+ U8cgh7 <= Zmufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ X9cgh7 <= 1'b0;
+ end
+ else
+ begin
+ X9cgh7 <= T7qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zacgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zacgh7 <= Xnufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Cccgh7 <= 1'b0;
+ end
+ else
+ begin
+ Cccgh7 <= D5qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Edcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Edcgh7 <= Voufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hecgh7 <= 1'b0;
+ end
+ else
+ begin
+ Hecgh7 <= N2qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Jfcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Jfcgh7 <= Naufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kgcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Kgcgh7 <= Rhufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Mhcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Mhcgh7 <= P9ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Nicgh7 <= 1'b0;
+ end
+ else
+ begin
+ Nicgh7 <= Tgufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Pjcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Pjcgh7 <= R8ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Qkcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Qkcgh7 <= Vfufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Slcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Slcgh7 <= T7ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tmcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Tmcgh7 <= Xeufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Vncgh7 <= 1'b0;
+ end
+ else
+ begin
+ Vncgh7 <= V6ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wocgh7 <= 1'b0;
+ end
+ else
+ begin
+ Wocgh7 <= Zdufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ypcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ypcgh7 <= Bdufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zqcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zqcgh7 <= R5ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zrcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zrcgh7 <= Zjufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Btcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Btcgh7 <= Ggqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Cucgh7 <= 1'b0;
+ end
+ else
+ begin
+ Cucgh7 <= Xkufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Fvcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Fvcgh7 <= Qdqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hwcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Hwcgh7 <= Vlufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kxcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Kxcgh7 <= Abqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Mycgh7 <= 1'b0;
+ end
+ else
+ begin
+ Mycgh7 <= Tmufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Pzcgh7 <= 1'b0;
+ end
+ else
+ begin
+ Pzcgh7 <= K8qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ R0dgh7 <= 1'b0;
+ end
+ else
+ begin
+ R0dgh7 <= Rnufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ U1dgh7 <= 1'b0;
+ end
+ else
+ begin
+ U1dgh7 <= U5qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ W2dgh7 <= 1'b0;
+ end
+ else
+ begin
+ W2dgh7 <= Poufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Z3dgh7 <= 1'b0;
+ end
+ else
+ begin
+ Z3dgh7 <= E3qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ B5dgh7 <= 1'b0;
+ end
+ else
+ begin
+ B5dgh7 <= Haufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ C6dgh7 <= 1'b0;
+ end
+ else
+ begin
+ C6dgh7 <= Lhufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ E7dgh7 <= 1'b0;
+ end
+ else
+ begin
+ E7dgh7 <= J9ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ F8dgh7 <= 1'b0;
+ end
+ else
+ begin
+ F8dgh7 <= Ngufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H9dgh7 <= 1'b0;
+ end
+ else
+ begin
+ H9dgh7 <= L8ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Iadgh7 <= 1'b0;
+ end
+ else
+ begin
+ Iadgh7 <= Pfufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kbdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Kbdgh7 <= N7ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Lcdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Lcdgh7 <= Reufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Nddgh7 <= 1'b0;
+ end
+ else
+ begin
+ Nddgh7 <= P6ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Oedgh7 <= 1'b0;
+ end
+ else
+ begin
+ Oedgh7 <= Tdufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Qfdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Qfdgh7 <= Vcufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rgdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Rgdgh7 <= L5ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rhdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Rhdgh7 <= Tjufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tidgh7 <= 1'b0;
+ end
+ else
+ begin
+ Tidgh7 <= Xgqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ujdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ujdgh7 <= Rkufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Xkdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Xkdgh7 <= Heqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zldgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zldgh7 <= Plufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Cndgh7 <= 1'b0;
+ end
+ else
+ begin
+ Cndgh7 <= Rbqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Eodgh7 <= 1'b0;
+ end
+ else
+ begin
+ Eodgh7 <= Nmufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hpdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Hpdgh7 <= B9qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Jqdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Jqdgh7 <= Lnufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Mrdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Mrdgh7 <= L6qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Osdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Osdgh7 <= Joufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rtdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Rtdgh7 <= V3qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tudgh7 <= 1'b0;
+ end
+ else
+ begin
+ Tudgh7 <= Hpufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wvdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Wvdgh7 <= F1qfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ywdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ywdgh7 <= Zaufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zxdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zxdgh7 <= Diufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Bzdgh7 <= 1'b0;
+ end
+ else
+ begin
+ Bzdgh7 <= Baufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ C0egh7 <= 1'b0;
+ end
+ else
+ begin
+ C0egh7 <= Fhufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ E1egh7 <= 1'b0;
+ end
+ else
+ begin
+ E1egh7 <= D9ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ F2egh7 <= 1'b0;
+ end
+ else
+ begin
+ F2egh7 <= Hgufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H3egh7 <= 1'b0;
+ end
+ else
+ begin
+ H3egh7 <= F8ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ I4egh7 <= 1'b0;
+ end
+ else
+ begin
+ I4egh7 <= Jfufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ K5egh7 <= 1'b0;
+ end
+ else
+ begin
+ K5egh7 <= H7ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ L6egh7 <= 1'b0;
+ end
+ else
+ begin
+ L6egh7 <= Leufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ N7egh7 <= 1'b0;
+ end
+ else
+ begin
+ N7egh7 <= J6ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ O8egh7 <= 1'b0;
+ end
+ else
+ begin
+ O8egh7 <= Ndufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Q9egh7 <= 1'b0;
+ end
+ else
+ begin
+ Q9egh7 <= Pcufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Raegh7 <= 1'b0;
+ end
+ else
+ begin
+ Raegh7 <= Z4ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Rbegh7 <= 1'b0;
+ end
+ else
+ begin
+ Rbegh7 <= Z1ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Scegh7 <= 1'b0;
+ end
+ else
+ begin
+ Scegh7 <= F2ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Udegh7 <= 1'b0;
+ end
+ else
+ begin
+ Udegh7 <= Taufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Veegh7 <= 1'b0;
+ end
+ else
+ begin
+ Veegh7 <= Xhufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Xfegh7 <= 1'b0;
+ end
+ else
+ begin
+ Xfegh7 <= V9ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ygegh7 <= 1'b0;
+ end
+ else
+ begin
+ Ygegh7 <= Zgufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Aiegh7 <= 1'b0;
+ end
+ else
+ begin
+ Aiegh7 <= X8ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Bjegh7 <= 1'b0;
+ end
+ else
+ begin
+ Bjegh7 <= Bgufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Dkegh7 <= 1'b0;
+ end
+ else
+ begin
+ Dkegh7 <= Z7ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Elegh7 <= 1'b0;
+ end
+ else
+ begin
+ Elegh7 <= Dfufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Gmegh7 <= 1'b0;
+ end
+ else
+ begin
+ Gmegh7 <= B7ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hnegh7 <= 1'b0;
+ end
+ else
+ begin
+ Hnegh7 <= Feufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Joegh7 <= 1'b0;
+ end
+ else
+ begin
+ Joegh7 <= D6ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Jpegh7 <= 1'b0;
+ end
+ else
+ begin
+ Jpegh7 <= Hdufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kqegh7 <= 1'b0;
+ end
+ else
+ begin
+ Kqegh7 <= L2ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kregh7 <= 1'b0;
+ end
+ else
+ begin
+ Kregh7 <= R2ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ksegh7 <= 1'b0;
+ end
+ else
+ begin
+ Ksegh7 <= D3ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ktegh7 <= 1'b0;
+ end
+ else
+ begin
+ Ktegh7 <= J3ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kuegh7 <= 1'b0;
+ end
+ else
+ begin
+ Kuegh7 <= P3ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kvegh7 <= 1'b0;
+ end
+ else
+ begin
+ Kvegh7 <= B4ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kwegh7 <= 1'b0;
+ end
+ else
+ begin
+ Kwegh7 <= F5ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kxegh7 <= 1'b0;
+ end
+ else
+ begin
+ Kxegh7 <= X2ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kyegh7 <= 1'b0;
+ end
+ else
+ begin
+ Kyegh7 <= Jcufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Lzegh7 <= 1'b0;
+ end
+ else
+ begin
+ Lzegh7 <= Xzpfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ O0fgh7 <= 1'b0;
+ end
+ else
+ begin
+ O0fgh7 <= Mlqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ P1fgh7 <= 1'b0;
+ end
+ else
+ begin
+ P1fgh7 <= Gerfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ S2fgh7 <= 1'b0;
+ end
+ else
+ begin
+ S2fgh7 <= A9rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ V3fgh7 <= 1'b0;
+ end
+ else
+ begin
+ V3fgh7 <= M0sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ X4fgh7 <= 1'b0;
+ end
+ else
+ begin
+ X4fgh7 <= Ezrfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Z5fgh7 <= 1'b0;
+ end
+ else
+ begin
+ Z5fgh7 <= D1sfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ B7fgh7 <= 1'b0;
+ end
+ else
+ begin
+ B7fgh7 <= Vzrfh7;
+ end
+ always @(posedge Puufh7) D8fgh7 <= Tstfh7;
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ H9fgh7 <= 1'b0;
+ end
+ else
+ begin
+ H9fgh7 <= B7rfh7;
+ end
+ always @(posedge Puufh7) Hafgh7 <= Xtufh7;
+ always @(posedge Puufh7) Lbfgh7 <= Rtufh7;
+ always @(posedge Puufh7) Pcfgh7 <= Ltufh7;
+ always @(posedge Puufh7) Tdfgh7 <= Ftufh7;
+ always @(posedge Puufh7) Xefgh7 <= Zsufh7;
+ always @(posedge Puufh7) Bgfgh7 <= Tsufh7;
+ always @(posedge Puufh7) Fhfgh7 <= Nsufh7;
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Jifgh7 <= 1'b0;
+ end
+ else
+ begin
+ Jifgh7 <= H1ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ojfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ojfgh7 <= B1ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tkfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Tkfgh7 <= P0ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ylfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ylfgh7 <= J0ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Dnfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Dnfgh7 <= D0ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Iofgh7 <= 1'b1;
+ end
+ else
+ begin
+ Iofgh7 <= Xztfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Npfgh7 <= 1'b1;
+ end
+ else
+ begin
+ Npfgh7 <= Rztfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Sqfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Sqfgh7 <= Lztfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Yrfgh7 <= 1'b1;
+ end
+ else
+ begin
+ Yrfgh7 <= Fztfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Etfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Etfgh7 <= Zytfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kufgh7 <= 1'b1;
+ end
+ else
+ begin
+ Kufgh7 <= Tytfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Qvfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Qvfgh7 <= Nytfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wwfgh7 <= 1'b1;
+ end
+ else
+ begin
+ Wwfgh7 <= Hytfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Cyfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Cyfgh7 <= Vxtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Izfgh7 <= 1'b0;
+ end
+ else
+ begin
+ Izfgh7 <= Pxtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ O0ggh7 <= 1'b0;
+ end
+ else
+ begin
+ O0ggh7 <= Jxtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ U1ggh7 <= 1'b0;
+ end
+ else
+ begin
+ U1ggh7 <= Dxtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ A3ggh7 <= 1'b0;
+ end
+ else
+ begin
+ A3ggh7 <= Xwtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ G4ggh7 <= 1'b1;
+ end
+ else
+ begin
+ G4ggh7 <= Rwtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ M5ggh7 <= 1'b1;
+ end
+ else
+ begin
+ M5ggh7 <= Lwtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ S6ggh7 <= 1'b0;
+ end
+ else
+ begin
+ S6ggh7 <= Fwtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Y7ggh7 <= 1'b0;
+ end
+ else
+ begin
+ Y7ggh7 <= Zvtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ E9ggh7 <= 1'b0;
+ end
+ else
+ begin
+ E9ggh7 <= Tvtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kaggh7 <= 1'b0;
+ end
+ else
+ begin
+ Kaggh7 <= Nvtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Qbggh7 <= 1'b1;
+ end
+ else
+ begin
+ Qbggh7 <= Hvtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wcggh7 <= 1'b0;
+ end
+ else
+ begin
+ Wcggh7 <= Bvtfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ceggh7 <= 1'b1;
+ end
+ else
+ begin
+ Ceggh7 <= Vutfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ifggh7 <= 1'b0;
+ end
+ else
+ begin
+ Ifggh7 <= Putfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ogggh7 <= 1'b0;
+ end
+ else
+ begin
+ Ogggh7 <= Dcufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Phggh7 <= 1'b0;
+ end
+ else
+ begin
+ Phggh7 <= V0ufh7;
+ end
+ always @(posedge Puufh7) Uiggh7 <= Hsufh7;
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Yjggh7 <= 1'b0;
+ end
+ else
+ begin
+ Yjggh7 <= Fbufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ykggh7 <= 1'b0;
+ end
+ else
+ begin
+ Ykggh7 <= V3ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ylggh7 <= 1'b1;
+ end
+ else
+ begin
+ Ylggh7 <= Bytfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Enggh7 <= 1'b0;
+ end
+ else
+ begin
+ Enggh7 <= Jiufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Foggh7 <= 1'b0;
+ end
+ else
+ begin
+ Foggh7 <= K6rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hpggh7 <= 1'b0;
+ end
+ else
+ begin
+ Hpggh7 <= C5rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Jqggh7 <= 1'b0;
+ end
+ else
+ begin
+ Jqggh7 <= L4rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Lrggh7 <= 1'b0;
+ end
+ else
+ begin
+ Lrggh7 <= U3rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Nsggh7 <= 1'b0;
+ end
+ else
+ begin
+ Nsggh7 <= D3rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ptggh7 <= 1'b0;
+ end
+ else
+ begin
+ Ptggh7 <= M2rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ruggh7 <= 1'b0;
+ end
+ else
+ begin
+ Ruggh7 <= V1rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tvggh7 <= 1'b0;
+ end
+ else
+ begin
+ Tvggh7 <= E1rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Vwggh7 <= 1'b0;
+ end
+ else
+ begin
+ Vwggh7 <= N0rfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Xxggh7 <= 1'b0;
+ end
+ else
+ begin
+ Xxggh7 <= Wzqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Azggh7 <= 1'b0;
+ end
+ else
+ begin
+ Azggh7 <= Fzqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ D0hgh7 <= 1'b0;
+ end
+ else
+ begin
+ D0hgh7 <= Oyqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ G1hgh7 <= 1'b0;
+ end
+ else
+ begin
+ G1hgh7 <= Xxqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ J2hgh7 <= 1'b0;
+ end
+ else
+ begin
+ J2hgh7 <= Gxqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ M3hgh7 <= 1'b0;
+ end
+ else
+ begin
+ M3hgh7 <= Pwqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ P4hgh7 <= 1'b0;
+ end
+ else
+ begin
+ P4hgh7 <= Yvqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ S5hgh7 <= 1'b0;
+ end
+ else
+ begin
+ S5hgh7 <= Hvqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ V6hgh7 <= 1'b0;
+ end
+ else
+ begin
+ V6hgh7 <= Quqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Y7hgh7 <= 1'b0;
+ end
+ else
+ begin
+ Y7hgh7 <= Ztqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ B9hgh7 <= 1'b0;
+ end
+ else
+ begin
+ B9hgh7 <= Itqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Eahgh7 <= 1'b0;
+ end
+ else
+ begin
+ Eahgh7 <= Rsqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Hbhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Hbhgh7 <= Asqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Kchgh7 <= 1'b0;
+ end
+ else
+ begin
+ Kchgh7 <= Jrqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ndhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ndhgh7 <= Sqqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Qehgh7 <= 1'b0;
+ end
+ else
+ begin
+ Qehgh7 <= Bqqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Tfhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Tfhgh7 <= Kpqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Wghgh7 <= 1'b0;
+ end
+ else
+ begin
+ Wghgh7 <= Toqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Zhhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Zhhgh7 <= Coqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Cjhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Cjhgh7 <= Lnqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Fkhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Fkhgh7 <= Umqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Ilhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Ilhgh7 <= Dmqfh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Lmhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Lmhgh7 <= Lbufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Mnhgh7 <= 1'b0;
+ end
+ else
+ begin
+ Mnhgh7 <= H4ufh7;
+ end
+ always @(posedge Puufh7 or negedge Duufh7) if (~Duufh7) begin
+ Mohgh7 <= 1'b1;
+ end
+ else
+ begin
+ Mohgh7 <= N1ufh7;
+ end
+ always @(posedge Puufh7) Rphgh7 <= Fttfh7;
+ always @(posedge Puufh7) Vqhgh7 <= Lttfh7;
+ always @(posedge Puufh7) Zrhgh7 <= Rttfh7;
+ always @(posedge Puufh7) Dthgh7 <= Dutfh7;
+ always @(posedge Puufh7) Huhgh7 <= Zstfh7;
+ always @(posedge Puufh7) Lvhgh7 <= Xttfh7;
+ always @(posedge Puufh7) Pwhgh7 <= Jutfh7;
+endmodule
+
+/* Design Summary
+ modules: 1
+ udps: 0
+ mod flatinsts: 0
+ udp flatinsts: 0
+ nodes: 3002 (0)
+ node widths: 3242 (0)
+ process: 281 (0)
+ gates: 0 (0)
+ contassigns: 2769 (0)
+ ports: 27 (0)
+ modinsts: 0 (0)
+ udpinsts: 0 (0)
+ portconnects: 0 (0)
+*/
+
+// END: VCS tokens
+// Currnet Allocated Virtual Memory Size: 203.99 MB
+// ===================
+// DESIGN STATISTICS
+// ===================
+//
+// No. of design lines (note: includes comments and blank lines) 7430
+//
+// Static<!> Elaborated<@> Size(KB)
+// ------ ---------- --------
+// No. of all modules (module+interface+package+program): 1 1 0
+// No. of module instances: 1 1 0
+// No. of all processes: 281 281 0
+// No. of all nodes (variable+net): 3002 3002 0
+// No. of constants 653 653 0
+// No. of scalar nets: 2705 2705 0
+// No. of vector nets: 16 16 0
+// No. of scalar regs/logics: 281 281 0
+// No. of always blocks: 281 281 0
+// No. of operators: 4486 4486 0
+// No. of concatenations: 8 8 0
+// No. of bit selects: 306 306 0
+// No. of part selects: 2 2 0
+// No. of non-blocking assignments: 546 546 0
+// No. of continuous assignments: 2769 2769 0
+//
+// No. of top level modules/programs/packages/interfaces: 1
+// modules: 1
+// No. of module+udp ports: 27
+//
+// Footnotes:
+// ---------
+// <!> No. of unique instances of a construct as it appears in the source.
+// <@> No. of instances of a construct when the design is elaborated.
+// K, M, B: Counted in thousands, millions and billions (if big numbers are present)
+//
+// <#> Multiple specify blocks in the SAME module are combined and counted
+// as ONE block.
diff --git a/IPLIB/ADPcontrol_v1_0/ADPcontrol_bas__mangled.v b/IPLIB/ADPcontrol_v1_0/ADPcontrol_bas__mangled.v
new file mode 100755
index 0000000000000000000000000000000000000000..20e0b88d4a2b2a51aac842b3007e8b4dcb837e87
--- /dev/null
+++ b/IPLIB/ADPcontrol_v1_0/ADPcontrol_bas__mangled.v
@@ -0,0 +1,4923 @@
+//
+// A joint work commissioned on behalf of SoC Labs.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Obfuscated RTL
+//
+// Copyright (C) 2021-2, SoC Labs (www.soclabs.org)
+//
+
+/*
+ instances: 0
+ nodes: 1943 (0)
+ node widths: 2119 (0)
+ process: 173 (0)
+ contassign: 1818 (0)
+ ports: 27 (0)
+*/
+
+/* Source file "tokens.v", line 14 */
+module ADPcontrol(ahb_hclk, ahb_hresetn, com_rx_tready, com_rx_tdata,
+ com_rx_tvalid, com_tx_tvalid, com_tx_tdata, com_tx_tready,
+ stdio_rx_tready, stdio_rx_tdata, stdio_rx_tvalid, stdio_tx_tvalid,
+ stdio_tx_tdata, stdio_tx_tready, gpo8, gpi8, ahb_haddr, ahb_hburst,
+ ahb_hmastlock, ahb_hprot, ahb_hsize, ahb_htrans, ahb_hwdata, ahb_hwrite,
+ ahb_hrdata, ahb_hready, ahb_hresp);
+
+ input [7:0] com_rx_tdata;
+ output [7:0] com_tx_tdata;
+ input [7:0] stdio_rx_tdata;
+ output [7:0] stdio_tx_tdata;
+ output [7:0] gpo8;
+ input [7:0] gpi8;
+ output [31:0] ahb_haddr;
+ output [2:0] ahb_hburst;
+ output [3:0] ahb_hprot;
+ output [2:0] ahb_hsize;
+ output [1:0] ahb_htrans;
+ output [31:0] ahb_hwdata;
+ input [31:0] ahb_hrdata;
+ input ahb_hclk;
+ input ahb_hresetn;
+ input com_rx_tvalid;
+ input com_tx_tready;
+ input stdio_rx_tvalid;
+ input stdio_tx_tready;
+ input ahb_hready;
+ input ahb_hresp;
+ output com_rx_tready;
+ output com_tx_tvalid;
+ output stdio_rx_tready;
+ output stdio_tx_tvalid;
+ output ahb_hmastlock;
+ output ahb_hwrite;
+
+ wire Xzpfh7;
+ wire O0qfh7;
+ wire F1qfh7;
+ wire W1qfh7;
+ wire N2qfh7;
+ wire E3qfh7;
+ wire V3qfh7;
+ wire M4qfh7;
+ wire D5qfh7;
+ wire U5qfh7;
+ wire L6qfh7;
+ wire C7qfh7;
+ wire T7qfh7;
+ wire K8qfh7;
+ wire B9qfh7;
+ wire S9qfh7;
+ wire Jaqfh7;
+ wire Abqfh7;
+ wire Rbqfh7;
+ wire Icqfh7;
+ wire Zcqfh7;
+ wire Qdqfh7;
+ wire Heqfh7;
+ wire Yeqfh7;
+ wire Pfqfh7;
+ wire Ggqfh7;
+ wire Xgqfh7;
+ wire Ohqfh7;
+ wire Fiqfh7;
+ wire Wiqfh7;
+ wire Njqfh7;
+ wire Ekqfh7;
+ wire Vkqfh7;
+ wire Mlqfh7;
+ wire Dmqfh7;
+ wire Umqfh7;
+ wire Lnqfh7;
+ wire Coqfh7;
+ wire Toqfh7;
+ wire Kpqfh7;
+ wire Bqqfh7;
+ wire Sqqfh7;
+ wire Jrqfh7;
+ wire Asqfh7;
+ wire Rsqfh7;
+ wire Itqfh7;
+ wire Ztqfh7;
+ wire Quqfh7;
+ wire Hvqfh7;
+ wire Yvqfh7;
+ wire Pwqfh7;
+ wire Gxqfh7;
+ wire Xxqfh7;
+ wire Oyqfh7;
+ wire Fzqfh7;
+ wire Wzqfh7;
+ wire N0rfh7;
+ wire E1rfh7;
+ wire V1rfh7;
+ wire M2rfh7;
+ wire D3rfh7;
+ wire U3rfh7;
+ wire L4rfh7;
+ wire C5rfh7;
+ wire T5rfh7;
+ wire K6rfh7;
+ wire B7rfh7;
+ wire S7rfh7;
+ wire J8rfh7;
+ wire A9rfh7;
+ wire R9rfh7;
+ wire Iarfh7;
+ wire Zarfh7;
+ wire Qbrfh7;
+ wire Gcrfh7;
+ wire Wcrfh7;
+ wire Mdrfh7;
+ wire Cerfh7;
+ wire Serfh7;
+ wire Ifrfh7;
+ wire Yfrfh7;
+ wire Ogrfh7;
+ wire Ehrfh7;
+ wire Uhrfh7;
+ wire Kirfh7;
+ wire Ajrfh7;
+ wire Qjrfh7;
+ wire Gkrfh7;
+ wire Wkrfh7;
+ wire Mlrfh7;
+ wire Cmrfh7;
+ wire Smrfh7;
+ wire Inrfh7;
+ wire Ynrfh7;
+ wire Oorfh7;
+ wire Eprfh7;
+ wire Uprfh7;
+ wire Kqrfh7;
+ wire Arrfh7;
+ wire Qrrfh7;
+ wire Gsrfh7;
+ wire Wsrfh7;
+ wire Mtrfh7;
+ wire Curfh7;
+ wire Surfh7;
+ wire Ivrfh7;
+ wire Yvrfh7;
+ wire Wwrfh7;
+ wire Bxrfh7;
+ wire Gxrfh7;
+ wire Lxrfh7;
+ wire Qxrfh7;
+ wire Vxrfh7;
+ wire Ayrfh7;
+ wire Fyrfh7;
+ wire Kyrfh7;
+ wire Pyrfh7;
+ wire Uyrfh7;
+ wire Zyrfh7;
+ wire Ezrfh7;
+ wire Jzrfh7;
+ wire Ozrfh7;
+ wire Tzrfh7;
+ wire Yzrfh7;
+ wire D0sfh7;
+ wire I0sfh7;
+ wire N0sfh7;
+ wire S0sfh7;
+ wire X0sfh7;
+ wire C1sfh7;
+ wire H1sfh7;
+ wire M1sfh7;
+ wire R1sfh7;
+ wire W1sfh7;
+ wire B2sfh7;
+ wire G2sfh7;
+ wire L2sfh7;
+ wire Q2sfh7;
+ wire V2sfh7;
+ wire A3sfh7;
+ wire F3sfh7;
+ wire K3sfh7;
+ wire P3sfh7;
+ wire U3sfh7;
+ wire Z3sfh7;
+ wire E4sfh7;
+ wire J4sfh7;
+ wire O4sfh7;
+ wire T4sfh7;
+ wire Y4sfh7;
+ wire D5sfh7;
+ wire I5sfh7;
+ wire N5sfh7;
+ wire S5sfh7;
+ wire X5sfh7;
+ wire C6sfh7;
+ wire H6sfh7;
+ wire M6sfh7;
+ wire R6sfh7;
+ wire W6sfh7;
+ wire B7sfh7;
+ wire G7sfh7;
+ wire L7sfh7;
+ wire Q7sfh7;
+ wire V7sfh7;
+ wire A8sfh7;
+ wire F8sfh7;
+ wire K8sfh7;
+ wire P8sfh7;
+ wire U8sfh7;
+ wire Z8sfh7;
+ wire E9sfh7;
+ wire J9sfh7;
+ wire O9sfh7;
+ wire T9sfh7;
+ wire Y9sfh7;
+ wire Dasfh7;
+ wire Iasfh7;
+ wire Nasfh7;
+ wire Sasfh7;
+ wire Xasfh7;
+ wire Cbsfh7;
+ wire Hbsfh7;
+ wire Mbsfh7;
+ wire Rbsfh7;
+ wire Wbsfh7;
+ wire Bcsfh7;
+ wire Gcsfh7;
+ wire Lcsfh7;
+ wire Qcsfh7;
+ wire Vcsfh7;
+ wire Adsfh7;
+ wire Fdsfh7;
+ wire Kdsfh7;
+ wire Pdsfh7;
+ wire Udsfh7;
+ wire Zdsfh7;
+ wire Eesfh7;
+ wire Jesfh7;
+ wire Oesfh7;
+ wire Tesfh7;
+ wire Yesfh7;
+ wire Dfsfh7;
+ wire Ifsfh7;
+ wire Nfsfh7;
+ wire Sfsfh7;
+ wire Xfsfh7;
+ wire Cgsfh7;
+ wire Hgsfh7;
+ wire Mgsfh7;
+ wire Rgsfh7;
+ wire Wgsfh7;
+ wire Bhsfh7;
+ wire Ghsfh7;
+ wire Lhsfh7;
+ wire Qhsfh7;
+ wire Vhsfh7;
+ wire Aisfh7;
+ wire Fisfh7;
+ wire Kisfh7;
+ wire Pisfh7;
+ wire Uisfh7;
+ wire Zisfh7;
+ wire Ejsfh7;
+ wire Jjsfh7;
+ wire Ojsfh7;
+ wire Tjsfh7;
+ wire Yjsfh7;
+ wire Dksfh7;
+ wire Iksfh7;
+ wire Oksfh7;
+ wire Uksfh7;
+ wire Alsfh7;
+ wire Glsfh7;
+ wire Mlsfh7;
+ wire Slsfh7;
+ wire Ylsfh7;
+ wire Emsfh7;
+ wire Kmsfh7;
+ wire Qmsfh7;
+ wire Wmsfh7;
+ wire Cnsfh7;
+ wire Insfh7;
+ wire Onsfh7;
+ wire Unsfh7;
+ wire Aosfh7;
+ wire Gosfh7;
+ wire Mosfh7;
+ wire Sosfh7;
+ wire Yosfh7;
+ wire Epsfh7;
+ wire Kpsfh7;
+ wire Qpsfh7;
+ wire Wpsfh7;
+ wire Cqsfh7;
+ wire Iqsfh7;
+ wire Oqsfh7;
+ wire Uqsfh7;
+ wire Arsfh7;
+ wire Grsfh7;
+ wire Mrsfh7;
+ wire Srsfh7;
+ wire Yrsfh7;
+ wire Essfh7;
+ wire Kssfh7;
+ wire Qssfh7;
+ wire Wssfh7;
+ wire Ctsfh7;
+ wire Itsfh7;
+ wire Otsfh7;
+ wire Utsfh7;
+ wire Ausfh7;
+ wire Gusfh7;
+ wire Musfh7;
+ wire Susfh7;
+ wire Yusfh7;
+ wire Evsfh7;
+ wire Kvsfh7;
+ wire Qvsfh7;
+ wire Wvsfh7;
+ wire Cwsfh7;
+ wire Iwsfh7;
+ wire Owsfh7;
+ wire Uwsfh7;
+ wire Axsfh7;
+ wire Gxsfh7;
+ wire Mxsfh7;
+ wire Sxsfh7;
+ wire Yxsfh7;
+ wire Eysfh7;
+ wire Kysfh7;
+ wire Qysfh7;
+ wire Wysfh7;
+ wire Czsfh7;
+ wire Izsfh7;
+ wire Ozsfh7;
+ wire Uzsfh7;
+ wire A0tfh7;
+ wire G0tfh7;
+ wire M0tfh7;
+ wire S0tfh7;
+ wire Y0tfh7;
+ wire E1tfh7;
+ wire K1tfh7;
+ wire Q1tfh7;
+ wire W1tfh7;
+ wire C2tfh7;
+ wire I2tfh7;
+ wire O2tfh7;
+ wire U2tfh7;
+ wire A3tfh7;
+ wire G3tfh7;
+ wire M3tfh7;
+ wire S3tfh7;
+ wire Y3tfh7;
+ wire E4tfh7;
+ wire K4tfh7;
+ wire Q4tfh7;
+ wire W4tfh7;
+ wire C5tfh7;
+ wire I5tfh7;
+ wire O5tfh7;
+ wire U5tfh7;
+ wire A6tfh7;
+ wire G6tfh7;
+ wire M6tfh7;
+ wire S6tfh7;
+ wire Y6tfh7;
+ wire E7tfh7;
+ wire K7tfh7;
+ wire Q7tfh7;
+ wire W7tfh7;
+ wire C8tfh7;
+ wire I8tfh7;
+ wire O8tfh7;
+ wire U8tfh7;
+ wire A9tfh7;
+ wire G9tfh7;
+ wire M9tfh7;
+ wire S9tfh7;
+ wire Y9tfh7;
+ wire Eatfh7;
+ wire Katfh7;
+ wire Qatfh7;
+ wire Watfh7;
+ wire Cbtfh7;
+ wire Ibtfh7;
+ wire Obtfh7;
+ wire Ubtfh7;
+ wire Actfh7;
+ wire Gctfh7;
+ wire Mctfh7;
+ wire Sctfh7;
+ wire Yctfh7;
+ wire Edtfh7;
+ wire Kdtfh7;
+ wire Qdtfh7;
+ wire Wdtfh7;
+ wire Cetfh7;
+ wire Ietfh7;
+ wire Oetfh7;
+ wire Uetfh7;
+ wire Aftfh7;
+ wire Gftfh7;
+ wire Mftfh7;
+ wire Sftfh7;
+ wire Yftfh7;
+ wire Egtfh7;
+ wire Kgtfh7;
+ wire Qgtfh7;
+ wire Wgtfh7;
+ wire Chtfh7;
+ wire Ihtfh7;
+ wire Ohtfh7;
+ wire Uhtfh7;
+ wire Aitfh7;
+ wire Gitfh7;
+ wire Mitfh7;
+ wire Sitfh7;
+ wire Yitfh7;
+ wire Ejtfh7;
+ wire Kjtfh7;
+ wire Qjtfh7;
+ wire Wjtfh7;
+ wire Cktfh7;
+ wire Iktfh7;
+ wire Oktfh7;
+ wire Uktfh7;
+ wire Altfh7;
+ wire Gltfh7;
+ wire Mltfh7;
+ wire Sltfh7;
+ wire Yltfh7;
+ wire Emtfh7;
+ wire Kmtfh7;
+ wire Qmtfh7;
+ wire Wmtfh7;
+ wire Cntfh7;
+ wire Intfh7;
+ wire Ontfh7;
+ wire Untfh7;
+ wire Aotfh7;
+ wire Gotfh7;
+ wire Motfh7;
+ wire Sotfh7;
+ wire Yotfh7;
+ wire Eptfh7;
+ wire Kptfh7;
+ wire Qptfh7;
+ wire Wptfh7;
+ wire Cqtfh7;
+ wire Iqtfh7;
+ wire Oqtfh7;
+ wire Uqtfh7;
+ wire Artfh7;
+ wire Grtfh7;
+ wire Mrtfh7;
+ wire Srtfh7;
+ wire Yrtfh7;
+ wire Estfh7;
+ wire Kstfh7;
+ wire Qstfh7;
+ wire Wstfh7;
+ wire Cttfh7;
+ wire Ittfh7;
+ wire Ottfh7;
+ wire Uttfh7;
+ wire Autfh7;
+ wire Gutfh7;
+ wire Mutfh7;
+ wire Sutfh7;
+ wire Yutfh7;
+ wire Evtfh7;
+ wire Kvtfh7;
+ wire Qvtfh7;
+ wire Wvtfh7;
+ wire Cwtfh7;
+ wire Iwtfh7;
+ wire Owtfh7;
+ wire Uwtfh7;
+ wire Axtfh7;
+ wire Gxtfh7;
+ wire Mxtfh7;
+ wire Sxtfh7;
+ wire Yxtfh7;
+ wire Eytfh7;
+ wire Kytfh7;
+ wire Qytfh7;
+ wire Wytfh7;
+ wire Cztfh7;
+ wire Iztfh7;
+ wire Oztfh7;
+ wire Uztfh7;
+ wire A0ufh7;
+ wire G0ufh7;
+ wire M0ufh7;
+ wire S0ufh7;
+ wire Y0ufh7;
+ wire E1ufh7;
+ wire K1ufh7;
+ wire Q1ufh7;
+ wire W1ufh7;
+ wire C2ufh7;
+ wire I2ufh7;
+ wire O2ufh7;
+ wire U2ufh7;
+ wire A3ufh7;
+ wire G3ufh7;
+ wire M3ufh7;
+ wire S3ufh7;
+ wire Y3ufh7;
+ wire E4ufh7;
+ wire K4ufh7;
+ wire Q4ufh7;
+ wire W4ufh7;
+ wire C5ufh7;
+ wire I5ufh7;
+ wire O5ufh7;
+ wire U5ufh7;
+ wire A6ufh7;
+ wire G6ufh7;
+ wire M6ufh7;
+ wire S6ufh7;
+ wire Y6ufh7;
+ wire E7ufh7;
+ wire K7ufh7;
+ wire Q7ufh7;
+ wire W7ufh7;
+ wire C8ufh7;
+ wire I8ufh7;
+ wire O8ufh7;
+ wire U8ufh7;
+ wire A9ufh7;
+ wire G9ufh7;
+ wire M9ufh7;
+ wire S9ufh7;
+ wire Y9ufh7;
+ wire Eaufh7;
+ wire Kaufh7;
+ wire Qaufh7;
+ wire Waufh7;
+ wire Cbufh7;
+ wire Ibufh7;
+ wire Obufh7;
+ wire Ubufh7;
+ wire Acufh7;
+ wire Gcufh7;
+ wire Mcufh7;
+ wire Scufh7;
+ wire Ycufh7;
+ wire Edufh7;
+ wire Kdufh7;
+ wire Qdufh7;
+ wire Wdufh7;
+ wire Ceufh7;
+ wire Ieufh7;
+ wire Oeufh7;
+ wire Ueufh7;
+ wire Afufh7;
+ wire Gfufh7;
+ wire Mfufh7;
+ wire Sfufh7;
+ wire Yfufh7;
+ wire Egufh7;
+ wire Kgufh7;
+ wire Qgufh7;
+ wire Wgufh7;
+ wire Chufh7;
+ wire Ihufh7;
+ wire Ohufh7;
+ wire Uhufh7;
+ wire Aiufh7;
+ wire Giufh7;
+ wire Miufh7;
+ wire Siufh7;
+ wire Yiufh7;
+ wire Ejufh7;
+ wire Kjufh7;
+ wire Qjufh7;
+ wire Wjufh7;
+ wire Ckufh7;
+ wire Ikufh7;
+ wire Okufh7;
+ wire Ukufh7;
+ wire Alufh7;
+ wire Glufh7;
+ wire Mlufh7;
+ wire Slufh7;
+ wire Ylufh7;
+ wire Emufh7;
+ wire Kmufh7;
+ wire Qmufh7;
+ wire Wmufh7;
+ wire Cnufh7;
+ wire Inufh7;
+ wire Onufh7;
+ wire Unufh7;
+ wire Aoufh7;
+ wire Goufh7;
+ wire Moufh7;
+ wire Soufh7;
+ wire Youfh7;
+ wire Epufh7;
+ wire Kpufh7;
+ wire Qpufh7;
+ wire Wpufh7;
+ wire Cqufh7;
+ wire Iqufh7;
+ wire Oqufh7;
+ wire Uqufh7;
+ wire Arufh7;
+ wire Grufh7;
+ wire Mrufh7;
+ wire Srufh7;
+ wire Yrufh7;
+ wire Esufh7;
+ wire Ksufh7;
+ wire Qsufh7;
+ wire Wsufh7;
+ wire Ctufh7;
+ wire Itufh7;
+ wire Otufh7;
+ wire Utufh7;
+ wire Auufh7;
+ wire Guufh7;
+ wire Muufh7;
+ wire Suufh7;
+ wire Yuufh7;
+ wire Evufh7;
+ wire Kvufh7;
+ wire Qvufh7;
+ wire Wvufh7;
+ wire Cwufh7;
+ wire Iwufh7;
+ wire Owufh7;
+ wire Uwufh7;
+ wire Axufh7;
+ wire Gxufh7;
+ wire Mxufh7;
+ wire Sxufh7;
+ wire Yxufh7;
+ wire Eyufh7;
+ wire Kyufh7;
+ wire Qyufh7;
+ wire Wyufh7;
+ wire Czufh7;
+ wire Izufh7;
+ wire Ozufh7;
+ wire Uzufh7;
+ wire A0vfh7;
+ wire G0vfh7;
+ wire M0vfh7;
+ wire S0vfh7;
+ wire Y0vfh7;
+ wire E1vfh7;
+ wire K1vfh7;
+ wire Q1vfh7;
+ wire W1vfh7;
+ wire C2vfh7;
+ wire I2vfh7;
+ wire O2vfh7;
+ wire U2vfh7;
+ wire A3vfh7;
+ wire G3vfh7;
+ wire M3vfh7;
+ wire S3vfh7;
+ wire Y3vfh7;
+ wire E4vfh7;
+ wire K4vfh7;
+ wire Q4vfh7;
+ wire W4vfh7;
+ wire C5vfh7;
+ wire I5vfh7;
+ wire O5vfh7;
+ wire U5vfh7;
+ wire A6vfh7;
+ wire G6vfh7;
+ wire M6vfh7;
+ wire S6vfh7;
+ wire Y6vfh7;
+ wire E7vfh7;
+ wire K7vfh7;
+ wire Q7vfh7;
+ wire W7vfh7;
+ wire C8vfh7;
+ wire I8vfh7;
+ wire O8vfh7;
+ wire U8vfh7;
+ wire A9vfh7;
+ wire G9vfh7;
+ wire M9vfh7;
+ wire S9vfh7;
+ wire Y9vfh7;
+ wire Eavfh7;
+ wire Kavfh7;
+ wire Qavfh7;
+ wire Wavfh7;
+ wire Cbvfh7;
+ wire Ibvfh7;
+ wire Obvfh7;
+ wire Ubvfh7;
+ wire Acvfh7;
+ wire Gcvfh7;
+ wire Mcvfh7;
+ wire Scvfh7;
+ wire Ycvfh7;
+ wire Edvfh7;
+ wire Kdvfh7;
+ wire Qdvfh7;
+ wire Wdvfh7;
+ wire Cevfh7;
+ wire Ievfh7;
+ wire Oevfh7;
+ wire Uevfh7;
+ wire Afvfh7;
+ wire Gfvfh7;
+ wire Mfvfh7;
+ wire Sfvfh7;
+ wire Yfvfh7;
+ wire Egvfh7;
+ wire Kgvfh7;
+ wire Qgvfh7;
+ wire Wgvfh7;
+ wire Chvfh7;
+ wire Ihvfh7;
+ wire Ohvfh7;
+ wire Uhvfh7;
+ wire Aivfh7;
+ wire Givfh7;
+ wire Mivfh7;
+ wire Sivfh7;
+ wire Yivfh7;
+ wire Ejvfh7;
+ wire Kjvfh7;
+ wire Qjvfh7;
+ wire Wjvfh7;
+ wire Ckvfh7;
+ wire Ikvfh7;
+ wire Okvfh7;
+ wire Ukvfh7;
+ wire Alvfh7;
+ wire Glvfh7;
+ wire Mlvfh7;
+ wire Slvfh7;
+ wire Ylvfh7;
+ wire Emvfh7;
+ wire Kmvfh7;
+ wire Qmvfh7;
+ wire Wmvfh7;
+ wire Cnvfh7;
+ wire Invfh7;
+ wire Onvfh7;
+ wire Unvfh7;
+ wire Aovfh7;
+ wire Govfh7;
+ wire Movfh7;
+ wire Sovfh7;
+ wire Yovfh7;
+ wire Epvfh7;
+ wire Kpvfh7;
+ wire Qpvfh7;
+ wire Wpvfh7;
+ wire Cqvfh7;
+ wire Iqvfh7;
+ wire Oqvfh7;
+ wire Uqvfh7;
+ wire Arvfh7;
+ wire Grvfh7;
+ wire Mrvfh7;
+ wire Srvfh7;
+ wire Yrvfh7;
+ wire Esvfh7;
+ wire Ksvfh7;
+ wire Qsvfh7;
+ wire Wsvfh7;
+ wire Ctvfh7;
+ wire Itvfh7;
+ wire Otvfh7;
+ wire Utvfh7;
+ wire Auvfh7;
+ wire Guvfh7;
+ wire Muvfh7;
+ wire Suvfh7;
+ wire Yuvfh7;
+ wire Evvfh7;
+ wire Kvvfh7;
+ wire Qvvfh7;
+ wire Wvvfh7;
+ wire Cwvfh7;
+ wire Iwvfh7;
+ wire Owvfh7;
+ wire Uwvfh7;
+ wire Axvfh7;
+ wire Gxvfh7;
+ wire Mxvfh7;
+ wire Sxvfh7;
+ wire Yxvfh7;
+ wire Eyvfh7;
+ wire Kyvfh7;
+ wire Qyvfh7;
+ wire Wyvfh7;
+ wire Czvfh7;
+ wire Izvfh7;
+ wire Ozvfh7;
+ wire Uzvfh7;
+ wire A0wfh7;
+ wire G0wfh7;
+ wire M0wfh7;
+ wire S0wfh7;
+ wire Y0wfh7;
+ wire E1wfh7;
+ wire K1wfh7;
+ wire Q1wfh7;
+ wire W1wfh7;
+ wire C2wfh7;
+ wire I2wfh7;
+ wire O2wfh7;
+ wire U2wfh7;
+ wire A3wfh7;
+ wire G3wfh7;
+ wire M3wfh7;
+ wire S3wfh7;
+ wire Y3wfh7;
+ wire E4wfh7;
+ wire K4wfh7;
+ wire Q4wfh7;
+ wire W4wfh7;
+ wire C5wfh7;
+ wire I5wfh7;
+ wire O5wfh7;
+ wire U5wfh7;
+ wire A6wfh7;
+ wire G6wfh7;
+ wire M6wfh7;
+ wire S6wfh7;
+ wire Y6wfh7;
+ wire E7wfh7;
+ wire K7wfh7;
+ wire Q7wfh7;
+ wire W7wfh7;
+ wire C8wfh7;
+ wire I8wfh7;
+ wire O8wfh7;
+ wire U8wfh7;
+ wire A9wfh7;
+ wire G9wfh7;
+ wire M9wfh7;
+ wire S9wfh7;
+ wire Y9wfh7;
+ wire Eawfh7;
+ wire Kawfh7;
+ wire Qawfh7;
+ wire Wawfh7;
+ wire Cbwfh7;
+ wire Ibwfh7;
+ wire Obwfh7;
+ wire Ubwfh7;
+ wire Acwfh7;
+ wire Gcwfh7;
+ wire Mcwfh7;
+ wire Scwfh7;
+ wire Ycwfh7;
+ wire Edwfh7;
+ wire Kdwfh7;
+ wire Qdwfh7;
+ wire Wdwfh7;
+ wire Cewfh7;
+ wire Iewfh7;
+ wire Oewfh7;
+ wire Uewfh7;
+ wire Afwfh7;
+ wire Gfwfh7;
+ wire Mfwfh7;
+ wire Sfwfh7;
+ wire Yfwfh7;
+ wire Egwfh7;
+ wire Kgwfh7;
+ wire Qgwfh7;
+ wire Wgwfh7;
+ wire Chwfh7;
+ wire Ihwfh7;
+ wire Ohwfh7;
+ wire Uhwfh7;
+ wire Aiwfh7;
+ wire Giwfh7;
+ wire Miwfh7;
+ wire Siwfh7;
+ wire Yiwfh7;
+ wire Ejwfh7;
+ wire Kjwfh7;
+ wire Qjwfh7;
+ wire Wjwfh7;
+ wire Ckwfh7;
+ wire Ikwfh7;
+ wire Okwfh7;
+ wire Ukwfh7;
+ wire Alwfh7;
+ wire Glwfh7;
+ wire Mlwfh7;
+ wire Slwfh7;
+ wire Ylwfh7;
+ wire Emwfh7;
+ wire Kmwfh7;
+ wire Qmwfh7;
+ wire Wmwfh7;
+ wire Cnwfh7;
+ wire Inwfh7;
+ wire Onwfh7;
+ wire Unwfh7;
+ wire Aowfh7;
+ wire Gowfh7;
+ wire Mowfh7;
+ wire Sowfh7;
+ wire Yowfh7;
+ wire Epwfh7;
+ wire Kpwfh7;
+ wire Qpwfh7;
+ wire Wpwfh7;
+ wire Cqwfh7;
+ wire Iqwfh7;
+ wire Oqwfh7;
+ wire Uqwfh7;
+ wire Arwfh7;
+ wire Grwfh7;
+ wire Mrwfh7;
+ wire Srwfh7;
+ wire Yrwfh7;
+ wire Eswfh7;
+ wire Kswfh7;
+ wire Qswfh7;
+ wire Wswfh7;
+ wire Ctwfh7;
+ wire Itwfh7;
+ wire Otwfh7;
+ wire Utwfh7;
+ wire Auwfh7;
+ wire Guwfh7;
+ wire Muwfh7;
+ wire Suwfh7;
+ wire Yuwfh7;
+ wire Evwfh7;
+ wire Kvwfh7;
+ wire Qvwfh7;
+ wire Wvwfh7;
+ wire Cwwfh7;
+ wire Iwwfh7;
+ wire Owwfh7;
+ wire Uwwfh7;
+ wire Axwfh7;
+ wire Gxwfh7;
+ wire Mxwfh7;
+ wire Sxwfh7;
+ wire Yxwfh7;
+ wire Eywfh7;
+ wire Kywfh7;
+ wire Qywfh7;
+ wire Wywfh7;
+ wire Czwfh7;
+ wire Izwfh7;
+ wire Ozwfh7;
+ wire Uzwfh7;
+ wire A0xfh7;
+ wire G0xfh7;
+ wire M0xfh7;
+ wire S0xfh7;
+ wire Y0xfh7;
+ wire E1xfh7;
+ wire K1xfh7;
+ wire Q1xfh7;
+ wire W1xfh7;
+ wire C2xfh7;
+ wire I2xfh7;
+ wire O2xfh7;
+ wire U2xfh7;
+ wire A3xfh7;
+ wire G3xfh7;
+ wire M3xfh7;
+ wire S3xfh7;
+ wire Y3xfh7;
+ wire E4xfh7;
+ wire K4xfh7;
+ wire Q4xfh7;
+ wire W4xfh7;
+ wire C5xfh7;
+ wire I5xfh7;
+ wire O5xfh7;
+ wire U5xfh7;
+ wire A6xfh7;
+ wire G6xfh7;
+ wire M6xfh7;
+ wire S6xfh7;
+ wire Y6xfh7;
+ wire E7xfh7;
+ wire K7xfh7;
+ wire Q7xfh7;
+ wire W7xfh7;
+ wire C8xfh7;
+ wire I8xfh7;
+ wire O8xfh7;
+ wire U8xfh7;
+ wire A9xfh7;
+ wire G9xfh7;
+ wire M9xfh7;
+ wire S9xfh7;
+ wire Y9xfh7;
+ wire Eaxfh7;
+ wire Kaxfh7;
+ wire Qaxfh7;
+ wire Waxfh7;
+ wire Cbxfh7;
+ wire Ibxfh7;
+ wire Obxfh7;
+ wire Ubxfh7;
+ wire Acxfh7;
+ wire Gcxfh7;
+ wire Mcxfh7;
+ wire Scxfh7;
+ wire Ycxfh7;
+ wire Edxfh7;
+ wire Kdxfh7;
+ wire Qdxfh7;
+ wire Wdxfh7;
+ wire Cexfh7;
+ wire Iexfh7;
+ wire Oexfh7;
+ wire Uexfh7;
+ wire Afxfh7;
+ wire Gfxfh7;
+ wire Mfxfh7;
+ wire Sfxfh7;
+ wire Yfxfh7;
+ wire Egxfh7;
+ wire Kgxfh7;
+ wire Qgxfh7;
+ wire Wgxfh7;
+ wire Chxfh7;
+ wire Ihxfh7;
+ wire Ohxfh7;
+ wire Uhxfh7;
+ wire Aixfh7;
+ wire Gixfh7;
+ wire Mixfh7;
+ wire Sixfh7;
+ wire Yixfh7;
+ wire Ejxfh7;
+ wire Kjxfh7;
+ wire Qjxfh7;
+ wire Wjxfh7;
+ wire Ckxfh7;
+ wire Ikxfh7;
+ wire Okxfh7;
+ wire Ukxfh7;
+ wire Alxfh7;
+ wire Glxfh7;
+ wire Mlxfh7;
+ wire Slxfh7;
+ wire Ylxfh7;
+ wire Emxfh7;
+ wire Kmxfh7;
+ wire Qmxfh7;
+ wire Wmxfh7;
+ wire Cnxfh7;
+ wire Inxfh7;
+ wire Onxfh7;
+ wire Unxfh7;
+ wire Aoxfh7;
+ wire Goxfh7;
+ wire Moxfh7;
+ wire Soxfh7;
+ wire Yoxfh7;
+ wire Epxfh7;
+ wire Kpxfh7;
+ wire Qpxfh7;
+ wire Wpxfh7;
+ wire Cqxfh7;
+ wire Iqxfh7;
+ wire Oqxfh7;
+ wire Uqxfh7;
+ wire Arxfh7;
+ wire Grxfh7;
+ wire Mrxfh7;
+ wire Srxfh7;
+ wire Yrxfh7;
+ wire Esxfh7;
+ wire Ksxfh7;
+ wire Qsxfh7;
+ wire Wsxfh7;
+ wire Ctxfh7;
+ wire Itxfh7;
+ wire Otxfh7;
+ wire Utxfh7;
+ wire Auxfh7;
+ wire Guxfh7;
+ wire Muxfh7;
+ wire Suxfh7;
+ wire Yuxfh7;
+ wire Evxfh7;
+ wire Kvxfh7;
+ wire Qvxfh7;
+ wire Wvxfh7;
+ wire Cwxfh7;
+ wire Iwxfh7;
+ wire Owxfh7;
+ wire Uwxfh7;
+ wire Axxfh7;
+ wire Gxxfh7;
+ wire Mxxfh7;
+ wire Sxxfh7;
+ wire Yxxfh7;
+ wire Eyxfh7;
+ wire Kyxfh7;
+ wire Qyxfh7;
+ wire Wyxfh7;
+ wire Czxfh7;
+ wire Izxfh7;
+ wire Ozxfh7;
+ wire Uzxfh7;
+ wire A0yfh7;
+ wire G0yfh7;
+ wire M0yfh7;
+ wire S0yfh7;
+ wire Y0yfh7;
+ wire E1yfh7;
+ wire K1yfh7;
+ wire Q1yfh7;
+ wire W1yfh7;
+ wire C2yfh7;
+ wire I2yfh7;
+ wire O2yfh7;
+ wire U2yfh7;
+ wire A3yfh7;
+ wire G3yfh7;
+ wire M3yfh7;
+ wire S3yfh7;
+ wire Y3yfh7;
+ wire E4yfh7;
+ wire K4yfh7;
+ wire Q4yfh7;
+ wire W4yfh7;
+ wire C5yfh7;
+ wire I5yfh7;
+ wire O5yfh7;
+ wire U5yfh7;
+ wire A6yfh7;
+ wire G6yfh7;
+ wire M6yfh7;
+ wire S6yfh7;
+ wire Y6yfh7;
+ wire E7yfh7;
+ wire K7yfh7;
+ wire Q7yfh7;
+ wire W7yfh7;
+ wire C8yfh7;
+ wire I8yfh7;
+ wire O8yfh7;
+ wire U8yfh7;
+ wire A9yfh7;
+ wire G9yfh7;
+ wire M9yfh7;
+ wire S9yfh7;
+ wire Y9yfh7;
+ wire Eayfh7;
+ wire Kayfh7;
+ wire Qayfh7;
+ wire Wayfh7;
+ wire Cbyfh7;
+ wire Ibyfh7;
+ wire Obyfh7;
+ wire Ubyfh7;
+ wire Acyfh7;
+ wire Gcyfh7;
+ wire Mcyfh7;
+ wire Scyfh7;
+ wire Ycyfh7;
+ wire Edyfh7;
+ wire Kdyfh7;
+ wire Qdyfh7;
+ wire Wdyfh7;
+ wire Ceyfh7;
+ wire Ieyfh7;
+ wire Oeyfh7;
+ wire Ueyfh7;
+ wire Afyfh7;
+ wire Gfyfh7;
+ wire Mfyfh7;
+ wire Sfyfh7;
+ wire Yfyfh7;
+ wire Egyfh7;
+ wire Kgyfh7;
+ wire Qgyfh7;
+ wire Wgyfh7;
+ wire Chyfh7;
+ wire Ihyfh7;
+ wire Ohyfh7;
+ wire Uhyfh7;
+ wire Aiyfh7;
+ wire Giyfh7;
+ wire Miyfh7;
+ wire Siyfh7;
+ wire Yiyfh7;
+ wire Ejyfh7;
+ wire Kjyfh7;
+ wire Qjyfh7;
+ wire Wjyfh7;
+ wire Ckyfh7;
+ wire Ikyfh7;
+ wire Okyfh7;
+ wire Ukyfh7;
+ wire Alyfh7;
+ wire Glyfh7;
+ wire Mlyfh7;
+ wire Slyfh7;
+ wire Ylyfh7;
+ wire Emyfh7;
+ wire Kmyfh7;
+ wire Qmyfh7;
+ wire Wmyfh7;
+ wire Cnyfh7;
+ wire Inyfh7;
+ wire Onyfh7;
+ wire Unyfh7;
+ wire Aoyfh7;
+ wire Goyfh7;
+ wire Moyfh7;
+ wire Soyfh7;
+ wire Yoyfh7;
+ wire Epyfh7;
+ wire Kpyfh7;
+ wire Qpyfh7;
+ wire Wpyfh7;
+ wire Cqyfh7;
+ wire Iqyfh7;
+ wire Oqyfh7;
+ wire Uqyfh7;
+ wire Aryfh7;
+ wire Gryfh7;
+ wire Mryfh7;
+ wire Sryfh7;
+ wire Yryfh7;
+ wire Esyfh7;
+ wire Ksyfh7;
+ wire Qsyfh7;
+ wire Wsyfh7;
+ wire Ctyfh7;
+ wire Ityfh7;
+ wire Otyfh7;
+ wire Utyfh7;
+ wire Auyfh7;
+ wire Guyfh7;
+ wire Muyfh7;
+ wire Suyfh7;
+ wire Yuyfh7;
+ wire Evyfh7;
+ wire Kvyfh7;
+ wire Qvyfh7;
+ wire Wvyfh7;
+ wire Cwyfh7;
+ wire Iwyfh7;
+ wire Owyfh7;
+ wire Uwyfh7;
+ wire Axyfh7;
+ wire Gxyfh7;
+ wire Mxyfh7;
+ wire Sxyfh7;
+ wire Yxyfh7;
+ wire Eyyfh7;
+ wire Kyyfh7;
+ wire Qyyfh7;
+ wire Wyyfh7;
+ wire Czyfh7;
+ wire Izyfh7;
+ wire Ozyfh7;
+ wire Uzyfh7;
+ wire A0zfh7;
+ wire G0zfh7;
+ wire M0zfh7;
+ wire S0zfh7;
+ wire Y0zfh7;
+ wire E1zfh7;
+ wire K1zfh7;
+ wire Q1zfh7;
+ wire W1zfh7;
+ wire C2zfh7;
+ wire I2zfh7;
+ wire O2zfh7;
+ wire U2zfh7;
+ wire A3zfh7;
+ wire G3zfh7;
+ wire M3zfh7;
+ wire S3zfh7;
+ wire Y3zfh7;
+ wire E4zfh7;
+ wire K4zfh7;
+ wire Q4zfh7;
+ wire W4zfh7;
+ wire C5zfh7;
+ wire I5zfh7;
+ wire O5zfh7;
+ wire U5zfh7;
+ wire A6zfh7;
+ wire G6zfh7;
+ wire M6zfh7;
+ wire S6zfh7;
+ wire Y6zfh7;
+ wire E7zfh7;
+ wire K7zfh7;
+ wire Q7zfh7;
+ wire W7zfh7;
+ wire C8zfh7;
+ wire I8zfh7;
+ wire O8zfh7;
+ wire U8zfh7;
+ wire A9zfh7;
+ wire G9zfh7;
+ wire M9zfh7;
+ wire S9zfh7;
+ wire Y9zfh7;
+ wire Eazfh7;
+ wire Kazfh7;
+ wire Qazfh7;
+ wire Wazfh7;
+ wire Cbzfh7;
+ wire Ibzfh7;
+ wire Obzfh7;
+ wire Ubzfh7;
+ wire Aczfh7;
+ wire Gczfh7;
+ wire Mczfh7;
+ wire Sczfh7;
+ wire Yczfh7;
+ wire Edzfh7;
+ wire Kdzfh7;
+ wire Qdzfh7;
+ wire Wdzfh7;
+ wire Cezfh7;
+ wire Iezfh7;
+ wire Oezfh7;
+ wire Uezfh7;
+ wire Afzfh7;
+ wire Gfzfh7;
+ wire Mfzfh7;
+ wire Sfzfh7;
+ wire Yfzfh7;
+ wire Egzfh7;
+ wire Kgzfh7;
+ wire Qgzfh7;
+ wire Wgzfh7;
+ wire Chzfh7;
+ wire Ihzfh7;
+ wire Ohzfh7;
+ wire Uhzfh7;
+ wire Aizfh7;
+ wire Gizfh7;
+ wire Mizfh7;
+ wire Sizfh7;
+ wire Yizfh7;
+ wire Ejzfh7;
+ wire Kjzfh7;
+ wire Qjzfh7;
+ wire Wjzfh7;
+ wire Ckzfh7;
+ wire Ikzfh7;
+ wire Okzfh7;
+ wire Ukzfh7;
+ wire Alzfh7;
+ wire Glzfh7;
+ wire Mlzfh7;
+ wire Slzfh7;
+ wire Ylzfh7;
+ wire Emzfh7;
+ wire Kmzfh7;
+ wire Qmzfh7;
+ wire Wmzfh7;
+ wire Cnzfh7;
+ wire Inzfh7;
+ wire Onzfh7;
+ wire Unzfh7;
+ wire Aozfh7;
+ wire Gozfh7;
+ wire Mozfh7;
+ wire Sozfh7;
+ wire Yozfh7;
+ wire Epzfh7;
+ wire Kpzfh7;
+ wire Qpzfh7;
+ wire Wpzfh7;
+ wire Cqzfh7;
+ wire Iqzfh7;
+ wire Oqzfh7;
+ wire Uqzfh7;
+ wire Arzfh7;
+ wire Grzfh7;
+ wire Mrzfh7;
+ wire Srzfh7;
+ wire Yrzfh7;
+ wire Eszfh7;
+ wire Kszfh7;
+ wire Qszfh7;
+ wire Wszfh7;
+ wire Ctzfh7;
+ wire Itzfh7;
+ wire Otzfh7;
+ wire Utzfh7;
+ wire Auzfh7;
+ wire Guzfh7;
+ wire Muzfh7;
+ wire Suzfh7;
+ wire Yuzfh7;
+ wire Evzfh7;
+ wire Kvzfh7;
+ wire Qvzfh7;
+ wire Wvzfh7;
+ wire Cwzfh7;
+ wire Iwzfh7;
+ wire Owzfh7;
+ wire Uwzfh7;
+ wire Axzfh7;
+ wire Gxzfh7;
+ wire Mxzfh7;
+ wire Sxzfh7;
+ wire Yxzfh7;
+ wire Eyzfh7;
+ wire Kyzfh7;
+ wire Qyzfh7;
+ wire Wyzfh7;
+ wire Czzfh7;
+ wire Izzfh7;
+ wire Ozzfh7;
+ wire Uzzfh7;
+ wire A00gh7;
+ wire G00gh7;
+ wire M00gh7;
+ wire S00gh7;
+ wire Y00gh7;
+ wire E10gh7;
+ wire K10gh7;
+ wire Q10gh7;
+ wire W10gh7;
+ wire C20gh7;
+ wire I20gh7;
+ wire O20gh7;
+ wire U20gh7;
+ wire A30gh7;
+ wire G30gh7;
+ wire M30gh7;
+ wire S30gh7;
+ wire Y30gh7;
+ wire E40gh7;
+ wire K40gh7;
+ wire Q40gh7;
+ wire W40gh7;
+ wire C50gh7;
+ wire I50gh7;
+ wire O50gh7;
+ wire U50gh7;
+ wire A60gh7;
+ wire G60gh7;
+ wire M60gh7;
+ wire S60gh7;
+ wire Y60gh7;
+ wire E70gh7;
+ wire K70gh7;
+ wire Q70gh7;
+ wire W70gh7;
+ wire C80gh7;
+ wire I80gh7;
+ wire O80gh7;
+ wire U80gh7;
+ wire A90gh7;
+ wire G90gh7;
+ wire M90gh7;
+ wire S90gh7;
+ wire Y90gh7;
+ wire Ea0gh7;
+ wire Ka0gh7;
+ wire Qa0gh7;
+ wire Wa0gh7;
+ wire Cb0gh7;
+ wire Ib0gh7;
+ wire Ob0gh7;
+ wire Ub0gh7;
+ wire Ac0gh7;
+ wire Gc0gh7;
+ wire Mc0gh7;
+ wire Sc0gh7;
+ wire Yc0gh7;
+ wire Ed0gh7;
+ wire Kd0gh7;
+ wire Qd0gh7;
+ wire Wd0gh7;
+ wire Ce0gh7;
+ wire Ie0gh7;
+ wire Oe0gh7;
+ wire Ue0gh7;
+ wire Af0gh7;
+ wire Gf0gh7;
+ wire Mf0gh7;
+ wire Sf0gh7;
+ wire Yf0gh7;
+ wire Eg0gh7;
+ wire Kg0gh7;
+ wire Qg0gh7;
+ wire Wg0gh7;
+ wire Ch0gh7;
+ wire Ih0gh7;
+ wire Oh0gh7;
+ wire Uh0gh7;
+ wire Ai0gh7;
+ wire Gi0gh7;
+ wire Mi0gh7;
+ wire Si0gh7;
+ wire Yi0gh7;
+ wire Ej0gh7;
+ wire Kj0gh7;
+ wire Qj0gh7;
+ wire Wj0gh7;
+ wire Ck0gh7;
+ wire Ik0gh7;
+ wire Ok0gh7;
+ wire Uk0gh7;
+ wire Al0gh7;
+ wire Gl0gh7;
+ wire Ml0gh7;
+ wire Sl0gh7;
+ wire Yl0gh7;
+ wire Em0gh7;
+ wire Km0gh7;
+ wire Qm0gh7;
+ wire Wm0gh7;
+ wire Cn0gh7;
+ wire In0gh7;
+ wire On0gh7;
+ wire Un0gh7;
+ wire Ao0gh7;
+ wire Go0gh7;
+ wire Mo0gh7;
+ wire So0gh7;
+ wire Yo0gh7;
+ wire Ep0gh7;
+ wire Kp0gh7;
+ wire Qp0gh7;
+ wire Wp0gh7;
+ wire Cq0gh7;
+ wire Iq0gh7;
+ wire Oq0gh7;
+ wire Uq0gh7;
+ wire Ar0gh7;
+ wire Gr0gh7;
+ wire Mr0gh7;
+ wire Sr0gh7;
+ wire Yr0gh7;
+ wire Es0gh7;
+ wire Ks0gh7;
+ wire Qs0gh7;
+ wire Ws0gh7;
+ wire Ct0gh7;
+ wire It0gh7;
+ wire Ot0gh7;
+ wire Ut0gh7;
+ wire Au0gh7;
+ wire Gu0gh7;
+ wire Mu0gh7;
+ wire Su0gh7;
+ wire Yu0gh7;
+ wire Ev0gh7;
+ wire Kv0gh7;
+ wire Qv0gh7;
+ wire Wv0gh7;
+ wire Cw0gh7;
+ wire Iw0gh7;
+ wire Ow0gh7;
+ wire Uw0gh7;
+ wire Ax0gh7;
+ wire Gx0gh7;
+ wire Mx0gh7;
+ wire Sx0gh7;
+ wire Yx0gh7;
+ wire Ey0gh7;
+ wire Ky0gh7;
+ wire Qy0gh7;
+ wire Wy0gh7;
+ wire Cz0gh7;
+ wire Iz0gh7;
+ wire Oz0gh7;
+ wire Uz0gh7;
+ wire A01gh7;
+ wire G01gh7;
+ wire M01gh7;
+ wire S01gh7;
+ wire Y01gh7;
+ wire E11gh7;
+ wire K11gh7;
+ wire Q11gh7;
+ wire W11gh7;
+ wire C21gh7;
+ wire I21gh7;
+ wire O21gh7;
+ wire U21gh7;
+ wire A31gh7;
+ wire G31gh7;
+ wire M31gh7;
+ wire S31gh7;
+ wire Y31gh7;
+ wire E41gh7;
+ wire K41gh7;
+ wire Q41gh7;
+ wire W41gh7;
+ wire C51gh7;
+ wire I51gh7;
+ wire O51gh7;
+ wire U51gh7;
+ wire A61gh7;
+ wire G61gh7;
+ wire M61gh7;
+ wire S61gh7;
+ wire Y61gh7;
+ wire E71gh7;
+ wire K71gh7;
+ wire Q71gh7;
+ wire W71gh7;
+ wire C81gh7;
+ wire I81gh7;
+ wire O81gh7;
+ wire U81gh7;
+ wire A91gh7;
+ wire G91gh7;
+ wire M91gh7;
+ wire S91gh7;
+ wire Y91gh7;
+ wire Ea1gh7;
+ wire Ka1gh7;
+ wire Qa1gh7;
+ wire Wa1gh7;
+ wire Cb1gh7;
+ wire Ib1gh7;
+ wire Ob1gh7;
+ wire Ub1gh7;
+ wire Ac1gh7;
+ wire Gc1gh7;
+ wire Mc1gh7;
+ wire Sc1gh7;
+ wire Yc1gh7;
+ wire Ed1gh7;
+ wire Kd1gh7;
+ wire Qd1gh7;
+ wire Wd1gh7;
+ wire Ce1gh7;
+ wire Ie1gh7;
+ wire Oe1gh7;
+ wire Ue1gh7;
+ wire Af1gh7;
+ wire Gf1gh7;
+ wire Mf1gh7;
+ wire Sf1gh7;
+ wire Yf1gh7;
+ wire Eg1gh7;
+ wire Kg1gh7;
+ wire Qg1gh7;
+ wire Wg1gh7;
+ wire Ch1gh7;
+ wire Ih1gh7;
+ wire Oh1gh7;
+ wire Uh1gh7;
+ wire Ai1gh7;
+ wire Gi1gh7;
+ wire Mi1gh7;
+ wire Si1gh7;
+ wire Yi1gh7;
+ wire Ej1gh7;
+ wire Kj1gh7;
+ wire Qj1gh7;
+ wire Wj1gh7;
+ wire Ck1gh7;
+ wire Ik1gh7;
+ wire Ok1gh7;
+ wire Uk1gh7;
+ wire Al1gh7;
+ wire Gl1gh7;
+ wire Ml1gh7;
+ wire Sl1gh7;
+ wire Yl1gh7;
+ wire Em1gh7;
+ wire Km1gh7;
+ wire Qm1gh7;
+ wire Wm1gh7;
+ wire Cn1gh7;
+ wire In1gh7;
+ wire On1gh7;
+ wire Un1gh7;
+ wire Ao1gh7;
+ wire Go1gh7;
+ wire Mo1gh7;
+ wire So1gh7;
+ wire Yo1gh7;
+ wire Ep1gh7;
+ wire Kp1gh7;
+ wire Qp1gh7;
+ wire Wp1gh7;
+ wire Cq1gh7;
+ wire Iq1gh7;
+ wire Oq1gh7;
+ wire Uq1gh7;
+ wire Ar1gh7;
+ wire Gr1gh7;
+ wire Mr1gh7;
+ wire Sr1gh7;
+ wire Yr1gh7;
+ wire Es1gh7;
+ wire Ks1gh7;
+ wire Qs1gh7;
+ wire Ws1gh7;
+ wire Ct1gh7;
+ wire It1gh7;
+ wire Ot1gh7;
+ wire Ut1gh7;
+ wire Au1gh7;
+ wire Gu1gh7;
+ wire Mu1gh7;
+ wire Su1gh7;
+ wire Yu1gh7;
+ wire Ev1gh7;
+ wire Kv1gh7;
+ wire Qv1gh7;
+ wire Wv1gh7;
+ wire Cw1gh7;
+ wire Iw1gh7;
+ wire Ow1gh7;
+ wire Uw1gh7;
+ wire Ax1gh7;
+ wire Gx1gh7;
+ wire Mx1gh7;
+ wire Sx1gh7;
+ wire Yx1gh7;
+ wire Ey1gh7;
+ wire Ky1gh7;
+ wire Qy1gh7;
+ wire Wy1gh7;
+ wire Cz1gh7;
+ wire Iz1gh7;
+ wire Oz1gh7;
+ wire Uz1gh7;
+ wire A02gh7;
+ wire G02gh7;
+ wire M02gh7;
+ wire S02gh7;
+ wire Y02gh7;
+ wire E12gh7;
+ wire K12gh7;
+ wire Q12gh7;
+ wire W12gh7;
+ wire C22gh7;
+ wire I22gh7;
+ wire O22gh7;
+ wire U22gh7;
+ wire A32gh7;
+ wire G32gh7;
+ wire M32gh7;
+ wire S32gh7;
+ wire Y32gh7;
+ wire E42gh7;
+ wire K42gh7;
+ wire Q42gh7;
+ wire W42gh7;
+ wire C52gh7;
+ wire I52gh7;
+ wire O52gh7;
+ wire U52gh7;
+ wire A62gh7;
+ wire G62gh7;
+ wire M62gh7;
+ wire S62gh7;
+ wire Y62gh7;
+ wire E72gh7;
+ wire K72gh7;
+ wire Q72gh7;
+ wire W72gh7;
+ wire C82gh7;
+ wire I82gh7;
+ wire O82gh7;
+ wire U82gh7;
+ wire A92gh7;
+ wire G92gh7;
+ reg M92gh7;
+ reg Ma2gh7;
+ reg Pb2gh7;
+ reg Sc2gh7;
+ reg Ud2gh7;
+ reg Ue2gh7;
+ reg Xf2gh7;
+ reg Xg2gh7;
+ reg Ai2gh7;
+ reg Dj2gh7;
+ reg Fk2gh7;
+ reg Hl2gh7;
+ reg Jm2gh7;
+ reg Ln2gh7;
+ reg Oo2gh7;
+ reg Rp2gh7;
+ reg Rq2gh7;
+ reg Rr2gh7;
+ reg Rs2gh7;
+ reg Rt2gh7;
+ reg Ru2gh7;
+ reg Rv2gh7;
+ reg Rw2gh7;
+ reg Rx2gh7;
+ reg Uy2gh7;
+ reg Xz2gh7;
+ reg A13gh7;
+ reg D23gh7;
+ reg F33gh7;
+ reg H43gh7;
+ reg J53gh7;
+ reg L63gh7;
+ reg O73gh7;
+ reg R83gh7;
+ reg U93gh7;
+ reg Xa3gh7;
+ reg Ac3gh7;
+ reg Wc3gh7;
+ reg Zd3gh7;
+ reg Cf3gh7;
+ reg Fg3gh7;
+ reg Ih3gh7;
+ reg Li3gh7;
+ reg Oj3gh7;
+ reg Rk3gh7;
+ reg Tl3gh7;
+ reg Wm3gh7;
+ reg Zn3gh7;
+ reg Cp3gh7;
+ reg Dq3gh7;
+ reg Fr3gh7;
+ reg Is3gh7;
+ reg Lt3gh7;
+ reg Lu3gh7;
+ reg Pv3gh7;
+ reg Tw3gh7;
+ reg Ux3gh7;
+ reg Wy3gh7;
+ reg Yz3gh7;
+ reg A14gh7;
+ reg D24gh7;
+ reg G34gh7;
+ reg J44gh7;
+ reg M54gh7;
+ reg P64gh7;
+ reg R74gh7;
+ reg T84gh7;
+ reg W94gh7;
+ reg Ya4gh7;
+ reg Ac4gh7;
+ reg Cd4gh7;
+ reg Ee4gh7;
+ reg Ff4gh7;
+ reg Gg4gh7;
+ reg Ih4gh7;
+ reg Ji4gh7;
+ reg Nj4gh7;
+ reg Sk4gh7;
+ reg Ul4gh7;
+ reg Vm4gh7;
+ reg Xn4gh7;
+ reg Yo4gh7;
+ reg Bq4gh7;
+ reg Dr4gh7;
+ reg Gs4gh7;
+ reg It4gh7;
+ reg Lu4gh7;
+ reg Nv4gh7;
+ reg Qw4gh7;
+ reg Sx4gh7;
+ reg Vy4gh7;
+ reg Xz4gh7;
+ reg D15gh7;
+ reg J25gh7;
+ reg P35gh7;
+ reg U45gh7;
+ reg Y55gh7;
+ reg D75gh7;
+ reg F85gh7;
+ reg G95gh7;
+ reg Ia5gh7;
+ reg Jb5gh7;
+ reg Mc5gh7;
+ reg Od5gh7;
+ reg Re5gh7;
+ reg Tf5gh7;
+ reg Wg5gh7;
+ reg Yh5gh7;
+ reg Bj5gh7;
+ reg Dk5gh7;
+ reg Gl5gh7;
+ reg Im5gh7;
+ reg On5gh7;
+ reg Uo5gh7;
+ reg Aq5gh7;
+ reg Er5gh7;
+ reg Js5gh7;
+ reg Nt5gh7;
+ reg Su5gh7;
+ reg Uv5gh7;
+ reg Vw5gh7;
+ reg Xx5gh7;
+ reg Yy5gh7;
+ reg B06gh7;
+ reg D16gh7;
+ reg G26gh7;
+ reg I36gh7;
+ reg L46gh7;
+ reg N56gh7;
+ reg Q66gh7;
+ reg S76gh7;
+ reg V86gh7;
+ reg X96gh7;
+ reg Ab6gh7;
+ reg Cc6gh7;
+ reg Id6gh7;
+ reg Oe6gh7;
+ reg Uf6gh7;
+ reg Ah6gh7;
+ reg Ei6gh7;
+ reg Jj6gh7;
+ reg Nk6gh7;
+ reg Sl6gh7;
+ reg Ym6gh7;
+ reg Eo6gh7;
+ reg Kp6gh7;
+ reg Qq6gh7;
+ reg Vr6gh7;
+ reg Vs6gh7;
+ reg Bu6gh7;
+ reg Bv6gh7;
+ reg Hw6gh7;
+ reg Hx6gh7;
+ reg Ny6gh7;
+ reg Nz6gh7;
+ reg T07gh7;
+ reg T17gh7;
+ reg Z27gh7;
+ reg Z37gh7;
+ reg F57gh7;
+ reg J67gh7;
+ reg N77gh7;
+ reg N87gh7;
+ reg T97gh7;
+ reg Ya7gh7;
+ reg Cc7gh7;
+ reg Cd7gh7;
+ reg Ie7gh7;
+ reg Nf7gh7;
+ reg Rg7gh7;
+ reg Vh7gh7;
+ reg Zi7gh7;
+ reg Dk7gh7;
+ wire [33:0] Hl7gh7;
+
+ assign ahb_hburst[2] = 1'b0;
+ assign ahb_hburst[1] = 1'b0;
+ assign ahb_hmastlock = 1'b0;
+ assign ahb_hprot[3] = 1'b0;
+ assign ahb_hprot[2] = 1'b0;
+ assign ahb_hsize[2] = 1'b0;
+ assign ahb_hsize[0] = 1'b0;
+ assign ahb_htrans[0] = 1'b0;
+ assign ahb_hburst[0] = 1'b1;
+ assign ahb_hprot[1] = 1'b1;
+ assign ahb_hprot[0] = 1'b1;
+ assign ahb_hsize[1] = 1'b1;
+ assign G92gh7 = (!M92gh7);
+ assign A92gh7 = (!Ma2gh7);
+ assign U82gh7 = (!Pb2gh7);
+ assign M62gh7 = (!Sc2gh7);
+ assign stdio_rx_tready = Ud2gh7;
+ assign O82gh7 = (!Ue2gh7);
+ assign com_tx_tvalid = Xf2gh7;
+ assign M32gh7 = (!Xg2gh7);
+ assign S32gh7 = (!Ai2gh7);
+ assign I22gh7 = (!Dj2gh7);
+ assign Y02gh7 = (!Fk2gh7);
+ assign I82gh7 = (!Hl2gh7);
+ assign M02gh7 = (!Jm2gh7);
+ assign A62gh7 = (!Ln2gh7);
+ assign A02gh7 = (!Oo2gh7);
+ assign com_rx_tready = Rp2gh7;
+ assign Iz1gh7 = (!Rq2gh7);
+ assign Uz1gh7 = (!Rr2gh7);
+ assign Oz1gh7 = (!Rs2gh7);
+ assign Cz1gh7 = (!Rt2gh7);
+ assign Wy1gh7 = (!Ru2gh7);
+ assign C82gh7 = (!Rv2gh7);
+ assign Qy1gh7 = (!Rw2gh7);
+ assign I52gh7 = (!Rx2gh7);
+ assign G02gh7 = (!Uy2gh7);
+ assign Y32gh7 = (!Xz2gh7);
+ assign Q42gh7 = (!A13gh7);
+ assign W12gh7 = (!D23gh7);
+ assign Q12gh7 = (!F33gh7);
+ assign E12gh7 = (!H43gh7);
+ assign U22gh7 = (!J53gh7);
+ assign G62gh7 = (!L63gh7);
+ assign C22gh7 = (!O73gh7);
+ assign G32gh7 = (!R83gh7);
+ assign A32gh7 = (!U93gh7);
+ assign K42gh7 = (!Xa3gh7);
+ assign W72gh7 = (!Ac3gh7);
+ assign S62gh7 = (!Wc3gh7);
+ assign W42gh7 = (!Zd3gh7);
+ assign O52gh7 = (!Cf3gh7);
+ assign U52gh7 = (!Fg3gh7);
+ assign E72gh7 = (!Ih3gh7);
+ assign Q72gh7 = Li3gh7;
+ assign S02gh7 = (!Oj3gh7);
+ assign K12gh7 = (!Rk3gh7);
+ assign C52gh7 = (!Tl3gh7);
+ assign Y62gh7 = (!Wm3gh7);
+ assign ahb_hwrite = Zn3gh7;
+ assign K72gh7 = (!Cp3gh7);
+ assign Yvrfh7 = Dq3gh7;
+ assign E42gh7 = (!Fr3gh7);
+ assign O22gh7 = (!Is3gh7);
+ assign stdio_tx_tvalid = Lt3gh7;
+ assign com_tx_tdata[7] = Lu3gh7;
+ assign com_tx_tdata[5] = Pv3gh7;
+ assign Yzrfh7 = (!Pv3gh7);
+ assign ahb_haddr[0] = Tw3gh7;
+ assign Gr1gh7 = (!Ux3gh7);
+ assign Es1gh7 = (!Wy3gh7);
+ assign Ct1gh7 = (!Yz3gh7);
+ assign Au1gh7 = (!A14gh7);
+ assign Ky1gh7 = (!D24gh7);
+ assign Mx1gh7 = (!G34gh7);
+ assign Iw1gh7 = (!J44gh7);
+ assign Ow1gh7 = (!M54gh7);
+ assign ahb_haddr[28] = P64gh7;
+ assign ahb_haddr[31] = R74gh7;
+ assign Ev1gh7 = (!T84gh7);
+ assign ahb_haddr[24] = W94gh7;
+ assign ahb_haddr[20] = Ya4gh7;
+ assign ahb_haddr[16] = Ac4gh7;
+ assign ahb_haddr[12] = Cd4gh7;
+ assign ahb_haddr[8] = Ee4gh7;
+ assign ahb_haddr[4] = Ff4gh7;
+ assign Mr1gh7 = (!Gg4gh7);
+ assign ahb_haddr[1] = Ih4gh7;
+ assign stdio_tx_tdata[1] = Ji4gh7;
+ assign ahb_hwdata[1] = Nj4gh7;
+ assign X0sfh7 = (!Nj4gh7);
+ assign Ks1gh7 = (!Sk4gh7);
+ assign ahb_haddr[5] = Ul4gh7;
+ assign It1gh7 = (!Vm4gh7);
+ assign ahb_haddr[9] = Xn4gh7;
+ assign Gu1gh7 = (!Yo4gh7);
+ assign ahb_haddr[13] = Bq4gh7;
+ assign Ey1gh7 = (!Dr4gh7);
+ assign ahb_haddr[17] = Gs4gh7;
+ assign Gx1gh7 = (!It4gh7);
+ assign ahb_haddr[21] = Lu4gh7;
+ assign Wv1gh7 = (!Nv4gh7);
+ assign ahb_haddr[25] = Qw4gh7;
+ assign Cw1gh7 = (!Sx4gh7);
+ assign ahb_haddr[29] = Vy4gh7;
+ assign ahb_hwdata[29] = Xz4gh7;
+ assign X5sfh7 = (!Xz4gh7);
+ assign ahb_hwdata[25] = D15gh7;
+ assign D5sfh7 = (!D15gh7);
+ assign ahb_hwdata[13] = J25gh7;
+ assign V2sfh7 = (!J25gh7);
+ assign ahb_hwdata[9] = P35gh7;
+ assign G2sfh7 = (!P35gh7);
+ assign stdio_tx_tdata[5] = U45gh7;
+ assign ahb_hwdata[5] = Y55gh7;
+ assign R1sfh7 = (!Y55gh7);
+ assign Yr1gh7 = (!D75gh7);
+ assign ahb_haddr[3] = F85gh7;
+ assign Ws1gh7 = (!G95gh7);
+ assign ahb_haddr[7] = Ia5gh7;
+ assign Ut1gh7 = (!Jb5gh7);
+ assign ahb_haddr[11] = Mc5gh7;
+ assign Su1gh7 = (!Od5gh7);
+ assign ahb_haddr[15] = Re5gh7;
+ assign Sx1gh7 = (!Tf5gh7);
+ assign ahb_haddr[19] = Wg5gh7;
+ assign Uw1gh7 = (!Yh5gh7);
+ assign ahb_haddr[23] = Bj5gh7;
+ assign Yu1gh7 = (!Dk5gh7);
+ assign ahb_haddr[27] = Gl5gh7;
+ assign ahb_hwdata[27] = Im5gh7;
+ assign N5sfh7 = (!Im5gh7);
+ assign ahb_hwdata[15] = On5gh7;
+ assign F3sfh7 = (!On5gh7);
+ assign ahb_hwdata[11] = Uo5gh7;
+ assign Q2sfh7 = (!Uo5gh7);
+ assign stdio_tx_tdata[7] = Aq5gh7;
+ assign ahb_hwdata[7] = Er5gh7;
+ assign W1sfh7 = (!Er5gh7);
+ assign stdio_tx_tdata[3] = Js5gh7;
+ assign ahb_hwdata[3] = Nt5gh7;
+ assign H1sfh7 = (!Nt5gh7);
+ assign Sr1gh7 = (!Su5gh7);
+ assign ahb_haddr[2] = Uv5gh7;
+ assign Qs1gh7 = (!Vw5gh7);
+ assign ahb_haddr[6] = Xx5gh7;
+ assign Ot1gh7 = (!Yy5gh7);
+ assign ahb_haddr[10] = B06gh7;
+ assign Mu1gh7 = (!D16gh7);
+ assign ahb_haddr[14] = G26gh7;
+ assign Yx1gh7 = (!I36gh7);
+ assign ahb_haddr[18] = L46gh7;
+ assign Ax1gh7 = (!N56gh7);
+ assign ahb_haddr[22] = Q66gh7;
+ assign Kv1gh7 = (!S76gh7);
+ assign ahb_haddr[26] = V86gh7;
+ assign Qv1gh7 = (!X96gh7);
+ assign ahb_haddr[30] = Ab6gh7;
+ assign ahb_hwdata[30] = Cc6gh7;
+ assign C6sfh7 = (!Cc6gh7);
+ assign ahb_hwdata[26] = Id6gh7;
+ assign I5sfh7 = (!Id6gh7);
+ assign ahb_hwdata[14] = Oe6gh7;
+ assign A3sfh7 = (!Oe6gh7);
+ assign ahb_hwdata[10] = Uf6gh7;
+ assign L2sfh7 = (!Uf6gh7);
+ assign stdio_tx_tdata[6] = Ah6gh7;
+ assign ahb_hwdata[6] = Ei6gh7;
+ assign Ozrfh7 = (!Ei6gh7);
+ assign stdio_tx_tdata[2] = Jj6gh7;
+ assign ahb_hwdata[2] = Nk6gh7;
+ assign C1sfh7 = (!Nk6gh7);
+ assign ahb_hwdata[31] = Sl6gh7;
+ assign H6sfh7 = (!Sl6gh7);
+ assign ahb_hwdata[28] = Ym6gh7;
+ assign S5sfh7 = (!Ym6gh7);
+ assign ahb_hwdata[24] = Eo6gh7;
+ assign Y4sfh7 = (!Eo6gh7);
+ assign ahb_hwdata[12] = Kp6gh7;
+ assign Kyrfh7 = (!Kp6gh7);
+ assign ahb_hwdata[8] = Qq6gh7;
+ assign B2sfh7 = (!Qq6gh7);
+ assign gpo8[6] = Vr6gh7;
+ assign Ayrfh7 = (!Vr6gh7);
+ assign ahb_hwdata[22] = Vs6gh7;
+ assign O4sfh7 = (!Vs6gh7);
+ assign gpo8[5] = Bu6gh7;
+ assign Vxrfh7 = (!Bu6gh7);
+ assign ahb_hwdata[21] = Bv6gh7;
+ assign J4sfh7 = (!Bv6gh7);
+ assign gpo8[3] = Hw6gh7;
+ assign Lxrfh7 = (!Hw6gh7);
+ assign ahb_hwdata[19] = Hx6gh7;
+ assign Z3sfh7 = (!Hx6gh7);
+ assign gpo8[2] = Ny6gh7;
+ assign Gxrfh7 = (!Ny6gh7);
+ assign ahb_hwdata[18] = Nz6gh7;
+ assign U3sfh7 = (!Nz6gh7);
+ assign gpo8[1] = T07gh7;
+ assign Bxrfh7 = (!T07gh7);
+ assign ahb_hwdata[17] = T17gh7;
+ assign P3sfh7 = (!T17gh7);
+ assign gpo8[7] = Z27gh7;
+ assign Fyrfh7 = (!Z27gh7);
+ assign ahb_hwdata[23] = Z37gh7;
+ assign T4sfh7 = (!Z37gh7);
+ assign com_tx_tdata[4] = F57gh7;
+ assign Tzrfh7 = (!F57gh7);
+ assign stdio_tx_tdata[4] = J67gh7;
+ assign gpo8[4] = N77gh7;
+ assign Qxrfh7 = (!N77gh7);
+ assign ahb_hwdata[20] = N87gh7;
+ assign E4sfh7 = (!N87gh7);
+ assign ahb_hwdata[4] = T97gh7;
+ assign M1sfh7 = (!T97gh7);
+ assign stdio_tx_tdata[0] = Ya7gh7;
+ assign gpo8[0] = Cc7gh7;
+ assign Wwrfh7 = (!Cc7gh7);
+ assign ahb_hwdata[16] = Cd7gh7;
+ assign K3sfh7 = (!Cd7gh7);
+ assign ahb_hwdata[0] = Ie7gh7;
+ assign Pyrfh7 = (!Ie7gh7);
+ assign com_tx_tdata[2] = Nf7gh7;
+ assign Ezrfh7 = (!Nf7gh7);
+ assign com_tx_tdata[0] = Rg7gh7;
+ assign Uyrfh7 = (!Rg7gh7);
+ assign com_tx_tdata[1] = Vh7gh7;
+ assign Zyrfh7 = (!Vh7gh7);
+ assign com_tx_tdata[3] = Zi7gh7;
+ assign Jzrfh7 = (!Zi7gh7);
+ assign com_tx_tdata[6] = Dk7gh7;
+ assign D0sfh7 = (!Dk7gh7);
+ assign Hl7gh7 = ({ahb_haddr, 1'b0} + {{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 1'b0, Ivrfh7, 1'b0, 1'b0}, 1'b1});
+ assign {Qbrfh7, Gcrfh7, Wcrfh7, Mdrfh7, Cerfh7, Serfh7, Ifrfh7, Yfrfh7,
+ Ogrfh7, Ehrfh7, Uhrfh7, Kirfh7, Ajrfh7, Qjrfh7, Gkrfh7, Wkrfh7,
+ Mlrfh7, Cmrfh7, Smrfh7, Inrfh7, Ynrfh7, Oorfh7, Eprfh7, Uprfh7,
+ Kqrfh7, Arrfh7, Qrrfh7, Gsrfh7, Wsrfh7, Mtrfh7, Curfh7, Surfh7}
+ = Hl7gh7[33:1];
+ assign Wpsfh7 = (!Cqsfh7);
+ assign Cqsfh7 = (!ahb_hresetn);
+ assign Iqsfh7 = (!Oqsfh7);
+ assign Oqsfh7 = (!ahb_hclk);
+ assign Dksfh7 = (~(Uqsfh7 & Arsfh7));
+ assign Uqsfh7 = (Mrsfh7 ? Iz1gh7 : Grsfh7);
+ assign Yjsfh7 = (!Srsfh7);
+ assign Srsfh7 = (Mrsfh7 ? Uz1gh7 : Yrsfh7);
+ assign Tjsfh7 = (Mrsfh7 ? Essfh7 : com_rx_tdata[6]);
+ assign Ojsfh7 = (~(Kssfh7 & Arsfh7));
+ assign Kssfh7 = (Mrsfh7 ? Cz1gh7 : Qssfh7);
+ assign Jjsfh7 = (!Wssfh7);
+ assign Wssfh7 = (Mrsfh7 ? Wy1gh7 : Ctsfh7);
+ assign Ejsfh7 = (~(Itsfh7 & Arsfh7));
+ assign Itsfh7 = (Mrsfh7 ? C82gh7 : Otsfh7);
+ assign Mrsfh7 = (!Utsfh7);
+ assign Zisfh7 = (~(Ausfh7 & Arsfh7));
+ assign Arsfh7 = (~(Utsfh7 & Gusfh7));
+ assign Ausfh7 = (Utsfh7 ? Musfh7 : Qy1gh7);
+ assign Uisfh7 = (S0sfh7 ? Susfh7 : ahb_hwrite);
+ assign Susfh7 = (~(Yusfh7 & Evsfh7));
+ assign Evsfh7 = (~(Kvsfh7 & Qvsfh7));
+ assign Pisfh7 = (~(Wvsfh7 & Cwsfh7));
+ assign Cwsfh7 = (Iwsfh7 & Owsfh7);
+ assign Iwsfh7 = (~(Uwsfh7 & Axsfh7));
+ assign Wvsfh7 = (Gxsfh7 & Mxsfh7);
+ assign Mxsfh7 = (~(Sxsfh7 & Yxsfh7));
+ assign Gxsfh7 = (~(Eysfh7 & ahb_haddr[31]));
+ assign Kisfh7 = (~(Kysfh7 & Qysfh7));
+ assign Qysfh7 = (Wysfh7 & Owsfh7);
+ assign Wysfh7 = (~(Czsfh7 & Izsfh7));
+ assign Izsfh7 = (~(Ozsfh7 & Uzsfh7));
+ assign Uzsfh7 = (~(A0tfh7 & G0tfh7));
+ assign Ozsfh7 = (~(com_rx_tdata[0] & M0tfh7));
+ assign M0tfh7 = (S0tfh7 | Y0tfh7);
+ assign Kysfh7 = (E1tfh7 & K1tfh7);
+ assign K1tfh7 = (~(Sxsfh7 & Q1tfh7));
+ assign E1tfh7 = (~(Eysfh7 & ahb_haddr[0]));
+ assign Fisfh7 = (~(W1tfh7 & C2tfh7));
+ assign C2tfh7 = (I2tfh7 & Owsfh7);
+ assign I2tfh7 = (~(Uwsfh7 & O2tfh7));
+ assign W1tfh7 = (U2tfh7 & A3tfh7);
+ assign A3tfh7 = (~(Sxsfh7 & G3tfh7));
+ assign U2tfh7 = (~(Eysfh7 & ahb_haddr[30]));
+ assign Aisfh7 = (~(M3tfh7 & S3tfh7));
+ assign S3tfh7 = (Y3tfh7 & Owsfh7);
+ assign Y3tfh7 = (~(Uwsfh7 & E4tfh7));
+ assign M3tfh7 = (K4tfh7 & Q4tfh7);
+ assign Q4tfh7 = (~(Sxsfh7 & W4tfh7));
+ assign K4tfh7 = (~(Eysfh7 & ahb_haddr[29]));
+ assign Vhsfh7 = (~(C5tfh7 & I5tfh7));
+ assign I5tfh7 = (O5tfh7 & Owsfh7);
+ assign O5tfh7 = (~(Uwsfh7 & U5tfh7));
+ assign C5tfh7 = (A6tfh7 & G6tfh7);
+ assign G6tfh7 = (~(Sxsfh7 & M6tfh7));
+ assign A6tfh7 = (~(Eysfh7 & ahb_haddr[28]));
+ assign Qhsfh7 = (~(S6tfh7 & Y6tfh7));
+ assign Y6tfh7 = (E7tfh7 & Owsfh7);
+ assign E7tfh7 = (~(Uwsfh7 & K7tfh7));
+ assign S6tfh7 = (Q7tfh7 & W7tfh7);
+ assign W7tfh7 = (~(Sxsfh7 & Axsfh7));
+ assign Q7tfh7 = (~(Eysfh7 & ahb_haddr[27]));
+ assign Lhsfh7 = (~(C8tfh7 & I8tfh7));
+ assign I8tfh7 = (O8tfh7 & Owsfh7);
+ assign O8tfh7 = (~(Uwsfh7 & U8tfh7));
+ assign C8tfh7 = (A9tfh7 & G9tfh7);
+ assign G9tfh7 = (~(Sxsfh7 & O2tfh7));
+ assign A9tfh7 = (~(Eysfh7 & ahb_haddr[26]));
+ assign Ghsfh7 = (~(M9tfh7 & S9tfh7));
+ assign S9tfh7 = (Y9tfh7 & Owsfh7);
+ assign Y9tfh7 = (~(Uwsfh7 & Eatfh7));
+ assign M9tfh7 = (Katfh7 & Qatfh7);
+ assign Qatfh7 = (~(Sxsfh7 & E4tfh7));
+ assign Katfh7 = (~(Eysfh7 & ahb_haddr[25]));
+ assign Bhsfh7 = (~(Watfh7 & Cbtfh7));
+ assign Cbtfh7 = (Ibtfh7 & Owsfh7);
+ assign Ibtfh7 = (~(Uwsfh7 & Obtfh7));
+ assign Watfh7 = (Ubtfh7 & Actfh7);
+ assign Actfh7 = (~(Sxsfh7 & U5tfh7));
+ assign Ubtfh7 = (~(Eysfh7 & ahb_haddr[24]));
+ assign Wgsfh7 = (~(Gctfh7 & Mctfh7));
+ assign Mctfh7 = (Sctfh7 & Owsfh7);
+ assign Sctfh7 = (~(Uwsfh7 & Yctfh7));
+ assign Gctfh7 = (Edtfh7 & Kdtfh7);
+ assign Kdtfh7 = (~(Sxsfh7 & K7tfh7));
+ assign Edtfh7 = (~(Eysfh7 & ahb_haddr[23]));
+ assign Rgsfh7 = (~(Qdtfh7 & Wdtfh7));
+ assign Wdtfh7 = (Cetfh7 & Owsfh7);
+ assign Cetfh7 = (~(Uwsfh7 & Ietfh7));
+ assign Qdtfh7 = (Oetfh7 & Uetfh7);
+ assign Uetfh7 = (~(Sxsfh7 & U8tfh7));
+ assign Oetfh7 = (~(Eysfh7 & ahb_haddr[22]));
+ assign Mgsfh7 = (~(Aftfh7 & Gftfh7));
+ assign Gftfh7 = (Mftfh7 & Owsfh7);
+ assign Mftfh7 = (~(Uwsfh7 & Sftfh7));
+ assign Aftfh7 = (Yftfh7 & Egtfh7);
+ assign Egtfh7 = (~(Sxsfh7 & Eatfh7));
+ assign Yftfh7 = (~(Eysfh7 & ahb_haddr[21]));
+ assign Hgsfh7 = (~(Kgtfh7 & Qgtfh7));
+ assign Qgtfh7 = (Wgtfh7 & Owsfh7);
+ assign Wgtfh7 = (~(Uwsfh7 & Chtfh7));
+ assign Kgtfh7 = (Ihtfh7 & Ohtfh7);
+ assign Ohtfh7 = (~(Sxsfh7 & Obtfh7));
+ assign Ihtfh7 = (~(Eysfh7 & ahb_haddr[20]));
+ assign Cgsfh7 = (~(Uhtfh7 & Aitfh7));
+ assign Aitfh7 = (Gitfh7 & Owsfh7);
+ assign Gitfh7 = (~(Uwsfh7 & Mitfh7));
+ assign Uhtfh7 = (Sitfh7 & Yitfh7);
+ assign Yitfh7 = (~(Sxsfh7 & Yctfh7));
+ assign Sitfh7 = (~(Eysfh7 & ahb_haddr[19]));
+ assign Xfsfh7 = (~(Ejtfh7 & Kjtfh7));
+ assign Kjtfh7 = (Qjtfh7 & Owsfh7);
+ assign Qjtfh7 = (~(Uwsfh7 & Wjtfh7));
+ assign Ejtfh7 = (Cktfh7 & Iktfh7);
+ assign Iktfh7 = (~(Sxsfh7 & Ietfh7));
+ assign Cktfh7 = (~(Eysfh7 & ahb_haddr[18]));
+ assign Sfsfh7 = (~(Oktfh7 & Uktfh7));
+ assign Uktfh7 = (Altfh7 & Owsfh7);
+ assign Altfh7 = (~(Uwsfh7 & Gltfh7));
+ assign Oktfh7 = (Mltfh7 & Sltfh7);
+ assign Sltfh7 = (~(Sxsfh7 & Sftfh7));
+ assign Mltfh7 = (~(Eysfh7 & ahb_haddr[17]));
+ assign Nfsfh7 = (~(Yltfh7 & Emtfh7));
+ assign Emtfh7 = (Kmtfh7 & Owsfh7);
+ assign Kmtfh7 = (~(Uwsfh7 & Qmtfh7));
+ assign Yltfh7 = (Wmtfh7 & Cntfh7);
+ assign Cntfh7 = (~(Sxsfh7 & Chtfh7));
+ assign Wmtfh7 = (~(Eysfh7 & ahb_haddr[16]));
+ assign Ifsfh7 = (~(Intfh7 & Ontfh7));
+ assign Ontfh7 = (Untfh7 & Owsfh7);
+ assign Untfh7 = (~(Uwsfh7 & Aotfh7));
+ assign Intfh7 = (Gotfh7 & Motfh7);
+ assign Motfh7 = (~(Sxsfh7 & Mitfh7));
+ assign Gotfh7 = (~(Eysfh7 & ahb_haddr[15]));
+ assign Dfsfh7 = (~(Sotfh7 & Yotfh7));
+ assign Yotfh7 = (Eptfh7 & Owsfh7);
+ assign Eptfh7 = (~(Uwsfh7 & Kptfh7));
+ assign Sotfh7 = (Qptfh7 & Wptfh7);
+ assign Wptfh7 = (~(Sxsfh7 & Wjtfh7));
+ assign Qptfh7 = (~(Eysfh7 & ahb_haddr[14]));
+ assign Yesfh7 = (~(Cqtfh7 & Iqtfh7));
+ assign Iqtfh7 = (Oqtfh7 & Owsfh7);
+ assign Oqtfh7 = (~(Uwsfh7 & Uqtfh7));
+ assign Cqtfh7 = (Artfh7 & Grtfh7);
+ assign Grtfh7 = (~(Sxsfh7 & Gltfh7));
+ assign Artfh7 = (~(Eysfh7 & ahb_haddr[13]));
+ assign Tesfh7 = (~(Mrtfh7 & Srtfh7));
+ assign Srtfh7 = (Yrtfh7 & Owsfh7);
+ assign Yrtfh7 = (~(Uwsfh7 & Estfh7));
+ assign Mrtfh7 = (Kstfh7 & Qstfh7);
+ assign Qstfh7 = (~(Sxsfh7 & Qmtfh7));
+ assign Kstfh7 = (~(Eysfh7 & ahb_haddr[12]));
+ assign Oesfh7 = (~(Wstfh7 & Cttfh7));
+ assign Cttfh7 = (Ittfh7 & Owsfh7);
+ assign Ittfh7 = (~(Uwsfh7 & Ottfh7));
+ assign Wstfh7 = (Uttfh7 & Autfh7);
+ assign Autfh7 = (~(Sxsfh7 & Aotfh7));
+ assign Uttfh7 = (~(Eysfh7 & ahb_haddr[11]));
+ assign Jesfh7 = (~(Gutfh7 & Mutfh7));
+ assign Mutfh7 = (Sutfh7 & Owsfh7);
+ assign Sutfh7 = (~(Uwsfh7 & Yutfh7));
+ assign Gutfh7 = (Evtfh7 & Kvtfh7);
+ assign Kvtfh7 = (~(Sxsfh7 & Kptfh7));
+ assign Evtfh7 = (~(Eysfh7 & ahb_haddr[10]));
+ assign Eesfh7 = (~(Qvtfh7 & Wvtfh7));
+ assign Wvtfh7 = (Cwtfh7 & Owsfh7);
+ assign Cwtfh7 = (~(Uwsfh7 & Iwtfh7));
+ assign Qvtfh7 = (Owtfh7 & Uwtfh7);
+ assign Uwtfh7 = (~(Sxsfh7 & Uqtfh7));
+ assign Owtfh7 = (~(Eysfh7 & ahb_haddr[9]));
+ assign Zdsfh7 = (~(Axtfh7 & Gxtfh7));
+ assign Gxtfh7 = (Mxtfh7 & Owsfh7);
+ assign Mxtfh7 = (~(Uwsfh7 & Sxtfh7));
+ assign Axtfh7 = (Yxtfh7 & Eytfh7);
+ assign Eytfh7 = (~(Sxsfh7 & Estfh7));
+ assign Yxtfh7 = (~(Eysfh7 & ahb_haddr[8]));
+ assign Udsfh7 = (~(Kytfh7 & Qytfh7));
+ assign Qytfh7 = (Wytfh7 & Owsfh7);
+ assign Wytfh7 = (~(Uwsfh7 & Cztfh7));
+ assign Kytfh7 = (Iztfh7 & Oztfh7);
+ assign Oztfh7 = (~(Sxsfh7 & Ottfh7));
+ assign Iztfh7 = (~(Eysfh7 & ahb_haddr[7]));
+ assign Pdsfh7 = (~(Uztfh7 & A0ufh7));
+ assign A0ufh7 = (G0ufh7 & Owsfh7);
+ assign G0ufh7 = (~(Uwsfh7 & M0ufh7));
+ assign Uztfh7 = (S0ufh7 & Y0ufh7);
+ assign Y0ufh7 = (~(Sxsfh7 & Yutfh7));
+ assign S0ufh7 = (~(Eysfh7 & ahb_haddr[6]));
+ assign Kdsfh7 = (~(E1ufh7 & K1ufh7));
+ assign K1ufh7 = (Q1ufh7 & Owsfh7);
+ assign Q1ufh7 = (~(Uwsfh7 & W1ufh7));
+ assign E1ufh7 = (C2ufh7 & I2ufh7);
+ assign I2ufh7 = (~(Sxsfh7 & Iwtfh7));
+ assign C2ufh7 = (~(Eysfh7 & ahb_haddr[5]));
+ assign Fdsfh7 = (~(O2ufh7 & U2ufh7));
+ assign U2ufh7 = (A3ufh7 & Owsfh7);
+ assign A3ufh7 = (~(Uwsfh7 & Q1tfh7));
+ assign Uwsfh7 = (Czsfh7 & G3ufh7);
+ assign G3ufh7 = (M3ufh7 | S0tfh7);
+ assign O2ufh7 = (S3ufh7 & Y3ufh7);
+ assign Y3ufh7 = (~(Sxsfh7 & Sxtfh7));
+ assign S3ufh7 = (~(Eysfh7 & ahb_haddr[4]));
+ assign Adsfh7 = (~(E4ufh7 & K4ufh7));
+ assign K4ufh7 = (Q4ufh7 & Owsfh7);
+ assign Q4ufh7 = (~(Czsfh7 & M3ufh7));
+ assign M3ufh7 = (W4ufh7 | C5ufh7);
+ assign C5ufh7 = (com_rx_tdata[2] ? A0tfh7 : I5ufh7);
+ assign I5ufh7 = (O5ufh7 & com_rx_tdata[1]);
+ assign W4ufh7 = (U5ufh7 | Y0tfh7);
+ assign Y0tfh7 = (A6ufh7 & G6ufh7);
+ assign A6ufh7 = (M6ufh7 & com_rx_tdata[3]);
+ assign E4ufh7 = (S6ufh7 & Y6ufh7);
+ assign Y6ufh7 = (~(Sxsfh7 & Cztfh7));
+ assign S6ufh7 = (~(Eysfh7 & ahb_haddr[3]));
+ assign Vcsfh7 = (~(E7ufh7 & K7ufh7));
+ assign K7ufh7 = (Q7ufh7 & Owsfh7);
+ assign Q7ufh7 = (~(Czsfh7 & W7ufh7));
+ assign W7ufh7 = (~(C8ufh7 & I8ufh7));
+ assign C8ufh7 = (Otsfh7 ? U8ufh7 : O8ufh7);
+ assign U8ufh7 = (~(A9ufh7 & O5ufh7));
+ assign E7ufh7 = (G9ufh7 & M9ufh7);
+ assign M9ufh7 = (~(Sxsfh7 & M0ufh7));
+ assign G9ufh7 = (~(Eysfh7 & ahb_haddr[2]));
+ assign Qcsfh7 = (~(S9ufh7 & Y9ufh7));
+ assign Y9ufh7 = (Eaufh7 & Owsfh7);
+ assign Owsfh7 = (~(Kaufh7 & Qaufh7));
+ assign Eaufh7 = (~(Czsfh7 & Waufh7));
+ assign Waufh7 = (U5ufh7 | Cbufh7);
+ assign Cbufh7 = (~(Musfh7 | O8ufh7));
+ assign O8ufh7 = (~(S0tfh7 | A0tfh7));
+ assign A0tfh7 = (O5ufh7 & Grsfh7);
+ assign S0tfh7 = (G6ufh7 & Ctsfh7);
+ assign G6ufh7 = (Ibufh7 & com_rx_tdata[4]);
+ assign Ibufh7 = (~(Obufh7 | com_rx_tdata[6]));
+ assign U5ufh7 = (~(I8ufh7 & Ubufh7));
+ assign Ubufh7 = (~(Acufh7 & O5ufh7));
+ assign Acufh7 = (M6ufh7 & com_rx_tdata[0]);
+ assign I8ufh7 = (~(Gcufh7 & Mcufh7));
+ assign Mcufh7 = (com_rx_tdata[0] & Musfh7);
+ assign Gcufh7 = (O5ufh7 & com_rx_tdata[2]);
+ assign O5ufh7 = (Scufh7 & com_rx_tdata[6]);
+ assign Scufh7 = (Ctsfh7 & Qssfh7);
+ assign S9ufh7 = (Ycufh7 & Edufh7);
+ assign Edufh7 = (~(Sxsfh7 & W1ufh7));
+ assign Sxsfh7 = (~(Kdufh7 & Qdufh7));
+ assign Qdufh7 = (~(Wdufh7 & com_rx_tdata[7]));
+ assign Kdufh7 = (Ceufh7 & Qaufh7);
+ assign Ceufh7 = (~(Czsfh7 & Ieufh7));
+ assign Ieufh7 = (~(Oeufh7 & Ueufh7));
+ assign Ueufh7 = (com_rx_tdata[6] ? Gfufh7 : Afufh7);
+ assign Gfufh7 = (Ctsfh7 ? Qssfh7 : Grsfh7);
+ assign Afufh7 = (~(Mfufh7 & Obufh7));
+ assign Mfufh7 = (~(com_rx_tdata[0] & Qssfh7));
+ assign Oeufh7 = (Sfufh7 & Yfufh7);
+ assign Yfufh7 = (~(Egufh7 & Qssfh7));
+ assign Egufh7 = (~(Kgufh7 & Qgufh7));
+ assign Qgufh7 = (com_rx_tdata[6] ? Chufh7 : Wgufh7);
+ assign Chufh7 = (~(M6ufh7 & Grsfh7));
+ assign Wgufh7 = (~(G0tfh7 | Ihufh7));
+ assign Kgufh7 = (Ohufh7 & Uhufh7);
+ assign Uhufh7 = (~(A9ufh7 & com_rx_tdata[2]));
+ assign Ohufh7 = (~(com_rx_tdata[5] & com_rx_tdata[3]));
+ assign Sfufh7 = (~(com_rx_tdata[3] & G0tfh7));
+ assign G0tfh7 = (!M6ufh7);
+ assign Czsfh7 = (Aiufh7 & Wdufh7);
+ assign Aiufh7 = (Qaufh7 & Yrsfh7);
+ assign Yrsfh7 = (!com_rx_tdata[7]);
+ assign Ycufh7 = (~(Eysfh7 & ahb_haddr[1]));
+ assign Eysfh7 = (Kvsfh7 & Qaufh7);
+ assign Qaufh7 = (~(Giufh7 & Miufh7));
+ assign Miufh7 = (~(Wdufh7 & Siufh7));
+ assign Giufh7 = (Yiufh7 & Ejufh7);
+ assign Ejufh7 = (Kjufh7 | Qjufh7);
+ assign Lcsfh7 = (~(Wjufh7 & Ckufh7));
+ assign Ckufh7 = (Ikufh7 | Fyrfh7);
+ assign Ikufh7 = (Okufh7 & Ukufh7);
+ assign Ukufh7 = (~(Ws1gh7 & It1gh7));
+ assign Wjufh7 = (~(Alufh7 & Ottfh7));
+ assign Gcsfh7 = (~(Glufh7 & Mlufh7));
+ assign Mlufh7 = (Slufh7 | Wwrfh7);
+ assign Slufh7 = (Okufh7 & Ylufh7);
+ assign Ylufh7 = (~(Gr1gh7 & It1gh7));
+ assign Glufh7 = (~(Alufh7 & Q1tfh7));
+ assign Bcsfh7 = (~(Emufh7 & Kmufh7));
+ assign Kmufh7 = (Qmufh7 | Bxrfh7);
+ assign Qmufh7 = (Okufh7 & Wmufh7);
+ assign Wmufh7 = (~(Mr1gh7 & It1gh7));
+ assign Emufh7 = (~(Alufh7 & W1ufh7));
+ assign Wbsfh7 = (~(Cnufh7 & Inufh7));
+ assign Inufh7 = (Onufh7 | Gxrfh7);
+ assign Onufh7 = (Okufh7 & Unufh7);
+ assign Unufh7 = (~(Sr1gh7 & It1gh7));
+ assign Cnufh7 = (~(Alufh7 & M0ufh7));
+ assign Rbsfh7 = (~(Aoufh7 & Goufh7));
+ assign Goufh7 = (Moufh7 | Lxrfh7);
+ assign Moufh7 = (Okufh7 & Soufh7);
+ assign Soufh7 = (~(Yr1gh7 & It1gh7));
+ assign Aoufh7 = (~(Alufh7 & Cztfh7));
+ assign Mbsfh7 = (~(Youfh7 & Epufh7));
+ assign Epufh7 = (Kpufh7 | Qxrfh7);
+ assign Kpufh7 = (Okufh7 & Qpufh7);
+ assign Qpufh7 = (~(Es1gh7 & It1gh7));
+ assign Youfh7 = (~(Alufh7 & Sxtfh7));
+ assign Hbsfh7 = (~(Wpufh7 & Cqufh7));
+ assign Cqufh7 = (Iqufh7 | Vxrfh7);
+ assign Iqufh7 = (Okufh7 & Oqufh7);
+ assign Oqufh7 = (~(Ks1gh7 & It1gh7));
+ assign Wpufh7 = (~(Alufh7 & Iwtfh7));
+ assign Cbsfh7 = (~(Uqufh7 & Arufh7));
+ assign Arufh7 = (Grufh7 | Ayrfh7);
+ assign Grufh7 = (Okufh7 & Mrufh7);
+ assign Mrufh7 = (~(Qs1gh7 & It1gh7));
+ assign Okufh7 = (~(Srufh7 | Ct1gh7));
+ assign Uqufh7 = (~(Alufh7 & Yutfh7));
+ assign Alufh7 = (~(Srufh7 | It1gh7));
+ assign Srufh7 = (~(Yrufh7 & Esufh7));
+ assign Esufh7 = (Ksufh7 & Qsufh7);
+ assign Qsufh7 = (Wsufh7 & Ctufh7);
+ assign Ctufh7 = (Itufh7 & Ky1gh7);
+ assign Itufh7 = (Wpsfh7 & Hvqfh7);
+ assign Wsufh7 = (Otufh7 & Sx1gh7);
+ assign Otufh7 = (Yx1gh7 & Ey1gh7);
+ assign Ksufh7 = (Utufh7 & Auufh7);
+ assign Auufh7 = (Guufh7 & Ax1gh7);
+ assign Guufh7 = (Gx1gh7 & Mx1gh7);
+ assign Utufh7 = (Muufh7 & Iw1gh7);
+ assign Muufh7 = (Ow1gh7 & Uw1gh7);
+ assign Yrufh7 = (Suufh7 & Yuufh7);
+ assign Yuufh7 = (Evufh7 & Kvufh7);
+ assign Kvufh7 = (Qvufh7 & Qv1gh7);
+ assign Qvufh7 = (Wv1gh7 & Cw1gh7);
+ assign Evufh7 = (Wvufh7 & Yu1gh7);
+ assign Wvufh7 = (Ev1gh7 & Kv1gh7);
+ assign Suufh7 = (Cwufh7 & Iwufh7);
+ assign Iwufh7 = (Owufh7 & Gu1gh7);
+ assign Owufh7 = (Mu1gh7 & Su1gh7);
+ assign Cwufh7 = (Uwufh7 & Ot1gh7);
+ assign Uwufh7 = (Ut1gh7 & Au1gh7);
+ assign Xasfh7 = (~(Axufh7 & Gxufh7));
+ assign Gxufh7 = (Mxufh7 & Sxufh7);
+ assign Sxufh7 = (~(Yxufh7 & Chtfh7));
+ assign Mxufh7 = (~(ahb_hrdata[16] & Eyufh7));
+ assign Axufh7 = (Kyufh7 & Qyufh7);
+ assign Qyufh7 = (Wyufh7 | K3sfh7);
+ assign Kyufh7 = (Czufh7 | Wwrfh7);
+ assign Sasfh7 = (~(Izufh7 & Ozufh7));
+ assign Ozufh7 = (Uzufh7 & A0vfh7);
+ assign A0vfh7 = (~(Yxufh7 & Sftfh7));
+ assign Uzufh7 = (~(ahb_hrdata[17] & Eyufh7));
+ assign Izufh7 = (G0vfh7 & M0vfh7);
+ assign M0vfh7 = (~(S0vfh7 & Y0vfh7));
+ assign G0vfh7 = (Czufh7 | Bxrfh7);
+ assign Nasfh7 = (~(E1vfh7 & K1vfh7));
+ assign K1vfh7 = (Q1vfh7 & W1vfh7);
+ assign W1vfh7 = (~(Yxufh7 & Ietfh7));
+ assign Q1vfh7 = (~(ahb_hrdata[18] & Eyufh7));
+ assign E1vfh7 = (C2vfh7 & I2vfh7);
+ assign I2vfh7 = (~(S0vfh7 & O2vfh7));
+ assign C2vfh7 = (Czufh7 | Gxrfh7);
+ assign Iasfh7 = (~(U2vfh7 & A3vfh7));
+ assign A3vfh7 = (G3vfh7 & M3vfh7);
+ assign M3vfh7 = (~(Yxufh7 & Yctfh7));
+ assign G3vfh7 = (~(ahb_hrdata[19] & Eyufh7));
+ assign U2vfh7 = (S3vfh7 & Y3vfh7);
+ assign Y3vfh7 = (~(S0vfh7 & E4vfh7));
+ assign S3vfh7 = (Czufh7 | Lxrfh7);
+ assign Dasfh7 = (~(K4vfh7 & Q4vfh7));
+ assign Q4vfh7 = (W4vfh7 & C5vfh7);
+ assign C5vfh7 = (~(Yxufh7 & Obtfh7));
+ assign W4vfh7 = (~(ahb_hrdata[20] & Eyufh7));
+ assign K4vfh7 = (I5vfh7 & O5vfh7);
+ assign O5vfh7 = (Wyufh7 | E4sfh7);
+ assign I5vfh7 = (Czufh7 | Qxrfh7);
+ assign Y9sfh7 = (~(U5vfh7 & A6vfh7));
+ assign A6vfh7 = (G6vfh7 & M6vfh7);
+ assign M6vfh7 = (~(Yxufh7 & Eatfh7));
+ assign G6vfh7 = (~(ahb_hrdata[21] & Eyufh7));
+ assign U5vfh7 = (S6vfh7 & Y6vfh7);
+ assign Y6vfh7 = (~(S0vfh7 & E7vfh7));
+ assign S6vfh7 = (Czufh7 | Vxrfh7);
+ assign T9sfh7 = (~(K7vfh7 & Q7vfh7));
+ assign Q7vfh7 = (W7vfh7 & C8vfh7);
+ assign C8vfh7 = (~(Yxufh7 & U8tfh7));
+ assign W7vfh7 = (~(ahb_hrdata[22] & Eyufh7));
+ assign K7vfh7 = (I8vfh7 & O8vfh7);
+ assign O8vfh7 = (~(S0vfh7 & U8vfh7));
+ assign I8vfh7 = (Czufh7 | Ayrfh7);
+ assign O9sfh7 = (~(A9vfh7 & G9vfh7));
+ assign G9vfh7 = (M9vfh7 & S9vfh7);
+ assign S9vfh7 = (~(Yxufh7 & K7tfh7));
+ assign M9vfh7 = (~(ahb_hrdata[23] & Eyufh7));
+ assign A9vfh7 = (Y9vfh7 & Eavfh7);
+ assign Eavfh7 = (~(S0vfh7 & Kavfh7));
+ assign Y9vfh7 = (Czufh7 | Fyrfh7);
+ assign J9sfh7 = (~(Qavfh7 & Wavfh7));
+ assign Wavfh7 = (Cbvfh7 & Ibvfh7);
+ assign Ibvfh7 = (~(Yxufh7 & U5tfh7));
+ assign Cbvfh7 = (~(ahb_hrdata[24] & Eyufh7));
+ assign Qavfh7 = (Obvfh7 & Ubvfh7);
+ assign Ubvfh7 = (Wyufh7 | Y4sfh7);
+ assign Obvfh7 = (~(gpi8[0] & Acvfh7));
+ assign E9sfh7 = (~(Gcvfh7 & Mcvfh7));
+ assign Mcvfh7 = (Scvfh7 & Ycvfh7);
+ assign Ycvfh7 = (~(Yxufh7 & E4tfh7));
+ assign Scvfh7 = (~(ahb_hrdata[25] & Eyufh7));
+ assign Gcvfh7 = (Edvfh7 & Kdvfh7);
+ assign Kdvfh7 = (~(S0vfh7 & Qdvfh7));
+ assign Edvfh7 = (~(gpi8[1] & Acvfh7));
+ assign Z8sfh7 = (~(Wdvfh7 & Cevfh7));
+ assign Cevfh7 = (Ievfh7 & Oevfh7);
+ assign Oevfh7 = (~(Yxufh7 & O2tfh7));
+ assign Ievfh7 = (~(ahb_hrdata[26] & Eyufh7));
+ assign Wdvfh7 = (Uevfh7 & Afvfh7);
+ assign Afvfh7 = (~(S0vfh7 & Gfvfh7));
+ assign Uevfh7 = (~(gpi8[2] & Acvfh7));
+ assign U8sfh7 = (~(Mfvfh7 & Sfvfh7));
+ assign Sfvfh7 = (Yfvfh7 & Egvfh7);
+ assign Egvfh7 = (~(Yxufh7 & Axsfh7));
+ assign Yfvfh7 = (~(ahb_hrdata[27] & Eyufh7));
+ assign Mfvfh7 = (Kgvfh7 & Qgvfh7);
+ assign Qgvfh7 = (~(S0vfh7 & Wgvfh7));
+ assign Kgvfh7 = (~(gpi8[3] & Acvfh7));
+ assign P8sfh7 = (~(Chvfh7 & Ihvfh7));
+ assign Ihvfh7 = (Ohvfh7 & Uhvfh7);
+ assign Uhvfh7 = (~(Yxufh7 & M6tfh7));
+ assign Ohvfh7 = (~(ahb_hrdata[28] & Eyufh7));
+ assign Chvfh7 = (Aivfh7 & Givfh7);
+ assign Givfh7 = (Wyufh7 | S5sfh7);
+ assign Aivfh7 = (~(gpi8[4] & Acvfh7));
+ assign K8sfh7 = (~(Mivfh7 & Sivfh7));
+ assign Sivfh7 = (Yivfh7 & Ejvfh7);
+ assign Ejvfh7 = (~(Yxufh7 & W4tfh7));
+ assign Yivfh7 = (~(ahb_hrdata[29] & Eyufh7));
+ assign Mivfh7 = (Kjvfh7 & Qjvfh7);
+ assign Qjvfh7 = (~(S0vfh7 & Wjvfh7));
+ assign Kjvfh7 = (~(gpi8[5] & Acvfh7));
+ assign F8sfh7 = (~(Ckvfh7 & Ikvfh7));
+ assign Ikvfh7 = (Okvfh7 & Ukvfh7);
+ assign Ukvfh7 = (~(Yxufh7 & G3tfh7));
+ assign Okvfh7 = (~(ahb_hrdata[30] & Eyufh7));
+ assign Ckvfh7 = (Alvfh7 & Glvfh7);
+ assign Glvfh7 = (~(S0vfh7 & Mlvfh7));
+ assign Alvfh7 = (~(gpi8[6] & Acvfh7));
+ assign A8sfh7 = (~(Slvfh7 & Ylvfh7));
+ assign Ylvfh7 = (Emvfh7 & Kmvfh7);
+ assign Kmvfh7 = (~(Yxufh7 & Yxsfh7));
+ assign Yxufh7 = (!Qmvfh7);
+ assign Emvfh7 = (~(ahb_hrdata[31] & Eyufh7));
+ assign Slvfh7 = (Wmvfh7 & Cnvfh7);
+ assign Cnvfh7 = (~(S0vfh7 & Invfh7));
+ assign Wmvfh7 = (~(gpi8[7] & Acvfh7));
+ assign Acvfh7 = (!Czufh7);
+ assign V7sfh7 = (Onvfh7 & Unvfh7);
+ assign Unvfh7 = (~(Aovfh7 & Govfh7));
+ assign Govfh7 = (Movfh7 & Sovfh7);
+ assign Sovfh7 = (Yovfh7 & Epvfh7);
+ assign Epvfh7 = (Kpvfh7 & Qpvfh7);
+ assign Yovfh7 = (Wpvfh7 & Cqvfh7);
+ assign Cqvfh7 = (~(Iqvfh7 & Oqvfh7));
+ assign Iqvfh7 = (~(Uqvfh7 | M1sfh7));
+ assign Wpvfh7 = (~(Arvfh7 & Grvfh7));
+ assign Arvfh7 = (Mrvfh7 ^ Srvfh7);
+ assign Movfh7 = (Yrvfh7 & Esvfh7);
+ assign Esvfh7 = (Ksvfh7 & Qsvfh7);
+ assign Qsvfh7 = (~(Wsvfh7 & Ctvfh7));
+ assign Wsvfh7 = (Itvfh7 ^ Otvfh7);
+ assign Ksvfh7 = (~(Utvfh7 & Auvfh7));
+ assign Utvfh7 = (~(Guvfh7 ^ S5sfh7));
+ assign Yrvfh7 = (Muvfh7 & Suvfh7);
+ assign Suvfh7 = (~(Yuvfh7 & Evvfh7));
+ assign Yuvfh7 = (~(Kvvfh7 ^ K3sfh7));
+ assign Muvfh7 = (~(Qvvfh7 & Wvvfh7));
+ assign Qvvfh7 = (~(Cwvfh7 ^ Y4sfh7));
+ assign Aovfh7 = (Iwvfh7 & Owvfh7);
+ assign Owvfh7 = (Uwvfh7 & Axvfh7);
+ assign Axvfh7 = (Gxvfh7 & Mxvfh7);
+ assign Mxvfh7 = (~(Sxvfh7 & Yxvfh7));
+ assign Sxvfh7 = (~(Eyvfh7 ^ E4sfh7));
+ assign Gxvfh7 = (~(Kyvfh7 & Qyvfh7));
+ assign Kyvfh7 = (Wyvfh7 ^ Czvfh7);
+ assign Uwvfh7 = (Izvfh7 & Ozvfh7);
+ assign Ozvfh7 = (~(Uzvfh7 & A0wfh7));
+ assign Izvfh7 = (~(G0wfh7 & M0wfh7));
+ assign Iwvfh7 = (S0wfh7 & Y0wfh7);
+ assign S0wfh7 = (E1wfh7 & K1wfh7);
+ assign K1wfh7 = (Q1wfh7 | Iz1gh7);
+ assign E1wfh7 = (~(stdio_rx_tdata[0] & W1wfh7));
+ assign Onvfh7 = (~(Uyrfh7 & C2wfh7));
+ assign Q7sfh7 = (I2wfh7 & O2wfh7);
+ assign O2wfh7 = (~(U2wfh7 & A3wfh7));
+ assign A3wfh7 = (G3wfh7 & M3wfh7);
+ assign M3wfh7 = (S3wfh7 & Y3wfh7);
+ assign Y3wfh7 = (E4wfh7 & K4wfh7);
+ assign S3wfh7 = (Q4wfh7 & W4wfh7);
+ assign W4wfh7 = (C5wfh7 | I5wfh7);
+ assign C5wfh7 = (G2sfh7 ? U5wfh7 : O5wfh7);
+ assign U5wfh7 = (~(O5wfh7 & A6wfh7));
+ assign O5wfh7 = (B2sfh7 & G6wfh7);
+ assign Q4wfh7 = (M6wfh7 | S6wfh7);
+ assign M6wfh7 = (X0sfh7 ? E7wfh7 : Y6wfh7);
+ assign E7wfh7 = (~(Y6wfh7 & K7wfh7));
+ assign Y6wfh7 = (Pyrfh7 & Q7wfh7);
+ assign G3wfh7 = (W7wfh7 & C8wfh7);
+ assign C8wfh7 = (~(Wvvfh7 & I8wfh7));
+ assign I8wfh7 = (~(O8wfh7 & U8wfh7));
+ assign U8wfh7 = (~(A9wfh7 & Gfvfh7));
+ assign A9wfh7 = (!G9wfh7);
+ assign O8wfh7 = (~(M9wfh7 & Qdvfh7));
+ assign W7wfh7 = (S9wfh7 & Y9wfh7);
+ assign Y9wfh7 = (~(Auvfh7 & Eawfh7));
+ assign Eawfh7 = (~(Kawfh7 & Qawfh7));
+ assign Qawfh7 = (~(Wawfh7 & Mlvfh7));
+ assign Wawfh7 = (!Cbwfh7);
+ assign Kawfh7 = (~(Ibwfh7 & Wjvfh7));
+ assign S9wfh7 = (~(Evvfh7 & Obwfh7));
+ assign Obwfh7 = (~(Ubwfh7 & Acwfh7));
+ assign Acwfh7 = (~(Gcwfh7 & O2vfh7));
+ assign Gcwfh7 = (!Mcwfh7);
+ assign Ubwfh7 = (~(Scwfh7 & Y0vfh7));
+ assign U2wfh7 = (Ycwfh7 & Edwfh7);
+ assign Edwfh7 = (Kdwfh7 & Qdwfh7);
+ assign Qdwfh7 = (Wdwfh7 & Cewfh7);
+ assign Cewfh7 = (~(Yxvfh7 & Iewfh7));
+ assign Iewfh7 = (~(Oewfh7 & Uewfh7));
+ assign Uewfh7 = (~(Afwfh7 & U8vfh7));
+ assign Afwfh7 = (!Gfwfh7);
+ assign Oewfh7 = (~(Mfwfh7 & E7vfh7));
+ assign Wdwfh7 = (Sfwfh7 | Yfwfh7);
+ assign Sfwfh7 = (V2sfh7 ? Kgwfh7 : Egwfh7);
+ assign Kgwfh7 = (~(Egwfh7 & Qgwfh7));
+ assign Egwfh7 = (Kyrfh7 & Wgwfh7);
+ assign Kdwfh7 = (Chwfh7 & Ihwfh7);
+ assign Ihwfh7 = (Q1wfh7 | Qy1gh7);
+ assign Chwfh7 = (~(stdio_rx_tdata[1] & W1wfh7));
+ assign Ycwfh7 = (Ohwfh7 & Uhwfh7);
+ assign Uhwfh7 = (A0wfh7 ? Giwfh7 : Aiwfh7);
+ assign Giwfh7 = (~(R1sfh7 & Miwfh7));
+ assign Aiwfh7 = (!Uzvfh7);
+ assign Ohwfh7 = (Siwfh7 & Yiwfh7);
+ assign I2wfh7 = (~(Zyrfh7 & C2wfh7));
+ assign L7sfh7 = (Ejwfh7 & Kjwfh7);
+ assign Kjwfh7 = (~(Qjwfh7 & Wjwfh7));
+ assign Wjwfh7 = (Ckwfh7 & Ikwfh7);
+ assign Ikwfh7 = (Okwfh7 & Ukwfh7);
+ assign Ukwfh7 = (Alwfh7 & Kpvfh7);
+ assign Alwfh7 = (~(Glwfh7 & Ctvfh7));
+ assign Glwfh7 = (Mlwfh7 & K7wfh7);
+ assign Mlwfh7 = (~(Pyrfh7 & X0sfh7));
+ assign Okwfh7 = (Slwfh7 & Ylwfh7);
+ assign Ylwfh7 = (~(Emwfh7 & Grvfh7));
+ assign Emwfh7 = (Kmwfh7 & A6wfh7);
+ assign Kmwfh7 = (~(B2sfh7 & G2sfh7));
+ assign Slwfh7 = (~(Qmwfh7 & Qyvfh7));
+ assign Qmwfh7 = (Wmwfh7 & Qgwfh7);
+ assign Wmwfh7 = (~(Kyrfh7 & V2sfh7));
+ assign Ckwfh7 = (Cnwfh7 & Inwfh7);
+ assign Inwfh7 = (Onwfh7 & Unwfh7);
+ assign Onwfh7 = (~(Aowfh7 & Evvfh7));
+ assign Aowfh7 = (Mcwfh7 & O2vfh7);
+ assign O2vfh7 = (!U3sfh7);
+ assign Mcwfh7 = (Scwfh7 | Y0vfh7);
+ assign Y0vfh7 = (!P3sfh7);
+ assign Scwfh7 = (~(K3sfh7 & E4vfh7));
+ assign Cnwfh7 = (Gowfh7 & Mowfh7);
+ assign Mowfh7 = (~(Sowfh7 & Yxvfh7));
+ assign Sowfh7 = (Gfwfh7 & U8vfh7);
+ assign U8vfh7 = (!O4sfh7);
+ assign Gfwfh7 = (Mfwfh7 | E7vfh7);
+ assign E7vfh7 = (!J4sfh7);
+ assign Mfwfh7 = (~(E4sfh7 & Kavfh7));
+ assign Gowfh7 = (~(Yowfh7 & Wvvfh7));
+ assign Yowfh7 = (G9wfh7 & Gfvfh7);
+ assign Gfvfh7 = (!I5sfh7);
+ assign G9wfh7 = (M9wfh7 | Qdvfh7);
+ assign Qdvfh7 = (!D5sfh7);
+ assign M9wfh7 = (~(Y4sfh7 & Wgvfh7));
+ assign Qjwfh7 = (Epwfh7 & Kpwfh7);
+ assign Kpwfh7 = (Qpwfh7 & Wpwfh7);
+ assign Wpwfh7 = (Cqwfh7 & Iqwfh7);
+ assign Iqwfh7 = (~(Oqwfh7 & Auvfh7));
+ assign Oqwfh7 = (Cbwfh7 & Mlvfh7);
+ assign Mlvfh7 = (!C6sfh7);
+ assign Cbwfh7 = (Ibwfh7 | Wjvfh7);
+ assign Wjvfh7 = (!X5sfh7);
+ assign Ibwfh7 = (~(S5sfh7 & Invfh7));
+ assign Cqwfh7 = (~(Uqwfh7 & Q2sfh7));
+ assign Uqwfh7 = (Grvfh7 & A6wfh7);
+ assign Qpwfh7 = (Arwfh7 & Grwfh7);
+ assign Grwfh7 = (~(Mrwfh7 & H1sfh7));
+ assign Mrwfh7 = (Ctvfh7 & K7wfh7);
+ assign Arwfh7 = (~(Srwfh7 & F3sfh7));
+ assign Srwfh7 = (Qyvfh7 & Qgwfh7);
+ assign Epwfh7 = (Yrwfh7 & Eswfh7);
+ assign Eswfh7 = (Kswfh7 & Qswfh7);
+ assign Qswfh7 = (~(W1sfh7 & Miwfh7));
+ assign Kswfh7 = (Q1wfh7 | C82gh7);
+ assign Yrwfh7 = (Wswfh7 & Ctwfh7);
+ assign Ctwfh7 = (~(stdio_rx_tdata[2] & W1wfh7));
+ assign Ejwfh7 = (~(Ezrfh7 & C2wfh7));
+ assign G7sfh7 = (Itwfh7 & Otwfh7);
+ assign Otwfh7 = (~(Utwfh7 & Auwfh7));
+ assign Auwfh7 = (Guwfh7 & Muwfh7);
+ assign Muwfh7 = (Suwfh7 & Yuwfh7);
+ assign Yuwfh7 = (Evwfh7 & Kvwfh7);
+ assign Evwfh7 = (~(Qvwfh7 & Wvwfh7));
+ assign Wvwfh7 = (G2sfh7 & G6wfh7);
+ assign Qvwfh7 = (Grvfh7 & L2sfh7);
+ assign Suwfh7 = (Cwwfh7 & Iwwfh7);
+ assign Iwwfh7 = (~(Owwfh7 & Uwwfh7));
+ assign Uwwfh7 = (Oqvfh7 & Axwfh7);
+ assign Owwfh7 = (R1sfh7 & Ozrfh7);
+ assign Cwwfh7 = (~(Gxwfh7 & Mxwfh7));
+ assign Mxwfh7 = (X0sfh7 & Q7wfh7);
+ assign Gxwfh7 = (Ctvfh7 & C1sfh7);
+ assign Guwfh7 = (Sxwfh7 & Yxwfh7);
+ assign Yxwfh7 = (~(Eywfh7 & Kywfh7));
+ assign Kywfh7 = (D5sfh7 & Wgvfh7);
+ assign Eywfh7 = (Wvvfh7 & I5sfh7);
+ assign Sxwfh7 = (Qywfh7 & Wywfh7);
+ assign Wywfh7 = (~(Czwfh7 & Izwfh7));
+ assign Izwfh7 = (X5sfh7 & Invfh7);
+ assign Czwfh7 = (Auvfh7 & C6sfh7);
+ assign Qywfh7 = (~(Ozwfh7 & Uzwfh7));
+ assign Uzwfh7 = (P3sfh7 & E4vfh7);
+ assign Ozwfh7 = (Evvfh7 & U3sfh7);
+ assign Utwfh7 = (A0xfh7 & G0xfh7);
+ assign G0xfh7 = (M0xfh7 & S0xfh7);
+ assign S0xfh7 = (Q1wfh7 | Wy1gh7);
+ assign M0xfh7 = (Y0xfh7 & E1xfh7);
+ assign E1xfh7 = (~(K1xfh7 & Q1xfh7));
+ assign Q1xfh7 = (J4sfh7 & Kavfh7);
+ assign K1xfh7 = (Yxvfh7 & O4sfh7);
+ assign Y0xfh7 = (~(W1xfh7 & C2xfh7));
+ assign C2xfh7 = (V2sfh7 & Wgwfh7);
+ assign W1xfh7 = (Qyvfh7 & A3sfh7);
+ assign A0xfh7 = (I2xfh7 & Wswfh7);
+ assign Wswfh7 = (O2xfh7 & U2xfh7);
+ assign O2xfh7 = (A3xfh7 & Qpvfh7);
+ assign I2xfh7 = (Siwfh7 & G3xfh7);
+ assign G3xfh7 = (~(stdio_rx_tdata[3] & W1wfh7));
+ assign Siwfh7 = (M3xfh7 & S3xfh7);
+ assign S3xfh7 = (Y3xfh7 & M0wfh7);
+ assign M3xfh7 = (E4xfh7 & K4xfh7);
+ assign Itwfh7 = (~(Jzrfh7 & C2wfh7));
+ assign B7sfh7 = (Q4xfh7 & W4xfh7);
+ assign W4xfh7 = (~(C5xfh7 & I5xfh7));
+ assign I5xfh7 = (O5xfh7 & U5xfh7);
+ assign U5xfh7 = (A6xfh7 & G6xfh7);
+ assign G6xfh7 = (M6xfh7 & Kpvfh7);
+ assign M6xfh7 = (S6xfh7 & K4wfh7);
+ assign A6xfh7 = (Kvwfh7 & Y6xfh7);
+ assign O5xfh7 = (E7xfh7 & K7xfh7);
+ assign K7xfh7 = (Q7xfh7 & A3xfh7);
+ assign Q7xfh7 = (W7xfh7 | Uqvfh7);
+ assign Uqvfh7 = (Axwfh7 & C8xfh7);
+ assign C8xfh7 = (~(R1sfh7 & Ozrfh7));
+ assign E7xfh7 = (I8xfh7 & O8xfh7);
+ assign O8xfh7 = (~(Evvfh7 & U8xfh7));
+ assign U8xfh7 = (!Kvvfh7);
+ assign I8xfh7 = (~(Yxvfh7 & A9xfh7));
+ assign A9xfh7 = (!Eyvfh7);
+ assign C5xfh7 = (G9xfh7 & M9xfh7);
+ assign M9xfh7 = (S9xfh7 & Y9xfh7);
+ assign Y9xfh7 = (Eaxfh7 & Kaxfh7);
+ assign Kaxfh7 = (~(Wvvfh7 & Qaxfh7));
+ assign Qaxfh7 = (!Cwvfh7);
+ assign Eaxfh7 = (~(Auvfh7 & Waxfh7));
+ assign Waxfh7 = (!Guvfh7);
+ assign S9xfh7 = (Cbxfh7 & Ibxfh7);
+ assign Ibxfh7 = (I5wfh7 | Mrvfh7);
+ assign Cbxfh7 = (Yfwfh7 | Wyvfh7);
+ assign G9xfh7 = (Obxfh7 & Ubxfh7);
+ assign Ubxfh7 = (Acxfh7 & Gcxfh7);
+ assign Gcxfh7 = (S6wfh7 | Itvfh7);
+ assign Acxfh7 = (Q1wfh7 | Cz1gh7);
+ assign Obxfh7 = (U2xfh7 & Mcxfh7);
+ assign Mcxfh7 = (~(stdio_rx_tdata[4] & W1wfh7));
+ assign Q4xfh7 = (~(Tzrfh7 & C2wfh7));
+ assign W6sfh7 = (Scxfh7 & Ycxfh7);
+ assign Ycxfh7 = (~(Edxfh7 & Kdxfh7));
+ assign Kdxfh7 = (Qdxfh7 & Wdxfh7);
+ assign Wdxfh7 = (Cexfh7 & W7xfh7);
+ assign Cexfh7 = (S6wfh7 & Iexfh7);
+ assign Qdxfh7 = (Kpvfh7 & I5wfh7);
+ assign Edxfh7 = (Oexfh7 & Uexfh7);
+ assign Uexfh7 = (Afxfh7 & Gfxfh7);
+ assign Gfxfh7 = (~(stdio_rx_tdata[5] & W1wfh7));
+ assign Afxfh7 = (Mfxfh7 & Sfxfh7);
+ assign Mfxfh7 = (~(Yfxfh7 & G0wfh7));
+ assign Yfxfh7 = (A3xfh7 & M0wfh7);
+ assign Oexfh7 = (U2xfh7 & Egxfh7);
+ assign U2xfh7 = (Kgxfh7 & Qgxfh7);
+ assign Kgxfh7 = (E4wfh7 & Wgxfh7);
+ assign Scxfh7 = (~(Yzrfh7 & C2wfh7));
+ assign R6sfh7 = (Chxfh7 & Ihxfh7);
+ assign Ihxfh7 = (~(Ohxfh7 & Uhxfh7));
+ assign Uhxfh7 = (Aixfh7 & Gixfh7);
+ assign Gixfh7 = (Mixfh7 & Sixfh7);
+ assign Sixfh7 = (Kvwfh7 & K4wfh7);
+ assign Mixfh7 = (Yixfh7 & Unwfh7);
+ assign Unwfh7 = (~(Ejxfh7 & Miwfh7));
+ assign Ejxfh7 = (Kjxfh7 & Axwfh7);
+ assign Kjxfh7 = (~(R1sfh7 & M1sfh7));
+ assign Yixfh7 = (~(Itvfh7 & Ctvfh7));
+ assign Ctvfh7 = (!S6wfh7);
+ assign Itvfh7 = (Qjxfh7 & Q7wfh7);
+ assign Qjxfh7 = (~(C1sfh7 & X0sfh7));
+ assign Aixfh7 = (Wjxfh7 & Ckxfh7);
+ assign Ckxfh7 = (~(Uzvfh7 & Axwfh7));
+ assign Uzvfh7 = (Oqvfh7 & Ikxfh7);
+ assign Wjxfh7 = (Okxfh7 & Ukxfh7);
+ assign Ukxfh7 = (~(Mrvfh7 & Grvfh7));
+ assign Grvfh7 = (!I5wfh7);
+ assign Mrvfh7 = (Alxfh7 & G6wfh7);
+ assign Alxfh7 = (~(L2sfh7 & G2sfh7));
+ assign Okxfh7 = (~(Wyvfh7 & Qyvfh7));
+ assign Qyvfh7 = (!Yfwfh7);
+ assign Wyvfh7 = (Glxfh7 & Wgwfh7);
+ assign Glxfh7 = (~(A3sfh7 & V2sfh7));
+ assign Ohxfh7 = (Mlxfh7 & Slxfh7);
+ assign Slxfh7 = (Ylxfh7 & Emxfh7);
+ assign Emxfh7 = (Kmxfh7 & Qmxfh7);
+ assign Qmxfh7 = (~(Evvfh7 & Kvvfh7));
+ assign Kvvfh7 = (Wmxfh7 & E4vfh7);
+ assign E4vfh7 = (!Z3sfh7);
+ assign Wmxfh7 = (~(U3sfh7 & P3sfh7));
+ assign Kmxfh7 = (~(Yxvfh7 & Eyvfh7));
+ assign Eyvfh7 = (Cnxfh7 & Kavfh7);
+ assign Kavfh7 = (!T4sfh7);
+ assign Cnxfh7 = (~(O4sfh7 & J4sfh7));
+ assign Yxvfh7 = (!Inxfh7);
+ assign Ylxfh7 = (Onxfh7 & Unxfh7);
+ assign Unxfh7 = (~(Wvvfh7 & Cwvfh7));
+ assign Cwvfh7 = (Aoxfh7 & Wgvfh7);
+ assign Wgvfh7 = (!N5sfh7);
+ assign Aoxfh7 = (~(I5sfh7 & D5sfh7));
+ assign Onxfh7 = (~(Auvfh7 & Guvfh7));
+ assign Guvfh7 = (Goxfh7 & Invfh7);
+ assign Invfh7 = (!H6sfh7);
+ assign Goxfh7 = (~(C6sfh7 & X5sfh7));
+ assign Auvfh7 = (!Moxfh7);
+ assign Mlxfh7 = (Soxfh7 & Y0wfh7);
+ assign Y0wfh7 = (Yoxfh7 & Yiwfh7);
+ assign Yiwfh7 = (Epxfh7 & Qgxfh7);
+ assign Epxfh7 = (S6xfh7 & Czufh7);
+ assign Yoxfh7 = (Kpxfh7 & A3xfh7);
+ assign Kpxfh7 = (~(Miwfh7 & A0wfh7));
+ assign A0wfh7 = (~(Qpxfh7 | W1sfh7));
+ assign Miwfh7 = (~(W7xfh7 | Ozrfh7));
+ assign Soxfh7 = (Wpxfh7 & Cqxfh7);
+ assign Cqxfh7 = (Q1wfh7 | Oz1gh7);
+ assign Wpxfh7 = (~(stdio_rx_tdata[6] & W1wfh7));
+ assign Chxfh7 = (~(D0sfh7 & C2wfh7));
+ assign M6sfh7 = (C2wfh7 ? com_tx_tdata[7] : Iqxfh7);
+ assign C2wfh7 = (!Qgxfh7);
+ assign Qgxfh7 = (Wpsfh7 & Oqxfh7);
+ assign Oqxfh7 = (~(Uqxfh7 & Arxfh7));
+ assign Arxfh7 = (~(Grxfh7 & Mrxfh7));
+ assign Mrxfh7 = (~(Srxfh7 & Yrxfh7));
+ assign Iqxfh7 = (stdio_rx_tdata[7] & W1wfh7);
+ assign S0sfh7 = (~(Esxfh7 & Ksxfh7));
+ assign Esxfh7 = (Qsxfh7 & Wsxfh7);
+ assign N0sfh7 = (ahb_hready ? ahb_htrans[1] : Ctxfh7);
+ assign I0sfh7 = (~(Itxfh7 | W72gh7));
+ assign Itxfh7 = (~(Otxfh7 | A3xfh7));
+ assign Qpsfh7 = (~(Utxfh7 & Auxfh7));
+ assign Auxfh7 = (~(stdio_tx_tdata[7] & Guxfh7));
+ assign Utxfh7 = (Muxfh7 & Suxfh7);
+ assign Suxfh7 = (~(Yuxfh7 & com_rx_tdata[7]));
+ assign Muxfh7 = (~(Evxfh7 & Ottfh7));
+ assign Kpsfh7 = (~(Kvxfh7 & Qvxfh7));
+ assign Qvxfh7 = (~(stdio_tx_tdata[6] & Guxfh7));
+ assign Kvxfh7 = (Wvxfh7 & Cwxfh7);
+ assign Cwxfh7 = (~(Yuxfh7 & com_rx_tdata[6]));
+ assign Wvxfh7 = (~(Evxfh7 & Yutfh7));
+ assign Epsfh7 = (~(Iwxfh7 & Owxfh7));
+ assign Owxfh7 = (~(stdio_tx_tdata[5] & Guxfh7));
+ assign Iwxfh7 = (Uwxfh7 & Axxfh7);
+ assign Axxfh7 = (~(Yuxfh7 & com_rx_tdata[5]));
+ assign Uwxfh7 = (~(Evxfh7 & Iwtfh7));
+ assign Yosfh7 = (~(Gxxfh7 & Mxxfh7));
+ assign Mxxfh7 = (~(stdio_tx_tdata[4] & Guxfh7));
+ assign Gxxfh7 = (Sxxfh7 & Yxxfh7);
+ assign Yxxfh7 = (~(Yuxfh7 & com_rx_tdata[4]));
+ assign Sxxfh7 = (~(Evxfh7 & Sxtfh7));
+ assign Sosfh7 = (~(Eyxfh7 & Kyxfh7));
+ assign Kyxfh7 = (~(stdio_tx_tdata[3] & Guxfh7));
+ assign Eyxfh7 = (Qyxfh7 & Wyxfh7);
+ assign Wyxfh7 = (~(Yuxfh7 & com_rx_tdata[3]));
+ assign Qyxfh7 = (~(Evxfh7 & Cztfh7));
+ assign Mosfh7 = (~(Czxfh7 & Izxfh7));
+ assign Izxfh7 = (~(stdio_tx_tdata[2] & Guxfh7));
+ assign Czxfh7 = (Ozxfh7 & Uzxfh7);
+ assign Uzxfh7 = (~(Yuxfh7 & com_rx_tdata[2]));
+ assign Ozxfh7 = (~(Evxfh7 & M0ufh7));
+ assign Gosfh7 = (~(A0yfh7 & G0yfh7));
+ assign G0yfh7 = (~(stdio_tx_tdata[1] & Guxfh7));
+ assign A0yfh7 = (M0yfh7 & S0yfh7);
+ assign S0yfh7 = (~(Yuxfh7 & com_rx_tdata[1]));
+ assign M0yfh7 = (~(Evxfh7 & W1ufh7));
+ assign Aosfh7 = (~(Y0yfh7 & E1yfh7));
+ assign E1yfh7 = (~(stdio_tx_tdata[0] & Guxfh7));
+ assign Y0yfh7 = (K1yfh7 & Q1yfh7);
+ assign Q1yfh7 = (~(Yuxfh7 & com_rx_tdata[0]));
+ assign Yuxfh7 = (~(Guxfh7 | Y3xfh7));
+ assign K1yfh7 = (~(Evxfh7 & Q1tfh7));
+ assign Evxfh7 = (~(Guxfh7 | K4xfh7));
+ assign Guxfh7 = (~(W1yfh7 & stdio_tx_tready));
+ assign W1yfh7 = (Wpsfh7 & C2yfh7);
+ assign C2yfh7 = (~(I2yfh7 & K4xfh7));
+ assign I2yfh7 = (~(O2yfh7 & U2yfh7));
+ assign Unsfh7 = (~(A3yfh7 & G3yfh7));
+ assign G3yfh7 = (~(S0vfh7 & Wgwfh7));
+ assign Wgwfh7 = (!F3sfh7);
+ assign A3yfh7 = (M3yfh7 & S3yfh7);
+ assign S3yfh7 = (Y3yfh7 | Su1gh7);
+ assign M3yfh7 = (~(ahb_hrdata[15] & Eyufh7));
+ assign Onsfh7 = (~(E4yfh7 & K4yfh7));
+ assign K4yfh7 = (~(S0vfh7 & Qgwfh7));
+ assign Qgwfh7 = (!A3sfh7);
+ assign E4yfh7 = (Q4yfh7 & W4yfh7);
+ assign W4yfh7 = (Y3yfh7 | Mu1gh7);
+ assign Q4yfh7 = (~(ahb_hrdata[14] & Eyufh7));
+ assign Insfh7 = (~(C5yfh7 & I5yfh7));
+ assign I5yfh7 = (Wyufh7 | V2sfh7);
+ assign C5yfh7 = (O5yfh7 & U5yfh7);
+ assign U5yfh7 = (Y3yfh7 | Gu1gh7);
+ assign O5yfh7 = (~(ahb_hrdata[13] & Eyufh7));
+ assign Cnsfh7 = (~(A6yfh7 & G6yfh7));
+ assign G6yfh7 = (~(S0vfh7 & Czvfh7));
+ assign Czvfh7 = (!Kyrfh7);
+ assign A6yfh7 = (M6yfh7 & S6yfh7);
+ assign S6yfh7 = (Y3yfh7 | Au1gh7);
+ assign M6yfh7 = (~(ahb_hrdata[12] & Eyufh7));
+ assign Wmsfh7 = (~(Y6yfh7 & E7yfh7));
+ assign E7yfh7 = (~(S0vfh7 & G6wfh7));
+ assign G6wfh7 = (!Q2sfh7);
+ assign Y6yfh7 = (K7yfh7 & Q7yfh7);
+ assign Q7yfh7 = (Y3yfh7 | Ut1gh7);
+ assign K7yfh7 = (~(ahb_hrdata[11] & Eyufh7));
+ assign Qmsfh7 = (~(W7yfh7 & C8yfh7));
+ assign C8yfh7 = (~(S0vfh7 & A6wfh7));
+ assign A6wfh7 = (!L2sfh7);
+ assign W7yfh7 = (I8yfh7 & O8yfh7);
+ assign O8yfh7 = (Y3yfh7 | Ot1gh7);
+ assign I8yfh7 = (~(ahb_hrdata[10] & Eyufh7));
+ assign Kmsfh7 = (~(U8yfh7 & A9yfh7));
+ assign A9yfh7 = (Wyufh7 | G2sfh7);
+ assign U8yfh7 = (G9yfh7 & M9yfh7);
+ assign M9yfh7 = (Y3yfh7 | It1gh7);
+ assign G9yfh7 = (~(ahb_hrdata[9] & Eyufh7));
+ assign Emsfh7 = (~(S9yfh7 & Y9yfh7));
+ assign Y9yfh7 = (~(S0vfh7 & Srvfh7));
+ assign Srvfh7 = (!B2sfh7);
+ assign S9yfh7 = (Eayfh7 & Kayfh7);
+ assign Kayfh7 = (Y3yfh7 | Ct1gh7);
+ assign Eayfh7 = (~(ahb_hrdata[8] & Eyufh7));
+ assign Ylsfh7 = (~(Qayfh7 & Wayfh7));
+ assign Wayfh7 = (~(S0vfh7 & Axwfh7));
+ assign Axwfh7 = (!W1sfh7);
+ assign Qayfh7 = (Cbyfh7 & Ibyfh7);
+ assign Ibyfh7 = (~(Obyfh7 & Ottfh7));
+ assign Cbyfh7 = (~(ahb_hrdata[7] & Eyufh7));
+ assign Slsfh7 = (~(Ubyfh7 & Acyfh7));
+ assign Acyfh7 = (Wyufh7 | Ozrfh7);
+ assign Ubyfh7 = (Gcyfh7 & Mcyfh7);
+ assign Mcyfh7 = (~(Obyfh7 & Yutfh7));
+ assign Gcyfh7 = (~(ahb_hrdata[6] & Eyufh7));
+ assign Mlsfh7 = (~(Scyfh7 & Ycyfh7));
+ assign Ycyfh7 = (~(S0vfh7 & Ikxfh7));
+ assign Ikxfh7 = (!R1sfh7);
+ assign Scyfh7 = (Edyfh7 & Kdyfh7);
+ assign Kdyfh7 = (~(Obyfh7 & Iwtfh7));
+ assign Edyfh7 = (~(ahb_hrdata[5] & Eyufh7));
+ assign Glsfh7 = (~(Qdyfh7 & Wdyfh7));
+ assign Wdyfh7 = (~(S0vfh7 & Qpxfh7));
+ assign Qpxfh7 = (!M1sfh7);
+ assign Qdyfh7 = (Ceyfh7 & Ieyfh7);
+ assign Ieyfh7 = (~(Obyfh7 & Sxtfh7));
+ assign Ceyfh7 = (~(ahb_hrdata[4] & Eyufh7));
+ assign Alsfh7 = (~(Oeyfh7 & Ueyfh7));
+ assign Ueyfh7 = (~(S0vfh7 & Q7wfh7));
+ assign Q7wfh7 = (!H1sfh7);
+ assign Oeyfh7 = (Afyfh7 & Gfyfh7);
+ assign Gfyfh7 = (~(Obyfh7 & Cztfh7));
+ assign Afyfh7 = (~(ahb_hrdata[3] & Eyufh7));
+ assign Uksfh7 = (~(Mfyfh7 & Sfyfh7));
+ assign Sfyfh7 = (~(S0vfh7 & K7wfh7));
+ assign K7wfh7 = (!C1sfh7);
+ assign Mfyfh7 = (Yfyfh7 & Egyfh7);
+ assign Egyfh7 = (~(Obyfh7 & M0ufh7));
+ assign Yfyfh7 = (~(ahb_hrdata[2] & Eyufh7));
+ assign Oksfh7 = (~(Kgyfh7 & Qgyfh7));
+ assign Qgyfh7 = (Wyufh7 | X0sfh7);
+ assign Kgyfh7 = (Wgyfh7 & Chyfh7);
+ assign Chyfh7 = (~(Obyfh7 & W1ufh7));
+ assign Wgyfh7 = (~(ahb_hrdata[1] & Eyufh7));
+ assign Iksfh7 = (~(Ihyfh7 & Ohyfh7));
+ assign Ohyfh7 = (~(S0vfh7 & Otvfh7));
+ assign Otvfh7 = (!Pyrfh7);
+ assign Ihyfh7 = (Uhyfh7 & Aiyfh7);
+ assign Aiyfh7 = (~(Obyfh7 & Q1tfh7));
+ assign Obyfh7 = (~(Y3yfh7 & Giyfh7));
+ assign Giyfh7 = (~(Miyfh7 & Wyufh7));
+ assign Y3yfh7 = (Czufh7 & Qmvfh7);
+ assign Qmvfh7 = (~(Siyfh7 & Wyufh7));
+ assign Wyufh7 = (!S0vfh7);
+ assign Siyfh7 = (~(M0wfh7 & Q1wfh7));
+ assign Uhyfh7 = (~(ahb_hrdata[0] & Eyufh7));
+ assign Eyufh7 = (~(K4wfh7 | S0vfh7));
+ assign S0vfh7 = (Yiyfh7 & Wsxfh7);
+ assign ahb_htrans[1] = (~(Ctxfh7 | K72gh7));
+ assign Ctxfh7 = (!G92gh7);
+ assign Xzpfh7 = (~(Ejyfh7 & Kjyfh7));
+ assign Kjyfh7 = (~(Qjyfh7 & Yxsfh7));
+ assign Ejyfh7 = (~(Qbrfh7 & Wjyfh7));
+ assign O0qfh7 = (~(Ckyfh7 & Ikyfh7));
+ assign Ikyfh7 = (~(Qjyfh7 & G3tfh7));
+ assign Ckyfh7 = (~(Gcrfh7 & Wjyfh7));
+ assign F1qfh7 = (~(Okyfh7 & Ukyfh7));
+ assign Ukyfh7 = (~(Qjyfh7 & W4tfh7));
+ assign Okyfh7 = (~(Wcrfh7 & Wjyfh7));
+ assign W1qfh7 = (~(Alyfh7 & Glyfh7));
+ assign Glyfh7 = (~(Qjyfh7 & M6tfh7));
+ assign Alyfh7 = (~(Mdrfh7 & Wjyfh7));
+ assign N2qfh7 = (~(Mlyfh7 & Slyfh7));
+ assign Slyfh7 = (~(Qjyfh7 & Axsfh7));
+ assign Mlyfh7 = (~(Cerfh7 & Wjyfh7));
+ assign E3qfh7 = (~(Ylyfh7 & Emyfh7));
+ assign Emyfh7 = (~(Qjyfh7 & O2tfh7));
+ assign Ylyfh7 = (~(Serfh7 & Wjyfh7));
+ assign V3qfh7 = (~(Kmyfh7 & Qmyfh7));
+ assign Qmyfh7 = (~(Qjyfh7 & E4tfh7));
+ assign Kmyfh7 = (~(Ifrfh7 & Wjyfh7));
+ assign M4qfh7 = (~(Wmyfh7 & Cnyfh7));
+ assign Cnyfh7 = (~(Qjyfh7 & U5tfh7));
+ assign Wmyfh7 = (~(Yfrfh7 & Wjyfh7));
+ assign D5qfh7 = (~(Inyfh7 & Onyfh7));
+ assign Onyfh7 = (~(Qjyfh7 & K7tfh7));
+ assign Inyfh7 = (~(Ogrfh7 & Wjyfh7));
+ assign U5qfh7 = (~(Unyfh7 & Aoyfh7));
+ assign Aoyfh7 = (~(Qjyfh7 & U8tfh7));
+ assign Unyfh7 = (~(Ehrfh7 & Wjyfh7));
+ assign L6qfh7 = (~(Goyfh7 & Moyfh7));
+ assign Moyfh7 = (~(Qjyfh7 & Eatfh7));
+ assign Goyfh7 = (~(Uhrfh7 & Wjyfh7));
+ assign C7qfh7 = (~(Soyfh7 & Yoyfh7));
+ assign Yoyfh7 = (~(Qjyfh7 & Obtfh7));
+ assign Soyfh7 = (~(Kirfh7 & Wjyfh7));
+ assign T7qfh7 = (~(Epyfh7 & Kpyfh7));
+ assign Kpyfh7 = (~(Qjyfh7 & Yctfh7));
+ assign Epyfh7 = (~(Ajrfh7 & Wjyfh7));
+ assign K8qfh7 = (~(Qpyfh7 & Wpyfh7));
+ assign Wpyfh7 = (~(Qjyfh7 & Ietfh7));
+ assign Qpyfh7 = (~(Qjrfh7 & Wjyfh7));
+ assign B9qfh7 = (~(Cqyfh7 & Iqyfh7));
+ assign Iqyfh7 = (~(Qjyfh7 & Sftfh7));
+ assign Cqyfh7 = (~(Gkrfh7 & Wjyfh7));
+ assign S9qfh7 = (~(Oqyfh7 & Uqyfh7));
+ assign Uqyfh7 = (~(Qjyfh7 & Chtfh7));
+ assign Oqyfh7 = (~(Wkrfh7 & Wjyfh7));
+ assign Jaqfh7 = (~(Aryfh7 & Gryfh7));
+ assign Gryfh7 = (~(Qjyfh7 & Mitfh7));
+ assign Aryfh7 = (~(Mlrfh7 & Wjyfh7));
+ assign Abqfh7 = (~(Mryfh7 & Sryfh7));
+ assign Sryfh7 = (~(Qjyfh7 & Wjtfh7));
+ assign Mryfh7 = (~(Cmrfh7 & Wjyfh7));
+ assign Rbqfh7 = (~(Yryfh7 & Esyfh7));
+ assign Esyfh7 = (~(Qjyfh7 & Gltfh7));
+ assign Yryfh7 = (~(Smrfh7 & Wjyfh7));
+ assign Icqfh7 = (~(Ksyfh7 & Qsyfh7));
+ assign Qsyfh7 = (~(Qjyfh7 & Qmtfh7));
+ assign Ksyfh7 = (~(Inrfh7 & Wjyfh7));
+ assign Zcqfh7 = (~(Wsyfh7 & Ctyfh7));
+ assign Ctyfh7 = (~(Qjyfh7 & Aotfh7));
+ assign Wsyfh7 = (~(Ynrfh7 & Wjyfh7));
+ assign Qdqfh7 = (~(Ityfh7 & Otyfh7));
+ assign Otyfh7 = (~(Qjyfh7 & Kptfh7));
+ assign Ityfh7 = (~(Oorfh7 & Wjyfh7));
+ assign Heqfh7 = (~(Utyfh7 & Auyfh7));
+ assign Auyfh7 = (~(Qjyfh7 & Uqtfh7));
+ assign Utyfh7 = (~(Eprfh7 & Wjyfh7));
+ assign Yeqfh7 = (~(Guyfh7 & Muyfh7));
+ assign Muyfh7 = (~(Qjyfh7 & Estfh7));
+ assign Guyfh7 = (~(Uprfh7 & Wjyfh7));
+ assign Pfqfh7 = (~(Suyfh7 & Yuyfh7));
+ assign Yuyfh7 = (~(Qjyfh7 & Ottfh7));
+ assign Suyfh7 = (~(Kqrfh7 & Wjyfh7));
+ assign Ggqfh7 = (~(Evyfh7 & Kvyfh7));
+ assign Kvyfh7 = (~(Qjyfh7 & Yutfh7));
+ assign Evyfh7 = (~(Arrfh7 & Wjyfh7));
+ assign Xgqfh7 = (~(Qvyfh7 & Wvyfh7));
+ assign Wvyfh7 = (~(Qjyfh7 & Iwtfh7));
+ assign Qvyfh7 = (~(Qrrfh7 & Wjyfh7));
+ assign Ohqfh7 = (~(Cwyfh7 & Iwyfh7));
+ assign Iwyfh7 = (~(Qjyfh7 & Sxtfh7));
+ assign Cwyfh7 = (~(Gsrfh7 & Wjyfh7));
+ assign Fiqfh7 = (~(Owyfh7 & Uwyfh7));
+ assign Uwyfh7 = (~(Qjyfh7 & Cztfh7));
+ assign Owyfh7 = (~(Wsrfh7 & Wjyfh7));
+ assign Wiqfh7 = (~(Axyfh7 & Gxyfh7));
+ assign Gxyfh7 = (~(Qjyfh7 & M0ufh7));
+ assign Axyfh7 = (~(Mtrfh7 & Wjyfh7));
+ assign Njqfh7 = (~(Mxyfh7 & Sxyfh7));
+ assign Sxyfh7 = (~(Qjyfh7 & W1ufh7));
+ assign Mxyfh7 = (~(Curfh7 & Wjyfh7));
+ assign Ekqfh7 = (~(Yxyfh7 & Eyyfh7));
+ assign Eyyfh7 = (~(Qjyfh7 & Q1tfh7));
+ assign Qjyfh7 = (Kyyfh7 & Kjufh7);
+ assign Yxyfh7 = (~(Surfh7 & Wjyfh7));
+ assign Wjyfh7 = (~(Qyyfh7 & Wyyfh7));
+ assign Wyyfh7 = (Czyfh7 & Izyfh7);
+ assign Czyfh7 = (Ozyfh7 & Kjufh7);
+ assign Kjufh7 = (~(Uzyfh7 & A0zfh7));
+ assign A0zfh7 = (G0zfh7 & M0zfh7);
+ assign M0zfh7 = (S0zfh7 & Y0zfh7);
+ assign Y0zfh7 = (E1zfh7 & K1zfh7);
+ assign K1zfh7 = (W1ufh7 & Q1tfh7);
+ assign Q1tfh7 = (!Gr1gh7);
+ assign W1ufh7 = (!Mr1gh7);
+ assign E1zfh7 = (Cztfh7 & M0ufh7);
+ assign M0ufh7 = (!Sr1gh7);
+ assign Cztfh7 = (!Yr1gh7);
+ assign S0zfh7 = (Q1zfh7 & W1zfh7);
+ assign W1zfh7 = (Iwtfh7 & Sxtfh7);
+ assign Sxtfh7 = (!Es1gh7);
+ assign Iwtfh7 = (!Ks1gh7);
+ assign Q1zfh7 = (Ottfh7 & Yutfh7);
+ assign Yutfh7 = (!Qs1gh7);
+ assign Ottfh7 = (!Ws1gh7);
+ assign G0zfh7 = (C2zfh7 & I2zfh7);
+ assign I2zfh7 = (O2zfh7 & U2zfh7);
+ assign U2zfh7 = (Uqtfh7 & Estfh7);
+ assign Estfh7 = (!Ct1gh7);
+ assign Uqtfh7 = (!It1gh7);
+ assign O2zfh7 = (Aotfh7 & Kptfh7);
+ assign Kptfh7 = (!Ot1gh7);
+ assign Aotfh7 = (!Ut1gh7);
+ assign C2zfh7 = (A3zfh7 & G3zfh7);
+ assign G3zfh7 = (Gltfh7 & Qmtfh7);
+ assign Qmtfh7 = (!Au1gh7);
+ assign Gltfh7 = (!Gu1gh7);
+ assign A3zfh7 = (Mitfh7 & Wjtfh7);
+ assign Wjtfh7 = (!Mu1gh7);
+ assign Mitfh7 = (!Su1gh7);
+ assign Uzyfh7 = (M3zfh7 & S3zfh7);
+ assign S3zfh7 = (Y3zfh7 & E4zfh7);
+ assign E4zfh7 = (K4zfh7 & Q4zfh7);
+ assign Q4zfh7 = (Yxsfh7 & Axsfh7);
+ assign Axsfh7 = (!Yu1gh7);
+ assign Yxsfh7 = (!Ev1gh7);
+ assign K4zfh7 = (G3tfh7 & O2tfh7);
+ assign O2tfh7 = (!Kv1gh7);
+ assign G3tfh7 = (!Qv1gh7);
+ assign Y3zfh7 = (W4zfh7 & C5zfh7);
+ assign C5zfh7 = (W4tfh7 & E4tfh7);
+ assign E4tfh7 = (!Wv1gh7);
+ assign W4tfh7 = (!Cw1gh7);
+ assign W4zfh7 = (M6tfh7 & U5tfh7);
+ assign U5tfh7 = (!Iw1gh7);
+ assign M6tfh7 = (!Ow1gh7);
+ assign M3zfh7 = (I5zfh7 & O5zfh7);
+ assign O5zfh7 = (U5zfh7 & A6zfh7);
+ assign A6zfh7 = (U8tfh7 & K7tfh7);
+ assign K7tfh7 = (!Uw1gh7);
+ assign U8tfh7 = (!Ax1gh7);
+ assign U5zfh7 = (Obtfh7 & Eatfh7);
+ assign Eatfh7 = (!Gx1gh7);
+ assign Obtfh7 = (!Mx1gh7);
+ assign I5zfh7 = (G6zfh7 & M6zfh7);
+ assign M6zfh7 = (Ietfh7 & Yctfh7);
+ assign Yctfh7 = (!Sx1gh7);
+ assign Ietfh7 = (!Yx1gh7);
+ assign G6zfh7 = (Chtfh7 & Sftfh7);
+ assign Sftfh7 = (!Ey1gh7);
+ assign Chtfh7 = (!Ky1gh7);
+ assign Qyyfh7 = (~(S6zfh7 | Y6zfh7));
+ assign Vkqfh7 = (~(E7zfh7 & K7zfh7));
+ assign E7zfh7 = (Q7zfh7 & W7zfh7);
+ assign Mlqfh7 = (~(C8zfh7 & I8zfh7));
+ assign I8zfh7 = (O8zfh7 & Yrxfh7);
+ assign O8zfh7 = (U8zfh7 | Grxfh7);
+ assign C8zfh7 = (Uqxfh7 & Srxfh7);
+ assign Uqxfh7 = (A9zfh7 & G9zfh7);
+ assign G9zfh7 = (M9zfh7 & S9zfh7);
+ assign S9zfh7 = (Y9zfh7 & Eazfh7);
+ assign Y9zfh7 = (Kazfh7 & Sfxfh7);
+ assign A9zfh7 = (Qazfh7 & Wazfh7);
+ assign Wazfh7 = (Cbzfh7 & Ibzfh7);
+ assign Qazfh7 = (Yiyfh7 & Obzfh7);
+ assign Obzfh7 = (~(Ubzfh7 & W1wfh7));
+ assign W1wfh7 = (!Aczfh7);
+ assign Dmqfh7 = (~(Gczfh7 & Mczfh7));
+ assign Mczfh7 = (Sczfh7 | S32gh7);
+ assign Gczfh7 = (E4wfh7 | Otxfh7);
+ assign Umqfh7 = (~(Yczfh7 & Edzfh7));
+ assign Edzfh7 = (~(Kdzfh7 & Ubzfh7));
+ assign Yczfh7 = (Qdzfh7 | M32gh7);
+ assign Lnqfh7 = (~(Wdzfh7 & Cezfh7));
+ assign Cezfh7 = (~(Iezfh7 & Oezfh7));
+ assign Coqfh7 = (~(Ibzfh7 & Uezfh7));
+ assign Uezfh7 = (Afzfh7 | C22gh7);
+ assign Ibzfh7 = (~(Gfzfh7 & Mfzfh7));
+ assign Mfzfh7 = (Sfzfh7 & Yfzfh7);
+ assign Gfzfh7 = (stdio_rx_tvalid & com_tx_tready);
+ assign Toqfh7 = (~(M9zfh7 & Egzfh7));
+ assign Egzfh7 = (Afzfh7 | G02gh7);
+ assign M9zfh7 = (~(Y6zfh7 | Kgzfh7));
+ assign Kgzfh7 = (Qgzfh7 & Wgzfh7);
+ assign Wgzfh7 = (Chzfh7 & Qvsfh7);
+ assign Chzfh7 = (Ihzfh7 & Ozyfh7);
+ assign Qgzfh7 = (Ohzfh7 & Uhzfh7);
+ assign Uhzfh7 = (~(Aizfh7 & Gizfh7));
+ assign Ohzfh7 = (!Kpvfh7);
+ assign Kpvfh7 = (~(Kvsfh7 & Mizfh7));
+ assign Mizfh7 = (~(Sizfh7 & Yizfh7));
+ assign Yizfh7 = (Ejzfh7 & Kjzfh7);
+ assign Sizfh7 = (Iz1gh7 & Qy1gh7);
+ assign Y6zfh7 = (~(S6zfh7 | Kvsfh7));
+ assign Kvsfh7 = (!M0wfh7);
+ assign S6zfh7 = (~(Qjzfh7 & Wjzfh7));
+ assign Wjzfh7 = (Ckzfh7 & Ikzfh7);
+ assign Ckzfh7 = (Okzfh7 & Yusfh7);
+ assign Qjzfh7 = (Ukzfh7 & Alzfh7);
+ assign Ukzfh7 = (G0wfh7 & U8zfh7);
+ assign G0wfh7 = (Glzfh7 & Mlzfh7);
+ assign Mlzfh7 = (Slzfh7 & Ylzfh7);
+ assign Ylzfh7 = (Emzfh7 & Czufh7);
+ assign Emzfh7 = (K4wfh7 & Q1wfh7);
+ assign Slzfh7 = (Y3xfh7 & S6xfh7);
+ assign Glzfh7 = (Kmzfh7 & Qmzfh7);
+ assign Qmzfh7 = (Wmzfh7 & K4xfh7);
+ assign Wmzfh7 = (Sfxfh7 & Wgxfh7);
+ assign Kmzfh7 = (Aczfh7 & Srxfh7);
+ assign Kpqfh7 = (~(Yiyfh7 & Cnzfh7));
+ assign Cnzfh7 = (Qdzfh7 | U82gh7);
+ assign Yiyfh7 = (Inzfh7 & Onzfh7);
+ assign Onzfh7 = (Czufh7 & Q1wfh7);
+ assign Q1wfh7 = (~(Unzfh7 & Aozfh7));
+ assign Unzfh7 = (Gozfh7 & Mozfh7);
+ assign Mozfh7 = (!A92gh7);
+ assign Czufh7 = (~(Sozfh7 & Yozfh7));
+ assign Yozfh7 = (~(Epzfh7 | E72gh7));
+ assign Sozfh7 = (Kpzfh7 & Qpzfh7);
+ assign Inzfh7 = (Wpzfh7 & Cqzfh7);
+ assign Cqzfh7 = (~(Iqzfh7 & Oqzfh7));
+ assign Oqzfh7 = (!K4wfh7);
+ assign Wpzfh7 = (~(Miyfh7 & Uqzfh7));
+ assign Miyfh7 = (!S6xfh7);
+ assign Bqqfh7 = (~(Qjufh7 & Arzfh7));
+ assign Arzfh7 = (~(Grzfh7 & Iqzfh7));
+ assign Grzfh7 = (!Yusfh7);
+ assign Qjufh7 = (!Kyyfh7);
+ assign Kyyfh7 = (Mrzfh7 & Qy1gh7);
+ assign Mrzfh7 = (Srzfh7 & Yrzfh7);
+ assign Sqqfh7 = (~(Eszfh7 & Kszfh7));
+ assign Kszfh7 = (~(Qszfh7 & Ubzfh7));
+ assign Eszfh7 = (Qdzfh7 | G32gh7);
+ assign Jrqfh7 = (~(Wszfh7 & Ctzfh7));
+ assign Ctzfh7 = (Afzfh7 | A02gh7);
+ assign Asqfh7 = (~(W7zfh7 & Itzfh7));
+ assign Itzfh7 = (Afzfh7 | S02gh7);
+ assign W7zfh7 = (~(Otzfh7 & O2yfh7));
+ assign Otzfh7 = (stdio_tx_tready & U2yfh7);
+ assign Rsqfh7 = (~(Utzfh7 & Auzfh7));
+ assign Auzfh7 = (Afzfh7 | A62gh7);
+ assign Utzfh7 = (~(Guzfh7 & com_rx_tvalid));
+ assign Itqfh7 = (~(Muzfh7 & Suzfh7));
+ assign Suzfh7 = (Yuzfh7 & Evzfh7);
+ assign Evzfh7 = (~(Grxfh7 & Kvzfh7));
+ assign Kvzfh7 = (~(Qvzfh7 & Wvzfh7));
+ assign Wvzfh7 = (A3xfh7 | W72gh7);
+ assign Yuzfh7 = (Cwzfh7 & Iwzfh7);
+ assign Iwzfh7 = (~(Owzfh7 & O2yfh7));
+ assign Owzfh7 = (U2yfh7 & Uwzfh7);
+ assign Cwzfh7 = (~(Axzfh7 & Gxzfh7));
+ assign Gxzfh7 = (~(M0wfh7 & Mxzfh7));
+ assign Mxzfh7 = (Sxzfh7 | Alzfh7);
+ assign Muzfh7 = (Yxzfh7 & Eyzfh7);
+ assign Eyzfh7 = (Ikzfh7 | Kyzfh7);
+ assign Kyzfh7 = (!Uqzfh7);
+ assign Yxzfh7 = (Qyzfh7 | A32gh7);
+ assign Ztqfh7 = (~(Eazfh7 & Wyzfh7));
+ assign Wyzfh7 = (Afzfh7 | Y62gh7);
+ assign Eazfh7 = (~(Czzfh7 & Izzfh7));
+ assign Izzfh7 = (Ejzfh7 & Yrzfh7);
+ assign Ejzfh7 = (~(Cz1gh7 | Wy1gh7));
+ assign Czzfh7 = (Ozzfh7 & Iz1gh7);
+ assign Ozzfh7 = (Qy1gh7 & Kjzfh7);
+ assign Quqfh7 = (~(Wsxfh7 & Uzzfh7));
+ assign Uzzfh7 = (Afzfh7 | I52gh7);
+ assign Wsxfh7 = (~(A00gh7 & G00gh7));
+ assign G00gh7 = (~(C82gh7 | Iz1gh7));
+ assign A00gh7 = (Yrzfh7 & Aizfh7);
+ assign Hvqfh7 = (~(Izyfh7 | Ihzfh7));
+ assign Yvqfh7 = (~(M00gh7 & K7zfh7));
+ assign K7zfh7 = (~(S00gh7 & stdio_tx_tready));
+ assign M00gh7 = (Afzfh7 | W42gh7);
+ assign Pwqfh7 = (Y00gh7 & E10gh7);
+ assign E10gh7 = (Aizfh7 & Qvsfh7);
+ assign Y00gh7 = (C82gh7 & Yrzfh7);
+ assign Gxqfh7 = (~(K10gh7 & Ksxfh7));
+ assign Ksxfh7 = (Izyfh7 | Qvsfh7);
+ assign Qvsfh7 = (~(Q10gh7 & Iz1gh7));
+ assign Q10gh7 = (C82gh7 & Aizfh7);
+ assign Aizfh7 = (W10gh7 & C20gh7);
+ assign C20gh7 = (I20gh7 & Essfh7);
+ assign I20gh7 = (~(Cz1gh7 | Qy1gh7));
+ assign W10gh7 = (Wy1gh7 & Uz1gh7);
+ assign Izyfh7 = (~(Yrzfh7 & O20gh7));
+ assign O20gh7 = (~(Qy1gh7 & Srzfh7));
+ assign Srzfh7 = (!Ihzfh7);
+ assign Ihzfh7 = (~(U20gh7 & A30gh7));
+ assign A30gh7 = (Wy1gh7 & Gizfh7);
+ assign Gizfh7 = (!Iz1gh7);
+ assign U20gh7 = (Cz1gh7 & Kjzfh7);
+ assign Kjzfh7 = (G30gh7 & C82gh7);
+ assign G30gh7 = (Uz1gh7 & Essfh7);
+ assign Essfh7 = (!Oz1gh7);
+ assign Yrzfh7 = (~(M0wfh7 | Axzfh7));
+ assign M0wfh7 = (~(M30gh7 & S30gh7));
+ assign S30gh7 = (~(Q72gh7 | U52gh7));
+ assign M30gh7 = (G62gh7 & Y30gh7);
+ assign K10gh7 = (E40gh7 | Afzfh7);
+ assign Xxqfh7 = (K40gh7 & Gusfh7);
+ assign Gusfh7 = (!Q40gh7);
+ assign K40gh7 = (~(Sxzfh7 | Alzfh7));
+ assign Oyqfh7 = (~(W40gh7 & Yiufh7));
+ assign Yiufh7 = (~(Utsfh7 & Q40gh7));
+ assign Utsfh7 = (C50gh7 & I50gh7);
+ assign I50gh7 = (O50gh7 & Ozyfh7);
+ assign O50gh7 = (~(U50gh7 & A60gh7));
+ assign U50gh7 = (M6ufh7 & G60gh7);
+ assign C50gh7 = (Kaufh7 & Siufh7);
+ assign W40gh7 = (Afzfh7 | O52gh7);
+ assign Fzqfh7 = (~(M60gh7 & S60gh7));
+ assign S60gh7 = (Afzfh7 | G62gh7);
+ assign M60gh7 = (~(Sfzfh7 & com_rx_tvalid));
+ assign Sfzfh7 = (!Wgxfh7);
+ assign Wzqfh7 = (~(Y60gh7 & E70gh7));
+ assign E70gh7 = (Otxfh7 | K70gh7);
+ assign Y60gh7 = (~(Iezfh7 & Q70gh7));
+ assign N0rfh7 = (~(W70gh7 & C80gh7));
+ assign C80gh7 = (Yrxfh7 | Otxfh7);
+ assign Yrxfh7 = (~(W72gh7 & I80gh7));
+ assign W70gh7 = (Afzfh7 | S62gh7);
+ assign E1rfh7 = (!O80gh7);
+ assign O80gh7 = (Grxfh7 ? Qpvfh7 : U80gh7);
+ assign U80gh7 = (A90gh7 | Q42gh7);
+ assign V1rfh7 = (~(G90gh7 & M90gh7));
+ assign M90gh7 = (Grxfh7 ? E4xfh7 : S90gh7);
+ assign S90gh7 = (~(Y90gh7 & Ea0gh7));
+ assign G90gh7 = (Cbzfh7 & Kazfh7);
+ assign Kazfh7 = (~(Ka0gh7 & O2yfh7));
+ assign O2yfh7 = (~(Y3xfh7 | Sxzfh7));
+ assign Sxzfh7 = (!Siufh7);
+ assign Ka0gh7 = (!U2yfh7);
+ assign U2yfh7 = (~(Qa0gh7 & Wa0gh7));
+ assign Wa0gh7 = (Cb0gh7 & Ib0gh7);
+ assign Cb0gh7 = (Otsfh7 & Obufh7);
+ assign Qa0gh7 = (Ob0gh7 & A9ufh7);
+ assign Ob0gh7 = (com_rx_tdata[4] & com_rx_tdata[3]);
+ assign Cbzfh7 = (~(S00gh7 & Uwzfh7));
+ assign Uwzfh7 = (!stdio_tx_tready);
+ assign S00gh7 = (!K4xfh7);
+ assign K4xfh7 = (~(Ub0gh7 & Ac0gh7));
+ assign Ac0gh7 = (W42gh7 & Gc0gh7);
+ assign M2rfh7 = (!Mc0gh7);
+ assign Mc0gh7 = (Grxfh7 ? S6wfh7 : Sc0gh7);
+ assign Sc0gh7 = (A90gh7 | Y32gh7);
+ assign D3rfh7 = (!Yc0gh7);
+ assign Yc0gh7 = (Grxfh7 ? W7xfh7 : Ed0gh7);
+ assign Ed0gh7 = (~(Kd0gh7 & Qd0gh7));
+ assign U3rfh7 = (!Wd0gh7);
+ assign Wd0gh7 = (Grxfh7 ? I5wfh7 : Ce0gh7);
+ assign Ce0gh7 = (Ie0gh7 | U22gh7);
+ assign L4rfh7 = (!Oe0gh7);
+ assign Oe0gh7 = (Grxfh7 ? Yfwfh7 : Ue0gh7);
+ assign Ue0gh7 = (~(Af0gh7 & Gf0gh7));
+ assign C5rfh7 = (!Mf0gh7);
+ assign Mf0gh7 = (Grxfh7 ? Yf0gh7 : Sf0gh7);
+ assign Sf0gh7 = (~(Eg0gh7 & Kg0gh7));
+ assign T5rfh7 = (!Qg0gh7);
+ assign Qg0gh7 = (Grxfh7 ? Inxfh7 : Wg0gh7);
+ assign Wg0gh7 = (~(Af0gh7 & Ch0gh7));
+ assign Af0gh7 = (Y90gh7 | Evvfh7);
+ assign K6rfh7 = (!Ih0gh7);
+ assign Ih0gh7 = (Grxfh7 ? Uh0gh7 : Oh0gh7);
+ assign Oh0gh7 = (~(Ai0gh7 & Gi0gh7));
+ assign B7rfh7 = (!Mi0gh7);
+ assign Mi0gh7 = (Grxfh7 ? Moxfh7 : Si0gh7);
+ assign Si0gh7 = (Yi0gh7 | I82gh7);
+ assign S7rfh7 = (!Ej0gh7);
+ assign Ej0gh7 = (Grxfh7 ? Kvwfh7 : Moxfh7);
+ assign J8rfh7 = (~(Kj0gh7 & Qj0gh7));
+ assign Qj0gh7 = (Sczfh7 | Y02gh7);
+ assign Sczfh7 = (~(Otxfh7 & Wj0gh7));
+ assign Wj0gh7 = (~(A90gh7 & Kvwfh7));
+ assign A90gh7 = (U8zfh7 & E4xfh7);
+ assign Kj0gh7 = (Y6xfh7 | Otxfh7);
+ assign A9rfh7 = (~(Ck0gh7 & Sfxfh7));
+ assign Sfxfh7 = (~(Ik0gh7 & Ok0gh7));
+ assign Ok0gh7 = (~(Uk0gh7 | M62gh7));
+ assign Ck0gh7 = (Grxfh7 ? Iexfh7 : Al0gh7);
+ assign Al0gh7 = (~(Gl0gh7 & Ml0gh7));
+ assign R9rfh7 = (~(Afzfh7 | M62gh7));
+ assign Afzfh7 = (~(Sl0gh7 | Iezfh7));
+ assign Iezfh7 = (~(Yl0gh7 & Em0gh7));
+ assign Em0gh7 = (Km0gh7 & Qm0gh7);
+ assign Qm0gh7 = (~(Wm0gh7 & Wdufh7));
+ assign Wdufh7 = (!Cn0gh7);
+ assign Wm0gh7 = (Q40gh7 & Ozyfh7);
+ assign Km0gh7 = (In0gh7 & Qyzfh7);
+ assign Qyzfh7 = (~(On0gh7 & Un0gh7));
+ assign Un0gh7 = (~(stdio_rx_tvalid & Ao0gh7));
+ assign Ao0gh7 = (Wgxfh7 | com_tx_tready);
+ assign On0gh7 = (Go0gh7 & Yfzfh7);
+ assign In0gh7 = (~(Mo0gh7 & So0gh7));
+ assign So0gh7 = (A60gh7 & G60gh7);
+ assign G60gh7 = (Yo0gh7 & Qssfh7);
+ assign Yo0gh7 = (Obufh7 ? com_rx_tdata[0] : Ctsfh7);
+ assign A60gh7 = (~(Ep0gh7 | Ihufh7));
+ assign Ihufh7 = (com_rx_tdata[0] & Ctsfh7);
+ assign Ep0gh7 = (!Ib0gh7);
+ assign Mo0gh7 = (Kaufh7 & M6ufh7);
+ assign Kaufh7 = (!Kp0gh7);
+ assign Yl0gh7 = (Qp0gh7 & Wp0gh7);
+ assign Qp0gh7 = (Qsxfh7 & Q7zfh7);
+ assign Q7zfh7 = (Cq0gh7 | Uqzfh7);
+ assign Uqzfh7 = (stdio_tx_tvalid & stdio_tx_tready);
+ assign Cq0gh7 = (Ikzfh7 & S6xfh7);
+ assign S6xfh7 = (~(Ub0gh7 & Iq0gh7));
+ assign Iq0gh7 = (~(Gc0gh7 | W42gh7));
+ assign Gc0gh7 = (!C52gh7);
+ assign Ub0gh7 = (Oq0gh7 & Uq0gh7);
+ assign Ikzfh7 = (~(Ar0gh7 & Gr0gh7));
+ assign Ar0gh7 = (M02gh7 & Mr0gh7);
+ assign Qsxfh7 = (Sr0gh7 | Iqzfh7);
+ assign Sr0gh7 = (K4wfh7 & Yusfh7);
+ assign Yusfh7 = (~(Yr0gh7 & Es0gh7));
+ assign Es0gh7 = (Ks0gh7 & Qpzfh7);
+ assign Ks0gh7 = (~(Epzfh7 | I52gh7));
+ assign Epzfh7 = (!Qs0gh7);
+ assign Yr0gh7 = (Ws0gh7 & Oq0gh7);
+ assign Ws0gh7 = (Ct0gh7 & E72gh7);
+ assign K4wfh7 = (~(It0gh7 & Ot0gh7));
+ assign It0gh7 = (Q72gh7 & G62gh7);
+ assign Sl0gh7 = (~(Ut0gh7 & Qdzfh7));
+ assign Qdzfh7 = (~(Au0gh7 & Otxfh7));
+ assign Otxfh7 = (!Grxfh7);
+ assign Au0gh7 = (~(U8zfh7 & Srxfh7));
+ assign Srxfh7 = (~(Gl0gh7 | Gu0gh7));
+ assign Gu0gh7 = (!Iexfh7);
+ assign Iexfh7 = (~(Mu0gh7 & Su0gh7));
+ assign Mu0gh7 = (~(Yu0gh7 | U82gh7));
+ assign Gl0gh7 = (~(Ev0gh7 & Kv0gh7));
+ assign Kv0gh7 = (Egxfh7 & E4wfh7);
+ assign E4wfh7 = (~(Qv0gh7 & Wv0gh7));
+ assign Wv0gh7 = (Cw0gh7 & S32gh7);
+ assign Cw0gh7 = (~(Oezfh7 | M32gh7));
+ assign Qv0gh7 = (Su0gh7 & U82gh7);
+ assign Egxfh7 = (Iw0gh7 & Ow0gh7);
+ assign Ow0gh7 = (Y6xfh7 & Moxfh7);
+ assign Moxfh7 = (~(Uw0gh7 & Gr0gh7));
+ assign Gr0gh7 = (Ax0gh7 & Gx0gh7);
+ assign Ax0gh7 = (~(Mx0gh7 | Sx0gh7));
+ assign Uw0gh7 = (S02gh7 & Yx0gh7);
+ assign Yx0gh7 = (!M02gh7);
+ assign Y6xfh7 = (~(Ey0gh7 & Ky0gh7));
+ assign Ky0gh7 = (~(Qy0gh7 | I22gh7));
+ assign Ey0gh7 = (~(Wy0gh7 | Mx0gh7));
+ assign Mx0gh7 = (!A02gh7);
+ assign Iw0gh7 = (Yi0gh7 & Kvwfh7);
+ assign Kvwfh7 = (~(Cz0gh7 & Iz0gh7));
+ assign Cz0gh7 = (~(Gf0gh7 | Y02gh7));
+ assign Yi0gh7 = (~(Eg0gh7 | Evvfh7));
+ assign Evvfh7 = (!Yf0gh7);
+ assign Yf0gh7 = (~(Oz0gh7 & Uz0gh7));
+ assign Oz0gh7 = (A01gh7 & Ch0gh7);
+ assign Ch0gh7 = (!W12gh7);
+ assign Eg0gh7 = (Ai0gh7 | Wvvfh7);
+ assign Wvvfh7 = (!Uh0gh7);
+ assign Uh0gh7 = (~(G01gh7 & M01gh7));
+ assign M01gh7 = (~(S01gh7 | I82gh7));
+ assign Ai0gh7 = (~(Yfwfh7 & Inxfh7));
+ assign Inxfh7 = (~(Y01gh7 & E11gh7));
+ assign E11gh7 = (Q12gh7 & Gi0gh7);
+ assign Yfwfh7 = (~(Y01gh7 & K11gh7));
+ assign K11gh7 = (K12gh7 & Kg0gh7);
+ assign Y01gh7 = (Uz0gh7 & W12gh7);
+ assign Uz0gh7 = (G01gh7 & Q11gh7);
+ assign Q11gh7 = (W11gh7 & I82gh7);
+ assign Ev0gh7 = (~(C21gh7 | Y90gh7));
+ assign Y90gh7 = (~(Ie0gh7 & I5wfh7));
+ assign I5wfh7 = (~(I21gh7 & Iz0gh7));
+ assign Iz0gh7 = (G01gh7 & O21gh7);
+ assign O21gh7 = (U21gh7 & I82gh7);
+ assign G01gh7 = (A31gh7 & G02gh7);
+ assign I21gh7 = (Y02gh7 & Gf0gh7);
+ assign Gf0gh7 = (!E12gh7);
+ assign Ie0gh7 = (~(Kd0gh7 | Oqvfh7));
+ assign Oqvfh7 = (!W7xfh7);
+ assign W7xfh7 = (~(G31gh7 & M31gh7));
+ assign G31gh7 = (~(Qd0gh7 | U22gh7));
+ assign Kd0gh7 = (~(Qpvfh7 & S6wfh7));
+ assign S6wfh7 = (~(S31gh7 & M31gh7));
+ assign M31gh7 = (Y31gh7 & E41gh7);
+ assign S31gh7 = (U22gh7 & Qd0gh7);
+ assign Qd0gh7 = (!O22gh7);
+ assign Qpvfh7 = (~(K41gh7 & Q41gh7));
+ assign Q41gh7 = (Y32gh7 & Ea0gh7);
+ assign C21gh7 = (!E4xfh7);
+ assign E4xfh7 = (W41gh7 & C51gh7);
+ assign C51gh7 = (~(K41gh7 & I51gh7));
+ assign I51gh7 = (~(Ea0gh7 | Y32gh7));
+ assign Ea0gh7 = (!E42gh7);
+ assign K41gh7 = (O51gh7 & U51gh7);
+ assign W41gh7 = (~(A61gh7 & G61gh7));
+ assign G61gh7 = (~(S01gh7 | G02gh7));
+ assign S01gh7 = (!M61gh7);
+ assign A61gh7 = (A31gh7 & I82gh7);
+ assign A31gh7 = (S61gh7 & Y61gh7);
+ assign Y61gh7 = (M02gh7 & S02gh7);
+ assign S61gh7 = (Gx0gh7 & A02gh7);
+ assign U8zfh7 = (E71gh7 & K71gh7);
+ assign K71gh7 = (~(I80gh7 | Q71gh7));
+ assign I80gh7 = (!A3xfh7);
+ assign A3xfh7 = (~(W71gh7 & C81gh7));
+ assign C81gh7 = (K42gh7 & I81gh7);
+ assign E71gh7 = (Qvzfh7 & K70gh7);
+ assign K70gh7 = (O81gh7 & U81gh7);
+ assign U81gh7 = (~(Ik0gh7 & A91gh7));
+ assign A91gh7 = (M62gh7 & Uk0gh7);
+ assign Ik0gh7 = (G91gh7 & A62gh7);
+ assign O81gh7 = (~(M91gh7 & S91gh7));
+ assign M91gh7 = (~(Oezfh7 | S32gh7));
+ assign Qvzfh7 = (Y91gh7 & Ea1gh7);
+ assign Ea1gh7 = (~(Ka1gh7 & Qa1gh7));
+ assign Qa1gh7 = (~(Wa1gh7 | Y62gh7));
+ assign Y91gh7 = (~(Cb1gh7 & Ib1gh7));
+ assign Ib1gh7 = (~(Ob1gh7 | G32gh7));
+ assign Iarfh7 = (~(Ub1gh7 & Ac1gh7));
+ assign Ac1gh7 = (~(com_rx_tvalid & Go0gh7));
+ assign Go0gh7 = (~(Okzfh7 & Wgxfh7));
+ assign Wgxfh7 = (~(W71gh7 & Gc1gh7));
+ assign Gc1gh7 = (Q42gh7 & Q70gh7);
+ assign W71gh7 = (O51gh7 & Mc1gh7);
+ assign O51gh7 = (Sc1gh7 & Yc1gh7);
+ assign Okzfh7 = (!Guzfh7);
+ assign Ub1gh7 = (Ut0gh7 & Ed1gh7);
+ assign Ed1gh7 = (~(Kd1gh7 & Q40gh7));
+ assign Q40gh7 = (~(Qd1gh7 & Wd1gh7));
+ assign Wd1gh7 = (Ce1gh7 & Ie1gh7);
+ assign Ie1gh7 = (~(com_rx_tdata[2] & Grsfh7));
+ assign Grsfh7 = (!com_rx_tdata[0]);
+ assign Ce1gh7 = (~(A9ufh7 | M6ufh7));
+ assign M6ufh7 = (Musfh7 & Otsfh7);
+ assign Otsfh7 = (!com_rx_tdata[2]);
+ assign A9ufh7 = (com_rx_tdata[1] & com_rx_tdata[0]);
+ assign Qd1gh7 = (~(Ctsfh7 | Oe1gh7));
+ assign Kd1gh7 = (~(Axzfh7 | Alzfh7));
+ assign Axzfh7 = (!Ozyfh7);
+ assign Ozyfh7 = (~(Ue1gh7 & Af1gh7));
+ assign Af1gh7 = (Musfh7 & Ctsfh7);
+ assign Ctsfh7 = (!com_rx_tdata[3]);
+ assign Musfh7 = (!com_rx_tdata[1]);
+ assign Ue1gh7 = (~(Oe1gh7 | com_rx_tdata[0]));
+ assign Oe1gh7 = (~(Gf1gh7 & Ib0gh7));
+ assign Ib0gh7 = (~(com_rx_tdata[6] | com_rx_tdata[7]));
+ assign Gf1gh7 = (Qssfh7 & Obufh7);
+ assign Obufh7 = (!com_rx_tdata[5]);
+ assign Qssfh7 = (!com_rx_tdata[4]);
+ assign Ut0gh7 = (Mf1gh7 | Siufh7);
+ assign Siufh7 = (com_rx_tvalid & com_rx_tready);
+ assign Mf1gh7 = (Alzfh7 & Y3xfh7);
+ assign Y3xfh7 = (~(Sf1gh7 & Yf1gh7));
+ assign Yf1gh7 = (~(Uk0gh7 | A62gh7));
+ assign Uk0gh7 = (!S62gh7);
+ assign Sf1gh7 = (G91gh7 & M62gh7);
+ assign G91gh7 = (Eg1gh7 & Kg1gh7);
+ assign Kg1gh7 = (Qg1gh7 & Uq0gh7);
+ assign Qg1gh7 = (~(Wg1gh7 | Q72gh7));
+ assign Eg1gh7 = (Ch1gh7 & G62gh7);
+ assign Ch1gh7 = (U52gh7 & O52gh7);
+ assign Alzfh7 = (Cn0gh7 & Kp0gh7);
+ assign Kp0gh7 = (~(Ot0gh7 & Ih1gh7));
+ assign Ih1gh7 = (~(Q72gh7 | G62gh7));
+ assign Ot0gh7 = (U52gh7 & Y30gh7);
+ assign Y30gh7 = (Oh1gh7 & Uh1gh7);
+ assign Uh1gh7 = (Ai1gh7 & S62gh7);
+ assign Ai1gh7 = (Uq0gh7 & Ct0gh7);
+ assign Oh1gh7 = (Gi1gh7 & O52gh7);
+ assign Gi1gh7 = (A62gh7 & M62gh7);
+ assign Cn0gh7 = (~(Mi1gh7 & Si1gh7));
+ assign Si1gh7 = (~(Wg1gh7 | O52gh7));
+ assign Wg1gh7 = (!Ct0gh7);
+ assign Mi1gh7 = (Yi1gh7 & Uq0gh7);
+ assign Uq0gh7 = (Ej1gh7 & Kj1gh7);
+ assign Kj1gh7 = (Qpzfh7 & Qs0gh7);
+ assign Ej1gh7 = (I52gh7 & E72gh7);
+ assign Zarfh7 = (~(Qj1gh7 & Wdzfh7));
+ assign Wdzfh7 = (~(Q71gh7 & Grxfh7));
+ assign Grxfh7 = (com_tx_tready & com_tx_tvalid);
+ assign Q71gh7 = (Wj1gh7 & Ck1gh7);
+ assign Ck1gh7 = (Ik1gh7 & Ok1gh7);
+ assign Ok1gh7 = (~(Qy0gh7 | C22gh7));
+ assign Ik1gh7 = (A02gh7 & I22gh7);
+ assign Wj1gh7 = (Uk1gh7 & Al1gh7);
+ assign Uk1gh7 = (Qpzfh7 & Y62gh7);
+ assign Qj1gh7 = (Wp0gh7 & Wszfh7);
+ assign Wszfh7 = (~(Gl1gh7 & Guzfh7));
+ assign Guzfh7 = (Cb1gh7 & Ml1gh7);
+ assign Ml1gh7 = (G32gh7 & Ob1gh7);
+ assign Ob1gh7 = (!A32gh7);
+ assign Cb1gh7 = (Aozfh7 & A92gh7);
+ assign Aozfh7 = (Sl1gh7 & Yl1gh7);
+ assign Sl1gh7 = (U82gh7 & Em1gh7);
+ assign Gl1gh7 = (stdio_rx_tvalid & Yfzfh7);
+ assign Yfzfh7 = (!com_rx_tvalid);
+ assign Wp0gh7 = (Ubzfh7 | Aczfh7);
+ assign Aczfh7 = (~(Qszfh7 | Kdzfh7));
+ assign Kdzfh7 = (Km1gh7 & S91gh7);
+ assign S91gh7 = (Qm1gh7 & Su0gh7);
+ assign Su0gh7 = (Wm1gh7 & Yl1gh7);
+ assign Yl1gh7 = (Cn1gh7 & Sc1gh7);
+ assign Sc1gh7 = (Y31gh7 & In1gh7);
+ assign Y31gh7 = (Al1gh7 & Qs0gh7);
+ assign Qs0gh7 = (~(On1gh7 | Wa1gh7));
+ assign Wa1gh7 = (~(Un1gh7 & Ao1gh7));
+ assign Ao1gh7 = (~(Ml0gh7 | Qy0gh7));
+ assign Un1gh7 = (A02gh7 & C22gh7);
+ assign On1gh7 = (!Y62gh7);
+ assign Wm1gh7 = (A92gh7 & Gozfh7);
+ assign Qm1gh7 = (U82gh7 & M32gh7);
+ assign Km1gh7 = (S32gh7 & Oezfh7);
+ assign Oezfh7 = (!O82gh7);
+ assign Qszfh7 = (Go1gh7 & Gx0gh7);
+ assign Gx0gh7 = (~(Wy0gh7 | Ml0gh7));
+ assign Ml0gh7 = (!I22gh7);
+ assign Wy0gh7 = (~(Ka1gh7 & Mo1gh7));
+ assign Mo1gh7 = (Y62gh7 & C22gh7);
+ assign Ka1gh7 = (Al1gh7 & Qpzfh7);
+ assign Qpzfh7 = (In1gh7 & E41gh7);
+ assign E41gh7 = (Cn1gh7 & Yc1gh7);
+ assign Yc1gh7 = (So1gh7 & Yo1gh7);
+ assign Yo1gh7 = (Em1gh7 & Gozfh7);
+ assign Gozfh7 = (A32gh7 & G32gh7);
+ assign Em1gh7 = (!Yu0gh7);
+ assign Yu0gh7 = (~(Ep1gh7 & M32gh7));
+ assign Ep1gh7 = (S32gh7 & O82gh7);
+ assign So1gh7 = (U82gh7 & A92gh7);
+ assign Cn1gh7 = (U51gh7 & Mc1gh7);
+ assign Mc1gh7 = (Y32gh7 & E42gh7);
+ assign U51gh7 = (~(Q70gh7 | I81gh7));
+ assign I81gh7 = (!Q42gh7);
+ assign Q70gh7 = (!K42gh7);
+ assign In1gh7 = (O22gh7 & U22gh7);
+ assign Al1gh7 = (Kpzfh7 & E72gh7);
+ assign Kpzfh7 = (Kp1gh7 & Oq0gh7);
+ assign Oq0gh7 = (Yi1gh7 & O52gh7);
+ assign Yi1gh7 = (Qp1gh7 & Wp1gh7);
+ assign Wp1gh7 = (Cq1gh7 & M62gh7);
+ assign Cq1gh7 = (S62gh7 & E40gh7);
+ assign E40gh7 = (!Q72gh7);
+ assign Qp1gh7 = (Iq1gh7 & G62gh7);
+ assign Iq1gh7 = (U52gh7 & A62gh7);
+ assign Kp1gh7 = (Ct0gh7 & I52gh7);
+ assign Ct0gh7 = (W42gh7 & C52gh7);
+ assign Go1gh7 = (~(Qy0gh7 | A02gh7));
+ assign Qy0gh7 = (~(Oq1gh7 & M02gh7));
+ assign Oq1gh7 = (~(Mr0gh7 | Sx0gh7));
+ assign Sx0gh7 = (~(Uq1gh7 & G02gh7));
+ assign Uq1gh7 = (I82gh7 & M61gh7);
+ assign M61gh7 = (W11gh7 & U21gh7);
+ assign U21gh7 = (W12gh7 & A01gh7);
+ assign A01gh7 = (~(Gi0gh7 | Kg0gh7));
+ assign Kg0gh7 = (!Q12gh7);
+ assign Gi0gh7 = (!K12gh7);
+ assign W11gh7 = (Y02gh7 & E12gh7);
+ assign Mr0gh7 = (!S02gh7);
+ assign Ubzfh7 = (stdio_rx_tready & stdio_rx_tvalid);
+ assign Ivrfh7 = (Iqzfh7 & Yvrfh7);
+ assign Iqzfh7 = (Ar1gh7 & ahb_hready);
+ assign Ar1gh7 = (~(G92gh7 | K72gh7));
+
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ M92gh7 <= 1'b0;
+ end
+ else
+ begin
+ M92gh7 <= N0sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ma2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ma2gh7 <= Bqqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Pb2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Pb2gh7 <= Kpqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Sc2gh7 <= 1'b1;
+ end
+ else
+ begin
+ Sc2gh7 <= R9rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ud2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ud2gh7 <= Zarfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ue2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ue2gh7 <= Lnqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xf2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xf2gh7 <= Mlqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xg2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xg2gh7 <= Umqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ai2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ai2gh7 <= Dmqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Dj2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Dj2gh7 <= A9rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Fk2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Fk2gh7 <= J8rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Hl2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Hl2gh7 <= B7rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Jm2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Jm2gh7 <= S7rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ln2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ln2gh7 <= Rsqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Oo2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Oo2gh7 <= Jrqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rp2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rp2gh7 <= Iarfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rq2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rq2gh7 <= Dksfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rr2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rr2gh7 <= Yjsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rs2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rs2gh7 <= Tjsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rt2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rt2gh7 <= Ojsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ru2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ru2gh7 <= Jjsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rv2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rv2gh7 <= Ejsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rw2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rw2gh7 <= Zisfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rx2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rx2gh7 <= Quqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Uy2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Uy2gh7 <= Toqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xz2gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xz2gh7 <= M2rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ A13gh7 <= 1'b0;
+ end
+ else
+ begin
+ A13gh7 <= E1rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ D23gh7 <= 1'b0;
+ end
+ else
+ begin
+ D23gh7 <= T5rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ F33gh7 <= 1'b0;
+ end
+ else
+ begin
+ F33gh7 <= C5rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ H43gh7 <= 1'b0;
+ end
+ else
+ begin
+ H43gh7 <= L4rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ J53gh7 <= 1'b0;
+ end
+ else
+ begin
+ J53gh7 <= U3rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ L63gh7 <= 1'b0;
+ end
+ else
+ begin
+ L63gh7 <= Fzqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ O73gh7 <= 1'b0;
+ end
+ else
+ begin
+ O73gh7 <= Coqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ R83gh7 <= 1'b0;
+ end
+ else
+ begin
+ R83gh7 <= Sqqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ U93gh7 <= 1'b0;
+ end
+ else
+ begin
+ U93gh7 <= Itqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xa3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xa3gh7 <= Wzqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ac3gh7 <= 1'b1;
+ end
+ else
+ begin
+ Ac3gh7 <= I0sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Wc3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wc3gh7 <= N0rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Zd3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Zd3gh7 <= Yvqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Cf3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Cf3gh7 <= Oyqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Fg3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Fg3gh7 <= Xxqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ih3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ih3gh7 <= Hvqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Li3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Li3gh7 <= Gxqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Oj3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Oj3gh7 <= Asqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Rk3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Rk3gh7 <= K6rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Tl3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Tl3gh7 <= Pwqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Wm3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wm3gh7 <= Ztqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Zn3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Zn3gh7 <= Uisfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Cp3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Cp3gh7 <= S0sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Dq3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Dq3gh7 <= S0sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Fr3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Fr3gh7 <= V1rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Is3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Is3gh7 <= D3rfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Lt3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Lt3gh7 <= Vkqfh7;
+ end
+ always @(posedge Iqsfh7) Lu3gh7 <= M6sfh7;
+ always @(posedge Iqsfh7) Pv3gh7 <= W6sfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Tw3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Tw3gh7 <= Ekqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ux3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ux3gh7 <= Kisfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Wy3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wy3gh7 <= Fdsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Yz3gh7 <= 1'b0;
+ end
+ else
+ begin
+ Yz3gh7 <= Zdsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ A14gh7 <= 1'b0;
+ end
+ else
+ begin
+ A14gh7 <= Tesfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ D24gh7 <= 1'b0;
+ end
+ else
+ begin
+ D24gh7 <= Nfsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ G34gh7 <= 1'b0;
+ end
+ else
+ begin
+ G34gh7 <= Hgsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ J44gh7 <= 1'b0;
+ end
+ else
+ begin
+ J44gh7 <= Bhsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ M54gh7 <= 1'b0;
+ end
+ else
+ begin
+ M54gh7 <= Vhsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ P64gh7 <= 1'b0;
+ end
+ else
+ begin
+ P64gh7 <= W1qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ R74gh7 <= 1'b0;
+ end
+ else
+ begin
+ R74gh7 <= Xzpfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ T84gh7 <= 1'b0;
+ end
+ else
+ begin
+ T84gh7 <= Pisfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ W94gh7 <= 1'b0;
+ end
+ else
+ begin
+ W94gh7 <= M4qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ya4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ya4gh7 <= C7qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ac4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ac4gh7 <= S9qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Cd4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Cd4gh7 <= Icqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ee4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ee4gh7 <= Yeqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ff4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ff4gh7 <= Ohqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Gg4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Gg4gh7 <= Qcsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ih4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ih4gh7 <= Njqfh7;
+ end
+ always @(posedge Iqsfh7) Ji4gh7 <= Gosfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Nj4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Nj4gh7 <= Oksfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Sk4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Sk4gh7 <= Kdsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ul4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ul4gh7 <= Xgqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Vm4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Vm4gh7 <= Eesfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xn4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xn4gh7 <= Heqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Yo4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Yo4gh7 <= Yesfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Bq4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Bq4gh7 <= Rbqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Dr4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Dr4gh7 <= Sfsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Gs4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Gs4gh7 <= B9qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ It4gh7 <= 1'b0;
+ end
+ else
+ begin
+ It4gh7 <= Mgsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Lu4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Lu4gh7 <= L6qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Nv4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Nv4gh7 <= Ghsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Qw4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Qw4gh7 <= V3qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Sx4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Sx4gh7 <= Aisfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Vy4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Vy4gh7 <= F1qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xz4gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xz4gh7 <= K8sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ D15gh7 <= 1'b0;
+ end
+ else
+ begin
+ D15gh7 <= E9sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ J25gh7 <= 1'b1;
+ end
+ else
+ begin
+ J25gh7 <= Insfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ P35gh7 <= 1'b1;
+ end
+ else
+ begin
+ P35gh7 <= Kmsfh7;
+ end
+ always @(posedge Iqsfh7) U45gh7 <= Epsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Y55gh7 <= 1'b0;
+ end
+ else
+ begin
+ Y55gh7 <= Mlsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ D75gh7 <= 1'b0;
+ end
+ else
+ begin
+ D75gh7 <= Adsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ F85gh7 <= 1'b0;
+ end
+ else
+ begin
+ F85gh7 <= Fiqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ G95gh7 <= 1'b0;
+ end
+ else
+ begin
+ G95gh7 <= Udsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ia5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ia5gh7 <= Pfqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Jb5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Jb5gh7 <= Oesfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Mc5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Mc5gh7 <= Zcqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Od5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Od5gh7 <= Ifsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Re5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Re5gh7 <= Jaqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Tf5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Tf5gh7 <= Cgsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Wg5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Wg5gh7 <= T7qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Yh5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Yh5gh7 <= Wgsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Bj5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Bj5gh7 <= D5qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Dk5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Dk5gh7 <= Qhsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Gl5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Gl5gh7 <= N2qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Im5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Im5gh7 <= U8sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ On5gh7 <= 1'b1;
+ end
+ else
+ begin
+ On5gh7 <= Unsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Uo5gh7 <= 1'b1;
+ end
+ else
+ begin
+ Uo5gh7 <= Wmsfh7;
+ end
+ always @(posedge Iqsfh7) Aq5gh7 <= Qpsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Er5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Er5gh7 <= Ylsfh7;
+ end
+ always @(posedge Iqsfh7) Js5gh7 <= Sosfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Nt5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Nt5gh7 <= Alsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Su5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Su5gh7 <= Vcsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Uv5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Uv5gh7 <= Wiqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Vw5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Vw5gh7 <= Pdsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Xx5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Xx5gh7 <= Ggqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Yy5gh7 <= 1'b0;
+ end
+ else
+ begin
+ Yy5gh7 <= Jesfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ B06gh7 <= 1'b0;
+ end
+ else
+ begin
+ B06gh7 <= Qdqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ D16gh7 <= 1'b0;
+ end
+ else
+ begin
+ D16gh7 <= Dfsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ G26gh7 <= 1'b0;
+ end
+ else
+ begin
+ G26gh7 <= Abqfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ I36gh7 <= 1'b0;
+ end
+ else
+ begin
+ I36gh7 <= Xfsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ L46gh7 <= 1'b0;
+ end
+ else
+ begin
+ L46gh7 <= K8qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ N56gh7 <= 1'b0;
+ end
+ else
+ begin
+ N56gh7 <= Rgsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Q66gh7 <= 1'b0;
+ end
+ else
+ begin
+ Q66gh7 <= U5qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ S76gh7 <= 1'b0;
+ end
+ else
+ begin
+ S76gh7 <= Lhsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ V86gh7 <= 1'b0;
+ end
+ else
+ begin
+ V86gh7 <= E3qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ X96gh7 <= 1'b0;
+ end
+ else
+ begin
+ X96gh7 <= Fisfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ab6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ab6gh7 <= O0qfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Cc6gh7 <= 1'b1;
+ end
+ else
+ begin
+ Cc6gh7 <= F8sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Id6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Id6gh7 <= Z8sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Oe6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Oe6gh7 <= Onsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Uf6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Uf6gh7 <= Qmsfh7;
+ end
+ always @(posedge Iqsfh7) Ah6gh7 <= Kpsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ei6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Ei6gh7 <= Slsfh7;
+ end
+ always @(posedge Iqsfh7) Jj6gh7 <= Mosfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Nk6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Nk6gh7 <= Uksfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Sl6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Sl6gh7 <= A8sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ym6gh7 <= 1'b1;
+ end
+ else
+ begin
+ Ym6gh7 <= P8sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Eo6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Eo6gh7 <= J9sfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Kp6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Kp6gh7 <= Cnsfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Qq6gh7 <= 1'b1;
+ end
+ else
+ begin
+ Qq6gh7 <= Emsfh7;
+ end
+ always @(posedge Iqsfh7) Vr6gh7 <= Cbsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Vs6gh7 <= 1'b1;
+ end
+ else
+ begin
+ Vs6gh7 <= T9sfh7;
+ end
+ always @(posedge Iqsfh7) Bu6gh7 <= Hbsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Bv6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Bv6gh7 <= Y9sfh7;
+ end
+ always @(posedge Iqsfh7) Hw6gh7 <= Rbsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Hx6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Hx6gh7 <= Iasfh7;
+ end
+ always @(posedge Iqsfh7) Ny6gh7 <= Wbsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Nz6gh7 <= 1'b0;
+ end
+ else
+ begin
+ Nz6gh7 <= Nasfh7;
+ end
+ always @(posedge Iqsfh7) T07gh7 <= Bcsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ T17gh7 <= 1'b0;
+ end
+ else
+ begin
+ T17gh7 <= Sasfh7;
+ end
+ always @(posedge Iqsfh7) Z27gh7 <= Lcsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Z37gh7 <= 1'b1;
+ end
+ else
+ begin
+ Z37gh7 <= O9sfh7;
+ end
+ always @(posedge Iqsfh7) F57gh7 <= B7sfh7;
+ always @(posedge Iqsfh7) J67gh7 <= Yosfh7;
+ always @(posedge Iqsfh7) N77gh7 <= Mbsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ N87gh7 <= 1'b0;
+ end
+ else
+ begin
+ N87gh7 <= Dasfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ T97gh7 <= 1'b0;
+ end
+ else
+ begin
+ T97gh7 <= Glsfh7;
+ end
+ always @(posedge Iqsfh7) Ya7gh7 <= Aosfh7;
+ always @(posedge Iqsfh7) Cc7gh7 <= Gcsfh7;
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Cd7gh7 <= 1'b1;
+ end
+ else
+ begin
+ Cd7gh7 <= Xasfh7;
+ end
+ always @(posedge Iqsfh7 or negedge Wpsfh7) if (~Wpsfh7) begin
+ Ie7gh7 <= 1'b1;
+ end
+ else
+ begin
+ Ie7gh7 <= Iksfh7;
+ end
+ always @(posedge Iqsfh7) Nf7gh7 <= L7sfh7;
+ always @(posedge Iqsfh7) Rg7gh7 <= V7sfh7;
+ always @(posedge Iqsfh7) Vh7gh7 <= Q7sfh7;
+ always @(posedge Iqsfh7) Zi7gh7 <= G7sfh7;
+ always @(posedge Iqsfh7) Dk7gh7 <= R6sfh7;
+endmodule
+
+/* Design Summary
+ modules: 1
+ udps: 0
+ mod flatinsts: 0
+ udp flatinsts: 0
+ nodes: 1943 (0)
+ node widths: 2119 (0)
+ process: 173 (0)
+ gates: 0 (0)
+ contassigns: 1818 (0)
+ ports: 27 (0)
+ modinsts: 0 (0)
+ udpinsts: 0 (0)
+ portconnects: 0 (0)
+*/
+
+// END: VCS tokens
+// Currnet Allocated Virtual Memory Size: 203.73 MB
+// ===================
+// DESIGN STATISTICS
+// ===================
+//
+// No. of design lines (note: includes comments and blank lines) 4726
+//
+// Static<!> Elaborated<@> Size(KB)
+// ------ ---------- --------
+// No. of all modules (module+interface+package+program): 1 1 0
+// No. of module instances: 1 1 0
+// No. of all processes: 173 173 0
+// No. of all nodes (variable+net): 1943 1943 0
+// No. of constants 430 430 0
+// No. of scalar nets: 1756 1756 0
+// No. of vector nets: 14 14 0
+// No. of scalar regs/logics: 173 173 0
+// No. of always blocks: 173 173 0
+// No. of operators: 2933 2933 0
+// No. of concatenations: 4 4 0
+// No. of bit selects: 234 234 0
+// No. of part selects: 1 1 0
+// No. of non-blocking assignments: 322 322 0
+// No. of continuous assignments: 1818 1818 0
+//
+// No. of top level modules/programs/packages/interfaces: 1
+// modules: 1
+// No. of module+udp ports: 27
+//
+// Footnotes:
+// ---------
+// <!> No. of unique instances of a construct as it appears in the source.
+// <@> No. of instances of a construct when the design is elaborated.
+// K, M, B: Counted in thousands, millions and billions (if big numbers are present)
+//
+// <#> Multiple specify blocks in the SAME module are combined and counted
+// as ONE block.
diff --git a/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v b/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..7b8967c18e34a77bb98084ede844e99853f3e47c
--- /dev/null
+++ b/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
@@ -0,0 +1,103 @@
+//-----------------------------------------------------------------------------
+// top-level soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+
+ module ADPcontrol_v1_0 #
+ (
+ // Users to add parameters here
+ parameter PROMPT_CHAR = "]"
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Ports of Axi Slave Bus Interface com_rx
+ input wire ahb_hclk,
+ input wire ahb_hresetn,
+
+ output wire com_rx_tready,
+ input wire [7 : 0] com_rx_tdata,
+ input wire com_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface com_tx
+ output wire com_tx_tvalid,
+ output wire [7 : 0] com_tx_tdata,
+ input wire com_tx_tready,
+
+ // Ports of Axi Slave Bus Interface stdio_rx
+ output wire stdio_rx_tready,
+ input wire [7 : 0] stdio_rx_tdata,
+ input wire stdio_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface stdio_tx
+ output wire stdio_tx_tvalid,
+ output wire [7 : 0] stdio_tx_tdata,
+ input wire stdio_tx_tready,
+
+ output wire [7 : 0] gpo8,
+ input wire [7 : 0] gpi8,
+
+ output wire [31:0] ahb_haddr ,
+ output wire [ 2:0] ahb_hburst ,
+ output wire ahb_hmastlock,
+ output wire [ 3:0] ahb_hprot ,
+ output wire [ 2:0] ahb_hsize ,
+ output wire [ 1:0] ahb_htrans ,
+ output wire [31:0] ahb_hwdata ,
+ output wire ahb_hwrite ,
+ input wire [31:0] ahb_hrdata ,
+ input wire ahb_hready ,
+ input wire ahb_hresp
+ );
+
+ // Add user logic here
+
+ADPmanager
+ #(.PROMPT_CHAR (PROMPT_CHAR))
+ ADPmanager(
+ .HCLK (ahb_hclk ),
+ .HRESETn (ahb_hresetn ),
+ .HADDR32_o (ahb_haddr ),
+ .HBURST3_o (ahb_hburst ),
+ .HMASTLOCK_o (ahb_hmastlock ),
+ .HPROT4_o (ahb_hprot ),
+ .HSIZE3_o (ahb_hsize ),
+ .HTRANS2_o (ahb_htrans ),
+ .HWDATA32_o (ahb_hwdata ),
+ .HWRITE_o (ahb_hwrite ),
+ .HRDATA32_i (ahb_hrdata ),
+ .HREADY_i (ahb_hready ),
+ .HRESP_i (ahb_hresp ),
+ .GPO8_o (gpo8 ),
+ .GPI8_i (gpi8 ),
+ .COMRX_TREADY_o(com_rx_tready),
+ .COMRX_TDATA_i(com_rx_tdata),
+ .COMRX_TVALID_i(com_rx_tvalid),
+ .STDRX_TREADY_o(stdio_rx_tready),
+ .STDRX_TDATA_i(stdio_rx_tdata),
+ .STDRX_TVALID_i(stdio_rx_tvalid),
+ .COMTX_TVALID_o(com_tx_tvalid),
+ .COMTX_TDATA_o(com_tx_tdata),
+ .COMTX_TREADY_i(com_tx_tready),
+ .STDTX_TVALID_o(stdio_tx_tvalid),
+ .STDTX_TDATA_o(stdio_tx_tdata),
+ .STDTX_TREADY_i(stdio_tx_tready)
+
+ );
+
+
+endmodule
diff --git a/IPLIB/ADPcontrol_v1_0/ADPmanager.v b/IPLIB/ADPcontrol_v1_0/ADPmanager.v
new file mode 100755
index 0000000000000000000000000000000000000000..f4747ae3006625177bd065d731cdf0604d7334e9
--- /dev/null
+++ b/IPLIB/ADPcontrol_v1_0/ADPmanager.v
@@ -0,0 +1,786 @@
+//-----------------------------------------------------------------------------
+// soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+
+//`define ADPBASIC 1
+
+module ADPmanager // AHB initiator interface
+ #(parameter PROMPT_CHAR = "]"
+ )
+ ( input wire HCLK,
+ input wire HRESETn,
+ output wire [31:0] HADDR32_o,
+ output wire [ 2:0] HBURST3_o,
+ output wire HMASTLOCK_o,
+ output wire [ 3:0] HPROT4_o,
+ output wire [ 2:0] HSIZE3_o,
+ output wire [ 1:0] HTRANS2_o,
+ output wire [31:0] HWDATA32_o,
+ output wire HWRITE_o,
+ input wire [31:0] HRDATA32_i,
+ input wire HREADY_i,
+ input wire HRESP_i,
+// COMIO interface
+ output wire [ 7:0] GPO8_o,
+ input wire [ 7:0] GPI8_i,
+// input wire COM_RXE_i,
+ input wire [ 7:0] COMRX_TDATA_i,
+ input wire COMRX_TVALID_i,
+ output wire COMRX_TREADY_o,
+// input wire COM_TXF_i,
+ output wire [ 7:0] COMTX_TDATA_o,
+ output wire COMTX_TVALID_o,
+ input wire COMTX_TREADY_i,
+// STDIO interface
+// input wire STDOUT_RXE_i,
+ input wire [ 7:0] STDRX_TDATA_i,
+ input wire STDRX_TVALID_i,
+ output wire STDRX_TREADY_o,
+// input wire STDIN_TXF_i
+ output wire [ 7:0] STDTX_TDATA_o,
+ output wire STDTX_TVALID_o,
+ input wire STDTX_TREADY_i
+);
+
+wire COM_RXE_i = !COMRX_TVALID_i;
+wire COM_TXF_i = !COMTX_TREADY_i;
+
+//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o;
+//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o;
+
+
+wire STD_TXF_i = !STDTX_TREADY_i;
+wire STD_RXE_i = !STDRX_TVALID_i;
+
+`ifdef ADPBASIC
+ localparam BANNERHEX = 32'h50c1ab01;
+`else
+ localparam BANNERHEX = 32'h50c1ab02;
+`endif
+
+localparam CMD_bad = 4'b0000;
+localparam CMD_A = 4'b0001; // set address
+`ifndef ADPBASIC
+localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++
+localparam CMD_M = 4'b1010; // set read mask
+localparam CMD_P = 4'b1011; // Poll hardware (count)
+localparam CMD_V = 4'b1100; // match value
+localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++
+`endif
+localparam CMD_C = 4'b1001; // Control
+localparam CMD_R = 4'b0010; // read word, addr++
+localparam CMD_S = 4'b0011; // Status/STDIN
+localparam CMD_W = 4'b0100; // write word, addr++
+localparam CMD_X = 4'b0101; // exit
+
+
+function FNvalid_adp_entry; // Escape char
+input [7:0] char8;
+ FNvalid_adp_entry = (char8[7:0] == 8'h1b);
+endfunction
+
+function [3:0] FNvalid_cmd;
+input [7:0] char8;
+case (char8[7:0])
+"A": FNvalid_cmd = CMD_A;
+"a": FNvalid_cmd = CMD_A;
+"C": FNvalid_cmd = CMD_C;
+"c": FNvalid_cmd = CMD_C;
+"R": FNvalid_cmd = CMD_R;
+"r": FNvalid_cmd = CMD_R;
+"S": FNvalid_cmd = CMD_S;
+"s": FNvalid_cmd = CMD_S;
+"W": FNvalid_cmd = CMD_W;
+"w": FNvalid_cmd = CMD_W;
+"X": FNvalid_cmd = CMD_X;
+"x": FNvalid_cmd = CMD_X;
+`ifndef ADPBASIC
+"B": FNvalid_cmd = CMD_B;
+"b": FNvalid_cmd = CMD_B;
+"M": FNvalid_cmd = CMD_M;
+"m": FNvalid_cmd = CMD_M;
+"P": FNvalid_cmd = CMD_P;
+"p": FNvalid_cmd = CMD_P;
+"V": FNvalid_cmd = CMD_V;
+"v": FNvalid_cmd = CMD_V;
+"Z": FNvalid_cmd = CMD_Z;
+"z": FNvalid_cmd = CMD_Z;
+`endif
+default:
+ FNvalid_cmd = 0;
+endcase
+endfunction
+
+function FNvalid_space; // space or tab char
+input [7:0] char8;
+ FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09));
+endfunction
+
+function FNnull; // space or tab char
+input [7:0] char8;
+ FNnull = (char8[7:0] == 8'h00);
+endfunction
+
+function FNexit; // EOF
+input [7:0] char8;
+ FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00));
+endfunction
+
+function FNvalid_EOL; // CR or LF
+input [7:0] char8;
+ FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d));
+endfunction
+
+function FNuppercase;
+input [7:0] char8;
+ FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8);
+endfunction
+
+function [63:0] FNBuild_param64_hexdigit;
+input [63:0] param64;
+input [7:0] char8;
+case (char8[7:0])
+"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64
+" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64
+"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64
+"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64
+"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000};
+"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001};
+"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010};
+"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011};
+"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100};
+"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101};
+"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110};
+"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111};
+"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000};
+"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001};
+"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010};
+"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011};
+"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100};
+"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101};
+"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110};
+"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111};
+"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010};
+"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011};
+"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100};
+"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101};
+"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110};
+"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111};
+default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged
+endcase
+endfunction
+
+function [63:0] FNBuild_param64_byte;
+input [63:0] param64;
+input [7:0] byte;
+ FNBuild_param64_byte = {byte[7:0], param64[63:08]};
+endfunction
+
+function [31:0] FNBuild_param32_hexdigit;
+input [31:0] param32;
+input [7:0] char8;
+case (char8[7:0])
+"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32
+" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32
+"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32
+"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32
+"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000};
+"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001};
+"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010};
+"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011};
+"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100};
+"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101};
+"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110};
+"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111};
+"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000};
+"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001};
+"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010};
+"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011};
+"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100};
+"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101};
+"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110};
+"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111};
+"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010};
+"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011};
+"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100};
+"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101};
+"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110};
+"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111};
+default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged
+endcase
+endfunction
+
+function [31:0] FNBuild_param32_byte;
+input [31:0] param32;
+input [7:0] byte;
+ FNBuild_param32_byte = {byte[7:0], param32[31:08]};
+endfunction
+
+
+
+function [7:0] FNmap_hex_digit;
+input [3:0] nibble;
+case (nibble[3:0])
+4'b0000: FNmap_hex_digit = "0";
+4'b0001: FNmap_hex_digit = "1";
+4'b0010: FNmap_hex_digit = "2";
+4'b0011: FNmap_hex_digit = "3";
+4'b0100: FNmap_hex_digit = "4";
+4'b0101: FNmap_hex_digit = "5";
+4'b0110: FNmap_hex_digit = "6";
+4'b0111: FNmap_hex_digit = "7";
+4'b1000: FNmap_hex_digit = "8";
+4'b1001: FNmap_hex_digit = "9";
+4'b1010: FNmap_hex_digit = "a";
+4'b1011: FNmap_hex_digit = "b";
+4'b1100: FNmap_hex_digit = "c";
+4'b1101: FNmap_hex_digit = "d";
+4'b1110: FNmap_hex_digit = "e";
+4'b1111: FNmap_hex_digit = "f";
+default: FNmap_hex_digit = "0";
+endcase
+endfunction
+
+
+// as per Vivado synthesis mapping
+`ifdef ADPFSMDESIGN
+localparam ADP_WRITEHEX = 6'b000000 ;
+localparam ADP_WRITEHEXS = 6'b000001 ;
+localparam ADP_WRITEHEX9 = 6'b000010 ;
+localparam ADP_WRITEHEX8 = 6'b000011 ;
+localparam ADP_WRITEHEX7 = 6'b000100 ;
+localparam ADP_WRITEHEX6 = 6'b000101 ;
+localparam ADP_WRITEHEX5 = 6'b000110 ;
+localparam ADP_WRITEHEX4 = 6'b000111 ;
+localparam ADP_WRITEHEX3 = 6'b001000 ;
+localparam ADP_WRITEHEX2 = 6'b001001 ;
+localparam ADP_WRITEHEX1 = 6'b001010 ;
+localparam ADP_WRITEHEX0 = 6'b001011 ;
+localparam ADP_LINEACK = 6'b001101 ;
+localparam ADP_LINEACK2 = 6'b110010 ;
+localparam ADP_PROMPT = 6'b001110 ;
+localparam ADP_IOCHK = 6'b001111 ;
+localparam ADP_RXCMD = 6'b010000 ;
+localparam ADP_RXPARAM = 6'b010010 ;
+localparam ADP_ACTION = 6'b010011 ;
+localparam ADP_READ = 6'b010001 ;
+localparam ADP_SYSCHK = 6'b010100 ;
+localparam ADP_STDIN = 6'b010101 ;
+localparam ADP_SYSCTL = 6'b010110 ;
+localparam ADP_WRITE = 6'b010111 ;
+localparam ADP_EXIT = 6'b011000 ;
+localparam STD_IOCHK = 6'b011001 ;
+localparam STD_RXD1 = 6'b011010 ;
+localparam STD_RXD2 = 6'b011011 ;
+localparam STD_TXD1 = 6'b011101 ;
+localparam STD_TXD2 = 6'b011110 ;
+localparam ADP_BCTRL = 6'b011111 ;
+localparam ADP_BREADB0 = 6'b100000 ;
+localparam ADP_BREADB1 = 6'b100001 ;
+localparam ADP_BREADB2 = 6'b100010 ;
+localparam ADP_BREADB3 = 6'b100011 ;
+localparam ADP_BWRITE = 6'b100100 ;
+localparam ADP_POLL = 6'b100101 ;
+localparam ADP_POLL1 = 6'b100110 ;
+localparam ADP_POLL2 = 6'b100111 ;
+localparam ADP_ZCTRL = 6'b101110 ;
+localparam ADP_ZWRITE = 6'b101111 ;
+localparam ADP_ECHOCMD = 6'b110000 ;
+localparam ADP_ECHOCMDSP = 6'b110001 ;
+localparam ADP_UNKNOWN = 6'b101000 ;
+localparam ADP_STDOUT = 6'b101010 ;
+localparam ADP_STDOUT1 = 6'b101011 ;
+localparam ADP_STDOUT2 = 6'b101100 ;
+localparam ADP_STDOUT3 = 6'b101101 ;
+reg [5:0] adp_state ;
+`else
+// one-hot encoded explicitly
+localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000
+localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001
+localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010
+localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011
+localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100
+localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101
+localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110
+localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111
+localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000
+localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001
+localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010
+localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011
+localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001101
+localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b110010
+localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110
+localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111
+localparam ADP_RXCMD = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000
+localparam ADP_RXPARAM = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010010
+localparam ADP_ACTION = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010011
+localparam ADP_READ = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010001
+localparam ADP_SYSCHK = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100
+localparam ADP_STDIN = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101
+localparam ADP_SYSCTL = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110
+localparam ADP_WRITE = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111
+localparam ADP_EXIT = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000
+localparam STD_IOCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001
+localparam STD_RXD1 = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010
+localparam STD_RXD2 = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011
+localparam STD_TXD1 = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011101
+localparam STD_TXD2 = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011110
+localparam ADP_BCTRL = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011111
+localparam ADP_BREADB0 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b100000
+localparam ADP_BREADB1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100001
+localparam ADP_BREADB2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100010
+localparam ADP_BREADB3 = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100011
+localparam ADP_BWRITE = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100100
+localparam ADP_POLL = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100101
+localparam ADP_POLL1 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100110
+localparam ADP_POLL2 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100111
+localparam ADP_ZCTRL = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b101110
+localparam ADP_ZWRITE = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101111
+localparam ADP_ECHOCMD = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b110000
+localparam ADP_ECHOCMDSP = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b110001
+localparam ADP_UNKNOWN = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101000
+localparam ADP_STDOUT = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101010
+localparam ADP_STDOUT1 = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101011
+localparam ADP_STDOUT2 = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101100
+localparam ADP_STDOUT3 = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101101
+reg [47:0] adp_state ;
+`endif
+
+reg [31:0] adp_bus_data;
+reg banner ;
+reg com_tx_req ;
+reg [7:0] com_tx_byte ;
+reg com_rx_ack ;
+reg std_tx_req ;
+reg [ 7:0] std_tx_byte;
+reg std_rx_ack ;
+reg adp_bus_req ;
+reg adp_bus_write ;
+reg [7:0] adp_cmd ;
+reg [31:0] adp_param ;
+reg [31:0] adp_addr ;
+reg adp_addr_inc;
+reg [31:0] adp_sys ;
+
+assign GPO8_o = adp_sys[7:0];
+
+// ADP RX stream
+wire com_rx_req = COMRX_TVALID_i;
+wire [ 7:0] com_rx_byte = COMRX_TDATA_i;
+assign COMRX_TREADY_o = com_rx_ack;
+// ADP TX stream
+wire com_tx_ack = COMTX_TREADY_i;
+assign COMTX_TDATA_o = com_tx_byte;
+assign COMTX_TVALID_o = com_tx_req;
+// STD RX stream (from STDOUT)
+wire std_rx_req = STDRX_TVALID_i;
+wire [ 7:0] std_rx_byte = STDRX_TDATA_i;
+assign STDRX_TREADY_o = std_rx_ack;
+// STD TX stream (to STDIN)
+wire std_tx_ack = STDTX_TREADY_i;
+assign STDTX_TDATA_o = std_tx_byte;
+assign STDTX_TVALID_o = std_tx_req;
+
+//AMBA AHB master as "stream" interface
+reg ahb_dphase;
+wire ahb_aphase = adp_bus_req & !ahb_dphase;
+wire adp_bus_ack = ahb_dphase & HREADY_i;
+// control pipe
+always @(posedge HCLK or negedge HRESETn)
+ if(!HRESETn)
+ ahb_dphase <= 0;
+ else if (HREADY_i)
+ ahb_dphase <= (ahb_aphase);
+
+assign HADDR32_o = adp_addr;
+assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer;
+assign HMASTLOCK_o = 1'b0;
+assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1};
+assign HSIZE3_o[2:0] = {1'b0, 2'b10};
+assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq
+assign HWDATA32_o = adp_bus_data;
+assign HWRITE_o = adp_bus_write;
+
+
+`ifndef ADPBASIC
+//reg [63:0] adp_bctrl64;
+reg [31:0] adp_bctrl;
+reg [31:0] adp_val;
+reg [31:0] adp_mask;
+reg [31:0] adp_poll;
+reg [31:0] adp_count;
+reg adp_count_dec ;
+wire adp_delay_done;
+wire adp_bctrl_done;
+wire adp_bctrl_zero;
+wire poll2_loop_next;
+`endif
+
+// ADP_control flags in the 'C' control field
+wire adp_disable;
+wire adp_stdin_wait;
+
+// commnon interface handshake terms
+wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o;
+wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i;
+wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o;
+wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i;
+wire adp_bus_done = (adp_bus_req & adp_bus_ack);
+
+// common task to set up for next state
+task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner)
+// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end
+ begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end
+endtask
+task ADP_PROMPT_next; // prepare prompt TX
+ begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end
+endtask
+task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion
+ begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end
+endtask
+task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion
+ begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end
+endtask
+
+task ADP_hexdigit_next; // output nibble
+input [3:0] nibble;
+ begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
+endtask
+task ADP_txchar_next; // output char
+input [7:0] byte;
+ begin com_tx_req<= 1; com_tx_byte <= byte; end
+endtask
+
+task com_rx_nxt; com_rx_ack <=1; endtask
+
+function FNcount_down_zero_next; // param about to be zero
+input [31:0] counter;
+ FNcount_down_zero_next = !(|counter[31:1]);
+endfunction
+
+always @(posedge HCLK or negedge HRESETn)
+ if(!HRESETn) begin
+ adp_state <= ADP_WRITEHEX ;
+ adp_bus_data <= BANNERHEX;
+ banner <= 1; // start-up HEX message
+ com_tx_req <= 0; // default no TX req
+ com_rx_ack <= 0; // default no RX ack
+ std_tx_req <= 0; // default no TX req
+ std_rx_ack <= 0; // default no RX ack
+ adp_bus_req <= 0; // default no bus transaction
+ adp_cmd <= 0;
+ adp_param <= 0;
+ adp_addr <= 0;
+ adp_addr_inc <= 0;
+ adp_bus_write<= 0;
+`ifndef ADPBASIC
+ adp_count <= 0;
+ adp_count_dec<= 0;
+ adp_val <= 0;
+ adp_mask <= 0;
+ adp_sys <= 0;
+`endif
+ end else begin // default states
+ adp_state <= adp_state; // default to hold current state
+ com_tx_req <= 0; // default no TX req
+ com_rx_ack <= 0; // default no RX ack
+ std_tx_req <= 0; // default no TX req
+ std_rx_ack <= 0; // default no RX ack
+ adp_bus_req <= 0; // default no bus transaction
+ adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++
+ adp_addr_inc <= 0;
+`ifndef ADPBASIC
+ adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param--
+ adp_count_dec<= 0;
+`endif
+ case (adp_state)
+// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>>
+ STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
+ if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN
+// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
+ else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
+ STD_TXD1: // get STD out char
+ if (std_rx_done)
+ begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end
+ else std_rx_ack <= 1; // extend
+ STD_TXD2: // output char to ADP channel
+ if (com_tx_done) begin adp_state <= STD_IOCHK; end
+ else com_tx_req <= 1; // extend
+ STD_RXD1: // read rx char and check for ADP entry else STDIN **
+ if (com_rx_done) begin
+ if (FNvalid_adp_entry(com_rx_byte))
+ begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt
+ else if (std_tx_ack)
+ begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end
+ else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked
+ end else com_rx_ack <= 1; // extend
+ STD_RXD2: // get STD in char
+ if (std_tx_done) begin adp_state <= STD_IOCHK; end
+ else std_tx_req <= 1; // extend
+
+// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>>
+ ADP_PROMPT: // transition after reset deassertion
+ if (com_tx_done) begin adp_state <= ADP_IOCHK; end
+ else com_tx_req <= 1; // extend
+
+ ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
+ if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
+ else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+
+// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>>
+ ADP_STDOUT: // output "<"
+ if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end
+ else com_tx_req <= 1; // extend stream request if not ready
+ ADP_STDOUT1: // get STD out char
+ if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end
+ else std_rx_ack <= 1; // else extend
+ ADP_STDOUT2: // output char
+ if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end
+ else com_tx_req <= 1; // else extend
+ ADP_STDOUT3: // output ">"
+ if (com_tx_done) begin adp_state <= ADP_IOCHK; end
+ else com_tx_req <= 1; // else extend
+
+// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>>
+ ADP_RXCMD: // read and save ADP command
+ if (com_rx_done) begin
+ if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit
+ else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command
+ else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param
+ else begin adp_cmd <= com_rx_byte; adp_param <= 32'hffffffff; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter
+ end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_RXPARAM: // read and build hex parameter
+ if (com_rx_done) begin // RX byte
+ if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit
+ else if (FNvalid_EOL(com_rx_byte))
+`ifndef ADPBASIC
+ begin adp_count <= adp_param; adp_state <= ADP_ACTION; end // parameter complete on EOL
+`else
+ begin adp_state <= ADP_ACTION; end // parameter complete on EOL
+`endif
+ else
+ begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter
+ end
+ else com_rx_ack <= 1;
+
+ ADP_ACTION: // parse command and action with parameter
+ if (FNexit(com_rx_byte))
+ adp_state <= STD_IOCHK;
+ else if (FNvalid_cmd(adp_cmd) == CMD_A)
+ begin if (adp_param == 32'hffffffff) adp_param <= adp_addr; else adp_addr <= adp_param;
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_C) begin
+ if (adp_param[31:8] == 0) // report GPO
+ begin adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 1) // clear bits in GPO
+ begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 2) // set bits in GPO
+ begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 3) // overwrite bits in GPO
+ begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else // 4 etc, report GPO
+ begin adp_state <= ADP_SYSCTL; end
+ end
+ else if (FNvalid_cmd(adp_cmd) == CMD_R)
+ begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param
+ else if (FNvalid_cmd(adp_cmd) == CMD_S)
+ begin adp_state <= ADP_SYSCHK; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_W)
+ begin adp_bus_data <= adp_param; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_X)
+ begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end
+`ifndef ADPBASIC
+ else if (FNvalid_cmd(adp_cmd) == CMD_B)
+ if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_BCTRL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_M)
+ begin if (adp_param == 32'hffffffff) adp_param <= adp_mask; else adp_mask <= adp_param;
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_P)
+ if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_V)
+ begin if (adp_param == 32'hffffffff) adp_param <= adp_val; else adp_val <= adp_param;
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_Z)
+ if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_ZCTRL; // non-zero count
+`endif
+ else
+ begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald
+
+// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>>
+
+ ADP_WRITE: // perform bus write at current address pointer (and auto increment)
+ if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; end
+ else begin ADP_BUSWRITEINC_next(); end // extend request
+
+ ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; ADP_txchar_next("R"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end
+ else begin ADP_BUSREADINC_next(); end // extend request
+
+`ifndef ADPBASIC
+
+// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>>
+ ADP_BCTRL: // set control value
+ begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes
+ ADP_BREADB0: // read raw binary byte
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_BREADB1: // read raw binary byte
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_BREADB2: // read raw binary byte 0
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_BREADB3: // read raw binary byte 0
+ if (com_rx_done)
+ begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_BWRITE; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_BWRITE: // Write word to Addr++
+ if (adp_bus_done) begin // auto address++, count--
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_BREADB0; end
+ end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request
+
+// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>>
+ ADP_POLL: // set poll value
+ begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end
+ ADP_POLL1: // wait for read data, no addr++
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; end
+ else begin adp_bus_req <= 1; adp_count_dec <=1; end
+ ADP_POLL2:
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; // timeout
+ else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match
+ else adp_state <= ADP_POLL;
+
+// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>>
+ ADP_ZCTRL: // set control value
+ begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_ZWRITE; end
+ ADP_ZWRITE: // Write word to Addr++
+ if (adp_bus_done) begin // auto address++, count--
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_ZCTRL; end
+ end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request
+`endif
+
+ // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>>
+
+ ADP_UNKNOWN: // output "?"
+ if (com_tx_done) begin ADP_LINEACK_next(); end
+ else com_tx_req <= 1; // extend stream request if not ready
+
+ ADP_EXIT: // exit ADP mode
+ if (com_tx_done) adp_state <= STD_IOCHK;
+ else com_tx_req <= 1; // extend stream request if not ready
+
+ ADP_SYSCHK: // check STDIN fifo
+ begin // no upper flags so STDIN char
+ if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end
+ else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt
+ end
+ ADP_STDIN: // push char into STDIN
+ if (std_tx_done) begin adp_bus_data <= adp_param[7:0]; ADP_txchar_next("S"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end
+ else std_tx_req <= 1; // extend
+
+ ADP_SYSCTL: // read current status - and report in hex
+ begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end
+
+ ADP_ECHOCMD: // output command and (param) data
+ begin adp_state <= ADP_ECHOCMDSP; ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param; end // output command char
+ ADP_ECHOCMDSP: // output command space and (bus) data
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space char
+ else com_tx_req <= 1; // extend
+
+ ADP_WRITEHEX: // output hex word with prefix
+ begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output "0" hex prefix
+
+ ADP_WRITEHEXS:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX9:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX8:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX7: // output hex nibble 7
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX6: // output hex nibble 6
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX5: // output hex nibble 5
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX4: // output hex nibble 4
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX3: // output hex nibble 3
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX2: // output hex nibble 2
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX1: // output hex nibble 1
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack
+ if (com_tx_done) begin
+ if (banner) begin ADP_LINEACK_next(); end
+ else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt
+ end else com_tx_req <= 1; // extend
+
+ ADP_LINEACK: // write EOLN
+ if (com_tx_done) begin
+ begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end
+ end else com_tx_req <= 1; // extend
+ ADP_LINEACK2: // CR
+ if (com_tx_done) begin
+ if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end
+ else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end
+ end else com_tx_req <= 1; // extend
+ default:
+ begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default error
+ endcase
+ end
+
+endmodule
+
+////AHBLITE_ADPMASTER instancing
+//ADPmaster
+// #(.PROMPT_CHAR ("]"))
+// ADPmaster(
+// .HCLK (ahb_hclk ),
+// .HRESETn (ahb_hrestn ),
+// .HADDR32_o (ahb_haddr ),
+// .HBURST3_o (ahb_hburst ),
+// .HMASTLOCK_o (ahb_hmastlock ),
+// .HPROT4_o (ahb_hprot ),
+// .HSIZE3_o (ahb_hsize ),
+// .HTRANS2_o (ahb_htrans ),
+// .HWDATA32_o (ahb_hwdata ),
+// .HWRITE_o (ahb_hwrite ),
+// .HRDATA32_i (ahb_hrdata ),
+// .HREADY_i (ahb_hready ),
+// .HRESP_i (ahb_hresp ),
+
+// .COMRX_TREADY_o(com_rx_tready),
+// .COMRX_TDATA_i(com_rx_tdata),
+// .COMRX_TVALID_i(com_rx_tvalid),
+// .STDRX_TREADY_o(std_rx_tready),
+// .STDRX_TDATA_i(std_rx_tdata),
+// .STDRX_TVALID_i(std_rx_tvalid),
+// .COMTX_TVALID_o(com_tx_tvalid),
+// .COMTX_TDATA_o(com_tx_tdata),
+// .COMTX_TREADY_i(com_tx_tready),
+// .STDTX_TVALID_o(std_tx_tvalid),
+// .STDTX_TDATA_o(std_tx_tdata),
+// .STDTX_TREADY_i(std_tx_tready)
+
+// );
diff --git a/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v b/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..b5b8d4ba3fee47808bd78c5a9b117b47b9ea24d6
--- /dev/null
+++ b/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
@@ -0,0 +1,305 @@
+//-----------------------------------------------------------------------------
+// soclabs on-chip AXI stream to FTDI FT1248 controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module ft1248_streamio_v1_0 #
+ (
+ // Users to add parameters here
+ // FTDI Interface 1,2,4 width supported
+ parameter integer FT1248_WIDTH = 1,
+ // FTDI clock always on - else quiet when no access
+ parameter integer FT1248_CLKON = 1
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Parameters of Axi Stream Master Bus Interface TXD
+ // Parameters of Axi Stream Slave Bus Interface RXD
+ )
+ (
+ // IO pad interface - to FT232R configured in 1/2/4/8 mode
+ output wire ft_clk_o, // SCLK
+ output wire ft_ssn_o, // SS_N
+ input wire ft_miso_i, // MISO
+ output wire [FT1248_WIDTH-1:0] ft_miosio_o, // MIOSIO tristate output when enabled
+ output wire [FT1248_WIDTH-1:0] ft_miosio_e, // MIOSIO tristate output enable (active hi)
+ output wire [FT1248_WIDTH-1:0] ft_miosio_z, // MIOSIO tristate output enable (active lo)
+ input wire [FT1248_WIDTH-1:0] ft_miosio_i, // MIOSIO tristate input
+
+ input wire [7:0] ft_clkdiv, // divider prescaler to ensure SCLK <1MHz
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // initially clocked from aclk
+ // asynch
+ input wire clk,
+ input wire resetn,
+
+ // Ports of Axi Master Bus Interface TXD
+ output wire txd_tvalid,
+ output wire [7 : 0] txd_tdata,
+ output wire txd_tlast,
+ input wire txd_tready,
+
+ // Ports of Axi Slave Bus Interface RXD
+ output wire rxd_tready,
+ input wire [7 : 0] rxd_tdata,
+ input wire rxd_tlast,
+ input wire rxd_tvalid
+ );
+
+ //----------------------------------------------
+ //-- State Machine encoding
+ //----------------------------------------------
+
+// Explicit FSM state bit assignment
+// bit [0] SCLK
+// bit [1] MIO_OE
+// bit [2] CMD/W
+// bit [3] DAT/R
+// bit [4] SSEL
+
+localparam FT_0_IDLE = 5'b00000;
+localparam FT_1_IDLE = 5'b00001;
+localparam FT_ZCMD_CLKLO = 5'b10100;
+localparam FT_CMD_CLKHI = 5'b10111;
+localparam FT_CMD_CLKLO = 5'b10110;
+localparam FT_ZBT_CLKHI = 5'b10001;
+localparam FT_ZBT_CLKLO = 5'b10000;
+localparam FT_WD_CLKHI = 5'b11111;
+localparam FT_WD_CLKLO = 5'b11110;
+localparam FT_ZWD_CLKLO = 5'b11100;
+localparam FT_RD_CLKHI = 5'b11001;
+localparam FT_RD_CLKLO = 5'b11000;
+
+reg [4:0] ft_state;
+// 9- bit shift register to support 8-bit data + 1 sequence control flag
+// write data uses bits[7:0], with bit[8] set to flag length for serialized transfers
+// read data uses bits[8:1], with bit[0] set to flag continuation for serialized transfers
+reg [8:0] ft_reg;
+
+ //----------------------------------------------
+ //-- IO PAD control, parameterized on WIDTH param
+ //----------------------------------------------
+
+wire bwid8 = (FT1248_WIDTH==8);
+wire bwid4 = (FT1248_WIDTH==4);
+wire bwid2 = (FT1248_WIDTH==2);
+wire bwid1 = (FT1248_WIDTH==1);
+
+wire [7:0] ft_rdmasked;
+
+generate if (FT1248_WIDTH == 8) begin
+assign ft_rdmasked[7:1] = ft_miosio_i[7:1];
+assign ft_miosio_o[7:1] = ft_reg[7:1];
+assign ft_miosio_e[7:1] = {7{ft_state[1]}};
+assign ft_miosio_z[7:1] = ~{7{ft_state[1]}};
+end
+endgenerate
+
+generate if (FT1248_WIDTH == 4) begin
+assign ft_rdmasked[7:1] = {4'b1111, ft_miosio_i[3:1]};
+assign ft_miosio_o[3:1] = ft_reg[3:1];
+assign ft_miosio_e[3:1] = {3{ft_state[1]}};
+assign ft_miosio_z[3:1] = ~{3{ft_state[1]}};
+end
+endgenerate
+
+generate if (FT1248_WIDTH == 2) begin
+assign ft_rdmasked[7:1] = {6'b111111, ft_miosio_i[1]};
+assign ft_miosio_o[1] = ft_reg[1];
+assign ft_miosio_e[1] = ft_state[1];
+assign ft_miosio_z[1] = ~ft_state[1];
+end
+endgenerate
+
+generate if (FT1248_WIDTH == 1)
+assign ft_rdmasked[7:1] = 7'b1111111;
+endgenerate
+
+assign ft_rdmasked[0] = ft_miosio_i[0];
+assign ft_miosio_o[0] = ft_reg[0];
+assign ft_miosio_e[0] = ft_state[1];
+assign ft_miosio_z[0] = ~ft_state[1];
+
+assign ft_clk_o = ft_state[0];
+assign ft_ssn_o = !ft_state[4];
+
+// diagnostic decodes
+//wire ft_cmd = !ft_state[3] & ft_state[2];
+//wire ft_dwr = ft_state[3] & ft_state[2];
+//wire ft_drd = ft_state[3] & !ft_state[2];
+
+
+ //----------------------------------------------
+ //-- Internal clock prescaler
+ //----------------------------------------------
+
+ // clock prescaler, ft_clken enables serial IO engine clocking
+ reg [7:0] ft_clkcnt_r;
+ reg ft_clken;
+
+ always @(posedge clk or negedge resetn )
+ begin
+ if (!resetn) begin
+ ft_clkcnt_r <= 0;
+ ft_clken <= 0;
+ end
+ else begin
+ ft_clken <= (ft_clkcnt_r == ft_clkdiv);
+ ft_clkcnt_r <= (ft_clkcnt_r == ft_clkdiv) ? 0 : (ft_clkcnt_r +1);
+ end
+ end
+
+ //----------------------------------------------
+ //-- Internal "synchronizers" (dual stage)
+ //----------------------------------------------
+ // synchronizers for channel ready flags when idle
+ // (treat these signals as synchronous during transfer sequencing)
+ reg ft_miso_i_sync;
+ reg ft_miosio_i0_sync;
+ reg ft_miso_i_sync_1;
+ reg ft_miosio_i0_sync_1;
+
+ always @(posedge clk or negedge resetn )
+ begin
+ if (!resetn) begin
+ ft_miso_i_sync_1 <= 1;
+ ft_miosio_i0_sync_1 <= 1;
+ ft_miso_i_sync <= 1;
+ ft_miosio_i0_sync <= 1;
+ end
+ else begin
+ ft_miso_i_sync_1 <= ft_miso_i;
+ ft_miosio_i0_sync_1 <= ft_miosio_i[0];
+ ft_miso_i_sync <= ft_miso_i_sync_1;
+ ft_miosio_i0_sync <= ft_miosio_i0_sync_1;
+ end
+ end
+
+ //----------------------------------------------
+ //-- AXI Stream interface handshakes
+ //----------------------------------------------
+
+reg ft_txf; // FTDI Transmit channel Full
+reg ft_rxe; // FTDO Receive channel Empty
+reg ft_wcyc; // read access committed
+reg ft_nak; // check for NAK terminate
+
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txdata;
+assign txd_tdata = txdata[7:0];
+assign txd_tvalid = txdata[8];
+
+// activate if RX channel data and the stream buffer is not full
+wire ft_rxreq = !ft_rxe & !txdata[8];
+
+
+// RX stream handshakes on valid FT1248 write data transfer
+reg rxdone;
+reg rxrdy;
+assign rxd_tready = rxdone;
+
+// activate if TX channel not full and and the stream buffer data valid
+wire ft_txreq = !ft_txf & rxd_tvalid; // & !rxdone; // FTDI TX data ready and rxstream ready
+
+// FTDI1248 commands
+wire [3:0] wcmd = 4'b0000; // write request
+wire [3:0] rcmd = 4'b0001; // read request
+wire [3:0] fcmd = 4'b0100; // write flush request
+//wire [3:0] rcmd = 4'b1000; // read request BE bit-pattern
+//wire [3:0] fcmd = 4'b0010; // write flush request BE bit-pattern
+// and full FT1248 command bit patterns (using top-bits for shift sequencing)
+wire [8:0] wcmdpatt = {2'b11, wcmd[0], wcmd[1], 1'b0, wcmd[2], 1'b0, 1'b0, wcmd[3]};
+wire [8:0] rcmdpatt = {2'b11, rcmd[0], rcmd[1], 1'b0, rcmd[2], 1'b0, 1'b0, rcmd[3]};
+
+reg ssn_del;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ssn_del <= 1'b1;
+ else if (ft_clken)
+ ssn_del <= ft_ssn_o;
+wire ssn_start = ft_ssn_o & ssn_del;
+
+// FTDI1248 state machine
+
+always @(posedge clk or negedge resetn)
+ if (!resetn) begin
+ ft_state <= FT_0_IDLE;
+ ft_reg <= 0;
+ txdata <= 0;
+ rxdone <= 0;
+ ft_wcyc <= 0;
+ ft_txf <= 1; // ftdi channel TXE# ('1' full)
+ ft_rxe <= 1; // ftdi channel RXF# ('1' empty)
+ ft_nak <= 0;
+ end
+ else begin
+ ft_txf <= (ft_state==FT_0_IDLE) ? (ft_miosio_i[0] | ft_miosio_i0_sync) : 1'b1; //ft_txf & !( ft_wcyc &(ft_state==FT_ZBT_CLKHI) & ft_miso_i);
+ ft_rxe <= (ft_state==FT_0_IDLE) ? (ft_miso_i | ft_miso_i_sync) : 1'b1; //ft_rxe & !(!ft_wcyc & (ft_state==FT_ZBT_CLKHI) & ft_miso_i);
+ txdata[8] <= txdata[8] & !txd_tready; // tx_valid handshake
+ rxdone <= (ft_clken & (ft_state==FT_ZWD_CLKLO) & !ft_nak) | (rxdone & !rxd_tvalid); // hold until acknowledged
+ if (ft_clken)
+ case (ft_state)
+ FT_0_IDLE: begin // RX req priority
+ if (ssn_start & ft_rxreq) begin ft_reg <= rcmdpatt; ft_state <= FT_ZCMD_CLKLO; end
+ else if (ssn_start & ft_txreq) begin ft_reg <= wcmdpatt; ft_state <= FT_ZCMD_CLKLO; ft_wcyc <= 1; end
+ else ft_state <= (!ft_txf | !ft_rxe | (FT1248_CLKON!=0)) ? FT_1_IDLE : FT_0_IDLE;
+ end
+ FT_1_IDLE:
+ ft_state <= FT_0_IDLE;
+ FT_ZCMD_CLKLO:
+ ft_state <= FT_CMD_CLKHI;
+ FT_CMD_CLKHI:
+ ft_state <= FT_CMD_CLKLO;
+ FT_CMD_CLKLO: // 2, 4 or 7 shifts
+ if (bwid8) begin ft_reg <= FT_ZBT_CLKHI; end
+ else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= (|ft_reg[8:5]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
+ else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
+ else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
+ FT_ZBT_CLKHI:
+ ft_state <= FT_ZBT_CLKLO;
+ FT_ZBT_CLKLO:
+ if (ft_wcyc) begin ft_reg <= {1'b1,rxd_tdata}; ft_state <= FT_WD_CLKHI; end
+ else begin ft_reg <= 9'b011111111; ft_state <= FT_RD_CLKHI; end
+ FT_WD_CLKHI:
+ if (ft_miso_i & ft_reg[8]) begin ft_nak <= 1'b1; ft_state <= FT_ZWD_CLKLO; end // NAK terminate on first cycle
+ else if (bwid8) ft_state <= (ft_reg[8]) ? FT_WD_CLKLO : FT_ZWD_CLKLO; // special case repeat on write data
+ else if (bwid4) ft_state <= (|ft_reg[8:5]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ else if (bwid2) ft_state <= (|ft_reg[8:3]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ else ft_state <= (|ft_reg[8:2]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ FT_WD_CLKLO:
+ if (bwid8) begin ft_reg <= { 1'b0,ft_reg[7:0]}; ft_state <= FT_WD_CLKHI; end // clear top flag
+ else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= FT_WD_CLKHI; end // shift 4 bits right
+ else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= FT_WD_CLKHI; end // shift 2 bits right
+ else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= FT_WD_CLKHI; end // shift 1 bit right
+ FT_ZWD_CLKLO:
+ if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end // terminate without TX handshake
+ else begin ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end
+ FT_RD_CLKHI: // capture iodata pins end of CLKHI phase
+ if (ft_miso_i & (&ft_reg[7:0])) begin ft_nak <= 1'b1; ft_state <= FT_RD_CLKLO; end // NAK terminate on first cycle
+ else if (bwid8) begin ft_reg <= (ft_reg[0]) ? {ft_rdmasked[7:0],1'b1} : {ft_reg[8:1],1'b0}; ft_state <= FT_RD_CLKLO; end // 8-bit read twice
+ else if (bwid4) begin ft_reg <= {ft_rdmasked[3:0],ft_reg[8:4]}; ft_state <= FT_RD_CLKLO; end
+ else if (bwid2) begin ft_reg <= {ft_rdmasked[1:0],ft_reg[8:2]}; ft_state <= FT_RD_CLKLO; end
+ else begin ft_reg <= {ft_rdmasked[ 0],ft_reg[8:1]}; ft_state <= FT_RD_CLKLO; end
+ FT_RD_CLKLO:
+ if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; txdata <= 9'b0; end // terminate without TX handshake
+ else if (ft_reg[0]) begin ft_state <= FT_RD_CLKHI; ft_reg[0] <= !(bwid8); end // loop until all 8 bits shifted in (or 8-bit read repeated)
+ else begin ft_state <= FT_0_IDLE; txdata <= {1'b1,ft_reg[8:1]}; end
+ default:
+ ft_state <= FT_0_IDLE;
+ endcase
+ end
+
+ // User logic ends
+
+endmodule
diff --git a/IPLIB/axi_stream_io_v1_0/axi_stream_io_v1_0.v b/IPLIB/axi_stream_io_v1_0/axi_stream_io_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..a229917f1d1ba9277051b772cfebef6767cacd0e
--- /dev/null
+++ b/IPLIB/axi_stream_io_v1_0/axi_stream_io_v1_0.v
@@ -0,0 +1,114 @@
+
+`timescale 1 ns / 1 ps
+
+ module iostream_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Slave Bus Interface axi
+ parameter integer C_axi_DATA_WIDTH = 32,
+ parameter integer C_axi_ADDR_WIDTH = 4,
+
+ // Parameters of Axi Master Bus Interface tx
+ parameter integer C_tx_TDATA_WIDTH = 8,
+ parameter integer C_tx_START_COUNT = 3,
+
+ // Parameters of Axi Slave Bus Interface rx
+ parameter integer C_rx_TDATA_WIDTH = 8
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Slave Bus Interface axi
+ input wire axi_aclk,
+ input wire axi_aresetn,
+ input wire [C_axi_ADDR_WIDTH-1 : 0] axi_awaddr,
+ input wire [2 : 0] axi_awprot,
+ input wire axi_awvalid,
+ output wire axi_awready,
+ input wire [C_axi_DATA_WIDTH-1 : 0] axi_wdata,
+ input wire [(C_axi_DATA_WIDTH/8)-1 : 0] axi_wstrb,
+ input wire axi_wvalid,
+ output wire axi_wready,
+ output wire [1 : 0] axi_bresp,
+ output wire axi_bvalid,
+ input wire axi_bready,
+ input wire [C_axi_ADDR_WIDTH-1 : 0] axi_araddr,
+ input wire [2 : 0] axi_arprot,
+ input wire axi_arvalid,
+ output wire axi_arready,
+ output wire [C_axi_DATA_WIDTH-1 : 0] axi_rdata,
+ output wire [1 : 0] axi_rresp,
+ output wire axi_rvalid,
+ input wire axi_rready,
+
+ output wire interrupt,
+ // Ports of Axi Master Bus Interface tx
+ output wire tx_tvalid,
+ output wire [C_tx_TDATA_WIDTH-1 : 0] tx_tdata,
+ output wire [(C_tx_TDATA_WIDTH/8)-1 : 0] tx_tstrb,
+ output wire tx_tlast,
+ input wire tx_tready,
+
+ // Ports of Axi Slave Bus Interface rx
+ output wire rx_tready,
+ input wire [C_rx_TDATA_WIDTH-1 : 0] rx_tdata,
+ input wire [(C_rx_TDATA_WIDTH/8)-1 : 0] rx_tstrb,
+ input wire rx_tlast,
+ input wire rx_tvalid
+ );
+// Instantiation of Axi Bus Interface axi
+ iostream_v1_0_axi # (
+ .C_S_AXI_DATA_WIDTH(C_axi_DATA_WIDTH),
+ .C_S_AXI_ADDR_WIDTH(C_axi_ADDR_WIDTH)
+ ) iostream_v1_0_axi_inst (
+ .S_AXI_ACLK(axi_aclk),
+ .S_AXI_ARESETN(axi_aresetn),
+ .tx_tvalid(tx_tvalid),
+ .tx_tdata(tx_tdata),
+// output wire [0 : 0] tx_tstrb,
+// output wire tx_tlast,
+ .tx_tready(tx_tready),
+ .rx_tvalid(rx_tvalid),
+ .rx_tdata(rx_tdata),
+// input wire [0 : 0] tx_tstrb,
+// input wire tx_tlast,
+ .tx_tready(rx_tready),
+ .interrupt(interrupt),
+ .S_AXI_AWADDR(axi_awaddr),
+ .S_AXI_AWPROT(axi_awprot),
+ .S_AXI_AWVALID(axi_awvalid),
+ .S_AXI_AWREADY(axi_awready),
+ .S_AXI_WDATA(axi_wdata),
+ .S_AXI_WSTRB(axi_wstrb),
+ .S_AXI_WVALID(axi_wvalid),
+ .S_AXI_WREADY(axi_wready),
+ .S_AXI_BRESP(axi_bresp),
+ .S_AXI_BVALID(axi_bvalid),
+ .S_AXI_BREADY(axi_bready),
+ .S_AXI_ARADDR(axi_araddr),
+ .S_AXI_ARPROT(axi_arprot),
+ .S_AXI_ARVALID(axi_arvalid),
+ .S_AXI_ARREADY(axi_arready),
+ .S_AXI_RDATA(axi_rdata),
+ .S_AXI_RRESP(axi_rresp),
+ .S_AXI_RVALID(axi_rvalid),
+ .S_AXI_RREADY(axi_rready)
+ );
+
+assign tx_tstrb[0:0] = tx_tvalid;
+assign tx_tlast = 1'b0;
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/IPLIB/axi_stream_io_v1_0/axi_stream_io_v1_0_axi_s.v b/IPLIB/axi_stream_io_v1_0/axi_stream_io_v1_0_axi_s.v
new file mode 100755
index 0000000000000000000000000000000000000000..d8e6eea56a867b6dc1a997a0094d8d7da474bdc1
--- /dev/null
+++ b/IPLIB/axi_stream_io_v1_0/axi_stream_io_v1_0_axi_s.v
@@ -0,0 +1,424 @@
+
+`timescale 1 ns / 1 ps
+
+ module iostream_v1_0_axi #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXI data bus
+ parameter integer C_S_AXI_DATA_WIDTH = 32,
+ // Width of S_AXI address bus
+ parameter integer C_S_AXI_ADDR_WIDTH = 4
+ )
+ (
+ // Users to add ports here
+ output wire interrupt,
+
+ // Ports of Axi Master Bus Interface tx
+// input wire tx_aclk,
+// input wire tx_aresetn,
+ output wire tx_tvalid,
+ output wire [7 : 0] tx_tdata,
+// output wire [0 : 0] tx_tstrb,
+// output wire tx_tlast,
+ input wire tx_tready,
+
+ // Ports of Axi Slave Bus Interface rx
+// input wire rx_aclk,
+// input wire rx_aresetn,
+ output wire rx_tready,
+ input wire [7 : 0] rx_tdata,
+// input wire [0 : 0] rx_tstrb,
+// input wire rx_tlast,
+ input wire rx_tvalid,
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global Clock Signal
+ input wire S_AXI_ACLK,
+ // Global Reset Signal. This Signal is Active LOW
+ input wire S_AXI_ARESETN,
+ // Write address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+ // Write channel Protection type. This signal indicates the
+ // privilege and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_AWPROT,
+ // Write address valid. This signal indicates that the master signaling
+ // valid write address and control information.
+ input wire S_AXI_AWVALID,
+ // Write address ready. This signal indicates that the slave is ready
+ // to accept an address and associated control signals.
+ output wire S_AXI_AWREADY,
+ // Write data (issued by master, acceped by Slave)
+ input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+ // Write strobes. This signal indicates which byte lanes hold
+ // valid data. There is one write strobe bit for each eight
+ // bits of the write data bus.
+ input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available.
+ input wire S_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ output wire S_AXI_WREADY,
+ // Write response. This signal indicates the status
+ // of the write transaction.
+ output wire [1 : 0] S_AXI_BRESP,
+ // Write response valid. This signal indicates that the channel
+ // is signaling a valid write response.
+ output wire S_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ input wire S_AXI_BREADY,
+ // Read address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether the
+ // transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_ARPROT,
+ // Read address valid. This signal indicates that the channel
+ // is signaling valid read address and control information.
+ input wire S_AXI_ARVALID,
+ // Read address ready. This signal indicates that the slave is
+ // ready to accept an address and associated control signals.
+ output wire S_AXI_ARREADY,
+ // Read data (issued by slave)
+ output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+ // Read response. This signal indicates the status of the
+ // read transfer.
+ output wire [1 : 0] S_AXI_RRESP,
+ // Read valid. This signal indicates that the channel is
+ // signaling the required read data.
+ output wire S_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ input wire S_AXI_RREADY
+ );
+
+ // AXI4LITE signals
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awready;
+ reg axi_wready;
+ reg [1 : 0] axi_bresp;
+ reg axi_bvalid;
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arready;
+ reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
+ reg [1 : 0] axi_rresp;
+ reg axi_rvalid;
+
+ // Example-specific design signals
+ // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ // ADDR_LSB is used for addressing 32/64 bit registers/memories
+ // ADDR_LSB = 2 for 32 bits (n downto 2)
+ // ADDR_LSB = 3 for 64 bits (n downto 3)
+ localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+ localparam integer OPT_MEM_ADDR_BITS = 1;
+
+ //----------------------------------------------
+ //-- Signals for user logic register space example
+ //------------------------------------------------
+ //-- Number of Slave Registers 4
+ reg [8:0] tx_reg; // TX data
+ reg [8:0] rx_reg; // RX data
+ reg [7:0] ctrl_reg; // ctrl
+ wire slv_reg_rden;
+ wire slv_reg_wren;
+ reg [7:0] reg_data_out;
+ integer byte_index;
+ reg aw_en;
+
+ wire tx_req = tx_reg[8]; // request to transmit
+ wire tx_ack = tx_tready; // acknowledge when stream ready
+ wire tx_rdy = !tx_reg[8];
+ wire rx_req = rx_tvalid; // request to receive
+ wire rx_ack = !rx_reg[8];
+ wire rx_rdy = rx_reg[8];
+
+ //assign rx_reg[7:0] <= rx_tdata;
+
+ // I/O Connections assignments
+
+ assign interrupt = ctrl_reg[4] & (!tx_req | rx_req);
+
+ // TX stream interface
+ assign tx_tdata = tx_reg[7:0];
+ assign tx_tvalid = tx_req;
+
+ // RX stream interface
+ assign rx_tready = rx_ack;
+
+ //AXI Slave
+ assign S_AXI_AWREADY = axi_awready;
+ assign S_AXI_WREADY = axi_wready;
+ assign S_AXI_BRESP = axi_bresp;
+ assign S_AXI_BVALID = axi_bvalid;
+ assign S_AXI_ARREADY = axi_arready;
+ assign S_AXI_RDATA = axi_rdata;
+ assign S_AXI_RRESP = axi_rresp;
+ assign S_AXI_RVALID = axi_rvalid;
+ // Implement axi_awready generation
+ // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awready <= 1'b0;
+ aw_en <= 1'b1;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // slave is ready to accept write address when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_awready <= 1'b1;
+ aw_en <= 1'b0;
+ end
+ else if (S_AXI_BREADY && axi_bvalid)
+ begin
+ aw_en <= 1'b1;
+ axi_awready <= 1'b0;
+ end
+ else
+ begin
+ axi_awready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_awaddr latching
+ // This process is used to latch the address when both
+ // S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awaddr <= 0;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end
+ end
+ end
+
+ // Implement axi_wready generation
+ // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_wready <= 1'b0;
+ end
+ else
+ begin
+ if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+ begin
+ // slave is ready to accept write data when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_wready <= 1'b1;
+ end
+ else
+ begin
+ axi_wready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and write logic generation
+ // The write data is accepted and written to memory mapped registers when
+ // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ // select byte enables of slave registers while writing.
+ // These registers are cleared when reset (active low) is applied.
+ // Slave register write enable is asserted when valid address and data are available
+ // and the slave is ready to accept the write address and write data.
+ assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ rx_reg <= 0;
+ else if ((ctrl_reg[1] == 1'b1))
+ rx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
+ rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
+ rx_reg[8] <= 1'b0;
+ else if (rx_req & rx_ack) // check precedence (rx_req)
+ rx_reg[8:0] <= {1'b1, rx_tdata[7:0]};
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ tx_reg <= 0;
+ else if ((ctrl_reg[0] == 1'b1))
+ tx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1))
+ tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (tx_req & tx_ack)
+ tx_reg[8] <= 1'b0;
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ ctrl_reg <= 8'b00000100;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h3))
+ ctrl_reg[7:0] <= S_AXI_WDATA[7:0];
+ end
+
+ // Implement write response logic generation
+ // The write response and response valid signals are asserted by the slave
+ // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ // This marks the acceptance of address and indicates the status of
+ // write transaction.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_bvalid <= 0;
+ axi_bresp <= 2'b0;
+ end
+ else
+ begin
+ if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+ begin
+ // indicates a valid write response is available
+ axi_bvalid <= 1'b1;
+ axi_bresp <= 2'b0; // 'OKAY' response
+ end // work error responses in future
+ else
+ begin
+ if (S_AXI_BREADY && axi_bvalid)
+ //check if bready is asserted while bvalid is high)
+ //(there is a possibility that bready is always asserted high)
+ begin
+ axi_bvalid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ // Implement axi_arready generation
+ // axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ // S_AXI_ARVALID is asserted. axi_awready is
+ // de-asserted when reset (active low) is asserted.
+ // The read address is also latched when S_AXI_ARVALID is
+ // asserted. axi_araddr is reset to zero on reset assertion.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_arready <= 1'b0;
+ axi_araddr <= 32'b0;
+ end
+ else
+ begin
+ if (~axi_arready && S_AXI_ARVALID)
+ begin
+ // indicates that the slave has acceped the valid read address
+ axi_arready <= 1'b1;
+ // Read address latching
+ axi_araddr <= S_AXI_ARADDR;
+ end
+ else
+ begin
+ axi_arready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_arvalid generation
+ // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ // data are available on the axi_rdata bus at this instance. The
+ // assertion of axi_rvalid marks the validity of read data on the
+ // bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ // is deasserted on reset (active low). axi_rresp and axi_rdata are
+ // cleared to zero on reset (active low).
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rvalid <= 0;
+ axi_rresp <= 0;
+ end
+ else
+ begin
+ if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+ begin
+ // Valid read data is available at the read data bus
+ axi_rvalid <= 1'b1;
+ axi_rresp <= 2'b0; // 'OKAY' response
+ end
+ else if (axi_rvalid && S_AXI_RREADY)
+ begin
+ // Read data is accepted by the master
+ axi_rvalid <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and read logic generation
+ // Slave register read enable is asserted when valid address is available
+ // and the slave is ready to accept the read address.
+ assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+ always @(*)
+ begin
+ // Address decoding for reading registers
+ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+ 2'h0 : reg_data_out <= rx_reg[7:0];
+ 2'h1 : reg_data_out <= tx_reg[7:0];
+ 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_rdy, tx_rdy, rx_rdy, rx_rdy};
+ 2'h3 : reg_data_out <= ctrl_reg;
+ default : reg_data_out <= 0;
+ endcase
+ end
+
+ // Output register or memory read data
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rdata <= 0;
+ end
+ else
+ begin
+ // When there is a valid read address (S_AXI_ARVALID) with
+ // acceptance of read address by the slave (axi_arready),
+ // output the read dada
+ if (slv_reg_rden)
+ begin
+ axi_rdata <= {24'h000000, reg_data_out}; // register read data
+ end
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule