From 5887c42f0aba4ba9a6f16f757b4a3f22040d03ad Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Sat, 1 Jul 2023 10:27:59 +0100
Subject: [PATCH] Fixed ROMTable Tests
---
.../nanosoc_system/verilog/nanosoc_system.v | 2 +-
testcodes/generic/config_id.h | 7 +-
testcodes/makefile | 2 +-
testcodes/{defs.makefile => makefile.defs} | 0
verif/tb/verilog/nanosoc_tb.v | 87 ++++++++-----------
5 files changed, 39 insertions(+), 59 deletions(-)
rename testcodes/{defs.makefile => makefile.defs} (100%)
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
index fd2baef..0a885c6 100644
--- a/system/nanosoc_system/verilog/nanosoc_system.v
+++ b/system/nanosoc_system/verilog/nanosoc_system.v
@@ -66,7 +66,7 @@ module nanosoc_system #(
parameter SYSTABLE_BASE = 32'hF000_0000, // Base Address of System ROM Table
// SoCLabs Manufacture ID
- parameter SOCLABS_JEPID = 7'd0,
+ parameter SOCLABS_JEPID = 7'd51, //- SL (SoCLabs)
// NanoSoC Part and Revision Numbers
parameter NANOSOC_PARTNUMBER = 12'h001,
diff --git a/testcodes/generic/config_id.h b/testcodes/generic/config_id.h
index 3a4f01b..64ad291 100644
--- a/testcodes/generic/config_id.h
+++ b/testcodes/generic/config_id.h
@@ -216,18 +216,15 @@
// <o> EXPECTED_BASEADDR: Expected value of BASEADDR[31:0] at CORTEXM0DAP <0x0-0xFFFFFFFF>
-#ifdef CORTEX_M0
-#define EXPECTED_BASEADDR 0xE00FF003
-#else
+// Modified to point to SystemROMTable
#define EXPECTED_BASEADDR 0xF0000003
-#endif
// <o> EXPECTED_JTAGnSW: Expected Cortex M0(+) DAP Protocol <0=> Serial Wire <1=> JTAG
#define EXPECTED_JTAGnSW 0
// <h> System ROM Table ID values
// <o> EXPECTED_CUST_JEP_ID: Expected JEDEC JEP-106 identity code (0-0x7F)
-#define EXPECTED_CUST_JEP_ID 0x00
+#define EXPECTED_CUST_JEP_ID 0x51
// <o> EXPECTED_CUST_JEP_CONT: Expected JEDEC JEP-106 continuation code (0-0xF)
diff --git a/testcodes/makefile b/testcodes/makefile
index 48b0a9b..bc28ab4 100644
--- a/testcodes/makefile
+++ b/testcodes/makefile
@@ -37,7 +37,7 @@
#
# Configurations
#
-include defs.makefile
+include makefile.defs
all: all_$(TOOL_CHAIN)
diff --git a/testcodes/defs.makefile b/testcodes/makefile.defs
similarity index 100%
rename from testcodes/defs.makefile
rename to testcodes/makefile.defs
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 5b179e0..be19c15 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -244,61 +244,44 @@ reg baud_clk_del;
// --------------------------------------------------------------------------------
// UART connection cross over for UART test
-// assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
-// assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
-
-assign P1[4] = P1[5]; // loopback UART2
-
-wire ft_clk_out = P1[1];
-wire ft_miso_in;
-assign P1[0] = ft_miso_in;
-wire ft_ssn_out = P1[3];
-
-//
-// AXI stream io testing
-//
-
-wire txd8_ready;
-wire txd8_valid;
-wire [7:0] txd8_data ;
-
-wire rxd8_ready;
-wire rxd8_valid;
-wire [7:0] rxd8_data ;
-
-nanosoc_axi_stream_io_8_txd_from_file
- #(.TXDFILENAME(ADP_FILENAME))
- u_nanosoc_axi_stream_io_8_txd_from_file
- (
- .aclk (XTAL1),
- .aresetn (NRST),
- .txd8_ready (txd8_ready),
- .txd8_valid (txd8_valid),
- .txd8_data (txd8_data)
- );
-
-/*
-axi_stream_io_8_buffer
- u_axi_stream_io_8_buffer
- (
- .aclk (XTAL1),
- .aresetn (NRST),
- .rxd8_ready (txd8_ready),
- .rxd8_valid (txd8_valid),
- .rxd8_data (txd8_data),
- .txd8_ready (rxd8_ready),
- .txd8_valid (rxd8_valid),
- .txd8_data (rxd8_data)
+ // assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
+ // assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
+
+ assign P1[4] = P1[5]; // loopback UART2
+
+ wire ft_clk_out = P1[1];
+ wire ft_miso_in;
+ assign P1[0] = ft_miso_in;
+ wire ft_ssn_out = P1[3];
+
+ //
+ // AXI stream io testing
+ //
+
+ wire txd8_ready;
+ wire txd8_valid;
+ wire [7:0] txd8_data ;
+
+ wire rxd8_ready;
+ wire rxd8_valid;
+ wire [7:0] rxd8_data ;
+
+ nanosoc_axi_stream_io_8_txd_from_file #(
+ .TXDFILENAME(ADP_FILENAME)
+ ) u_nanosoc_axi_stream_io_8_txd_from_file (
+ .aclk (XTAL1),
+ .aresetn (NRST),
+ .txd8_ready (txd8_ready),
+ .txd8_valid (txd8_valid),
+ .txd8_data (txd8_data)
);
-*/
-wire ft_miosio_o;
-wire ft_miosio_z;
-wire ft_miosio_i = P1[2]; // & ft_miosio_z;
-assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
+ wire ft_miosio_o;
+ wire ft_miosio_z;
+ wire ft_miosio_i = P1[2]; // & ft_miosio_z;
+ assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
-nanosoc_ft1248x1_to_axi_streamio_v1_0
- u_nanosoc_ft1248x1_to_axi_streamio_v1_0
+ nanosoc_ft1248x1_to_axi_streamio_v1_0 u_nanosoc_ft1248x1_to_axi_streamio_v1_0
(
.ft_clk_i (ft_clk_out),
.ft_ssn_i (ft_ssn_out),
--
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