diff --git a/.gitmodules b/.gitmodules
index 7b62837b308b8827b2fea65b93733f072564fd39..b21f95ef765d36c3782b63b8f169ddba78c5dc8d 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,6 @@
[submodule "nanosoc/sldma350_tech"]
path = nanosoc/sldma350_tech
url = https://git.soton.ac.uk/soclabs/sldma350_tech.git
+[submodule "nanosoc/sl_ams_tech"]
+ path = nanosoc/sl_ams_tech
+ url = https://git.soton.ac.uk/soclabs/sl_ams_tech.git
diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist
index 063742ca5497ea8f87686cc15f89b88e0c7dbe77..fc6b47ca1746d05c03ee756a10b9e798ba39c7d9 100644
--- a/flist/nanosoc_ip.flist
+++ b/flist/nanosoc_ip.flist
@@ -52,6 +52,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_reg
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
// NanoSoC Regions - SysTable Region
@@ -63,4 +64,3 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
-
diff --git a/flows/makefile.asic b/flows/makefile.asic
index 070b8d7608ccdd31dd5a8f4e2ce53086ac36f098..34d8c16dbf583640ba95e52c8c09fa1a332063d9 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -62,16 +62,16 @@ RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
flist_dc_nanosoc: gen_defs
@mkdir -p $(TCL_ASIC_FLIST_DIR)
@(cd $(TCL_ASIC_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(DC_OUTPUT_FILELIST) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(DC_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
flist_genus_nanosoc: gen_defs
@mkdir -p $(TCL_ASIC_FLIST_DIR)
@(cd $(TCL_ASIC_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
flist_formality_nanosoc: gen_defs
@(cd $(TCL_ASIC_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -F -a -f $(DESIGN_VC) -o $(FORMALITY_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src;)
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -F -a -f $(DESIGN_VC) -o $(FORMALITY_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/synthesis/src;)
gen_memories: bootrom
@mkdir -p $(MEMORIES_DIR)
diff --git a/flows/makefile.fpga b/flows/makefile.fpga
index fc041a0c09f7a7f01189cff16bc34047c442950d..14b851d6152cc750517986095dfa819643ab1d69 100644
--- a/flows/makefile.fpga
+++ b/flows/makefile.fpga
@@ -68,7 +68,7 @@ code:
flist_tcl_nanosoc: gen_defs
@mkdir -p $(TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
# Package NanoSoC Socket Components
package_socket:
diff --git a/flows/makefile.simulate b/flows/makefile.simulate
index 95875fad7e8f2cfad8e6cfdb09fa8481a20c88d4..09996ac00e2bc05c95d8d60b394471d8a21da8bf 100644
--- a/flows/makefile.simulate
+++ b/flows/makefile.simulate
@@ -22,10 +22,14 @@ MTI_VC_OPTIONS += -f $(TBENCH_VC) $(ADP_OPTIONS)
MTI_RUN_OPTIONS = -voptargs=+acc
# VCS options
-VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug
+VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug -debug_access+all
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
+ifdef AMS
+ VCS_OPTIONS += -ad=$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/vcsAD.init -ams_discipline logic -ams
+endif
+
# XM verilog options
XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
XM_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
@@ -82,7 +86,7 @@ flist_vfiles_nanosoc: gen_defs
@if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir -p $(SIM_DIR)/logs; \
fi
- @cd $(SIM_DIR); python $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -f $(TBENCH_VC) -a -v -o tbench.vc
+ @cd $(SIM_DIR); python $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -f $(TBENCH_VC) -a -i $(FLIST_INCLUDES) -v -o tbench.vc
# ------- VCS -----------
diff --git a/makefile b/makefile
index 95e7e04362cf0686e74e69ff121ec2d7d3328c53..0ab9e8d7dad0b31060572a4d2771cc51a827fc11 100644
--- a/makefile
+++ b/makefile
@@ -9,6 +9,7 @@
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
+include $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc.config
#-------------------------------------
# - Commonly Overloaded Variables
@@ -25,8 +26,10 @@ ACCELERATOR ?= yes
# Is the Arm QuickStart being used?
QUICKSTART ?= no
+# IS this for an ASIC Flow?
ASIC ?= no
+# Are simulations to be run in fast mode? (i.e. RAMs preloaded)
FAST_SIM ?= yes
#-------------------------------------
@@ -67,11 +70,62 @@ ifeq ($(ACCELERATOR),yes)
NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
endif
+# Set variables for tesbench if fast simulation
ifeq ($(FAST_SIM),yes)
DEFINES_VC += +define+FAST_SIM
NANOSOC_DEFINES += FAST_SIM
endif
+ifdef DMA_DMA350_INCLUDE
+ ifdef DMA350_SMALL
+ NANOSOC_DEFINES += DMAC_DMA350
+ FLIST_INCLUDES += $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb_small.flist
+ endif
+ ifdef DMA350_DEFAULT
+ NANOSOC_DEFINES += DMAC_DMA350 DMA350_STREAM_2
+ FLIST_INCLUDES += $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+ endif
+ ifdef DMA350_BIG
+ NANOSOC_DEFINES += DMAC_DMA350 DMA350_STREAM_2 DMA350_STREAM_3
+ FLIST_INCLUDES += $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb_big.flist
+ endif
+else
+ ifdef DMA_0_PL230_INCLUDE
+ NANOSOC_DEFINES += DMAC_0_PL230
+ FLIST_INCLUDES +=$(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
+ endif
+ ifdef DMA_1_PL230_INCLUDE
+ NANOSOC_DEFINES += DMAC_1_PL230
+ FLIST_INCLUDES +=$(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
+ endif
+endif
+
+ifdef ADC_0_INCLUDE
+ AMS = yes
+ NANOSOC_DEFINES += AMS_PERIPHERALS ADC_0_INCLUDE
+ FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
+endif
+
+ifdef ADC_1_INCLUDE
+ AMS = yes
+ NANOSOC_DEFINES += AMS_PERIPHERALS ADC_1_INCLUDE
+ FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
+endif
+
+ifdef ADC_2_INCLUDE
+ AMS = yes
+ NANOSOC_DEFINES += AMS_PERIPHERALS ADC_2_INCLUDE
+ FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
+endif
+
+ifdef ADC_3_INCLUDE
+ AMS = yes
+ NANOSOC_DEFINES += AMS_PERIPHERALS ADC_3_INCLUDE
+ FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
+endif
+
+
+
# System Design Filelist
ifeq ($(QUICKSTART),yes)
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
@@ -84,21 +138,19 @@ else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
- NANOSOC_DEFINES += DMAC_0_PL230 DMAC_1_PL230 ASIC_TEST_PORTS POWER_PINS
+ NANOSOC_DEFINES += ASIC_TEST_PORTS POWER_PINS
else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
- ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
- ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
TB_TOP ?= nanosoc_tb
- NANOSOC_DEFINES += DMAC_0_PL230
endif
endif
# Make variables visible to target shells
export ARM_CORTEX_M0_DIR
export ARM_CORSTONE_101_DIR
-
+export FLIST_INCLUDES
+export AMS
# Location of Defines File
DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/
DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v
@@ -132,6 +184,9 @@ gen_defs:
@mkdir -p $(DEFINES_DIR)
@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
+TEST_AMS:
+ $(info AMS is $(AMS))
+ $(info VCS OPTIONS is $(VCS_OPTIONS))
# Remove RTL compile files, log files, software compile files
clean : clean_all_code
@rm -rf $(SIM_TOP_DIR)
diff --git a/nanosoc.config b/nanosoc.config
new file mode 100644
index 0000000000000000000000000000000000000000..f28efadd92ac416f19f9bc71385c8654d91d2ad0
--- /dev/null
+++ b/nanosoc.config
@@ -0,0 +1,31 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Configuration file
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### IP Configuration
+# !!EDIT this to point to the relevant logical directories of IP
+ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
+ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+
+# DMA_xxx_INCLUDE (yes or leave blank)
+DMA_0_PL230_INCLUDE := yes
+DMA_1_PL230_INCLUDE :=
+DMA_DMA350_INCLUDE :=
+
+# DMA 350 options set to yes for one of them
+# !! MAKE sure you run the correct configuration in the SLDMA350 directory
+# Small configuration of DMA, 2 channels, no stream interface, no extended features
+# Default configuration of DMA, 2 channels, stream interface, extended features
+# Big configuration of DMA, 3 channels, stream interface, extended features
+DMA350_SMALL :=
+DMA350_DEFAULT :=
+DMA350_BIG :=
+
+# ADC Include (yes or leave blank)
+ADC_0_INCLUDE:=
+ADC_1_INCLUDE:=
+ADC_2_INCLUDE:=
+ADC_3_INCLUDE:=
\ No newline at end of file
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 180c16b593e27a7efe27ec14715af603afee5376..cf3ac0d42c8bca6d512b48d82d69c59c3314bb26 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -10,6 +10,7 @@
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
+`include "gen_defines.v"
module nanosoc_region_sysio #(
parameter SYS_ADDR_W=32, // System Address Width
@@ -108,7 +109,8 @@ module nanosoc_region_sysio #(
localparam BASEADDR_APBSS = 32'h4000_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
- localparam BASEADDR_SYSCTRL = 32'h4001_f000; // Sysctrl peripheral basse address
+ localparam BASEADDR_SYSCTRL = 32'h4001_f000; // Sysctrl peripheral base address
+ localparam BASEADDR_ADC = 32'h4002_0000; // ADC Peripheral base address
localparam BE = 0;
// ------------------------------------------------------------
@@ -140,13 +142,20 @@ module nanosoc_region_sysio #(
wire [SYS_DATA_W-1:0] sysctrl_hrdata;
wire sysctrl_hresp;
+ wire adcsys_hsel; // ADC subsystem AHB interface signals
+ wire adcsys_hreadyout;
+ wire [SYS_DATA_W-1:0] adcsys_hrdata;
+ wire adcsys_hresp;
+
+
// AHB address decode
nanosoc_sysio_decode #(
.BASEADDR_APBSS (BASEADDR_APBSS),
.BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1),
- .BASEADDR_SYSCTRL (BASEADDR_SYSCTRL)
+ .BASEADDR_SYSCTRL (BASEADDR_SYSCTRL),
+ .BASEADDR_ADC (BASEADDR_ADC)
) u_addr_decode (
// System Address
.hsel (HSEL),
@@ -155,9 +164,16 @@ module nanosoc_region_sysio #(
.gpio0_hsel (gpio0_hsel),
.gpio1_hsel (gpio1_hsel),
.sysctrl_hsel (sysctrl_hsel),
+ `ifdef AMS_PERIPHERALS
+ .adcsys_hsel (adcsys_hsel),
+ `endif
.defslv_hsel (defslv_hsel)
);
-
+`ifdef AMS_PERIPHERALS
+ parameter AMS_PERIPHERAL_PORT = 1;
+`else
+ parameter AMS_PERIPHERAL_PORT = 0;
+`endif
// AHB slave multiplexer
cmsdk_ahb_slave_mux #(
.PORT0_ENABLE (1), // APB subsystem bridge
@@ -165,7 +181,7 @@ module nanosoc_region_sysio #(
.PORT2_ENABLE (1), // GPIO Port 1
.PORT3_ENABLE (1), // SYS control
.PORT4_ENABLE (1), // Default
- .PORT5_ENABLE (0),
+ .PORT5_ENABLE (AMS_PERIPHERAL_PORT), // ADC Region
.PORT6_ENABLE (0),
.PORT7_ENABLE (0),
.PORT8_ENABLE (0),
@@ -195,10 +211,10 @@ module nanosoc_region_sysio #(
.HREADYOUT4 (defslv_hreadyout),
.HRESP4 (defslv_hresp),
.HRDATA4 (defslv_hrdata),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (defslv_hreadyout),
- .HRESP5 (defslv_hresp),
- .HRDATA5 (defslv_hrdata),
+ .HSEL5 (adcsys_hsel), // Input Port 5
+ .HREADYOUT5 (adcsys_hreadyout),
+ .HRESP5 (adcsys_hresp),
+ .HRDATA5 (adcsys_hrdata),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (defslv_hreadyout),
.HRESP6 (defslv_hresp),
@@ -429,4 +445,63 @@ module nanosoc_region_sysio #(
.watchdog_reset (WDOGRESETREQ)
);
+`ifdef AMS_PERIPHERALS
+ nanosoc_sysio_adc_ss #(
+`ifdef ADC_0_INCLUDE
+ .ADC_0_ENABLE (1),
+`endif
+`ifdef ADC_1_INCLUDE
+ .ADC_1_ENABLE (1),
+`endif
+`ifdef ADC_2_INCLUDE
+ .ADC_2_ENABLE (1),
+`endif
+`ifdef ADC_3_INCLUDE
+ .ADC_3_ENABLE (1),
+`endif
+ .INCLUDE_IRQ_SYNCHRONIZER(0), // require IRQs to be HCLK synchronous
+ .INCLUDE_APB_TEST_SLAVE (1), // Include example test slave
+ .BE (BE)
+ ) u_sysio_adc_ss (
+`ifdef ADC_0_ENABLE
+ .adc_0_in(),
+ .i_adc_0_irq(),
+`endif
+`ifdef ADC_1_ENABLE
+ .adc_1_in(),
+ .i_adc_1_irq(),
+`endif
+`ifdef ADC_2_ENABLE
+ .adc_2_in(),
+ .i_adc_1_irq(),
+`endif
+`ifdef ADC_3_ENABLE
+ .adc_3_in(),
+ .i_adc_1_irq(),
+`endif
+
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+
+ .HSEL(adcsys_hsel),
+ .HADDR(HADDR[15:0]),
+ .HTRANS(HTRANS[1:0]),
+ .HWRITE(HWRITE),
+ .HSIZE(HSIZE),
+ .HPROT(HPROT),
+ .HREADY(HREADY),
+ .HWDATA(HWDATA[31:0]),
+
+ .HREADYOUT(adcsys_hreadyout),
+ .HRDATA(adcsys_hrdata),
+ .HRESP(adcsys_hresp),
+
+ .PCLK(PCLK), // Peripheral clock
+ .PCLKG(PCLKG), // Gate PCLK for bus interface only
+ .PCLKEN(PCLKEN), // Clock divider for AHB to APB bridge
+ .PRESETn(PRESETn) // APB reset
+
+ );
+`endif
+
endmodule
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v
new file mode 100755
index 0000000000000000000000000000000000000000..299d32799f42687b1e6a141e3693e2d915b191bd
--- /dev/null
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v
@@ -0,0 +1,593 @@
+//-----------------------------------------------------------------------------
+// NanoSoC APB Subsystem adapted from Arm CMSDK APB Subsystem
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : APB sub system
+//-----------------------------------------------------------------------------
+module nanosoc_sysio_adc_ss #(
+ // Enable setting for APB extension ports
+ // By default, all four extension ports are not used.
+ // This can be overriden by parameters at instantiations.
+ parameter ADC_0_ENABLE=0,
+ parameter ADC_1_ENABLE=0,
+ parameter ADC_2_ENABLE=0,
+ parameter ADC_3_ENABLE=0,
+
+ // If peripherals are generated with asynchronous clock domain to HCLK of the processor
+ // You might need to add synchroniser to the IRQ signal.
+ // In this example APB subsystem, the IRQ synchroniser is used to all peripherals
+ // when the INCLUDE_IRQ_SYNCHRONIZER parameter is set to 1. In practice you may have
+ // some IRQ signals need to be synchronised and some do not.
+ parameter INCLUDE_IRQ_SYNCHRONIZER=0,
+
+
+ // By default the APB subsystem include a simple test slave use in ARM for
+ // validation purpose. You can remove this test slave by setting the
+ // INCLUDE_APB_TEST_SLAVE paramater to 0,
+ parameter INCLUDE_APB_TEST_SLAVE = 1,
+
+ // Big endian - Add additional endian conversion logic to support big endian.
+ // (for ARM internal testing and evaluation of the processor in
+ // big endian configuration).
+ // 0 = little endian, 1 = big endian
+ //
+ // The example systems including this APB subsystem are designed as
+ // little endian. Most of the peripherals and memory system are
+ // little endian. This parameter is introduced to allows ARM to
+ // perform system level tests to verified behaviour of bus
+ // components in big endian configuration, and to allow designers
+ // to evaluate the processor in big endian configuration.
+ //
+ // Use of this parameter is not recommended for actual product
+ // development as this adds extra hardware. For big endian systems
+ // ideally the peripherals should be modified to use a big endian
+ // programmer's model.
+ parameter BE = 0)
+ (
+// --------------------------------------------------------------------------
+// Port Definitions
+// --------------------------------------------------------------------------
+ // AHB interface for AHB to APB bridge
+ // Peripherals
+ // ADC
+`ifdef ADC_0_ENABLE
+ electrical adc_0_in,
+`endif
+`ifdef ADC_1_ENABLE
+ electrical adc_1_in,
+`endif
+`ifdef ADC_2_ENABLE
+ electrical adc_2_in,
+`endif
+`ifdef ADC_3_ENABLE
+ electrical adc_3_in,
+`endif
+ output wire i_adc_0_irq,
+ output wire i_adc_1_irq,
+ output wire i_adc_2_irq,
+ output wire i_adc_3_irq,
+
+ input wire HCLK,
+ input wire HRESETn,
+
+ input wire HSEL,
+ input wire [15:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire HWRITE,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HREADY,
+ input wire [31:0] HWDATA,
+ output wire HREADYOUT,
+ output wire [31:0] HRDATA,
+ output wire HRESP,
+
+ input wire PCLK, // Peripheral clock
+ input wire PCLKG, // Gate PCLK for bus interface only
+ input wire PCLKEN, // Clock divider for AHB to APB bridge
+ input wire PRESETn // APB reset
+ );
+
+ // --------------------------------------------------------------------------
+ // Internal wires
+ // --------------------------------------------------------------------------
+ wire [15:0] i_paddr;
+ wire i_psel;
+ wire i_penable;
+ wire i_pwrite;
+ wire [2:0] i_pprot;
+ wire [3:0] i_pstrb;
+ wire [31:0] i_pwdata;
+
+ // wire from APB slave mux to APB bridge
+ wire i_pready_mux;
+ wire [31:0] i_prdata_mux;
+ wire i_pslverr_mux;
+
+ // Peripheral signals
+ wire adc_0_psel;
+ wire [31:0] adc_0_prdata;
+ wire adc_0_pready;
+ wire adc_0_pslverr;
+
+ wire adc_1_psel;
+ wire [31:0] adc_1_prdata;
+ wire adc_1_pready;
+ wire adc_1_pslverr;
+
+ wire adc_2_psel;
+ wire [31:0] adc_2_prdata;
+ wire adc_2_pready;
+ wire adc_2_pslverr;
+
+ wire adc_3_psel;
+ wire [31:0] adc_3_prdata;
+ wire adc_3_pready;
+ wire adc_3_pslverr;
+
+ wire test_slave_psel;
+ wire [31:0] test_slave_prdata;
+ wire test_slave_pready;
+ wire test_slave_pslverr;
+
+ wire psel4;
+ wire psel5;
+ wire psel6;
+ wire psel7;
+ wire psel8;
+ wire psel9;
+ wire psel10;
+ wire psel11;
+ wire psel12;
+ wire psel13;
+ wire psel14;
+ wire psel15;
+
+ // Interrupt signals from peripherals
+ wire adc_0_irq;
+ wire adc_1_irq;
+ wire adc_2_irq;
+ wire adc_3_irq;
+
+ // endian handling
+ wire bigendian;
+ assign bigendian = (BE!=0) ? 1'b1 : 1'b0;
+
+ wire [31:0] hwdata_le; // Little endian write data
+ wire [31:0] hrdata_le; // Little endian read data
+ wire reg_be_swap_ctrl_en = HSEL & HTRANS[1] & HREADY & bigendian;
+ reg [1:0] reg_be_swap_ctrl; // registered byte swap control
+ wire [1:0] nxt_be_swap_ctrl; // next state of byte swap control
+
+ assign nxt_be_swap_ctrl[1] = bigendian & (HSIZE[1:0]==2'b10); // Swap upper and lower half word
+ assign nxt_be_swap_ctrl[0] = bigendian & (HSIZE[1:0]!=2'b00); // Swap byte within hafword
+
+ // Register byte swap control for data phase
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_be_swap_ctrl <= 2'b00;
+ else if (reg_be_swap_ctrl_en)
+ reg_be_swap_ctrl <= nxt_be_swap_ctrl;
+ end
+
+ // swap byte within half word
+ wire [31:0] hwdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
+ {HWDATA[23:16],HWDATA[31:24],HWDATA[7:0],HWDATA[15:8]}:
+ {HWDATA[31:24],HWDATA[23:16],HWDATA[15:8],HWDATA[7:0]};
+ // swap lower and upper half word
+ assign hwdata_le = (reg_be_swap_ctrl[1] & bigendian) ?
+ {hwdata_mux_1[15: 0],hwdata_mux_1[31:16]}:
+ {hwdata_mux_1[31:16],hwdata_mux_1[15:0]};
+ // swap byte within half word
+ wire [31:0] hrdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
+ {hrdata_le[23:16],hrdata_le[31:24],hrdata_le[ 7:0],hrdata_le[15:8]}:
+ {hrdata_le[31:24],hrdata_le[23:16],hrdata_le[15:8],hrdata_le[7:0]};
+ // swap lower and upper half word
+ assign HRDATA = (reg_be_swap_ctrl[1] & bigendian) ?
+ {hrdata_mux_1[15: 0],hrdata_mux_1[31:16]}:
+ {hrdata_mux_1[31:16],hrdata_mux_1[15:0]};
+
+ // AHB to APB bus bridge
+ cmsdk_ahb_to_apb
+ #(.ADDRWIDTH (16),
+ .REGISTER_RDATA (1),
+ .REGISTER_WDATA (0))
+ u_ahb_to_apb(
+ // AHB side
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL),
+ .HADDR (HADDR[15:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HPROT (HPROT),
+ .HWRITE (HWRITE),
+ .HREADY (HREADY),
+ .HWDATA (hwdata_le),
+
+ .HREADYOUT(HREADYOUT), // AHB Outputs
+ .HRDATA (hrdata_le),
+ .HRESP (HRESP),
+
+ .PADDR (i_paddr[15:0]),
+ .PSEL (i_psel),
+ .PENABLE (i_penable),
+ .PSTRB (i_pstrb),
+ .PPROT (i_pprot),
+ .PWRITE (i_pwrite),
+ .PWDATA (i_pwdata),
+
+ .APBACTIVE(APBACTIVE),
+ .PCLKEN (PCLKEN), // APB clock enable signal
+
+ .PRDATA (i_prdata_mux),
+ .PREADY (i_pready_mux),
+ .PSLVERR (i_pslverr_mux)
+ );
+
+ // APB slave multiplexer
+ cmsdk_apb_slave_mux #( // Parameter to determine which ports are used
+ .PORT0_ENABLE (ADC_0_ENABLE), // ADC 0 APB Port Enable
+ .PORT1_ENABLE (ADC_1_ENABLE), // ADC 1 APB Port Enable
+ .PORT2_ENABLE (ADC_2_ENABLE), // ADC 2 APB Port Enable
+ .PORT3_ENABLE (ADC_3_ENABLE), // ADC 3 APB Port Enable
+ .PORT4_ENABLE (1), // not used
+ .PORT5_ENABLE (1), // not used
+ .PORT6_ENABLE (1), // not used
+ .PORT7_ENABLE (1), // not used
+ .PORT8_ENABLE (1), // not used
+ .PORT9_ENABLE (1), // not used
+ .PORT10_ENABLE (1), // not used
+ .PORT11_ENABLE (1), // not used
+ .PORT12_ENABLE (1), // not used
+ .PORT13_ENABLE (1), // not used
+ .PORT14_ENABLE (1), // not used
+ .PORT15_ENABLE (1) // not used
+ ) u_apb_slave_mux (
+ // Inputs
+ .DECODE4BIT (i_paddr[15:12]),
+ .PSEL (i_psel),
+ // PSEL (output) and return status & data (inputs) for each port
+ .PSEL0 (adc_0_psel),
+ .PREADY0 (adc_0_pready),
+ .PRDATA0 (adc_0_prdata),
+ .PSLVERR0 (adc_0_pslverr),
+
+ .PSEL1 (adc_1_psel),
+ .PREADY1 (adc_1_pready),
+ .PRDATA1 (adc_1_prdata),
+ .PSLVERR1 (adc_1_pslverr),
+
+ .PSEL2 (adc_2_psel),
+ .PREADY2 (adc_2_pready),
+ .PRDATA2 (adc_2_prdata),
+ .PSLVERR2 (adc_2_pslverr),
+
+ .PSEL3 (adc_3_psel),
+ .PREADY3 (adc_3_pready),
+ .PRDATA3 (adc_3_prdata),
+ .PSLVERR3 (adc_3_pslverr),
+
+ .PSEL4 (psel4),
+ .PREADY4 (1'b1),
+ .PRDATA4 (32'h00000000),
+ .PSLVERR4 (1'b1),
+
+ .PSEL5 (psel5),
+ .PREADY5 (1'b1),
+ .PRDATA5 (32'h00000000),
+ .PSLVERR5 (1'b1),
+
+ .PSEL6 (psel6),
+ .PREADY6 (1'b1),
+ .PRDATA6 (32'h00000000),
+ .PSLVERR6 (1'b1),
+
+ .PSEL7 (psel7),
+ .PREADY7 (1'b1),
+ .PRDATA7 (32'h00000000),
+ .PSLVERR7 (1'b1),
+
+ .PSEL8 (psel8),
+ .PREADY8 (1'b1),
+ .PRDATA8 (32'h00000000),
+ .PSLVERR8 (1'b1),
+
+ .PSEL9 (psel9),
+ .PREADY9 (1'b1),
+ .PRDATA9 (32'h00000000),
+ .PSLVERR9 (1'b1),
+
+ .PSEL10 (psel10),
+ .PREADY10 (1'b1),
+ .PRDATA10 (32'h00000000),
+ .PSLVERR10 (1'b1),
+
+ .PSEL11 (test_slave_psel),
+ .PREADY11 (test_slave_pready),
+ .PRDATA11 (test_slave_prdata),
+ .PSLVERR11 (test_slave_pslverr),
+
+ .PSEL12 (psel12),
+ .PREADY12 (1'b1),
+ .PRDATA12 (32'h00000000),
+ .PSLVERR12 (1'b1),
+
+ .PSEL13 (psel13),
+ .PREADY13 (1'b1),
+ .PRDATA13 (32'h00000000),
+ .PSLVERR13 (1'b1),
+
+ .PSEL14 (psel14),
+ .PREADY14 (1'b1),
+ .PRDATA14 (32'h00000000),
+ .PSLVERR14 (1'b1),
+
+ .PSEL15 (psel15),
+ .PREADY15 (1'b1),
+ .PRDATA15 (32'h00000000),
+ .PSLVERR15 (1'b1),
+
+ // Output
+ .PREADY (i_pready_mux),
+ .PRDATA (i_prdata_mux),
+ .PSLVERR (i_pslverr_mux)
+ );
+
+ // -----------------------------------------------------------------
+ // Timers
+
+ generate if (ADC_0_ENABLE == 1) begin : gen_adc_0
+ soclabs_adc u_adc_0 (
+ .PCLK (PCLK), // PCLK for timer operation
+ .PCLKG (PCLKG), // Gated PCLK for bus
+ .PRESETn (PRESETn), // Reset
+ // APB interface inputs
+ .PSEL (adc_0_psel),
+ .PADDR (i_paddr[11:2]),
+ .PENABLE (i_penable),
+ .PWRITE (i_pwrite),
+ .PWDATA (i_pwdata),
+ // APB interface outputs
+ .PRDATA (adc_0_prdata),
+ .PREADY (adc_0_pready),
+ .PSLVERR (adc_0_pslverr),
+
+ .EXTIN (adc_0_in), // Extenal input
+ .ADCINT (adc_0_irq) // interrupt output
+ );
+ end else
+ begin : gen_no_adc_0
+ assign adc_0_prdata = {32{1'b0}};
+ assign adc_0_pready = 1'b1;
+ assign adc_0_pslverr = 1'b0;
+ assign adc_0_irq = 1'b0;
+ end endgenerate
+
+
+ generate if (ADC_1_ENABLE == 1) begin : gen_adc_1
+ soclabs_adc u_adc_1 (
+ .PCLK (PCLK), // PCLK for timer operation
+ .PCLKG (PCLKG), // Gated PCLK for bus
+ .PRESETn (PRESETn), // Reset
+ // APB interface inputs
+ .PSEL (adc_1_psel),
+ .PADDR (i_paddr[11:2]),
+ .PENABLE (i_penable),
+ .PWRITE (i_pwrite),
+ .PWDATA (i_pwdata),
+ // APB interface outputs
+ .PRDATA (adc_1_prdata),
+ .PREADY (adc_1_pready),
+ .PSLVERR (adc_1_pslverr),
+
+ .EXTIN (adc_1_in), // Extenal input
+ .ADCINT (adc_1_irq) // interrupt output
+ );
+ end else
+ begin : gen_no_adc_1
+ assign adc_1_prdata = {32{1'b0}};
+ assign adc_1_pready = 1'b1;
+ assign adc_1_pslverr = 1'b0;
+ assign adc_1_irq = 1'b0;
+ end endgenerate
+
+
+ generate if (ADC_2_ENABLE == 1) begin : gen_adc_2
+ soclabs_adc u_adc_2 (
+ .PCLK (PCLK), // PCLK for timer operation
+ .PCLKG (PCLKG), // Gated PCLK for bus
+ .PRESETn (PRESETn), // Reset
+ // APB interface inputs
+ .PSEL (adc_2_psel),
+ .PADDR (i_paddr[11:2]),
+ .PENABLE (i_penable),
+ .PWRITE (i_pwrite),
+ .PWDATA (i_pwdata),
+ // APB interface outputs
+ .PRDATA (adc_2_prdata),
+ .PREADY (adc_2_pready),
+ .PSLVERR (adc_2_pslverr),
+
+ .EXTIN (adc_2_in), // Extenal input
+ .ADCINT (adc_2_irq) // interrupt output
+ );
+ end else
+ begin : gen_no_adc_2
+ assign adc_2_prdata = {32{1'b0}};
+ assign adc_2_pready = 1'b1;
+ assign adc_2_pslverr = 1'b0;
+ assign adc_2_irq = 1'b0;
+ end endgenerate
+
+
+ generate if (ADC_3_ENABLE == 1) begin : gen_adc_3
+ soclabs_adc u_adc_3 (
+ .PCLK (PCLK), // PCLK for timer operation
+ .PCLKG (PCLKG), // Gated PCLK for bus
+ .PRESETn (PRESETn), // Reset
+ // APB interface inputs
+ .PSEL (adc_3_psel),
+ .PADDR (i_paddr[11:2]),
+ .PENABLE (i_penable),
+ .PWRITE (i_pwrite),
+ .PWDATA (i_pwdata),
+ // APB interface outputs
+ .PRDATA (adc_3_prdata),
+ .PREADY (adc_3_pready),
+ .PSLVERR (adc_3_pslverr),
+
+ .EXTIN (adc_3_in), // Extenal input
+ .ADCINT (adc_3_irq) // interrupt output
+ );
+ end else
+ begin : gen_no_adc_3
+ assign adc_3_prdata = {32{1'b0}};
+ assign adc_3_pready = 1'b1;
+ assign adc_3_pslverr = 1'b0;
+ assign adc_3_irq = 1'b0;
+ end endgenerate
+
+ generate if (INCLUDE_IRQ_SYNCHRONIZER == 0) begin : gen_irq_synchroniser
+ // If PCLK is syncrhonous to HCLK, no need to have synchronizers
+ assign i_adc_0_irq = adc_0_irq;
+ assign i_adc_1_irq = adc_1_irq;
+ assign i_adc_2_irq = adc_2_irq;
+ assign i_adc_3_irq = adc_3_irq;
+ end else
+ begin : gen_no_irq_synchroniser
+ // If IRQ source are asyncrhonous to HCLK, then we
+ // need to add synchronizers to prevent metastability
+ // on interrupt signals.
+ cmsdk_irq_sync u_irq_sync_0 (
+ .RSTn (HRESETn),
+ .CLK (HCLK),
+ .IRQIN (adc_0_irq),
+ .IRQOUT(i_adc_0_irq)
+ );
+
+ cmsdk_irq_sync u_irq_sync_1 (
+ .RSTn (HRESETn),
+ .CLK (HCLK),
+ .IRQIN (adc_1_irq),
+ .IRQOUT(i_adc_1_irq)
+ );
+
+ cmsdk_irq_sync u_irq_sync_2 (
+ .RSTn (HRESETn),
+ .CLK (HCLK),
+ .IRQIN (adc_2_irq),
+ .IRQOUT(i_adc_2_irq)
+ );
+
+ cmsdk_irq_sync u_irq_sync_3 (
+ .RSTn (HRESETn),
+ .CLK (HCLK),
+ .IRQIN (adc_3_irq),
+ .IRQOUT(i_adc_3_irq)
+ );
+
+ end endgenerate
+
+
+
+ `ifdef ARM_APB_ASSERT_ON
+ // ------------------------------------------------------------
+ // Assertions
+ // ------------------------------------------------------------
+`include "std_ovl_defines.h"
+
+ // PSEL should be one-hot
+ // If this OVL fires - there is an error in the design of the address decoder
+ assert_zero_one_hot
+ #(`OVL_FATAL,16,`OVL_ASSERT,
+ "Only one PSEL input can be activated.")
+ u_ovl_psel_one_hot
+ (.clk(PCLK), .reset_n(PRESETn),
+ .test_expr({adc_0_psel,adc_1_psel,adc_2_psel,adc_3_psel,
+ psel4,psel5,psel6,psel7,psel8,psel9,psel10,psel11,psel12,psel13,psel14,psel15}));
+
+
+ // All Writes to the APB peripherals must be word size since PSTRB only
+ // supported on the APB test slave. Therefore, the AHB bridge can generate
+ // non-word sized writes which can break the APB peripherals (not
+ // including the the test slave) since they don't support this (i.e. PSTRB
+ // is not present). Hence, restrict the appropriate accesses to word sized
+ // writes.
+ assert_implication
+ #(`OVL_ERROR,`OVL_ASSERT,
+ "All Writes to the APB peripherals must be word size not including the test slave")
+ u_ovl_apb_write_word_size_32bits
+ (.clk (PCLK),
+ .reset_n (PRESETn),
+ .antecedent_expr (i_penable && i_psel && i_pwrite && (~test_slave_psel)),
+ .consequent_expr (i_pstrb == 4'b1111)
+ );
+
+ // This protocol checker is placed here and attached to the PCLK and PCLKEN.
+ // A note should be made that this means that the value of PCLKEN may not
+ // necessarily be the same as the enable term that is gating PCLK to generate
+ // PCLKG.
+ ApbPC #(.ADDR_WIDTH (16),
+ .DATA_WIDTH (32),
+ .SEL_WIDTH (1),
+ // OVL instances property_type (0=assert, 1=assume, 2=ignore)
+ .MASTER_REQUIREMENT_PROPTYPE (0),
+ .SLAVE_REQUIREMENT_PROPTYPE (0),
+
+ .PREADY_FUNCTIONAL (1),
+ .PSLVERR_FUNCTIONAL (1),
+ .PPROT_FUNCTIONAL (1),
+ .PSTRB_FUNCTIONAL (1)
+ ) u_ApbPC
+ (
+ // Inputs
+ .PCLK (PCLK),
+ .PRESETn (PRESETn),
+ .PSELx (i_psel),
+ .PPROT (i_pprot),
+ .PSTRB (i_pstrb),
+ .PENABLE (i_penable),
+ .PREADY (i_pready_mux),
+ .PSLVERR (i_pslverr_mux),
+ .PADDR (i_paddr),
+ .PWRITE (i_pwrite),
+ .PWDATA (i_pwdata),
+ .PRDATA (i_prdata_mux)
+ );
+
+
+`endif
+
+endmodule
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
index e17ffc5ff8c8ec2b99a2dafd0558ee1c41d3875a..5cb63f01ad43dda6766228a50265b89ffa72511a 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -37,6 +37,7 @@
// Also performs address decode for MTB
//-----------------------------------------------------------------------------
//
+`include "gen_defines.v"
module nanosoc_sysio_decode #(
parameter SYS_ADDR_W = 32,
@@ -47,8 +48,9 @@ module nanosoc_sysio_decode #(
// GPIO1 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000,
// Sysctrl base address
- parameter BASEADDR_SYSCTRL = 32'h4001_f000
- )(
+ parameter BASEADDR_SYSCTRL = 32'h4001_f000,
+ parameter BASEADDR_ADC = 32'h4002_0000
+)(
// System Address
input wire hsel,
input wire [SYS_ADDR_W-1:0] haddr,
@@ -58,7 +60,9 @@ module nanosoc_sysio_decode #(
output wire gpio0_hsel,
output wire gpio1_hsel,
output wire sysctrl_hsel,
-
+ `ifdef AMS_PERIPHERALS
+ output wire adcsys_hsel,
+ `endif
// Default slave
output wire defslv_hsel
);
@@ -81,14 +85,24 @@ module nanosoc_sysio_decode #(
BASEADDR_GPIO1[31:12]); // 0x40011000
assign sysctrl_hsel = hsel & (haddr[31:12]==
BASEADDR_SYSCTRL[31:12]); // 0x4001F000
-
+`ifdef AMS_PERIPHERALS
+ assign adcsys_hsel = hsel & (haddr[31:12]==
+ BASEADDR_ADC[31:12]); // 0x40020000
+`endif
// ----------------------------------------------------------
// Default slave decode logic
// ----------------------------------------------------------
-
+`ifdef AMS_PERIPHERALS
+ assign defslv_hsel = ~(apbsys_hsel |
+ gpio0_hsel | gpio1_hsel |
+ sysctrl_hsel | adcsys_hsel
+ );
+`else
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel
);
+`endif
+
endmodule
diff --git a/nanosoc/sl_ams_tech b/nanosoc/sl_ams_tech
new file mode 160000
index 0000000000000000000000000000000000000000..a4a0fcf677a5b5c0cdcd08062ad2e50f1129d5a0
--- /dev/null
+++ b/nanosoc/sl_ams_tech
@@ -0,0 +1 @@
+Subproject commit a4a0fcf677a5b5c0cdcd08062ad2e50f1129d5a0
diff --git a/software/common/validation/adc_tests.c b/software/common/validation/adc_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..4820fa9ebb70c001cae448929dc1be7bb6804c95
--- /dev/null
+++ b/software/common/validation/adc_tests.c
@@ -0,0 +1,286 @@
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ * (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ * ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ * SVN Information
+ *
+ * Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ * Revision : $Revision: 371321 $
+ *
+ * Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ A simple test to check the operation of APB slave multiplexer
+*/
+
+
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+int adc_detect(void);
+int adc_check_clk_div(void);
+#if defined ( __CC_ARM )
+__asm void address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ void address_test_write(unsigned int addr, unsigned int wdata);
+ unsigned int address_test_read(unsigned int addr);
+#endif
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+int ID_Check(const unsigned int id_array[], unsigned int offset);
+int APB_test_slave_Check(unsigned int offset);
+
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+ int hardfault_verbose=0; // 0:Not displaying anything in hardfault handler
+
+#define SL_ADC_BASE (0x40020000UL)
+#define SL_ADC_0_BASE (SL_ADC_BASE + 0x0000UL)
+
+int main (void)
+{
+
+ int err_code = 0;
+ int data[64];
+ int i;
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit");
+ puts(" - ADC test - revision $Revision: 371321 $\n");
+
+ if(adc_detect()!=0) {
+ return 0; // Quit test if ADC not present
+ }
+ err_code += adc_check_clk_div();
+ address_test_write(SL_ADC_0_BASE + 0x00C, 0x01);
+ printf("Enable ADC... \n");
+ printf("Read ADC Data: \n");
+ for (i =0; i<64; i++){
+ while(!address_test_read(SL_ADC_0_BASE+0x004)){;}
+ data[i]=address_test_read(SL_ADC_0_BASE);
+ }
+
+ for (i =0; i<64; i++){
+ printf("0x%02x \n",data[i]);
+ }
+
+ if (err_code==0) {
+ printf ("\n** TEST PASSED **\n");
+ } else {
+ printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code);
+ }
+ UartEndSimulation();
+ return 0;
+}
+
+int adc_check_clk_div(void)
+{
+ int clk_div_actual;
+
+ puts("Testing Clock Divider read/write access \n");
+ clk_div_actual = address_test_read(SL_ADC_0_BASE + 0x008);
+ printf("Clock divider after reset: %d\n", clk_div_actual);
+ address_test_write(SL_ADC_0_BASE + 0x008, 0x5E);
+ printf("Clock divider set to: 0x5E\n");
+ clk_div_actual = address_test_read(SL_ADC_0_BASE + 0x008);
+ printf("Clock divider set read: 0x%02X\n", clk_div_actual);
+ if(clk_div_actual!=0x320)
+ {
+ return 1;
+ }
+ else{
+ return 0;
+ }
+}
+
+int adc_detect(void)
+{
+ int result;
+ int volatile rdata;
+ unsigned const int adc_id[16] = {0x53, 0x4C, 0x00, 0x61, 0x64, 0x63, 0x00, 0x08};
+ puts("Detect if ADC is present...");
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ rdata = address_test_read(SL_ADC_0_BASE+ 0xFE0);
+ hardfault_expected = 0;
+ result = hardfault_occurred ? 1 : ID_Check(&adc_id[0], SL_ADC_0_BASE);
+ hardfault_occurred = 0;
+ if (result!=0) {
+ puts("** TEST SKIPPED ** ADC is not present.\n");
+ UartEndSimulation();
+ }
+ return(result);
+}
+
+
+int ID_Check(const unsigned int id_array[], unsigned int offset)
+{
+int i;
+unsigned long expected_val, actual_val;
+unsigned long compare_mask;
+int mismatch = 0;
+unsigned long test_addr;
+
+ /* Check the peripheral ID and component ID */
+ for (i=0;i<8;i++) {
+ test_addr = offset + 4*i + 0xFC0;
+ expected_val = id_array[i];
+ actual_val = HW32_REG(test_addr);
+
+ /* create mask to ignore version numbers */
+ if (i==2) { compare_mask = 0xF0;} // mask out version field
+ else { compare_mask = 0x00;} // compare whole value
+
+ if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
+ printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
+ mismatch++;
+ }
+
+ } // end_for
+return (mismatch);
+}
+
+#if defined ( __CC_ARM )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ STR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ BX LR
+}
+
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ __asm(" str r1,[r0]\n"
+ " dsb \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+ ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ if (hardfault_verbose) puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ if (hardfault_verbose) printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ if (hardfault_verbose) printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
+
+
diff --git a/testcodes/adc_tests/adc_tests.hex b/testcodes/adc_tests/adc_tests.hex
new file mode 100644
index 0000000000000000000000000000000000000000..df53d01d00e546f7efb2fc65f1ad03f522a0f76d
--- /dev/null
+++ b/testcodes/adc_tests/adc_tests.hex
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diff --git a/testcodes/adc_tests/makefile b/testcodes/adc_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..678fdb54bf613a930e2e59417df809e07713d405
--- /dev/null
+++ b/testcodes/adc_tests/makefile
@@ -0,0 +1,275 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+
+TARGET = arm-none-eabi
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = adc_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),ds6)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=Cortex-M0plus
+ else
+ CPU_TYPE = -mcpu=Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+ifeq ($(TOOL_CHAIN),ds6)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# D5-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ifeq ($(TOOL_CHAIN),ds6)
+ ARM_TARGET = --target=arm-$(TARGET)
+ CC_TOOL = armclang -O1
+ ASM_TOOL = armclang -masm=armasm $(ARM_TARGET) -c
+else
+ CC_TOOL = armcc -O3
+ ASM_TOOL = armasm
+ ARM_TARGET = -Otime
+endif
+
+ARM_CC_OPTIONS = $(ARM_TARGET) -c -g -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = $(TARGET)-gcc
+GNU_OBJDUMP = $(TARGET)-objdump
+GNU_OBJCOPY = $(TARGET)-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+all_ds6 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ $(ASM_TOOL) $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia