From 55869a680bc78f605da584f285860af6a6ccbacd Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 6 Jul 2023 12:10:29 +0100
Subject: [PATCH] Added Cocotb flow to simulation makefile

---
 .gitignore                   |  2 ++
 flows/makefile.fpga          |  4 ++--
 flows/makefile.simulate      | 38 +++++++++++++++++++++++++++++++++++-
 verif/cocotb/makefile        |  6 ++++++
 verif/cocotb/makefile.source | 25 ++++++++++++++++++++++++
 5 files changed, 72 insertions(+), 3 deletions(-)
 create mode 100644 verif/cocotb/makefile
 create mode 100644 verif/cocotb/makefile.source

diff --git a/.gitignore b/.gitignore
index aed68fe..d65cdde 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,6 @@
 # Exclude Simulation Files
+verif/cocotb/modelsim.ini
+verif/cocotb/transcript
 
 # Exclude Compiled Binaries
 /software/*/*.elf
diff --git a/flows/makefile.fpga b/flows/makefile.fpga
index c432db2..acfa471 100644
--- a/flows/makefile.fpga
+++ b/flows/makefile.fpga
@@ -64,7 +64,7 @@ code:
 	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) bootrom
 
 # Generate TCL filelist from flists
-flist_nanosoc: gen_defs
+flist_tcl_nanosoc: gen_defs
 	@mkdir -p $(TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
 	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
@@ -82,7 +82,7 @@ package_nanosoc: export FPGA_VENDOR             = $(NANOSOC_VENDOR)
 package_nanosoc: export FPGA_CORE_REV           = $(NANOSOC_CORE_REV)
 
 # Package NanoSoC IP
-package_nanosoc: code flist_nanosoc
+package_nanosoc: code flist_tcl_nanosoc
 	@echo Packaging NanoSoC
 	@mkdir -p $(RUN_DIR)
 	@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
diff --git a/flows/makefile.simulate b/flows/makefile.simulate
index eeea9bf..8274c9e 100644
--- a/flows/makefile.simulate
+++ b/flows/makefile.simulate
@@ -30,6 +30,28 @@ VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
 XMSIM_OPTIONS  = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
 XM_VC_OPTIONS  = -f $(TBENCH_VC) $(ADP_OPTIONS) 
 
+# ------- Cocotb Variables -----------
+# Convert Simulator Name for Cocotb
+COCOTB_SIMULATOR ?= questa
+
+ifeq ($(SIMULATOR),mti)
+	COCOTB_SIMULATOR := questa
+else ifeq ($(SIMULATOR),xm)
+	COCOTB_SIMULATOR := xcelium
+else ifeq ($(SIMULATOR),vcs)
+	COCOTB_SIMULATOR := vcs
+endif
+
+# Cocotb GUI Variable
+GUI ?= 0
+
+# Cocotb Scratch Directory
+COCOTB_DIR := $(SIM_TOP_DIR)/cocotb
+COCOTB_SCRATCH_DIR := $(COCOTB_DIR)/scratch
+
+# Filelist for Cocotb 
+MAKEFILE_FILELIST     := $(COCOTB_DIR)/makefile.flist
+
 # Create a List of PHONY Targets
 .PHONY: compile_$(SIMULATOR) run_$(SIMULATOR) sim_$(SIMULATOR)
 
@@ -125,4 +147,18 @@ sim_mti : code compile_mti
 
 # Create work directory
 lib_mti :
-	vlib work
\ No newline at end of file
+	vlib work
+
+# Generate Make filelist from flists
+flist_makefile_nanosoc: gen_defs
+	@mkdir -p $(COCOTB_DIR)
+	@(cd $(COCOTB_DIR); \
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -m -f $(DESIGN_VC) -o $(MAKEFILE_FILELIST);)
+	
+run_cocotb: flist_makefile_nanosoc
+	@mkdir -p $(SIM_DIR)
+	@cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR)/verif/cocotb clean SIM_BUILD=$(COCOTB_SCRATCH_DIR)
+	@cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR)/verif/cocotb sim SIM=$(COCOTB_SIMULATOR) MODULE=$(TESTNAME) GUI=$(GUI) SIM_BUILD=$(COCOTB_SCRATCH_DIR)
+
+sim_cocotb: GUI=1
+sim_cocotb: run_cocotb
diff --git a/verif/cocotb/makefile b/verif/cocotb/makefile
new file mode 100644
index 0000000..b51957f
--- /dev/null
+++ b/verif/cocotb/makefile
@@ -0,0 +1,6 @@
+
+SIM = questa
+PYTHON_BIN = /usr/bin/python3.8
+include makefile.source
+
+MODULE = test_nanosoc_chip
diff --git a/verif/cocotb/makefile.source b/verif/cocotb/makefile.source
new file mode 100644
index 0000000..17cd3a4
--- /dev/null
+++ b/verif/cocotb/makefile.source
@@ -0,0 +1,25 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOPLEVEL_LANG ?= verilog
+
+ifneq ($(TOPLEVEL_LANG),verilog)
+
+all:
+	@echo "Skipping test due to TOPLEVEL_LANG=$(TOPLEVEL_LANG) not being verilog"
+clean::
+
+else
+
+TOPLEVEL := nanosoc_tb
+
+PWD=$(shell pwd)
+
+COCOTB?=$(PWD)/../../..
+
+include $(SOCLABS_PROJECT_DIR)/simulate/sim/cocotb/makefile.flist
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+endif
-- 
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