diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
index ed3df93e7cfe6df1066b78dbc93af48b4006c44a..f5201f579f1bfa1da525dea7d61d314788f0e3aa 100644
--- a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
@@ -77,10 +77,10 @@ typedef enum IRQn
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/
- UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
- UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
- UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
- UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
+ EXP0_IRQn = 0, /*!< was UARTRX0_IRQn Interrupt */
+ EXP1_IRQn = 1, /*!< was UARTTX0_IRQn Interrupt */
+ EXP2_IRQn = 2, /*!< was UARTRX1_IRQn Interrupt */
+ EXP3_IRQn = 3, /*!< was UARTTX1_IRQn Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
@@ -88,9 +88,9 @@ typedef enum IRQn
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
- /*!< IRQ11 - Unused */
- UARTOVF0_IRQn = 12, /*!< UART 0 Overflow Interrupt */
- UARTOVF1_IRQn = 13, /*!< UART 1 Overflow Interrupt */
+ EXPB_IRQn = 11, /*!< was IRQ11 - Unused */
+ EXPC_IRQn = 12, /*!< was UART 0 Overflow Interrupt */
+ EXPD_IRQn = 13, /*!< was UART 1 Overflow Interrupt */
UARTOVF2_IRQn = 14, /*!< UART 2 Overflow Interrupt */
DMA_IRQn = 15, /*!< PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
diff --git a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
index 29bc88adfc2f1833ab75bc6b546bc6fa71690d66..723f4764a5e92e426e50f0ca70c19b144332def8 100644
--- a/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
+++ b/Cortex-M0/nanosoc/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
@@ -76,10 +76,10 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
- DCD UARTRX0_Handler ; UART 0 RX Handler
- DCD UARTTX0_Handler ; UART 0 TX Handler
- DCD UARTRX1_Handler ; UART 1 RX Handler
- DCD UARTTX1_Handler ; UART 1 TX Handler
+ DCD EXP0_Handler ; was: UARTRX0_Handler
+ DCD EXP1_Handler ; was: UARTTX0_Handler
+ DCD EXP2_Handler ; was: UARTRX1_Handler
+ DCD EXP3_Handler ; was: UARTTX1_Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
@@ -87,9 +87,9 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
- DCD 0 ; Reserved
- DCD UARTOVF0_Handler ; UART 0 Overflow Handler
- DCD UARTOVF1_Handler ; UART 1 Overflow Handler
+ DCD EXPB_Handler ; was: Reserved
+ DCD EXPC_Handler ; was: UARTOVF0_Handler Overflow Handler
+ DCD EXPD_Handler ; was: UARTOVF1_Handler Overflow Handler
DCD UARTOVF2_Handler ; UART 2 Overflow Handler
DCD DMA_Handler ; DMA handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
@@ -152,10 +152,10 @@ SysTick_Handler PROC
B .
ENDP
Default_Handler PROC
- EXPORT UARTRX0_Handler [WEAK]
- EXPORT UARTTX0_Handler [WEAK]
- EXPORT UARTRX1_Handler [WEAK]
- EXPORT UARTTX1_Handler [WEAK]
+ EXPORT EXP0_Handler [WEAK]
+ EXPORT EXP1_Handler [WEAK]
+ EXPORT EXP2_Handler [WEAK]
+ EXPORT EXP3_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
@@ -163,8 +163,9 @@ Default_Handler PROC
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
- EXPORT UARTOVF0_Handler [WEAK]
- EXPORT UARTOVF1_Handler [WEAK]
+ EXPORT EXPB_Handler [WEAK]
+ EXPORT EXPC_Handler [WEAK]
+ EXPORT EXPD_Handler [WEAK]
EXPORT UARTOVF2_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
@@ -183,10 +184,10 @@ Default_Handler PROC
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
-UARTRX0_Handler
-UARTTX0_Handler
-UARTRX1_Handler
-UARTTX1_Handler
+EXP0_Handler
+EXP1_Handler
+EXP2_Handler
+EXP3_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
@@ -194,8 +195,9 @@ PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
-UARTOVF0_Handler
-UARTOVF1_Handler
+EXPB_Handler
+EXPC_Handler
+EXPD_Handler
UARTOVF2_Handler
DMA_Handler
PORT0_0_Handler
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/aes128_tests/aes128_tests.c b/Cortex-M0/nanosoc/systems/mcu/testcodes/aes128_tests/aes128_tests.c
index 8df6aee230cb49927b612e3c07e06d075c25a137..42e24802a6151425dcf274037556d0bba0fc3fa2 100644
--- a/Cortex-M0/nanosoc/systems/mcu/testcodes/aes128_tests/aes128_tests.c
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/aes128_tests/aes128_tests.c
@@ -17,6 +17,19 @@ static volatile dma_pl230_channel_data aes_op_chain[2];
#define DMA_CHAN_AES128_IP (0)
#define DMA_CHAN_AES128_OP (1)
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+volatile int aes_key_irq_occurred;
+volatile int aes_key_irq_expected;
+volatile int aes_ip_irq_occurred;
+volatile int aes_ip_irq_expected;
+volatile int aes_op_irq_occurred;
+volatile int aes_op_irq_expected;
+volatile int aes_err_irq_occurred;
+volatile int aes_err_irq_expected;
+
uint8_t _test_key128[AES_KEY_LEN_128] = {
0x75, 0x46, 0x20, 0x67,
0x6e, 0x75, 0x4b, 0x20,
@@ -202,7 +215,7 @@ void aes128_driver_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input,
AES128->DRQ_MSK = 0;
AES128->IRQ_MSK = 0;
AES128->QUAL = 0;
- AES128->CTRL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT | AES128_CTRL_ERR_REQ_BIT;
// Set up parameters
if (mode == 1)
@@ -234,6 +247,7 @@ void aes128_driver_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input,
input += len;
result += len;
nbytes -= len;
+ AES128->IRQ_MSK_SET = (AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
}
AES128->CTRL = 0;
}
@@ -283,7 +297,7 @@ void aes128_driver_dma32(uint8_t *key, uint32_t nbytes, uint8_t *input,
AES128->DRQ_MSK = 0;
AES128->IRQ_MSK = 0;
AES128->QUAL = 0;
- AES128->CTRL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
// Set up parameters
if (mode == 1)
@@ -331,7 +345,7 @@ void aes128_driver_dma32(uint8_t *key, uint32_t nbytes, uint8_t *input,
;
AES128->DRQ_MSK = 0;
AES128->IRQ_MSK = 0;
- CMSDK_DMA->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
dma_pl230_init(0); // none active
return;
}
@@ -344,7 +358,7 @@ void aes128_driver_dma8(uint8_t *key, uint32_t nbytes, uint8_t *input,
AES128->DRQ_MSK = 0;
AES128->IRQ_MSK = 0;
AES128->QUAL = 0;
- AES128->CTRL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
// Set up parameters
if (mode == 1)
@@ -392,7 +406,7 @@ void aes128_driver_dma8(uint8_t *key, uint32_t nbytes, uint8_t *input,
;
AES128->DRQ_MSK = 0;
AES128->IRQ_MSK = 0;
- CMSDK_DMA->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
dma_pl230_init(0); // none active
return;
}
@@ -443,13 +457,40 @@ int main(void) {
}
id_string[12] = 0;
printf("%s\n",id_string);
+
+ aes_key_irq_occurred = 0;
+ aes_key_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP0_IRQn);
+ NVIC_EnableIRQ(EXP0_IRQn);
+ aes_ip_irq_occurred = 0;
+ aes_ip_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
+ aes_op_irq_occurred = 0;
+ aes_op_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP2_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
+ aes_err_irq_occurred = 0;
+ aes_err_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(EXP3_IRQn);
+
printf("AES128 SW (memcpy) tests...\n");
printf(" AES128 reference pattern test\n");
printf(" AES128 input/output bypass test\n");
aes128_bypass_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
-
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 2){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 1){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
printf(" AES128 encrypt test\n");
aes128_encrypt_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
@@ -458,10 +499,25 @@ int main(void) {
aes128_decrypt_memcpy(test_key128, sizeof(buf128), buf128, buf128);
fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+
printf(" AES128 logic toggle test\n");
printf(" AES128 input/output pattern test\n");
aes128_bypass_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != (129+1)){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 129){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
printf(" AES128 pattern encrypt test\n");
aes128_encrypt_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
printf(" AES128 pattern decrypt test\n");
@@ -470,10 +526,27 @@ int main(void) {
printf("AES128 DMA tests...\n");
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
printf(" AES128 dma input/output bypass test\n");
aes128_bypass_dma(test_key128, sizeof(test_text128), test_text128, buf128);
fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+ if (dma_done_irq_occurred < 2){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
printf(" AES128 dma encrypt test\n");
aes128_encrypt_dma(test_key128, sizeof(test_text128), test_text128, buf128);
fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
@@ -482,6 +555,12 @@ int main(void) {
aes128_decrypt_dma(test_key128, sizeof(buf128), buf128, buf128);
fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+ if (dma_done_irq_occurred < 6){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
printf(" AES128 dma unaligned pattern test\n");
aes128_bypass_dma(test_key128,(16*63), shift_patt, shift_buf1+3);
fail += aes128_buffer_verify((16*63), shift_buf1+3, shift_patt);
@@ -495,6 +574,28 @@ int main(void) {
aes128_decrypt_dma(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+ if (dma_done_irq_occurred < (2*7)){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ // check IRQ masked by DRQs - except when Iinput buffer empty after DMA done
+ if (aes_key_irq_occurred != 0){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 7){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 0){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ NVIC_DisableIRQ(DMA_IRQn);
+ NVIC_DisableIRQ(EXP0_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
+
printf ("Data retrieved from the AES is: %s\n", id_string);
printf ("Data expected from the AES is: %s\n", rx_char);
if (fail >0)
@@ -510,3 +611,78 @@ int main(void) {
}
+/* --------------------------------------------------------------- */
+/* Interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void DMA_Handler(void)
+{
+if ((DMA_PL230_DMAC->ERR_CLR & 1) != 0) {
+ /* DMA interrupt is caused by DMA error */
+ dma_error_irq_occurred ++;
+ DMA_PL230_DMAC->ERR_CLR = 1; /* Clear dma_err */
+ if (dma_error_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+else {
+ // DMA interrupt is caused by DMA done
+ dma_done_irq_occurred ++;
+ if (dma_done_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA done interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+}
+
+void EXP0_Handler(void)
+{
+ // AES128 interrupt is caused by Key Request IRQ
+ aes_key_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_KEY_REQ_BIT;
+ if (aes_key_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Key Request interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP1_Handler(void)
+{
+ // AES128 interrupt is caused by Key Request IRQ
+ aes_ip_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_IP_REQ_BIT;
+ if (aes_ip_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Input Buffer Reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP2_Handler(void)
+{
+ // AES128 interrupt is caused by Output Full Request IRQ
+ aes_op_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_OP_REQ_BIT;
+ if (aes_op_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Output full interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP3_Handler(void)
+{
+ // AES128 interrupt is caused by Error IRQ
+ aes_err_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_ERR_REQ_BIT;
+ if (aes_err_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
diff --git a/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz b/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz
index a371e317a9e60c2ad3e07ad0bbf81e7dd936cde3..35a2312298d655fb41fcb88be1aebe16587d1059 100644
Binary files a/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz and b/Cortex-M0/nanosoc/systems/mcu/v2html_doc.tgz differ
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
index 1d6ebe974b114be573f9d896977509cdc4735498..11126d04a91d53c1ddbc7654fb3f0148e55cc28e 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -397,7 +397,14 @@ localparam CORTEX_M0 = 1;
wire [15:0] p1_altfunc;
-
+ wire exp_irq0;
+ wire exp_irq1;
+ wire exp_irq2;
+ wire exp_irq3;
+ wire exp_irqB;
+ wire exp_irqC;
+ wire exp_irqD;
+
// -----------------------------------------------------------------------------
// AHB Interconnect declarations
// Upper-case AMBA naming convention maintained
@@ -850,10 +857,10 @@ localparam CORTEX_M0 = 1;
.dlast_ipdma128 (1'b0),
.drq_opdma128 (aes128_op_req),
.dlast_opdma128 (1'b0),
- .irq_key128 ( ),
- .irq_ip128 ( ),
- .irq_op128 ( ),
- .irq_error ( ),
+ .irq_key128 (exp_irq0),
+ .irq_ip128 (exp_irq1),
+ .irq_op128 (exp_irq2),
+ .irq_error (exp_irq3),
.irq_merged (aes128_irq)
);
@@ -1363,7 +1370,12 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
// match interrupts to CMSDK for validation code reuse
assign intnmi_cm0 = SYS_NMI;
- assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
+ //assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
+ assign intisr_cm0[ 0] = exp_irq0;
+ assign intisr_cm0[ 1] = exp_irq1;
+ assign intisr_cm0[ 2] = exp_irq2;
+ assign intisr_cm0[ 3] = exp_irq3;
+ assign intisr_cm0[ 5: 4] = SYS_APB_IRQ[ 5: 4];
assign intisr_cm0[ 6] = SYS_APB_IRQ[ 6] | gpio0_combintr;
assign intisr_cm0[ 7] = SYS_APB_IRQ[ 7] | gpio1_combintr;
assign intisr_cm0[14: 8] = SYS_APB_IRQ[14: 8];
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v b/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v
index 612dd5caca6accea1c68272ff6afc3be1e42abf9..ea3d362d960c05ed12f7f3c74d4e292ec8c8c6d2 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v
@@ -43,31 +43,27 @@ module soclabs_ahb_aes128_ctrl(
//----------------------------------------------------------------
///typedef struct {
-/// __I uint32_t CORE_NAME0; /* 0x0000 */
-/// __I uint32_t CORE_NAME1; /* 0x0004 */
-/// __I uint32_t CORE_VERSION; /* 0x0008 */
-/// uint32_t RESRV0C; /* 0x000C */
-/// __IO uint32_t CONTROL; /* 0x0010 */
-/// __O uint32_t CONTROL_SET; /* 0x0014 */
-/// __O uint32_t CONTROL_CLR; /* 0x0018 */
-/// __I uint32_t STATUS; /* 0x001c */
-/// __I uint32_t QUALIFIER; /* 0x0020 */
-/// uint32_t RESRV24[3]; /* 0x0024 - 2F*/
-/// __IO uint32_t DRQ_MSK; /* 0x0030 */
-/// __O uint32_t DRQ_MSK_SET; /* 0x0034 */
-/// __O uint32_t DRQ_MSK_CLR; /* 0x0038 */
-/// __I uint32_t DRQ_STATUS; /* 0x003C */
-/// __IO uint32_t IRQ_MSK; /* 0x0040 */
-/// __O uint32_t IRQ_MSK_SET; /* 0x0044 */
-/// __O uint32_t IRQ_MSK_CLR; /* 0x0048 */
-/// __I uint32_t IRQ_STATUS; /* 0x004C */
-/// uint32_t RESRV50[1024-80] /* 0x0050-0x3FFC (1024-(20*4)) */
-/// __IO unit32_t KYBUF128[1020]; /* 0x4000-7FEF */ (1024-4)
-/// __IO unit32_t KYBUF128END; /* 0x7FF0-7FFF */
-/// __IO unit32_t IPBUF128[1020]; /* 0x8000-BFEF */ (1024-4)
-/// __IO unit32_t IPBUF128END; /* 0xBFF0-BFFF */
-/// __IO unit32_t OPBUF128[1020]; /* 0xC000-FFEF */ (1024-4)
-/// __IO unit32_t OPBUF128END; /* 0xFFF0-FFFF */
+/// __I uint32_t CORE_NAME[2]; /* 0x0000-0007 */
+/// __I uint32_t CORE_VERSION; /* 0x0008-000B */
+/// uint32_t RESRV0C; /* 0x000C */
+/// __IO uint32_t CTRL; /* 0x0010 */
+/// __O uint32_t CTRL_SET; /* 0x0014 */
+/// __O uint32_t CTRLL_CLR; /* 0x0018 */
+/// __I uint32_t STATUS; /* 0x001c */
+/// __IO uint32_t QUAL; /* 0x0020 */
+/// uint32_t RESRV24[3]; /* 0x0024 - 2F*/
+/// __IO uint32_t DRQ_MSK; /* 0x0030 */
+/// __O uint32_t DRQ_MSK_SET; /* 0x0034 */
+/// __O uint32_t DRQ_MSK_CLR; /* 0x0038 */
+/// __I uint32_t DRQ_STATUS; /* 0x003C */
+/// __IO uint32_t IRQ_MSK; /* 0x0040 */
+/// __O uint32_t IRQ_MSK_SET; /* 0x0044 */
+/// __O uint32_t IRQ_MSK_CLR; /* 0x0048 */
+/// __I uint32_t IRQ_STATUS; /* 0x004C */
+/// uint32_t RESRV50[4076]; /* 0x0050-0x3FFC (4096-20 words) */
+/// __IO uint8_t KEY128[0x4000]; /* 0x4000-7FFF (0x3FFF is last alias) */
+/// __IO uint8_t TXTIP128[0x4000]; /* 0x8000-BFFF (0x3FFF is last alias) */
+/// __I uint8_t TXTOP128[0x4000]; /* 0xC000-FFFF (0x3FFF is last alias) */
///} AES128_TypeDef;
@@ -407,9 +403,9 @@ reg aes_err;
| (aes_err & !(sel_keybuf & wcyc_r));
end
- assign drq_active[REQ_KEYBUF_BIT] = control[CTRL_KEY_REQ_BIT] | (!aes_keyloaded_pulse & !aes_init & !aes_key_busy & !aes_key_rdy);
- assign drq_active[REQ_IP_BUF_BIT] = control[CTRL_IP_REQ_BIT] | (!aes_dataloaded_pulse & !aes_next & !aes_res_busy & !aes_res_rdy & aes_key_rdy);
- assign drq_active[REQ_OP_BUF_BIT] = control[CTRL_OP_REQ_BIT] | (!aes_res_busy & aes_res_rdy);
+ assign drq_active[REQ_KEYBUF_BIT] = control[CTRL_KEY_REQ_BIT] & (!aes_keyloaded_pulse & !aes_init & !aes_key_busy & !aes_key_rdy);
+ assign drq_active[REQ_IP_BUF_BIT] = control[CTRL_IP_REQ_BIT] & (!aes_dataloaded_pulse & !aes_next & !aes_res_busy & !aes_res_rdy & aes_key_rdy);
+ assign drq_active[REQ_OP_BUF_BIT] = control[CTRL_OP_REQ_BIT] & (!aes_res_busy & aes_res_rdy);
// input DMA channel shared by Key and Data-In
assign drq_ipdma128 = (drq_enable[REQ_KEYBUF_BIT] & drq_active[REQ_KEYBUF_BIT] & !wlast128) // if key DMA enabled
@@ -423,7 +419,7 @@ reg aes_err;
assign irq_active[REQ_KEYBUF_BIT] = drq_active[REQ_KEYBUF_BIT] & !drq_enable[REQ_KEYBUF_BIT];
assign irq_active[REQ_IP_BUF_BIT] = drq_active[REQ_IP_BUF_BIT] & !drq_enable[REQ_IP_BUF_BIT];
assign irq_active[REQ_OP_BUF_BIT] = drq_active[REQ_OP_BUF_BIT] & !drq_enable[REQ_OP_BUF_BIT];
- assign irq_active[REQ_ERROR_BIT ] = control[CTRL_ERR_REQ_BIT] | aes_err; // error raised in SW
+ assign irq_active[REQ_ERROR_BIT ] = control[CTRL_ERR_REQ_BIT] & aes_err; // error raised in SW
assign irq_key128 = irq_active[REQ_KEYBUF_BIT] & irq_enable[REQ_KEYBUF_BIT];
assign irq_ip128 = irq_active[REQ_IP_BUF_BIT] & irq_enable[REQ_IP_BUF_BIT];