diff --git a/.gitignore b/.gitignore
index b7ac34e947fe04a2aa58380e336bb19537b5da34..a550a88e1e9d4775effefbc25ad646b188662cc6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,24 +10,43 @@ ASIC/*.mr
ASIC/*.pvk
ASIC/alib-52
ASIC/WORK/*
-ASIC/*/Cadence/scripts/fv
-ASIC/*/Cadence/scripts/*.rpt
-ASIC/*/Cadence/scripts/*.tstamp
-
-ASIC/*/Cadence/scripts/.cadence
-ASIC/*/Cadence/scripts/.*
-ASIC/*/Cadence/scripts/*.spec
-ASIC/*/Cadence/scripts/*.sdf
-ASIC/*/Cadence/scripts/*.gif
-ASIC/*/Cadence/scripts/*.lef
-ASIC/*/Cadence/scripts/result
-ASIC/*/Cadence/scripts/nanosoc_chip_pads
-ASIC/*/Cadence/scripts/timingReports
-ASIC/*/Cadence/scripts/*.db*
-ASIC/*/Cadence/scripts/*.rpt*
-ASIC/*/Cadence/scripts/*.checkFPlan
-ASIC/*/Cadence/scripts/*.ptiavg
-ASIC/*/Cadence/scripts/*.ptifiles
+ASIC/*/*/Cadence/scripts/fv
+ASIC/*/*/Cadence/scripts/*.rpt
+ASIC/*/*/Cadence/scripts/*.tstamp
+ASIC/*/*/Cadence/scripts/.cadence
+ASIC/*/*/Cadence/scripts/.*
+ASIC/*/*/Cadence/scripts/*.spec
+ASIC/*/*/Cadence/scripts/*.sdf
+ASIC/*/*/Cadence/scripts/*.gif
+ASIC/*/*/Cadence/scripts/*.lef
+ASIC/*/*/Cadence/scripts/result
+ASIC/*/*/Cadence/scripts/nanosoc_chip_pads
+ASIC/*/*/Cadence/scripts/timingReports
+ASIC/*/*/Cadence/scripts/*.db*
+ASIC/*/*/Cadence/scripts/*.rpt*
+ASIC/*/*/Cadence/scripts/*.checkFPlan
+ASIC/*/*/Cadence/scripts/*.ptiavg
+ASIC/*/*/Cadence/scripts/*.ptifiles
+ASIC/*/*/Cadence/scripts/*.dofile
+ASIC/*/*/Cadence/scripts/*.testproc
+ASIC/*/*/Cadence/scripts/scheduling_file.cts.*
+ASIC/*/*/Synopsys_FC/HDL_LIBRARIES
+ASIC/*/*/Synopsys_FC/nanosoc_chip_pads.dlib
+ASIC/*/*/Synopsys_FC/*.txt
+ASIC/*/*/Synopsys_FC/fc_output.txt
+ASIC/*/*/Synopsys_FC/*.log
+ASIC/*/*/Synopsys_FC/check_design.ems
+ASIC/*/*/Synopsys_FC/PreFrameCheck
+ASIC/*/*/Synopsys_FC/*.svf
+ASIC/*/*/Synopsys_FC/rom_via
+ASIC/*/*/Synopsys_FC/sram_16k
+ASIC/*/*/Synopsys_FC/pad_lib
+ASIC/*/*/Synopsys_FC/.*/
+ASIC/*/*/Synopsys_FC/cln28ht
+ASIC/*/*/Synopsys_FC/cln28ht_pmk
+ASIC/*/*/Synopsys_FC/cln28ht_ret
+ASIC/*/*/Synopsys_FC/io_lib
+ASIC/*/*/Synopsys_FC/legalizer_debug_plots
ASIC/Synopsys/Formality/FM_INFO/*
ASIC/Synopsys/ICC2/CLIBs
ASIC/Synopsys/ICC2/PreFrameCheck
@@ -35,6 +54,15 @@ ASIC/Synopsys/ICC2/tsmc65lp/*
ASIC/Synopsys/ICC2/*.svf
ASIC/Synopsys/ICC2/*.ems
ASIC/Synopsys/ICC2/icc2_output.txt
+
+ASIC/TSMC28nm/no_pins/Synopsys_FC/cln28ht
+ASIC/TSMC28nm/no_pins/Synopsys_FC/rom_via
+ASIC/TSMC28nm/no_pins/Synopsys_FC/PreFrameCheck
+ASIC/TSMC28nm/no_pins/Synopsys_FC/sram_16k
+ASIC/TSMC28nm/no_pins/Synopsys_FC/*.svf
+ASIC/TSMC28nm/no_pins/Synopsys_FC/*.txt
+ASIC/TSMC28nm/no_pins/Synopsys_FC/*.log
+ASIC/TSMC28nm/no_pins/Synopsys_FC/.*
*.pvl
*.syn
*.mr
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/FC_flow.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/FC_flow.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5f51a5eeec97f7afefe325f42dc99274a572c742
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/FC_flow.tcl
@@ -0,0 +1,51 @@
+# Main flow for Synopsys fusion compiler
+set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+# Design setup: read libraries and RTL
+redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
+
+# Floorplan setup
+redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1111.1111111 1111.11111} -core_offset {140}}
+redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
+place_io
+# Read Constraints
+redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../../constraints.sdc}
+
+# Power Plan
+load_upf nanosoc_chip_pads.upf
+create_voltage_area -power_domains ACCEL
+create_voltage_area -power_domains PD_DBG
+create_voltage_area -power_domains PD_SYS
+
+create_voltage_area_shape -voltage_area ACCEL \
+ -region {{{140.000 140.000} {370.655 311.165}}} \
+ -guard_band {2 2}
+
+create_voltage_area_shape -voltage_area PD_DBG \
+ -region {{{703.115 140.000} {971.040 329.520}}} \
+ -guard_band {2 2}
+create_voltage_area_shape -voltage_area PD_SYS \
+ -region {{{234.000 453.940} {548.100 645.665}}} \
+ -guard_band {2 2}
+
+create_pg_region {pg_accel} -voltage_area {ACCEL}
+create_pg_region {pg_dbg} -voltage_area {PD_DBG}
+create_pg_region {pg_sys} -voltage_area {PD_SYS}
+
+redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
+
+# Init coarse placement
+redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
+
+# Physical aware synthesis
+redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
+redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
+save_lib nanosoc_chip_pads.dlib
+
+redirect -tee -file $LOG_DIR/08_clock_tree.log {synthesize_clock_trees -clocks {clk swdclk}}
+redirect -tee -file $LOG_DIR/09_clock_opt.log {clock_opt}
+redirect -tee -file $REPORT_DIR/timing_02_clock_opt.rep {report_timing}
+
+
+
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/design_setup.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/design_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7e44835bf109166bfcc269618781e38bd1029547
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/design_setup.tcl
@@ -0,0 +1,31 @@
+set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+
+set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
+
+set TLU_cbest $TLU_dir/cbest.tluplus
+set TLU_cworst $TLU_dir/cworst.tluplus
+set TLU_rcbest $TLU_dir/rcbest.tluplus
+set TLU_rcworst $TLU_dir/rcworst.tluplus
+set TLU_map $TLU_dir/tluplus.map
+
+create_lib nanosoc_chip_pads.dlib \
+ -technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf \
+ -ref_libs {./cln28ht/ ./cln28ht_pmk/ ./cln28ht_ret/ ./sram_16k/ ./rom_via/ ./io_lib/ ./pad_lib/}
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
+
+elaborate nanosoc_chip_pads
+set_top_module nanosoc_chip_pads
+
+redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
+redirect -tee -file ./lib_cell_pmk_summary.log {report_lib -cell_summary cln28ht_pmk}
+redirect -tee -file ./lib_cell_ret_summary.log {report_lib -cell_summary cln28ht_ret}
+
+read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
+
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def
new file mode 100644
index 0000000000000000000000000000000000000000..d6f55e61f0bd705211fe4d0465be905b6bd3be39
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def
@@ -0,0 +1,13 @@
+#
+# Fusion Compiler write_def
+# Release : U-2022.12
+# User Name : dwn1c21
+# Date : Fri Oct 25 13:42:48 2024
+#
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN nanosoc_chip_pads ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 0 1110700 ) ( 1111040 1110700 ) ( 1111040 0 ) ;
+END DESIGN
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..34eb70e0d6233d6bba3cb024dd500cbbfbcb1e3f
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl
@@ -0,0 +1,51 @@
+################################################################################
+#
+# Created by fc write_floorplan on Fri Oct 25 13:42:48 2024
+#
+################################################################################
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+source ${_dirName__0}/fp.tcl
+
+if { [get_attribute -name view_name [current_block]] == "design" } {
+ set __fp_crnt_design_name__ [get_attribute -name design_name [current_block]]
+ set __fp_crnt_label_name__ [get_attribute -name label_name [current_block]]
+ set __fp_crnt_lib_name__ [get_attribute -name lib_name [current_block]]
+ set __fp_crnt_lib_path__ [get_attribute -name source_file_name [current_lib]]
+ set __fp_crnt_abs_name__ ${__fp_crnt_lib_name__}:${__fp_crnt_design_name__}
+ set __fp_crnt_abs_path__ ${__fp_crnt_lib_path__}/${__fp_crnt_design_name__}
+ if { [string length ${__fp_crnt_label_name__} ] != 0 } {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}/${__fp_crnt_label_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/design_label.${__fp_crnt_label_name__}/abs
+ } else {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/abs
+ }
+ if { [sizeof_collection [get_blocks -quiet ${__fp_crnt_abs_name__}]] != 0} {
+ if { [get_attribute -name has_editable_abstract [current_block]] } {
+ echo "Design [get_attribute -name full_name [current_block]] has editable abstract view. Re-creating the abstract view after floorplan loading..."
+ set __fp_crnt_abs_type__ [get_attribute -quiet -name abstract_view_type [current_block]]
+ if { [string length ${__fp_crnt_abs_type__} ] == 0 } {
+ if { [file exists "${__fp_crnt_abs_path__}/abs.mc"] } {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ } else {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ }
+ } elseif { ${__fp_crnt_abs_type__} == "placement" } {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ } else {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ }
+ }
+ }
+}
+
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9b75f8bb7e6f0761ac431ebed19494ba9d241086
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
@@ -0,0 +1,44 @@
+################################################################################
+#
+# Created by fc compare_floorplans on Fri Oct 25 13:42:48 2024
+#
+# DO NOT EDIT - automatically generated file
+#
+################################################################################
+
+START nanosoc_chip_pads
+ MACROS
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {140.0000 919.4450} {304.6650 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {626.6800 781.1650} {798.8600 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {798.8600 781.1650} {971.0400 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {798.8600 563.3200} {971.0400 752.8550} }
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {626.6800 563.3200} {798.8600 752.8550} }
+ PINS
+ VDDIO { {555.5200 555.3500} {555.5201 555.3501} }
+ VSSIO { {555.5200 555.3500} {555.5201 555.3501} }
+ VDD { {555.5200 555.3500} {555.5201 555.3501} }
+ VSS { {555.5200 555.3500} {555.5201 555.3501} }
+ VDDACC { {555.5200 555.3500} {555.5201 555.3501} }
+ SE { {555.5200 555.3500} {555.5201 555.3501} }
+ CLK { {555.5200 555.3500} {555.5201 555.3501} }
+ TEST { {555.5200 555.3500} {555.5201 555.3501} }
+ NRST { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[7] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[6] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[5] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[4] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[3] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[2] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[1] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[0] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[7] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[6] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[5] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[4] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[3] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[2] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[1] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[0] { {555.5200 555.3500} {555.5201 555.3501} }
+ SWDIO { {555.5200 555.3500} {555.5201 555.3501} }
+ SWDCK { {555.5200 555.3500} {555.5201 555.3501} }
+END nanosoc_chip_pads
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..059b00a2130c7fac183d69ce138f595af3ad6e48
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl
@@ -0,0 +1,200 @@
+################################################################################
+#
+# Created by fc write_floorplan on Fri Oct 25 13:42:48 2024
+#
+################################################################################
+
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+################################################################################
+# Read DEF
+################################################################################
+
+read_def ${_dirName__0}/floorplan.def
+
+################################################################################
+# Macros
+################################################################################
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 140.0000 919.4450 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }
+create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }
+create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
+ 2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 781.1650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
+ 2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 781.1650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
+ 2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 563.3200 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
+ 2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 563.3200 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }
+create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
+ 2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }
+
+
+################################################################################
+# User attributes of macros
+################################################################################
+
+
+################################################################################
+# Bounds and user attributes of bound shapes
+################################################################################
+
+remove_bounds -all
+
+
+################################################################################
+# User attributes of bounds
+################################################################################
+
+
+################################################################################
+# Blockages
+################################################################################
+
+remove_routing_blockages -all -force
+
+remove_placement_blockages -all -force
+
+remove_pin_blockages -all
+
+remove_shaping_blockages -all
+
+################################################################################
+# User attributes of blockages
+################################################################################
+
+################################################################################
+# Module Boundaries
+################################################################################
+
+set hbCells [get_cells -quiet -filter hierarchy_type==boundary -hierarchical]
+if [sizeof_collection $hbCells] {
+ set_cell_hierarchy_type -type normal $hbCells
+}
+
+
+################################################################################
+# I/O guides
+################################################################################
+
+remove_io_guides -all
+
+create_io_guide -name main_io_ring.left -side left -line { {0.0000 110.0000} \
+ 890.7000 } -offset {0.0000 0.0000} -pad_cells { uPAD_CLK_I uPAD_NRST_I \
+ uPAD_P0_00 uPAD_P0_01 uPAD_P0_02 uPAD_P0_03 uPAD_P0_04 uPAD_P0_05 uPAD_P0_06 }
+create_io_guide -name main_io_ring.bottom -side bottom -line { {1001.0400 \
+ 0.0000} 891.0400 } -offset {0.0000 0.0000} -pad_cells { uPAD_P0_07 \
+ uPAD_P1_00 uPAD_P1_01 uPAD_P1_02 uPAD_P1_03 uPAD_P1_04 uPAD_P1_05 \
+ uPAD_P1_06 uPAD_P1_07 uPAD_SE_I }
+create_io_guide -name main_io_ring.right -side right -line { {1111.0400 \
+ 1000.7000} 890.7000 } -offset {0.0000 0.0000} -pad_cells { uPAD_SWDCK_I \
+ uPAD_SWDIO_IO uPAD_TEST_I uPAD_VDDACC_0 uPAD_VDDACC_1 uPAD_VDDACC_2 \
+ uPAD_VDDIO_0 uPAD_VDDIO_2 uPAD_VDDIO_3 }
+create_io_guide -name main_io_ring.top -side top -line { {110.0000 1110.7000} \
+ 891.0400 } -offset {0.0000 0.0000} -pad_cells { uPAD_VDD_0 uPAD_VDD_1 \
+ uPAD_VDD_2 uPAD_VDD_3 uPAD_VSSIO_0 uPAD_VSSIO_1 uPAD_VSS_0 uPAD_VSS_1 \
+ uPAD_VSS_2 uPAD_VSS_3 }
+
+################################################################################
+# User attributes of I/O guides
+################################################################################
+
+
+################################################################################
+# User attributes of current block
+################################################################################
+
+
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/mapfile b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/mapfile
new file mode 100644
index 0000000000000000000000000000000000000000..1af7533494755299cc3dee06e1613fbfb52d4cb6
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/mapfile
@@ -0,0 +1 @@
+nanosoc_chip_pads FLOORPLAN fp.tcl
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/init_placement.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/init_placement.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1fe3a0cc10b4fe2d754395cfd45684879e04b451
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/init_placement.tcl
@@ -0,0 +1,16 @@
+set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
+set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
+set_temperature -40 -min 125 -corners default
+set_voltage 0.81 -min 0.99 -corners default
+
+
+set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD}] 0.81
+set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD_SYS}] 0.81
+set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD_DBG}] 0.81
+set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDDACC}] 0.81
+set_voltage -min 0.0 -corners default -object_list [get_supply_nets {VSS}] 0.0
+redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
+
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
+explore_logic_hierarchy -place -rectangular
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/nanosoc_chip_pads.upf b/ASIC/TSMC28nm/38pin/Synopsys_FC/nanosoc_chip_pads.upf
new file mode 100644
index 0000000000000000000000000000000000000000..63e386c00a7042c76b577de20016ba8100d2af98
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/nanosoc_chip_pads.upf
@@ -0,0 +1,138 @@
+
+################################################################################
+# Create power domains
+################################################################################
+create_power_domain TOP
+create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
+create_power_domain PD_SYS -elements u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys
+create_power_domain PD_DBG -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_dbg \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_dap/u_ap}
+
+################################################################################
+# Create and logically connect power ports and nets
+################################################################################
+
+# Always on VDD
+create_supply_port VDD
+create_supply_net VDD -domain TOP
+create_supply_net VDD -domain PD_SYS -reuse
+create_supply_net VDD -domain PD_DBG -reuse
+connect_supply_net VDD -ports VDD
+
+# Ground
+create_supply_port VSS
+create_supply_net VSS -domain TOP
+create_supply_net VSS -domain PD_SYS -reuse
+create_supply_net VSS -domain PD_DBG -reuse
+create_supply_net VSS -domain ACCEL -reuse
+connect_supply_net VSS -ports VSS
+
+# Switched VDD
+create_supply_net VDD_SYS -domain PD_SYS -resolve parallel
+create_supply_net VDD_DBG -domain PD_DBG -resolve parallel
+
+# VDDACC
+create_supply_port VDDACC
+create_supply_net VDDACC -domain ACCEL
+connect_supply_net VDDACC -ports VDDACC
+
+################################################################################
+# Assign power supplies to power domains
+################################################################################
+
+set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
+set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+set_domain_supply_net PD_SYS -primary_power_net VDD_SYS -primary_ground_net VSS
+set_domain_supply_net PD_DBG -primary_power_net VDD_DBG -primary_ground_net VSS
+
+################################################################################
+# Create Power Switches
+################################################################################
+
+create_power_switch uswitch1 -domain PD_SYS \
+ -input_supply_port {VDD VDD} \
+ -output_supply_port {VDD_SYS VDD_SYS} \
+ -control_port {SYSPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWN} \
+ -ack_port {SYSPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWNACK {SYSPWRDOWN}} \
+ -ack_delay {SYSPWRDOWNACK 65000} \
+ -on_state {on_state VDD {!SYSPWRDOWN}} \
+ -off_state {off_state { SYSPWRDOWN}}
+
+create_power_switch uswitch2 -domain PD_DBG \
+ -input_supply_port {VDD VDD} \
+ -output_supply_port {VDD_DBG VDD_DBG} \
+ -control_port {DBGPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWN} \
+ -ack_port {DBGPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWNACK {DBGPWRDOWN}} \
+ -ack_delay {DBGPWRDOWNACK 65000} \
+ -on_state {on_state VDD {!DBGPWRDOWN}} \
+ -off_state {off_state { DBGPWRDOWN}}
+
+################################################################################
+# Set Isolation Controls
+# - iso_low1, iso_high1 at PD_SYS outputs
+# - iso_low2 at PD_DBG outputs
+################################################################################
+
+set_isolation iso_low1 -domain PD_SYS \
+ -isolation_power_net VDD \
+ -isolation_ground_net VSS \
+ -clamp_value 0 \
+ -applies_to outputs
+
+# The signals that need to be clamped HIGH
+set_isolation iso_high1 -domain PD_SYS \
+ -isolation_power_net VDD \
+ -isolation_ground_net VSS \
+ -clamp_value 1 \
+ -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleeping_o \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleep_deep_o}
+
+set_isolation_control iso_low1 -domain PD_SYS \
+ -isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
+ -isolation_sense low \
+ -location parent
+
+set_isolation_control iso_high1 -domain PD_SYS \
+ -isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
+ -isolation_sense low \
+ -location parent
+
+set_isolation iso_low2 -domain PD_DBG \
+ -isolation_power_net VDD \
+ -isolation_ground_net VSS \
+ -clamp_value 0 \
+ -applies_to outputs
+
+set_isolation_control iso_low2 -domain PD_DBG \
+ -isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGISOLATEn \
+ -isolation_sense low \
+ -location parent
+
+################################################################################
+# Set Retention
+################################################################################
+
+set_retention drff -domain PD_SYS -retention_power_net VDD -retention_ground_net VSS
+set_retention_control drff -domain PD_SYS -save_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn high} \
+ -restore_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn low}
+
+map_retention_cell drff -domain PD_SYS -lib_cell_type DRFF
+
+################################################################################
+# Define port states
+################################################################################
+
+add_port_state VSS -state {on 0.0 0.0 0.0}
+add_port_state VDD -state {on 0.81 0.9 0.99}
+add_port_state VDDACC -state {on 0.81 0.9 0.99}
+add_port_state uswitch1/VDD_SYS -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
+add_port_state uswitch2/VDD_DBG -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
+
+################################################################################
+# Define power state table
+################################################################################
+
+create_pst cm0_pst -supplies {VSS VDD VDD_SYS VDD_DBG VDDACC}
+add_pst_state run -pst cm0_pst -state {on on on off on }
+add_pst_state slp -pst cm0_pst -state {on on off off on }
+add_pst_state dbg -pst cm0_pst -state {on on on on on }
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/power_plan.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..014f1a83598cbc7e4a24a45563740f22984b44d7
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/power_plan.tcl
@@ -0,0 +1,28 @@
+connect_pg_net -create_nets_only
+connect_pg_net -automatic
+
+create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
+ -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
+set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VDDACC VSS}} {offset: {3 3}}} -core
+compile_pg -strategies core_ring
+
+
+create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
+ {{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
+set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VDDACC VSS}}} -core
+compile_pg -strategies M5M8_mesh
+
+
+create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
+set_pg_strategy std_cell_accel -voltage_areas ACCEL -pattern {{name : std_pattern}{nets : {VDDACC VSS}}}
+set_pg_strategy std_cell_dbg -voltage_areas PD_DBG -pattern {{name : std_pattern}{nets : {VDD_DBG VSS}}}
+set_pg_strategy std_cell_sys -voltage_areas PD_SYS -pattern {{name : std_pattern}{nets : {VDD_SYS VSS}}}
+
+set_pg_strategy std_cell_strat -voltage_areas DEFAULT_VA -pattern {{name: std_pattern} {nets: {VDD VSS}}}
+
+compile_pg -strategies std_cell_accel
+compile_pg -strategies std_cell_dbg
+compile_pg -strategies std_cell_sys
+
+
+compile_pg -strategies std_cell_strat
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/synopsys_lib_conversion.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0e54a812fa410c71f725f9668874da0e1c8f47b7
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/synopsys_lib_conversion.tcl
@@ -0,0 +1,126 @@
+## Paths Please Edit for your system
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+set pmk_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_pmk_svt_c35/r1p0
+set ret_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_rklo_lvt_svt_c30_c35/r1p0
+
+# Technology files
+set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf
+set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.lef
+
+# Standard Cell libraries
+set standard_cell_lef_file $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
+set standard_cell_gds_file $standard_cell_base_path/gds2/sc12mcpp140z_cln28ht_base_svt_c35.gds2
+set standard_cell_db_file_ss_0p81v_125C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set standard_cell_db_file_tt_0p90v_25C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
+set standard_cell_db_file_ff_0p99v_m40C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set standard_cell_antenna_file $standard_cell_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_base_svt_c35_antenna.clf
+
+# Power Management Kit
+set pmk_lef_file $pmk_base_path/lef/sc12mcpp140z_cln28ht_pmk_svt_c35.lef
+set pmk_gds_file $pmk_base_path/gds2/sc12mcpp140z_cln28ht_pmk_svt_c35.gds2
+set pmk_db_file_ss_0p81v_125C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set pmk_db_file_tt_0p90v_25C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_25c.db
+set pmk_db_file_ff_0p99v_m40C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set pmk_antenna_file $pmk_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_pmk_svt_c35_antenna.clf
+
+# Retention Kit
+set ret_lef_file $ret_base_path/lef/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.lef
+set ret_gds_file $ret_base_path/gds2/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.gds2
+set ret_db_file_ss_0p81v_125C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p81v_125c.db
+set ret_db_file_tt_0p90v_25C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_25c.db
+set ret_db_file_ff_0p99v_m40C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_m40c.db
+set ret_antenna_file $ret_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_antenna.clf
+
+
+# IO Paths
+set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
+set tphn28hpcpgv18_lef_file $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/6lm/lef/tphn28hpcpgv18_6lm.lef
+set tphn28hpcpgv18_lib_path $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
+set IO_TT_0p9v_1p8v_25c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18tt0p9v1p8v25c.db
+set IO_FF_0p99v_1p98v_m40c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ffg0p99v1p98vm40c.db
+set IO_SS_0p81v_1p62v_125c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ssg0p81v1p62v125c.db
+
+set pad_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
+
+# SRAM files (using Arm compiler)
+set sram_16k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
+set sram_16k_lef_file $sram_16k_path/sram_16k.lef
+set sram_16k_gds_file $sram_16k_path/sram_16k.gds2
+set sram_16k_lib_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_16k_lib_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
+set sram_16k_lib_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
+set sram_16k_db_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_16k_db_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.db
+set sram_16k_db_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
+
+# ROM Files (using arm Compiler)
+set rom_path $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+set rom_via_lef_file $rom_path/rom_via.lef
+set rom_via_gds_file $rom_path/rom_via.gds2
+set rom_via_lib_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
+set rom_via_lib_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
+set rom_via_lib_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib
+set rom_via_db_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db
+set rom_via_db_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
+set rom_via_db_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
+
+# Create standard cell fusion library
+create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p81v_125C $standard_cell_db_file_tt_0p90v_25C $standard_cell_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $standard_cell_lef_file] -technology $cln28ht_tech_file cln28ht
+save_fusion_lib cln28ht
+close_fusion_lib cln28ht
+
+# Create Power Management Kit fusion library
+create_fusion_lib -dbs [list $pmk_db_file_ss_0p81v_125C $pmk_db_file_tt_0p90v_25C $pmk_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $pmk_lef_file] -technology $cln28ht_tech_file cln28ht_pmk
+save_fusion_lib cln28ht_pmk
+close_fusion_lib cln28ht_pmk
+
+# Create Retention fusion library
+create_fusion_lib -dbs [list $ret_db_file_ss_0p81v_125C $ret_db_file_tt_0p90v_25C $ret_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $ret_lef_file] -technology $cln28ht_tech_file cln28ht_ret
+save_fusion_lib cln28ht_ret
+close_fusion_lib cln28ht_ret
+
+# 16K SRAM
+read_lib $sram_16k_lib_file_ss_0p81v_125c
+write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
+
+read_lib $sram_16k_lib_file_tt_0p90v_25c
+write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_85c
+close_lib -all
+
+read_lib $sram_16k_lib_file_ff_0p99v_m40c
+write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
+save_fusion_lib sram_16k
+close_fusion_lib sram_16k
+
+# Boot ROM
+read_lib $rom_via_lib_file_ss_0p81v_125c
+write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
+
+read_lib $rom_via_lib_file_tt_0p90v_25c
+write_lib -output $rom_via_db_file_tt_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
+
+read_lib $rom_via_lib_file_ff_0p99v_m40c
+write_lib -output $rom_via_db_file_ff_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $rom_via_db_file_ss_0p81v_125c $rom_via_db_file_tt_0p90v_25c $rom_via_db_file_ff_0p99v_m40c] -lefs $rom_via_lef_file -technology $cln28ht_tech_file rom_via
+save_fusion_lib rom_via
+close_fusion_lib rom_via
+
+# IO Lib
+create_fusion_lib -dbs [list $IO_SS_0p81v_1p62v_125c_db $IO_TT_0p9v_1p8v_25c_db $IO_FF_0p99v_1p98v_m40c_db] -lefs $tphn28hpcpgv18_lef_file -technology $cln28ht_tech_file io_lib
+save_fusion_lib io_lib
+close_fusion_lib io_lib
+
+# Pad Lib
+create_fusion_lib -lefs $pad_lef_file -technology $cln28ht_tech_file pad_lib
+save_fusion_lib pad_lib
+close_fusion_lib pad_lib
+exit
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/constraints.sdc b/ASIC/TSMC28nm/constraints.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..024c31d325ac47a1df9732abb51f387806af9eb9
--- /dev/null
+++ b/ASIC/TSMC28nm/constraints.sdc
@@ -0,0 +1,71 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### CLOCK DEFINITION
+
+set EXTCLK "clk";
+set SWDCLK "swdclk";
+set_units -time ns;
+
+set_units -capacitance pF;
+set EXTCLK_PERIOD 4.16667;
+set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
+set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
+set INTER_CLOCK_UNCERTAINTY 0.1
+
+create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
+create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
+
+set_clock_uncertainty $CLK_ERROR [get_clocks $EXTCLK]
+set_clock_uncertainty $CLK_ERROR [get_clocks $SWDCLK]
+
+set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $SWDCLK] -rise_to [get_clocks $EXTCLK]
+set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $EXTCLK] -rise_to [get_clocks $SWDCLK]
+
+### Multicycle path through asynchronous clock domains
+set_multicycle_path 2 -setup -end -from SWDCK -to CLK
+set_multicycle_path 1 -hold -end -from SWDCK -to CLK
+set_multicycle_path 2 -setup -end -from CLK -to SWDCK
+set_multicycle_path 1 -hold -end -from CLK -to SWDCK
+
+set_false_path -hold -from CLK -to SWDCK
+
+### Multicycle path through pads
+set_false_path -through uPAD_SWDIO_IO
+set_multicycle_path 2 -through uPAD_SWDIO_IO
+#set_false_path -through uPAD_P0_*
+#set_false_path -through uPAD_P1_*
+
+set_multicycle_path 2 -from uPAD_SWDIO_IO/I -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/IE -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/DS -to uPAD_SWDIO_IO/C
+set_multicycle_path 2 -from uPAD_SWDIO_IO/OEN -to uPAD_SWDIO_IO/C
+
+set_multicycle_path 2 -from uPAD_P0_*/I -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/IE -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/DS -to uPAD_P0_*/C
+set_multicycle_path 2 -from uPAD_P0_*/OEN -to uPAD_P0_*/C
+
+set_multicycle_path 2 -from uPAD_P1_*/I -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/IE -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/DS -to uPAD_P1_*/C
+set_multicycle_path 2 -from uPAD_P1_*/OEN -to uPAD_P1_*/C
+
+#### DELAY DEFINITION
+
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports NRST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports TEST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P0]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P1]
+set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.1 [get_ports SWDIO]
+
+set_max_capacitance 3 [all_outputs]
+set_max_fanout 10 [all_inputs]
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/FC_flow.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/FC_flow.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..660b9c5cf7a06c5f196e7053bd3e83c5e6a99b16
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/FC_flow.tcl
@@ -0,0 +1,24 @@
+# Main flow for Synopsys fusion compiler
+set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+# Design setup: read libraries and RTL
+redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
+
+# Floorplan setup
+redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1111.1111111 1111.11111} -core_offset {140}}
+redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
+
+# Read Constraints
+redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../../constraints.sdc}
+
+# Power Plan
+redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
+
+# Init coarse placement
+redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
+
+# Physical aware synthesis
+redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
+save_lib nanosoc_chip_pads.dlib
+redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/design_setup.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/design_setup.tcl
index 98a8de3e444b4f4870b95409f0263956d3f8cec3..c0c9dfa67b42f41b4fb1ab2246b1e1b3146ceac9 100644
--- a/ASIC/TSMC28nm/no_pins/Synopsys_FC/design_setup.tcl
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/design_setup.tcl
@@ -1,12 +1,30 @@
set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
+
+set TLU_cbest $TLU_dir/cbest.tluplus
+set TLU_cworst $TLU_dir/cworst.tluplus
+set TLU_rcbest $TLU_dir/rcbest.tluplus
+set TLU_rcworst $TLU_dir/rcworst.tluplus
+set TLU_map $TLU_dir/tluplus.map
+
create_lib nanosoc_chip_pads.dlib \
- -technology $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf \
- -ref_libs {./cln28ht_sc9mcpp140z/}
+ -technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf \
+ -ref_libs {./cln28ht/ ./sram_16k/ ./rom_via/}
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
-analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+analyze -format verilog $env(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
+analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_no_pads.v
elaborate nanosoc_chip_pads
-set_top_module nanosoc_chip_pads
\ No newline at end of file
+set_top_module nanosoc_chip_pads
+
+redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
+
+read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
+
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.def b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.def
new file mode 100644
index 0000000000000000000000000000000000000000..018405835fd51fbec4efe0fd73a585f6f6c44e95
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.def
@@ -0,0 +1,13 @@
+#
+# Fusion Compiler write_def
+# Release : U-2022.12
+# User Name : dwn1c21
+# Date : Thu Sep 12 11:29:50 2024
+#
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN nanosoc_chip_pads ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 0 1110700 ) ( 1111040 1110700 ) ( 1111040 0 ) ;
+END DESIGN
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8a9a7025a43fc644af0a7ead1392b5af8543d2d1
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.tcl
@@ -0,0 +1,51 @@
+################################################################################
+#
+# Created by fc write_floorplan on Thu Sep 12 11:29:50 2024
+#
+################################################################################
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+source ${_dirName__0}/fp.tcl
+
+if { [get_attribute -name view_name [current_block]] == "design" } {
+ set __fp_crnt_design_name__ [get_attribute -name design_name [current_block]]
+ set __fp_crnt_label_name__ [get_attribute -name label_name [current_block]]
+ set __fp_crnt_lib_name__ [get_attribute -name lib_name [current_block]]
+ set __fp_crnt_lib_path__ [get_attribute -name source_file_name [current_lib]]
+ set __fp_crnt_abs_name__ ${__fp_crnt_lib_name__}:${__fp_crnt_design_name__}
+ set __fp_crnt_abs_path__ ${__fp_crnt_lib_path__}/${__fp_crnt_design_name__}
+ if { [string length ${__fp_crnt_label_name__} ] != 0 } {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}/${__fp_crnt_label_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/design_label.${__fp_crnt_label_name__}/abs
+ } else {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/abs
+ }
+ if { [sizeof_collection [get_blocks -quiet ${__fp_crnt_abs_name__}]] != 0} {
+ if { [get_attribute -name has_editable_abstract [current_block]] } {
+ echo "Design [get_attribute -name full_name [current_block]] has editable abstract view. Re-creating the abstract view after floorplan loading..."
+ set __fp_crnt_abs_type__ [get_attribute -quiet -name abstract_view_type [current_block]]
+ if { [string length ${__fp_crnt_abs_type__} ] == 0 } {
+ if { [file exists "${__fp_crnt_abs_path__}/abs.mc"] } {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ } else {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ }
+ } elseif { ${__fp_crnt_abs_type__} == "placement" } {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ } else {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ }
+ }
+ }
+}
+
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan_compare_data.txt b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan_compare_data.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0c0d01e014a6da323cd8c069c7981fb9c176728b
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan_compare_data.txt
@@ -0,0 +1,55 @@
+################################################################################
+#
+# Created by fc compare_floorplans on Thu Sep 12 11:29:50 2024
+#
+# DO NOT EDIT - automatically generated file
+#
+################################################################################
+
+START nanosoc_chip_pads
+ MACROS
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {140.0000 944.1350} {235.0500 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {282.3200 781.1650} {454.5000 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {454.5000 781.1650} {626.6800 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {798.8600 781.1650} {971.0400 970.7000} }
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {626.6800 781.1650} {798.8600 970.7000} }
+ PINS
+ SE { {555.5200 555.3500} {555.5201 555.3501} }
+ CLK { {555.5200 555.3500} {555.5201 555.3501} }
+ TEST { {555.5200 555.3500} {555.5201 555.3501} }
+ NRST { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[15] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[14] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[13] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[12] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[11] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[10] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[9] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[8] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[7] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[6] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[5] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[4] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[3] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[2] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[1] { {555.5200 555.3500} {555.5201 555.3501} }
+ P0[0] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[15] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[14] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[13] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[12] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[11] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[10] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[9] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[8] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[7] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[6] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[5] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[4] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[3] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[2] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[1] { {555.5200 555.3500} {555.5201 555.3501} }
+ P1[0] { {555.5200 555.3500} {555.5201 555.3501} }
+ SWDIO { {555.5200 555.3500} {555.5201 555.3501} }
+ SWDCK { {555.5200 555.3500} {555.5201 555.3501} }
+END nanosoc_chip_pads
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/fp.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/fp.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6ee55ac7ec897c676880b08e3eafc573ba5f23bc
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/fp.tcl
@@ -0,0 +1,82 @@
+################################################################################
+#
+# Created by fc write_floorplan on Thu Sep 12 11:29:50 2024
+#
+################################################################################
+
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+################################################################################
+# Read DEF
+################################################################################
+
+read_def ${_dirName__0}/floorplan.def
+
+################################################################################
+# Macros
+################################################################################
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 235.0500 944.1350 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 454.5000 781.1650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 626.6800 781.1650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 781.1650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 781.1650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+
+################################################################################
+# User attributes of macros
+################################################################################
+
+
+################################################################################
+# I/O guides
+################################################################################
+
+remove_io_guides -all
+
+
+################################################################################
+# User attributes of I/O guides
+################################################################################
+
+
+################################################################################
+# User attributes of current block
+################################################################################
+
+
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/mapfile b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/mapfile
new file mode 100644
index 0000000000000000000000000000000000000000..1af7533494755299cc3dee06e1613fbfb52d4cb6
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/mapfile
@@ -0,0 +1 @@
+nanosoc_chip_pads FLOORPLAN fp.tcl
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/init_placement.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/init_placement.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e3f8a3213be9c8e0f3904ea1c37094b4b18052e9
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/init_placement.tcl
@@ -0,0 +1,10 @@
+set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
+set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
+set_temperature -40 -min 125 -corners default
+set_voltage 0.99 -min 0.81 -corners default
+
+redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
+
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
+explore_logic_hierarchy -place -rectangular
+save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/power_plan.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..407e63e1efc3bd7abbec1e5f5b8bab07c6034a2d
--- /dev/null
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/power_plan.tcl
@@ -0,0 +1,16 @@
+connect_pg_net -automatic
+
+create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
+ -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
+
+create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
+ {{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
+create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
+
+set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core
+set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core
+set_pg_strategy std_cell_strat -core -pattern {{name: std_pattern} {nets: {VDD VSS}}}
+
+compile_pg -strategies core_ring
+compile_pg -strategies M5M8_mesh
+compile_pg -strategies std_cell_strat
diff --git a/ASIC/TSMC28nm/no_pins/Synopsys_FC/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm/no_pins/Synopsys_FC/synopsys_lib_conversion.tcl
index 464cd56d59fbcd9aee90fcb3943e5791b9a1bd38..3e56c3f835bc2bdc672178fd35b59d7cbd23d199 100644
--- a/ASIC/TSMC28nm/no_pins/Synopsys_FC/synopsys_lib_conversion.tcl
+++ b/ASIC/TSMC28nm/no_pins/Synopsys_FC/synopsys_lib_conversion.tcl
@@ -1,27 +1,78 @@
-set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+# Technology files
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf
+set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.lef
-set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf
-set cln28ht_lef_file $cln28ht_tech_path/lef/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.lef
+# Standard Cell libraries
+set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+set sc9mcpp140z_lef_file $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
+set sc9mcpp140z_gds_file $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
+set sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
+set sc9mcpp140z_db_file_ff_0p99v_m40C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
-set sc9mcpp140z_lef_file $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
-set sc9mcpp140z_gds_file $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
-set sc9mcpp140z_db_file $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
-set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
+# SRAM files (using Arm compiler)
+set sram_16k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
+set sram_16k_lef_file $sram_16k_path/sram_16k.lef
+set sram_16k_gds_file $sram_16k_path/sram_16k.gds2
+set sram_16k_lib_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_16k_lib_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
+set sram_16k_lib_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
+set sram_16k_db_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_16k_db_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.db
+set sram_16k_db_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
-create_physical_lib -technology $cln28ht_tech_file cln28ht
-read_lef -library cln28ht $sc9mcpp140z_lef_file
-read_gds -library cln28ht $sc9mcpp140z_gds_file
-set_cell_site -site_def unit
-update_physical_properties -library cln28ht -format clf -file $sc9mcpp140z_antenna_file
+# ROM Files (using arm Compiler)
+set rom_path $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+set rom_via_lef_file $rom_path/rom_via.lef
+set rom_via_gds_file $rom_path/rom_via.gds2
+set rom_via_lib_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
+set rom_via_lib_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
+set rom_via_lib_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib
+set rom_via_db_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db
+set rom_via_db_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
+set rom_via_db_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
-update_physical_properties -library cln28ht -format db -file $sc9mcpp140z_db_file
-create_frame
+# Create standard cell fusion library
+create_fusion_lib -dbs [list $sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $sc9mcpp140z_lef_file] -technology $cln28ht_tech_file cln28ht
+save_fusion_lib cln28ht
-set_app_options -name
+close_fusion_lib cln28ht
-write_physical_lib -output cln28ht.ndm
-report_lib -all cln28ht
+# 16K SRAM
+read_lib $sram_16k_lib_file_ss_0p81v_125c
+write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
-set_check_library_options -logic_vs_physical -physical
-check_library -physical_library_name cln28ht -logic_library_name $sc9mcpp140z_db_file
\ No newline at end of file
+read_lib $sram_16k_lib_file_tt_0p90v_25c
+write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_85c
+close_lib -all
+
+read_lib $sram_16k_lib_file_ff_0p99v_m40c
+write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
+save_fusion_lib sram_16k
+close_fusion_lib sram_16k
+
+# Boot ROM
+read_lib $rom_via_lib_file_ss_0p81v_125c
+write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
+
+read_lib $rom_via_lib_file_tt_0p90v_25c
+write_lib -output $rom_via_db_file_tt_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
+
+read_lib $rom_via_lib_file_ff_0p99v_m40c
+write_lib -output $rom_via_db_file_ff_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $rom_via_db_file_ss_0p81v_125c $rom_via_db_file_tt_0p90v_25c $rom_via_db_file_ff_0p99v_m40c] -lefs $rom_via_lef_file -technology $cln28ht_tech_file rom_via
+save_fusion_lib rom_via
+close_fusion_lib rom_via
+
+
+exit
\ No newline at end of file
diff --git a/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v b/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
index 08ae5f440d81397c18295589b473482e446885ac..486b4acd71c1c4015ce3385d960bbc19eb930fb7 100644
--- a/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
+++ b/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
@@ -224,122 +224,101 @@ nanosoc_chip_cfg #(
// Pad IO power supplies
-PVDD2CDG uPAD_VDDIO_0(
+PVDD2DGZ_H_G uPAD_VDDIO_0(
.VDDPST(VDDIO)
);
-//PVDD2CDG uPAD_VDDIO_1(
-// .VDDPST(VDDIO)
-// );
-PVDD2CDG uPAD_VDDIO_2(
+PVDD2DGZ_H_G uPAD_VDDIO_2(
.VDDPST(VDDIO)
);
-PVDD2POC uPAD_VDDIO_3(
+PVDD2POC_H_G uPAD_VDDIO_3(
.VDDPST(VDDIO)
);
-PVSS2CDG uPAD_VSSIO_0(
+PVSS2DGZ_H_G uPAD_VSSIO_0(
.VSSPST(VSSIO)
);
-PVSS2CDG uPAD_VSSIO_1(
+PVSS2DGZ_H_G uPAD_VSSIO_1(
.VSSPST(VSSIO)
);
// Core power supplies
-PVDD1CDG uPAD_VDD_0(
+PVDD1DGZ_H_G uPAD_VDD_0(
.VDD(VDD)
);
-PVDD1CDG uPAD_VDD_1(
+PVDD1DGZ_V_G uPAD_VDD_1(
.VDD(VDD)
);
-PVDD1CDG uPAD_VDD_2(
+PVDD1DGZ_H_G uPAD_VDD_2(
.VDD(VDD)
);
-PVDD1CDG uPAD_VDD_3(
+PVDD1DGZ_V_G uPAD_VDD_3(
.VDD(VDD)
);
-PVSS1CDG uPAD_VSS_0(
+PVSS1DGZ_H_G uPAD_VSS_0(
.VSS(VSS)
);
-PVSS1CDG uPAD_VSS_1(
+PVSS1DGZ_V_G uPAD_VSS_1(
.VSS(VSS)
);
-PVSS1CDG uPAD_VSS_2(
+PVSS1DGZ_H_G uPAD_VSS_2(
.VSS(VSS)
);
-PVSS1CDG uPAD_VSS_3(
+PVSS1DGZ_V_G uPAD_VSS_3(
.VSS(VSS)
);
// Accelerator Power supplies
-PVDD1CDG uPAD_VDDACC_0(
+PVDD1DGZ_H_G uPAD_VDDACC_0(
.VDD(VDDACC)
);
-PVDD1CDG uPAD_VDDACC_1(
+PVDD1DGZ_V_G uPAD_VDDACC_1(
.VDD(VDDACC)
);
-PVDD1CDG uPAD_VDDACC_2(
+PVDD1DGZ_H_G uPAD_VDDACC_2(
.VDD(VDDACC)
);
// Clock, Reset and Serial Wire Debug ports
-PRDW0408SCDG uPAD_SE_I (
- .IE(tiehi),
+PRDW08SDGZ_V_G uPAD_SE_I (
.C(pad_se_i),
- .PE(tielo),
- .DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(SE)
);
-PRDW0408SCDG uPAD_CLK_I (
- .IE(tiehi),
+PRDW08SDGZ_V_G uPAD_CLK_I (
.C(pad_clk_i),
- .PE(tielo),
- .DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(CLK)
);
-PRDW0408SCDG uPAD_TEST_I (
- .IE(tiehi),
+PRDW08SDGZ_V_G uPAD_TEST_I (
.C(pad_test_i),
- .PE(tielo),
- .DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(TEST)
);
-PRDW0408SCDG uPAD_NRST_I (
- .IE(tiehi),
+PRDW08SDGZ_V_G uPAD_NRST_I (
.C(pad_nrst_i),
- .PE(tielo),
- .DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(NRST)
);
-PRDW0408SCDG uPAD_SWDIO_IO (
- .IE(pad_swdio_z),
+PRDW08SDGZ_V_G uPAD_SWDIO_IO (
.C(pad_swdio_i),
- .PE(tielo),
- .DS(tielo),
.I(pad_swdio_o),
.OEN(pad_swdio_z),
.PAD(SWDIO)
);
-PRDW0408SCDG uPAD_SWDCK_I (
- .IE(tiehi),
+PRDW08SDGZ_V_G uPAD_SWDCK_I (
.C(pad_swdclk_i),
- .PE(tielo),
- .DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(SWDCK)
@@ -347,162 +326,114 @@ PRDW0408SCDG uPAD_SWDCK_I (
// GPI.I Port 0 x 16
-PRDW0408SCDG uPAD_P0_00 (
- .IE(pad_gpio_port0_z[00]),
+PRDW08SDGZ_V_G uPAD_P0_00 (
.C(pad_gpio_port0_i[00]),
- .PE(pad_gpio_port0_z[00]&pad_gpio_port0_o[00]),
- .DS(tielo),
.I(pad_gpio_port0_o[00]),
.OEN(pad_gpio_port0_z[00]),
.PAD(P0[00])
);
-PRDW0408SCDG uPAD_P0_01 (
- .IE(pad_gpio_port0_z[01]),
+PRDW08SDGZ_V_G uPAD_P0_01 (
.C(pad_gpio_port0_i[01]),
- .PE(pad_gpio_port0_z[01]&pad_gpio_port0_o[01]),
- .DS(tielo),
.I(pad_gpio_port0_o[01]),
.OEN(pad_gpio_port0_z[01]),
.PAD(P0[01])
);
-PRDW0408SCDG uPAD_P0_02 (
- .IE(pad_gpio_port0_z[02]),
+PRDW08SDGZ_V_G uPAD_P0_02 (
.C(pad_gpio_port0_i[02]),
- .PE(pad_gpio_port0_z[02]&pad_gpio_port0_o[02]),
- .DS(tielo),
.I(pad_gpio_port0_o[02]),
.OEN(pad_gpio_port0_z[02]),
.PAD(P0[02])
);
-PRDW0408SCDG uPAD_P0_03 (
- .IE(pad_gpio_port0_z[03]),
+PRDW08SDGZ_V_G uPAD_P0_03 (
.C(pad_gpio_port0_i[03]),
- .PE(pad_gpio_port0_z[03]&pad_gpio_port0_o[03]),
- .DS(tielo),
.I(pad_gpio_port0_o[03]),
.OEN(pad_gpio_port0_z[03]),
.PAD(P0[03])
);
-PRDW0408SCDG uPAD_P0_04 (
- .IE(pad_gpio_port0_z[04]),
+PRDW08SDGZ_V_G uPAD_P0_04 (
.C(pad_gpio_port0_i[04]),
- .PE(pad_gpio_port0_z[04]&pad_gpio_port0_o[04]),
- .DS(tielo),
.I(pad_gpio_port0_o[04]),
.OEN(pad_gpio_port0_z[04]),
.PAD(P0[04])
);
-PRDW0408SCDG uPAD_P0_05 (
- .IE(pad_gpio_port0_z[05]),
+PRDW08SDGZ_V_G uPAD_P0_05 (
.C(pad_gpio_port0_i[05]),
- .PE(pad_gpio_port0_z[05]&pad_gpio_port0_o[05]),
- .DS(tielo),
.I(pad_gpio_port0_o[05]),
.OEN(pad_gpio_port0_z[05]),
.PAD(P0[05])
);
-PRDW0408SCDG uPAD_P0_06 (
- .IE(pad_gpio_port0_z[06]),
+PRDW08SDGZ_V_G uPAD_P0_06 (
.C(pad_gpio_port0_i[06]),
- .PE(pad_gpio_port0_z[06]&pad_gpio_port0_o[06]),
- .DS(tielo),
.I(pad_gpio_port0_o[06]),
.OEN(pad_gpio_port0_z[06]),
.PAD(P0[06])
);
-PRDW0408SCDG uPAD_P0_07 (
- .IE(pad_gpio_port0_z[07]),
+PRDW08SDGZ_V_G uPAD_P0_07 (
.C(pad_gpio_port0_i[07]),
- .PE(pad_gpio_port0_z[07]&pad_gpio_port0_o[07]),
- .DS(tielo),
.I(pad_gpio_port0_o[07]),
.OEN(pad_gpio_port0_z[07]),
.PAD(P0[07])
);
// GPI.I Port 1 x 16
-PRDW0408SCDG uPAD_P1_00 (
- .IE(pad_gpio_port1_z[00]),
+PRDW08SDGZ_V_G uPAD_P1_00 (
.C(pad_gpio_port1_i[00]),
- .PE(pad_gpio_port1_z[00]&pad_gpio_port1_o[00]),
- .DS(tielo),
.I(pad_gpio_port1_o[00]),
.OEN(pad_gpio_port1_z[00]),
.PAD(P1[00])
);
-PRDW0408SCDG uPAD_P1_01 (
- .IE(pad_gpio_port1_z[01]),
+PRDW08SDGZ_V_G uPAD_P1_01 (
.C(pad_gpio_port1_i[01]),
- .PE(pad_gpio_port1_z[01]&pad_gpio_port1_o[01]),
- .DS(tielo),
.I(pad_gpio_port1_o[01]),
.OEN(pad_gpio_port1_z[01]),
.PAD(P1[01])
);
-PRDW0408SCDG uPAD_P1_02 (
- .IE(pad_gpio_port1_z[02]),
+PRDW08SDGZ_V_G uPAD_P1_02 (
.C(pad_gpio_port1_i[02]),
- .PE(pad_gpio_port1_z[02]&pad_gpio_port1_o[02]),
- .DS(tielo),
.I(pad_gpio_port1_o[02]),
.OEN(pad_gpio_port1_z[02]),
.PAD(P1[02])
);
-PRDW0408SCDG uPAD_P1_03 (
- .IE(pad_gpio_port1_z[03]),
+PRDW08SDGZ_V_G uPAD_P1_03 (
.C(pad_gpio_port1_i[03]),
- .PE(pad_gpio_port1_z[03]&pad_gpio_port1_o[03]),
- .DS(tielo),
.I(pad_gpio_port1_o[03]),
.OEN(pad_gpio_port1_z[03]),
.PAD(P1[03])
);
-PRDW0408SCDG uPAD_P1_04 (
- .IE(pad_gpio_port1_z[04]),
+PRDW08SDGZ_V_G uPAD_P1_04 (
.C(pad_gpio_port1_i[04]),
- .PE(pad_gpio_port1_z[04]&pad_gpio_port1_o[04]),
- .DS(tielo),
.I(pad_gpio_port1_o[04]),
.OEN(pad_gpio_port1_z[04]),
.PAD(P1[04])
);
-PRDW0408SCDG uPAD_P1_05 (
- .IE(pad_gpio_port1_z[05]),
+PRDW08SDGZ_V_G uPAD_P1_05 (
.C(pad_gpio_port1_i[05]),
- .PE(pad_gpio_port1_z[05]&pad_gpio_port1_o[05]),
- .DS(tielo),
.I(pad_gpio_port1_o[05]),
.OEN(pad_gpio_port1_z[05]),
.PAD(P1[05])
);
-PRDW0408SCDG uPAD_P1_06 (
- .IE(pad_gpio_port1_z[06]),
+PRDW08SDGZ_V_G uPAD_P1_06 (
.C(pad_gpio_port1_i[06]),
- .PE(pad_gpio_port1_z[06]&pad_gpio_port1_o[06]),
- .DS(tielo),
.I(pad_gpio_port1_o[06]),
.OEN(pad_gpio_port1_z[06]),
.PAD(P1[06])
);
-PRDW0408SCDG uPAD_P1_07 (
- .IE(pad_gpio_port1_z[07]),
+PRDW08SDGZ_V_G uPAD_P1_07 (
.C(pad_gpio_port1_i[07]),
- .PE(pad_gpio_port1_z[07]&pad_gpio_port1_o[07]),
- .DS(tielo),
.I(pad_gpio_port1_o[07]),
.OEN(pad_gpio_port1_z[07]),
.PAD(P1[07])
diff --git a/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_no_pads.v b/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_no_pads.v
new file mode 100644
index 0000000000000000000000000000000000000000..f7d856e5f73a239d117e6ddf79638b5c2c8ad2fa
--- /dev/null
+++ b/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_no_pads.v
@@ -0,0 +1,527 @@
+//-----------------------------------------------------------------------------
+// customised top-level Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+
+module nanosoc_chip_pads (
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+ inout wire VDDACC,
+`endif
+ input wire SE,
+ inout wire CLK, // input
+ inout wire TEST, // output
+ inout wire NRST, // active low reset
+ inout wire [15:0] P0,
+ inout wire [15:0] P1,
+ inout wire SWDIO,
+ inout wire SWDCK);
+
+
+//------------------------------------
+// internal wires
+
+localparam GPIO_TIO = 4;
+
+wire pad_clk_i;
+wire pad_nrst_i;
+wire pad_test_i;
+wire pad_swdclk_i;
+wire pad_swdio_i;
+wire pad_swdio_o;
+wire pad_swdio_e;
+wire pad_swdio_z;
+wire [15:0] pad_gpio_port0_i ;
+wire [15:0] pad_gpio_port0_o ;
+wire [15:0] pad_gpio_port0_e ;
+wire [15:0] pad_gpio_port0_z ;
+wire [15:0] pad_gpio_port1_i ;
+wire [15:0] pad_gpio_port1_o ;
+wire [15:0] pad_gpio_port1_e ;
+wire [15:0] pad_gpio_port1_z ;
+wire soc_nreset;
+wire soc_diag_mode;
+wire soc_diag_ctrl;
+wire soc_scan_mode;
+wire soc_scan_enable;
+wire [GPIO_TIO-1:0] soc_scan_in; //soc test status outputs
+wire [GPIO_TIO-1:0] soc_scan_out; //soc test status outputs
+wire soc_bist_mode;
+wire soc_bist_enable;
+wire [GPIO_TIO-1:0] soc_bist_in; //soc test status outputs
+wire [GPIO_TIO-1:0] soc_bist_out; //soc test status outputs
+wire soc_alt_mode; // ALT MODE = UART
+wire soc_uart_rxd_i; // UART RXD
+wire soc_uart_txd_o; // UART TXD
+wire soc_swd_mode; // SWD mode
+wire soc_swd_clk_i; // SWDCLK
+wire soc_swd_dio_i; // SWDIO tristate input
+wire soc_swd_dio_o; // SWDIO trstate output
+wire soc_swd_dio_e; // SWDIO tristate output enable
+wire soc_swd_dio_z; // SWDIO tristate output hiz
+wire [15:0] soc_gpio_port0_i; // GPIO SOC tristate input
+wire [15:0] soc_gpio_port0_o; // GPIO SOC trstate output
+wire [15:0] soc_gpio_port0_e; // GPIO SOC tristate output enable
+wire [15:0] soc_gpio_port0_z; // GPIO SOC tristate output hiz
+wire [15:0] soc_gpio_port1_i; // GPIO SOC tristate input
+wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
+wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
+wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
+
+wire pad_se_i;
+
+
+// connect up high order GPIOs
+assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
+assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
+assign pad_gpio_port0_e[15:GPIO_TIO] = soc_gpio_port0_e[15:GPIO_TIO];
+assign pad_gpio_port0_z[15:GPIO_TIO] = soc_gpio_port0_z[15:GPIO_TIO];
+assign soc_gpio_port1_i[15:GPIO_TIO] = pad_gpio_port1_i[15:GPIO_TIO];
+assign pad_gpio_port1_o[15:GPIO_TIO] = soc_gpio_port1_o[15:GPIO_TIO];
+assign pad_gpio_port1_e[15:GPIO_TIO] = soc_gpio_port1_e[15:GPIO_TIO];
+assign pad_gpio_port1_z[15:GPIO_TIO] = soc_gpio_port1_z[15:GPIO_TIO];
+
+wire tiehi = 1'b1;
+wire tielo = 1'b0;
+
+nanosoc_chip_cfg #(
+ .GPIO_TIO (GPIO_TIO)
+ )
+ u_nanosoc_chip_cfg
+ (
+ // Primary Inputs
+ .pad_clk_i (pad_clk_i )
+ ,.pad_nrst_i (pad_nrst_i )
+ ,.pad_test_i (pad_test_i )
+ // Alternate/reconfigurable IP and associated bidirectional I/O
+ ,.pad_altin_i (pad_se_i ) // SWCLK/UARTRXD/SCAN-ENABLE
+ ,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
+ ,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
+ ,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
+ ,.pad_altio_z (pad_swdio_z ) // SWDIO/UARTTXD tristate output hiz
+ // Reconfigurable General Purpose bidirectional I/Os Port-0 (user)
+ ,.pad_gpio_port0_i (pad_gpio_port0_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
+ ,.pad_gpio_port0_o (pad_gpio_port0_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
+ ,.pad_gpio_port0_e (pad_gpio_port0_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
+ ,.pad_gpio_port0_z (pad_gpio_port0_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
+ // Reconfigurable General Purpose bidirectional I/Os Port-1 (system)
+ ,.pad_gpio_port1_i (pad_gpio_port1_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
+ ,.pad_gpio_port1_o (pad_gpio_port1_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
+ ,.pad_gpio_port1_e (pad_gpio_port1_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
+ ,.pad_gpio_port1_z (pad_gpio_port1_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
+ //SOC
+ ,.soc_nreset (soc_nreset )
+ ,.soc_diag_mode (soc_diag_mode )
+ ,.soc_diag_ctrl (soc_diag_ctrl )
+ ,.soc_scan_mode (soc_scan_mode )
+ ,.soc_scan_enable (soc_scan_enable )
+ ,.soc_scan_in (soc_scan_in ) // soc test scan chain inputs
+ ,.soc_scan_out (soc_scan_out ) // soc test scan chain outputs
+ ,.soc_bist_mode (soc_bist_mode )
+ ,.soc_bist_enable (soc_bist_enable )
+ ,.soc_bist_in (soc_bist_in ) // soc bist control inputs
+ ,.soc_bist_out (soc_bist_out ) // soc test status outputs
+ ,.soc_alt_mode (soc_alt_mode )// ALT MODE = UART
+ ,.soc_uart_rxd_i (soc_uart_rxd_i ) // UART RXD
+ ,.soc_uart_txd_o (soc_uart_txd_o ) // UART TXD
+ ,.soc_swd_mode (soc_swd_mode ) // SWD mode
+ ,.soc_swd_clk_i (soc_swd_clk_i ) // SWDCLK
+ ,.soc_swd_dio_i (soc_swd_dio_i ) // SWDIO tristate input
+ ,.soc_swd_dio_o (soc_swd_dio_o ) // SWDIO trstate output
+ ,.soc_swd_dio_e (soc_swd_dio_e ) // SWDIO tristate output enable
+ ,.soc_swd_dio_z (soc_swd_dio_z ) // SWDIO tristate output hiz
+ ,.soc_gpio_port0_i (soc_gpio_port0_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
+ ,.soc_gpio_port0_o (soc_gpio_port0_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
+ ,.soc_gpio_port0_e (soc_gpio_port0_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
+ ,.soc_gpio_port0_z (soc_gpio_port0_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
+ ,.soc_gpio_port1_i (soc_gpio_port1_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
+ ,.soc_gpio_port1_o (soc_gpio_port1_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
+ ,.soc_gpio_port1_e (soc_gpio_port1_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
+ ,.soc_gpio_port1_z (soc_gpio_port1_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
+);
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0 nanosoc Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip u_nanosoc_chip (
+`ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ .VDDACC (VDDACC),
+`endif
+//`ifdef ASIC_TEST_PORTS
+ .diag_mode (soc_diag_mode ),
+ .diag_ctrl (soc_diag_ctrl ),
+ .scan_mode (soc_scan_mode ),
+ .scan_enable (soc_scan_enable ),
+ .scan_in (soc_scan_in ), // soc test scan chain inputs
+ .scan_out (soc_scan_out ), // soc test scan chain outputs
+ .bist_mode (soc_bist_mode ),
+ .bist_enable (soc_bist_enable ),
+ .bist_in (soc_bist_in ), // soc bist control inputs
+ .bist_out (soc_bist_out ), // soc test status outputs
+ .alt_mode (soc_alt_mode ),// ALT MODE = UART
+ .uart_rxd_i (soc_uart_rxd_i ), // UART RXD
+ .uart_txd_o (soc_uart_txd_o ), // UART TXD
+ .swd_mode (soc_swd_mode ), // SWD mode
+//`endif
+ .clk_i (pad_clk_i),
+ .test_i (soc_scan_mode), //(test_i),
+ .nrst_i (soc_nreset), //(nrst_i),
+ .p0_i (soc_gpio_port0_i), // level-shifted input from pad
+ .p0_o (soc_gpio_port0_o), // output port drive
+ .p0_e (soc_gpio_port0_e), // active high output drive enable (pad tech dependent)
+ .p0_z (soc_gpio_port0_z), // active low output drive enable (pad tech dependent)
+ .p1_i (soc_gpio_port1_i), // level-shifted input from pad
+ .p1_o (soc_gpio_port1_o), // output port drive
+ .p1_e (soc_gpio_port1_e), // active high output drive enable (pad tech dependent)
+ .p1_z (soc_gpio_port1_z), // active low output drive enable (pad tech dependent)
+ .swdio_i (soc_swd_dio_i),
+ .swdio_o (soc_swd_dio_o),
+ .swdio_e (soc_swd_dio_e),
+ .swdio_z (soc_swd_dio_z),
+ .swdclk_i (pad_swdclk_i)
+ );
+
+
+ // --------------------------------------------------------------------------------
+ // IO pad (GLIB Generic Library napping)
+ // --------------------------------------------------------------------------------
+
+`ifdef POWER_PINS
+// Pad IO power supplies
+
+PAD_VDDIO uPAD_VDDIO_1(
+ .PAD(VDDIO)
+ );
+
+PAD_VSSIO uPAD_VSSIO_1(
+ .PAD(VSSIO)
+ );
+
+// Core power supplies
+
+PAD_VDDSOC uPAD_VDD_1(
+ .PAD(VDD)
+ );
+
+PAD_VSS uPAD_VSS_1(
+ .PAD(VSS)
+ );
+
+// Accelerator Power supplies
+PAD_VDDSOC uPAD_VDDACC_1(
+ .PAD(VDDACC)
+ );
+`endif
+
+// Clock, Reset and Serial Wire Debug ports
+
+PAD_INOUT8MA_NOE uPAD_SE_I (
+ .PAD (SE),
+ .O (tielo),
+ .I (pad_se_i),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_CLK_I (
+ .PAD (CLK),
+ .O (tielo),
+ .I (pad_clk_i),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_XTAL_I (
+ .PAD (TEST),
+ .O (tielo),
+ .I (pad_test_i),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_NRST_I (
+ .PAD (NRST),
+ .O (tielo),
+ .I (pad_nrst_i),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_SWDIO_IO (
+ .PAD (SWDIO),
+ .O (pad_swdio_o),
+ .I (pad_swdio_i),
+ .NOE (pad_swdio_z)
+ );
+
+PAD_INOUT8MA_NOE uPAD_SWDCK_I (
+ .PAD (SWDCK),
+ .O (tielo),
+ .I (pad_swdclk_i),
+ .NOE (tiehi)
+ );
+
+// GPI.I Port 0 x 16
+
+PAD_INOUT8MA_NOE uPAD_P0_00 (
+ .PAD (P0[00]),
+ .O (pad_gpio_port0_o[00]),
+ .I (pad_gpio_port0_i[00]),
+ .NOE (pad_gpio_port0_z[00])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_01 (
+ .PAD (P0[01]),
+ .O (pad_gpio_port0_o[01]),
+ .I (pad_gpio_port0_i[01]),
+ .NOE (pad_gpio_port0_z[01])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_02 (
+ .PAD (P0[02]),
+ .O (pad_gpio_port0_o[02]),
+ .I (pad_gpio_port0_i[02]),
+ .NOE (pad_gpio_port0_z[02])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_03 (
+ .PAD (P0[03]),
+ .O (pad_gpio_port0_o[03]),
+ .I (pad_gpio_port0_i[03]),
+ .NOE (pad_gpio_port0_z[03])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_04 (
+ .PAD (P0[04]),
+ .O (pad_gpio_port0_o[04]),
+ .I (pad_gpio_port0_i[04]),
+ .NOE (pad_gpio_port0_z[04])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_05 (
+ .PAD (P0[05]),
+ .O (pad_gpio_port0_o[05]),
+ .I (pad_gpio_port0_i[05]),
+ .NOE (pad_gpio_port0_z[05])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_06 (
+ .PAD (P0[06]),
+ .O (pad_gpio_port0_o[06]),
+ .I (pad_gpio_port0_i[06]),
+ .NOE (pad_gpio_port0_z[06])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_07 (
+ .PAD (P0[07]),
+ .O (pad_gpio_port0_o[07]),
+ .I (pad_gpio_port0_i[07]),
+ .NOE (pad_gpio_port0_z[07])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_08 (
+ .PAD (P0[08]),
+ .O (pad_gpio_port0_o[08]),
+ .I (pad_gpio_port0_i[08]),
+ .NOE (pad_gpio_port0_z[08])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_09 (
+ .PAD (P0[09]),
+ .O (pad_gpio_port0_o[09]),
+ .I (pad_gpio_port0_i[09]),
+ .NOE (pad_gpio_port0_z[09])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_10 (
+ .PAD (P0[10]),
+ .O (pad_gpio_port0_o[10]),
+ .I (pad_gpio_port0_i[10]),
+ .NOE (pad_gpio_port0_z[10])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_11 (
+ .PAD (P0[11]),
+ .O (pad_gpio_port0_o[11]),
+ .I (pad_gpio_port0_i[11]),
+ .NOE (pad_gpio_port0_z[11])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_12 (
+ .PAD (P0[12]),
+ .O (pad_gpio_port0_o[12]),
+ .I (pad_gpio_port0_i[12]),
+ .NOE (pad_gpio_port0_z[12])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_13 (
+ .PAD (P0[13]),
+ .O (pad_gpio_port0_o[13]),
+ .I (pad_gpio_port0_i[13]),
+ .NOE (pad_gpio_port0_z[13])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_14 (
+ .PAD (P0[14]),
+ .O (pad_gpio_port0_o[14]),
+ .I (pad_gpio_port0_i[14]),
+ .NOE (pad_gpio_port0_z[14])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_15 (
+ .PAD (P0[15]),
+ .O (pad_gpio_port0_o[15]),
+ .I (pad_gpio_port0_i[15]),
+ .NOE (pad_gpio_port0_z[15])
+ );
+
+// GPI.I Port 1 x 16
+
+PAD_INOUT8MA_NOE uPAD_P1_00 (
+ .PAD (P1[00]),
+ .O (pad_gpio_port1_o[00]),
+ .I (pad_gpio_port1_i[00]),
+ .NOE (pad_gpio_port1_z[00])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_01 (
+ .PAD (P1[01]),
+ .O (pad_gpio_port1_o[01]),
+ .I (pad_gpio_port1_i[01]),
+ .NOE (pad_gpio_port1_z[01])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_02 (
+ .PAD (P1[02]),
+ .O (pad_gpio_port1_o[02]),
+ .I (pad_gpio_port1_i[02]),
+ .NOE (pad_gpio_port1_z[02])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_03 (
+ .PAD (P1[03]),
+ .O (pad_gpio_port1_o[03]),
+ .I (pad_gpio_port1_i[03]),
+ .NOE (pad_gpio_port1_z[03])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_04 (
+ .PAD (P1[04]),
+ .O (pad_gpio_port1_o[04]),
+ .I (pad_gpio_port1_i[04]),
+ .NOE (pad_gpio_port1_z[04])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_05 (
+ .PAD (P1[05]),
+ .O (pad_gpio_port1_o[05]),
+ .I (pad_gpio_port1_i[05]),
+ .NOE (pad_gpio_port1_z[05])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_06 (
+ .PAD (P1[06]),
+ .O (pad_gpio_port1_o[06]),
+ .I (pad_gpio_port1_i[06]),
+ .NOE (pad_gpio_port1_z[06])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_07 (
+ .PAD (P1[07]),
+ .O (pad_gpio_port1_o[07]),
+ .I (pad_gpio_port1_i[07]),
+ .NOE (pad_gpio_port1_z[07])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_08 (
+ .PAD (P1[08]),
+ .O (pad_gpio_port1_o[08]),
+ .I (pad_gpio_port1_i[08]),
+ .NOE (pad_gpio_port1_z[08])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_09 (
+ .PAD (P1[09]),
+ .O (pad_gpio_port1_o[09]),
+ .I (pad_gpio_port1_i[09]),
+ .NOE (pad_gpio_port1_z[09])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_10 (
+ .PAD (P1[10]),
+ .O (pad_gpio_port1_o[10]),
+ .I (pad_gpio_port1_i[10]),
+ .NOE (pad_gpio_port1_z[10])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_11 (
+ .PAD (P1[11]),
+ .O (pad_gpio_port1_o[11]),
+ .I (pad_gpio_port1_i[11]),
+ .NOE (pad_gpio_port1_z[11])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_12 (
+ .PAD (P1[12]),
+ .O (pad_gpio_port1_o[12]),
+ .I (pad_gpio_port1_i[12]),
+ .NOE (pad_gpio_port1_z[12])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_13 (
+ .PAD (P1[13]),
+ .O (pad_gpio_port1_o[13]),
+ .I (pad_gpio_port1_i[13]),
+ .NOE (pad_gpio_port1_z[13])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_14 (
+ .PAD (P1[14]),
+ .O (pad_gpio_port1_o[14]),
+ .I (pad_gpio_port1_i[14]),
+ .NOE (pad_gpio_port1_z[14])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_15 (
+ .PAD (P1[15]),
+ .O (pad_gpio_port1_o[15]),
+ .I (pad_gpio_port1_i[15]),
+ .NOE (pad_gpio_port1_z[15])
+ );
+
+endmodule
diff --git a/flist/nanosoc_ASIC.flist b/flist/nanosoc_ASIC.flist
index 1fe143c29dd81106062ff6b6381193db8f6b98fe..cdfddfdd04a1d65f9781f0ce923cb83df438ad44 100644
--- a/flist/nanosoc_ASIC.flist
+++ b/flist/nanosoc_ASIC.flist
@@ -22,6 +22,10 @@
// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
+
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist