diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index bfb454a014dade7c9a99db5efc2eda89e3baab17..52a38a35683ea332a6af5cb430d80bf445ae54d8 100644
--- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -27,7 +27,7 @@ file mkdir $outputDir
 # local search path for configurations
 set search_path ../verilog
 
-set cortexm0_vlog    ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical
+set cortexm0_vlog    ../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical
 source scripts/rtl_source_cm0.tcl
 
 set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
@@ -35,7 +35,7 @@ read_verilog  [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
 read_verilog  [ glob $cortexm0_vlog/models/cells/*.v ]
 
 # Arm unmodified CMSDK RTL
-set cmsdk_vlog    ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+set cmsdk_vlog    ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
 source scripts/rtl_source_cmsdk.tcl
 
 set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
@@ -47,7 +47,7 @@ read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
 
 # configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
 set search_path [ concat $search_path ../verilog ]
-set dma230_vlog    ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+set dma230_vlog    ../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
 source scripts/rtl_source_dma230.tcl
 
 # ADP, FT1248 and streamio IP