From 48919e6951c7420cee6343957ecd1f68270138ff Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 5 Dec 2023 17:20:44 +0000
Subject: [PATCH] Add 3rd channel to dma350
---
ASIC/44pin/Cadence/scripts/place_macros.tcl | 1 -
ASIC/44pin/Cadence/scripts/power_plan.tcl | 13 +++---
.../exp/verilog/nanosoc_region_exp.v | 34 ++++++++++++--
.../dma/verilog/nanosoc_ss_dma.v | 30 ++++++++++++-
.../expansion/verilog/nanosoc_ss_expansion.v | 30 +++++++++++++
.../nanosoc_system/verilog/nanosoc_system.v | 45 +++++++++++++++++++
nanosoc/sldma350_tech | 2 +-
7 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/ASIC/44pin/Cadence/scripts/place_macros.tcl b/ASIC/44pin/Cadence/scripts/place_macros.tcl
index e2f219b..b115c38 100644
--- a/ASIC/44pin/Cadence/scripts/place_macros.tcl
+++ b/ASIC/44pin/Cadence/scripts/place_macros.tcl
@@ -26,4 +26,3 @@ create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
-0
\ No newline at end of file
diff --git a/ASIC/44pin/Cadence/scripts/power_plan.tcl b/ASIC/44pin/Cadence/scripts/power_plan.tcl
index 5895c39..8e16398 100644
--- a/ASIC/44pin/Cadence/scripts/power_plan.tcl
+++ b/ASIC/44pin/Cadence/scripts/power_plan.tcl
@@ -16,7 +16,7 @@ set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1
### Adding Rings
-add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 8 bottom 8 left 8 right 8} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 3 bottom 3 left 3 right 3} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 1 bottom 1 left 1 right 1} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
### Adding Stripes
set_db add_stripes_ignore_block_check true
@@ -25,8 +25,7 @@ set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
set_db add_stripes_extend_to_closest_target none
set_db add_stripes_stop_at_last_wire_for_area false
-set_db add_stripes_partial_set_through_domain true
-set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_ignore_non_default_domains true
set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
@@ -49,7 +48,7 @@ set_db add_stripes_ignore_block_check true
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
-set_db add_stripes_extend_to_closest_target stripe
+set_db add_stripes_extend_to_closest_target {ring stripe}
set_db add_stripes_stop_at_last_wire_for_area false
set_db add_stripes_partial_set_through_domain true
set_db add_stripes_ignore_non_default_domains false
@@ -65,17 +64,17 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
-add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 50 -over_power_domain 1 -start_from bottom -start_offset 15 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
# connect Macros
-select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
+select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
set_db add_stripes_ignore_block_check false
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
-set_db add_stripes_extend_to_closest_target stripe
+set_db add_stripes_extend_to_closest_target {ring stripe}
add_stripes -nets {VDD VSS} -layer M5 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 8 -stop_offset 0 -switch_layer_over_obs false -merge_stripes_value 500 -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
diff --git a/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v b/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
index 36b27aa..4ac6751 100644
--- a/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+++ b/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
@@ -59,6 +59,21 @@ module nanosoc_region_exp #(
output wire EXP_STR_OUT_1_TLAST,
input wire EXP_STR_OUT_1_FLUSH,
`endif
+`ifdef DMA350_STREAM_3
+
+ input wire EXP_STR_IN_2_TVALID,
+ output wire EXP_STR_IN_2_TREADY,
+ input wire [SYS_DATA_W-1:0] EXP_STR_IN_2_TDATA,
+ input wire [3:0] EXP_STR_IN_2_TSTRB,
+ input wire EXP_STR_IN_2_TLAST,
+
+ output wire EXP_STR_OUT_2_TVALID,
+ input wire EXP_STR_OUT_2_TREADY,
+ output wire [SYS_DATA_W-1:0] EXP_STR_OUT_2_TDATA,
+ output wire [3:0] EXP_STR_OUT_2_TSTRB,
+ output wire EXP_STR_OUT_2_TLAST,
+ input wire EXP_STR_OUT_2_FLUSH,
+`endif
`endif
// Interrupt and DMAC Connections
@@ -114,6 +129,21 @@ module nanosoc_region_exp #(
.EXP_STR_OUT_1_TLAST(EXP_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_FLUSH(EXP_STR_OUT_1_FLUSH),
`endif
+`ifdef DMA350_STREAM_3
+
+ .EXP_STR_IN_2_TVALID(EXP_STR_IN_2_TVALID),
+ .EXP_STR_IN_2_TREADY(EXP_STR_IN_2_TREADY),
+ .EXP_STR_IN_2_TDATA(EXP_STR_IN_2_TDATA),
+ .EXP_STR_IN_2_TSTRB(EXP_STR_IN_2_TSTRB),
+ .EXP_STR_IN_2_TLAST(EXP_STR_IN_2_TLAST),
+
+ .EXP_STR_OUT_2_TVALID(EXP_STR_OUT_2_TVALID),
+ .EXP_STR_OUT_2_TREADY(EXP_STR_OUT_2_TREADY),
+ .EXP_STR_OUT_2_TDATA(EXP_STR_OUT_2_TDATA),
+ .EXP_STR_OUT_2_TSTRB(EXP_STR_OUT_2_TSTRB),
+ .EXP_STR_OUT_2_TLAST(EXP_STR_OUT_2_TLAST),
+ .EXP_STR_OUT_2_FLUSH(EXP_STR_OUT_2_FLUSH),
+`endif
`endif
.EXP_IRQ(EXP_IRQ),
@@ -132,9 +162,7 @@ module nanosoc_region_exp #(
.HRESP (HRESP)
);
- assign EXP_STR_IN_0_TREADY = 1'b1;
- assign EXP_STR_IN_1_TREADY = 1'b1;
-
+
assign HRDATA = 32'heaedeaed; // Tie off Expansion Address Expansion Data
assign EXP_IRQ = 4'd0;
assign EXP_DRQ = 2'd0;
diff --git a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
index e9b4b27..4b7aa7f 100644
--- a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+++ b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -109,6 +109,22 @@ module nanosoc_ss_dma #(
input wire DMAC_STR_IN_1_TLAST,
output wire DMAC_STR_IN_1_FLUSH,
`endif
+`ifdef DMA350_STREAM_3
+// DMAC Channel 1 AXI Stream out
+ output wire DMAC_STR_OUT_2_TVALID,
+ input wire DMAC_STR_OUT_2_TREADY,
+ output wire [SYS_DATA_W-1:0] DMAC_STR_OUT_2_TDATA,
+ output wire [4-1:0] DMAC_STR_OUT_2_TSTRB,
+ output wire DMAC_STR_OUT_2_TLAST,
+
+ // DMAC Channel 1 AXI Stream out
+ input wire DMAC_STR_IN_2_TVALID,
+ output wire DMAC_STR_IN_2_TREADY,
+ input wire [SYS_DATA_W-1:0] DMAC_STR_IN_2_TDATA,
+ input wire [4-1:0] DMAC_STR_IN_2_TSTRB,
+ input wire DMAC_STR_IN_2_TLAST,
+ output wire DMAC_STR_IN_2_FLUSH,
+`endif
`endif
// DMAC 1 DMA Request and Status Port
@@ -200,7 +216,19 @@ module nanosoc_ss_dma #(
.DMAC_STR_IN_1_TLAST(DMAC_STR_IN_1_TLAST),
.DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH),
`endif
-
+`ifdef DMA350_STREAM_3
+ .DMAC_STR_OUT_2_TVALID(DMAC_STR_OUT_2_TVALID),
+ .DMAC_STR_OUT_2_TREADY(DMAC_STR_OUT_2_TREADY),
+ .DMAC_STR_OUT_2_TDATA(DMAC_STR_OUT_2_TDATA),
+ .DMAC_STR_OUT_2_TSTRB(DMAC_STR_OUT_2_TSTRB),
+ .DMAC_STR_OUT_2_TLAST(DMAC_STR_OUT_2_TLAST),
+ .DMAC_STR_IN_2_TVALID(DMAC_STR_IN_2_TVALID),
+ .DMAC_STR_IN_2_TREADY(DMAC_STR_IN_2_TREADY),
+ .DMAC_STR_IN_2_TDATA(DMAC_STR_IN_2_TDATA),
+ .DMAC_STR_IN_2_TSTRB(DMAC_STR_IN_2_TSTRB),
+ .DMAC_STR_IN_2_TLAST(DMAC_STR_IN_2_TLAST),
+ .DMAC_STR_IN_2_FLUSH(DMAC_STR_IN_2_FLUSH),
+`endif
.DMA_REQ(DMAC_0_DMA_REQ),
.DMA_DONE(DMAC_0_DMA_DONE),
.DMA_ERR(DMAC_0_DMA_ERR)
diff --git a/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v b/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
index 8e30b0f..9537771 100644
--- a/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+++ b/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
@@ -72,6 +72,21 @@ module nanosoc_ss_expansion #(
output wire EXP_STR_OUT_1_TLAST,
input wire EXP_STR_OUT_1_FLUSH,
`endif
+`ifdef DMA350_STREAM_3
+
+ input wire EXP_STR_IN_2_TVALID,
+ output wire EXP_STR_IN_2_TREADY,
+ input wire [SYS_DATA_W-1:0] EXP_STR_IN_2_TDATA,
+ input wire [3:0] EXP_STR_IN_2_TSTRB,
+ input wire EXP_STR_IN_2_TLAST,
+
+ output wire EXP_STR_OUT_2_TVALID,
+ input wire EXP_STR_OUT_2_TREADY,
+ output wire [SYS_DATA_W-1:0] EXP_STR_OUT_2_TDATA,
+ output wire [3:0] EXP_STR_OUT_2_TSTRB,
+ output wire EXP_STR_OUT_2_TLAST,
+ input wire EXP_STR_OUT_2_FLUSH,
+`endif
`endif
// SRAM Low Region AHB Port
@@ -161,6 +176,21 @@ module nanosoc_ss_expansion #(
.EXP_STR_OUT_1_TLAST(EXP_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_FLUSH(EXP_STR_OUT_1_FLUSH),
`endif
+`ifdef DMA350_STREAM_3
+
+ .EXP_STR_IN_2_TVALID(EXP_STR_IN_2_TVALID),
+ .EXP_STR_IN_2_TREADY(EXP_STR_IN_2_TREADY),
+ .EXP_STR_IN_2_TDATA(EXP_STR_IN_2_TDATA),
+ .EXP_STR_IN_2_TSTRB(EXP_STR_IN_2_TSTRB),
+ .EXP_STR_IN_2_TLAST(EXP_STR_IN_2_TLAST),
+
+ .EXP_STR_OUT_2_TVALID(EXP_STR_OUT_2_TVALID),
+ .EXP_STR_OUT_2_TREADY(EXP_STR_OUT_2_TREADY),
+ .EXP_STR_OUT_2_TDATA(EXP_STR_OUT_2_TDATA),
+ .EXP_STR_OUT_2_TSTRB(EXP_STR_OUT_2_TSTRB),
+ .EXP_STR_OUT_2_TLAST(EXP_STR_OUT_2_TLAST),
+ .EXP_STR_OUT_2_FLUSH(EXP_STR_OUT_2_FLUSH),
+`endif
`endif
// Interrupt and DMAC Connections
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index 47a49c6..d45e5bf 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -475,6 +475,21 @@ module nanosoc_system #(
wire DMAC_STR_IN_1_TLAST;
wire DMAC_STR_IN_1_FLUSH;
`endif
+`ifdef DMA350_STREAM_3
+// DMAC Channel 2 AXI Stream out
+ wire DMAC_STR_OUT_2_TVALID;
+ wire DMAC_STR_OUT_2_TREADY;
+ wire [SYS_DATA_W-1:0] DMAC_STR_OUT_2_TDATA;
+ wire [4-1:0] DMAC_STR_OUT_2_TSTRB;
+ wire DMAC_STR_OUT_2_TLAST;
+// DMAC Channel 2 AXI Stream out
+ wire DMAC_STR_IN_2_TVALID;
+ wire DMAC_STR_IN_2_TREADY;
+ wire [SYS_DATA_W-1:0] DMAC_STR_IN_2_TDATA;
+ wire [4-1:0] DMAC_STR_IN_2_TSTRB;
+ wire DMAC_STR_IN_2_TLAST;
+ wire DMAC_STR_IN_2_FLUSH;
+`endif
`endif
// Instantiate Subsystem
@@ -577,6 +592,21 @@ module nanosoc_system #(
.DMAC_STR_IN_1_TLAST(DMAC_STR_IN_1_TLAST),
.DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH),
`endif
+`ifdef DMA350_STREAM_3
+
+ .DMAC_STR_OUT_2_TVALID(DMAC_STR_OUT_2_TVALID),
+ .DMAC_STR_OUT_2_TREADY(DMAC_STR_OUT_2_TREADY),
+ .DMAC_STR_OUT_2_TDATA(DMAC_STR_OUT_2_TDATA),
+ .DMAC_STR_OUT_2_TSTRB(DMAC_STR_OUT_2_TSTRB),
+ .DMAC_STR_OUT_2_TLAST(DMAC_STR_OUT_2_TLAST),
+
+ .DMAC_STR_IN_2_TVALID(DMAC_STR_IN_2_TVALID),
+ .DMAC_STR_IN_2_TREADY(DMAC_STR_IN_2_TREADY),
+ .DMAC_STR_IN_2_TDATA(DMAC_STR_IN_2_TDATA),
+ .DMAC_STR_IN_2_TSTRB(DMAC_STR_IN_2_TSTRB),
+ .DMAC_STR_IN_2_TLAST(DMAC_STR_IN_2_TLAST),
+ .DMAC_STR_IN_2_FLUSH(DMAC_STR_IN_2_FLUSH),
+`endif
`endif
// DMAC 1 DMA Request and Status Port
@@ -815,6 +845,21 @@ module nanosoc_system #(
.EXP_STR_OUT_1_TLAST(DMAC_STR_IN_1_TLAST),
.EXP_STR_OUT_1_FLUSH(DMAC_STR_IN_1_FLUSH),
`endif
+`ifdef DMA350_STREAM_2
+
+ .EXP_STR_IN_2_TVALID(DMAC_STR_OUT_2_TVALID),
+ .EXP_STR_IN_2_TREADY(DMAC_STR_OUT_2_TREADY),
+ .EXP_STR_IN_2_TDATA(DMAC_STR_OUT_2_TDATA),
+ .EXP_STR_IN_2_TSTRB(DMAC_STR_OUT_2_TSTRB),
+ .EXP_STR_IN_2_TLAST(DMAC_STR_OUT_2_TLAST),
+
+ .EXP_STR_OUT_2_TVALID(DMAC_STR_IN_2_TVALID),
+ .EXP_STR_OUT_2_TREADY(DMAC_STR_IN_2_TREADY),
+ .EXP_STR_OUT_2_TDATA(DMAC_STR_IN_2_TDATA),
+ .EXP_STR_OUT_2_TSTRB(DMAC_STR_IN_2_TSTRB),
+ .EXP_STR_OUT_2_TLAST(DMAC_STR_IN_2_TLAST),
+ .EXP_STR_OUT_2_FLUSH(DMAC_STR_IN_2_FLUSH),
+`endif
`endif
diff --git a/nanosoc/sldma350_tech b/nanosoc/sldma350_tech
index 40601e4..d3a9db1 160000
--- a/nanosoc/sldma350_tech
+++ b/nanosoc/sldma350_tech
@@ -1 +1 @@
-Subproject commit 40601e44099d064d254b8ec53877682cc586b3ac
+Subproject commit d3a9db1014315bda22e9025b24fc9cda7b064a10
--
GitLab