From 45aebae98f1a1a8b2d87a4e4ac4c9aec1e1350c4 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 19 Sep 2023 12:10:24 +0100
Subject: [PATCH] Syn 12 track and upd mem and power place
---
synthesis/ICC2/icc_shell.tcl | 15 ++++++++++-----
synthesis/ICC2/place_memories.tcl | 10 +++++-----
synthesis/ICC2/power_plan.tcl | 6 +++---
synthesis/genus.tcl | 2 +-
4 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/synthesis/ICC2/icc_shell.tcl b/synthesis/ICC2/icc_shell.tcl
index f510717..4ee7785 100644
--- a/synthesis/ICC2/icc_shell.tcl
+++ b/synthesis/ICC2/icc_shell.tcl
@@ -11,11 +11,11 @@
set design_name nanosoc_chip_pads
-set PHYS_IP_DIR /home/dwn1c21/SoC-Labs/phys_ip
+set PHYS_IP_DIR /research/AAA/phys_ip_library
-set_app_var link_library $PHYS_IP_DIR/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
-create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc9_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef]
+set_app_var link_library $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
+create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc12_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef]
read_parasitic_tech -name typical -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
@@ -35,15 +35,20 @@ commit_upf
set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
current_corner default
-set_operating_conditions -max_library sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
+set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
current_corner default
set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
current_corner default
-set_operating_conditions -max_library sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
+set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
current_mode default
set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD]
set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO]
+set_app_options -list {opt.timing.effort {medium}}
+set_app_options -list {clock_opt.place.effort {high}}
+set_app_options -list {place_opt.flow.clock_aware_placement {true}}
+set_app_options -list {place_opt.final_place.effort {high}}
+set_app_options -list {clock_opt.hold.effort {ultra}}
set_app_options -list {opt.dft.optimize_scan_chain {false}}
set_app_options -list {opt.dft.do_repartition {false}}
set_app_options -list {place.coarse.continue_on_missing_scandef {true}}
diff --git a/synthesis/ICC2/place_memories.tcl b/synthesis/ICC2/place_memories.tcl
index 3a81003..89b6830 100644
--- a/synthesis/ICC2/place_memories.tcl
+++ b/synthesis/ICC2/place_memories.tcl
@@ -1,8 +1,8 @@
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset -0.2 -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner tl -anchor_corner tl -offset {0.2 -0.2} -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner br -anchor_corner br -offset {-0.2 0.3} -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner bl -anchor_corner bl -offset {0.2 0.3} -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom}] -target_orientation R0 -target_corner bl -anchor_corner bl -offset {0.4 0.15} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.1} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.3} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.5} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.7} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom}] -target_orientation R270 -target_corner br -anchor_corner br -offset {-0.1 0.4} -offset_type scalable
create_macro_relative_location_placement
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
diff --git a/synthesis/ICC2/power_plan.tcl b/synthesis/ICC2/power_plan.tcl
index f83d4ad..a1e3f5b 100644
--- a/synthesis/ICC2/power_plan.tcl
+++ b/synthesis/ICC2/power_plan.tcl
@@ -3,9 +3,9 @@ create_pg_ring_patter ring_pattern -horizontal_layer M7 -horizontal_width {5} -h
set_pg_strategy core_ring -pattern {{name:ring_pattern} {nets: {VDD VDDIO VSS VSSIO}}{offset: {3 3}}} -core
create_pg_mesh_pattern strap_pattern -layers {{{vertical_layer: M4} {width: 1} {pitch: 50} {spacing: interleaving} {trim: false}}}
-set_pg_strategy M4_straps -core -pattern {{name: strap_pattern}{nets: VDD VSS}}
+set_pg_strategy M4_straps -voltage_areas DEFAULT_VA -pattern {{name: strap_pattern}{nets: VDD VSS}} -blockage {{{macros_with_keepout : {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}}}} -extension {{{stop : outermost_ring}}}
create_pg_std_cell_conn_pattern rail_pattern -layers M1
-set_pg_strategy M1_rails -core -pattern {{name: rail_pattern}{nets: VDD VSS}}
+set_pg_strategy M1_rails -voltage_areas DEFAULT_VA -pattern {{name: rail_pattern}{nets: VDD VSS}} -blockage {{{macros_with_keepout : {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}}}} -extension {{{stop : outermost_ring}}}
-compile_pg -strategies {M4_straps M1_rails core_ring}
+compile_pg -strategies {core_ring M4_straps M1_rails}
diff --git a/synthesis/genus.tcl b/synthesis/genus.tcl
index bc18590..103274b 100644
--- a/synthesis/genus.tcl
+++ b/synthesis/genus.tcl
@@ -1,5 +1,5 @@
set_db init_lib_search_path ./
-set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
set RF_LIB $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.lib
set ROM_LIB $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.lib
set_db / .library "$BASE_LIB $RF_LIB $ROM_LIB"
--
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