From 44dbf9ea55b5a944dace4e4a525c95dbca540c3d Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Mon, 3 Jul 2023 16:25:25 +0100
Subject: [PATCH] MPS3 fpga build wrapper
---
.../CI_verification/run_AES_verification.py | 142 ++
.../component.xml | 13 +-
.../ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl | 86 +
.../uart_to_AXI_master_1.0/component.xml | 1707 +++++++++++++++++
.../hdl/uart_to_AXI_master_v1_0.v | 125 ++
.../hdl/uart_to_AXI_master_v1_0_M00_AXI.v | 907 +++++++++
.../uart_to_AXI_master_1.0/src/dbg_bridge.v | 623 ++++++
.../src/dbg_bridge_fifo.v | 118 ++
.../src/dbg_bridge_uart.v | 341 ++++
.../xgui/uart_to_AXI_master_v1_0.tcl | 190 ++
fpga_imp/scripts/build_mcu_fpga_arm_mps3.tcl | 20 +-
fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl | 9 +-
.../scripts/build_mcu_fpga_pynq_zcu104.tcl | 26 +-
fpga_imp/target_fpga_arm_mps3/design_1.tcl | 214 ++-
.../target_fpga_arm_mps3/design_1_wrapper.v | 371 +++-
15 files changed, 4774 insertions(+), 118 deletions(-)
create mode 100644 fpga_imp/CI_verification/run_AES_verification.py
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
create mode 100644 fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
diff --git a/fpga_imp/CI_verification/run_AES_verification.py b/fpga_imp/CI_verification/run_AES_verification.py
new file mode 100644
index 0000000..dd5c8ce
--- /dev/null
+++ b/fpga_imp/CI_verification/run_AES_verification.py
@@ -0,0 +1,142 @@
+
+from pynq.overlays.base import BaseOverlay
+overlay = BaseOverlay("base.bit")
+import os, warnings
+from pynq import PL
+from pynq import Overlay
+
+ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit")
+
+if not os.path.exists(PL.bitfile_name):
+ warnings.warn('There is no overlay loaded after boot.', UserWarning)
+
+ol = Overlay(PL.bitfile_name)
+ol.download()
+ol.timestamp
+## 2. Examining the overlay
+print(PL.bitfile_name)
+print(PL.timestamp)
+
+#PL.ip_dict
+### Interrogate the HWH database for interface addresses
+ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']
+print("ADPIO stream interface: ",hex(ADP_address))
+UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']
+print("UART(2) interface: ",hex(UART2_address))
+### Set up interface functions for ADP
+from pynq import Overlay
+from pynq import MMIO
+import time
+from time import sleep, time
+
+# HARDWARE CONSTANTS
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+# Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+
+# Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class ADPIO:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address, 0x10000, debug=False)
+ self.address = address
+
+ def setupCtrlReg(self):
+# # Reset FIFOs, disable interrupts
+# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)
+# sleep(1)
+ self.uart.write(CTRL_REG, 0)
+ sleep(1)
+
+ def monitorModeEnter(self):
+ self.uart.write(TX_FIFO, 0x1b)
+
+ def monitorModeExit(self):
+ self.uart.write(TX_FIFO, 0x04)
+
+ def wbyte(self, b, timeout=1):
+ # Write bytes via UART
+ while (self.uart.read(STAT_REG) & 1 << TX_FULL):
+ pass
+ self.uart.write_reg(TX_FIFO,int(b))
+ return
+
+ def read(self, count, timeout=1):
+ # status = currentStatus(uart) bad idea
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, stop waiting if timeoutpasses
+ while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):
+ pass
+ if time() >= stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout=1):
+ # Write bytes via UART
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ # Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):
+ pass
+ # Check timeout
+ if time() > stop_time:
+ wr_count = -1
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+
+adp = ADPIO(ADP_address)
+# Setup AXI UART register
+adp.setupCtrlReg()
+print(adp.read(100))
+### Enter ADP monitor mode ('ESC' char)
+adp.monitorModeEnter()
+print(adp.read(4))
+uart = ADPIO(UART2_address)
+# Setup AXI UART register
+uart.setupCtrlReg()
+uart.read(50)
+adp.monitorModeEnter()
+print(adp.read(4))
+import os
+file_name= "arm_tests/aes128_tests.bin"
+file_stats= os.stat(file_name)
+file_len_in_bytes = file_stats.st_size
+print(f'file size in bytes is {file_len_in_bytes}')
+bytecount_hex=hex(file_len_in_bytes)
+print(f'file size in bytes is {bytecount_hex}')
+print(f'U '+bytecount_hex+'\n')
+adp.write('A 0x20000000\n')
+adp.write('U '+bytecount_hex+'\n')
+count = file_len_in_bytes
+print(count)
+with open(file_name, mode='rb') as file:
+ while (count>0) :
+ b=file.read(1)
+ adp.wbyte(ord(b))
+ count-=1
+print(count)
+print(adp.read(100))
+adp.write('A 0x20000000\n')
+adp.write('R 40\n')
+print(adp.read(10000))
+adp.write('C 0x200\n')
+adp.write('C 0x201\n')
+print(adp.read(10000))
diff --git a/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml b/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
index e23a30e..796d46a 100644
--- a/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
+++ b/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
@@ -488,13 +488,15 @@
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">kintexu</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">kintex7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>ft1248x1_to_axi_streamio_v1.0</xilinx:displayName>
- <xilinx:coreRevision>8</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2023-02-26T14:27:06Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>9</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2023-06-01T10:11:18Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.df@428bf478_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@77d2a63f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
@@ -615,6 +617,13 @@
<xilinx:tag xilinx:name="ui.data.coregen.df@13049cbf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2c4fe533_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@19907224_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@23d3f1b7_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@22807dd0_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2fc76256_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7a60836b_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@74c04a33_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@e41b2f9_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6be6a0c9_ARCHIVE_LOCATION">/home/dwn1c21/SoC-Labs/nanosoc_tech/system/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl
new file mode 100644
index 0000000..4804aeb
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml
new file mode 100644
index 0000000..173a620
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml
@@ -0,0 +1,1707 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>user.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>uart_to_AXI_master</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="M00_AXI"/>
+ </spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWLEN</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awlen</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awsize</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awburst</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awlock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWCACHE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awcache</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWQOS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awqos</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awuser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wlast</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wuser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_buser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARID</spirit:name>
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+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
new file mode 100644
index 0000000..8baf1d3
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
@@ -0,0 +1,125 @@
+
+`timescale 1 ns / 1 ps
+
+ module uart_to_AXI_master_v1_0 #
+ (
+ // Users to add parameters here
+ parameter integer CLK_SPEED = 10000000,
+ parameter integer UART_BAUD_RATE = 115200,
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Master Bus Interface M00_AXI
+ parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
+ parameter integer C_M00_AXI_BURST_LEN = 16,
+ parameter integer C_M00_AXI_ID_WIDTH = 4,
+ parameter integer C_M00_AXI_ADDR_WIDTH = 32,
+ parameter integer C_M00_AXI_DATA_WIDTH = 32,
+ parameter integer C_M00_AXI_AWUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_ARUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_WUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_RUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_BUSER_WIDTH = 4
+ )
+ (
+ // Users to add ports her
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Master Bus Interface M00_AXI
+ input wire UART_RX,
+ output wire UART_TX,
+ input wire m00_axi_aclk,
+ input wire m00_axi_aresetn,
+ output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
+ output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
+ output wire [7 : 0] m00_axi_awlen,
+ output wire [2 : 0] m00_axi_awsize,
+ output wire [1 : 0] m00_axi_awburst,
+ output wire m00_axi_awlock,
+ output wire [3 : 0] m00_axi_awcache,
+ output wire [2 : 0] m00_axi_awprot,
+ output wire [3 : 0] m00_axi_awqos,
+ output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
+ output wire m00_axi_awvalid,
+ input wire m00_axi_awready,
+ output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
+ output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
+ output wire m00_axi_wlast,
+ output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
+ output wire m00_axi_wvalid,
+ input wire m00_axi_wready,
+ input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
+ input wire [1 : 0] m00_axi_bresp,
+ input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
+ input wire m00_axi_bvalid,
+ output wire m00_axi_bready,
+ output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
+ output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
+ output wire [7 : 0] m00_axi_arlen,
+ output wire [2 : 0] m00_axi_arsize,
+ output wire [1 : 0] m00_axi_arburst,
+ output wire m00_axi_arlock,
+ output wire [3 : 0] m00_axi_arcache,
+ output wire [2 : 0] m00_axi_arprot,
+ output wire [3 : 0] m00_axi_arqos,
+ output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
+ output wire m00_axi_arvalid,
+ input wire m00_axi_arready,
+ input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
+ input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
+ input wire [1 : 0] m00_axi_rresp,
+ input wire m00_axi_rlast,
+ input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
+ input wire m00_axi_rvalid,
+ output wire m00_axi_rready
+ );
+// Instantiation of Axi Bus Interface M00_AXI
+
+ // Add user logic here
+ dbg_bridge #(.CLK_FREQ(CLK_SPEED),
+ .UART_SPEED(UART_BAUD_RATE),
+ .AXI_ID(4'd0),
+ .GPIO_ADDRESS(32'hf0000000),
+ .STS_ADDRESS(32'hf0000004))
+ dbg_bridge_inst (
+ .clk_i (m00_axi_aclk),
+ .rst_i (~m00_axi_aresetn),
+ .uart_rxd_i (UART_RX),
+ .uart_txd_o (UART_TX),
+ .gpio_inputs_i (),
+ .gpio_outputs_o (),
+ .mem_awready_i (m00_axi_awready),
+ .mem_wready_i (m00_axi_wready),
+ .mem_bvalid_i (m00_axi_bvalid),
+ .mem_bresp_i (m00_axi_bresp),
+ .mem_bid_i (m00_axi_bid),
+ .mem_arready_i (m00_axi_arready),
+ .mem_rvalid_i (m00_axi_rvalid),
+ .mem_rdata_i (m00_axi_rdata),
+ .mem_rresp_i (m00_axi_rresp),
+ .mem_rid_i (m00_axi_rid),
+ .mem_rlast_i (m00_axi_rlast),
+ .mem_awvalid_o (m00_axi_awvalid),
+ .mem_awaddr_o (m00_axi_awaddr),
+ .mem_awid_o (m00_axi_awid),
+ .mem_awlen_o (m00_axi_awlen),
+ .mem_awburst_o (m00_axi_awburst),
+ .mem_wvalid_o (m00_axi_wvalid),
+ .mem_wdata_o (m00_axi_wdata),
+ .mem_wstrb_o (m00_axi_wstrb),
+ .mem_wlast_o (m00_axi_wlast),
+ .mem_bready_o (m00_axi_bready),
+ .mem_arvalid_o (m00_axi_arvalid),
+ .mem_araddr_o (m00_axi_araddr),
+ .mem_arid_o (m00_axi_arid),
+ .mem_arlen_o (m00_axi_arlen),
+ .mem_arburst_o (m00_axi_arburst),
+ .mem_rready_o (m00_axi_rready)
+ );
+ // User logic ends
+
+ endmodule
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
new file mode 100644
index 0000000..ac7d455
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
@@ -0,0 +1,907 @@
+
+`timescale 1 ns / 1 ps
+
+ module uart_to_AXI_master_v1_0_M00_AXI #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Base address of targeted slave
+ parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
+ // Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
+ parameter integer C_M_AXI_BURST_LEN = 16,
+ // Thread ID Width
+ parameter integer C_M_AXI_ID_WIDTH = 1,
+ // Width of Address Bus
+ parameter integer C_M_AXI_ADDR_WIDTH = 32,
+ // Width of Data Bus
+ parameter integer C_M_AXI_DATA_WIDTH = 32,
+ // Width of User Write Address Bus
+ parameter integer C_M_AXI_AWUSER_WIDTH = 0,
+ // Width of User Read Address Bus
+ parameter integer C_M_AXI_ARUSER_WIDTH = 0,
+ // Width of User Write Data Bus
+ parameter integer C_M_AXI_WUSER_WIDTH = 0,
+ // Width of User Read Data Bus
+ parameter integer C_M_AXI_RUSER_WIDTH = 0,
+ // Width of User Response Bus
+ parameter integer C_M_AXI_BUSER_WIDTH = 0
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Initiate AXI transactions
+ input wire INIT_AXI_TXN,
+ // Asserts when transaction is complete
+ output wire TXN_DONE,
+ // Asserts when ERROR is detected
+ output reg ERROR,
+ // Global Clock Signal.
+ input wire M_AXI_ACLK,
+ // Global Reset Singal. This Signal is Active Low
+ input wire M_AXI_ARESETN,
+ // Master Interface Write Address ID
+ output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
+ // Master Interface Write Address
+ output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
+ // Burst length. The burst length gives the exact number of transfers in a burst
+ output wire [7 : 0] M_AXI_AWLEN,
+ // Burst size. This signal indicates the size of each transfer in the burst
+ output wire [2 : 0] M_AXI_AWSIZE,
+ // Burst type. The burst type and the size information,
+ // determine how the address for each transfer within the burst is calculated.
+ output wire [1 : 0] M_AXI_AWBURST,
+ // Lock type. Provides additional information about the
+ // atomic characteristics of the transfer.
+ output wire M_AXI_AWLOCK,
+ // Memory type. This signal indicates how transactions
+ // are required to progress through a system.
+ output wire [3 : 0] M_AXI_AWCACHE,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ output wire [2 : 0] M_AXI_AWPROT,
+ // Quality of Service, QoS identifier sent for each write transaction.
+ output wire [3 : 0] M_AXI_AWQOS,
+ // Optional User-defined signal in the write address channel.
+ output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
+ // Write address valid. This signal indicates that
+ // the channel is signaling valid write address and control information.
+ output wire M_AXI_AWVALID,
+ // Write address ready. This signal indicates that
+ // the slave is ready to accept an address and associated control signals
+ input wire M_AXI_AWREADY,
+ // Master Interface Write Data.
+ output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
+ // Write strobes. This signal indicates which byte
+ // lanes hold valid data. There is one write strobe
+ // bit for each eight bits of the write data bus.
+ output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
+ // Write last. This signal indicates the last transfer in a write burst.
+ output wire M_AXI_WLAST,
+ // Optional User-defined signal in the write data channel.
+ output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available
+ output wire M_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ input wire M_AXI_WREADY,
+ // Master Interface Write Response.
+ input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
+ // Write response. This signal indicates the status of the write transaction.
+ input wire [1 : 0] M_AXI_BRESP,
+ // Optional User-defined signal in the write response channel
+ input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
+ // Write response valid. This signal indicates that the
+ // channel is signaling a valid write response.
+ input wire M_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ output wire M_AXI_BREADY,
+ // Master Interface Read Address.
+ output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
+ // Read address. This signal indicates the initial
+ // address of a read burst transaction.
+ output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
+ // Burst length. The burst length gives the exact number of transfers in a burst
+ output wire [7 : 0] M_AXI_ARLEN,
+ // Burst size. This signal indicates the size of each transfer in the burst
+ output wire [2 : 0] M_AXI_ARSIZE,
+ // Burst type. The burst type and the size information,
+ // determine how the address for each transfer within the burst is calculated.
+ output wire [1 : 0] M_AXI_ARBURST,
+ // Lock type. Provides additional information about the
+ // atomic characteristics of the transfer.
+ output wire M_AXI_ARLOCK,
+ // Memory type. This signal indicates how transactions
+ // are required to progress through a system.
+ output wire [3 : 0] M_AXI_ARCACHE,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ output wire [2 : 0] M_AXI_ARPROT,
+ // Quality of Service, QoS identifier sent for each read transaction
+ output wire [3 : 0] M_AXI_ARQOS,
+ // Optional User-defined signal in the read address channel.
+ output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
+ // Write address valid. This signal indicates that
+ // the channel is signaling valid read address and control information
+ output wire M_AXI_ARVALID,
+ // Read address ready. This signal indicates that
+ // the slave is ready to accept an address and associated control signals
+ input wire M_AXI_ARREADY,
+ // Read ID tag. This signal is the identification tag
+ // for the read data group of signals generated by the slave.
+ input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
+ // Master Read Data
+ input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
+ // Read response. This signal indicates the status of the read transfer
+ input wire [1 : 0] M_AXI_RRESP,
+ // Read last. This signal indicates the last transfer in a read burst
+ input wire M_AXI_RLAST,
+ // Optional User-defined signal in the read address channel.
+ input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
+ // Read valid. This signal indicates that the channel
+ // is signaling the required read data.
+ input wire M_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ output wire M_AXI_RREADY
+ );
+
+
+ // function called clogb2 that returns an integer which has the
+ //value of the ceiling of the log base 2
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // C_TRANSACTIONS_NUM is the width of the index counter for
+ // number of write or read transaction.
+ localparam integer C_TRANSACTIONS_NUM = clogb2(C_M_AXI_BURST_LEN-1);
+
+ // Burst length for transactions, in C_M_AXI_DATA_WIDTHs.
+ // Non-2^n lengths will eventually cause bursts across 4K address boundaries.
+ localparam integer C_MASTER_LENGTH = 12;
+ // total number of burst transfers is master length divided by burst length and burst size
+ localparam integer C_NO_BURSTS_REQ = C_MASTER_LENGTH-clogb2((C_M_AXI_BURST_LEN*C_M_AXI_DATA_WIDTH/8)-1);
+ // Example State machine to initialize counter, initialize write transactions,
+ // initialize read transactions and comparison of read data with the
+ // written data words.
+ parameter [1:0] IDLE = 2'b00, // This state initiates AXI4Lite transaction
+ // after the state machine changes state to INIT_WRITE
+ // when there is 0 to 1 transition on INIT_AXI_TXN
+ INIT_WRITE = 2'b01, // This state initializes write transaction,
+ // once writes are done, the state machine
+ // changes state to INIT_READ
+ INIT_READ = 2'b10, // This state initializes read transaction
+ // once reads are done, the state machine
+ // changes state to INIT_COMPARE
+ INIT_COMPARE = 2'b11; // This state issues the status of comparison
+ // of the written data with the read data
+
+ reg [1:0] mst_exec_state;
+
+ // AXI4LITE signals
+ //AXI4 internal temp signals
+ reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awvalid;
+ reg [C_M_AXI_DATA_WIDTH-1 : 0] axi_wdata;
+ reg axi_wlast;
+ reg axi_wvalid;
+ reg axi_bready;
+ reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arvalid;
+ reg axi_rready;
+ //write beat count in a burst
+ reg [C_TRANSACTIONS_NUM : 0] write_index;
+ //read beat count in a burst
+ reg [C_TRANSACTIONS_NUM : 0] read_index;
+ //size of C_M_AXI_BURST_LEN length burst in bytes
+ wire [C_TRANSACTIONS_NUM+2 : 0] burst_size_bytes;
+ //The burst counters are used to track the number of burst transfers of C_M_AXI_BURST_LEN burst length needed to transfer 2^C_MASTER_LENGTH bytes of data.
+ reg [C_NO_BURSTS_REQ : 0] write_burst_counter;
+ reg [C_NO_BURSTS_REQ : 0] read_burst_counter;
+ reg start_single_burst_write;
+ reg start_single_burst_read;
+ reg writes_done;
+ reg reads_done;
+ reg error_reg;
+ reg compare_done;
+ reg read_mismatch;
+ reg burst_write_active;
+ reg burst_read_active;
+ reg [C_M_AXI_DATA_WIDTH-1 : 0] expected_rdata;
+ //Interface response error flags
+ wire write_resp_error;
+ wire read_resp_error;
+ wire wnext;
+ wire rnext;
+ reg init_txn_ff;
+ reg init_txn_ff2;
+ reg init_txn_edge;
+ wire init_txn_pulse;
+
+
+ // I/O Connections assignments
+
+ //I/O Connections. Write Address (AW)
+ assign M_AXI_AWID = 'b0;
+ //The AXI address is a concatenation of the target base address + active offset range
+ assign M_AXI_AWADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;
+ //Burst LENgth is number of transaction beats, minus 1
+ assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1;
+ //Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
+ assign M_AXI_AWSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
+ //INCR burst type is usually used, except for keyhole bursts
+ assign M_AXI_AWBURST = 2'b01;
+ assign M_AXI_AWLOCK = 1'b0;
+ //Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
+ assign M_AXI_AWCACHE = 4'b0010;
+ assign M_AXI_AWPROT = 3'h0;
+ assign M_AXI_AWQOS = 4'h0;
+ assign M_AXI_AWUSER = 'b1;
+ assign M_AXI_AWVALID = axi_awvalid;
+ //Write Data(W)
+ assign M_AXI_WDATA = axi_wdata;
+ //All bursts are complete and aligned in this example
+ assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}};
+ assign M_AXI_WLAST = axi_wlast;
+ assign M_AXI_WUSER = 'b0;
+ assign M_AXI_WVALID = axi_wvalid;
+ //Write Response (B)
+ assign M_AXI_BREADY = axi_bready;
+ //Read Address (AR)
+ assign M_AXI_ARID = 'b0;
+ assign M_AXI_ARADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_araddr;
+ //Burst LENgth is number of transaction beats, minus 1
+ assign M_AXI_ARLEN = C_M_AXI_BURST_LEN - 1;
+ //Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
+ assign M_AXI_ARSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
+ //INCR burst type is usually used, except for keyhole bursts
+ assign M_AXI_ARBURST = 2'b01;
+ assign M_AXI_ARLOCK = 1'b0;
+ //Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
+ assign M_AXI_ARCACHE = 4'b0010;
+ assign M_AXI_ARPROT = 3'h0;
+ assign M_AXI_ARQOS = 4'h0;
+ assign M_AXI_ARUSER = 'b1;
+ assign M_AXI_ARVALID = axi_arvalid;
+ //Read and Read Response (R)
+ assign M_AXI_RREADY = axi_rready;
+ //Example design I/O
+ assign TXN_DONE = compare_done;
+ //Burst size in bytes
+ assign burst_size_bytes = C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8;
+ assign init_txn_pulse = (!init_txn_ff2) && init_txn_ff;
+
+
+ //Generate a pulse to initiate AXI transaction.
+ always @(posedge M_AXI_ACLK)
+ begin
+ // Initiates AXI transaction delay
+ if (M_AXI_ARESETN == 0 )
+ begin
+ init_txn_ff <= 1'b0;
+ init_txn_ff2 <= 1'b0;
+ end
+ else
+ begin
+ init_txn_ff <= INIT_AXI_TXN;
+ init_txn_ff2 <= init_txn_ff;
+ end
+ end
+
+
+ //--------------------
+ //Write Address Channel
+ //--------------------
+
+ // The purpose of the write address channel is to request the address and
+ // command information for the entire transaction. It is a single beat
+ // of information.
+
+ // The AXI4 Write address channel in this example will continue to initiate
+ // write commands as fast as it is allowed by the slave/interconnect.
+ // The address will be incremented on each accepted address transaction,
+ // by burst_size_byte to point to the next address.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_awvalid <= 1'b0;
+ end
+ // If previously not valid , start next transaction
+ else if (~axi_awvalid && start_single_burst_write)
+ begin
+ axi_awvalid <= 1'b1;
+ end
+ /* Once asserted, VALIDs cannot be deasserted, so axi_awvalid
+ must wait until transaction is accepted */
+ else if (M_AXI_AWREADY && axi_awvalid)
+ begin
+ axi_awvalid <= 1'b0;
+ end
+ else
+ axi_awvalid <= axi_awvalid;
+ end
+
+
+ // Next address after AWREADY indicates previous address acceptance
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ axi_awaddr <= 'b0;
+ end
+ else if (M_AXI_AWREADY && axi_awvalid)
+ begin
+ axi_awaddr <= axi_awaddr + burst_size_bytes;
+ end
+ else
+ axi_awaddr <= axi_awaddr;
+ end
+
+
+ //--------------------
+ //Write Data Channel
+ //--------------------
+
+ //The write data will continually try to push write data across the interface.
+
+ //The amount of data accepted will depend on the AXI slave and the AXI
+ //Interconnect settings, such as if there are FIFOs enabled in interconnect.
+
+ //Note that there is no explicit timing relationship to the write address channel.
+ //The write channel has its own throttling flag, separate from the AW channel.
+
+ //Synchronization between the channels must be determined by the user.
+
+ //The simpliest but lowest performance would be to only issue one address write
+ //and write data burst at a time.
+
+ //In this example they are kept in sync by using the same address increment
+ //and burst sizes. Then the AW and W channels have their transactions measured
+ //with threshold counters as part of the user logic, to make sure neither
+ //channel gets too far ahead of each other.
+
+ //Forward movement occurs when the write channel is valid and ready
+
+ assign wnext = M_AXI_WREADY & axi_wvalid;
+
+ // WVALID logic, similar to the axi_awvalid always block above
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_wvalid <= 1'b0;
+ end
+ // If previously not valid, start next transaction
+ else if (~axi_wvalid && start_single_burst_write)
+ begin
+ axi_wvalid <= 1'b1;
+ end
+ /* If WREADY and too many writes, throttle WVALID
+ Once asserted, VALIDs cannot be deasserted, so WVALID
+ must wait until burst is complete with WLAST */
+ else if (wnext && axi_wlast)
+ axi_wvalid <= 1'b0;
+ else
+ axi_wvalid <= axi_wvalid;
+ end
+
+
+ //WLAST generation on the MSB of a counter underflow
+ // WVALID logic, similar to the axi_awvalid always block above
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_wlast <= 1'b0;
+ end
+ // axi_wlast is asserted when the write index
+ // count reaches the penultimate count to synchronize
+ // with the last write data when write_index is b1111
+ // else if (&(write_index[C_TRANSACTIONS_NUM-1:1])&& ~write_index[0] && wnext)
+ else if (((write_index == C_M_AXI_BURST_LEN-2 && C_M_AXI_BURST_LEN >= 2) && wnext) || (C_M_AXI_BURST_LEN == 1 ))
+ begin
+ axi_wlast <= 1'b1;
+ end
+ // Deassrt axi_wlast when the last write data has been
+ // accepted by the slave with a valid response
+ else if (wnext)
+ axi_wlast <= 1'b0;
+ else if (axi_wlast && C_M_AXI_BURST_LEN == 1)
+ axi_wlast <= 1'b0;
+ else
+ axi_wlast <= axi_wlast;
+ end
+
+
+ /* Burst length counter. Uses extra counter register bit to indicate terminal
+ count to reduce decode logic */
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_write == 1'b1)
+ begin
+ write_index <= 0;
+ end
+ else if (wnext && (write_index != C_M_AXI_BURST_LEN-1))
+ begin
+ write_index <= write_index + 1;
+ end
+ else
+ write_index <= write_index;
+ end
+
+
+ /* Write Data Generator
+ Data pattern is only a simple incrementing count from 0 for each burst */
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ axi_wdata <= 'b1;
+ //else if (wnext && axi_wlast)
+ // axi_wdata <= 'b0;
+ else if (wnext)
+ axi_wdata <= axi_wdata + 1;
+ else
+ axi_wdata <= axi_wdata;
+ end
+
+
+ //----------------------------
+ //Write Response (B) Channel
+ //----------------------------
+
+ //The write response channel provides feedback that the write has committed
+ //to memory. BREADY will occur when all of the data and the write address
+ //has arrived and been accepted by the slave.
+
+ //The write issuance (number of outstanding write addresses) is started by
+ //the Address Write transfer, and is completed by a BREADY/BRESP.
+
+ //While negating BREADY will eventually throttle the AWREADY signal,
+ //it is best not to throttle the whole data channel this way.
+
+ //The BRESP bit [1] is used indicate any errors from the interconnect or
+ //slave for the entire write burst. This example will capture the error
+ //into the ERROR output.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_bready <= 1'b0;
+ end
+ // accept/acknowledge bresp with axi_bready by the master
+ // when M_AXI_BVALID is asserted by slave
+ else if (M_AXI_BVALID && ~axi_bready)
+ begin
+ axi_bready <= 1'b1;
+ end
+ // deassert after one clock cycle
+ else if (axi_bready)
+ begin
+ axi_bready <= 1'b0;
+ end
+ // retain the previous value
+ else
+ axi_bready <= axi_bready;
+ end
+
+
+ //Flag any write response errors
+ assign write_resp_error = axi_bready & M_AXI_BVALID & M_AXI_BRESP[1];
+
+
+ //----------------------------
+ //Read Address Channel
+ //----------------------------
+
+ //The Read Address Channel (AW) provides a similar function to the
+ //Write Address channel- to provide the tranfer qualifiers for the burst.
+
+ //In this example, the read address increments in the same
+ //manner as the write address channel.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_arvalid <= 1'b0;
+ end
+ // If previously not valid , start next transaction
+ else if (~axi_arvalid && start_single_burst_read)
+ begin
+ axi_arvalid <= 1'b1;
+ end
+ else if (M_AXI_ARREADY && axi_arvalid)
+ begin
+ axi_arvalid <= 1'b0;
+ end
+ else
+ axi_arvalid <= axi_arvalid;
+ end
+
+
+ // Next address after ARREADY indicates previous address acceptance
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ axi_araddr <= 'b0;
+ end
+ else if (M_AXI_ARREADY && axi_arvalid)
+ begin
+ axi_araddr <= axi_araddr + burst_size_bytes;
+ end
+ else
+ axi_araddr <= axi_araddr;
+ end
+
+
+ //--------------------------------
+ //Read Data (and Response) Channel
+ //--------------------------------
+
+ // Forward movement occurs when the channel is valid and ready
+ assign rnext = M_AXI_RVALID && axi_rready;
+
+
+ // Burst length counter. Uses extra counter register bit to indicate
+ // terminal count to reduce decode logic
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_read)
+ begin
+ read_index <= 0;
+ end
+ else if (rnext && (read_index != C_M_AXI_BURST_LEN-1))
+ begin
+ read_index <= read_index + 1;
+ end
+ else
+ read_index <= read_index;
+ end
+
+
+ /*
+ The Read Data channel returns the results of the read request
+
+ In this example the data checker is always able to accept
+ more data, so no need to throttle the RREADY signal
+ */
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_rready <= 1'b0;
+ end
+ // accept/acknowledge rdata/rresp with axi_rready by the master
+ // when M_AXI_RVALID is asserted by slave
+ else if (M_AXI_RVALID)
+ begin
+ if (M_AXI_RLAST && axi_rready)
+ begin
+ axi_rready <= 1'b0;
+ end
+ else
+ begin
+ axi_rready <= 1'b1;
+ end
+ end
+ // retain the previous value
+ end
+
+ //Check received read data against data generator
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ read_mismatch <= 1'b0;
+ end
+ //Only check data when RVALID is active
+ else if (rnext && (M_AXI_RDATA != expected_rdata))
+ begin
+ read_mismatch <= 1'b1;
+ end
+ else
+ read_mismatch <= 1'b0;
+ end
+
+ //Flag any read response errors
+ assign read_resp_error = axi_rready & M_AXI_RVALID & M_AXI_RRESP[1];
+
+
+ //----------------------------------------
+ //Example design read check data generator
+ //-----------------------------------------
+
+ //Generate expected read data to check against actual read data
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)// || M_AXI_RLAST)
+ expected_rdata <= 'b1;
+ else if (M_AXI_RVALID && axi_rready)
+ expected_rdata <= expected_rdata + 1;
+ else
+ expected_rdata <= expected_rdata;
+ end
+
+
+ //----------------------------------
+ //Example design error register
+ //----------------------------------
+
+ //Register and hold any data mismatches, or read/write interface errors
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ error_reg <= 1'b0;
+ end
+ else if (read_mismatch || write_resp_error || read_resp_error)
+ begin
+ error_reg <= 1'b1;
+ end
+ else
+ error_reg <= error_reg;
+ end
+
+
+ //--------------------------------
+ //Example design throttling
+ //--------------------------------
+
+ // For maximum port throughput, this user example code will try to allow
+ // each channel to run as independently and as quickly as possible.
+
+ // However, there are times when the flow of data needs to be throtted by
+ // the user application. This example application requires that data is
+ // not read before it is written and that the write channels do not
+ // advance beyond an arbitrary threshold (say to prevent an
+ // overrun of the current read address by the write address).
+
+ // From AXI4 Specification, 13.13.1: "If a master requires ordering between
+ // read and write transactions, it must ensure that a response is received
+ // for the previous transaction before issuing the next transaction."
+
+ // This example accomplishes this user application throttling through:
+ // -Reads wait for writes to fully complete
+ // -Address writes wait when not read + issued transaction counts pass
+ // a parameterized threshold
+ // -Writes wait when a not read + active data burst count pass
+ // a parameterized threshold
+
+ // write_burst_counter counter keeps track with the number of burst transaction initiated
+ // against the number of burst transactions the master needs to initiate
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ write_burst_counter <= 'b0;
+ end
+ else if (M_AXI_AWREADY && axi_awvalid)
+ begin
+ if (write_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
+ begin
+ write_burst_counter <= write_burst_counter + 1'b1;
+ //write_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
+ end
+ end
+ else
+ write_burst_counter <= write_burst_counter;
+ end
+
+ // read_burst_counter counter keeps track with the number of burst transaction initiated
+ // against the number of burst transactions the master needs to initiate
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ read_burst_counter <= 'b0;
+ end
+ else if (M_AXI_ARREADY && axi_arvalid)
+ begin
+ if (read_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
+ begin
+ read_burst_counter <= read_burst_counter + 1'b1;
+ //read_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
+ end
+ end
+ else
+ read_burst_counter <= read_burst_counter;
+ end
+
+
+ //implement master command interface state machine
+
+ always @ ( posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 1'b0 )
+ begin
+ // reset condition
+ // All the signals are assigned default values under reset condition
+ mst_exec_state <= IDLE;
+ start_single_burst_write <= 1'b0;
+ start_single_burst_read <= 1'b0;
+ compare_done <= 1'b0;
+ ERROR <= 1'b0;
+ end
+ else
+ begin
+
+ // state transition
+ case (mst_exec_state)
+
+ IDLE:
+ // This state is responsible to wait for user defined C_M_START_COUNT
+ // number of clock cycles.
+ if ( init_txn_pulse == 1'b1)
+ begin
+ mst_exec_state <= INIT_WRITE;
+ ERROR <= 1'b0;
+ compare_done <= 1'b0;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+
+ INIT_WRITE:
+ // This state is responsible to issue start_single_write pulse to
+ // initiate a write transaction. Write transactions will be
+ // issued until burst_write_active signal is asserted.
+ // write controller
+ if (writes_done)
+ begin
+ mst_exec_state <= INIT_READ;//
+ end
+ else
+ begin
+ mst_exec_state <= INIT_WRITE;
+
+ if (~axi_awvalid && ~start_single_burst_write && ~burst_write_active)
+ begin
+ start_single_burst_write <= 1'b1;
+ end
+ else
+ begin
+ start_single_burst_write <= 1'b0; //Negate to generate a pulse
+ end
+ end
+
+ INIT_READ:
+ // This state is responsible to issue start_single_read pulse to
+ // initiate a read transaction. Read transactions will be
+ // issued until burst_read_active signal is asserted.
+ // read controller
+ if (reads_done)
+ begin
+ mst_exec_state <= INIT_COMPARE;
+ end
+ else
+ begin
+ mst_exec_state <= INIT_READ;
+
+ if (~axi_arvalid && ~burst_read_active && ~start_single_burst_read)
+ begin
+ start_single_burst_read <= 1'b1;
+ end
+ else
+ begin
+ start_single_burst_read <= 1'b0; //Negate to generate a pulse
+ end
+ end
+
+ INIT_COMPARE:
+ // This state is responsible to issue the state of comparison
+ // of written data with the read data. If no error flags are set,
+ // compare_done signal will be asseted to indicate success.
+ //if (~error_reg)
+ begin
+ ERROR <= error_reg;
+ mst_exec_state <= IDLE;
+ compare_done <= 1'b1;
+ end
+ default :
+ begin
+ mst_exec_state <= IDLE;
+ end
+ endcase
+ end
+ end //MASTER_EXECUTION_PROC
+
+
+ // burst_write_active signal is asserted when there is a burst write transaction
+ // is initiated by the assertion of start_single_burst_write. burst_write_active
+ // signal remains asserted until the burst write is accepted by the slave
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ burst_write_active <= 1'b0;
+
+ //The burst_write_active is asserted when a write burst transaction is initiated
+ else if (start_single_burst_write)
+ burst_write_active <= 1'b1;
+ else if (M_AXI_BVALID && axi_bready)
+ burst_write_active <= 0;
+ end
+
+ // Check for last write completion.
+
+ // This logic is to qualify the last write count with the final write
+ // response. This demonstrates how to confirm that a write has been
+ // committed.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ writes_done <= 1'b0;
+
+ //The writes_done should be associated with a bready response
+ //else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
+ else if (M_AXI_BVALID && (write_burst_counter[C_NO_BURSTS_REQ]) && axi_bready)
+ writes_done <= 1'b1;
+ else
+ writes_done <= writes_done;
+ end
+
+ // burst_read_active signal is asserted when there is a burst write transaction
+ // is initiated by the assertion of start_single_burst_write. start_single_burst_read
+ // signal remains asserted until the burst read is accepted by the master
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ burst_read_active <= 1'b0;
+
+ //The burst_write_active is asserted when a write burst transaction is initiated
+ else if (start_single_burst_read)
+ burst_read_active <= 1'b1;
+ else if (M_AXI_RVALID && axi_rready && M_AXI_RLAST)
+ burst_read_active <= 0;
+ end
+
+
+ // Check for last read completion.
+
+ // This logic is to qualify the last read count with the final read
+ // response. This demonstrates how to confirm that a read has been
+ // committed.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ reads_done <= 1'b0;
+
+ //The reads_done should be associated with a rready response
+ //else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
+ else if (M_AXI_RVALID && axi_rready && (read_index == C_M_AXI_BURST_LEN-1) && (read_burst_counter[C_NO_BURSTS_REQ]))
+ reads_done <= 1'b1;
+ else
+ reads_done <= reads_done;
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v
new file mode 100644
index 0000000..c410c75
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v
@@ -0,0 +1,623 @@
+//-----------------------------------------------------------------
+// UART -> AXI Debug Bridge
+// V1.0
+// Ultra-Embedded.com
+// Copyright 2017-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module dbg_bridge
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+ parameter CLK_FREQ = 24000000
+ ,parameter UART_SPEED = 115200
+ ,parameter AXI_ID = 4'd0
+ ,parameter GPIO_ADDRESS = 32'hf0000000
+ ,parameter STS_ADDRESS = 32'hf0000004
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input uart_rxd_i
+ ,input mem_awready_i
+ ,input mem_wready_i
+ ,input mem_bvalid_i
+ ,input [ 1:0] mem_bresp_i
+ ,input [ 3:0] mem_bid_i
+ ,input mem_arready_i
+ ,input mem_rvalid_i
+ ,input [ 31:0] mem_rdata_i
+ ,input [ 1:0] mem_rresp_i
+ ,input [ 3:0] mem_rid_i
+ ,input mem_rlast_i
+ ,input [ 31:0] gpio_inputs_i
+
+ // Outputs
+ ,output uart_txd_o
+ ,output mem_awvalid_o
+ ,output [ 31:0] mem_awaddr_o
+ ,output [ 3:0] mem_awid_o
+ ,output [ 7:0] mem_awlen_o
+ ,output [ 1:0] mem_awburst_o
+ ,output mem_wvalid_o
+ ,output [ 31:0] mem_wdata_o
+ ,output [ 3:0] mem_wstrb_o
+ ,output mem_wlast_o
+ ,output mem_bready_o
+ ,output mem_arvalid_o
+ ,output [ 31:0] mem_araddr_o
+ ,output [ 3:0] mem_arid_o
+ ,output [ 7:0] mem_arlen_o
+ ,output [ 1:0] mem_arburst_o
+ ,output mem_rready_o
+ ,output [ 31:0] gpio_outputs_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines
+//-----------------------------------------------------------------
+localparam REQ_WRITE = 8'h10;
+localparam REQ_READ = 8'h11;
+
+`define STATE_W 4
+`define STATE_R 3:0
+localparam STATE_IDLE = 4'd0;
+localparam STATE_LEN = 4'd2;
+localparam STATE_ADDR0 = 4'd3;
+localparam STATE_ADDR1 = 4'd4;
+localparam STATE_ADDR2 = 4'd5;
+localparam STATE_ADDR3 = 4'd6;
+localparam STATE_WRITE = 4'd7;
+localparam STATE_READ = 4'd8;
+localparam STATE_DATA0 = 4'd9;
+localparam STATE_DATA1 = 4'd10;
+localparam STATE_DATA2 = 4'd11;
+localparam STATE_DATA3 = 4'd12;
+
+//-----------------------------------------------------------------
+// Wires / Regs
+//-----------------------------------------------------------------
+wire uart_wr_w;
+wire [7:0] uart_wr_data_w;
+wire uart_wr_busy_w;
+
+wire uart_rd_w;
+wire [7:0] uart_rd_data_w;
+wire uart_rd_valid_w;
+
+wire uart_rx_error_w;
+
+wire tx_valid_w;
+wire [7:0] tx_data_w;
+wire tx_accept_w;
+wire read_skip_w;
+
+wire rx_valid_w;
+wire [7:0] rx_data_w;
+wire rx_accept_w;
+
+reg [31:0] mem_addr_q;
+reg mem_busy_q;
+reg mem_wr_q;
+
+reg [7:0] len_q;
+
+// Byte Index
+reg [1:0] data_idx_q;
+
+// Word storage
+reg [31:0] data_q;
+
+wire magic_addr_w = (mem_addr_q == GPIO_ADDRESS || mem_addr_q == STS_ADDRESS);
+
+//-----------------------------------------------------------------
+// UART core
+//-----------------------------------------------------------------
+dbg_bridge_uart
+#( .UART_DIVISOR_W(32) )
+u_uart
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ // Control
+ .bit_div_i((CLK_FREQ / UART_SPEED) - 1),
+ .stop_bits_i(1'b0), // 0 = 1, 1 = 2
+
+ // Transmit
+ .wr_i(uart_wr_w),
+ .data_i(uart_wr_data_w),
+ .tx_busy_o(uart_wr_busy_w),
+
+ // Receive
+ .rd_i(uart_rd_w),
+ .data_o(uart_rd_data_w),
+ .rx_ready_o(uart_rd_valid_w),
+
+ .rx_err_o(uart_rx_error_w),
+
+ // UART pins
+ .rxd_i(uart_rxd_i),
+ .txd_o(uart_txd_o)
+);
+
+//-----------------------------------------------------------------
+// Output FIFO
+//-----------------------------------------------------------------
+wire uart_tx_pop_w = ~uart_wr_busy_w;
+
+dbg_bridge_fifo
+#(
+ .WIDTH(8),
+ .DEPTH(8),
+ .ADDR_W(3)
+)
+u_fifo_tx
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ // In
+ .push_i(tx_valid_w),
+ .data_in_i(tx_data_w),
+ .accept_o(tx_accept_w),
+
+ // Out
+ .pop_i(uart_tx_pop_w),
+ .data_out_o(uart_wr_data_w),
+ .valid_o(uart_wr_w)
+);
+
+//-----------------------------------------------------------------
+// Input FIFO
+//-----------------------------------------------------------------
+dbg_bridge_fifo
+#(
+ .WIDTH(8),
+ .DEPTH(8),
+ .ADDR_W(3)
+)
+u_fifo_rx
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ // In
+ .push_i(uart_rd_valid_w),
+ .data_in_i(uart_rd_data_w),
+ .accept_o(uart_rd_w),
+
+ // Out
+ .pop_i(rx_accept_w),
+ .data_out_o(rx_data_w),
+ .valid_o(rx_valid_w)
+);
+
+//-----------------------------------------------------------------
+// States
+//-----------------------------------------------------------------
+reg [`STATE_R] state_q;
+reg [`STATE_R] next_state_r;
+
+always @ *
+begin
+ next_state_r = state_q;
+
+ case (next_state_r)
+ //-------------------------------------------------------------
+ // IDLE:
+ //-------------------------------------------------------------
+ STATE_IDLE:
+ begin
+ if (rx_valid_w)
+ begin
+ case (rx_data_w)
+ REQ_WRITE,
+ REQ_READ:
+ next_state_r = STATE_LEN;
+ default:
+ ;
+ endcase
+ end
+ end
+ //-----------------------------------------
+ // STATE_LEN
+ //-----------------------------------------
+ STATE_LEN :
+ begin
+ if (rx_valid_w)
+ next_state_r = STATE_ADDR0;
+ end
+ //-----------------------------------------
+ // STATE_ADDR
+ //-----------------------------------------
+ STATE_ADDR0 : if (rx_valid_w) next_state_r = STATE_ADDR1;
+ STATE_ADDR1 : if (rx_valid_w) next_state_r = STATE_ADDR2;
+ STATE_ADDR2 : if (rx_valid_w) next_state_r = STATE_ADDR3;
+ STATE_ADDR3 :
+ begin
+ if (rx_valid_w && mem_wr_q)
+ next_state_r = STATE_WRITE;
+ else if (rx_valid_w)
+ next_state_r = STATE_READ;
+ end
+ //-----------------------------------------
+ // STATE_WRITE
+ //-----------------------------------------
+ STATE_WRITE :
+ begin
+ if (len_q == 8'b0 && (mem_bvalid_i || magic_addr_w))
+ next_state_r = STATE_IDLE;
+ else
+ next_state_r = STATE_WRITE;
+ end
+ //-----------------------------------------
+ // STATE_READ
+ //-----------------------------------------
+ STATE_READ :
+ begin
+ // Data ready
+ if (mem_rvalid_i || magic_addr_w)
+ next_state_r = STATE_DATA0;
+ end
+ //-----------------------------------------
+ // STATE_DATA
+ //-----------------------------------------
+ STATE_DATA0 :
+ begin
+ if (read_skip_w)
+ next_state_r = STATE_DATA1;
+ else if (tx_accept_w && (len_q == 8'b0))
+ next_state_r = STATE_IDLE;
+ else if (tx_accept_w)
+ next_state_r = STATE_DATA1;
+ end
+ STATE_DATA1 :
+ begin
+ if (read_skip_w)
+ next_state_r = STATE_DATA2;
+ else if (tx_accept_w && (len_q == 8'b0))
+ next_state_r = STATE_IDLE;
+ else if (tx_accept_w)
+ next_state_r = STATE_DATA2;
+ end
+ STATE_DATA2 :
+ begin
+ if (read_skip_w)
+ next_state_r = STATE_DATA3;
+ else if (tx_accept_w && (len_q == 8'b0))
+ next_state_r = STATE_IDLE;
+ else if (tx_accept_w)
+ next_state_r = STATE_DATA3;
+ end
+ STATE_DATA3 :
+ begin
+ if (tx_accept_w && (len_q != 8'b0))
+ next_state_r = STATE_READ;
+ else if (tx_accept_w)
+ next_state_r = STATE_IDLE;
+ end
+ default:
+ ;
+ endcase
+end
+
+// State storage
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ state_q <= STATE_IDLE;
+else
+ state_q <= next_state_r;
+
+//-----------------------------------------------------------------
+// RD/WR to and from UART
+//-----------------------------------------------------------------
+
+// Write to UART Tx buffer in the following states
+assign tx_valid_w = ((state_q == STATE_DATA0) |
+ (state_q == STATE_DATA1) |
+ (state_q == STATE_DATA2) |
+ (state_q == STATE_DATA3)) && !read_skip_w;
+
+// Accept data in the following states
+assign rx_accept_w = (state_q == STATE_IDLE) |
+ (state_q == STATE_LEN) |
+ (state_q == STATE_ADDR0) |
+ (state_q == STATE_ADDR1) |
+ (state_q == STATE_ADDR2) |
+ (state_q == STATE_ADDR3) |
+ (state_q == STATE_WRITE && !mem_busy_q);
+
+//-----------------------------------------------------------------
+// Capture length
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ len_q <= 8'd0;
+else if (state_q == STATE_LEN && rx_valid_w)
+ len_q[7:0] <= rx_data_w;
+else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
+ len_q <= len_q - 8'd1;
+else if (state_q == STATE_READ && ((mem_busy_q && mem_rvalid_i) || magic_addr_w))
+ len_q <= len_q - 8'd1;
+else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w && !read_skip_w))
+ len_q <= len_q - 8'd1;
+
+//-----------------------------------------------------------------
+// Capture addr
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_addr_q <= 'd0;
+else if (state_q == STATE_ADDR0 && rx_valid_w)
+ mem_addr_q[31:24] <= rx_data_w;
+else if (state_q == STATE_ADDR1 && rx_valid_w)
+ mem_addr_q[23:16] <= rx_data_w;
+else if (state_q == STATE_ADDR2 && rx_valid_w)
+ mem_addr_q[15:8] <= rx_data_w;
+else if (state_q == STATE_ADDR3 && rx_valid_w)
+ mem_addr_q[7:0] <= rx_data_w;
+// Address increment on every access issued
+else if (state_q == STATE_WRITE && (mem_busy_q && mem_bvalid_i))
+ mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
+else if (state_q == STATE_READ && (mem_busy_q && mem_rvalid_i))
+ mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
+
+//-----------------------------------------------------------------
+// Data Index
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_idx_q <= 2'b0;
+else if (state_q == STATE_ADDR3)
+ data_idx_q <= rx_data_w[1:0];
+else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
+ data_idx_q <= data_idx_q + 2'd1;
+else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && tx_accept_w && (data_idx_q != 2'b0))
+ data_idx_q <= data_idx_q - 2'd1;
+
+assign read_skip_w = (data_idx_q != 2'b0);
+
+//-----------------------------------------------------------------
+// Data Sample
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_q <= 32'b0;
+// Write to memory
+else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
+begin
+ case (data_idx_q)
+ 2'd0: data_q[7:0] <= rx_data_w;
+ 2'd1: data_q[15:8] <= rx_data_w;
+ 2'd2: data_q[23:16] <= rx_data_w;
+ 2'd3: data_q[31:24] <= rx_data_w;
+ endcase
+end
+// Read from GPIO Input?
+else if (state_q == STATE_READ && mem_addr_q == GPIO_ADDRESS)
+begin
+ data_q <= {{(32-32){1'b0}}, gpio_inputs_i};
+end
+// Read from status register?
+else if (state_q == STATE_READ && mem_addr_q == STS_ADDRESS)
+ data_q <= {16'hcafe, 15'd0, mem_busy_q};
+// Read from memory
+else if (state_q == STATE_READ && mem_rvalid_i)
+ data_q <= mem_rdata_i;
+// Shift data out (read response -> UART)
+else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w || read_skip_w))
+ data_q <= {8'b0, data_q[31:8]};
+
+assign tx_data_w = data_q[7:0];
+
+assign mem_wdata_o = data_q;
+
+//-----------------------------------------------------------------
+// AXI: Write Request
+//-----------------------------------------------------------------
+reg mem_awvalid_q;
+reg mem_awvalid_r;
+
+reg mem_wvalid_q;
+reg mem_wvalid_r;
+
+always @ *
+begin
+ mem_awvalid_r = 1'b0;
+ mem_wvalid_r = 1'b0;
+
+ // Hold
+ if (mem_awvalid_o && !mem_awready_i)
+ mem_awvalid_r = mem_awvalid_q;
+ else if (mem_awvalid_o)
+ mem_awvalid_r = 1'b0;
+ // Every 4th byte, issue bus access
+ else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
+ mem_awvalid_r = !magic_addr_w;
+
+ // Hold
+ if (mem_wvalid_o && !mem_wready_i)
+ mem_wvalid_r = mem_wvalid_q;
+ else if (mem_wvalid_o)
+ mem_wvalid_r = 1'b0;
+ // Every 4th byte, issue bus access
+ else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
+ mem_wvalid_r = !magic_addr_w;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ mem_awvalid_q <= 1'b0;
+ mem_wvalid_q <= 1'b0;
+end
+else
+begin
+ mem_awvalid_q <= mem_awvalid_r;
+ mem_wvalid_q <= mem_wvalid_r;
+end
+
+assign mem_awvalid_o = mem_awvalid_q;
+assign mem_wvalid_o = mem_wvalid_q;
+assign mem_awaddr_o = {mem_addr_q[31:2], 2'b0};
+assign mem_awid_o = AXI_ID;
+assign mem_awlen_o = 8'b0;
+assign mem_awburst_o = 2'b01;
+assign mem_wlast_o = 1'b1;
+
+assign mem_bready_o = 1'b1;
+
+//-----------------------------------------------------------------
+// AXI: Read Request
+//-----------------------------------------------------------------
+reg mem_arvalid_q;
+reg mem_arvalid_r;
+
+always @ *
+begin
+ mem_arvalid_r = 1'b0;
+
+ // Hold
+ if (mem_arvalid_o && !mem_arready_i)
+ mem_arvalid_r = mem_arvalid_q;
+ else if (mem_arvalid_o)
+ mem_arvalid_r = 1'b0;
+ else if (state_q == STATE_READ && !mem_busy_q)
+ mem_arvalid_r = !magic_addr_w;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_arvalid_q <= 1'b0;
+else
+ mem_arvalid_q <= mem_arvalid_r;
+
+assign mem_arvalid_o = mem_arvalid_q;
+assign mem_araddr_o = {mem_addr_q[31:2], 2'b0};
+assign mem_arid_o = AXI_ID;
+assign mem_arlen_o = 8'b0;
+assign mem_arburst_o = 2'b01;
+
+assign mem_rready_o = 1'b1;
+
+//-----------------------------------------------------------------
+// Write mask
+//-----------------------------------------------------------------
+reg [3:0] mem_sel_q;
+reg [3:0] mem_sel_r;
+
+always @ *
+begin
+ mem_sel_r = 4'b1111;
+
+ case (data_idx_q)
+ 2'd0: mem_sel_r = 4'b0001;
+ 2'd1: mem_sel_r = 4'b0011;
+ 2'd2: mem_sel_r = 4'b0111;
+ 2'd3: mem_sel_r = 4'b1111;
+ endcase
+
+ case (mem_addr_q[1:0])
+ 2'd0: mem_sel_r = mem_sel_r & 4'b1111;
+ 2'd1: mem_sel_r = mem_sel_r & 4'b1110;
+ 2'd2: mem_sel_r = mem_sel_r & 4'b1100;
+ 2'd3: mem_sel_r = mem_sel_r & 4'b1000;
+ endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_sel_q <= 4'b0;
+// Idle - reset for read requests
+else if (state_q == STATE_IDLE)
+ mem_sel_q <= 4'b1111;
+// Every 4th byte, issue bus access
+else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 8'd1))
+ mem_sel_q <= mem_sel_r;
+
+assign mem_wstrb_o = mem_sel_q;
+
+//-----------------------------------------------------------------
+// Write enable
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_wr_q <= 1'b0;
+else if (state_q == STATE_IDLE && rx_valid_w)
+ mem_wr_q <= (rx_data_w == REQ_WRITE);
+
+//-----------------------------------------------------------------
+// Access in progress
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i == 1'b1)
+ mem_busy_q <= 1'b0;
+else if (mem_arvalid_o || mem_awvalid_o)
+ mem_busy_q <= 1'b1;
+else if (mem_bvalid_i || mem_rvalid_i)
+ mem_busy_q <= 1'b0;
+
+//-----------------------------------------------------------------
+// GPIO Outputs
+//-----------------------------------------------------------------
+reg gpio_wr_q;
+reg [31:0] gpio_output_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ gpio_wr_q <= 1'b0;
+else if (mem_addr_q == GPIO_ADDRESS && state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
+ gpio_wr_q <= 1'b1;
+else
+ gpio_wr_q <= 1'b0;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ gpio_output_q <= 32'h0;
+else if (gpio_wr_q)
+ gpio_output_q <= data_q[31:0];
+
+assign gpio_outputs_o = gpio_output_q;
+
+
+
+endmodule
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
new file mode 100644
index 0000000..8f43639
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
@@ -0,0 +1,118 @@
+//-----------------------------------------------------------------
+// UART -> AXI Debug Bridge
+// V1.0
+// Ultra-Embedded.com
+// Copyright 2017-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+module dbg_bridge_fifo
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+ parameter WIDTH = 8,
+ parameter DEPTH = 4,
+ parameter ADDR_W = 2
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input [WIDTH-1:0] data_in_i
+ ,input push_i
+ ,input pop_i
+
+ // Outputs
+ ,output [WIDTH-1:0] data_out_o
+ ,output accept_o
+ ,output valid_o
+);
+
+//-----------------------------------------------------------------
+// Local Params
+//-----------------------------------------------------------------
+localparam COUNT_W = ADDR_W + 1;
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+reg [WIDTH-1:0] ram_q[DEPTH-1:0];
+reg [ADDR_W-1:0] rd_ptr_q;
+reg [ADDR_W-1:0] wr_ptr_q;
+reg [COUNT_W-1:0] count_q;
+
+//-----------------------------------------------------------------
+// Sequential
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ count_q <= {(COUNT_W) {1'b0}};
+ rd_ptr_q <= {(ADDR_W) {1'b0}};
+ wr_ptr_q <= {(ADDR_W) {1'b0}};
+end
+else
+begin
+ // Push
+ if (push_i & accept_o)
+ begin
+ ram_q[wr_ptr_q] <= data_in_i;
+ wr_ptr_q <= wr_ptr_q + 1;
+ end
+
+ // Pop
+ if (pop_i & valid_o)
+ rd_ptr_q <= rd_ptr_q + 1;
+
+ // Count up
+ if ((push_i & accept_o) & ~(pop_i & valid_o))
+ count_q <= count_q + 1;
+ // Count down
+ else if (~(push_i & accept_o) & (pop_i & valid_o))
+ count_q <= count_q - 1;
+end
+
+//-------------------------------------------------------------------
+// Combinatorial
+//-------------------------------------------------------------------
+/* verilator lint_off WIDTH */
+assign valid_o = (count_q != 0);
+assign accept_o = (count_q != DEPTH);
+/* verilator lint_on WIDTH */
+
+assign data_out_o = ram_q[rd_ptr_q];
+
+endmodule
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
new file mode 100644
index 0000000..fc3c570
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
@@ -0,0 +1,341 @@
+//-----------------------------------------------------------------
+// UART -> AXI Debug Bridge
+// V1.0
+// Ultra-Embedded.com
+// Copyright 2017-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+module dbg_bridge_uart
+
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+ parameter UART_DIVISOR_W = 9
+)
+
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+ // Clock & Reset
+ input clk_i,
+ input rst_i,
+
+ // Control
+ input [UART_DIVISOR_W-1:0] bit_div_i,
+ input stop_bits_i, // 0 = 1, 1 = 2
+
+ // Transmit
+ input wr_i,
+ input [7:0] data_i,
+ output tx_busy_o,
+
+ // Receive
+ input rd_i,
+ output [7:0] data_o,
+ output rx_ready_o,
+
+ output rx_err_o,
+
+ // UART pins
+ input rxd_i,
+ output txd_o
+);
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+localparam START_BIT = 4'd0;
+localparam STOP_BIT0 = 4'd9;
+localparam STOP_BIT1 = 4'd10;
+
+// Xilinx placement pragmas:
+//synthesis attribute IOB of txd_q is "TRUE"
+
+// TX Signals
+reg tx_busy_q;
+reg [3:0] tx_bits_q;
+reg [UART_DIVISOR_W-1:0] tx_count_q;
+reg [7:0] tx_shift_reg_q;
+reg txd_q;
+
+// RX Signals
+reg rxd_q;
+reg [7:0] rx_data_q;
+reg [3:0] rx_bits_q;
+reg [UART_DIVISOR_W-1:0] rx_count_q;
+reg [7:0] rx_shift_reg_q;
+reg rx_ready_q;
+reg rx_busy_q;
+
+reg rx_err_q;
+
+//-----------------------------------------------------------------
+// Re-sync RXD
+//-----------------------------------------------------------------
+reg rxd_ms_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ rxd_ms_q <= 1'b1;
+ rxd_q <= 1'b1;
+end
+else
+begin
+ rxd_ms_q <= rxd_i;
+ rxd_q <= rxd_ms_q;
+end
+
+//-----------------------------------------------------------------
+// RX Clock Divider
+//-----------------------------------------------------------------
+wire rx_sample_w = (rx_count_q == {(UART_DIVISOR_W){1'b0}});
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_count_q <= {(UART_DIVISOR_W){1'b0}};
+else
+begin
+ // Inactive
+ if (!rx_busy_q)
+ rx_count_q <= {1'b0, bit_div_i[UART_DIVISOR_W-1:1]};
+ // Rx bit timer
+ else if (rx_count_q != 0)
+ rx_count_q <= (rx_count_q - 1);
+ // Active
+ else if (rx_sample_w)
+ begin
+ // Last bit?
+ if ((rx_bits_q == STOP_BIT0 && !stop_bits_i) || (rx_bits_q == STOP_BIT1 && stop_bits_i))
+ rx_count_q <= {(UART_DIVISOR_W){1'b0}};
+ else
+ rx_count_q <= bit_div_i;
+ end
+end
+
+//-----------------------------------------------------------------
+// RX Shift Register
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ rx_shift_reg_q <= 8'h00;
+ rx_busy_q <= 1'b0;
+end
+// Rx busy
+else if (rx_busy_q && rx_sample_w)
+begin
+ // Last bit?
+ if (rx_bits_q == STOP_BIT0 && !stop_bits_i)
+ rx_busy_q <= 1'b0;
+ else if (rx_bits_q == STOP_BIT1 && stop_bits_i)
+ rx_busy_q <= 1'b0;
+ else if (rx_bits_q == START_BIT)
+ begin
+ // Start bit should still be low as sampling mid
+ // way through start bit, so if high, error!
+ if (rxd_q)
+ rx_busy_q <= 1'b0;
+ end
+ // Rx shift register
+ else
+ rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
+end
+// Start bit?
+else if (!rx_busy_q && rxd_q == 1'b0)
+begin
+ rx_shift_reg_q <= 8'h00;
+ rx_busy_q <= 1'b1;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_bits_q <= START_BIT;
+else if (rx_sample_w && rx_busy_q)
+begin
+ if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
+ rx_bits_q <= START_BIT;
+ else
+ rx_bits_q <= rx_bits_q + 4'd1;
+end
+else if (!rx_busy_q && (bit_div_i == {(UART_DIVISOR_W){1'b0}}))
+ rx_bits_q <= START_BIT + 4'd1;
+else if (!rx_busy_q)
+ rx_bits_q <= START_BIT;
+
+//-----------------------------------------------------------------
+// RX Data
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ rx_ready_q <= 1'b0;
+ rx_data_q <= 8'h00;
+ rx_err_q <= 1'b0;
+end
+else
+begin
+ // If reading data, reset data state
+ if (rd_i == 1'b1)
+ begin
+ rx_ready_q <= 1'b0;
+ rx_err_q <= 1'b0;
+ end
+
+ if (rx_busy_q && rx_sample_w)
+ begin
+ // Stop bit
+ if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
+ begin
+ // RXD should be still high
+ if (rxd_q)
+ begin
+ rx_data_q <= rx_shift_reg_q;
+ rx_ready_q <= 1'b1;
+ end
+ // Bad Stop bit - wait for a full bit period
+ // before allowing start bit detection again
+ else
+ begin
+ rx_ready_q <= 1'b0;
+ rx_data_q <= 8'h00;
+ rx_err_q <= 1'b1;
+ end
+ end
+ // Mid start bit sample - if high then error
+ else if (rx_bits_q == START_BIT && rxd_q)
+ rx_err_q <= 1'b1;
+ end
+end
+
+//-----------------------------------------------------------------
+// TX Clock Divider
+//-----------------------------------------------------------------
+wire tx_sample_w = (tx_count_q == {(UART_DIVISOR_W){1'b0}});
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ tx_count_q <= {(UART_DIVISOR_W){1'b0}};
+else
+begin
+ // Idle
+ if (!tx_busy_q)
+ tx_count_q <= bit_div_i;
+ // Tx bit timer
+ else if (tx_count_q != 0)
+ tx_count_q <= (tx_count_q - 1);
+ else if (tx_sample_w)
+ tx_count_q <= bit_div_i;
+end
+
+//-----------------------------------------------------------------
+// TX Shift Register
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ tx_shift_reg_q <= 8'h00;
+ tx_busy_q <= 1'b0;
+end
+// Tx busy
+else if (tx_busy_q)
+begin
+ // Shift tx data
+ if (tx_bits_q != START_BIT && tx_sample_w)
+ tx_shift_reg_q <= {1'b0, tx_shift_reg_q[7:1]};
+
+ // Last bit?
+ if (tx_bits_q == STOP_BIT0 && tx_sample_w && !stop_bits_i)
+ tx_busy_q <= 1'b0;
+ else if (tx_bits_q == STOP_BIT1 && tx_sample_w && stop_bits_i)
+ tx_busy_q <= 1'b0;
+end
+// Buffer data to transmit
+else if (wr_i)
+begin
+ tx_shift_reg_q <= data_i;
+ tx_busy_q <= 1'b1;
+end
+
+always @ (posedge clk_i or posedge rst_i )
+if (rst_i)
+ tx_bits_q <= 4'd0;
+else if (tx_sample_w && tx_busy_q)
+begin
+ if ((tx_bits_q == STOP_BIT1 && stop_bits_i) || (tx_bits_q == STOP_BIT0 && !stop_bits_i))
+ tx_bits_q <= START_BIT;
+ else
+ tx_bits_q <= tx_bits_q + 4'd1;
+end
+
+//-----------------------------------------------------------------
+// UART Tx Pin
+//-----------------------------------------------------------------
+reg txd_r;
+
+always @ *
+begin
+ txd_r = 1'b1;
+
+ if (tx_busy_q)
+ begin
+ // Start bit (TXD = L)
+ if (tx_bits_q == START_BIT)
+ txd_r = 1'b0;
+ // Stop bits (TXD = H)
+ else if (tx_bits_q == STOP_BIT0 || tx_bits_q == STOP_BIT1)
+ txd_r = 1'b1;
+ // Data bits
+ else
+ txd_r = tx_shift_reg_q[0];
+ end
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ txd_q <= 1'b1;
+else
+ txd_q <= txd_r;
+
+//-----------------------------------------------------------------
+// Outputs
+//-----------------------------------------------------------------
+assign tx_busy_o = tx_busy_q;
+assign rx_ready_o = rx_ready_q;
+assign txd_o = txd_q;
+assign data_o = rx_data_q;
+assign rx_err_o = rx_err_q;
+
+endmodule
diff --git a/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
new file mode 100644
index 0000000..5460b99
--- /dev/null
+++ b/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
@@ -0,0 +1,190 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_M00_AXI_TARGET_SLAVE_BASE_ADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_BURST_LEN" -parent ${Page_0} -widget comboBox
+ ipgui::add_param $IPINST -name "C_M00_AXI_ID_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_ADDR_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
+ ipgui::add_param $IPINST -name "C_M00_AXI_AWUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_ARUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_WUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_RUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_BUSER_WIDTH" -parent ${Page_0}
+
+ ipgui::add_param $IPINST -name "CLK_SPEED"
+ ipgui::add_param $IPINST -name "UART_BAUD_RATE"
+
+}
+
+proc update_PARAM_VALUE.CLK_SPEED { PARAM_VALUE.CLK_SPEED } {
+ # Procedure called to update CLK_SPEED when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CLK_SPEED { PARAM_VALUE.CLK_SPEED } {
+ # Procedure called to validate CLK_SPEED
+ return true
+}
+
+proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
+ # Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
+ # Procedure called to validate UART_BAUD_RATE
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to update C_M00_AXI_TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to validate C_M00_AXI_TARGET_SLAVE_BASE_ADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
+ # Procedure called to update C_M00_AXI_BURST_LEN when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
+ # Procedure called to validate C_M00_AXI_BURST_LEN
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
+ # Procedure called to update C_M00_AXI_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ID_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_M00_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_AWUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ARUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_WUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_RUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_BUSER_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_BURST_LEN { MODELPARAM_VALUE.C_M00_AXI_BURST_LEN PARAM_VALUE.C_M00_AXI_BURST_LEN } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BURST_LEN}] ${MODELPARAM_VALUE.C_M00_AXI_BURST_LEN}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ID_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.CLK_SPEED { MODELPARAM_VALUE.CLK_SPEED PARAM_VALUE.CLK_SPEED } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.CLK_SPEED}] ${MODELPARAM_VALUE.CLK_SPEED}
+}
+
+proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
+}
+
diff --git a/fpga_imp/scripts/build_mcu_fpga_arm_mps3.tcl b/fpga_imp/scripts/build_mcu_fpga_arm_mps3.tcl
index 40985d1..f0fde1c 100644
--- a/fpga_imp/scripts/build_mcu_fpga_arm_mps3.tcl
+++ b/fpga_imp/scripts/build_mcu_fpga_arm_mps3.tcl
@@ -61,14 +61,18 @@ read_verilog $importDir/design_1_wrapper.v
source $importDir/design_1.tcl
create_root_design ""
-add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../verilog/pl230_defs.v}
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property is_global_include true [get_files ../verilog/pl230_defs.v]
-
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property file_type {Verilog Header} [get_files ../verilog/pl230_defs.v]
+set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest
+add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
+add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
+add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
+
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
+
add_files $importDir/fpga_pinmap.xdc
diff --git a/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl b/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
index 9f09450..469eb25 100644
--- a/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
+++ b/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -64,14 +64,17 @@ source $importDir/design_1.tcl
create_root_design ""
set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest
-add_files -norecurse -scan_for_includes "$arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../defines/pl230_defs.v"
+add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
+add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
+add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property is_global_include true [get_files ../defines/pl230_defs.v]
+set_property is_global_include true [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property file_type {Verilog Header} [get_files ../defines/pl230_defs.v]
+set_property file_type {Verilog Header} [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
+
add_files $importDir/fpga_pinmap.xdc
diff --git a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
index a2643a2..36e63b6 100644
--- a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
+++ b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -28,7 +28,7 @@ set pynqDir pynq_export/pz104/pynq/overlays/soclabs
# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
#
source scripts/build_mcu_fpga_ip.tcl
-
+set_property include_dirs " $env(ACCELERATOR_DIR)/src/rtl $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines/ $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines" [current_fileset]
#
# STEP#1: setup design sources and constraints
#
@@ -62,20 +62,18 @@ read_verilog $importDir/design_1_wrapper.v
source $importDir/design_1.tcl
create_root_design ""
-#set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest
-#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
-#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
-
-#add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
-#set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-#set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-#set_property is_global_include true [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
+set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest
+add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
+add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
+add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
-#set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-#set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-#set_property file_type {Verilog Header} [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../system/sldma230_tech/src/defines/pl230_defs.v]
-#add_files -norecurse -scan_for_includes
add_files $importDir/fpga_pinmap.xdc
@@ -85,7 +83,7 @@ set_property top design_1_wrapper [current_fileset]
# STEP#3: save in Project mode to complete flow
#
-save_project_as $project ./$project -exclude_run_results -force
+save_project_as $project ./$project -exclude_run_results -force -scan_for_includes
update_compile_order -fileset sources_1
diff --git a/fpga_imp/target_fpga_arm_mps3/design_1.tcl b/fpga_imp/target_fpga_arm_mps3/design_1.tcl
index 5f7080c..becad42 100644
--- a/fpga_imp/target_fpga_arm_mps3/design_1.tcl
+++ b/fpga_imp/target_fpga_arm_mps3/design_1.tcl
@@ -37,50 +37,83 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl
-set bCheckIPsPassed 1
-##################################################################
-# CHECK IPs
-##################################################################
-set bCheckIPs 1
-if { $bCheckIPs == 1 } {
- set list_check_ips "\
-soclabs.org:user:nanosoc_chip:1.0\
-soclabs.org:user:ADPcontrol:1.0\
-xilinx.com:ip:ahblite_axi_bridge:3.0\
-xilinx.com:ip:axi_bram_ctrl:4.1\
-xilinx.com:ip:axi_gpio:2.0\
-soclabs.org:user:axi_stream_io:1.0\
-xilinx.com:ip:axi_uartlite:2.0\
-xilinx.com:ip:axis_data_fifo:2.0\
-xilinx.com:ip:blk_mem_gen:8.4\
-soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
-xilinx.com:ip:xlslice:1.0\
-xilinx.com:ip:xlconcat:2.1\
-xilinx.com:ip:proc_sys_reset:5.0\
-xilinx.com:ip:smartconnect:1.0\
-xilinx.com:ip:xlconstant:1.1\
-"
-
- set list_ips_missing ""
- common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
-
- foreach ip_vlnv $list_check_ips {
- set ip_obj [get_ipdefs -all $ip_vlnv]
- if { $ip_obj eq "" } {
- lappend list_ips_missing $ip_vlnv
- }
- }
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xcku115-flvb1760-1-c
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
- if { $list_ips_missing ne "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
- set bCheckIPsPassed 0
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
}
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
}
-if { $bCheckIPsPassed != 1 } {
- common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
- return 3
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
}
##################################################################
@@ -123,13 +156,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
current_bd_instance $hier_obj
# Create interface pins
- create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
-
# Create pins
+ create_bd_pin -dir I UART_RX
+ create_bd_pin -dir O UART_TX
create_bd_pin -dir I -type clk aclk
create_bd_pin -dir I -type rst ext_reset_in
- create_bd_pin -dir O -from 0 -to 0 -type rst nrst
create_bd_pin -dir O -from 15 -to 0 p0_tri_i
create_bd_pin -dir I -from 15 -to 0 p0_tri_o
create_bd_pin -dir I -from 15 -to 0 p0_tri_z
@@ -153,7 +185,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
set_property -dict [ list \
- CONFIG.ECC_TYPE {0} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.SINGLE_PORT_BRAM {1} \
] $axi_bram_ctrl_0
@@ -189,13 +220,13 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
set_property -dict [ list \
- CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
] $axi_uartlite_0
# Create instance: axi_uartlite_1, and set properties
set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
set_property -dict [ list \
- CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
] $axi_uartlite_1
# Create instance: axis_data_fifo_0, and set properties
@@ -231,16 +262,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: blk_mem_gen_0, and set properties
set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
set_property -dict [ list \
- CONFIG.Byte_Size {8} \
CONFIG.EN_SAFETY_CKT {true} \
CONFIG.Enable_32bit_Address {true} \
CONFIG.Read_Width_A {32} \
- CONFIG.Read_Width_B {32} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
- CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Use_RSTA_Pin {true} \
CONFIG.Write_Width_A {32} \
- CONFIG.Write_Width_B {32} \
CONFIG.use_bram_block {BRAM_Controller} \
] $blk_mem_gen_0
@@ -373,16 +400,26 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.NUM_PORTS {8} \
] $pmoda_z_concat8
- # Create instance: proc_sys_reset_0, and set properties
- set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
-
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
+ CONFIG.ADVANCED_PROPERTIES {0} \
CONFIG.NUM_MI {8} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
+ # Create instance: uart_to_AXI_master_0, and set properties
+ set uart_to_AXI_master_0 [ create_bd_cell -type ip -vlnv user.org:user:uart_to_AXI_master:1.0 uart_to_AXI_master_0 ]
+ set_property -dict [ list \
+ CONFIG.CLK_SPEED {50000000} \
+ CONFIG.C_M00_AXI_ARUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_AWUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_BUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_ID_WIDTH {4} \
+ CONFIG.C_M00_AXI_RUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_WUSER_WIDTH {4} \
+ ] $uart_to_AXI_master_0
+
# Create instance: xlconstant_0, and set properties
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
set_property -dict [ list \
@@ -416,11 +453,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
- connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+ connect_bd_intf_net -intf_net uart_to_AXI_master_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins uart_to_AXI_master_0/M00_AXI]
# Create port connections
connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net UART_RX_1 [get_bd_pins UART_RX] [get_bd_pins uart_to_AXI_master_0/UART_RX]
connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
@@ -429,6 +467,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_stream_io_0_tx_tdata [get_bd_pins axi_stream_io_0/tx_tdata] [get_bd_pins ft1248x1_to_axi_stream_0/rxd_tdata8_i]
+ connect_bd_net -net axi_stream_io_0_tx_tvalid [get_bd_pins axi_stream_io_0/tx_tvalid] [get_bd_pins ft1248x1_to_axi_stream_0/rxd_tvalid_i]
connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
@@ -439,6 +479,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ft1248x1_to_axi_stream_0_rxd_tready_o [get_bd_pins axi_stream_io_0/tx_tready] [get_bd_pins ft1248x1_to_axi_stream_0/rxd_tready_o]
connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
@@ -451,13 +492,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ext_reset_in] [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins uart_to_AXI_master_0/m00_axi_aresetn]
connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net uart_to_AXI_master_0_UART_TX [get_bd_pins UART_TX] [get_bd_pins uart_to_AXI_master_0/UART_TX]
connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins uart_to_AXI_master_0/m00_axi_aclk]
# Restore current instance
current_bd_instance $oldCurInst
@@ -469,6 +509,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
proc create_root_design { parentCell } {
variable script_folder
+ variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
@@ -498,6 +539,14 @@ proc create_root_design { parentCell } {
# Create interface ports
# Create ports
+ set EXT_CLK [ create_bd_port -dir I -type clk -freq_hz 50000000 EXT_CLK ]
+ # set_property -dict [ list \
+ # CONFIG.ASSOCIATED_ASYNC_RESET {nRST_CPU} \
+ # CONFIG.ASSOCIATED_RESET {nRST_CPU} \
+ #] $EXT_CLK
+ set UART_RX [ create_bd_port -dir I UART_RX ]
+ set UART_TX [ create_bd_port -dir O UART_TX ]
+ set nRST_CPU [ create_bd_port -dir I -type rst nRST_CPU ]
set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
@@ -508,65 +557,50 @@ proc create_root_design { parentCell } {
# Create instance: nanosoc_chip_0, and set properties
set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
-
-
- # Create interface connections
- connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
-
# Create port connections
- connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net EXT_CLK_1 [get_bd_ports EXT_CLK] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i]
+ connect_bd_net -net UART_RX_1 [get_bd_ports UART_RX] [get_bd_pins cmsdk_socket/UART_RX]
+ connect_bd_net -net cmsdk_socket_UART_TX [get_bd_ports UART_TX] [get_bd_pins cmsdk_socket/UART_TX]
connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
- connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net rst_sync_0_reset [get_bd_ports nRST_CPU] [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins nanosoc_chip_0/nrst_i]
connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
# Create address segments
- assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
- assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
- assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
+ validate_bd_design
+ save_bd_design
}
# End of create_root_design()
+##################################################################
+# MAIN FLOW
+##################################################################
+#create_root_design ""
-proc available_tcl_procs { } {
- puts "##################################################################"
- puts "# Available Tcl procedures to recreate hierarchical blocks:"
- puts "#"
- puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
- puts "# create_root_design"
- puts "#"
- puts "#"
- puts "# The following procedures will create hiearchical blocks with addressing "
- puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
- puts "# will not be handled outside those blocks:"
- puts "#"
- puts "# create_root_design"
- puts "#"
- puts "##################################################################"
-}
-available_tcl_procs
diff --git a/fpga_imp/target_fpga_arm_mps3/design_1_wrapper.v b/fpga_imp/target_fpga_arm_mps3/design_1_wrapper.v
index 438e63b..01c9af7 100644
--- a/fpga_imp/target_fpga_arm_mps3/design_1_wrapper.v
+++ b/fpga_imp/target_fpga_arm_mps3/design_1_wrapper.v
@@ -9,7 +9,376 @@
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
-module design_1_wrapper();
+module design_1_wrapper(
+//------------------------------------------------------
+// Port declarations
+//------------------------------------------------------
+// DDR
+ // output wire c0_ddr4_act_n,
+ // output wire [16:0] c0_ddr4_adr,
+ // output wire [1:0] c0_ddr4_ba,
+ // output wire [0:0] c0_ddr4_bg,
+ // output wire [0:0] c0_ddr4_cke,
+ // output wire [0:0] c0_ddr4_odt,
+ // output wire [0:0] c0_ddr4_cs_n,
+ // output wire [0:0] c0_ddr4_ck_t,
+ // output wire [0:0] c0_ddr4_ck_c,
+ // output wire c0_ddr4_reset_n,
+ // inout wire [7:0] c0_ddr4_dm_dbi_n,
+ // inout wire [63:0] c0_ddr4_dq,
+ // inout wire [7:0] c0_ddr4_dqs_t,
+ // inout wire [7:0] c0_ddr4_dqs_c,
+ // input wire c0_sys_clk_p,
+ // input wire c0_sys_clk_n,
+ // input wire DDR_nALERT,
+ // output wire DDR_PARITY,
+ // input DDR_nEVENT,
+ // output wire DDR_SCL,
+ // inout wire DDR_SDA,
+
+// SMB
+//-----------
+ output wire [6:0] SMBF_ADDR,
+ output wire SMBF_FIFOSEL,
+ inout wire [15:0] SMBF_DATA,
+ output wire SMBF_nOE,
+ output wire SMBF_nWE,
+ output wire SMBF_nRST,
+ output wire ETH_nCS,
+ output wire ETH_nOE,
+ input wire ETH_INT,
+
+ output wire USB_nCS,
+ output wire USB_DACK,
+ input wire USB_DREQ,
+ input wire USB_INT,
+
+// HDMI
+//-----------
+ output wire [23:0] MMB_DATA,
+ output wire MMB_DE,
+ output wire MMB_HS,
+ output wire MMB_VS,
+ output wire MMB_IDCLK,
+ output wire MMB_SCK,
+ output wire MMB_WS,
+ output wire [3:0] MMB_SD,
+
+ output wire HDMI_CSCL,
+ inout wire HDMI_CSDA,
+ input wire HDMI_INT,
+
+// Audio
+//-----------
+ output wire AUD_MCLK,
+ output wire AUD_SCLK,
+ output wire AUD_LRCK,
+ output wire AUD_SDIN,
+ input wire AUD_SDOUT,
+
+ output wire AUD_nRST,
+ output wire AUD_SCL,
+ inout wire AUD_SDA,
+
+// EMMC
+//-----------
+ inout wire [7:0] EMMC_DAT,
+ inout wire EMMC_CMD,
+ output wire EMMC_CLK,
+ output wire EMMC_nRST,
+ input wire EMMC_DS,
+
+// CLCD
+//-----------
+ inout wire [17:10] CLCD_PD,
+ output wire CLCD_RD,
+ output wire CLCD_RS,
+ output wire CLCD_CS,
+ output wire CLCD_WR_SCL,
+ output wire CLCD_BL,
+ output wire CLCD_RST,
+
+ output wire CLCD_TSCL,
+ inout wire CLCD_TSDA,
+ input wire CLCD_TINT,
+ output wire CLCD_TNC,
+
+// UART
+//-----------
+ output wire [3:0] UART_TX_F,
+
+ input wire [3:0] UART_RX_F,
+
+// DEBUG
+//-----------
+ input wire CS_TDI,
+ output wire CS_TDO, // SWV / JTAG TDO
+ inout wire CS_TMS, // SWD I/O / JTAG TMS
+ input wire CS_TCK, // SWD Clk / JTAG TCK
+ input wire CS_nSRST,
+ input wire CS_nTRST,
+ input wire CS_nDET,
+
+ output wire [15:0] CS_T_D, // Trace data
+ output wire CS_T_CLK, // Trace clock
+ output wire CS_T_CTL, // Trace control
+
+// LED SW
+//-----------
+ output wire [9:0] USER_nLED,
+ input wire [7:0] USER_SW,
+ input wire [1:0] USER_nPB,
+
+// OSCCLK
+//-----------
+ input wire [5:0] OSCCLK,
+
+// FMC
+//-----------
+ // input wire [1:0] CLK_M2C_P,
+ // input wire [1:0] CLK_M2C_N,
+
+ // input wire FMC_CLK_DIR,
+
+ // inout wire [3:2] CLK_BIDIR_P,
+ // inout wire [3:2] CLK_BIDIR_N,
+
+ // inout wire [23:0] HA_P, // HA CLK=0,1,17
+ // inout wire [23:0] HA_N,
+
+ // inout wire [21:0] HB_P, // HB CLK=0,6,17
+ // inout wire [21:0] HB_N,
+
+ // inout wire [33:0] LA_P, // LA CLK=0,1,17,18
+ // inout wire [33:0] LA_N,
+
+ // input wire [1:0] GBTCLK_M2C_P,
+ // input wire [1:0] GBTCLK_M2C_N,
+// `ifdef GTH
+ // input wire [9:0] DP_M2C_P,
+ // input wire [9:0] DP_M2C_N,
+
+ // output wire [9:0] DP_C2M_P,
+ // output wire [9:0] DP_C2M_N,
+// `endif
+ // input wire FMC_nPRSNT,
+
+ // input wire GTX_CLK_N,
+ // input wire GTX_CLK_P,
+
+ // input wire SATA_CLK_N,
+ // input wire SATA_CLK_P,
+
+// Quad SPI
+//-----------
+ inout wire QSPI_D0,
+ inout wire QSPI_D1,
+ inout wire QSPI_D2,
+ inout wire QSPI_D3,
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+
+// USER SD
+//-----------
+ inout wire [3:0] USD_DAT,
+ inout wire USD_CMD,
+ output wire USD_CLK,
+ input wire USD_NCD,
+
+// RESET
+//-----------
+ input wire CB_nPOR,
+ input wire CB_nRST,
+ input wire CB_RUN,
+
+ input wire IOFPGA_NRST,
+ input wire IOFPGA_NSPIR,
+
+ output wire IOFPGA_SYSWDT,
+ input wire PB_IRQ,
+ output wire WDOG_RREQ,
+
+// SCC
+//-----------
+ output wire CFG_DATAOUT,
+ input wire CFG_LOAD,
+ input wire CFG_nRST,
+ input wire CFG_CLK,
+ input wire CFG_DATAIN,
+ input wire CFG_WnR,
+
+// MCC SMB
+//-----------
+ input wire [25:16] SMBM_A,
+ inout wire [15:0] SMBM_D,
+ input wire [4:1] SMBM_nE,
+ input wire SMBM_CLK,
+ input wire [1:0] SMBM_nBL,
+ input wire SMBM_nOE,
+ input wire SMBM_nWE,
+ output wire SMBM_nWAIT,
+
+// SHIELD
+//-----------
+ inout wire [17:0] SH0_IO,
+ inout wire [17:0] SH1_IO,
+ output wire SH_nRST,
+
+ output wire SH_ADC_CS,
+ output wire SH_ADC_CK,
+ output wire SH_ADC_DI,
+ input wire SH_ADC_DO
+// (PMOD0_0,
+// PMOD0_1,
+// PMOD0_2,
+// PMOD0_3,
+// PMOD0_4,
+// PMOD0_5,
+// PMOD0_6,
+// PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ wire PMOD0_0;
+ wire PMOD0_1;
+ wire PMOD0_2;
+ wire PMOD0_3;
+ wire PMOD0_4;
+ wire PMOD0_5;
+ wire PMOD0_6;
+ wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+ assign SH0_IO[0] = PMOD0_0;
+ assign SH0_IO[1] = PMOD0_1;
+ assign SH0_IO[2] = PMOD0_2;
+ assign SH0_IO[3] = PMOD0_3;
+ assign CS_TMS = PMOD0_4;
+ assign SH0_IO[5] = PMOD0_5;
+ assign SH0_IO[6] = PMOD0_6;
+ assign CS_TCK = PMOD0_7;
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+//REFCLK24MHZ 24 MHz
+//******************************************************************************
+BUFG uBUFG_REFCLK24MHZ (.I(OSCCLK[0]), .O(REFCLK24MHZ));
+
+//ACLK Big CPU 50 MHz
+//******************************************************************************
+BUFG uBUFG_iACLK (.I(OSCCLK[1]), .O(ACLK)); //Big CPU 50 MHz
+BUFG uBUFG_iBCLK (.I(OSCCLK[2]), .O(BCLK));
+//******************************************************************************
+// SMBMCLK Micro SMB 25 MHz
+//******************************************************************************
+BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
+
+//******************************************************************************
+// Main body of code
+// =================
+//******************************************************************************
+ assign SMBF_FIFOSEL = 1'b0;
+ assign SMBF_ADDR = {7{1'b0}};
+ assign CLCD_BL = 1'b0; // Extinguish LCD back light
+ // Minimum design tie-offs
+ assign MMB_IDCLK = 1'b0;
+ assign EMMC_CLK = 1'b0;
+ assign QSPI_nCS = 1'b1;
+ assign QSPI_SCLK = 1'b0;
+ assign IOFPGA_SYSWDT = 1'b0;
+ assign WDOG_RREQ = 1'b0;
+ assign SMBM_nWAIT = 1'b1;
+ assign CFG_DATAOUT = 1'b0;
+ wire nRST;
+ reg rst_sync0, rst_sync1;
+ assign nRST_in = CB_nRST || CS_nSRST;
+
+ always @(posedge ACLK)
+ if (~nRST_in) begin
+ rst_sync0 <= 1'b0;
+ rst_sync1 <= 1'b0;
+ end else begin
+ rst_sync0 <= 1'b1;
+ rst_sync1 <= rst_sync0;
+ end
+
+ assign nRST = rst_sync1;
+
+
+ design_1 design_1_i
+ (.UART_RX(UART_RX_F[2]),
+ .UART_TX(UART_TX_F[2]),
+ .EXT_CLK(ACLK),
+ .nRST_CPU(nRST),
+ .pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
endmodule
--
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