From 4343bd1b3321bd3c5f60f33d072ff0b78008da08 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 6 Dec 2023 21:17:55 +0000
Subject: [PATCH] Add dma350 stream tests
---
nanosoc/sldma350_tech | 2 +-
.../common/validation/dma350_stream_tests.c | 507 +
.../dma350_stream_tests.hex | 10784 ++++++++++++++++
testcodes/dma350_stream_tests/makefile | 285 +
testcodes/excluded_tests.txt | 3 +-
5 files changed, 11579 insertions(+), 2 deletions(-)
create mode 100644 software/common/validation/dma350_stream_tests.c
create mode 100644 testcodes/dma350_stream_tests/dma350_stream_tests.hex
create mode 100644 testcodes/dma350_stream_tests/makefile
diff --git a/nanosoc/sldma350_tech b/nanosoc/sldma350_tech
index d3a9db1..a69e001 160000
--- a/nanosoc/sldma350_tech
+++ b/nanosoc/sldma350_tech
@@ -1 +1 @@
-Subproject commit d3a9db1014315bda22e9025b24fc9cda7b064a10
+Subproject commit a69e001167fc5d075728988e2ca1c047e66f3c14
diff --git a/software/common/validation/dma350_stream_tests.c b/software/common/validation/dma350_stream_tests.c
new file mode 100644
index 0000000..2e90352
--- /dev/null
+++ b/software/common/validation/dma350_stream_tests.c
@@ -0,0 +1,507 @@
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
+#include <stdio.h>
+#include "uart_stdout.h"
+#include "CMSDK_driver.h"
+
+
+#include "config_id.h"
+#include <string.h>
+#include <inttypes.h>
+#include "dma_350_command_lib.h"
+
+//Channel number defines
+// Note: Please add more channels if DMA has more than 8 channels
+#define CH0 0
+#define CH1 1
+
+
+// Note: Please modify the addresses according to the system memory map
+#define COPY_ADDR_SRC_0 0x80000000
+#define COPY_ADDR_SRC_1 0x80000100
+#define COPY_ADDR_SRC_2 0x80000200
+#define COPY_ADDR_DST_0 0x98000000
+#define COPY_ADDR_DST_1 0x98000100
+#define COPY_ADDR_DST_2 0x98000200
+
+
+// Note: Please modify to the desired data size
+#define DATA_SIZE 64
+#define LARGE_DATA_SIZE 10000
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+#if defined ( __CC_ARM )
+__asm void address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int address_test_read(unsigned int addr);
+#else
+ void address_test_write(unsigned int addr, unsigned int wdata);
+ unsigned int address_test_read(unsigned int addr);
+#endif
+
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+
+//typedef unsigned long int uintptr_t;
+// Array for command with a Header + 5 modified registers
+uint32_t LinkCmd[6];
+// Variable to store the address of the above array
+uintptr_t LinkCmd_adr = (uintptr_t) LinkCmd;
+
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+volatile int current_channel;
+
+uint8_t dma350_detect(void);
+void delay(uint32_t t);
+void SystemInitialization(void);
+void DMAClearChIrq(uint32_t ch);
+void DMA_Handler(void) __attribute__((interrupt));
+void initialise_destination(unsigned int actual_addr);
+uint8_t check_destination(unsigned int actual_addr);
+
+int main(void) {
+
+ // Get the number of channels and trigger interfaces
+ uint32_t ch_num;
+ uint32_t trig_in_num;
+ uint32_t trig_out_num;
+ uint32_t errors = 0;
+ unsigned int actual_addr;
+ hardfault_occurred = 0;
+ hardfault_expected = 0;
+ // Call Function for the testbench Specific Initialization
+ // Note: Change to the system specific function for initialization
+ SystemInitialization();
+
+ printf("<--- DMA START --->\n");
+
+ // Define structures for the tests
+ // Note: Command and channel parameters can be modified to the desired settings
+
+ // Set the DMA channel related parameters
+ // Channel Priority is '0' - Lowest Priority
+ // Cleaning DMA Channel registers at the end of the command is enabled
+ // Reloading initial register values at the end of the command is disabled
+ // STATUS_DONE status flag is asserted at the end of the command.
+ // Automatic pause request at the end of the command is disabled
+ // Maximum source and destination burst lengths sent by the DMA are 15+1=16 (Can be limited by FIFO size)
+ AdaChannelSettingsType ch_settings = {
+ .CHPRIO = 0,
+ .CLEARCMD = 1,
+ .REGRELOADTYPE = RELOAD_DISABLED,
+ .DONETYPE = DONETYPE_EOF_CMD,
+ .DONEPAUSEEN = 0,
+ .SRCMAXBURSTLEN = 15,
+ .DESMAXBURSTLEN = 15
+ };
+ AdaChannelSettingsType ch_settings_no_burst = {
+ .CHPRIO = 0,
+ .CLEARCMD = 1,
+ .REGRELOADTYPE = RELOAD_DISABLED,
+ .DONETYPE = DONETYPE_EOF_CMD,
+ .DONEPAUSEEN = 0,
+ .SRCMAXBURSTLEN = 0,
+ .DESMAXBURSTLEN = 0
+ };
+
+ // Set the attributes of the read AXI transactions sent by the DMA
+ // These settings affects the ARINNER[3:0], AWINNER[3:0], ARCACHE[3:0], AWCACHE[3:0] and AxDOMAIN[1:0] attributes
+ // of the AXI transactions
+ // This command uses Normal memory, Non-Cacheable, Bufferable, System-shareable AXI attributes
+ // ARINNER[3:0] = 4'b0011, AWINNER[3:0] = 4'b0011, ARCACHE[3:0] = 4'b0011, AWCACHE[3:0] = 4'b0011, AxDOMAIN[1:0] = 2'b11
+ // More information about the AXI attribute settings can be found in the TRM
+ // The command uses non-secure, non-privileged AXI read transactions
+ AdaChannelSrcAttrType ch_srcattr = {
+ .SRCMEMATTRLO = 4,
+ .SRCMEMATTRHI = 4,
+ .SRCSHAREATTR = 0,
+ .SRCNONSECATTR = 1,
+ .SRCPRIVATTR = 0
+ };
+
+ // Set the attributes of the write AXI transactions sent by the DMA
+ // These settings affects the ARINNER[3:0], AWINNER[3:0], ARCACHE[3:0], AWCACHE[3:0] and AxDOMAIN[1:0] attributes
+ // of the AXI transactions
+ // This command uses Normal memory, Non-Cacheable, Bufferable, System-shareable AXI attributes
+ // ARINNER[3:0] = 4'b0011, AWINNER[3:0] = 4'b0011, ARCACHE[3:0] = 4'b0011, AWCACHE[3:0] = 4'b0011, AxDOMAIN[1:0] = 2'b11
+ // More information about the AXI attribute settings can be found in the TRM
+ // The command uses non-secure, non-privileged AXI write transactions
+ AdaChannelDesAttrType ch_desattr = {
+ .DESMEMATTRLO = 4,
+ .DESMEMATTRHI = 4,
+ .DESSHAREATTR = 0,
+ .DESNONSECATTR = 1,
+ .DESPRIVATTR = 0
+ };
+
+ // Set the attributes of the read AXI transactions used for the command link related transfers
+ AdaChannelLinkAttrType ch_linkattr = {
+ .LINKMEMATTRLO = 4,
+ .LINKMEMATTRHI = 4,
+ .LINKSHAREATTR = 0
+ };
+
+
+ AdaBaseCommandType str_command_base_0 = {
+ .SRCADDR = COPY_ADDR_SRC_0, // Read from M0 interface
+ .DESADDR = COPY_ADDR_DST_0, // Write to M1 interface
+ .SRCXSIZE = DATA_SIZE,
+ .DESXSIZE = DATA_SIZE,
+ .TRANSIZE = BITS_32
+ };
+ AdaBaseCommandType str_command_base_1 = {
+ .SRCADDR = COPY_ADDR_SRC_1, // Read from M0 interface
+ .DESADDR = COPY_ADDR_DST_1, // Write to M1 interface
+ .SRCXSIZE = DATA_SIZE,
+ .DESXSIZE = DATA_SIZE,
+ .TRANSIZE = BITS_32
+ };
+ AdaBaseCommandType str_command_base_2 = {
+ .SRCADDR = COPY_ADDR_SRC_2, // Read from M0 interface
+ .DESADDR = COPY_ADDR_DST_2, // Write to M1 interface
+ .SRCXSIZE = DATA_SIZE,
+ .DESXSIZE = DATA_SIZE,
+ .TRANSIZE = BITS_32
+ };
+ // Set the increment of source and destination addresses
+ // The source and destination address increments are 1
+ Ada1DIncrCommandType command_1d_incr = {
+ .SRCXADDRINC = 1, // Autoincrement by transaction size
+ .DESXADDRINC = 1 // Autoincrement by transaction size
+ };
+
+ // Set the transfer types (2D and wrapping support)
+ // The transaction type is 1D basic transfer
+ AdaWrapCommandType command_1d_wrap = {
+ .FILLVAL = 0,
+ .XTYPE = OPTYPE_CONTINUE,
+ .YTYPE = OPTYPE_DISABLE
+ };
+
+ // Enable/disable the interupts of the channel
+ // Error and done interrupts are enabled
+ AdaIrqEnType ch_irqs = {
+ .INTREN_DONE = 1,
+ .INTREN_ERR = 1,
+ .INTREN_DISABLED = 0,
+ .INTREN_STOPPED = 0
+ };
+
+ // Set stream type
+ // Both stream in and out interfaces are used
+ AdaStreamType command_stream = {
+ .STREAMTYPE = IN_AND_OUT
+ } ;
+
+
+ if(dma350_detect()!=0){
+ return 0;
+ }
+
+ //Initialize TCM
+ printf("Initialize SRAM... ");
+ actual_addr = str_command_base_0.SRCADDR;
+ unsigned int test_data[str_command_base_0.SRCXSIZE];
+ int j;
+ for(j = 0; j < 64; j++){
+ test_data[j] = j;
+ address_test_write(actual_addr,test_data[j]);
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+ actual_addr = str_command_base_1.SRCADDR;
+ for(j = 0; j < 64; j++){
+ address_test_write(actual_addr,test_data[j]);
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+ actual_addr = str_command_base_2.SRCADDR;
+ for(j = 0; j < 64; j++){
+ address_test_write(actual_addr,test_data[j]);
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+ printf("done\n");
+
+
+ //Get the configuration information
+ ch_num = AdaGetChNum(SECURE);
+ trig_in_num = AdaGetTrigInNum(SECURE);
+ trig_out_num = AdaGetTrigOutNum(SECURE);
+
+ //Display the config parameters read
+ printf("Number of DMA channels: %d \n", ch_num);
+ printf("Number of DMA trigger inputs: %d \n", trig_in_num);
+ printf("Number of DMA trigger outputs: %d \n", trig_out_num);
+
+
+ printf("---STARTING Stream interface tests---\n");
+ __enable_irq();
+ for (uint32_t ch=0; ch < ch_num; ch++) {
+ current_channel=ch;
+ //
+ // Write all settings to the DMA registers
+ AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
+ Ada1DIncrCommand(str_command_base_0, command_1d_incr, ch, SECURE);
+ AdaStreamInit(command_stream, ch, SECURE);
+ AdaStreamEnable(1 ,ch, SECURE);
+ AdaSetIntEn(ch_irqs, ch, SECURE);
+
+
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+
+ printf("DMA %d configured. Starting the transfer.\n", ch);
+
+
+ // Start DMA operation and wait for done IRQ
+ AdaEnable(ch, SECURE);
+ __WFI();
+ printf("Return from interrupt\n");
+
+ //AdaClearChDone(ch, SECURE);
+ printf("DMA transfer finished\n");
+
+ if (check_destination(str_command_base_0.DESADDR)!=0){
+ errors++;
+ }
+ else{
+ printf("Passed\n");
+ }
+
+ initialise_destination(str_command_base_0.DESADDR);
+ // Disable channel and stream
+ AdaDisable(ch, SECURE);
+ AdaStreamEnable(0 ,ch, SECURE);
+ }
+
+
+
+
+ NVIC_DisableIRQ(DMA_IRQn);
+ __disable_irq();
+
+ if(errors!=0){
+ printf("\n** TEST FAILED **, Error code = (0x%x)\n",errors);
+ } else {
+ printf ("\n** TEST PASSED **\n");
+ }
+
+ UartEndSimulation();
+ return 0;
+}
+
+// Setup all components in the system
+void SystemInitialization(void){
+ // Initialize the system. For example clock gating, PPU, SAU, security components, peripherals etc.
+ // Note: This function should setup all system components
+ // UART init
+ UartStdOutInit();
+
+ // Test banner message and revision number
+ puts("\nCortex Microcontroller System Design Kit - DMA Test - revision $Revision: 371321 $\n");
+}
+
+uint8_t dma350_detect(void)
+{
+ uint8_t result;
+ int volatile rdata;
+ unsigned const int dma350_iidr = 0x3a00043b;
+ puts("Detect if DMA350 controller is present...");
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ rdata = address_test_read(ADA_DMA_S_BASE+0xFC8);
+ hardfault_expected = 0;
+ result = hardfault_occurred ? 1 : (rdata!=dma350_iidr);
+ if (result!=0) {
+ puts("** TEST SKIPPED ** DMA controller is not present.\n");
+ UartEndSimulation();
+ }
+ return(result);
+}
+
+void initialise_destination(unsigned int actual_addr)
+{
+ int j;
+ for(j = 0; j < 64; j++){
+ address_test_write(actual_addr,0);
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+}
+
+uint8_t check_destination(unsigned int actual_addr)
+{
+ uint32_t mismatches=0;
+ uint32_t value;
+ int j;
+ for(j = 0; j < 64; j++){
+ if (address_test_read(actual_addr)!=j)
+ {
+ mismatches++;
+ }
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+ return mismatches;
+}
+
+#if defined ( __CC_ARM )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ STR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ BX LR
+}
+
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+ __asm(" str r1,[r0]\n"
+ " dsb \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+/* Test function for read */
+#if defined ( __CC_ARM )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+ LDR R1,[R0]
+ DSB ; Ensure bus fault occurred before leaving this subroutine
+ MOVS R0, R1
+ BX LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int address_test_read(unsigned int addr)
+{
+ __asm(" ldr r1,[r0]\n"
+ " dsb \n"
+ " movs r0, r1 \n"
+ " bx lr \n"
+ );
+}
+#endif
+
+// Function for the Channel interrupt handlers
+void DMAClearChIrq(uint32_t ch) {
+ // Check the source of the interrupt and clear interrupts
+ AdaStatType ST = AdaReadStatus(ch, SECURE);
+ if (ST.STAT_DONE == 1) {
+ AdaClearChDone(ch, SECURE);
+ } else if (ST.STAT_ERR == 1) {
+ AdaClearChError(ch, SECURE);
+ } else if (ST.STAT_DISABLED == 1) {
+ AdaClearChDisabled(ch, SECURE);
+ } else if (ST.STAT_STOPPED == 1) {
+ AdaClearChStopped(ch, SECURE);
+ } else {
+ printf("Unknown IRQ on CH%d!\n", ch);
+ }
+}
+
+void DMA_Handler(void){
+ __disable_irq();
+ DMAClearChIrq(current_channel);
+ dma_done_irq_occurred++;
+ __enable_irq();
+ return;
+}
+
+#if defined ( __CC_ARM )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1
+ BEQ stacking_used_MSP
+ MRS R0, PSP ; // first parameter - stacking was using PSP
+ B get_LR_and_branch
+stacking_used_MSP
+ MRS R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+ MOV R1, LR ; // second parameter is LR current value
+ LDR R2,=__cpp(HardFault_Handler_c)
+ BX R2
+ ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+ __asm(" movs r0,#4\n"
+ " mov r1,lr\n"
+ " tst r0,r1\n"
+ " beq stacking_used_MSP\n"
+ " mrs r0,psp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ "stacking_used_MSP:\n"
+ " mrs r0,msp\n" /* first parameter - stacking was using PSP */
+ " ldr r1,=HardFault_Handler_c \n"
+ " bx r1\n"
+ ".pool\n" );
+}
+
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+ unsigned int stacked_pc;
+ unsigned int stacked_r0;
+ hardfault_occurred++;
+ puts ("[Hard Fault Handler]");
+ if (hardfault_expected==0) {
+ puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+ printf(" - Stacked PC : 0x%x\n", stacked_pc);
+ /* Modify R0 to a valid address */
+ hardfault_args[0] = (unsigned long) &temp_data;
+
+ return;
+}
+
+void delay(uint32_t t)
+{
+ int i;
+ for (i=0;i<t;i++){
+ __ISB();
+ }
+ return;
+}
diff --git a/testcodes/dma350_stream_tests/dma350_stream_tests.hex b/testcodes/dma350_stream_tests/dma350_stream_tests.hex
new file mode 100644
index 0000000..699138f
--- /dev/null
+++ b/testcodes/dma350_stream_tests/dma350_stream_tests.hex
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diff --git a/testcodes/dma350_stream_tests/makefile b/testcodes/dma350_stream_tests/makefile
new file mode 100644
index 0000000..8735e72
--- /dev/null
+++ b/testcodes/dma350_stream_tests/makefile
@@ -0,0 +1,285 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+TARGET = arm-none-eabi
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+GENERIC_DIR = ../generic
+
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = dma350_stream_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),ds6)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=Cortex-M0plus
+ else
+ CPU_TYPE = -mcpu=Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+ifeq ($(TOOL_CHAIN),ds6)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# Configuration ID values
+GENERIC_FILE = $(GENERIC_DIR)/config_id.h
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ifeq ($(TOOL_CHAIN),ds6)
+ ARM_TARGET = --target=arm-$(TARGET)
+ CC_TOOL = armclang -O1
+ ASM_TOOL = armclang -masm=armasm $(ARM_TARGET) -c
+else
+ CC_TOOL = armcc -O3
+ ASM_TOOL = armasm
+ ARM_TARGET = -Otime --c99
+endif
+
+ARM_CC_OPTIONS = $(ARM_TARGET) -c -g -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
+ARM_CC_OPTIONS_DRIVER = $(ARM_TARGET) -c -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = $(TARGET)-gcc
+GNU_OBJDUMP = $(TARGET)-objdump
+GNU_OBJCOPY = $(TARGET)-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+all_ds6 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(GENERIC_FILE) $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+dma_350_driver.o : $(SOFTWARE_DIR)/drivers/dma_350_command_lib.c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS_DRIVER) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ $(ASM_TOOL) $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o dma_350_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o dma_350_driver.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/drivers/dma_350_command_lib.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR)\
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/drivers \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/testcodes/excluded_tests.txt b/testcodes/excluded_tests.txt
index 3183be7..cf16029 100644
--- a/testcodes/excluded_tests.txt
+++ b/testcodes/excluded_tests.txt
@@ -1,2 +1,3 @@
rtx_demo
-gpio_tests
\ No newline at end of file
+gpio_tests
+dma350_stream_tests
\ No newline at end of file
--
GitLab