diff --git a/.gitmodules b/.gitmodules
index 21aa4e7d57437acffa8a84786621f5640a68077d..968fe3882123a1162f24f54356b604743faed026 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -16,3 +16,6 @@
[submodule "nanosoc/synopsys_28nm_slm_integration"]
path = nanosoc/synopsys_28nm_slm_integration
url = https://git.soton.ac.uk/soclabs/synopsys_28nm_slm_integration.git
+[submodule "nanosoc/ahb_qspi"]
+ path = nanosoc/ahb_qspi
+ url = https://git.soton.ac.uk/soclabs/ahb_qspi.git
diff --git a/flist/nanosoc.flist b/flist/nanosoc.flist
index 56ca5e4252e23972781828a332a65eabec8bc30a..3f8e75373f835945381994cd97d59e6faaff30ef 100644
--- a/flist/nanosoc.flist
+++ b/flist/nanosoc.flist
@@ -39,3 +39,6 @@ $(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// DMAC IP (better included at top level configuration)
//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
//-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
+
+// AHB QSPI
+-f $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI.flist
diff --git a/flist/nanosoc_FPGA.flist b/flist/nanosoc_FPGA.flist
index 3d54da0e5c88a029483dfd14bf64b5439ed4476a..aed3f5d8961fca8c8c6f5c181400ad2cdae832b7 100644
--- a/flist/nanosoc_FPGA.flist
+++ b/flist/nanosoc_FPGA.flist
@@ -37,3 +37,8 @@ $(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// DMAC IP (better included at top level configuration)
//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
//-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
+
+// AHB QSPI
+-f $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI.flist
+$(SOCLABS_AHB_QSPI_DIR)/logical/cache_models/generic/cache_ram.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/testbench/execution_tb/verilog/p_flash_cache_f0_sp_ram.v
diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist
index fc6b47ca1746d05c03ee756a10b9e798ba39c7d9..b58920d32f80b490806f361afd6319ce61856887 100644
--- a/flist/nanosoc_ip.flist
+++ b/flist/nanosoc_ip.flist
@@ -42,6 +42,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_re
// NanoSoC Regions - CPU Memories
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/flash_0/verilog/nanosoc_region_flash_0.v
// NanoSoC Regions - Expansion Regions
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
@@ -54,6 +55,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctr
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_qspi_apb_ss.v
// NanoSoC Regions - SysTable Region
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
diff --git a/flist/nanosoc_qs.flist b/flist/nanosoc_qs.flist
index bd1f5ceafb842e22c9c08b79c39c92bfbbcf49db..e66af1bfca332955031733a01ada8f1206cf771f 100644
--- a/flist/nanosoc_qs.flist
+++ b/flist/nanosoc_qs.flist
@@ -33,3 +33,6 @@ $(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// Debug IP
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
+
+// AHB QSPI
+-f $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI.flist
diff --git a/flist/nanosoc_vip.flist b/flist/nanosoc_vip.flist
index f610d0842edee329fa343f985a938e2f6f2a684d..74d9fed87d750095000828f7e365a8d893cdc888 100644
--- a/flist/nanosoc_vip.flist
+++ b/flist/nanosoc_vip.flist
@@ -29,3 +29,9 @@ $(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_datafile.v
+
+// AHB Qspi Components
+-f $(SOCLABS_AHB_QSPI_DIR)/flist/VIP/ahb_QSPI_VIP.flist
+
+$(SOCLABS_AHB_QSPI_DIR)/logical/cache_models/generic/cache_ram.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/testbench/execution_tb/verilog/p_flash_cache_f0_sp_ram.v
diff --git a/flows/makefile.regression b/flows/makefile.regression
index d62b6e5bdad2e1ca44682c473044a612cbdece3d..3fd923929d47262bcd99ce017a256d16edd065a7 100644
--- a/flows/makefile.regression
+++ b/flows/makefile.regression
@@ -13,7 +13,7 @@
PARALLEL_TESTS = 4
# Regression Simulation Timeout
-TIMEOUT = 40m
+TIMEOUT = 60m
# Create a Directory to Run a Regression in
$(eval REGRESSION_NAME =$(shell date +%Y_%m_%d_%H_%M_%S))
diff --git a/flows/makefile.software b/flows/makefile.software
index 6447521c6a963883c99a663445dde4adb780ed02..2fda512cfe5e57d180691d82455826cabaa11e4b 100644
--- a/flows/makefile.software
+++ b/flows/makefile.software
@@ -23,7 +23,7 @@ SW_MAKE_OPTIONS = CPU_PRODUCT=CORTEX_M0 TOOL_CHAIN=$(TOOL_CHAIN)
# Bootrom Parameters:
# Boot Loader image
BOOTLOADER ?= bootloader
-BOOTROM_ADDRW ?= 8
+BOOTROM_ADDRW ?= 9
BOOTROM_HEX ?= $(SOCLABS_NANOSOC_TECH_DIR)/testcodes/bootloader/$(BOOTLOADER).hex
BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom
diff --git a/fpga/targets/pynq_z2/fpga_pinmap.xdc b/fpga/targets/pynq_z2/fpga_pinmap.xdc
index 1dc9791544de0f085c0feb2d0424d88c2ca81946..3eda9ded20ad541004c76051f52140c8eb889179 100644
--- a/fpga/targets/pynq_z2/fpga_pinmap.xdc
+++ b/fpga/targets/pynq_z2/fpga_pinmap.xdc
@@ -32,4 +32,12 @@ set_property PULLUP true [get_ports PMOD0_5]
set_property PULLUP true [get_ports PMOD0_6]
set_property PULLUP true [get_ports PMOD0_7]
+set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports QSPI_nCS_0]
+set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[0]}]
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[1]}]
+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports QSPI_SCLK_0]
+set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports RESET];
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[2]}]
+set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[3]}]
+
##set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF]
diff --git a/fpga/targets/pynq_z2/nanosoc_design_wrapper.v b/fpga/targets/pynq_z2/nanosoc_design_wrapper.v
index 742a7c14b6cca8eaa83c2ef241cce1c3c879f8bf..61966656f651c44cff01c23c1e0a0669c1201b66 100644
--- a/fpga/targets/pynq_z2/nanosoc_design_wrapper.v
+++ b/fpga/targets/pynq_z2/nanosoc_design_wrapper.v
@@ -17,7 +17,11 @@ module nanosoc_design_wrapper
PMOD0_4,
PMOD0_5,
PMOD0_6,
- PMOD0_7
+ PMOD0_7,
+
+ QSPI_IO_0,
+ QSPI_SCLK_0,
+ QSPI_nCS_0
);
// PMOD1_0,
// PMOD1_1,
@@ -38,14 +42,10 @@ module nanosoc_design_wrapper
inout wire PMOD0_5;
inout wire PMOD0_6;
inout wire PMOD0_7;
-// inout wire PMOD1_0;
-// inout wire PMOD1_1;
-// inout wire PMOD1_2;
-// inout wire PMOD1_3;
-// inout wire PMOD1_4;
-// inout wire PMOD1_5;
-// inout wire PMOD1_6;
-// inout wire PMOD1_7;
+
+ inout wire [3:0] QSPI_IO_0;
+ output wire QSPI_SCLK_0;
+ output wire QSPI_nCS_0;
// input wire [3:0]dip_switch_4bits_tri_i;
// output wire [3:0]led_4bits_tri_o;
@@ -94,10 +94,60 @@ module nanosoc_design_wrapper
// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+ wire [3:0] qspi_io_i;
+ wire [3:0] qspi_io_o;
+ wire [3:0] qspi_io_e;
+ wire qspi_sclk;
+ wire qspi_ncs;
+
+
+ IOBUF QSPI_io0_iobuf(
+ .I(qspi_io_o[0]),
+ .IO(QSPI_IO_0[0]),
+ .O(qspi_io_i[0]),
+ .T(~qspi_io_e[0])
+ );
+ IOBUF QSPI_io1_iobuf(
+ .I(qspi_io_o[1]),
+ .IO(QSPI_IO_0[1]),
+ .O(qspi_io_i[1]),
+ .T(~qspi_io_e[1])
+ );
+ IOBUF QSPI_io2_iobuf(
+ .I(qspi_io_o[2]),
+ .IO(QSPI_IO_0[2]),
+ .O(qspi_io_i[2]),
+ .T(~qspi_io_e[2])
+ );
+ IOBUF QSPI_io3_iobuf(
+ .I(qspi_io_o[3]),
+ .IO(QSPI_IO_0[3]),
+ .O(qspi_io_i[3]),
+ .T(~qspi_io_e[3])
+ );
+ IOBUF QSPI_sclk_iobuf(
+ .I(qspi_sclk),
+ .IO(QSPI_SCLK_0),
+ .O(),
+ .T(1'b0)
+ );
+ IOBUF QSPI_ncs_iobuf(
+ .I(qspi_ncs),
+ .IO(QSPI_nCS_0),
+ .O(),
+ .T(1'b0)
+ );
+
+
nanosoc_design nanosoc_design_i
(.pmoda_tri_i(PMOD0_tri_i),
.pmoda_tri_o(PMOD0_tri_o),
- .pmoda_tri_z(PMOD0_tri_z)//,
+ .pmoda_tri_z(PMOD0_tri_z),
+ .qspi_io_i_0(qspi_io_i),
+ .qspi_io_o_0(qspi_io_o),
+ .qspi_io_e_0(qspi_io_e),
+ .qspi_sclk_0(qspi_sclk),
+ .qspi_ncs_0(qspi_ncs)
// .PMOD1_tri_i(PMOD1_tri_i),
// .PMOD1_tri_o(PMOD1_tri_o),
// .PMOD1_tri_z(PMOD1_tri_z),
diff --git a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
index 5b6771df2525f2742951c304a0c719378bfee601..ab841c8aa720571da45592d7c976327bd73ea48f 100644
--- a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
@@ -745,6 +745,12 @@ proc create_root_design { parentCell } {
set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+ set qspi_io_i_0 [ create_bd_port -dir I -from 3 -to 0 qspi_io_i_0]
+ set qspi_io_o_0 [ create_bd_port -dir O -from 3 -to 0 qspi_io_o_0]
+ set qspi_io_e_0 [ create_bd_port -dir O -from 3 -to 0 qspi_io_e_0]
+ set qspi_sclk_0 [ create_bd_port -dir O -from 0 -to 0 qspi_sclk_0]
+ set qspi_ncs_0 [ create_bd_port -dir O -from 0 -to 0 qspi_ncs_0]
+
# Create instance: cmsdk_socket
create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
@@ -864,6 +870,11 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins nanosoc_chip_0/clk_i]
+ connect_bd_net -net qspi_io_i_1 [get_bd_pins nanosoc_chip_0/qspi_io_i] [get_bd_ports qspi_io_i_0]
+ connect_bd_net -net qspi_io_o_1 [get_bd_pins nanosoc_chip_0/qspi_io_o] [get_bd_ports qspi_io_o_0]
+ connect_bd_net -net qspi_io_e_1 [get_bd_pins nanosoc_chip_0/qspi_io_e] [get_bd_ports qspi_io_e_0]
+ connect_bd_net -net qspi_sclk_1 [get_bd_pins nanosoc_chip_0/qspi_sclk] [get_bd_ports qspi_sclk_0]
+ connect_bd_net -net qspi_ncs_1 [get_bd_pins nanosoc_chip_0/qspi_ncs] [get_bd_ports qspi_ncs_0]
# Create address segments
assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/fpga/targets/pynq_zcu104/nanosoc_design_wrapper.v b/fpga/targets/pynq_zcu104/nanosoc_design_wrapper.v
index 742a7c14b6cca8eaa83c2ef241cce1c3c879f8bf..19dd346f5cde0f076559953fd5f1da33b7345515 100644
--- a/fpga/targets/pynq_zcu104/nanosoc_design_wrapper.v
+++ b/fpga/targets/pynq_zcu104/nanosoc_design_wrapper.v
@@ -93,11 +93,23 @@ module nanosoc_design_wrapper
// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+ wire [3:0] qspi_io_i;
+ wire [3:0] qspi_io_o;
+ wire [3:0] qspi_io_e;
+ wire qspi_sclk;
+ wire qspi_ncs;
+ assign qspi_io_i=4'hF;
+
nanosoc_design nanosoc_design_i
(.pmoda_tri_i(PMOD0_tri_i),
.pmoda_tri_o(PMOD0_tri_o),
- .pmoda_tri_z(PMOD0_tri_z)//,
+ .pmoda_tri_z(PMOD0_tri_z),
+ .qspi_io_i_0(qspi_io_i),
+ .qspi_io_o_0(qspi_io_o),
+ .qspi_io_e_0(qspi_io_e),
+ .qspi_sclk_0(qspi_sclk),
+ .qspi_ncs_0(qspi_ncs)
// .PMOD1_tri_i(PMOD1_tri_i),
// .PMOD1_tri_o(PMOD1_tri_o),
// .PMOD1_tri_z(PMOD1_tri_z),
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
index e11d1a3b2d3163c7ce02f80b20c77e398e2c36be..84cf9a9c04112eecaaaf989a03d24fb1da8bb834 100644
--- a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
@@ -741,6 +741,12 @@ proc create_root_design { parentCell } {
set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ set qspi_io_i_0 [ create_bd_port -dir I -from 3 -to 0 qspi_io_i_0]
+ set qspi_io_o_0 [ create_bd_port -dir O -from 3 -to 0 qspi_io_o_0]
+ set qspi_io_e_0 [ create_bd_port -dir O -from 3 -to 0 qspi_io_e_0]
+ set qspi_sclk_0 [ create_bd_port -dir O -from 0 -to 0 qspi_sclk_0]
+ set qspi_ncs_0 [ create_bd_port -dir O -from 0 -to 0 qspi_ncs_0]
# Create instance: cmsdk_socket
create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
@@ -1788,6 +1794,11 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
+ connect_bd_net -net qspi_io_i_1 [get_bd_pins nanosoc_chip_0/qspi_io_i] [get_bd_ports qspi_io_i_0]
+ connect_bd_net -net qspi_io_o_1 [get_bd_pins nanosoc_chip_0/qspi_io_o] [get_bd_ports qspi_io_o_0]
+ connect_bd_net -net qspi_io_e_1 [get_bd_pins nanosoc_chip_0/qspi_io_e] [get_bd_ports qspi_io_e_0]
+ connect_bd_net -net qspi_sclk_1 [get_bd_pins nanosoc_chip_0/qspi_sclk] [get_bd_ports qspi_sclk_0]
+ connect_bd_net -net qspi_ncs_1 [get_bd_pins nanosoc_chip_0/qspi_ncs] [get_bd_ports qspi_ncs_0]
# Create address segments
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl
index e11d1a3b2d3163c7ce02f80b20c77e398e2c36be..655abc1d3fdd1838e7ebc79382747520e2f43d20 100644
--- a/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl
@@ -742,6 +742,12 @@ proc create_root_design { parentCell } {
set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+ set qspi_io_i_0 [ create_bd_port -dir I -from 3 -to 0 qspi_io_i_0]
+ set qspi_io_o_0 [ create_bd_port -dir O -from 3 -to 0 qspi_io_o_0]
+ set qspi_io_e_0 [ create_bd_port -dir O -from 3 -to 0 qspi_io_e_0]
+ set qspi_sclk_0 [ create_bd_port -dir O -from 0 -to 0 qspi_sclk_0]
+ set qspi_ncs_0 [ create_bd_port -dir O -from 0 -to 0 qspi_ncs_0]
+
# Create instance: cmsdk_socket
create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
@@ -1788,6 +1794,11 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
+ connect_bd_net -net qspi_io_i_1 [get_bd_pins nanosoc_chip_0/qspi_io_i] [get_bd_ports qspi_io_i_0]
+ connect_bd_net -net qspi_io_o_1 [get_bd_pins nanosoc_chip_0/qspi_io_o] [get_bd_ports qspi_io_o_0]
+ connect_bd_net -net qspi_io_e_1 [get_bd_pins nanosoc_chip_0/qspi_io_e] [get_bd_ports qspi_io_e_0]
+ connect_bd_net -net qspi_sclk_1 [get_bd_pins nanosoc_chip_0/qspi_sclk] [get_bd_ports qspi_sclk_0]
+ connect_bd_net -net qspi_ncs_1 [get_bd_pins nanosoc_chip_0/qspi_ncs] [get_bd_ports qspi_ncs_0]
# Create address segments
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/nanosoc/ahb_qspi b/nanosoc/ahb_qspi
new file mode 160000
index 0000000000000000000000000000000000000000..32f89699e9e142bfd8bd267145c8710962d8d2ca
--- /dev/null
+++ b/nanosoc/ahb_qspi
@@ -0,0 +1 @@
+Subproject commit 32f89699e9e142bfd8bd267145c8710962d8d2ca
diff --git a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 12253d740a74707c81312d1585587d3ac1aa4eab..576eae18b21ecdf401cbc597bf88c894c947cfd7 100644
--- a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -51,7 +51,15 @@ module nanosoc_chip #(
output wire swdio_o,
output wire swdio_e,
output wire swdio_z,
- input wire swdclk_i // alternate test scan enable
+ input wire swdclk_i, // alternate test scan enable
+
+ // QSPI
+ output wire qspi_sclk,
+ output wire qspi_ncs,
+ output wire [3:0] qspi_io_o,
+ input wire [3:0] qspi_io_i,
+ output wire [3:0] qspi_io_e
+
);
//--------------------------
@@ -166,7 +174,14 @@ module nanosoc_chip #(
.P0_OUTEN(P0_OUTEN),
.P1_IN(P1_IN), //_MUX),
.P1_OUT(P1_OUT),
- .P1_OUTEN(P1_OUTEN)
+ .P1_OUTEN(P1_OUTEN),
+
+ .QSPI_SCLK(qspi_sclk),
+ .QSPI_nCS(qspi_ncs),
+ .QSPI_IO_o(qspi_io_o),
+ .QSPI_IO_i(qspi_io_i),
+ .QSPI_IO_e(qspi_io_e)
+
);
endmodule
diff --git a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
index e90a05005a4fd6c416c9ba88abc24b992e0e2758..21d8a1f8be947122f3c770bfe2ae4b79c616c352 100644
--- a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+++ b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
@@ -51,7 +51,11 @@ module nanosoc_chip_pads (
inout wire [15:0] P0,
inout wire [15:0] P1,
inout wire SWDIO,
- inout wire SWDCK);
+ inout wire SWDCK,
+ inout wire [3:0] QSPI_IO,
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS
+);
//------------------------------------
@@ -75,6 +79,12 @@ wire [15:0] pad_gpio_port1_i ;
wire [15:0] pad_gpio_port1_o ;
wire [15:0] pad_gpio_port1_e ;
wire [15:0] pad_gpio_port1_z ;
+wire pad_qspi_sclk;
+wire pad_qspi_ncs;
+wire [3:0] pad_qspi_io_o;
+wire [3:0] pad_qspi_io_i;
+wire [3:0] pad_qspi_io_e;
+
wire soc_nreset;
wire soc_diag_mode;
wire soc_diag_ctrl;
@@ -217,7 +227,12 @@ nanosoc_chip_cfg #(
.swdio_o (soc_swd_dio_o),
.swdio_e (soc_swd_dio_e),
.swdio_z (soc_swd_dio_z),
- .swdclk_i (pad_swdclk_i)
+ .swdclk_i (pad_swdclk_i),
+ .qspi_sclk (pad_qspi_sclk),
+ .qspi_ncs (pad_qspi_ncs),
+ .qspi_io_o (pad_qspi_io_o),
+ .qspi_io_i (pad_qspi_io_i),
+ .qspi_io_e (pad_qspi_io_e)
);
@@ -296,6 +311,50 @@ PAD_INOUT8MA_NOE uPAD_SWDCK_I (
.NOE (tiehi)
);
+PAD_INOUT8MA_NOE uPAD_QSPI_SCLK_o (
+ .PAD (QSPI_SCLK),
+ .O (pad_qspi_sclk),
+ .I (),
+ .NOE (tielo)
+ );
+
+PAD_INOUT8MA_NOE uPAD_QSPI_nCS_o (
+ .PAD (QSPI_nCS),
+ .O (pad_qspi_ncs),
+ .I (),
+ .NOE (tielo)
+ );
+
+
+// QSPI IO
+PAD_INOUT8MA_NOE uPAD_QSPI_IO_0 (
+ .PAD (QSPI_IO[0]),
+ .O (pad_qspi_io_o[0]),
+ .I (pad_qspi_io_i[0]),
+ .NOE (~pad_qspi_io_e[0])
+ );
+PAD_INOUT8MA_NOE uPAD_QSPI_IO_1 (
+ .PAD (QSPI_IO[1]),
+ .O (pad_qspi_io_o[1]),
+ .I (pad_qspi_io_i[1]),
+ .NOE (~pad_qspi_io_e[1])
+ );
+
+PAD_INOUT8MA_NOE uPAD_QSPI_IO_2 (
+ .PAD (QSPI_IO[2]),
+ .O (pad_qspi_io_o[2]),
+ .I (pad_qspi_io_i[2]),
+ .NOE (~pad_qspi_io_e[2])
+ );
+
+PAD_INOUT8MA_NOE uPAD_QSPI_IO_3 (
+ .PAD (QSPI_IO[3]),
+ .O (pad_qspi_io_o[3]),
+ .I (pad_qspi_io_i[3]),
+ .NOE (~pad_qspi_io_e[3])
+ );
+
+
// GPI.I Port 0 x 16
PAD_INOUT8MA_NOE uPAD_P0_00 (
diff --git a/nanosoc/nanosoc_regions/flash_0/verilog/nanosoc_region_flash_0.v b/nanosoc/nanosoc_regions/flash_0/verilog/nanosoc_region_flash_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..26c3f85e77520858f418343e89a4c5ee381d306c
--- /dev/null
+++ b/nanosoc/nanosoc_regions/flash_0/verilog/nanosoc_region_flash_0.v
@@ -0,0 +1,98 @@
+//-----------------------------------------------------------------------------
+// Nanosoc CPU Instruction Memory Region (IMEM) - SRAM
+// - Region Mapped to: 0x20000000-0x2fffffff
+// - Memory Exhibits Wrapping Behaviour
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_flash_0 #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32 // System Data Width
+)(
+ input wire HCLK,
+ input wire HRESETn,
+ input wire PCLK,
+ input wire PRESETn,
+ input wire SYS_RESETn,
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA,
+
+ // APB Signals
+ input wire [15:0] PADDR,
+ input wire [2:0] PPROT,
+ input wire PSEL,
+ input wire PENABLE,
+ input wire PWRITE,
+ input wire [31:0] PWDATA,
+ input wire [3:0] PSTRB,
+ output wire [31:0] PRDATA,
+ output wire PREADY,
+ output wire PSLVERR,
+
+ // QSPI Signals
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+ output wire [3:0] QSPI_IO_o,
+ input wire [3:0] QSPI_IO_i,
+ output wire [3:0] QSPI_IO_e
+
+);
+
+ top_ahb_qspi #(
+ .ADDR_W(SYS_ADDR_W),
+ .DATA_W(SYS_DATA_W)
+ ) u_imem_qspi (
+ .HCLK(HCLK),
+ .HRESETn(SYS_RESETn),
+ .PCLK(PCLK),
+ .PRESETn(SYS_RESETn),
+
+ .HADDR(HADDR),
+ .HTRANS(HTRANS),
+ .HWRITE(HWRITE),
+ .HSIZE(HSIZE),
+ .HBURST(3'b000),
+ .HPROT(HPROT),
+ .HWDATA(HWDATA),
+ .HSELx(HSEL),
+ .HRDATA(HRDATA),
+ .HREADY(HREADY),
+ .HREADYOUT(HREADYOUT),
+ .HRESP(HRESP),
+
+ .PADDR(PADDR),
+ .PPROT(PPROT),
+ .PSEL(PSEL),
+ .PENABLE(PENABLE),
+ .PWRITE(PWRITE),
+ .PWDATA(PWDATA),
+ .PSTRB(PSTRB),
+ .PRDATA(PRDATA),
+ .PREADY(PREADY),
+ .PSLVERR(PSLVERR),
+
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e)
+ );
+
+endmodule
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_qspi_apb_ss.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_qspi_apb_ss.v
new file mode 100644
index 0000000000000000000000000000000000000000..8fc3862707533dcc6ad89219a3277f2ac4a75d0d
--- /dev/null
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_qspi_apb_ss.v
@@ -0,0 +1,177 @@
+//-----------------------------------------------------------------------------
+// NanoSoC APB Subsystem adapted from Arm CMSDK APB Subsystem
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : APB sub system
+//-----------------------------------------------------------------------------
+module nanosoc_qspi_apb_ss #(
+ // Big endian - Add additional endian conversion logic to support big endian.
+ // (for ARM internal testing and evaluation of the processor in
+ // big endian configuration).
+ // 0 = little endian, 1 = big endian
+ //
+ // The example systems including this APB subsystem are designed as
+ // little endian. Most of the peripherals and memory system are
+ // little endian. This parameter is introduced to allows ARM to
+ // perform system level tests to verified behaviour of bus
+ // components in big endian configuration, and to allow designers
+ // to evaluate the processor in big endian configuration.
+ //
+ // Use of this parameter is not recommended for actual product
+ // development as this adds extra hardware. For big endian systems
+ // ideally the peripherals should be modified to use a big endian
+ // programmer's model.
+ parameter BE = 0)
+ (
+// --------------------------------------------------------------------------
+// Port Definitions
+// --------------------------------------------------------------------------
+ // AHB interface for AHB to APB bridge
+
+ input wire HCLK,
+ input wire HRESETn,
+
+ input wire HSEL,
+ input wire [15:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire HWRITE,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HREADY,
+ input wire [31:0] HWDATA,
+ output wire HREADYOUT,
+ output wire [31:0] HRDATA,
+ output wire HRESP,
+
+ input wire PCLK, // Peripheral clock
+ input wire PCLKG, // Gate PCLK for bus interface only
+ input wire PCLKEN, // Clock divider for AHB to APB bridge
+ input wire PRESETn, // APB reset
+
+ // APB Signals
+ input wire [15:0] PADDR,
+ input wire [2:0] PPROT,
+ input wire PSEL,
+ input wire PENABLE,
+ input wire PWRITE,
+ input wire [31:0] PWDATA,
+ input wire [3:0] PSTRB,
+ output wire [31:0] PRDATA,
+ output wire PREADY,
+ output wire PSLVERR,
+
+ output wire APBACTIVE
+);
+
+ // --------------------------------------------------------------------------
+ // Internal wires
+ // --------------------------------------------------------------------------
+
+ // endian handling
+ wire bigendian;
+ assign bigendian = (BE!=0) ? 1'b1 : 1'b0;
+
+ wire [31:0] hwdata_le; // Little endian write data
+ wire [31:0] hrdata_le; // Little endian read data
+ wire reg_be_swap_ctrl_en = HSEL & HTRANS[1] & HREADY & bigendian;
+ reg [1:0] reg_be_swap_ctrl; // registered byte swap control
+ wire [1:0] nxt_be_swap_ctrl; // next state of byte swap control
+
+ assign nxt_be_swap_ctrl[1] = bigendian & (HSIZE[1:0]==2'b10); // Swap upper and lower half word
+ assign nxt_be_swap_ctrl[0] = bigendian & (HSIZE[1:0]!=2'b00); // Swap byte within hafword
+
+ // Register byte swap control for data phase
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_be_swap_ctrl <= 2'b00;
+ else if (reg_be_swap_ctrl_en)
+ reg_be_swap_ctrl <= nxt_be_swap_ctrl;
+ end
+
+ // swap byte within half word
+ wire [31:0] hwdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
+ {HWDATA[23:16],HWDATA[31:24],HWDATA[7:0],HWDATA[15:8]}:
+ {HWDATA[31:24],HWDATA[23:16],HWDATA[15:8],HWDATA[7:0]};
+ // swap lower and upper half word
+ assign hwdata_le = (reg_be_swap_ctrl[1] & bigendian) ?
+ {hwdata_mux_1[15: 0],hwdata_mux_1[31:16]}:
+ {hwdata_mux_1[31:16],hwdata_mux_1[15:0]};
+ // swap byte within half word
+ wire [31:0] hrdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
+ {hrdata_le[23:16],hrdata_le[31:24],hrdata_le[ 7:0],hrdata_le[15:8]}:
+ {hrdata_le[31:24],hrdata_le[23:16],hrdata_le[15:8],hrdata_le[7:0]};
+ // swap lower and upper half word
+ assign HRDATA = (reg_be_swap_ctrl[1] & bigendian) ?
+ {hrdata_mux_1[15: 0],hrdata_mux_1[31:16]}:
+ {hrdata_mux_1[31:16],hrdata_mux_1[15:0]};
+
+ // AHB to APB bus bridge
+ cmsdk_ahb_to_apb
+ #(.ADDRWIDTH (16),
+ .REGISTER_RDATA (1),
+ .REGISTER_WDATA (0))
+ u_ahb_to_apb(
+ // AHB side
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL),
+ .HADDR (HADDR[15:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HPROT (HPROT),
+ .HWRITE (HWRITE),
+ .HREADY (HREADY),
+ .HWDATA (hwdata_le),
+
+ .HREADYOUT(HREADYOUT), // AHB Outputs
+ .HRDATA (hrdata_le),
+ .HRESP (HRESP),
+
+ .PADDR (PADDR[15:0]),
+ .PSEL (PSEL),
+ .PENABLE (PENABLE),
+ .PSTRB (PSTRB),
+ .PPROT (PPROT),
+ .PWRITE (PWRITE),
+ .PWDATA (PWDATA),
+
+ .APBACTIVE(APBACTIVE),
+ .PCLKEN (PCLKEN), // APB clock enable signal
+
+ .PRDATA (PRDATA),
+ .PREADY (PREADY),
+ .PSLVERR (PSLVERR)
+ );
+
+endmodule
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 46c146b2d2ba52fb95085460dc81ef87def5b1cd..39c9e0baa5bf23db24c024804a9c3e0ab45ed7e9 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -66,6 +66,18 @@ module nanosoc_region_sysio #(
input wire exp15_pready,
input wire exp15_pslverr,
+ // QSPI APB signals
+ output wire [15:0] QSPI_PADDR,
+ output wire [2:0] QSPI_PPROT,
+ output wire QSPI_PSEL,
+ output wire QSPI_PENABLE,
+ output wire QSPI_PWRITE,
+ output wire [31:0] QSPI_PWDATA,
+ output wire [3:0] QSPI_PSTRB,
+ input wire [31:0] QSPI_PRDATA,
+ input wire QSPI_PREADY,
+ input wire QSPI_PSLVERR,
+
// CPU sideband signalling
output wire SYS_NMI, // watchdog_interrupt;
output wire [31:0] SYS_APB_IRQ, // apbsubsys_interrupt;
@@ -169,6 +181,11 @@ module nanosoc_region_sysio #(
wire [SYS_DATA_W-1:0] pvtsys_hrdata;
wire pvtsys_hresp;
+ wire qspi_hsel; // QSPI subsystem AHB interface signals
+ wire qspi_hreadyout;
+ wire [SYS_DATA_W-1:0] qspi_hrdata;
+ wire qspi_hresp;
+
// AHB address decode
nanosoc_sysio_decode #(
@@ -185,6 +202,7 @@ module nanosoc_region_sysio #(
.gpio0_hsel (gpio0_hsel),
.gpio1_hsel (gpio1_hsel),
.sysctrl_hsel (sysctrl_hsel),
+ .qspi_hsel (qspi_hsel),
`ifdef AMS_PERIPHERALS
.adcsys_hsel (adcsys_hsel),
`endif
@@ -212,7 +230,7 @@ module nanosoc_region_sysio #(
.PORT4_ENABLE (1), // Default
.PORT5_ENABLE (AMS_PERIPHERAL_PORT), // ADC Region
.PORT6_ENABLE (SNPS_PERIPHERAL_PORT), // Synopsys PVT monitoring region
- .PORT7_ENABLE (0),
+ .PORT7_ENABLE (1),
.PORT8_ENABLE (0),
.PORT9_ENABLE (0),
.DW (32)
@@ -248,10 +266,10 @@ module nanosoc_region_sysio #(
.HREADYOUT6 (pvtsys_hreadyout),
.HRESP6 (pvtsys_hresp),
.HRDATA6 (pvtsys_hrdata),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (defslv_hreadyout),
- .HRESP7 (defslv_hresp),
- .HRDATA7 (defslv_hrdata),
+ .HSEL7 (qspi_hsel), // Input Port 7
+ .HREADYOUT7 (qspi_hreadyout),
+ .HRESP7 (qspi_hresp),
+ .HRDATA7 (qspi_hrdata),
.HSEL8 (1'b0), // Input Port 8
.HREADYOUT8 (defslv_hreadyout),
.HRESP8 (defslv_hresp),
@@ -598,4 +616,37 @@ module nanosoc_region_sysio #(
.PRESETn(PRESETn) // APB reset
);
`endif
+
+nanosoc_qspi_apb_ss #(.BE(BE)) u_nanosoc_qspi_apb_ss(
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .HSEL(qspi_hsel),
+ .HADDR(HADDR[15:0]),
+ .HTRANS(HTRANS),
+ .HWRITE(HWRITE),
+ .HSIZE(HSIZE),
+ .HPROT(HPROT),
+ .HREADY(HREADY),
+ .HWDATA(HWDATA),
+ .HREADYOUT(qspi_hreadyout),
+ .HRDATA(qspi_hrdata),
+ .HRESP(qspi_hresp),
+
+ .PCLK(PCLK),
+ .PCLKG(PCLKG),
+ .PCLKEN(1'b1),
+ .PRESETn(PRESETn),
+ .PADDR(QSPI_PADDR),
+ .PPROT(QSPI_PPROT),
+ .PSEL(QSPI_PSEL),
+ .PENABLE(QSPI_PENABLE),
+ .PWRITE(QSPI_PWRITE),
+ .PWDATA(QSPI_PWDATA),
+ .PSTRB(QSPI_PSTRB),
+ .PRDATA(QSPI_PRDATA),
+ .PREADY(QSPI_PREADY),
+ .PSLVERR(QSPI_PSLVERR),
+ .APBACTIVE()
+);
+
endmodule
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
index 5cb63f01ad43dda6766228a50265b89ffa72511a..9c738fb116fdef451e4a67fb5ec6b8485d7e958a 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -49,7 +49,8 @@ module nanosoc_sysio_decode #(
parameter BASEADDR_GPIO1 = 32'h4001_1000,
// Sysctrl base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000,
- parameter BASEADDR_ADC = 32'h4002_0000
+ parameter BASEADDR_ADC = 32'h4002_0000,
+ parameter BASEADDR_QSPI_CTRL = 32'h4003_0000
)(
// System Address
input wire hsel,
@@ -60,6 +61,7 @@ module nanosoc_sysio_decode #(
output wire gpio0_hsel,
output wire gpio1_hsel,
output wire sysctrl_hsel,
+ output wire qspi_hsel,
`ifdef AMS_PERIPHERALS
output wire adcsys_hsel,
`endif
@@ -72,6 +74,8 @@ module nanosoc_sysio_decode #(
// 0x40010000 - 0x40010FFF : AHB peripherals (GPIO0)
// 0x40011000 - 0x40011FFF : AHB peripherals (GPIO1)
// 0x4001F000 - 0x4001FFFF : AHB peripherals (SYS control)
+ // 0x40020000 - 0x4002FFFF : AMS peripherals
+ // 0x40030000 -
// ----------------------------------------------------------
// Peripheral Selection decode logic
@@ -85,6 +89,9 @@ module nanosoc_sysio_decode #(
BASEADDR_GPIO1[31:12]); // 0x40011000
assign sysctrl_hsel = hsel & (haddr[31:12]==
BASEADDR_SYSCTRL[31:12]); // 0x4001F000
+ assign qspi_hsel = hsel & (haddr[31:16]==
+ BASEADDR_QSPI_CTRL[31:16]); // 0x4001F000
+
`ifdef AMS_PERIPHERALS
assign adcsys_hsel = hsel & (haddr[31:12]==
BASEADDR_ADC[31:12]); // 0x40020000
@@ -93,12 +100,12 @@ module nanosoc_sysio_decode #(
// Default slave decode logic
// ----------------------------------------------------------
`ifdef AMS_PERIPHERALS
- assign defslv_hsel = ~(apbsys_hsel |
+ assign defslv_hsel = ~(apbsys_hsel | qspi_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel | adcsys_hsel
);
`else
- assign defslv_hsel = ~(apbsys_hsel |
+ assign defslv_hsel = ~(apbsys_hsel | qspi_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel
);
diff --git a/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v b/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
index c4974707404039481a6856b4fafa6055f8ba068c..98120a368df2e0438bba54fd0c7f27f7f6399fd5 100644
--- a/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+++ b/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
@@ -104,7 +104,41 @@ module nanosoc_ss_cpu #(
output wire [31:0] IMEM_0_HRDATA, // Read data bus
output wire IMEM_0_HRESP, // Transfer response
output wire IMEM_0_HREADYOUT, // AHB ready out
-
+
+ // FLASH 0 AHB Lite port
+ input wire FLASH_0_HSEL, // Select
+ input wire [31:0] FLASH_0_HADDR, // Address bus
+ input wire [1:0] FLASH_0_HTRANS, // Transfer type
+ input wire FLASH_0_HWRITE, // Transfer direction
+ input wire [2:0] FLASH_0_HSIZE, // Transfer size
+ input wire [2:0] FLASH_0_HBURST, // Burst type
+ input wire [3:0] FLASH_0_HPROT, // Protection control
+ input wire [31:0] FLASH_0_HWDATA, // Write data
+ input wire FLASH_0_HMASTLOCK, // Locked Sequence
+ input wire FLASH_0_HREADY, // HREADY feedback
+ output wire [31:0] FLASH_0_HRDATA, // Read data bus
+ output wire FLASH_0_HRESP, // Transfer response
+ output wire FLASH_0_HREADYOUT, // AHB ready out
+
+ // IMEM QSPI APB Signals
+ input wire [15:0] QSPI_PADDR,
+ input wire [2:0] QSPI_PPROT,
+ input wire QSPI_PSEL,
+ input wire QSPI_PENABLE,
+ input wire QSPI_PWRITE,
+ input wire [31:0] QSPI_PWDATA,
+ input wire [3:0] QSPI_PSTRB,
+ output wire [31:0] QSPI_PRDATA,
+ output wire QSPI_PREADY,
+ output wire QSPI_PSLVERR,
+
+ // QSPI Signals
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+ output wire [3:0] QSPI_IO_o,
+ input wire [3:0] QSPI_IO_i,
+ output wire [3:0] QSPI_IO_e,
+
// DMEM 0 AHB Lite port
input wire DMEM_0_HSEL, // Select
input wire [31:0] DMEM_0_HADDR, // Address bus
@@ -261,7 +295,55 @@ module nanosoc_ss_cpu #(
.HRESP(IMEM_0_HRESP),
.HRDATA(IMEM_0_HRDATA)
);
-
+ // -----------------------------------------------
+ // CPU 0 Instruction Memory (FLASH) Region Instantiation
+ // -----------------------------------------------
+ nanosoc_region_flash_0 #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W)
+ ) u_region_flash_0 (
+ // Clock and Reset
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
+ .PCLK(SYS_HCLK),
+ .PRESETn(SYS_HRESETn),
+
+ .SYS_RESETn(SYS_SYSRESETn),
+ // AHB connection to Initiator
+ .HSEL(FLASH_0_HSEL),
+ .HADDR(FLASH_0_HADDR),
+ .HTRANS(FLASH_0_HTRANS),
+ .HSIZE(FLASH_0_HSIZE),
+ .HPROT(FLASH_0_HPROT),
+ .HWRITE(FLASH_0_HWRITE),
+ .HREADY(FLASH_0_HREADY),
+ .HWDATA(FLASH_0_HWDATA),
+
+ // Outputs
+ .HREADYOUT(FLASH_0_HREADYOUT),
+ .HRESP(FLASH_0_HRESP),
+ .HRDATA(FLASH_0_HRDATA),
+
+ // APB
+ .PADDR(QSPI_PADDR),
+ .PPROT(QSPI_PPROT),
+ .PSEL(QSPI_PSEL),
+ .PENABLE(QSPI_PENABLE),
+ .PWRITE(QSPI_PWRITE),
+ .PWDATA(QSPI_PWDATA),
+ .PSTRB(QSPI_PSTRB),
+ .PRDATA(QSPI_PRDATA),
+ .PREADY(QSPI_PREADY),
+ .PSLVERR(QSPI_PSLVERR),
+
+ // QSPI Signals
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e)
+ );
+
// ---------------------------------------
// CPU 0 Data Memory Region Instantiation
// ---------------------------------------
@@ -290,6 +372,6 @@ module nanosoc_ss_cpu #(
.HRESP(DMEM_0_HRESP),
.HRDATA(DMEM_0_HRDATA)
);
-
-
-endmodule
\ No newline at end of file
+
+
+endmodule
diff --git a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 2796e1e9e04cb533c38187bab5a640be4f5b025a..343ca69f37fcac82ee33b4b83f71832475757936 100644
--- a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -67,6 +67,18 @@ module nanosoc_ss_systemctrl #(
output wire SYSTABLE_HRESP, // AHB response
output wire SYSTABLE_HREADYOUT, // AHB ready out
+ // QSPI APB signals
+ output wire [15:0] QSPI_PADDR,
+ output wire [2:0] QSPI_PPROT,
+ output wire QSPI_PSEL,
+ output wire QSPI_PENABLE,
+ output wire QSPI_PWRITE,
+ output wire [31:0] QSPI_PWDATA,
+ output wire [3:0] QSPI_PSTRB,
+ input wire [31:0] QSPI_PRDATA,
+ input wire QSPI_PREADY,
+ input wire QSPI_PSLVERR,
+
// APB clocking control
output wire SYS_PCLK, // Peripheral clock
output wire SYS_PCLKG, // Gated Peripheral bus clock
@@ -308,6 +320,18 @@ module nanosoc_ss_systemctrl #(
.exp15_pready(DMAC_0_PREADY),
.exp15_pslverr(DMAC_0_PSLVERR),
+ // QSPI APB interface
+ .QSPI_PADDR(QSPI_PADDR),
+ .QSPI_PPROT(QSPI_PPROT),
+ .QSPI_PSEL(QSPI_PSEL),
+ .QSPI_PENABLE(QSPI_PENABLE),
+ .QSPI_PWRITE(QSPI_PWRITE),
+ .QSPI_PWDATA(QSPI_PWDATA),
+ .QSPI_PSTRB(QSPI_PSTRB),
+ .QSPI_PRDATA(QSPI_PRDATA),
+ .QSPI_PREADY(QSPI_PREADY),
+ .QSPI_PSLVERR(QSPI_PSLVERR),
+
// CPU sideband signaling
.SYS_NMI(SYS_NMI),
.SYS_APB_IRQ(SYS_APB_IRQ),
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index 05751f4b05ce7a59253092226a2907c97c8926cc..ced6aa7d7ceac8873ac13021d773cf0458e32480 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -22,7 +22,7 @@ module nanosoc_system #(
parameter APB_DATA_W = 32, // APB Peripheral Data Width
// Bootrom 0 Parameters
- parameter BOOTROM_ADDR_W = 10, // Size of Bootrom (Based on Address Width) - Default 1KB
+ parameter BOOTROM_ADDR_W = 11, // Size of Bootrom (Based on Address Width) - Default 2KB
// IMEM 0 Parameters
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
@@ -98,7 +98,14 @@ module nanosoc_system #(
output wire [15:0] P0_OUTEN, // GPIO 0 output enables
input wire [15:0] P1_IN, // GPIO 1 inputs
output wire [15:0] P1_OUT, // GPIO 1 outputs
- output wire [15:0] P1_OUTEN // GPIO 1 output enables
+ output wire [15:0] P1_OUTEN, // GPIO 1 output enables
+
+ // QSPI
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+ output wire [3:0] QSPI_IO_o,
+ input wire [3:0] QSPI_IO_i,
+ output wire [3:0] QSPI_IO_e
);
// system General purpose I/O ports - before NANOSOC specific mappings
@@ -268,7 +275,20 @@ module nanosoc_system #(
wire CPU_0_SLEEPING; // Processor status - sleeping
wire CPU_0_SLEEPDEEP; // Processor status - deep sleep
-
+
+ // QSPI APB port for FLASH
+ wire [15:0] QSPI_PADDR;
+ wire [2:0] QSPI_PPROT;
+ wire QSPI_PSEL;
+ wire QSPI_PENABLE;
+ wire QSPI_PWRITE;
+ wire [31:0] QSPI_PWDATA;
+ wire [3:0] QSPI_PSTRB;
+ wire [31:0] QSPI_PRDATA;
+ wire QSPI_PREADY;
+ wire QSPI_PSLVERR;
+
+
// Interrupt Wiring
//--------------------------
assign CPU_0_NMI = SYS_NMI;
@@ -277,10 +297,6 @@ module nanosoc_system #(
//--------------------------
assign CPU_0_PMUENABLE = SYS_PMUENABLE;
-// QSPI ROM controller here, plus APB control port
- assign EXTROM_0_HRDATA[31:0] = 32'hEEEEEEEE; // Read data bus
- assign EXTROM_0_HREADYOUT = 1'b1; // HREADY tied off always ready
- assign EXTROM_0_HRESP = 1'b0; // Transfer response no error
// Instantiate Subsystem
//--------------------------
@@ -367,7 +383,41 @@ module nanosoc_system #(
.IMEM_0_HREADY(IMEM_0_HREADY),
.IMEM_0_HRESP(IMEM_0_HRESP),
.IMEM_0_HREADYOUT(IMEM_0_HREADYOUT),
-
+
+ // FLASH 0 AHB Lite port
+ .FLASH_0_HSEL(EXTROM_0_HSEL),
+ .FLASH_0_HADDR(EXTROM_0_HADDR),
+ .FLASH_0_HTRANS(EXTROM_0_HTRANS),
+ .FLASH_0_HWRITE(EXTROM_0_HWRITE),
+ .FLASH_0_HSIZE(EXTROM_0_HSIZE),
+ .FLASH_0_HBURST(EXTROM_0_HBURST),
+ .FLASH_0_HPROT(EXTROM_0_HPROT),
+ .FLASH_0_HWDATA(EXTROM_0_HWDATA),
+ .FLASH_0_HMASTLOCK(EXTROM_0_HMASTLOCK),
+ .FLASH_0_HRDATA(EXTROM_0_HRDATA),
+ .FLASH_0_HREADY(EXTROM_0_HREADY),
+ .FLASH_0_HRESP(EXTROM_0_HRESP),
+ .FLASH_0_HREADYOUT(EXTROM_0_HREADYOUT),
+
+ // FLASH QSPI APB Signals
+ .QSPI_PADDR(QSPI_PADDR),
+ .QSPI_PPROT(QSPI_PPROT),
+ .QSPI_PSEL(QSPI_PSEL),
+ .QSPI_PENABLE(QSPI_PENABLE),
+ .QSPI_PWRITE(QSPI_PWRITE),
+ .QSPI_PWDATA(QSPI_PWDATA),
+ .QSPI_PSTRB(QSPI_PSTRB),
+ .QSPI_PRDATA(QSPI_PRDATA),
+ .QSPI_PREADY(QSPI_PREADY),
+ .QSPI_PSLVERR(QSPI_PSLVERR),
+
+ // IMEM QSPI Signals
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e),
+
// DMEM 0 AHB Lite port
.DMEM_0_HSEL(DMEM_0_HSEL),
.DMEM_0_HADDR(DMEM_0_HADDR),
@@ -1176,6 +1226,17 @@ wire EXT_DAT_TXD_TREADY ;
.SYSTABLE_HRESP(SYSTABLE_HRESP), // AHB response
.SYSTABLE_HREADYOUT(SYSTABLE_HREADYOUT), // AHB ready out
+ .QSPI_PADDR(QSPI_PADDR),
+ .QSPI_PPROT(QSPI_PPROT),
+ .QSPI_PSEL(QSPI_PSEL),
+ .QSPI_PENABLE(QSPI_PENABLE),
+ .QSPI_PWRITE(QSPI_PWRITE),
+ .QSPI_PWDATA(QSPI_PWDATA),
+ .QSPI_PSTRB(QSPI_PSTRB),
+ .QSPI_PRDATA(QSPI_PRDATA),
+ .QSPI_PREADY(QSPI_PREADY),
+ .QSPI_PSLVERR(QSPI_PSLVERR),
+
// APB clocking control
.SYS_PCLK(SYS_PCLK), // Peripheral clock
.SYS_PCLKG(SYS_PCLKG), // Gated Peripheral bus clock
diff --git a/nanosoc/synopsys_28nm_slm_integration b/nanosoc/synopsys_28nm_slm_integration
index e88b3d4335b8416b5d78322f45e099ac9a12a1d0..4c4e598a2982a099f5871df1df2515068a288eab 160000
--- a/nanosoc/synopsys_28nm_slm_integration
+++ b/nanosoc/synopsys_28nm_slm_integration
@@ -1 +1 @@
-Subproject commit e88b3d4335b8416b5d78322f45e099ac9a12a1d0
+Subproject commit 4c4e598a2982a099f5871df1df2515068a288eab
diff --git a/projbranch b/projbranch
index 035ef78c2223c9129606d1bdd3be39d26a4d82a0..447d68173874ae653d9b00d6a8f4abe72cc5081a 100644
--- a/projbranch
+++ b/projbranch
@@ -15,4 +15,5 @@ nanosoc/sldma230_tech: main
nanosoc/socdebug_tech: main
nanosoc/sldma350_tech: main
nanosoc/sl_ams_tech: main
-nanosoc/synopsys_28nm_slm_integration: main
\ No newline at end of file
+nanosoc/synopsys_28nm_slm_integration: main
+nanosoc/ahb_qspi: main
\ No newline at end of file
diff --git a/software/cmsis/Device/ARM/CMSDK_CM0/Include/SL_QSPI.h b/software/cmsis/Device/ARM/CMSDK_CM0/Include/SL_QSPI.h
new file mode 100644
index 0000000000000000000000000000000000000000..15de964aa775b72bc6974d8edf92af56581ab0ae
--- /dev/null
+++ b/software/cmsis/Device/ARM/CMSDK_CM0/Include/SL_QSPI.h
@@ -0,0 +1,81 @@
+#include <stdint.h>
+
+#define QSPI_BASEADDR 0x40030000UL
+#define CG092_BASEADDR 0x40031000UL
+
+
+typedef struct{
+ volatile uint32_t CTRL;
+ volatile uint32_t STATUS;
+ volatile uint32_t SPI_CMD;
+ volatile uint32_t SPI_ADDR;
+ volatile uint32_t READ_DATA[4];
+ volatile uint32_t WRITE_DATA[4];
+ volatile uint32_t AHB_CMD;
+} SL_AHB_QSPI_TypeDef;
+
+#define SL_AHB_QSPI_CTRL_QIO_Pos 0
+#define SL_AHB_QSPI_CTRL_QIO_Msk (0x1UL << SL_AHB_QSPI_CTRL_QIO_Pos)
+
+#define SL_AHB_QSPI_CTRL_XiP_Pos 8
+#define SL_AHB_QSPI_CTRL_XiP_Msk (0x1UL << SL_AHB_QSPI_CTRL_XiP_Pos)
+
+#define SL_AHB_QSPI_CTRL_Mode_Code_Pos 16
+#define SL_AHB_QSPI_CTRL_Mode_Code_Msk (0xFFUL << SL_AHB_QSPI_CTRL_Mode_Code_Pos)
+
+#define SL_AHB_QSPI_CTRL_Cont_Rd_Pos 24
+#define SL_AHB_QSPI_CTRL_Cont_Rd_Msk (0x1UL << SL_AHB_QSPI_CTRL_Cont_Rd_Pos)
+
+#define SL_AHB_QSPI_CTRL_No_CMD_Pos 25
+#define SL_AHB_QSPI_CTRL_No_CMD_Msk (0x1UL << SL_AHB_QSPI_CTRL_No_CMD_Pos)
+
+#define SL_AHB_QSPI_STATUS_Busy_Pos 0
+#define SL_AHB_QSPI_STATUS_Busy_Msk (0x1UL << SL_AHB_QSPI_STATUS_Busy_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_Pos 0
+#define SL_AHB_QSPI_SPI_CMD_Msk (0xFFUL << SL_AHB_QSPI_SPI_CMD_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_Enable_Pos 8
+#define SL_AHB_QSPI_SPI_CMD_Enable_Msk (0x1UL << SL_AHB_QSPI_SPI_CMD_Enable_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_Rd_Enable_Pos 9
+#define SL_AHB_QSPI_SPI_CMD_Rd_Enable_Msk (0x1UL << SL_AHB_QSPI_SPI_CMD_Rd_Enable_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_Wr_Enable_Pos 10
+#define SL_AHB_QSPI_SPI_CMD_Wr_Enable_Msk (0x1UL << SL_AHB_QSPI_SPI_CMD_Wr_Enable_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_Addr_Enable_Pos 11
+#define SL_AHB_QSPI_SPI_CMD_Addr_Enable_Msk (0x1UL << SL_AHB_QSPI_SPI_CMD_Addr_Enable_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_N_Dummy_Pos 12
+#define SL_AHB_QSPI_SPI_CMD_N_Dummy_Msk (0xFUL << SL_AHB_QSPI_SPI_CMD_N_Dummy_Pos)
+
+#define SL_AHB_QSPI_SPI_CMD_N_RW_Bytes_Pos 16
+#define SL_AHB_QSPI_SPI_CMD_N_RW_Bytes_Msk (0xFUL << SL_AHB_QSPI_SPI_CMD_N_RW_Bytes_Pos)
+
+
+typedef struct{
+ volatile uint32_t CCR;
+ volatile uint32_t SR;
+ volatile uint32_t IRQMASK;
+ volatile uint32_t IRQSTAT;
+ volatile uint32_t HWPARAMS;
+ volatile uint32_t CSHR;
+ volatile uint32_t CSMR;
+} CG092_TypeDef;
+
+
+#define SL_QSPI ((SL_AHB_QSPI_TypeDef *) QSPI_BASEADDR)
+#define CG092 ((CG092_TypeDef *) CG092_BASEADDR)
+
+extern uint32_t SPI_READ_JEDIC(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern int SPI_STARTUP(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern void SPI_WAIT_BUSY(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern void SPI_RESET(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern void SET_QPI_MODE(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern void QPI_READ_WORDS_no_data(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI, uint32_t addr, uint8_t n_words, uint32_t n_dummy, uint8_t cont_read);
+extern void QPI_SET_CONT_READ(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern void QPI_SET_CONT_READ_MICRON(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+extern void QPI_SET_AHB_MODE(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+
+extern void CACHE_STARTUP(CG092_TypeDef *CACHE);
diff --git a/software/cmsis/Device/ARM/CMSDK_CM0/Source/SL_QSPI.c b/software/cmsis/Device/ARM/CMSDK_CM0/Source/SL_QSPI.c
new file mode 100644
index 0000000000000000000000000000000000000000..f6796e62151785d77762cbffe05f81e2971078de
--- /dev/null
+++ b/software/cmsis/Device/ARM/CMSDK_CM0/Source/SL_QSPI.c
@@ -0,0 +1,134 @@
+
+#include "SL_QSPI.h"
+
+uint8_t SET_QIO_MODE_CMD = 0x38;
+
+uint32_t SPI_READ_JEDIC(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+int SPI_STARTUP(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+void SPI_WAIT_BUSY(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+void SPI_RESET(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+void SET_QPI_MODE(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+void QPI_READ_WORDS_no_data(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI, uint32_t addr, uint8_t n_words, uint32_t n_dummy, uint8_t cont_read);
+void QPI_SET_CONT_READ(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+void QPI_SET_CONT_READ_MICRON(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+void QPI_SET_AHB_MODE(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI);
+
+void CACHE_STARTUP(CG092_TypeDef *CACHE);
+
+void CACHE_STARTUP(CG092_TypeDef *CACHE){
+ CACHE->CCR=0;
+ CACHE->CCR=0x1; //DON'T USE PREFETCH
+ while((CACHE->SR)&0x3 != 2){;}
+}
+
+int SPI_STARTUP(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ uint32_t ID;
+ // Check first if warm reset
+ if(SL_AHB_QSPI->CTRL == 0){
+ SPI_RESET(SL_AHB_QSPI);
+ ID=SPI_READ_JEDIC(SL_AHB_QSPI);
+ if((ID==0xFFFFFFFF)||(ID==0x00000000)){
+ return 1;
+ } else {
+ if((ID&0xFF)!=0xBF){
+ SET_QIO_MODE_CMD = 0x35;
+ SL_AHB_QSPI->AHB_CMD = (8<<SL_AHB_QSPI_SPI_CMD_N_Dummy_Pos) + 0x0B;
+ SET_QPI_MODE(SL_AHB_QSPI);
+ QPI_SET_CONT_READ_MICRON(SL_AHB_QSPI);
+ QPI_READ_WORDS_no_data(SL_AHB_QSPI, 0x00000000, 1, 10, 0);
+ SL_AHB_QSPI->CTRL |= (1<<25);
+ QPI_READ_WORDS_no_data(SL_AHB_QSPI, 0x00001000, 1, 8, 1);
+ QPI_SET_AHB_MODE(SL_AHB_QSPI);
+ } else{
+ SL_AHB_QSPI->AHB_CMD = (4<<SL_AHB_QSPI_SPI_CMD_N_Dummy_Pos) + 0x0B;
+ SET_QPI_MODE(SL_AHB_QSPI);
+ QPI_READ_WORDS_no_data(SL_AHB_QSPI, 0x00000000, 1, 6, 0);
+ QPI_SET_CONT_READ(SL_AHB_QSPI);
+ QPI_READ_WORDS_no_data(SL_AHB_QSPI, 0x00001000, 1, 4, 1);
+ QPI_SET_AHB_MODE(SL_AHB_QSPI);
+ }
+ return 0;
+ }
+ }
+ else {
+ return 0;
+ }
+}
+
+void QPI_SET_CONT_READ(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ SL_AHB_QSPI->CTRL |= (1<<25);
+}
+
+void QPI_SET_CONT_READ_MICRON(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ uint32_t CMD=0;
+ // Write Enable
+ SL_AHB_QSPI->SPI_CMD = 0x06;
+ SL_AHB_QSPI->SPI_CMD = 0x106;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+
+ // Write to volatile register
+ SL_AHB_QSPI->WRITE_DATA[0]=0xF3;
+ CMD = 0x81;
+ CMD |= SL_AHB_QSPI_SPI_CMD_Wr_Enable_Msk;
+ SL_AHB_QSPI->SPI_CMD = CMD;
+ SL_AHB_QSPI->SPI_CMD |= SL_AHB_QSPI_SPI_CMD_Enable_Msk;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+
+ // Write disable
+ SL_AHB_QSPI->SPI_CMD = 0x04;
+ SL_AHB_QSPI->SPI_CMD = 0x104;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+}
+
+void QPI_SET_AHB_MODE(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ SL_AHB_QSPI->CTRL |= (1<<8);
+}
+
+void SPI_WAIT_BUSY(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ while(((SL_AHB_QSPI->STATUS)&SL_AHB_QSPI_STATUS_Busy_Msk)!=0){;}
+}
+
+void SPI_RESET(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ SL_AHB_QSPI->SPI_CMD = 0x66;
+ SL_AHB_QSPI->SPI_CMD = 0x166;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+ SL_AHB_QSPI->SPI_CMD = 0x99;
+ SL_AHB_QSPI->SPI_CMD = 0x199;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+}
+
+uint32_t SPI_READ_JEDIC(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ SL_AHB_QSPI->SPI_CMD = 0x0003009F;
+ SL_AHB_QSPI->SPI_CMD = 0x0003039F;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+ return SL_AHB_QSPI->READ_DATA[0];
+}
+
+void QPI_READ_WORDS_no_data(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI, uint32_t addr, uint8_t n_words, uint32_t n_dummy, uint8_t cont_read){
+ uint32_t CMD = 0;
+
+ SL_AHB_QSPI->SPI_ADDR = addr;
+
+ if(cont_read==0){
+ SL_AHB_QSPI->CTRL |= SL_AHB_QSPI_CTRL_Cont_Rd_Msk;
+ SL_AHB_QSPI->CTRL |= (SL_AHB_QSPI_CTRL_Mode_Code_Msk & (0xA0<<16));
+ }
+ CMD |= (SL_AHB_QSPI_SPI_CMD_N_Dummy_Msk & (n_dummy<<12));
+ CMD |= 0x0B;
+ CMD |= SL_AHB_QSPI_SPI_CMD_Rd_Enable_Msk;
+ CMD |= SL_AHB_QSPI_SPI_CMD_Addr_Enable_Msk;
+ CMD |= (SL_AHB_QSPI_SPI_CMD_N_RW_Bytes_Msk & (n_words << 16));
+ SL_AHB_QSPI->SPI_CMD = CMD;
+
+ SL_AHB_QSPI->SPI_CMD |= SL_AHB_QSPI_SPI_CMD_Enable_Msk;
+
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+
+}
+
+void SET_QPI_MODE(SL_AHB_QSPI_TypeDef *SL_AHB_QSPI){
+ SL_AHB_QSPI->SPI_CMD = SET_QIO_MODE_CMD;
+ SL_AHB_QSPI->SPI_CMD = 0x100 + SET_QIO_MODE_CMD;
+ SPI_WAIT_BUSY(SL_AHB_QSPI);
+ SL_AHB_QSPI->CTRL |= SL_AHB_QSPI_CTRL_QIO_Msk;
+}
diff --git a/software/common/bootloader/bootloader.c b/software/common/bootloader/bootloader.c
index 9a9996a9c24a2f7ce2ef7bd437041a47233e0f54..5f8ca8c83c2c9b8a6a68e837133517ddfe2ecf03 100644
--- a/software/common/bootloader/bootloader.c
+++ b/software/common/bootloader/bootloader.c
@@ -52,6 +52,8 @@
#include "CMSDK_CM4.h"
#endif
+#include "SL_QSPI.h"
+
#define UART_CTRL_TXEN CMSDK_UART_CTRL_TXEN_Msk
#define UART_CTRL_RXEN CMSDK_UART_CTRL_RXEN_Msk
#define UART_CTRL_TXRXEN (CMSDK_UART_CTRL_TXEN_Msk + CMSDK_UART_CTRL_RXEN_Msk)
@@ -139,8 +141,15 @@ void FlashLoader(void)
UartPutc(0x4); // Terminate simulation
while (1);
}
- UartPuts("REMAP->IMEM0\n"); // CMSDK boot loader\n");
- CMSDK_SYSCON->REMAP = 0; // Clear remap
+ if(SPI_STARTUP(SL_QSPI)==0){
+ // QSPI flash present
+ UartPuts("REMAP->FLASH\n"); // CMSDK boot loader\n");
+ CACHE_STARTUP(CG092);
+ CMSDK_SYSCON->REMAP = 3;
+ } else {
+ UartPuts("REMAP->IMEM0\n"); // CMSDK boot loader\n");
+ CMSDK_SYSCON->REMAP = 0; // Clear remap
+ }
__DSB();
__ISB();
diff --git a/software/common/scripts/cmsdk_bootloader.ld b/software/common/scripts/cmsdk_bootloader.ld
index 155a8dca6f2bc19aaf2b0e5994b1825edb4d0ba4..34322fad13994c307ebd9d2d7ce5ce1662fe67f3 100644
--- a/software/common/scripts/cmsdk_bootloader.ld
+++ b/software/common/scripts/cmsdk_bootloader.ld
@@ -33,7 +33,7 @@ INCLUDE "lib-nosys.ld"
MEMORY
{
- FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x1000 /* 4K */
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 4K */
RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x3C00 /* 15K */
}
diff --git a/software/debug_tester/debugtester_be.hex b/software/debug_tester/debugtester_be.hex
index c88abd2e70279fba6073c20b62595b3e06e2464a..0f17ccc331e41e4a0da11f9f21320e2cb74ed2d0 100644
--- a/software/debug_tester/debugtester_be.hex
+++ b/software/debug_tester/debugtester_be.hex
@@ -2,15 +2,15 @@ A8
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@@ -196,9 +196,9 @@ F0
F8
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@@ -208,32 +208,52 @@ C8
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@@ -242,19 +262,23 @@ B6
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@@ -6858,8 +6886,8 @@ E7
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@@ -7030,14 +7058,12 @@ A5
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BC
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@@ -7057,6 +7083,8 @@ C5
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@@ -7086,7 +7114,7 @@ BD
01
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01
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diff --git a/software/debug_tester/debugtester_le.hex b/software/debug_tester/debugtester_le.hex
index 945b789017c41519413f9cdfa3bc7d8b168791bb..59b8e04e55e302964486266969270c409d7ccafd 100644
--- a/software/debug_tester/debugtester_le.hex
+++ b/software/debug_tester/debugtester_le.hex
@@ -2,15 +2,15 @@ A8
05
00
20
-8D
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1A
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@@ -208,32 +208,52 @@ C8
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@@ -6826,7 +6854,7 @@ E7
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@@ -7025,6 +7051,8 @@ C5
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@@ -7054,7 +7082,7 @@ BD
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diff --git a/testcodes/apb_mux_tests/apb_mux_tests.hex b/testcodes/apb_mux_tests/apb_mux_tests.hex
index a2ff3251fbb38106e7fbcbdf838486c5dd584aaa..6285cb911fbe38b6f84eb42a982714294152df9b 100644
--- a/testcodes/apb_mux_tests/apb_mux_tests.hex
+++ b/testcodes/apb_mux_tests/apb_mux_tests.hex
@@ -2,15 +2,15 @@
04
00
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diff --git a/testcodes/bootloader/bootloader.hex b/testcodes/bootloader/bootloader.hex
index 4a91c68ec2c4740520853b11bb5a8c26687794e4..bc9e0ee08e373bac658b627065c5062c27b3bf5c 100644
--- a/testcodes/bootloader/bootloader.hex
+++ b/testcodes/bootloader/bootloader.hex
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diff --git a/testcodes/bootloader/makefile b/testcodes/bootloader/makefile
index 910b7f3b758e90b7671e1d0b4cb56eaecaa756ae..fef15f54317f962e699729bb51a840dff8ee93ea 100644
--- a/testcodes/bootloader/makefile
+++ b/testcodes/bootloader/makefile
@@ -191,14 +191,17 @@ all_ds6 : $(BOOTLOADER).hex $(BOOTLOADER).lst
$(BOOTLOADER).o : $(SOFTWARE_DIR)/common/bootloader/$(BOOTLOADER).c $(DEPS_LIST)
$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+SL_QSPI.o : $(DEVICE_DIR)/Source/SL_QSPI.c
+ $(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
$(ASM_TOOL) $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
-$(BOOTLOADER).ELF : $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o $(DEPS_LIST)
- armlink $(ARM_LINK_OPTIONS) $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o -o $@
+$(BOOTLOADER).ELF : $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o SL_QSPI.o $(DEPS_LIST)
+ armlink $(ARM_LINK_OPTIONS) $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o SL_QSPI.o -o $@
$(BOOTLOADER).hex : $(BOOTLOADER).ELF $(DEPS_LIST)
fromelf --vhx --8x1 $< --output $@
diff --git a/testcodes/dataio_tests/dataio_tests.hex b/testcodes/dataio_tests/dataio_tests.hex
index 68a237a52d1c19c1703ffb4f6697313c5917db6f..9ef648a4a2aed01d4b1b4156b68335405469a533 100644
--- a/testcodes/dataio_tests/dataio_tests.hex
+++ b/testcodes/dataio_tests/dataio_tests.hex
@@ -2,15 +2,15 @@
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@@ -242,19 +262,23 @@ B6
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diff --git a/testcodes/dma_tests/dma_tests.hex b/testcodes/dma_tests/dma_tests.hex
index c6226ee50b614413975fb7192c3d79a235c7db45..fa2b45ebef0277a18783984d8cbf3f51b8bd83a0 100644
--- a/testcodes/dma_tests/dma_tests.hex
+++ b/testcodes/dma_tests/dma_tests.hex
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diff --git a/testcodes/dualtimer_demo/dualtimer_demo.hex b/testcodes/dualtimer_demo/dualtimer_demo.hex
index b6cb43dd5aceb7d8cc6fb4780069de602b8bbe29..0a59631c598c0bb94fcd6b231fec9ba305a344c5 100644
--- a/testcodes/dualtimer_demo/dualtimer_demo.hex
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diff --git a/testcodes/gpio_driver_tests/gpio_driver_tests.hex b/testcodes/gpio_driver_tests/gpio_driver_tests.hex
index 7da9c8a73fb7d168908d56b2492c47212cc72c90..cc47386eb45c4d6196b9e415412cce2e10cf77d9 100644
--- a/testcodes/gpio_driver_tests/gpio_driver_tests.hex
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index 83dcf62acf3e629c47784a54f2b7d46bf9fd7b60..fe3db9e1fc84d904a84c23e68b027d3fb17c0610 100644
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-A8
+AC
15
00
00
@@ -286,6 +310,10 @@ D5
47
00
00
+70
+47
+00
+00
00
23
00
@@ -4330,7 +4358,7 @@ C0
0F
00
40
-2C
+48
16
00
00
@@ -4722,7 +4750,7 @@ E7
47
00
00
-45
+61
12
00
00
@@ -5576,14 +5604,12 @@ F7
FE
60
BC
-00
-27
-49
-08
B6
46
00
26
+00
+27
C0
C5
C0
@@ -5603,6 +5629,8 @@ C5
40
3D
49
+08
+49
00
8D
46
@@ -5630,7 +5658,7 @@ BD
48
70
47
-1C
+20
00
00
30
@@ -5762,7 +5790,7 @@ BD
0A
00
00
-A4
+C0
16
00
00
@@ -5774,23 +5802,23 @@ A4
00
00
00
-04
+1C
01
00
00
-C0
+DC
16
00
00
-1C
+20
00
00
30
-64
+60
04
00
00
-20
+3C
01
00
00
diff --git a/testcodes/watchdog_demo/watchdog_demo.hex b/testcodes/watchdog_demo/watchdog_demo.hex
index 60a3d51c5c53d783be52a38e5f77b10c7019fc7d..c3ba3af368479e5df40cb63e47e4a32330b1a8ca 100644
--- a/testcodes/watchdog_demo/watchdog_demo.hex
+++ b/testcodes/watchdog_demo/watchdog_demo.hex
@@ -2,15 +2,15 @@
04
00
30
-D9
+F5
08
00
00
-47
+63
08
00
00
-E3
+FF
08
00
00
@@ -42,8 +42,8 @@ E3
00
00
00
-E5
-08
+01
+09
00
00
00
@@ -54,140 +54,140 @@ E5
00
00
00
-E7
-08
+03
+09
00
00
-E9
-08
+05
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
-EB
-08
+07
+09
00
00
00
@@ -196,9 +196,9 @@ F0
F8
00
F0
-46
+54
F8
-0C
+12
A0
30
C8
@@ -208,32 +208,52 @@ C8
18
2D
18
+AC
+42
+01
+D1
+00
+F0
+4B
+F8
+0F
+CC
A2
46
-67
-1E
AB
46
+0C
+A7
+30
+CF
+2D
+1B
+08
+3F
+3F
+19
+7C
+42
+7F
+1E
54
-46
-5D
-46
+44
+2D
+09
+04
+26
+F4
+41
+64
+1E
AC
42
01
-D1
+D3
00
F0
38
F8
-7E
-46
-0F
-3E
-0F
-CC
-B6
-46
01
26
33
@@ -242,19 +262,23 @@ B6
D0
FB
1A
-A2
-46
-AB
-46
33
43
-18
+98
47
-10
+54
+46
+5D
+46
+DF
+E7
+00
+00
+14
0C
00
00
-30
+34
0C
00
00
@@ -286,6 +310,10 @@ D5
47
00
00
+70
+47
+00
+00
00
23
00
@@ -1906,7 +1934,7 @@ C0
FF
01
40
-B0
+CC
0C
00
00
@@ -2230,7 +2258,7 @@ CC
00
00
30
-40
+5C
05
00
00
@@ -2294,7 +2322,7 @@ E7
47
00
00
-C9
+E5
08
00
00
@@ -3148,14 +3176,12 @@ F7
FE
60
BC
-00
-27
-49
-08
B6
46
00
26
+00
+27
C0
C5
C0
@@ -3175,6 +3201,8 @@ C5
40
3D
49
+08
+49
00
8D
46
@@ -3338,7 +3366,7 @@ BD
00
00
00
-2C
+48
0D
00
00
@@ -3350,11 +3378,11 @@ BD
00
00
00
-04
+1C
01
00
00
-44
+60
0D
00
00
@@ -3366,7 +3394,7 @@ BD
04
00
00
-20
+3C
01
00
00
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 3ab628e10101c8afd73be3e997ee34036b2277ab..ea0dc6d21097d415884ac287a3e95abae4788817 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -95,6 +95,32 @@ localparam BE=0;
localparam DATA_IN_FILENAME="data_in.csv";
localparam DATA_OUT_FILENAME="logs/data_out.csv";
+// External Flash
+wire QSPI_SCLK;
+wire QSPI_nCS;
+wire [3:0] QSPI_IO;
+
+pullup(QSPI_IO[0]);
+pullup(QSPI_IO[1]);
+pullup(QSPI_IO[2]);
+pullup(QSPI_IO[3]);
+
+// External Flash instantiation
+// Uncomment to use flash
+
+// sst26vf064b u_sst26vf064b(
+// .SCK(QSPI_SCLK),
+// .SIO(QSPI_IO),
+// .CEb(QSPI_nCS)
+// );
+// defparam u_sst26vf064b.I0.Tbe = 1_000;
+// defparam u_sst26vf064b.I0.Tse = 1_000;
+// defparam u_sst26vf064b.I0.Tsce = 1_000;
+// defparam u_sst26vf064b.I0.Tpp = 1_000;
+// defparam u_sst26vf064b.I0.Tws = 1000;
+
+// initial #1 $readmemh("image.hex",u_sst26vf064b.I0.memory);
+
/*
SROM_Ax32
#(.ADDRWIDTH (8),
@@ -147,7 +173,10 @@ initial begin
.P0 (P0[7:0]),
.P1 (P1[7:0]),
.SWDIO (SWDIOTMS),
- .SWDCK (SWCLKTCK)
+ .SWDCK (SWCLKTCK),
+ .QSPI_IO (QSPI_IO[3:0]),
+ .QSPI_SCLK (QSPI_SCLK),
+ .QSPI_nCS (QSPI_nCS)
);
`else
nanosoc_chip_pads
@@ -166,7 +195,10 @@ initial begin
.P0 (P0[15:0]),
.P1 (P1[15:0]),
.SWDIO (SWDIOTMS),
- .SWDCK (SWCLKTCK)
+ .SWDCK (SWCLKTCK),
+ .QSPI_IO (QSPI_IO[3:0]),
+ .QSPI_SCLK (QSPI_SCLK),
+ .QSPI_nCS (QSPI_nCS)
);
`endif
// --------------------------------------------------------------------------------
diff --git a/verif/tb/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
index a79fca87865ec3ce8070499990c904254a4c5875..75a41253e5a7109f072bf544605356bce28f787a 100644
--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -95,6 +95,16 @@ localparam BE=0;
localparam DATA_IN_FILENAME="data_in.csv";
localparam DATA_OUT_FILENAME="logs/data_out.csv";
+// External Flash
+wire QSPI_SCLK;
+wire QSPI_nCS;
+wire [3:0] QSPI_IO;
+
+pullup(QSPI_IO[0]);
+pullup(QSPI_IO[1]);
+pullup(QSPI_IO[2]);
+pullup(QSPI_IO[3]);
+
/*
SROM_Ax32
#(.ADDRWIDTH (8),
@@ -147,7 +157,10 @@ initial begin
.P0 (P0[7:0]),
.P1 (P1[7:0]),
.SWDIO (SWDIOTMS),
- .SWDCK (SWCLKTCK)
+ .SWDCK (SWCLKTCK),
+ .QSPI_IO (QSPI_IO[3:0]),
+ .QSPI_SCLK (QSPI_SCLK),
+ .QSPI_nCS (QSPI_nCS)
);
`else
nanosoc_chip_pads
@@ -166,7 +179,10 @@ initial begin
.P0 (P0[15:0]),
.P1 (P1[15:0]),
.SWDIO (SWDIOTMS),
- .SWDCK (SWCLKTCK)
+ .SWDCK (SWCLKTCK),
+ .QSPI_IO (QSPI_IO[3:0]),
+ .QSPI_SCLK (QSPI_SCLK),
+ .QSPI_nCS (QSPI_nCS)
);
`endif
// --------------------------------------------------------------------------------