From 3f21999742925d3fea7ad47ab74db1bf27533572 Mon Sep 17 00:00:00 2001 From: dwf1m12 <d.w.flynn@soton.ac.uk> Date: Mon, 20 Feb 2023 21:20:20 +0000 Subject: [PATCH] fix UART(2) loopback for uart tests --- Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v index 8ab7912..b6fccfb 100644 --- a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v +++ b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v @@ -240,6 +240,8 @@ reg baud_clk_del; // assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD // assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD +assign P1[4] = P1[5]; // loopback UART2 + wire ft_clk_out = P1[1]; wire ft_miso_in; assign P1[0] = ft_miso_in; -- GitLab