diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/verilog/nanosoc_chip.v
index 213f784bd066e2cfef46f136c303fe451c2c8c4f..a1e108ad4ddc822c7d3b9d3ba7a3303d42bf8d98 100644
--- a/system/src/verilog/nanosoc_chip.v
+++ b/system/src/verilog/nanosoc_chip.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -847,33 +847,38 @@ localparam CORTEX_M0 = 1;
//----------------------------------------
`ifdef NANOSOC_EXPANSION_REGION
-nanosoc_acc_wrapper #(
+
+nanosoc_exp_wrapper #(
.AHBADDRWIDTH(29),
+ .INPACKETWIDTH(16),
+ .CFGSIZEWIDTH(32),
+ .CFGSCHEMEWIDTH(1),
+ .OUTPACKETWIDTH(16),
.CFGNUMIRQ(4)
) u_nanosoc_exp_wrapper (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (HSEL_exp),
- .HADDRS (HADDR_exp[28:0]),
- .HTRANSS (HTRANS_exp),
- .HSIZES (HSIZE_exp),
- .HPROTS (HPROT_exp),
- .HWRITES (HWRITE_exp),
- .HREADYS (HREADYMUX_exp),
- .HWDATAS (HWDATA_exp),
-
- .HREADYOUTS (HREADYOUT_exp),
- .HRESPS (HRESP_exp),
- .HRDATAS (HRDATA_exp),
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ // AHB port: 32 bit data bus interface
+ .HSEL_i (HSEL_exp),
+ .HADDR_i (HADDR_exp[28:0]),
+ .HTRANS_i (HTRANS_exp),
+ .HSIZE_i (HSIZE_exp),
+ .HPROT_i (HPROT_exp),
+ .HWRITE_i (HWRITE_exp),
+ .HREADY_i (HREADYMUX_exp),
+ .HWDATA_i (HWDATA_exp),
+ .HREADYOUT_o (HREADYOUT_exp),
+ .HRESP_o (HRESP_exp),
+ .HRDATA_o (HRDATA_exp),
.exp_drq_ip_o (exp_drq_ip),
.exp_dlast_ip_i(1'b0),
.exp_drq_op_o (exp_drq_op),
.exp_dlast_op_i(1'b0),
.exp_irq_o (exp_irq)
);
+
`else
+
// Default slave - if no expansion region
cmsdk_ahb_default_slave u_ahb_exp (
.HCLK (HCLK),
@@ -886,30 +891,6 @@ nanosoc_acc_wrapper #(
);
assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data
-//nanosoc_exp_wrapper #(.AHBADDRWIDTH(29)
-//) u_nanosoc_exp_wrapper (
-// .HCLK (HCLK),
-// .HRESETn (HRESETn),
-//
-// // Input slave port: 32 bit data bus interface
-// .HSEL_i (HSEL_exp),
-// .HADDR_i (HADDR_exp[28:0]),
-// .HTRANS_i (HTRANS_exp),
-// .HSIZE_i (HSIZE_exp),
-// .HPROT_i (HPROT_exp),
-// .HWRITE_i (HWRITE_exp),
-// .HREADY_i (HREADYMUX_exp),
-// .HWDATA_i (HWDATA_exp),
-//
-// .HREADYOUT_o (HREADYOUT_exp),
-// .HRESP_o (HRESP_exp),
-// .HRDATA_o (HRDATA_exp),
-// .exp_drq_ip_o (exp_drq_ip),
-// .exp_dlast_ip_i(1'b0),
-// .exp_drq_op_o (exp_drq_op),
-// .exp_dlast_op_i(1'b0),
-// .exp_irq_o (exp_irq)
-//);
`endif
assign HRUSER_exp = 2'b00;
diff --git a/system/testcodes/aes128_tests/makefile b/system/testcodes/aes128_tests/makefile
index 1c6281f3079689cf236acc3bcd2bc9aad3ee43f0..965b6ef9ee7d004b7db2c4c65f740aa979634c60 100644
--- a/system/testcodes/aes128_tests/makefile
+++ b/system/testcodes/aes128_tests/makefile
@@ -156,7 +156,7 @@ all: all_$(TOOL_CHAIN)
# ---------------------------------------------------------------------------------------
# DS-5
-all_ds5 : $(TESTNAME).hex $(TESTNAME).lst $(TESTNAME).bin
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
diff --git a/system/verif/verilog/nanosoc_acc_log_to_file.v b/system/verif/verilog/nanosoc_acc_log_to_file.v
new file mode 100644
index 0000000000000000000000000000000000000000..8a03a47a5d59124247ad257c4fc7d16d91fa73d0
--- /dev/null
+++ b/system/verif/verilog/nanosoc_acc_log_to_file.v
@@ -0,0 +1,183 @@
+//-----------------------------------------------------------------------------
+// AHB transaction logger, developed for DMA integration testing
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_acc_log_to_file
+ #(parameter FILENAME = "accelerator.log",
+ parameter AHBADDRWIDTH = 29,
+ parameter CFGNUMIRQ = 1,
+ parameter TIMESTAMP = 1)
+ (
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+ input wire HSEL_i, // Device select
+ input wire [AHBADDRWIDTH-1:0] HADDR_i, // Address for byte select
+ input wire [1:0] HTRANS_i, // Transfer control
+ input wire [2:0] HSIZE_i, // Transfer size
+ input wire [3:0] HPROT_i, // Protection control
+ input wire HWRITE_i, // Write control
+ input wire HREADY_i, // Transfer phase done
+ input wire [31:0] HWDATA_i, // Write data
+ input wire HREADYOUT_o, // Device ready
+ input wire [31:0] HRDATA_o, // Read data output
+ input wire HRESP_o, // Device response
+// stream data
+ input wire exp_drq_ip_o, // (to) DMAC input burst request
+ input wire exp_dlast_ip_i,// (from) DMAC input burst end (last transfer)
+ input wire exp_drq_op_o, // (to) DMAC output dma burst request
+ input wire exp_dlast_op_i,// (from) DMAC output burst end (last transfer)
+ input wire [CFGNUMIRQ-1:0] exp_irq_o
+ );
+
+
+ // AHB transction de-pipelining
+
+ // --------------------------------------------------------------------------
+ // Internal regs/wires
+ // --------------------------------------------------------------------------
+
+ reg sel_r;
+ reg [AHBADDRWIDTH-1:0] addr_r;
+ reg wcyc_r;
+ reg rcyc_r;
+ reg [3:0] byte4_r;
+ reg [3:0] dma_ctrl_state_r;
+
+ // --------------------------------------------------------------------------
+ // AHB slave byte buffer interface, support for unaligned data transfers
+ // --------------------------------------------------------------------------
+
+ wire [1:0] byte_addr = HADDR_i[1:0];
+ // generate next byte enable decodes for Word/Half/Byte CPU/DMA accesses
+ wire [3:0] byte_nxt;
+ assign byte_nxt[0] = (HSIZE_i[1])|((HSIZE_i[0])&(!byte_addr[1]))|(byte_addr[1:0]==2'b00);
+ assign byte_nxt[1] = (HSIZE_i[1])|((HSIZE_i[0])&(!byte_addr[1]))|(byte_addr[1:0]==2'b01);
+ assign byte_nxt[2] = (HSIZE_i[1])|((HSIZE_i[0])&( byte_addr[1]))|(byte_addr[1:0]==2'b10);
+ assign byte_nxt[3] = (HSIZE_i[1])|((HSIZE_i[0])&( byte_addr[1]))|(byte_addr[1:0]==2'b11);
+
+ // de-pipelined registered access signals
+ always @(posedge HCLK or negedge HRESETn)
+ if (!HRESETn)
+ begin
+ addr_r <= 16'h0000;
+ sel_r <= 1'b0;
+ wcyc_r <= 1'b0;
+ rcyc_r <= 1'b0;
+ byte4_r <= 4'b0000;
+ end else if (HREADY_i)
+ begin
+ addr_r <= (HSEL_i & HTRANS_i[1]) ? HADDR_i : addr_r;
+ sel_r <= (HSEL_i & HTRANS_i[1]);
+ wcyc_r <= (HSEL_i & HTRANS_i[1] & HWRITE_i);
+ rcyc_r <= (HSEL_i & HTRANS_i[1] & !HWRITE_i);
+ byte4_r <= (HSEL_i & HTRANS_i[1]) ? byte_nxt[3:0] : 4'b0000;
+ end
+
+ wire [31:0] hdata = (wcyc_r)? HWDATA_i : HRDATA_o;
+
+ //----------------------------------------------
+ //-- File I/O
+ //----------------------------------------------
+
+ integer fd; // channel descriptor for cmd file input
+ integer ch;
+
+ reg exp_drq_ip_o_prev;
+ reg exp_dlast_ip_i_prev;
+ reg exp_drq_op_o_prev;
+ reg exp_dlast_op_i_prev;
+ reg [CFGNUMIRQ-1:0] exp_irq_prev;
+
+ wire exp_drq_ip_change;
+ wire exp_dlast_ip_change;
+ wire exp_drq_op_change;
+ wire exp_dlast_op_change;
+ wire [CFGNUMIRQ-1:0] exp_irq_change;
+ wire irq_change;
+ wire drq_change;
+ wire any_change;
+
+ reg [31:0] cyc_count;
+`define EOF -1
+
+ reg [7:0] ctrl_reg;
+ reg [2:0] dreq_reg;
+ reg [2:0] ireq_reg;
+
+ always @(posedge HCLK or negedge HRESETn)
+ if (!HRESETn)
+ begin
+ exp_drq_ip_o_prev <= 1'b0;
+ exp_dlast_ip_i_prev <= 1'b0;
+ exp_drq_op_o_prev <= 1'b0;
+ exp_dlast_op_i_prev <= 1'b0;
+ exp_irq_prev <= {CFGNUMIRQ{1'b0}};
+
+ end else if (HREADY_i)
+ begin
+ exp_drq_ip_o_prev <= exp_drq_ip_o ;
+ exp_dlast_ip_i_prev <= exp_dlast_ip_i;
+ exp_drq_op_o_prev <= exp_drq_op_o ;
+ exp_dlast_op_i_prev <= exp_dlast_op_i;
+ exp_irq_prev <= exp_irq_o ;
+ end
+
+ assign exp_drq_ip_change = (exp_drq_ip_o_prev ^ exp_drq_ip_o );
+ assign exp_dlast_ip_change = (exp_dlast_ip_i_prev ^ exp_dlast_ip_i);
+ assign exp_drq_op_change = (exp_drq_op_o_prev ^ exp_drq_op_o );
+ assign exp_dlast_op_change = (exp_dlast_op_i_prev ^ exp_dlast_op_i);
+ assign drq_change = exp_drq_ip_change | exp_drq_op_change
+ | exp_dlast_ip_change | exp_dlast_op_change;
+ assign exp_irq_change = (exp_irq_prev ^ exp_irq_o);
+ assign irq_change = |(exp_irq_change);
+
+ assign any_change = drq_change
+ | irq_change
+ ;
+
+ initial
+ begin
+ fd= $fopen(FILENAME,"w");
+ cyc_count <= 0;
+ if (fd == 0)
+ $write("** %m : output log file failed to open **\n");
+ else begin
+ @(posedge HRESETn);
+ while (1) begin
+ @(posedge HCLK);
+ cyc_count <= cyc_count +1;
+ if (sel_r & HREADY_i) begin
+ $fwrite(fd, "ACC: A+0x%08x, %s, D=0x", addr_r, (wcyc_r) ? "W" : "R");
+ if (byte4_r[3]) $fwrite(fd, "%02x", hdata[31:24]); else $fwrite(fd, "--");
+ if (byte4_r[2]) $fwrite(fd, "%02x", hdata[23:16]); else $fwrite(fd, "--");
+ if (byte4_r[1]) $fwrite(fd, "%02x", hdata[15: 8]); else $fwrite(fd, "--");
+ if (byte4_r[0]) $fwrite(fd, "%02x", hdata[ 7: 0]); else $fwrite(fd, "--");
+ if (TIMESTAMP) $fwrite(fd, ", CYC=%8d (@%t)\n", cyc_count, $time); else $fwrite(fd, "\n");
+ end
+ if (any_change) begin
+ $fwrite(fd, "ACC-DRQ: ");
+ if (drq_change) begin
+ $fwrite(fd, " exp_drq_ip_o=%b,",exp_drq_ip_o);
+ $fwrite(fd, " exp_dlast_ip_i=%b,",exp_dlast_ip_i);
+ $fwrite(fd, " exp_drq_op_o=%b,",exp_drq_op_o);
+ $fwrite(fd, " exp_dlast_op_i=%b",exp_dlast_op_i);
+ end
+ if (irq_change) begin
+ if (drq_change) $fwrite(fd, ",");
+ $fwrite(fd, " ACC-IRQ=%b,",exp_irq_o);
+ end
+ if (TIMESTAMP) $fwrite(fd, ", CYC=%8d (@%t)\n",cyc_count, $time); else $fwrite(fd, "\n");
+ end
+ end
+ $fclose(fd);
+ end
+ end
+
+endmodule
diff --git a/system/verif/verilog/nanosoc_tb.v b/system/verif/verilog/nanosoc_tb.v
index 2117f354b5098cf525ae73f592d5e7dde5a826e5..8a7bc4ffcae6980e7792ae6b782680c0971516c5 100644
--- a/system/verif/verilog/nanosoc_tb.v
+++ b/system/verif/verilog/nanosoc_tb.v
@@ -594,35 +594,31 @@ nanosoc_ft1248x1_track
);
// --------------------------------------------------------------------------------
- // Tracking AES logging support
+ // Tracking Accelerator logging support
// --------------------------------------------------------------------------------
- `define AES_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper.u_exp_aes128
-
- aes128_log_to_file #(.FILENAME("logs/aes128.log"),.TIMESTAMP(1))
- u_aes_log_to_file (
- .ahb_hclk (`AES_PATH.ahb_hclk ),
- .ahb_hresetn (`AES_PATH.ahb_hresetn ),
- .ahb_hsel (`AES_PATH.ahb_hsel ),
- .ahb_haddr16 (`AES_PATH.ahb_haddr16 ),
- .ahb_htrans (`AES_PATH.ahb_htrans ),
- .ahb_hwrite (`AES_PATH.ahb_hwrite ),
- .ahb_hsize (`AES_PATH.ahb_hsize ),
- .ahb_hprot (`AES_PATH.ahb_hprot ),
- .ahb_hwdata (`AES_PATH.ahb_hwdata ),
- .ahb_hready (`AES_PATH.ahb_hready ),
- .ahb_hrdata (`AES_PATH.ahb_hrdata ),
- .ahb_hreadyout (`AES_PATH.ahb_hreadyout ),
- .ahb_hresp (`AES_PATH.ahb_hresp ),
- .drq_ipdma128 (`AES_PATH.drq_ipdma128 ),
- .dlast_ipdma128 (`AES_PATH.dlast_ipdma128),
- .drq_opdma128 (`AES_PATH.drq_opdma128 ),
- .dlast_opdma128 (`AES_PATH.dlast_opdma128),
- .irq_key128 (`AES_PATH.irq_key128 ),
- .irq_ip128 (`AES_PATH.irq_ip128 ),
- .irq_op128 (`AES_PATH.irq_op128 ),
- .irq_error (`AES_PATH.irq_error ),
- .irq_merged (`AES_PATH.irq_merged )
+ `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper
+
+ nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1))
+ u_nanosoc_acc_log_to_file (
+ .HCLK (`ACC_PATH.HCLK ),
+ .HRESETn (`ACC_PATH.HRESETn ),
+ .HSEL_i (`ACC_PATH.HSEL_i ),
+ .HADDR_i (`ACC_PATH.HADDR_i ),
+ .HTRANS_i (`ACC_PATH.HTRANS_i ),
+ .HWRITE_i (`ACC_PATH.HWRITE_i ),
+ .HSIZE_i (`ACC_PATH.HSIZE_i ),
+ .HPROT_i (`ACC_PATH.HPROT_i ),
+ .HWDATA_i (`ACC_PATH.HWDATA_i ),
+ .HREADY_i (`ACC_PATH.HREADY_i ),
+ .HRDATA_o (`ACC_PATH.HRDATA_o ),
+ .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ),
+ .HRESP_o (`ACC_PATH.HRESP_o ),
+ .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ),
+ .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i),
+ .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ),
+ .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i),
+ .exp_irq_o (`ACC_PATH.exp_irq_o )
);
diff --git a/system/work/_info b/system/work/_info
new file mode 100644
index 0000000000000000000000000000000000000000..0438877c64cf8656282cd6500f1e163238a00771
--- /dev/null
+++ b/system/work/_info
@@ -0,0 +1,10 @@
+m255
+K4
+z2
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+d/home/dwf1m12/work/soclabs_aes128/accelerator-project-secworks-aes-128/nanosoc_tech/system