From 32f4e250bd6db5d4b9fc8e0996d006edd2966d8a Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Wed, 27 Sep 2023 11:35:42 +0100
Subject: [PATCH] Tie-off TEST mode pin inactive in testbench

---
 verif/tb/verilog/nanosoc_tb.v | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index e16d5b0..2ae8fdb 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -130,6 +130,8 @@ SROM_Ax32
   );
   `endif
 
+  assign TEST=1'b0;
+  
   // Pullup to suppress X-inputs
   pullup(P0[ 0]);
   pullup(P0[ 1]);
-- 
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