From 32cde988177ce32ed9dbaad0eb650855738da031 Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Mon, 3 Jul 2023 22:19:18 +0100 Subject: [PATCH] Cleaned FPGA Makeflow and commented --- fpga/build_fpga.tcl | 1 + fpga/makefile | 146 ++++++++++++++++++------------------- fpga/makefile.fpga_targets | 29 ++++++++ 3 files changed, 102 insertions(+), 74 deletions(-) create mode 100644 fpga/makefile.fpga_targets diff --git a/fpga/build_fpga.tcl b/fpga/build_fpga.tcl index ad018d7..17adbd3 100644 --- a/fpga/build_fpga.tcl +++ b/fpga/build_fpga.tcl @@ -102,4 +102,5 @@ exec mkdir -p $output_dir exec cp -p $project_dir/export/$design_name.bit $output_dir exec cp -p $project_dir/export/$design_name.hwh $output_dir +exec rm -r $nanosoc_lib exit 0 diff --git a/fpga/makefile b/fpga/makefile index 9c2fa1b..d5b3055 100644 --- a/fpga/makefile +++ b/fpga/makefile @@ -1,112 +1,110 @@ -IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga +#----------------------------------------------------------------------------- +# NanoSoC FPGA Flow Makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright (C) 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +# Get properties for FPGA Boards +include $(SOCLABS_NANOSOC_TECH_DIR)/fpga/makefile.fpga_targets + +# Vivado Options +VIVIADO_VERSION ?= 2021_1 + +# NanoSoC Synthesis Properties +VENDOR ?= soclabs.org +NANOSOC_CORE_REV ?= 2 # System Design Filelist ifeq ($(QUICKSTART),yes) DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist - TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist - ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical - ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical - TB_TOP ?= nanosoc_tb_qs else DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist - TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist - ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical - ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical - TB_TOP ?= nanosoc_tb endif -# Name of generated filelist by python script -TCL_FLIST_DIR := $(IMP_DIR)/flist -TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl - -ifeq ($(FPGA),mps3) - XILINX_PART := xcku115-flvb1760-1-c - BOARD_NAME := arm_mps3 - PLATFORM := bare -else ifeq ($(FPGA),zcu104) - XILINX_PART := xczu7ev-ffvc1156-2-e - BOARD_NAME := pynq_zcu104 - PLATFORM := pynq -else ifeq ($(FPGA),z2) - XILINX_PART := xc7z020clg400-1 - BOARD_NAME := pynq_z2 - PLATFORM := pynq -else # Default to z2 - XILINX_PART := xc7z020clg400-1 - BOARD_NAME := pynq_z2 - PLATFORM := pynq -endif - -# Is an accelerator subsystem present in the design? -ACCELERATOR ?= yes +# Top-level of RTL design to Implement +FPGA_TOP ?= nanosoc_chip -ifeq ($(ACCELERATOR),yes) - ACCELERATOR_SUBSYSTEM = 1 -else - ACCELERATOR_SUBSYSTEM = 0 -endif +# Name of Implemented Chip Design (Including Socket IP) +DESIGN_NAME ?= nanosoc_design -FPGA_TOP ?= nanosoc_chip +# Location to build FPGA files +IMPLEMENTATION_DIR ?= $(SOCLABS_PROJECT_DIR)/imp/fpga +RUN_DIR := $(IMPLEMENTATION_DIR)/run +TEMP_RTL_NANOSOC_DIR := $(RUN_DIR)/temp_nanosoc_lib +PROJECT_DIR := $(IMPLEMENTATION_DIR)/targets/$(BOARD_NAME) -# NanoSoC Synthesis Properties -VENDOR ?= soclabs.org -NANOSOC_CORE_REV ?= 2 -VIVIADO_VERSION ?= 2021_1 - -TEMP_RTL_NANOSOC_DIR := $(IMP_DIR)/nanosoc_lib -RTL_SOCKET_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/socket/xilinx_lib +# Name of generated filelist by python script +TCL_FLIST_DIR := $(IMPLEMENTATION_DIR)/flist +TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl +# NanoSoC Tech Flow Dependencies NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga +TARGET_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME) +TARGET_TCL_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)/vivado_script/$(VIVIADO_VERSION) -RUN_DIR := $(IMP_DIR)/run -PROJECT_DIR := $(IMP_DIR)/targets/$(BOARD_NAME) -DESIGN_NAME ?= nanosoc_design - -TARGET_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME) -TARGET_TCL_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)/vivado_script/$(VIVIADO_VERSION) +# NanoSoC Tech Socket Design Dependencies +RTL_SOCKET_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/socket/xilinx_lib +# Define Bitfile Output Directory depending on Platform ifeq ($(PLATFORM), bare) - OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME) + OUTPUT_DIR ?= $(FPGA_IMPLEMENTATION_DIR)/output/$(BOARD_NAME) else ifeq ($(PLATFORM), pynq) - OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME)/overlays -# OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME)/pynq/overlays/soclabs + OUTPUT_DIR ?= $(FPGA_IMPLEMENTATION_DIR)/output/$(BOARD_NAME)/overlays endif -# FPGA_Flow -build_fpga: export FPGA_NAME = $(BOARD_NAME) -build_fpga: export FPGA_PART = $(XILINX_PART) -build_fpga: export FPGA_PROJECT_DIR = $(PROJECT_DIR) -build_fpga: export FPGA_TARGET = $(TARGET_DIR) -build_fpga: export FPGA_TARGET_TCL = $(TARGET_TCL_DIR) -build_fpga: export FPGA_TCL_FILELIST = $(TCL_OUTPUT_FILELIST) -build_fpga: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM) -build_fpga: export FPGA_DESIGN_TOP = $(FPGA_TOP) -build_fpga: export FPGA_VENDOR = $(VENDOR) -build_fpga: export FPGA_CORE_REV = $(NANOSOC_CORE_REV) -build_fpga: export FPGA_NANOSOC_LIB = $(TEMP_RTL_NANOSOC_DIR) -build_fpga: export FPGA_SOCKET_LIB = $(RTL_SOCKET_DIR) -build_fpga: export FPGA_IMP_DIR = $(IMP_DIR) -build_fpga: export FPGA_FLOW_DIR = $(NANOSOC_FPGA_FLOW_DIR) -build_fpga: export FPGA_DESIGN_NAME = $(DESIGN_NAME) -build_fpga: export FPGA_OUTPUT_DIR = $(OUTPUT_DIR) +# Is an accelerator subsystem present in the design? +ACCELERATOR ?= yes +ifeq ($(ACCELERATOR),yes) + ACCELERATOR_SUBSYSTEM = 1 +else + ACCELERATOR_SUBSYSTEM = 0 +endif + +# Export Environment Variables so FPGA TCL scripts can access values +build_fpga: export FPGA_NAME = $(BOARD_NAME) +build_fpga: export FPGA_PART = $(XILINX_PART) +build_fpga: export FPGA_PROJECT_DIR = $(PROJECT_DIR) +build_fpga: export FPGA_TARGET = $(TARGET_DIR) +build_fpga: export FPGA_TARGET_TCL = $(TARGET_TCL_DIR) +build_fpga: export FPGA_TCL_FILELIST = $(TCL_OUTPUT_FILELIST) +build_fpga: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM) +build_fpga: export FPGA_DESIGN_TOP = $(FPGA_TOP) +build_fpga: export FPGA_VENDOR = $(VENDOR) +build_fpga: export FPGA_CORE_REV = $(NANOSOC_CORE_REV) +build_fpga: export FPGA_NANOSOC_LIB = $(TEMP_RTL_NANOSOC_DIR) +build_fpga: export FPGA_SOCKET_LIB = $(RTL_SOCKET_DIR) +build_fpga: export FPGA_IMPLEMENTATION_DIR = $(IMPLEMENTATION_DIR) +build_fpga: export FPGA_FLOW_DIR = $(NANOSOC_FPGA_FLOW_DIR) +build_fpga: export FPGA_DESIGN_NAME = $(DESIGN_NAME) +build_fpga: export FPGA_OUTPUT_DIR = $(OUTPUT_DIR) + +# Generate TCL filelist from flists tcl_flist: @mkdir -p $(TCL_FLIST_DIR) @(cd $(TCL_FLIST_DIR); \ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(TEMP_RTL_NANOSOC_DIR);) +# Synthesise and Implement an FPGA Bitfile build_fpga: tcl_flist clean_fpga @echo Starting Vivado Run @mkdir -p $(RUN_DIR) @cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_fpga.tcl @echo Vivado Build Complete +# Clean FPGA Run clean_fpga: @echo Cleaning Previous Runs of $(BOARD_NAME) @rm -rf $(PROJECT_DIR) @rm -rf $(TEMP_RTL_NANOSOC_DIR) @rm -rf $(RUN_DIR) - + +# Clean ALL FPGA Implementation Directory clean_fpga_all: @echo Cleaning FPGA Implementation Directory - @rm -rf $(IMP_DIR) \ No newline at end of file + @rm -rf $(IMPLEMENTATION_DIR) \ No newline at end of file diff --git a/fpga/makefile.fpga_targets b/fpga/makefile.fpga_targets new file mode 100644 index 0000000..12ba27c --- /dev/null +++ b/fpga/makefile.fpga_targets @@ -0,0 +1,29 @@ +#----------------------------------------------------------------------------- +# NanoSoC FPGA Targets Declaration Makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright (C) 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +# FPGA Specific Options - More can be added later +ifeq ($(FPGA),mps3) + XILINX_PART := xcku115-flvb1760-1-c + BOARD_NAME := arm_mps3 + PLATFORM := bare +else ifeq ($(FPGA),zcu104) + XILINX_PART := xczu7ev-ffvc1156-2-e + BOARD_NAME := pynq_zcu104 + PLATFORM := pynq +else ifeq ($(FPGA),z2) + XILINX_PART := xc7z020clg400-1 + BOARD_NAME := pynq_z2 + PLATFORM := pynq +else # Default to Z2 + XILINX_PART := xc7z020clg400-1 + BOARD_NAME := pynq_z2 + PLATFORM := pynq +endif \ No newline at end of file -- GitLab