From 30156ab6ed83d9a57acf1362901d4a089c2ee14e Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 15 Jun 2023 14:58:09 +0100
Subject: [PATCH] SOC1-230: Renamed Debug Master in Bus Matrix and created
debug Subsystem
---
.../nanosoc_busmatrix/nanosoc_busmatrix.xml | 128 ++++++++--------
.../nanosoc_busmatrix_lite.xml | 116 +++++++--------
system/nanosoc_busmatrix/logs/nanosoc.log | 58 ++++----
.../nanosoc_busmatrix/nanosoc_busmatrix.v | 138 +++++++++---------
.../nanosoc_busmatrix_lite.v | 100 ++++++-------
...CDEBUG.v => nanosoc_matrix_decode_DEBUG.v} | 2 +-
system/nanosoc_busmatrix/xml/nanosoc.xml | 2 +-
.../debug/verilog/nanosoc_ss_debug.v | 115 +++++++++++++++
8 files changed, 387 insertions(+), 272 deletions(-)
rename system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/{nanosoc_matrix_decode_SOCDEBUG.v => nanosoc_matrix_decode_DEBUG.v} (99%)
create mode 100644 system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
diff --git a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
index 7520bf7..24dd19e 100644
--- a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
+++ b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
@@ -38,12 +38,12 @@
<!--Slave interfaces -->
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Slave__SOCDEBUG</spirit:name>
- <spirit:description>Slave port _SOCDEBUG</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DEBUG</spirit:name>
+ <spirit:description>Slave port _DEBUG</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__SOCDEBUG_MM"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DEBUG_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
@@ -80,7 +80,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_SOCDEBUG</spirit:name>
+ <spirit:name>HSEL_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -88,7 +88,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_SOCDEBUG</spirit:name>
+ <spirit:name>HADDR_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -96,7 +96,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_SOCDEBUG</spirit:name>
+ <spirit:name>HTRANS_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -104,7 +104,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_SOCDEBUG</spirit:name>
+ <spirit:name>HWRITE_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -112,7 +112,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_SOCDEBUG</spirit:name>
+ <spirit:name>HSIZE_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -120,7 +120,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_SOCDEBUG</spirit:name>
+ <spirit:name>HBURST_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -128,18 +128,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_SOCDEBUG</spirit:name>
+ <spirit:name>HPROT_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_SOCDEBUG unmapped -->
+ <!-- HMASTER_DEBUG unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HWDATA_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -147,7 +147,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_SOCDEBUG</spirit:name>
+ <spirit:name>HMASTLOCK_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -155,7 +155,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_SOCDEBUG</spirit:name>
+ <spirit:name>HREADY_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -165,7 +165,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HRDATA_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -173,7 +173,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_SOCDEBUG</spirit:name>
+ <spirit:name>HREADYOUT_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -181,7 +181,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_SOCDEBUG</spirit:name>
+ <spirit:name>HRESP_DEBUG</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -2152,17 +2152,17 @@
<spirit:remapStates>
<spirit:remapState>
- <spirit:name>remap_0</spirit:name>
- <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -2335,8 +2335,8 @@
<spirit:memoryMaps>
<spirit:memoryMap>
- <spirit:name>AHBLiteTarget_Slave__SOCDEBUG_MM</spirit:name>
- <spirit:description>_SOCDEBUG memory map</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DEBUG_MM</spirit:name>
+ <spirit:description>_DEBUG memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
@@ -2408,20 +2408,9 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteTarget_Slave__SOCDEBUG_remap_0_remap_MM</spirit:name>
- <spirit:description>_SOCDEBUG remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteTarget_Slave__SOCDEBUG_remap_n0_remap_MM</spirit:name>
- <spirit:description>_SOCDEBUG remap_n0 remap</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0 remap</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
@@ -2430,6 +2419,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
<spirit:memoryMap>
@@ -2658,17 +2658,6 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_0_remap_MM</spirit:name>
- <spirit:description>_CPU_0 remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_n0 remap</spirit:description>
@@ -2680,6 +2669,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_0_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
</spirit:memoryMaps>
@@ -2735,13 +2735,13 @@
<!-- Input signals of Slave interfaces -->
<spirit:port>
- <spirit:name>HSEL_SOCDEBUG</spirit:name>
+ <spirit:name>HSEL_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_SOCDEBUG</spirit:name>
+ <spirit:name>HADDR_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2751,7 +2751,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_SOCDEBUG</spirit:name>
+ <spirit:name>HTRANS_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2761,13 +2761,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_SOCDEBUG</spirit:name>
+ <spirit:name>HWRITE_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_SOCDEBUG</spirit:name>
+ <spirit:name>HSIZE_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2777,7 +2777,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_SOCDEBUG</spirit:name>
+ <spirit:name>HBURST_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2790,7 +2790,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_SOCDEBUG</spirit:name>
+ <spirit:name>HPROT_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2800,7 +2800,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_SOCDEBUG</spirit:name>
+ <spirit:name>HMASTER_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2813,7 +2813,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HWDATA_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2823,13 +2823,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_SOCDEBUG</spirit:name>
+ <spirit:name>HMASTLOCK_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_SOCDEBUG</spirit:name>
+ <spirit:name>HREADY_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
@@ -4363,7 +4363,7 @@
<!-- Output signals of Slave interfaces -->
<spirit:port>
- <spirit:name>HRDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HRDATA_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4373,13 +4373,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_SOCDEBUG</spirit:name>
+ <spirit:name>HREADYOUT_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_SOCDEBUG</spirit:name>
+ <spirit:name>HRESP_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4497,7 +4497,7 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
diff --git a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
index 70ebb8b..1e82bdb 100644
--- a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
+++ b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
@@ -38,12 +38,12 @@
<!--Slave interfaces -->
<spirit:busInterface>
- <spirit:name>AHBLiteInitiator_Slave__SOCDEBUG</spirit:name>
- <spirit:description>Slave port _SOCDEBUG</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG</spirit:name>
+ <spirit:description>Slave port _DEBUG</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__SOCDEBUG_MM"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DEBUG_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
@@ -80,7 +80,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_SOCDEBUG</spirit:name>
+ <spirit:name>HADDR_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -88,7 +88,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_SOCDEBUG</spirit:name>
+ <spirit:name>HTRANS_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -96,7 +96,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_SOCDEBUG</spirit:name>
+ <spirit:name>HWRITE_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -104,7 +104,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_SOCDEBUG</spirit:name>
+ <spirit:name>HSIZE_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -112,7 +112,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_SOCDEBUG</spirit:name>
+ <spirit:name>HBURST_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -120,7 +120,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_SOCDEBUG</spirit:name>
+ <spirit:name>HPROT_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -128,7 +128,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HWDATA_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -136,7 +136,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_SOCDEBUG</spirit:name>
+ <spirit:name>HMASTLOCK_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -146,7 +146,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HRDATA_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -154,7 +154,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_SOCDEBUG</spirit:name>
+ <spirit:name>HREADY_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -162,7 +162,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_SOCDEBUG</spirit:name>
+ <spirit:name>HRESP_DEBUG</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -1990,17 +1990,17 @@
<spirit:remapStates>
<spirit:remapState>
- <spirit:name>remap_0</spirit:name>
- <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -2173,8 +2173,8 @@
<spirit:memoryMaps>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__SOCDEBUG_MM</spirit:name>
- <spirit:description>_SOCDEBUG memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_MM</spirit:name>
+ <spirit:description>_DEBUG memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
@@ -2246,20 +2246,9 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteInitiator_Slave__SOCDEBUG_remap_0_remap_MM</spirit:name>
- <spirit:description>_SOCDEBUG remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteInitiator_Slave__SOCDEBUG_remap_n0_remap_MM</spirit:name>
- <spirit:description>_SOCDEBUG remap_n0 remap</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0 remap</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
@@ -2268,6 +2257,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
<spirit:memoryMap>
@@ -2496,17 +2496,6 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_0_remap_MM</spirit:name>
- <spirit:description>_CPU_0 remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_n0 remap</spirit:description>
@@ -2518,6 +2507,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_0_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
</spirit:memoryMaps>
@@ -2573,7 +2573,7 @@
<!-- Input signals of Slave interfaces -->
<spirit:port>
- <spirit:name>HADDR_SOCDEBUG</spirit:name>
+ <spirit:name>HADDR_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2583,7 +2583,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_SOCDEBUG</spirit:name>
+ <spirit:name>HTRANS_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2593,13 +2593,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_SOCDEBUG</spirit:name>
+ <spirit:name>HWRITE_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_SOCDEBUG</spirit:name>
+ <spirit:name>HSIZE_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2609,7 +2609,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_SOCDEBUG</spirit:name>
+ <spirit:name>HBURST_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2622,7 +2622,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_SOCDEBUG</spirit:name>
+ <spirit:name>HPROT_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2632,7 +2632,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HWDATA_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2642,7 +2642,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_SOCDEBUG</spirit:name>
+ <spirit:name>HMASTLOCK_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
@@ -3957,7 +3957,7 @@
<!-- Output signals of Slave interfaces -->
<spirit:port>
- <spirit:name>HRDATA_SOCDEBUG</spirit:name>
+ <spirit:name>HRDATA_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3967,13 +3967,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_SOCDEBUG</spirit:name>
+ <spirit:name>HREADY_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_SOCDEBUG</spirit:name>
+ <spirit:name>HRESP_DEBUG</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
@@ -4079,7 +4079,7 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
diff --git a/system/nanosoc_busmatrix/logs/nanosoc.log b/system/nanosoc_busmatrix/logs/nanosoc.log
index 1f19b5e..dbd71df 100644
--- a/system/nanosoc_busmatrix/logs/nanosoc.log
+++ b/system/nanosoc_busmatrix/logs/nanosoc.log
@@ -14,7 +14,7 @@
=
= BuildBusMatrix.pl
=
-= Run Date : 12/06/2023 11:01:02
+= Run Date : 15/06/2023 14:39:47
==============================================================
Script accepted the following parameters:
@@ -26,7 +26,7 @@ Script accepted the following parameters:
- Architecture type : 'ahb2'
- Arbitration scheme : 'burst'
- Address map : user defined
- - Connectivity mapping : _SOCDEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+ - Connectivity mapping : _DEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
_DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
_DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
_CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
@@ -41,14 +41,14 @@ Script accepted the following parameters:
- IPXact source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/ipxact/src'
- Overwrite mode : enabled
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP_1.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP_2.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v' file...
@@ -59,14 +59,14 @@ Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busm
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP_1.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP_2.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v' file...
@@ -75,36 +75,36 @@ Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busm
Creating the bus matrix variant...
- - Rendering 'nanosoc_target_output_BOOTROM_0.v'
+ - Rendering 'nanosoc_matrix_decode_CPU_0.v'
+ - Rendering 'nanosoc_target_output_EXPRAM_H.v'
+ - Rendering 'nanosoc_target_output_EXP_1.v'
- Rendering 'nanosoc_target_output_SYSIO.v'
- - Rendering 'nanosoc_target_output_EXPRAM_L.v'
- - Rendering 'nanosoc_busmatrix_lite.v'
- - Rendering 'nanosoc_matrix_decode_DMAC_0.v'
- - Rendering 'nanosoc_target_output_EXP_2.v'
+ - Rendering 'nanosoc_inititator_input.v'
- Rendering 'nanosoc_arbiter_SYSIO.v'
- Rendering 'nanosoc_arbiter_EXPRAM_L.v'
- - Rendering 'nanosoc_arbiter_BOOTROM_0.v'
- - Rendering 'nanosoc_arbiter_EXP_1.v'
+ - Rendering 'nanosoc_target_output_IMEM_0.v'
+ - Rendering 'nanosoc_target_output_EXPRAM_L.v'
+ - Rendering 'nanosoc_target_output_DMEM_0.v'
+ - Rendering 'nanosoc_arbiter_EXP_2.v'
+ - Rendering 'nanosoc_target_output_EXP_2.v'
+ - Rendering 'nanosoc_arbiter_SYSTABLE.v'
+ - Rendering 'nanosoc_target_output_BOOTROM_0.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
- Rendering 'nanosoc_arbiter_DMEM_0.v'
- - Rendering 'nanosoc_target_output_EXP_1.v'
- - Rendering 'nanosoc_matrix_decode_CPU_0.v'
- - Rendering 'nanosoc_inititator_input.v'
- - Rendering 'nanosoc_arbiter_EXP_0.v'
+ - Rendering 'nanosoc_target_output_SYSTABLE.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_0.v'
- Rendering 'nanosoc_busmatrix_lite.xml'
+ - Rendering 'nanosoc_arbiter_EXP_1.v'
+ - Rendering 'nanosoc_arbiter_EXP_0.v'
+ - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_busmatrix_lite.v'
- Rendering 'nanosoc_busmatrix_default_slave.v'
- - Rendering 'nanosoc_matrix_decode_SOCDEBUG.v'
- Rendering 'nanosoc_target_output_EXP_0.v'
- - Rendering 'nanosoc_target_output_EXPRAM_H.v'
- - Rendering 'nanosoc_target_output_SYSTABLE.v'
- - Rendering 'nanosoc_target_output_DMEM_0.v'
- - Rendering 'nanosoc_arbiter_EXP_2.v'
- - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
- - Rendering 'nanosoc_arbiter_SYSTABLE.v'
- Rendering 'nanosoc_arbiter_EXPRAM_H.v'
- - Rendering 'nanosoc_target_output_IMEM_0.v'
- - Rendering 'nanosoc_busmatrix.v'
- Rendering 'nanosoc_arbiter_IMEM_0.v'
- - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_matrix_decode_DEBUG.v'
+ - Rendering 'nanosoc_arbiter_BOOTROM_0.v'
+ - Rendering 'nanosoc_busmatrix.v'
Done!
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
index 7ab092a..271c3ca 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
@@ -35,7 +35,7 @@
// - Routing data width of 32 bits,
// - Arbiter type 'burst',
// - Connectivity mapping:
-// _SOCDEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+// _DEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
// _DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
// _DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
// _CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
@@ -55,17 +55,17 @@ module nanosoc_busmatrix (
REMAP,
// Input port SI0 (inputs from master 0)
- HSEL_SOCDEBUG,
- HADDR_SOCDEBUG,
- HTRANS_SOCDEBUG,
- HWRITE_SOCDEBUG,
- HSIZE_SOCDEBUG,
- HBURST_SOCDEBUG,
- HPROT_SOCDEBUG,
- HMASTER_SOCDEBUG,
- HWDATA_SOCDEBUG,
- HMASTLOCK_SOCDEBUG,
- HREADY_SOCDEBUG,
+ HSEL_DEBUG,
+ HADDR_DEBUG,
+ HTRANS_DEBUG,
+ HWRITE_DEBUG,
+ HSIZE_DEBUG,
+ HBURST_DEBUG,
+ HPROT_DEBUG,
+ HMASTER_DEBUG,
+ HWDATA_DEBUG,
+ HMASTLOCK_DEBUG,
+ HREADY_DEBUG,
// Input port SI1 (inputs from master 1)
HSEL_DMAC_0,
@@ -292,9 +292,9 @@ module nanosoc_busmatrix (
HREADYMUX_SYSTABLE,
// Input port SI0 (outputs to master 0)
- HRDATA_SOCDEBUG,
- HREADYOUT_SOCDEBUG,
- HRESP_SOCDEBUG,
+ HRDATA_DEBUG,
+ HREADYOUT_DEBUG,
+ HRESP_DEBUG,
// Input port SI1 (outputs to master 1)
HRDATA_DMAC_0,
@@ -329,17 +329,17 @@ module nanosoc_busmatrix (
input [3:0] REMAP; // REMAP input
// Input port SI0 (inputs from master 0)
- input HSEL_SOCDEBUG; // Slave Select
- input [31:0] HADDR_SOCDEBUG; // Address bus
- input [1:0] HTRANS_SOCDEBUG; // Transfer type
- input HWRITE_SOCDEBUG; // Transfer direction
- input [2:0] HSIZE_SOCDEBUG; // Transfer size
- input [2:0] HBURST_SOCDEBUG; // Burst type
- input [3:0] HPROT_SOCDEBUG; // Protection control
- input [3:0] HMASTER_SOCDEBUG; // Master select
- input [31:0] HWDATA_SOCDEBUG; // Write data
- input HMASTLOCK_SOCDEBUG; // Locked Sequence
- input HREADY_SOCDEBUG; // Transfer done
+ input HSEL_DEBUG; // Slave Select
+ input [31:0] HADDR_DEBUG; // Address bus
+ input [1:0] HTRANS_DEBUG; // Transfer type
+ input HWRITE_DEBUG; // Transfer direction
+ input [2:0] HSIZE_DEBUG; // Transfer size
+ input [2:0] HBURST_DEBUG; // Burst type
+ input [3:0] HPROT_DEBUG; // Protection control
+ input [3:0] HMASTER_DEBUG; // Master select
+ input [31:0] HWDATA_DEBUG; // Write data
+ input HMASTLOCK_DEBUG; // Locked Sequence
+ input HREADY_DEBUG; // Transfer done
// Input port SI1 (inputs from master 1)
input HSEL_DMAC_0; // Slave Select
@@ -566,9 +566,9 @@ module nanosoc_busmatrix (
output HREADYMUX_SYSTABLE; // Transfer done
// Input port SI0 (outputs to master 0)
- output [31:0] HRDATA_SOCDEBUG; // Read data bus
- output HREADYOUT_SOCDEBUG; // HREADY feedback
- output [1:0] HRESP_SOCDEBUG; // Transfer response
+ output [31:0] HRDATA_DEBUG; // Read data bus
+ output HREADYOUT_DEBUG; // HREADY feedback
+ output [1:0] HRESP_DEBUG; // Transfer response
// Input port SI1 (outputs to master 1)
output [31:0] HRDATA_DMAC_0; // Read data bus
@@ -601,21 +601,21 @@ module nanosoc_busmatrix (
wire [3:0] REMAP; // REMAP signal
// Input Port SI0
- wire HSEL_SOCDEBUG; // Slave Select
- wire [31:0] HADDR_SOCDEBUG; // Address bus
- wire [1:0] HTRANS_SOCDEBUG; // Transfer type
- wire HWRITE_SOCDEBUG; // Transfer direction
- wire [2:0] HSIZE_SOCDEBUG; // Transfer size
- wire [2:0] HBURST_SOCDEBUG; // Burst type
- wire [3:0] HPROT_SOCDEBUG; // Protection control
- wire [3:0] HMASTER_SOCDEBUG; // Master select
- wire [31:0] HWDATA_SOCDEBUG; // Write data
- wire HMASTLOCK_SOCDEBUG; // Locked Sequence
- wire HREADY_SOCDEBUG; // Transfer done
-
- wire [31:0] HRDATA_SOCDEBUG; // Read data bus
- wire HREADYOUT_SOCDEBUG; // HREADY feedback
- wire [1:0] HRESP_SOCDEBUG; // Transfer response
+ wire HSEL_DEBUG; // Slave Select
+ wire [31:0] HADDR_DEBUG; // Address bus
+ wire [1:0] HTRANS_DEBUG; // Transfer type
+ wire HWRITE_DEBUG; // Transfer direction
+ wire [2:0] HSIZE_DEBUG; // Transfer size
+ wire [2:0] HBURST_DEBUG; // Burst type
+ wire [3:0] HPROT_DEBUG; // Protection control
+ wire [3:0] HMASTER_DEBUG; // Master select
+ wire [31:0] HWDATA_DEBUG; // Write data
+ wire HMASTLOCK_DEBUG; // Locked Sequence
+ wire HREADY_DEBUG; // Transfer done
+
+ wire [31:0] HRDATA_DEBUG; // Read data bus
+ wire HREADYOUT_DEBUG; // HREADY feedback
+ wire [1:0] HRESP_DEBUG; // Transfer response
// Input Port SI1
wire HSEL_DMAC_0; // Slave Select
@@ -1079,16 +1079,16 @@ module nanosoc_busmatrix (
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_SOCDEBUG),
- .HADDRS (HADDR_SOCDEBUG),
- .HTRANSS (HTRANS_SOCDEBUG),
- .HWRITES (HWRITE_SOCDEBUG),
- .HSIZES (HSIZE_SOCDEBUG),
- .HBURSTS (HBURST_SOCDEBUG),
- .HPROTS (HPROT_SOCDEBUG),
- .HMASTERS (HMASTER_SOCDEBUG),
- .HMASTLOCKS (HMASTLOCK_SOCDEBUG),
- .HREADYS (HREADY_SOCDEBUG),
+ .HSELS (HSEL_DEBUG),
+ .HADDRS (HADDR_DEBUG),
+ .HTRANSS (HTRANS_DEBUG),
+ .HWRITES (HWRITE_DEBUG),
+ .HSIZES (HSIZE_DEBUG),
+ .HBURSTS (HBURST_DEBUG),
+ .HPROTS (HPROT_DEBUG),
+ .HMASTERS (HMASTER_DEBUG),
+ .HMASTLOCKS (HMASTLOCK_DEBUG),
+ .HREADYS (HREADY_DEBUG),
// Internal Response
.active_ip (i_active0),
@@ -1096,8 +1096,8 @@ module nanosoc_busmatrix (
.resp_ip (i_resp0),
// Input Port Response
- .HREADYOUTS (HREADYOUT_SOCDEBUG),
- .HRESPS (HRESP_SOCDEBUG),
+ .HREADYOUTS (HREADYOUT_DEBUG),
+ .HRESPS (HRESP_DEBUG),
// Internal Address/Control Signals
.sel_ip (i_sel0),
@@ -1244,7 +1244,7 @@ module nanosoc_busmatrix (
// Matrix decoder for SI0
- nanosoc_matrix_decode_SOCDEBUG u_nanosoc_matrix_decode_socdebug (
+ nanosoc_matrix_decode_DEBUG u_nanosoc_matrix_decode_debug (
// Common AHB signals
.HCLK (HCLK),
@@ -1254,7 +1254,7 @@ module nanosoc_busmatrix (
.remapping_dec ( REMAP[0] ),
// Signals from Input stage SI0
- .HREADYS (HREADY_SOCDEBUG),
+ .HREADYS (HREADY_DEBUG),
.sel_dec (i_sel0),
.decode_addr_dec (i_addr0[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans0),
@@ -1333,7 +1333,7 @@ module nanosoc_busmatrix (
.active_dec (i_active0),
.HREADYOUTS (i_readyout0),
.HRESPS (i_resp0),
- .HRDATAS (HRDATA_SOCDEBUG)
+ .HRDATAS (HRDATA_DEBUG)
);
@@ -1620,7 +1620,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -1706,7 +1706,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -1792,7 +1792,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -1878,7 +1878,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -1964,7 +1964,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -2050,7 +2050,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -2136,7 +2136,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -2222,7 +2222,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -2308,7 +2308,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
@@ -2394,7 +2394,7 @@ module nanosoc_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_SOCDEBUG),
+ .wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
// Port 3 Signals
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
index 68a8cf5..ffe248a 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
@@ -40,14 +40,14 @@ module nanosoc_busmatrix_lite (
REMAP,
// Input port SI0 (inputs from master 0)
- HADDR_SOCDEBUG,
- HTRANS_SOCDEBUG,
- HWRITE_SOCDEBUG,
- HSIZE_SOCDEBUG,
- HBURST_SOCDEBUG,
- HPROT_SOCDEBUG,
- HWDATA_SOCDEBUG,
- HMASTLOCK_SOCDEBUG,
+ HADDR_DEBUG,
+ HTRANS_DEBUG,
+ HWRITE_DEBUG,
+ HSIZE_DEBUG,
+ HBURST_DEBUG,
+ HPROT_DEBUG,
+ HWDATA_DEBUG,
+ HMASTLOCK_DEBUG,
// Input port SI1 (inputs from master 1)
HADDR_DMAC_0,
@@ -255,9 +255,9 @@ module nanosoc_busmatrix_lite (
HREADYMUX_SYSTABLE,
// Input port SI0 (outputs to master 0)
- HRDATA_SOCDEBUG,
- HREADY_SOCDEBUG,
- HRESP_SOCDEBUG,
+ HRDATA_DEBUG,
+ HREADY_DEBUG,
+ HRESP_DEBUG,
// Input port SI1 (outputs to master 1)
HRDATA_DMAC_0,
@@ -291,14 +291,14 @@ module nanosoc_busmatrix_lite (
input [3:0] REMAP; // System Address REMAP control
// Input port SI0 (inputs from master 0)
- input [31:0] HADDR_SOCDEBUG; // Address bus
- input [1:0] HTRANS_SOCDEBUG; // Transfer type
- input HWRITE_SOCDEBUG; // Transfer direction
- input [2:0] HSIZE_SOCDEBUG; // Transfer size
- input [2:0] HBURST_SOCDEBUG; // Burst type
- input [3:0] HPROT_SOCDEBUG; // Protection control
- input [31:0] HWDATA_SOCDEBUG; // Write data
- input HMASTLOCK_SOCDEBUG; // Locked Sequence
+ input [31:0] HADDR_DEBUG; // Address bus
+ input [1:0] HTRANS_DEBUG; // Transfer type
+ input HWRITE_DEBUG; // Transfer direction
+ input [2:0] HSIZE_DEBUG; // Transfer size
+ input [2:0] HBURST_DEBUG; // Burst type
+ input [3:0] HPROT_DEBUG; // Protection control
+ input [31:0] HWDATA_DEBUG; // Write data
+ input HMASTLOCK_DEBUG; // Locked Sequence
// Input port SI1 (inputs from master 1)
input [31:0] HADDR_DMAC_0; // Address bus
@@ -506,9 +506,9 @@ module nanosoc_busmatrix_lite (
output HREADYMUX_SYSTABLE; // Transfer done
// Input port SI0 (outputs to master 0)
- output [31:0] HRDATA_SOCDEBUG; // Read data bus
- output HREADY_SOCDEBUG; // HREADY feedback
- output HRESP_SOCDEBUG; // Transfer response
+ output [31:0] HRDATA_DEBUG; // Read data bus
+ output HREADY_DEBUG; // HREADY feedback
+ output HRESP_DEBUG; // Transfer response
// Input port SI1 (outputs to master 1)
output [31:0] HRDATA_DMAC_0; // Read data bus
@@ -540,18 +540,18 @@ module nanosoc_busmatrix_lite (
wire [3:0] REMAP; // System REMAP signal
// Input Port SI0
- wire [31:0] HADDR_SOCDEBUG; // Address bus
- wire [1:0] HTRANS_SOCDEBUG; // Transfer type
- wire HWRITE_SOCDEBUG; // Transfer direction
- wire [2:0] HSIZE_SOCDEBUG; // Transfer size
- wire [2:0] HBURST_SOCDEBUG; // Burst type
- wire [3:0] HPROT_SOCDEBUG; // Protection control
- wire [31:0] HWDATA_SOCDEBUG; // Write data
- wire HMASTLOCK_SOCDEBUG; // Locked Sequence
-
- wire [31:0] HRDATA_SOCDEBUG; // Read data bus
- wire HREADY_SOCDEBUG; // HREADY feedback
- wire HRESP_SOCDEBUG; // Transfer response
+ wire [31:0] HADDR_DEBUG; // Address bus
+ wire [1:0] HTRANS_DEBUG; // Transfer type
+ wire HWRITE_DEBUG; // Transfer direction
+ wire [2:0] HSIZE_DEBUG; // Transfer size
+ wire [2:0] HBURST_DEBUG; // Burst type
+ wire [3:0] HPROT_DEBUG; // Protection control
+ wire [31:0] HWDATA_DEBUG; // Write data
+ wire HMASTLOCK_DEBUG; // Locked Sequence
+
+ wire [31:0] HRDATA_DEBUG; // Read data bus
+ wire HREADY_DEBUG; // HREADY feedback
+ wire HRESP_DEBUG; // Transfer response
// Input Port SI1
wire [31:0] HADDR_DMAC_0; // Address bus
@@ -762,7 +762,7 @@ module nanosoc_busmatrix_lite (
wire [3:0] tie_hi_4;
wire tie_hi;
wire tie_low;
- wire [1:0] i_hresp_SOCDEBUG;
+ wire [1:0] i_hresp_DEBUG;
wire [1:0] i_hresp_DMAC_0;
wire [1:0] i_hresp_DMAC_1;
wire [1:0] i_hresp_CPU_0;
@@ -797,7 +797,7 @@ module nanosoc_busmatrix_lite (
assign tie_low = 1'b0;
- assign HRESP_SOCDEBUG = i_hresp_SOCDEBUG[0];
+ assign HRESP_DEBUG = i_hresp_DEBUG[0];
assign HRESP_DMAC_0 = i_hresp_DMAC_0[0];
@@ -823,20 +823,20 @@ module nanosoc_busmatrix_lite (
.REMAP (REMAP),
// Input port SI0 signals
- .HSEL_SOCDEBUG (tie_hi),
- .HADDR_SOCDEBUG (HADDR_SOCDEBUG),
- .HTRANS_SOCDEBUG (HTRANS_SOCDEBUG),
- .HWRITE_SOCDEBUG (HWRITE_SOCDEBUG),
- .HSIZE_SOCDEBUG (HSIZE_SOCDEBUG),
- .HBURST_SOCDEBUG (HBURST_SOCDEBUG),
- .HPROT_SOCDEBUG (HPROT_SOCDEBUG),
- .HWDATA_SOCDEBUG (HWDATA_SOCDEBUG),
- .HMASTLOCK_SOCDEBUG (HMASTLOCK_SOCDEBUG),
- .HMASTER_SOCDEBUG (tie_hi_4),
- .HREADY_SOCDEBUG (HREADY_SOCDEBUG),
- .HRDATA_SOCDEBUG (HRDATA_SOCDEBUG),
- .HREADYOUT_SOCDEBUG (HREADY_SOCDEBUG),
- .HRESP_SOCDEBUG (i_hresp_SOCDEBUG),
+ .HSEL_DEBUG (tie_hi),
+ .HADDR_DEBUG (HADDR_DEBUG),
+ .HTRANS_DEBUG (HTRANS_DEBUG),
+ .HWRITE_DEBUG (HWRITE_DEBUG),
+ .HSIZE_DEBUG (HSIZE_DEBUG),
+ .HBURST_DEBUG (HBURST_DEBUG),
+ .HPROT_DEBUG (HPROT_DEBUG),
+ .HWDATA_DEBUG (HWDATA_DEBUG),
+ .HMASTLOCK_DEBUG (HMASTLOCK_DEBUG),
+ .HMASTER_DEBUG (tie_hi_4),
+ .HREADY_DEBUG (HREADY_DEBUG),
+ .HRDATA_DEBUG (HRDATA_DEBUG),
+ .HREADYOUT_DEBUG (HREADY_DEBUG),
+ .HRESP_DEBUG (i_hresp_DEBUG),
// Input port SI1 signals
.HSEL_DMAC_0 (tie_hi),
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
index ea7c5f4..f65e6d4 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
@@ -33,7 +33,7 @@
-module nanosoc_matrix_decode_SOCDEBUG (
+module nanosoc_matrix_decode_DEBUG (
// Common AHB signals
HCLK,
diff --git a/system/nanosoc_busmatrix/xml/nanosoc.xml b/system/nanosoc_busmatrix/xml/nanosoc.xml
index 417b2a9..f0ec0ce 100644
--- a/system/nanosoc_busmatrix/xml/nanosoc.xml
+++ b/system/nanosoc_busmatrix/xml/nanosoc.xml
@@ -61,7 +61,7 @@
<!-- Slave interface definitions -->
- <slave_interface name="_SOCDEBUG">
+ <slave_interface name="_DEBUG">
<sparse_connect interface="_BOOTROM_0"/>
<sparse_connect interface="_IMEM_0"/>
<sparse_connect interface="_DMEM_0"/>
diff --git a/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v b/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
new file mode 100644
index 0000000..a66d440
--- /dev/null
+++ b/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
@@ -0,0 +1,115 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Debug Subsystem - Contains SoCDebug Module
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.masptone@soton.ac.uk)
+//
+// Copyright (C) 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_ss_debug #(
+ // System Parameters
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+
+ // SoCDebug Parameters
+ parameter PROMPT_CHAR = "]",
+ parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
+ parameter integer FT1248_CLKON = 1 // FTDI clock always on - else quiet when no access
+)(
+ // System Clocks and Resets
+ input wire SYS_HCLK,
+ input wire SYS_HRESETn,
+ input wire SYS_PCLK,
+ input wire SYS_PCLKG,
+ input wire SYS_PRESETn,
+
+ // AHB-lite Master Interface - ADP
+ output wire [31:0] DEBUG_HADDR,
+ output wire [ 2:0] DEBUG_HBURST,
+ output wire DEBUG_HMASTLOCK,
+ output wire [ 3:0] DEBUG_HPROT,
+ output wire [ 2:0] DEBUG_HSIZE,
+ output wire [ 1:0] DEBUG_HTRANS,
+ output wire [31:0] DEBUG_HWDATA,
+ output wire DEBUG_HWRITE,
+ input wire [31:0] DEBUG_HRDATA,
+ input wire DEBUG_HREADY,
+ input wire DEBUG_HRESP,
+
+ // APB Slave Interface - USRT
+ input wire DEBUG_PSEL, // Device select
+ input wire [11:2] DEBUG_PADDR, // Address
+ input wire DEBUG_PENABLE, // Transfer control
+ input wire DEBUG_PWRITE, // Write control
+ input wire [31:0] DEBUG_PWDATA, // Write data
+ output wire [31:0] DEBUG_PRDATA, // Read data
+ output wire DEBUG_PREADY, // Device ready
+ output wire DEBUG_PSLVERR, // Device error response
+
+ // FT1248 Interace - FT1248
+ output wire FT_CLK_O, // SCLK
+ output wire FT_SSN_O, // SS_N
+ input wire FT_MISO_I, // MISO
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
+ input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
+ input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
+
+ // GPIO interface
+ output wire [7:0] GPO8,
+ input wire [7:0] GPI8
+);
+
+ socdebug_ahb #(
+ .PROMPT_CHAR(PROMPT_CHAR),
+ .FT1248_WIDTH(FT1248_WIDTH),
+ .FT1248_CLKON(FT1248_CLKON)
+ ) u_socdebbug (
+ // AHB-lite Master Interface - ADP
+ .HCLK(DEBUG_SYS_HCLK),
+ .HRESETn(DEBUG_SYS_HRESETn),
+ .HADDR32_o(DEBUG_HADDR),
+ .HBURST3_o(DEBUG_HBURST),
+ .HMASTLOCK_o(DEBUG_HMASTLOCK),
+ .HPROT4_o(DEBUG_HPROT),
+ .HSIZE3_o(DEBUG_HSIZE),
+ .HTRANS2_o(DEBUG_HTRANS),
+ .HWDATA32_o(DEBUG_HWDATA),
+ .HWRITE_o(DEBUG_HWRITE),
+ .HRDATA32_i(DEBUG_HRDATA32),
+ .HREADY_i(DEBUG_HREADY),
+ .HRESP_i(DEBUG_HRESP),
+
+ // APB Slave Interface - USRT
+ .PCLK(DEBUG_PCLK),
+ .PCLKG(DEBUG_PCLKG),
+ .PRESETn(DEBUG_PRESETn),
+ .PSEL_i(DEBUG_PSEL),
+ .PADDR_i(DEBUG_PADDR),
+ .PENABLE_i(DEBUG_PENABLE),
+ .PWRITE_i(DEBUG_PWRITE),
+ .PWDATA_i(DEBUG_PWDATA),
+ .PRDATA_o(DEBUG_PRDATA),
+ .PREADY_o(DEBUG_PREADY),
+ .PSLVERR_o(DEBUG_PSLVERR),
+
+ // FT1248 Interace - FT1248
+ .FT_CLK_O(FT_CLK_O),
+ .FT_SSN_O(FT_SSN_O),
+ .FT_MISO_I(FT_MISO_I),
+ .FT_MIOSIO_O(FT_MIOSIO_O),
+ .FT_MIOSIO_E(FT_MIOSIO_E),
+ .FT_MIOSIO_Z(FT_MIOSIO_Z),
+ .FT_MIOSIO_I(FT_MIOSIO_I),
+ .FT_CLKDIV(FT_CLKDIV),
+
+ // GPIO interface
+ .GPO8_o(GPO8_o),
+ .GPI8_i(GPI8_i)
+ );
+
+endmodule
\ No newline at end of file
--
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