diff --git a/system/fpga_imp/python_verification/ADP_test.py b/system/fpga_imp/python_verification/ADP_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..dbd34716c95e1d63a7e81ac69498b7cd31409527
--- /dev/null
+++ b/system/fpga_imp/python_verification/ADP_test.py
@@ -0,0 +1,21 @@
+import sys
+from drivers/ADP_UART_driver import ADP
+
+adp = ADP("COM7", 0x80020000)
+adp.write32(adp.CTRL_REG,0x00)
+print(adp.read(adp.RX_FIF0,100))
+
+adp.write32(adp.TX_FIFO,0x1b)
+print(adp.read(adp.RX_FIF0,500))
+adp.write(adp.TX_FIFO,'A 0x00000000\nR 4\n')
+print(adp.read(adp.RX_FIF0,500))
+adp.write(adp.TX_FIFO,'A 0x10000000\nR 4\n')
+print(adp.read(adp.RX_FIF0,500))
+adp.write(adp.TX_FIFO,'A 0x20000000\nR 4\n')
+print(adp.read(adp.RX_FIF0,100))
+adp.write(adp.TX_FIFO,'A 0x20000000\nW 0x11223344\n')
+print(adp.read(adp.RX_FIF0,100))
+adp.write(adp.TX_FIFO,'A 0x20000000\nR 4\n')
+print(adp.read(adp.RX_FIF0,100))
+
+
diff --git a/system/fpga_imp/python_verification/bootrom_test.py b/system/fpga_imp/python_verification/bootrom_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/system/fpga_imp/python_verification/drivers/ADP_UART_driver.py b/system/fpga_imp/python_verification/drivers/ADP_UART_driver.py
new file mode 100644
index 0000000000000000000000000000000000000000..df4aafc63b747490e35c958bdd9c7d345eb45c20
--- /dev/null
+++ b/system/fpga_imp/python_verification/drivers/ADP_UART_driver.py
@@ -0,0 +1,169 @@
+import serial
+from time import time
+
+class ADP:
+    def __init__(self, iface = '/dev/ttyUSB2', base_addr = 0x80020000, baud = 115200):
+        self.interface  = iface
+        self.baud       = baud
+        self.uart       = None
+        self.prog_cb    = None
+        self.CMD_WRITE  = 0x10
+        self.CMD_READ   = 0x11
+        self.MAX_SIZE   = 255
+        self.BLOCK_SIZE = 128
+        self.GPIO_ADDR  = 0xF0000000
+        self.STS_ADDR   = 0xF0000004
+        self.BASE_ADDR  = base_addr
+        self.RX_FIF0    = 0x00
+        self.TX_FIFO    = 0x04
+        self.STAT_REG   = 0x08
+        self.CTRL_REG   = 0x0C
+        self.RX_VALID   = 0
+        self.TX_FULL    = 3
+
+    ##################################################################
+    # connect: Open serial connection
+    ##################################################################
+    def connect(self):
+        self.uart = serial.Serial(
+            port=self.interface,
+            baudrate=self.baud,
+            parity=serial.PARITY_NONE,
+            stopbits=serial.STOPBITS_ONE,
+            bytesize=serial.EIGHTBITS
+        )
+        self.uart.isOpen()
+
+        # Check status register
+        value = self.checkStatus()
+        if ((value & 0xFFFF0000) != 0xcafe0000):
+            raise Exception("Target not responding correctly, check interface / baud rate...")
+        
+    def checkStatus(self):
+        addr = self.STS_ADDR
+        cmd = bytearray([self.CMD_READ, 
+                         4, 
+                        (addr >> 24) & 0xFF, 
+                        (addr >> 16) & 0xFF, 
+                        (addr >> 8) & 0xFF, 
+                        (addr >> 0) & 0xFF])
+        self.uart.write(cmd)
+
+        value = 0
+        idx   = 0
+        while (idx < 4):
+            b = self.uart.read(1)
+            value |= (ord(b) << (idx * 8))
+            idx += 1
+
+        return value
+    ##################################################################
+    # read32: Read a word from a specified address
+    ##################################################################
+    def read32(self, offset):
+        # Connect if required
+        if self.uart == None:
+            self.connect()
+
+        addr = self.BASE_ADDR+offset
+        # Send read command
+        cmd = bytearray([self.CMD_READ, 
+                         4, 
+                        (addr >> 24) & 0xFF, 
+                        (addr >> 16) & 0xFF, 
+                        (addr >> 8) & 0xFF, 
+                        (addr >> 0) & 0xFF])
+        self.uart.write(cmd)
+
+        value = 0
+        idx   = 0
+        while (idx < 4):
+            b = self.uart.read(1)
+            value |= (ord(b) << (idx * 8))
+            idx += 1
+
+        return value
+
+    ##################################################################
+    # write32: Write a word to a specified address
+    ##################################################################
+    def write32(self, offset, value):
+        # Connect if required
+        if self.uart == None:
+            self.connect()
+
+        addr = self.BASE_ADDR + offset
+
+        # Send write command
+        cmd = bytearray([self.CMD_WRITE,
+                         4, 
+                        (addr >> 24)  & 0xFF, 
+                        (addr >> 16)  & 0xFF, 
+                        (addr >> 8)   & 0xFF, 
+                        (addr >> 0)   & 0xFF, 
+                        (value >> 0)  & 0xFF, 
+                        (value>> 8)  & 0xFF, 
+                        (value >> 16)  & 0xFF, 
+                        (value >> 24)  & 0xFF])
+        self.uart.write(cmd)
+
+    ##################################################################
+    # write: Write a block of data to a specified address
+    ##################################################################
+    def write(self, addr, buf, timeout = 1):
+        # Connect if required
+        if self.uart == None:
+            self.connect()
+
+        stop_time = time() + timeout
+        wr_count = 0
+        for i in buf:
+            while (self.read32(self.STAT_REG) & 1 << self.TX_FULL) and (time() < stop_time):
+                pass
+            if time() > stop_time:
+                wr_count = -1
+                break
+            self.write32(addr,ord(i))
+            wr_count += 1
+        return wr_count
+
+    ##################################################################
+    # read: Read a block of data from a specified address
+    ##################################################################
+    def read(self, addr, length):
+        # Connect if required
+        if self.uart == None:
+            self.connect()
+
+        buf = ""
+        timeout = 1
+        stop_time = time() + timeout
+        for i in range(length):
+            while(not(self.read32(self.STAT_REG) & 1 << self.RX_VALID) and (time() < stop_time)):
+                pass
+            if time() > stop_time:
+                break
+            buf += chr(self.read32(addr))
+            stop_time = time() + timeout
+
+        return buf
+    
+    def readLine(self,addr):
+        if self.uart == None:
+            self.connect()
+
+        buf = ""
+        timeout = 1
+        stop_time = time() + timeout
+        stop=False
+        while(not(stop)):
+            while(not(self.read32(self.STAT_REG) & 1 << self.RX_VALID) and (time() < stop_time)):
+                pass
+            if time() > stop_time:
+                break
+            next_chr = chr(self.read32(addr))
+            buf += next_chr
+            stop_time = time() + timeout
+            if (next_chr == '\n'):
+                stop = True
+        return buf
\ No newline at end of file
diff --git a/system/fpga_imp/python_verification/drivers/NanoSoC_Verification.py b/system/fpga_imp/python_verification/drivers/NanoSoC_Verification.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/system/fpga_imp/python_verification/romtable_test.py b/system/fpga_imp/python_verification/romtable_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391