From 2b8bbcb16c3b36dd7995c1b7469e4069cadfd953 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Mon, 4 Dec 2023 13:50:08 +0000
Subject: [PATCH] updated testbench ready for test mode support
---
.../nanosoc_chip/chip/verilog/nanosoc_chip.v | 36 +++++++++++++++----
.../pads/glib/verilog/nanosoc_chip_pads.v | 18 ++++++++--
verif/control/verilog/nanosoc_clkreset.v | 26 ++++++++++----
verif/tb/verilog/nanosoc_tb.v | 11 ++++--
verif/tb/verilog/nanosoc_tb_qs.v | 11 ++++--
5 files changed, 81 insertions(+), 21 deletions(-)
diff --git a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 192f534..4981b33 100644
--- a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -11,14 +11,29 @@
`include "gen_defines.v"
module nanosoc_chip #(
- parameter integer FT1248_WIDTH = 1 // FTDI Interface 1,2,4 width supported
+ parameter integer FT1248_WIDTH = 1, // Only 1-bit serial supported for min pincount
+ parameter integer GPIO_TIO = 4 // reconfigure lowest four GPIO ports for test
)(
`ifdef POWER_PINS
- inout wire VDDIO,
- inout wire VSSIO,
inout wire VDD,
inout wire VSS,
inout wire VDDACC,
+`endif
+`ifdef ASIC_TEST_PORTS
+ input wire diag_mode,
+ input wire diag_ctrl,
+ input wire scan_mode,
+ input wire scan_enable,
+ input wire [GPIO_TIO-1:0] scan_in, // soc test scan chain inputs
+ output wire [GPIO_TIO-1:0] scan_out, // soc test scan chain outputs
+ input wire bist_mode,
+ input wire bist_enable,
+ input wire [GPIO_TIO-1:0] bist_in, // soc bist control inputs
+ output wire [GPIO_TIO-1:0] bist_out, // soc test status outputs
+ input wire alt_mode, // ALT MODE = UART
+ input wire uart_rxd_i, // UART RXD
+ output wire uart_txd_o, // UART TXD
+ input wire swd_mode, // SWD mode
`endif
input wire clk_i,
// output wire xtal_clk_o,
@@ -95,11 +110,20 @@ module nanosoc_chip #(
// clk_i
assign PLL_CLK = clk_i; // Default to no PLL
-
+
+`ifdef ASIC_TEST_PORTS
+ assign SYS_SCANENABLE = scan_enable;
+ assign SYS_TESTMODE = scan_mode;
+ assign SYS_SCANINHCLK = 1'b1;
+ assign scan_out = scan_in;
+ assign bist_out = bist_in;
+ assign uart_txd_o = uart_rxd_i;
+`else
assign SYS_SCANENABLE = test_i & swdio_i;
assign SYS_TESTMODE = test_i;
- assign SYS_SCANINHCLK = test_i & swdclk_i;
-
+ assign SYS_SCANINHCLK = 1'b1;
+`endif
+
//--------------------------
// Clock Wiring
//--------------------------
diff --git a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
index 7d41fc8..6c11506 100644
--- a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+++ b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
@@ -80,11 +80,25 @@ module nanosoc_chip_pads (
nanosoc_chip u_nanosoc_chip (
`ifdef POWER_PINS
- .VDDIO (VDDIO),
- .VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
.VDDACC (VDDACC),
+`endif
+`ifdef ASIC_TEST_PORTS
+ .diag_mode (1'b0),
+ .diag_ctrl (1'b0),
+ .scan_mode (1'b0),
+ .scan_enable (1'b0),
+ .scan_in (4'b0000), // soc test scan chain inputs
+ .scan_out ( ), // soc test scan chain outputs
+ .bist_mode (1'b0),
+ .bist_enable (1'b0),
+ .bist_in (4'b0000), // soc bist control inputs
+ .bist_out ( ), // soc test status outputs
+ .alt_mode (1'b0), // ALT MODE = UART
+ .uart_rxd_i (1'b1), // UART RXD
+ .uart_txd_o ( ), // UART TXD
+ .swd_mode (1'b1), // SWD mode
`endif
.clk_i(clk_i),
.test_i(test_i),
diff --git a/verif/control/verilog/nanosoc_clkreset.v b/verif/control/verilog/nanosoc_clkreset.v
index fc1deef..90af3c8 100644
--- a/verif/control/verilog/nanosoc_clkreset.v
+++ b/verif/control/verilog/nanosoc_clkreset.v
@@ -38,25 +38,37 @@
module nanosoc_clkreset(
output wire CLK,
- output wire NRST);
+ output wire NRST,
+ output wire NRST_early,
+ output wire NRST_late,
+ output wire NRST_ext
+ );
reg clock_q;
- reg reset_n_q;
+ reg [15:0] shifter;
+
initial
begin
- clock_q <= 1'b0;
- reset_n_q <= 1'b0;
+ clock_q <= 1'b0;
+ shifter <= 16'h0000;
#40 clock_q <= 1'b1;
- #100 reset_n_q <= 1'b1;
end
always @(clock_q)
// #25 clock_q <= ~clock_q; // 50ns period 20MHz - 9600 baud
- #5 clock_q <= ~clock_q; // 10ns period, 100MHz - 48000 baud
+ #5 clock_q <= !clock_q; // 10ns period, 100MHz - 48000 baud
assign CLK = clock_q;
- assign NRST = reset_n_q;
+
+ always @(posedge clock_q)
+ if (! (&shifter)) // until full...
+ shifter <= {shifter[14:0], 1'b1}; // shift left, fill with 1's
+
+ assign NRST_early = shifter[ 7];
+ assign NRST = shifter[ 8];
+ assign NRST_late = shifter[9] ;
+ assign NRST_ext = shifter[15];
endmodule
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 082a591..7dad76f 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -51,6 +51,7 @@ module nanosoc_tb;
wire VSSIO;
wire VDD;
wire VSS;
+ wire VDDACC;
//Debug tester signals
wire nTRST;
@@ -111,6 +112,7 @@ SROM_Ax32
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
+ .VDDACC (VDDACC),
`endif
.CLK (CLK), // input
.TEST (TEST), // input
@@ -126,8 +128,11 @@ SROM_Ax32
// --------------------------------------------------------------------------------
`ifndef COCOTB_SIM
nanosoc_clkreset u_nanosoc_clkreset(
- .CLK (CLK),
- .NRST (NRST)
+ .CLK (CLK),
+ .NRST (NRST),
+ .NRST_early( ),
+ .NRST_late ( ),
+ .NRST_ext ( )
);
`endif
diff --git a/verif/tb/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
index a32dd26..56fe9a8 100644
--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -50,6 +50,7 @@ module nanosoc_tb_qs;
wire VSSIO;
wire VDD;
wire VSS;
+ wire VDDACC;
//Debug tester signals
wire nTRST;
@@ -110,6 +111,7 @@ SROM_Ax32
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
+ .VDDACC (VDDACC),
`endif
.CLK (CLK), // input
.TEST (TEST), // output
@@ -125,8 +127,11 @@ SROM_Ax32
// --------------------------------------------------------------------------------
`ifndef COCOTB_SIM
nanosoc_clkreset u_nanosoc_clkreset(
- .CLK (CLK),
- .NRST (NRST)
+ .CLK (CLK),
+ .NRST (NRST),
+ .NRST_early( ),
+ .NRST_late ( ),
+ .NRST_ext ( )
);
`endif
--
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