diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
index 0ec1801e875cd83d7cdc77649dfb96f87b886c84..7209c105abd57a0d750f616dbed4d3c5164e0abb 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -36,7 +36,17 @@
 //-----------------------------------------------------------------------------
 //
 
+//param ADDR_WIDTH_RAM = 9;  // 512B
+//param ADDR_WIDTH_RAM = 10; // 1024B
+//param ADDR_WIDTH_RAM = 11; // 2KB
+//param ADDR_WIDTH_RAM = 12; // 4KB
+//param ADDR_WIDTH_RAM = 13; // 8KB
+//param ADDR_WIDTH_RAM = 14; // 16KB
+//param ADDR_WIDTH_RAM = 15; // 32KB
+//param ADDR_WIDTH_RAM = 16; // 64KB
+
 module nanosoc_chip
+ #(parameter ADDR_WIDTH_RAM = 14)
  (
 `ifdef POWER_PINS
   inout  wire          VDDIO,
@@ -808,7 +818,51 @@ localparam    CORTEX_M0 = 1;
     .SCANOUTHCLK     (SCANOUTHCLK)
   );
 
+// ************************************************
+// ************************************************
+//
+//  ADD YOUR EXPERIMENTAL AHB-MAPPED I/O HERE
+//
+//
+// ************************************************
+
 
+//
+// dummy interface of the form:
+//  experimental_ip u_exp (
+//    .HCLK        (HCLK),
+//    .HRESETn     (HRESETn),
+//    .HSEL        (HSEL_exp),
+//    .HADDR       (HADDR_exp),
+//    .HTRANS      (HTRANS_exp),
+//    .HWRITE      (HWRITE_exp),
+//    .HSIZE       (HSIZE_exp),
+//    .HBURST      (HBURST_exp),
+//    .HPROT       (HPROT_exp),
+//    .HWDATA      (HWDATA_exp),
+//    .HMASTLOCK   (HMASTLOCK_exp),
+//    .HREADY      (HREADYMUX_exp),
+//    .HRDATA      (HRDATA_exp),
+//    .HREADYOUT   (HREADYOUT_exp),
+//    .HRESP       (HRESP_exp)
+//  );
+ 
+  // Default slave
+  cmsdk_ahb_default_slave u_ahb_exp (
+    .HCLK         (HCLK),
+    .HRESETn      (HRESETn),
+    .HSEL         (HSEL_exp),
+    .HTRANS       (HTRANS_exp),
+    .HREADY       (HREADYMUX_exp),
+    .HREADYOUT    (HREADYOUT_exp),
+    .HRESP        (HRESP_exp)
+  );
+
+  assign   HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data
+  assign   HRUSER_exp = 2'b00;
+  
+// ************************************************
+   
 //----------------------------------------
 // Boot ROM "rom1" firmware
 // mapped 0x10000000-0x1fffffff
@@ -838,10 +892,7 @@ ahb_bootrom
 // mapped 0x20000000-0x2fffffff
 //----------------------------------------
 
-//localparam AWRAM2 = 9; // 512B
-//localparam AWRAM2 = 10; // 1024B
-localparam AWRAM2 = 14; // 16KB
-//localparam AWRAM2 = 16; // 64KB
+localparam AWRAM2 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
   wire  [AWRAM2-3:0] addr_ram2;
   wire    [31:0] wdata_ram2;
   wire    [31:0] rdata_ram2;
@@ -896,10 +947,7 @@ localparam AWRAM2 = 14; // 16KB
 // mapped 0x30000000-0x3fffffff
 //----------------------------------------
 
-//localparam AWRAM3 = 9; // 512B
-//localparam AWRAM3 = 10; // 1024B
-localparam AWRAM3 = 14; // 16KB
-//localparam AWRAM3 = 16; // 64KB
+localparam AWRAM3 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
   wire  [AWRAM3-3:0] addr_ram3;
   wire    [31:0] wdata_ram3;
   wire    [31:0] rdata_ram3;
@@ -951,10 +999,7 @@ localparam AWRAM3 = 14; // 16KB
 // Expansion/DMA "ram8,ram9" RAM instances
 //----------------------------------------
 
-//localparam AWRAM8 = 9; // 512B
-//localparam AWRAM8 = 10; // 1024B
-localparam AWRAM8 = 14; // 16KB
-//localparam AWRAM8 = 16; // 64KB
+localparam AWRAM8 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
   wire  [AWRAM8-3:0] addr_ram8;
   wire    [31:0] wdata_ram8;
   wire    [31:0] rdata_ram8;
@@ -1003,10 +1048,8 @@ localparam AWRAM8 = 14; // 16KB
    );
 
 // instandiate expansion RAM instance to appear at 0x90000000
-//localparam AWRAM9 = 9; // 512B
-//localparam AWRAM9 = 10; // 1024B
-localparam AWRAM9 = 14; // 16KB
-//localparam AWRAM9 = 16; // 64KB
+
+localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
   wire  [AWRAM9-3:0] addr_ram9;
   wire    [31:0] wdata_ram9;
   wire    [31:0] rdata_ram9;