diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v index dc30f11f31b87be7a43a2b680ec040990a0ebfa6..e17ffc5ff8c8ec2b99a2dafd0558ee1c41d3875a 100644 --- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v +++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v @@ -73,13 +73,14 @@ module nanosoc_sysio_decode #( // Peripheral Selection decode logic // ---------------------------------------------------------- - assign apbsys_hsel = hsel & (haddr[31:16]==16'h4000); // 0x40000000 + assign apbsys_hsel = hsel & (haddr[31:16]== + BASEADDR_APBSS[31:16]); // 0x40000000 assign gpio0_hsel = hsel & (haddr[31:12]== - BASEADDR_GPIO0[31:12]); // 0x40010000 + BASEADDR_GPIO0[31:12]); // 0x40010000 assign gpio1_hsel = hsel & (haddr[31:12]== - BASEADDR_GPIO1[31:12]); // 0x40011000 + BASEADDR_GPIO1[31:12]); // 0x40011000 assign sysctrl_hsel = hsel & (haddr[31:12]== - BASEADDR_SYSCTRL[31:12]); // 0x4001F000 + BASEADDR_SYSCTRL[31:12]); // 0x4001F000 // ---------------------------------------------------------- // Default slave decode logic diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v index 0af026c1b84feb79b23af095c055a6fe78b7cefa..0b8d22fe37f9ef9f66c398b7240c3183d422da32 100644 --- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v +++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v @@ -128,7 +128,6 @@ module nanosoc_system #( // System Reset Request Signals wire SYS_SYSRESETREQ; // System Request from System Managers - wire SYS_PRMURESETREQ; // CPU Control Reset Request (PMU and Reset Unit) // AHB Clocks and Resets wire SYS_PORESETn; // System Power On Reset