From 1ebe89b6929421c7fe0d0247fb8c3e857c584b24 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Thu, 1 Feb 2024 11:38:59 +0000
Subject: [PATCH] update PnR include miniASIC m scheme and bondpad place
---
ASIC/44pin/Cadence/scripts/design_import.tcl | 3 +-
ASIC/44pin/Cadence/scripts/genus.tcl | 2 +-
ASIC/44pin/Cadence/scripts/place_bondpads.tcl | 42 +++++++++++++++++++
ASIC/44pin/Cadence/scripts/pnr_flow.tcl | 19 ++++++---
ASIC/44pin/Cadence/scripts/power_plan.tcl | 4 +-
flows/makefile.asic | 4 +-
6 files changed, 63 insertions(+), 11 deletions(-)
create mode 100644 ASIC/44pin/Cadence/scripts/place_bondpads.tcl
diff --git a/ASIC/44pin/Cadence/scripts/design_import.tcl b/ASIC/44pin/Cadence/scripts/design_import.tcl
index 9bfbe84..90dccb2 100644
--- a/ASIC/44pin/Cadence/scripts/design_import.tcl
+++ b/ASIC/44pin/Cadence/scripts/design_import.tcl
@@ -14,7 +14,8 @@ read_mmmc nanosoc.mmmc
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
-set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
+#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
diff --git a/ASIC/44pin/Cadence/scripts/genus.tcl b/ASIC/44pin/Cadence/scripts/genus.tcl
index 35cf920..964a721 100644
--- a/ASIC/44pin/Cadence/scripts/genus.tcl
+++ b/ASIC/44pin/Cadence/scripts/genus.tcl
@@ -11,7 +11,7 @@
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
-
+set_multi_cpu_usage -local_cpu 8
## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
diff --git a/ASIC/44pin/Cadence/scripts/place_bondpads.tcl b/ASIC/44pin/Cadence/scripts/place_bondpads.tcl
new file mode 100644
index 0000000..771351c
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/place_bondpads.tcl
@@ -0,0 +1,42 @@
+eval_legacy {addInst -cell PAD60LU -inst BPAD_TEST_I -loc {149.29 1428} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDCK_I -loc {257.86 1428} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_3 -loc {366.43 1428} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_3 -loc {475.00 1428} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_3 -loc {583.57 1428} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_00 -loc {692.14 1428} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_01 -loc {800.71 1428} -ori R180}
+
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_04 -loc {0.0 146.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_05 -loc {0.0 251.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_03 -loc {0.0 356.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_0 -loc {0.0 461.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_0 -loc {0.0 566.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_CLK_I -loc {0.0 671.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_0 -loc {0.0 776.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_0 -loc {0.0 881.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDIO_IO -loc {0.0 986.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_0 -loc {0.0 1091.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_06 -loc {0.0 1196.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_07 -loc {0.0 1301.25} -ori R270}
+
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_02 -loc {149.29 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_1 -loc {257.86 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_1 -loc {366.43 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_1 -loc {475.00 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_1 -loc {583.57 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_01 -loc {692.14 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_00 -loc {800.71 0} -ori R0}
+
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_07 -loc {928 146.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_06 -loc {928 251.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_1 -loc {928 356.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_03 -loc {928 461.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_02 -loc {928 566.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_2 -loc {928 671.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_2 -loc {928 776.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_2 -loc {928 881.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_2 -loc {928 986.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_NRST_I -loc {928 1091.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_04 -loc {928 1196.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_05 -loc {928 1301.25} -ori R90}
+
diff --git a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
index d60f9f8..312f543 100644
--- a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
+++ b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
@@ -17,7 +17,7 @@ set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
set RF_08K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.gds2
set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
-
+set_multi_cpu_usage -local_cpu 8
puts "Starting PnR Flow ..."
@@ -54,9 +54,7 @@ reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
-### Add filler cells
-eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
-eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
+
write_db nanosoc_chip_pads
### Routing
@@ -66,6 +64,17 @@ report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route
check_antenna
write_db nanosoc_chip_pads
+
+### Add filler cells
+#eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
+#eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true -fix_drc
+add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true -fix_drc
+
+source place_bondpads.tcl
+
### Fill metal
set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
@@ -87,7 +96,7 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_
gui_show
write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
- -map_file $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/tech.map \
+ -map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
-lib_name DesignLib \
-merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
-output_macros -unit 2000 -mode all
diff --git a/ASIC/44pin/Cadence/scripts/power_plan.tcl b/ASIC/44pin/Cadence/scripts/power_plan.tcl
index 197b284..e3d70dc 100644
--- a/ASIC/44pin/Cadence/scripts/power_plan.tcl
+++ b/ASIC/44pin/Cadence/scripts/power_plan.tcl
@@ -16,7 +16,7 @@ set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1
### Adding Rings
-add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 1 bottom 1 left 1 right 1} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
### Adding Stripes
set_db add_stripes_ignore_block_check true
@@ -38,7 +38,7 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
-add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 56 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
diff --git a/flows/makefile.asic b/flows/makefile.asic
index 46aa340..4d9e6d9 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -93,11 +93,11 @@ gen_memories: bootrom
convert_mem_to_db:
lc_shell -no_log -f $(NANOSOC_SYNTH_DIR)/synopsys_lib_conversion.tcl
-syn_genus:
+syn_genus_44pin:
@mkdir -p $(REPORTS_FOLDER)
@mkdir -p $(NETLIST_FOLDER)
@mkdir -p $(SYN_LOGS)
- cd $(NANOSOC_SYNTH_DIR)/Cadence/Genus; genus -f $(NANOSOC_SYNTH_DIR)/Cadence/Genus/genus.tcl -log $(SYN_LOGS)/nanosoc_synth_genus.log
+ cd $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts; genus -f $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts/genus.tcl -log $(SYN_LOGS)/nanosoc_synth_genus.log
syn_dc:
@mkdir -p $(REPORTS_FOLDER)
--
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