From 13a53d950b2857686339411420025153c373cca5 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Tue, 21 Feb 2023 22:05:29 +0000
Subject: [PATCH] upgrade pynq-z2 FPGA for nanosoc iotest
---
.../soclabs/nanosoc-iotest.ipynb | 708 ++++++++++++++++++
.../fpga_imp/target_fpga_pynq_z2/design_1.tcl | 308 ++++----
2 files changed, 891 insertions(+), 125 deletions(-)
create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
new file mode 100644
index 0000000..aa609ed
--- /dev/null
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
@@ -0,0 +1,708 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Downloading Overlays\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Instantiating an overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/2/20 17:44:40 +479858'"
+ ]
+ },
+ "execution_count": 5,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "#ADP_address = 0x43c00000 # nanosoc FT1248 com channel\n",
+ "#ADP_address = 0x43c10000 # streamio TX/RX loopback (unbuffered)\n",
+ "#ADP_address = 0x43c20000 # streamio TX/RX loopback (FIFO buffered)\n",
+ "ADP_address = 0x4sc30000 # local test ADP controller COM channel\n",
+ "UART2_address = 0x42c00000 # nanosoc UART2 com serial (9600 baud?)\n",
+ "#ADP_address = 0x42c10000 # uart TX/RX loopback\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ " sleep(1)\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB02 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "' 0x50c1ab02\\n\\r\\n\\r]'"
+ ]
+ },
+ "execution_count": 7,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "adp.read(20)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 8,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now check adp Address pointer reets to zero"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'A 0x00000000\\n\\r]'"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('A\\n')\n",
+ "adp.read(20)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "And do a couple of 32-bit reads"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'R 0x00000000\\n\\r]'"
+ ]
+ },
+ "execution_count": 10,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('R\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'R 0x00000000\\n\\r]'"
+ ]
+ },
+ "execution_count": 11,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('R\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Verify the address pointer has auto-incremented two words"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'A 0x00000008\\n\\r]'"
+ ]
+ },
+ "execution_count": 12,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('A\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now set adp address to high memory and write a couple of patterns"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'A 0xc0000000\\n\\r]'"
+ ]
+ },
+ "execution_count": 13,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('A c0000000\\n')\n",
+ "adp.read(20)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 14,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'W 0x11111111\\n\\r]'"
+ ]
+ },
+ "execution_count": 14,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('W 111111111\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 15,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'W 0x22222222\\n\\r]'"
+ ]
+ },
+ "execution_count": 15,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('W 22222222\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Reset the address pointer and verify same patterns read back"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 16,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'A 0xc0000000\\n\\r]'"
+ ]
+ },
+ "execution_count": 16,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('A c0000000\\n')\n",
+ "adp.read(20)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 17,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'R 0x11111111\\n\\r]'"
+ ]
+ },
+ "execution_count": 17,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('R\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 18,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'R 0x22222222\\n\\r]'"
+ ]
+ },
+ "execution_count": 18,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "adp.write('R\\n')\n",
+ "adp.read(15)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "\n",
+ "## ol.download()\n",
+ "ol.timestamp\n",
+ "ol.reset()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ip_info = {'trace_cntrl':\"ft1248tb_i/ila_0\"}\n",
+ "class pynq.logictools.trace_analyzer.TraceAnalyzer(ip_info)\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "gpio_0.register_map\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.timestamp\n",
+ "\n",
+ "PL.ip_dict\n",
+ "\n",
+ "leds_address = PL.ip_dict['led_4bits']['phys_addr']\n",
+ " \n",
+ "from pynq import MMIO\n",
+ "mmio_buttons = MMIO(0xa0000000, 16)\n",
+ "help (mmio_buttons)\n",
+ "\n",
+ "#print(hex(mmio_buttons))\n",
+ "#print(hex(mmio_buttons.read(0)))\n",
+ "\n",
+ "hex(pl.ip_dict[\"axi_gpio_1\"][\"phys_addr\"])\n",
+ "\n",
+ "\n",
+ "#buttons_address = ssc_dpram.ip_dict['push_button_4bits']['phys_addr']\n",
+ "#switches_address = ssc_dpram.ip_dict['dip_switch_4bits']['phys_addr']\n",
+ "#leds_address = ssc_dpram.ip_dict['led_4bitss']['phys_addr']"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
index 22a84df..86dc53c 100644
--- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
+++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
@@ -46,8 +46,15 @@ if { $bCheckIPs == 1 } {
set list_check_ips "\
soclabs.org:user:nanosoc_chip:1.0\
xilinx.com:ip:processing_system7:5.5\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:proc_sys_reset:5.0\
@@ -82,13 +89,13 @@ if { $bCheckIPsPassed != 1 } {
##################################################################
-# Hierarchical cell: cmsdk_socket
-proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+# Hierarchical cell: nanosoc_socket
+proc create_hier_cell_nanosoc_socket { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_nanosoc_socket() - Empty argument(s)!"}
return
}
@@ -123,10 +130,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create pins
create_bd_pin -dir I -type clk aclk
create_bd_pin -dir I -type rst ext_reset_in
- create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o
- create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z
- create_bd_pin -dir O -from 15 -to 0 gpio_tri_i
- create_bd_pin -dir I -from 15 -to 0 gpio_tri_o
create_bd_pin -dir O -from 0 -to 0 -type rst nrst
create_bd_pin -dir O -from 15 -to 0 p0_tri_i
create_bd_pin -dir I -from 15 -to 0 p0_tri_o
@@ -137,6 +140,24 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {Hamming} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
@@ -154,13 +175,17 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_1
- # Create instance: axi_gpio_2, and set properties
- set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_2
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
# Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
@@ -168,6 +193,61 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
] $axi_uartlite_0
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
# Create instance: p1_i_bit15to6, and set properties
set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
set_property -dict [ list \
@@ -187,6 +267,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.IN4_WIDTH {1} \
CONFIG.IN5_WIDTH {1} \
CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
CONFIG.NUM_PORTS {7} \
] $p1_i_concat
@@ -262,6 +344,24 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.DOUT_WIDTH {1} \
] $pmoda_i_bit3
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
# Create instance: pmoda_o_concat8, and set properties
set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
set_property -dict [ list \
@@ -280,7 +380,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
- CONFIG.NUM_MI {4} \
+ CONFIG.NUM_MI {8} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
@@ -294,41 +394,70 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
# Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
# Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
- connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o]
- connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o]
connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
- connect_bd_net -net nanosoc_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
- connect_bd_net -net nanosoc_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
- connect_bd_net -net nanosoc_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
- connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i]
- connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i]
- connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
- connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
- connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
- connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
- connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din]
- connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout]
- connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
# Restore current instance
@@ -377,106 +506,35 @@ proc create_root_design { parentCell } {
# Create instance: nanosoc_chip_0, and set properties
set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
- # Create instance: cmsdk_socket
- create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+ # Create instance: nanosoc_socket
+ create_hier_cell_nanosoc_socket [current_bd_instance .] nanosoc_socket
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
- set_property -dict [ list \
- CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
- CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
- CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {20.000000} \
- CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_CLK0_FREQ {20000000} \
- CONFIG.PCW_CLK1_FREQ {10000000} \
- CONFIG.PCW_CLK2_FREQ {10000000} \
- CONFIG.PCW_CLK3_FREQ {10000000} \
- CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
- CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
- CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
- CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
- CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {8} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} \
- CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
- CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
- CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
- CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
- CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
- CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
- ] $processing_system7_0
# Create interface connections
- connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins nanosoc_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
# Create port connections
- connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o]
- connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z]
- connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins nanosoc_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o]
- connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins nanosoc_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i]
- connect_bd_net -net cmsdk_socket_nrst [get_bd_pins nanosoc_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst]
- connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins nanosoc_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i]
- connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins nanosoc_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i]
- connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
- connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
- connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
- connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
- connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
- connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
- connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
- connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins nanosoc_chip_0/nrst_i] [get_bd_pins nanosoc_socket/nrst]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins nanosoc_chip_0/p0_i] [get_bd_pins nanosoc_socket/p0_tri_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins nanosoc_chip_0/p1_i] [get_bd_pins nanosoc_socket/p1_tri_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins nanosoc_chip_0/swdclk_i] [get_bd_pins nanosoc_socket/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins nanosoc_chip_0/swdio_i] [get_bd_pins nanosoc_socket/swdio_tri_i]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins nanosoc_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins nanosoc_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins nanosoc_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins nanosoc_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins nanosoc_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins nanosoc_socket/pmoda_tri_z]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins nanosoc_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins nanosoc_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins nanosoc_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins nanosoc_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins nanosoc_socket/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
# Create address segments
- assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force
- assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces nanosoc_socket/ADPcontrol_0/ahb] [get_bd_addr_segs nanosoc_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
# Restore current instance
@@ -492,7 +550,7 @@ proc available_tcl_procs { } {
puts "##################################################################"
puts "# Available Tcl procedures to recreate hierarchical blocks:"
puts "#"
- puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_hier_cell_nanosoc_socket parentCell nameHier"
puts "# create_root_design"
puts "#"
puts "#"
--
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