diff --git a/flist/nanosoc_busmatrix_ip.flist b/flist/nanosoc_busmatrix_ip.flist
index a328ec80bc1c5f12a437276ad11cdfa634dad363..6506febaa7601aa8353b2a2abac731269ad78439 100644
--- a/flist/nanosoc_busmatrix_ip.flist
+++ b/flist/nanosoc_busmatrix_ip.flist
@@ -32,6 +32,8 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
@@ -39,4 +41,4 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
-$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
diff --git a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
index 64f94570763c7b9e260d9fd39fa352d35fdf70e0..b0d76864cd4e8de6acc93fed1fbe774fa40203bf 100644
--- a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
+++ b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
@@ -491,6 +491,308 @@
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_2</spirit:name>
+ <spirit:description>Slave port _DMAC_2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_2_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXP" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_DMAC_2 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_DMAC_2</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_3</spirit:name>
+ <spirit:description>Slave port _DMAC_3</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_3_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXP" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_DMAC_3 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_DMAC_3</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
<spirit:busInterface>
<spirit:name>AHBLiteTarget_Slave__CPU_0</spirit:name>
<spirit:description>Slave port _CPU_0</spirit:description>
@@ -1856,17 +2158,17 @@
<spirit:remapStates>
<spirit:remapState>
- <spirit:name>remap_0</spirit:name>
- <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -2080,17 +2382,6 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_0_remap_MM</spirit:name>
- <spirit:description>_DEBUG remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
<spirit:description>_DEBUG remap_n0 remap</spirit:description>
@@ -2102,6 +2393,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
<spirit:memoryMap>
@@ -2174,8 +2476,146 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteTarget_Slave__DMAC_1_MM</spirit:name>
- <spirit:description>_DMAC_1 memory map</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_1_MM</spirit:name>
+ <spirit:description>_DMAC_1 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__SYSIO"
+ spirit:segmentRef="_SYSIO_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__SYSIO_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L"
+ spirit:segmentRef="_EXPRAM_L_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_L_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H"
+ spirit:segmentRef="_EXPRAM_H_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_H_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_2_MM</spirit:name>
+ <spirit:description>_DMAC_2 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__SYSIO"
+ spirit:segmentRef="_SYSIO_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__SYSIO_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L"
+ spirit:segmentRef="_EXPRAM_L_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_L_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H"
+ spirit:segmentRef="_EXPRAM_H_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_H_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_3_MM</spirit:name>
+ <spirit:description>_DMAC_3 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
@@ -2309,17 +2749,6 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_0_remap_MM</spirit:name>
- <spirit:description>_CPU_0 remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_n0 remap</spirit:description>
@@ -2331,6 +2760,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_0_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
</spirit:memoryMaps>
@@ -2688,6 +3128,208 @@
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>3</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HSEL_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>4</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
<spirit:port>
<spirit:name>HSEL_CPU_0</spirit:name>
<spirit:wire>
@@ -2762,7 +3404,7 @@
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:driver>
- <spirit:defaultValue>3</spirit:defaultValue>
+ <spirit:defaultValue>5</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
@@ -3851,6 +4493,58 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HRDATA_CPU_0</spirit:name>
<spirit:wire>
@@ -3919,6 +4613,14 @@
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
diff --git a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
index b0ec4cd05819bc7e1a25e70903bdf31cd0891041..54e94ed85b7954813f8cbf3621f5cc60a96eaca2 100644
--- a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
+++ b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
@@ -422,6 +422,262 @@
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_2</spirit:name>
+ <spirit:description>Slave port _DMAC_2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_2_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXP" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_DMAC_2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_3</spirit:name>
+ <spirit:description>Slave port _DMAC_3</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_3_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXP" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_DMAC_3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
<spirit:busInterface>
<spirit:name>AHBLiteInitiator_Slave__CPU_0</spirit:name>
<spirit:description>Slave port _CPU_0</spirit:description>
@@ -1708,17 +1964,17 @@
<spirit:remapStates>
<spirit:remapState>
- <spirit:name>remap_0</spirit:name>
- <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -1861,13 +2117,180 @@
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
- </spirit:addressSpaces>
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_MM</spirit:name>
+ <spirit:description>_DEBUG memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__SYSIO"
+ spirit:segmentRef="_SYSIO_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__SYSIO_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L"
+ spirit:segmentRef="_EXPRAM_L_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_L_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H"
+ spirit:segmentRef="_EXPRAM_H_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_H_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__SYSTABLE"
+ spirit:segmentRef="_SYSTABLE_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__SYSTABLE_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_0_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_0_MM</spirit:name>
+ <spirit:description>_DMAC_0 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__SYSIO"
+ spirit:segmentRef="_SYSIO_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__SYSIO_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L"
+ spirit:segmentRef="_EXPRAM_L_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_L_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H"
+ spirit:segmentRef="_EXPRAM_H_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXPRAM_H_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXP"
+ spirit:segmentRef="_EXP_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXP_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
- <spirit:memoryMaps>
+ </spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__DEBUG_MM</spirit:name>
- <spirit:description>_DEBUG memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_1_MM</spirit:name>
+ <spirit:description>_DMAC_1 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
@@ -1925,40 +2348,11 @@
<spirit:baseAddress>0xa0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__SYSTABLE"
- spirit:segmentRef="_SYSTABLE_0xf0000000_0xf003ffff">
- <!-- Address_region 0xf0000000-0xf003ffff -->
- <spirit:name>AHBLiteTarget_Master__SYSTABLE_0xf0000000_0_state_always_SM</spirit:name>
- <spirit:baseAddress>0xf0000000</spirit:baseAddress>
- </spirit:subspaceMap>
-
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_0_remap_MM</spirit:name>
- <spirit:description>_DEBUG remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
- <spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
- <spirit:description>_DEBUG remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
- <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__DMAC_0_MM</spirit:name>
- <spirit:description>_DMAC_0 memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_2_MM</spirit:name>
+ <spirit:description>_DMAC_2 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
@@ -2026,8 +2420,8 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__DMAC_1_MM</spirit:name>
- <spirit:description>_DMAC_1 memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_3_MM</spirit:name>
+ <spirit:description>_DMAC_3 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
@@ -2161,17 +2555,6 @@
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_0_remap_MM</spirit:name>
- <spirit:description>_CPU_0 remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
- spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_n0 remap</spirit:description>
@@ -2183,6 +2566,17 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_0_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
</spirit:memoryMap>
</spirit:memoryMaps>
@@ -2462,6 +2856,156 @@
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HADDR_CPU_0</spirit:name>
<spirit:wire>
@@ -3475,6 +4019,50 @@
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_DMAC_2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_DMAC_3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HRDATA_CPU_0</spirit:name>
<spirit:wire>
@@ -3543,6 +4131,14 @@
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
diff --git a/nanosoc/nanosoc_busmatrix/logs/nanosoc.log b/nanosoc/nanosoc_busmatrix/logs/nanosoc.log
index 038f8afe8758dffb63e4e2d6e3a6ce02e88e64e9..466230ae66592c8dc7253db10f6b4bb241ceac4f 100644
--- a/nanosoc/nanosoc_busmatrix/logs/nanosoc.log
+++ b/nanosoc/nanosoc_busmatrix/logs/nanosoc.log
@@ -14,14 +14,14 @@
=
= BuildBusMatrix.pl
=
-= Run Date : 16/06/2023 08:53:15
+= Run Date : 17/07/2024 10:27:53
==============================================================
Script accepted the following parameters:
- - Configuration file : '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/xml/nanosoc.xml'
+ - Configuration file : '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml'
- Top-level name : 'nanosoc_busmatrix'
- - Slave interfaces : 4
+ - Slave interfaces : 6
- Master interfaces : 8
- Architecture type : 'ahb2'
- Arbitration scheme : 'burst'
@@ -29,74 +29,80 @@ Script accepted the following parameters:
- Connectivity mapping : _DEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
_DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
_DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+ _DMAC_2 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+ _DMAC_3 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
_CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
- Connectivity type : sparse
- Routing data width : 32
- Routing address width : 32
- User signal width : 0
- Timescales : no
- - Configuration directory : '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog'
+ - Configuration directory : '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog'
- Source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/verilog/src'
- - IPXact target directory : '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/ipxact'
+ - IPXact target directory : '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/ipxact'
- IPXact source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/ipxact/src'
- Overwrite mode : enabled
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPANSION.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPANSION.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml' file...
+Deleting the '/home/dwf1m12/work/soclabs/accelerator-project/nanosoc_tech/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml' file...
Creating the bus matrix variant...
- - Rendering 'nanosoc_busmatrix.xml'
- Rendering 'nanosoc_busmatrix_lite.xml'
- - Rendering 'nanosoc_matrix_decode_DMAC_0.v'
- - Rendering 'nanosoc_target_output_BOOTROM_0.v'
+ - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
- Rendering 'nanosoc_arbiter_EXP.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_H.v'
- - Rendering 'nanosoc_target_output_IMEM_0.v'
- - Rendering 'nanosoc_target_output_DMEM_0.v'
+ - Rendering 'nanosoc_target_output_SYSTABLE.v'
+ - Rendering 'nanosoc_matrix_decode_DEBUG.v'
+ - Rendering 'nanosoc_arbiter_SYSTABLE.v'
- Rendering 'nanosoc_target_output_EXPRAM_L.v'
+ - Rendering 'nanosoc_busmatrix_lite.v'
+ - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_target_output_EXPRAM_H.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
- Rendering 'nanosoc_arbiter_SYSIO.v'
- - Rendering 'nanosoc_target_output_SYSIO.v'
+ - Rendering 'nanosoc_target_output_BOOTROM_0.v'
- Rendering 'nanosoc_busmatrix.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_2.v'
+ - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_arbiter_DMEM_0.v'
+ - Rendering 'nanosoc_target_output_IMEM_0.v'
+ - Rendering 'nanosoc_arbiter_EXPRAM_H.v'
- Rendering 'nanosoc_inititator_input.v'
- - Rendering 'nanosoc_target_output_EXPRAM_H.v'
+ - Rendering 'nanosoc_target_output_EXP.v'
- Rendering 'nanosoc_arbiter_BOOTROM_0.v'
- - Rendering 'nanosoc_busmatrix_lite.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_0.v'
- Rendering 'nanosoc_arbiter_IMEM_0.v'
- - Rendering 'nanosoc_arbiter_DMEM_0.v'
- - Rendering 'nanosoc_arbiter_SYSTABLE.v'
+ - Rendering 'nanosoc_target_output_DMEM_0.v'
- Rendering 'nanosoc_matrix_decode_CPU_0.v'
- - Rendering 'nanosoc_matrix_decode_DEBUG.v'
- - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
- - Rendering 'nanosoc_target_output_SYSTABLE.v'
- - Rendering 'nanosoc_target_output_EXP.v'
- - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_3.v'
+ - Rendering 'nanosoc_target_output_SYSIO.v'
Done!
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
index 850c0bccd60e389146d4d5d9ada76dd3ba8092f2..861093e66a81bc8f432cc29b58ce79bf83335d3e 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_BOOTROM_0 (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_BOOTROM_0 (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_BOOTROM_0 (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_BOOTROM_0 (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_BOOTROM_0 (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_BOOTROM_0 (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
index e2559ef58dfb6eb30868b759eb77d350e435cbda..c0b7557f85f827a22b7cb5153ae362175184d362 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_DMEM_0 (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_DMEM_0 (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_DMEM_0 (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_DMEM_0 (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_DMEM_0 (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_DMEM_0 (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
index 42a514fe5dada28a6eeada2033c99e5406cc4b18..a6cd8819f2c5f3d0bc097bb15abc93c6fff44129 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_EXP (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_EXP (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_EXP (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_EXP (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_EXP (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_EXP (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
index d49521d8b5f460400525106e60625a50eb972162..f545662c405442135b1f198c63cfb52db591d7e6 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_EXPRAM_H (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_EXPRAM_H (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_EXPRAM_H (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_EXPRAM_H (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_EXPRAM_H (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_EXPRAM_H (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
index 03c9c2571c3966f567e129e62dc9ac40fbad2e6a..b80c3d769b276c54d8f9558a9860ef0581a1e20f 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_EXPRAM_L (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_EXPRAM_L (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_EXPRAM_L (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_EXPRAM_L (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_EXPRAM_L (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_EXPRAM_L (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
index 7e3ec3846216af3a7076d6660ab27fc38e92184a..18b751b424f6a2ae36eee544ab6f02dc84437786 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_IMEM_0 (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_IMEM_0 (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_IMEM_0 (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_IMEM_0 (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_IMEM_0 (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_IMEM_0 (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
index ebbf33182df87673cdb9f6fd909b20fd192c794a..5e73476fa9f1a9846891c192528dc464c83461bf 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -43,6 +43,8 @@ module nanosoc_arbiter_SYSIO (
req_port1,
req_port2,
req_port3,
+ req_port4,
+ req_port5,
HREADYM,
HSELM,
@@ -68,12 +70,14 @@ module nanosoc_arbiter_SYSIO (
input req_port1; // Port 1 request signal
input req_port2; // Port 2 request signal
input req_port3; // Port 3 request signal
+ input req_port4; // Port 4 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -107,19 +111,21 @@ module nanosoc_arbiter_SYSIO (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -275,6 +281,8 @@ module nanosoc_arbiter_SYSIO (
req_port1 or
req_port2 or
req_port3 or
+ req_port4 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -284,18 +292,24 @@ module nanosoc_arbiter_SYSIO (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port1 | ( (i_addr_in_port == 3'b001) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b01;
- else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ addr_in_port_next = 3'b001;
+ else if ( req_port2 | ( (i_addr_in_port == 3'b010) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b10;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b010;
+ else if ( req_port3 | ( (i_addr_in_port == 3'b011) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b011;
+ else if ( req_port4 | ( (i_addr_in_port == 3'b100) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b100;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -309,7 +323,7 @@ module nanosoc_arbiter_SYSIO (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
index b0e8bef703369190c81fae4682b56b3ff8a22df1..da4d27d45f56c5a35d29bbb5d348d7d418462773 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -40,7 +40,7 @@ module nanosoc_arbiter_SYSTABLE (
// Input port request signals
req_port0,
- req_port3,
+ req_port5,
HREADYM,
HSELM,
@@ -63,13 +63,13 @@ module nanosoc_arbiter_SYSTABLE (
input HCLK; // AHB system clock
input HRESETn; // AHB system reset
input req_port0; // Port 0 request signal
- input req_port3; // Port 3 request signal
+ input req_port5; // Port 5 request signal
input HREADYM; // Transfer done
input HSELM; // Slave select line
input [1:0] HTRANSM; // Transfer type
input [2:0] HBURSTM; // Burst type
input HMASTLOCKM; // Locked transfer
- output [1:0] addr_in_port; // Port address input
+ output [2:0] addr_in_port; // Port address input
output no_port; // No port selected signal
@@ -100,20 +100,20 @@ module nanosoc_arbiter_SYSTABLE (
wire HCLK; // AHB system clock
wire HRESETn; // AHB system reset
wire req_port0; // Port 0 request signal
- wire req_port3; // Port 3 request signal
+ wire req_port5; // Port 5 request signal
wire HREADYM; // Transfer done
wire HSELM; // Slave select line
wire [1:0] HTRANSM; // Transfer type
wire [2:0] HBURSTM; // Burst type
wire HMASTLOCKM; // Locked transfer
- wire [1:0] addr_in_port; // Address input port
+ wire [2:0] addr_in_port; // Address input port
reg no_port; // No port selected signal
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
- reg [1:0] addr_in_port_next; // D-input of addr_in_port
- reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg [2:0] addr_in_port_next; // D-input of addr_in_port
+ reg [2:0] i_addr_in_port; // Internal version of addr_in_port
reg no_port_next; // D-input of no_port
reg [3:0] next_burst_count; // D-input of reg_burst_count
reg [3:0] reg_burst_count; // Burst counter
@@ -266,7 +266,7 @@ module nanosoc_arbiter_SYSTABLE (
always @ (
req_port0 or
- req_port3 or
+ req_port5 or
HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
)
begin : p_sel_port_comb
@@ -276,12 +276,12 @@ module nanosoc_arbiter_SYSTABLE (
if ( HMASTLOCKM | next_burst_hold )
addr_in_port_next = i_addr_in_port;
- else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ else if ( req_port0 | ( (i_addr_in_port == 3'b000) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b00;
- else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ addr_in_port_next = 3'b000;
+ else if ( req_port5 | ( (i_addr_in_port == 3'b101) & HSELM &
(HTRANSM != 2'b00) ) )
- addr_in_port_next = 2'b11;
+ addr_in_port_next = 3'b101;
else if (HSELM)
addr_in_port_next = i_addr_in_port;
else
@@ -295,7 +295,7 @@ module nanosoc_arbiter_SYSTABLE (
if (!HRESETn)
begin
no_port <= 1'b1;
- i_addr_in_port <= {2{1'b0}};
+ i_addr_in_port <= {3{1'b0}};
end
else
if (HREADYM)
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
index 9defea1e4032b715b527c70e4dc83f6e95c4f8bc..85cf9cebbd30debf2f8d285af03da729c93b7d1f 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -29,7 +29,7 @@
// Supports the following configured options:
//
// - Architecture type 'ahb2',
-// - 4 slave ports (connecting to masters),
+// - 6 slave ports (connecting to masters),
// - 8 master ports (connecting to slaves),
// - Routing address width of 32 bits,
// - Routing data width of 32 bits,
@@ -38,6 +38,8 @@
// _DEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
// _DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
// _DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+// _DMAC_2 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+// _DMAC_3 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
// _CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
// - Connectivity type 'sparse'.
//
@@ -94,6 +96,32 @@ module nanosoc_busmatrix (
HREADY_DMAC_1,
// Input port SI3 (inputs from master 3)
+ HSEL_DMAC_2,
+ HADDR_DMAC_2,
+ HTRANS_DMAC_2,
+ HWRITE_DMAC_2,
+ HSIZE_DMAC_2,
+ HBURST_DMAC_2,
+ HPROT_DMAC_2,
+ HMASTER_DMAC_2,
+ HWDATA_DMAC_2,
+ HMASTLOCK_DMAC_2,
+ HREADY_DMAC_2,
+
+ // Input port SI4 (inputs from master 4)
+ HSEL_DMAC_3,
+ HADDR_DMAC_3,
+ HTRANS_DMAC_3,
+ HWRITE_DMAC_3,
+ HSIZE_DMAC_3,
+ HBURST_DMAC_3,
+ HPROT_DMAC_3,
+ HMASTER_DMAC_3,
+ HWDATA_DMAC_3,
+ HMASTLOCK_DMAC_3,
+ HREADY_DMAC_3,
+
+ // Input port SI5 (inputs from master 5)
HSEL_CPU_0,
HADDR_CPU_0,
HTRANS_CPU_0,
@@ -271,6 +299,16 @@ module nanosoc_busmatrix (
HRESP_DMAC_1,
// Input port SI3 (outputs to master 3)
+ HRDATA_DMAC_2,
+ HREADYOUT_DMAC_2,
+ HRESP_DMAC_2,
+
+ // Input port SI4 (outputs to master 4)
+ HRDATA_DMAC_3,
+ HREADYOUT_DMAC_3,
+ HRESP_DMAC_3,
+
+ // Input port SI5 (outputs to master 5)
HRDATA_CPU_0,
HREADYOUT_CPU_0,
HRESP_CPU_0,
@@ -332,6 +370,32 @@ module nanosoc_busmatrix (
input HREADY_DMAC_1; // Transfer done
// Input port SI3 (inputs from master 3)
+ input HSEL_DMAC_2; // Slave Select
+ input [31:0] HADDR_DMAC_2; // Address bus
+ input [1:0] HTRANS_DMAC_2; // Transfer type
+ input HWRITE_DMAC_2; // Transfer direction
+ input [2:0] HSIZE_DMAC_2; // Transfer size
+ input [2:0] HBURST_DMAC_2; // Burst type
+ input [3:0] HPROT_DMAC_2; // Protection control
+ input [3:0] HMASTER_DMAC_2; // Master select
+ input [31:0] HWDATA_DMAC_2; // Write data
+ input HMASTLOCK_DMAC_2; // Locked Sequence
+ input HREADY_DMAC_2; // Transfer done
+
+ // Input port SI4 (inputs from master 4)
+ input HSEL_DMAC_3; // Slave Select
+ input [31:0] HADDR_DMAC_3; // Address bus
+ input [1:0] HTRANS_DMAC_3; // Transfer type
+ input HWRITE_DMAC_3; // Transfer direction
+ input [2:0] HSIZE_DMAC_3; // Transfer size
+ input [2:0] HBURST_DMAC_3; // Burst type
+ input [3:0] HPROT_DMAC_3; // Protection control
+ input [3:0] HMASTER_DMAC_3; // Master select
+ input [31:0] HWDATA_DMAC_3; // Write data
+ input HMASTLOCK_DMAC_3; // Locked Sequence
+ input HREADY_DMAC_3; // Transfer done
+
+ // Input port SI5 (inputs from master 5)
input HSEL_CPU_0; // Slave Select
input [31:0] HADDR_CPU_0; // Address bus
input [1:0] HTRANS_CPU_0; // Transfer type
@@ -509,6 +573,16 @@ module nanosoc_busmatrix (
output [1:0] HRESP_DMAC_1; // Transfer response
// Input port SI3 (outputs to master 3)
+ output [31:0] HRDATA_DMAC_2; // Read data bus
+ output HREADYOUT_DMAC_2; // HREADY feedback
+ output [1:0] HRESP_DMAC_2; // Transfer response
+
+ // Input port SI4 (outputs to master 4)
+ output [31:0] HRDATA_DMAC_3; // Read data bus
+ output HREADYOUT_DMAC_3; // HREADY feedback
+ output [1:0] HRESP_DMAC_3; // Transfer response
+
+ // Input port SI5 (outputs to master 5)
output [31:0] HRDATA_CPU_0; // Read data bus
output HREADYOUT_CPU_0; // HREADY feedback
output [1:0] HRESP_CPU_0; // Transfer response
@@ -580,6 +654,40 @@ module nanosoc_busmatrix (
wire [1:0] HRESP_DMAC_1; // Transfer response
// Input Port SI3
+ wire HSEL_DMAC_2; // Slave Select
+ wire [31:0] HADDR_DMAC_2; // Address bus
+ wire [1:0] HTRANS_DMAC_2; // Transfer type
+ wire HWRITE_DMAC_2; // Transfer direction
+ wire [2:0] HSIZE_DMAC_2; // Transfer size
+ wire [2:0] HBURST_DMAC_2; // Burst type
+ wire [3:0] HPROT_DMAC_2; // Protection control
+ wire [3:0] HMASTER_DMAC_2; // Master select
+ wire [31:0] HWDATA_DMAC_2; // Write data
+ wire HMASTLOCK_DMAC_2; // Locked Sequence
+ wire HREADY_DMAC_2; // Transfer done
+
+ wire [31:0] HRDATA_DMAC_2; // Read data bus
+ wire HREADYOUT_DMAC_2; // HREADY feedback
+ wire [1:0] HRESP_DMAC_2; // Transfer response
+
+ // Input Port SI4
+ wire HSEL_DMAC_3; // Slave Select
+ wire [31:0] HADDR_DMAC_3; // Address bus
+ wire [1:0] HTRANS_DMAC_3; // Transfer type
+ wire HWRITE_DMAC_3; // Transfer direction
+ wire [2:0] HSIZE_DMAC_3; // Transfer size
+ wire [2:0] HBURST_DMAC_3; // Burst type
+ wire [3:0] HPROT_DMAC_3; // Protection control
+ wire [3:0] HMASTER_DMAC_3; // Master select
+ wire [31:0] HWDATA_DMAC_3; // Write data
+ wire HMASTLOCK_DMAC_3; // Locked Sequence
+ wire HREADY_DMAC_3; // Transfer done
+
+ wire [31:0] HRDATA_DMAC_3; // Read data bus
+ wire HREADYOUT_DMAC_3; // HREADY feedback
+ wire [1:0] HRESP_DMAC_3; // Transfer response
+
+ // Input Port SI5
wire HSEL_CPU_0; // Slave Select
wire [31:0] HADDR_CPU_0; // Address bus
wire [1:0] HTRANS_CPU_0; // Transfer type
@@ -797,6 +905,36 @@ module nanosoc_busmatrix (
wire i_readyout3; // Readyout signal
wire [1:0] i_resp3; // Response signal
+ // Bus-switch input SI4
+ wire i_sel4; // HSEL signal
+ wire [31:0] i_addr4; // HADDR signal
+ wire [1:0] i_trans4; // HTRANS signal
+ wire i_write4; // HWRITE signal
+ wire [2:0] i_size4; // HSIZE signal
+ wire [2:0] i_burst4; // HBURST signal
+ wire [3:0] i_prot4; // HPROTS signal
+ wire [3:0] i_master4; // HMASTER signal
+ wire i_mastlock4; // HMASTLOCK signal
+ wire i_active4; // Active signal
+ wire i_held_tran4; // HeldTran signal
+ wire i_readyout4; // Readyout signal
+ wire [1:0] i_resp4; // Response signal
+
+ // Bus-switch input SI5
+ wire i_sel5; // HSEL signal
+ wire [31:0] i_addr5; // HADDR signal
+ wire [1:0] i_trans5; // HTRANS signal
+ wire i_write5; // HWRITE signal
+ wire [2:0] i_size5; // HSIZE signal
+ wire [2:0] i_burst5; // HBURST signal
+ wire [3:0] i_prot5; // HPROTS signal
+ wire [3:0] i_master5; // HMASTER signal
+ wire i_mastlock5; // HMASTLOCK signal
+ wire i_active5; // Active signal
+ wire i_held_tran5; // HeldTran signal
+ wire i_readyout5; // Readyout signal
+ wire [1:0] i_resp5; // Response signal
+
// Bus-switch SI0 to MI0 signals
wire i_sel0to0; // Routing selection signal
wire i_active0to0; // Active signal
@@ -913,9 +1051,65 @@ module nanosoc_busmatrix (
wire i_sel3to6; // Routing selection signal
wire i_active3to6; // Active signal
- // Bus-switch SI3 to MI7 signals
- wire i_sel3to7; // Routing selection signal
- wire i_active3to7; // Active signal
+ // Bus-switch SI4 to MI0 signals
+ wire i_sel4to0; // Routing selection signal
+ wire i_active4to0; // Active signal
+
+ // Bus-switch SI4 to MI1 signals
+ wire i_sel4to1; // Routing selection signal
+ wire i_active4to1; // Active signal
+
+ // Bus-switch SI4 to MI2 signals
+ wire i_sel4to2; // Routing selection signal
+ wire i_active4to2; // Active signal
+
+ // Bus-switch SI4 to MI3 signals
+ wire i_sel4to3; // Routing selection signal
+ wire i_active4to3; // Active signal
+
+ // Bus-switch SI4 to MI4 signals
+ wire i_sel4to4; // Routing selection signal
+ wire i_active4to4; // Active signal
+
+ // Bus-switch SI4 to MI5 signals
+ wire i_sel4to5; // Routing selection signal
+ wire i_active4to5; // Active signal
+
+ // Bus-switch SI4 to MI6 signals
+ wire i_sel4to6; // Routing selection signal
+ wire i_active4to6; // Active signal
+
+ // Bus-switch SI5 to MI0 signals
+ wire i_sel5to0; // Routing selection signal
+ wire i_active5to0; // Active signal
+
+ // Bus-switch SI5 to MI1 signals
+ wire i_sel5to1; // Routing selection signal
+ wire i_active5to1; // Active signal
+
+ // Bus-switch SI5 to MI2 signals
+ wire i_sel5to2; // Routing selection signal
+ wire i_active5to2; // Active signal
+
+ // Bus-switch SI5 to MI3 signals
+ wire i_sel5to3; // Routing selection signal
+ wire i_active5to3; // Active signal
+
+ // Bus-switch SI5 to MI4 signals
+ wire i_sel5to4; // Routing selection signal
+ wire i_active5to4; // Active signal
+
+ // Bus-switch SI5 to MI5 signals
+ wire i_sel5to5; // Routing selection signal
+ wire i_active5to5; // Active signal
+
+ // Bus-switch SI5 to MI6 signals
+ wire i_sel5to6; // Routing selection signal
+ wire i_active5to6; // Active signal
+
+ // Bus-switch SI5 to MI7 signals
+ wire i_sel5to7; // Routing selection signal
+ wire i_active5to7; // Active signal
wire i_hready_mux__bootrom_0; // Internal HREADYMUXM for MI0
wire i_hready_mux__imem_0; // Internal HREADYMUXM for MI1
@@ -1068,16 +1262,16 @@ module nanosoc_busmatrix (
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_CPU_0),
- .HADDRS (HADDR_CPU_0),
- .HTRANSS (HTRANS_CPU_0),
- .HWRITES (HWRITE_CPU_0),
- .HSIZES (HSIZE_CPU_0),
- .HBURSTS (HBURST_CPU_0),
- .HPROTS (HPROT_CPU_0),
- .HMASTERS (HMASTER_CPU_0),
- .HMASTLOCKS (HMASTLOCK_CPU_0),
- .HREADYS (HREADY_CPU_0),
+ .HSELS (HSEL_DMAC_2),
+ .HADDRS (HADDR_DMAC_2),
+ .HTRANSS (HTRANS_DMAC_2),
+ .HWRITES (HWRITE_DMAC_2),
+ .HSIZES (HSIZE_DMAC_2),
+ .HBURSTS (HBURST_DMAC_2),
+ .HPROTS (HPROT_DMAC_2),
+ .HMASTERS (HMASTER_DMAC_2),
+ .HMASTLOCKS (HMASTLOCK_DMAC_2),
+ .HREADYS (HREADY_DMAC_2),
// Internal Response
.active_ip (i_active3),
@@ -1085,8 +1279,8 @@ module nanosoc_busmatrix (
.resp_ip (i_resp3),
// Input Port Response
- .HREADYOUTS (HREADYOUT_CPU_0),
- .HRESPS (HRESP_CPU_0),
+ .HREADYOUTS (HREADYOUT_DMAC_2),
+ .HRESPS (HRESP_DMAC_2),
// Internal Address/Control Signals
.sel_ip (i_sel3),
@@ -1103,6 +1297,92 @@ module nanosoc_busmatrix (
);
+ // Input stage for SI4
+ nanosoc_inititator_input u_nanosoc_inititator_input_4 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL_DMAC_3),
+ .HADDRS (HADDR_DMAC_3),
+ .HTRANSS (HTRANS_DMAC_3),
+ .HWRITES (HWRITE_DMAC_3),
+ .HSIZES (HSIZE_DMAC_3),
+ .HBURSTS (HBURST_DMAC_3),
+ .HPROTS (HPROT_DMAC_3),
+ .HMASTERS (HMASTER_DMAC_3),
+ .HMASTLOCKS (HMASTLOCK_DMAC_3),
+ .HREADYS (HREADY_DMAC_3),
+
+ // Internal Response
+ .active_ip (i_active4),
+ .readyout_ip (i_readyout4),
+ .resp_ip (i_resp4),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT_DMAC_3),
+ .HRESPS (HRESP_DMAC_3),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel4),
+ .addr_ip (i_addr4),
+ .trans_ip (i_trans4),
+ .write_ip (i_write4),
+ .size_ip (i_size4),
+ .burst_ip (i_burst4),
+ .prot_ip (i_prot4),
+ .master_ip (i_master4),
+ .mastlock_ip (i_mastlock4),
+ .held_tran_ip (i_held_tran4)
+
+ );
+
+
+ // Input stage for SI5
+ nanosoc_inititator_input u_nanosoc_inititator_input_5 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input Port Address/Control Signals
+ .HSELS (HSEL_CPU_0),
+ .HADDRS (HADDR_CPU_0),
+ .HTRANSS (HTRANS_CPU_0),
+ .HWRITES (HWRITE_CPU_0),
+ .HSIZES (HSIZE_CPU_0),
+ .HBURSTS (HBURST_CPU_0),
+ .HPROTS (HPROT_CPU_0),
+ .HMASTERS (HMASTER_CPU_0),
+ .HMASTLOCKS (HMASTLOCK_CPU_0),
+ .HREADYS (HREADY_CPU_0),
+
+ // Internal Response
+ .active_ip (i_active5),
+ .readyout_ip (i_readyout5),
+ .resp_ip (i_resp5),
+
+ // Input Port Response
+ .HREADYOUTS (HREADYOUT_CPU_0),
+ .HRESPS (HRESP_CPU_0),
+
+ // Internal Address/Control Signals
+ .sel_ip (i_sel5),
+ .addr_ip (i_addr5),
+ .trans_ip (i_trans5),
+ .write_ip (i_write5),
+ .size_ip (i_size5),
+ .burst_ip (i_burst5),
+ .prot_ip (i_prot5),
+ .master_ip (i_master5),
+ .mastlock_ip (i_mastlock5),
+ .held_tran_ip (i_held_tran5)
+
+ );
+
+
// Matrix decoder for SI0
nanosoc_matrix_decode_DEBUG u_nanosoc_matrix_decode_debug (
@@ -1327,17 +1607,14 @@ module nanosoc_busmatrix (
// Matrix decoder for SI3
- nanosoc_matrix_decode_CPU_0 u_nanosoc_matrix_decode_cpu_0 (
+ nanosoc_matrix_decode_DMAC_2 u_nanosoc_matrix_decode_dmac_2 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
- // Internal address remapping control
- .remapping_dec ( REMAP[0] ),
-
// Signals from Input stage SI3
- .HREADYS (HREADY_CPU_0),
+ .HREADYS (HREADY_DMAC_2),
.sel_dec (i_sel3),
.decode_addr_dec (i_addr3[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans3),
@@ -1384,12 +1661,6 @@ module nanosoc_busmatrix (
.resp_dec6 (HRESP_EXP),
.rdata_dec6 (HRDATA_EXP),
- // Control/Response for Output Stage MI7
- .active_dec7 (i_active3to7),
- .readyout_dec7 (i_hready_mux__systable),
- .resp_dec7 (HRESP_SYSTABLE),
- .rdata_dec7 (HRDATA_SYSTABLE),
-
.sel_dec0 (i_sel3to0),
.sel_dec1 (i_sel3to1),
.sel_dec2 (i_sel3to2),
@@ -1397,11 +1668,162 @@ module nanosoc_busmatrix (
.sel_dec4 (i_sel3to4),
.sel_dec5 (i_sel3to5),
.sel_dec6 (i_sel3to6),
- .sel_dec7 (i_sel3to7),
.active_dec (i_active3),
.HREADYOUTS (i_readyout3),
.HRESPS (i_resp3),
+ .HRDATAS (HRDATA_DMAC_2)
+
+ );
+
+
+ // Matrix decoder for SI4
+ nanosoc_matrix_decode_DMAC_3 u_nanosoc_matrix_decode_dmac_3 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Signals from Input stage SI4
+ .HREADYS (HREADY_DMAC_3),
+ .sel_dec (i_sel4),
+ .decode_addr_dec (i_addr4[31:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans4),
+
+ // Control/Response for Output Stage MI0
+ .active_dec0 (i_active4to0),
+ .readyout_dec0 (i_hready_mux__bootrom_0),
+ .resp_dec0 (HRESP_BOOTROM_0),
+ .rdata_dec0 (HRDATA_BOOTROM_0),
+
+ // Control/Response for Output Stage MI1
+ .active_dec1 (i_active4to1),
+ .readyout_dec1 (i_hready_mux__imem_0),
+ .resp_dec1 (HRESP_IMEM_0),
+ .rdata_dec1 (HRDATA_IMEM_0),
+
+ // Control/Response for Output Stage MI2
+ .active_dec2 (i_active4to2),
+ .readyout_dec2 (i_hready_mux__dmem_0),
+ .resp_dec2 (HRESP_DMEM_0),
+ .rdata_dec2 (HRDATA_DMEM_0),
+
+ // Control/Response for Output Stage MI3
+ .active_dec3 (i_active4to3),
+ .readyout_dec3 (i_hready_mux__sysio),
+ .resp_dec3 (HRESP_SYSIO),
+ .rdata_dec3 (HRDATA_SYSIO),
+
+ // Control/Response for Output Stage MI4
+ .active_dec4 (i_active4to4),
+ .readyout_dec4 (i_hready_mux__expram_l),
+ .resp_dec4 (HRESP_EXPRAM_L),
+ .rdata_dec4 (HRDATA_EXPRAM_L),
+
+ // Control/Response for Output Stage MI5
+ .active_dec5 (i_active4to5),
+ .readyout_dec5 (i_hready_mux__expram_h),
+ .resp_dec5 (HRESP_EXPRAM_H),
+ .rdata_dec5 (HRDATA_EXPRAM_H),
+
+ // Control/Response for Output Stage MI6
+ .active_dec6 (i_active4to6),
+ .readyout_dec6 (i_hready_mux__exp),
+ .resp_dec6 (HRESP_EXP),
+ .rdata_dec6 (HRDATA_EXP),
+
+ .sel_dec0 (i_sel4to0),
+ .sel_dec1 (i_sel4to1),
+ .sel_dec2 (i_sel4to2),
+ .sel_dec3 (i_sel4to3),
+ .sel_dec4 (i_sel4to4),
+ .sel_dec5 (i_sel4to5),
+ .sel_dec6 (i_sel4to6),
+
+ .active_dec (i_active4),
+ .HREADYOUTS (i_readyout4),
+ .HRESPS (i_resp4),
+ .HRDATAS (HRDATA_DMAC_3)
+
+ );
+
+
+ // Matrix decoder for SI5
+ nanosoc_matrix_decode_CPU_0 u_nanosoc_matrix_decode_cpu_0 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Internal address remapping control
+ .remapping_dec ( REMAP[0] ),
+
+ // Signals from Input stage SI5
+ .HREADYS (HREADY_CPU_0),
+ .sel_dec (i_sel5),
+ .decode_addr_dec (i_addr5[31:10]), // HADDR[9:0] is not decoded
+ .trans_dec (i_trans5),
+
+ // Control/Response for Output Stage MI0
+ .active_dec0 (i_active5to0),
+ .readyout_dec0 (i_hready_mux__bootrom_0),
+ .resp_dec0 (HRESP_BOOTROM_0),
+ .rdata_dec0 (HRDATA_BOOTROM_0),
+
+ // Control/Response for Output Stage MI1
+ .active_dec1 (i_active5to1),
+ .readyout_dec1 (i_hready_mux__imem_0),
+ .resp_dec1 (HRESP_IMEM_0),
+ .rdata_dec1 (HRDATA_IMEM_0),
+
+ // Control/Response for Output Stage MI2
+ .active_dec2 (i_active5to2),
+ .readyout_dec2 (i_hready_mux__dmem_0),
+ .resp_dec2 (HRESP_DMEM_0),
+ .rdata_dec2 (HRDATA_DMEM_0),
+
+ // Control/Response for Output Stage MI3
+ .active_dec3 (i_active5to3),
+ .readyout_dec3 (i_hready_mux__sysio),
+ .resp_dec3 (HRESP_SYSIO),
+ .rdata_dec3 (HRDATA_SYSIO),
+
+ // Control/Response for Output Stage MI4
+ .active_dec4 (i_active5to4),
+ .readyout_dec4 (i_hready_mux__expram_l),
+ .resp_dec4 (HRESP_EXPRAM_L),
+ .rdata_dec4 (HRDATA_EXPRAM_L),
+
+ // Control/Response for Output Stage MI5
+ .active_dec5 (i_active5to5),
+ .readyout_dec5 (i_hready_mux__expram_h),
+ .resp_dec5 (HRESP_EXPRAM_H),
+ .rdata_dec5 (HRDATA_EXPRAM_H),
+
+ // Control/Response for Output Stage MI6
+ .active_dec6 (i_active5to6),
+ .readyout_dec6 (i_hready_mux__exp),
+ .resp_dec6 (HRESP_EXP),
+ .rdata_dec6 (HRDATA_EXP),
+
+ // Control/Response for Output Stage MI7
+ .active_dec7 (i_active5to7),
+ .readyout_dec7 (i_hready_mux__systable),
+ .resp_dec7 (HRESP_SYSTABLE),
+ .rdata_dec7 (HRDATA_SYSTABLE),
+
+ .sel_dec0 (i_sel5to0),
+ .sel_dec1 (i_sel5to1),
+ .sel_dec2 (i_sel5to2),
+ .sel_dec3 (i_sel5to3),
+ .sel_dec4 (i_sel5to4),
+ .sel_dec5 (i_sel5to5),
+ .sel_dec6 (i_sel5to6),
+ .sel_dec7 (i_sel5to7),
+
+ .active_dec (i_active5),
+ .HREADYOUTS (i_readyout5),
+ .HRESPS (i_resp5),
.HRDATAS (HRDATA_CPU_0)
);
@@ -1463,9 +1885,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to0),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to0),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_BOOTROM_0),
@@ -1473,6 +1921,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to0),
.active_op2 (i_active2to0),
.active_op3 (i_active3to0),
+ .active_op4 (i_active4to0),
+ .active_op5 (i_active5to0),
// Slave Address/Control Signals
.HSELM (HSEL_BOOTROM_0),
@@ -1549,9 +1999,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to1),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to1),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_IMEM_0),
@@ -1559,6 +2035,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to1),
.active_op2 (i_active2to1),
.active_op3 (i_active3to1),
+ .active_op4 (i_active4to1),
+ .active_op5 (i_active5to1),
// Slave Address/Control Signals
.HSELM (HSEL_IMEM_0),
@@ -1635,9 +2113,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to2),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to2),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_DMEM_0),
@@ -1645,6 +2149,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to2),
.active_op2 (i_active2to2),
.active_op3 (i_active3to2),
+ .active_op4 (i_active4to2),
+ .active_op5 (i_active5to2),
// Slave Address/Control Signals
.HSELM (HSEL_DMEM_0),
@@ -1721,9 +2227,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to3),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to3),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_SYSIO),
@@ -1731,6 +2263,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to3),
.active_op2 (i_active2to3),
.active_op3 (i_active3to3),
+ .active_op4 (i_active4to3),
+ .active_op5 (i_active5to3),
// Slave Address/Control Signals
.HSELM (HSEL_SYSIO),
@@ -1807,9 +2341,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to4),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to4),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_EXPRAM_L),
@@ -1817,6 +2377,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to4),
.active_op2 (i_active2to4),
.active_op3 (i_active3to4),
+ .active_op4 (i_active4to4),
+ .active_op5 (i_active5to4),
// Slave Address/Control Signals
.HSELM (HSEL_EXPRAM_L),
@@ -1893,9 +2455,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to5),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to5),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_EXPRAM_H),
@@ -1903,6 +2491,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to5),
.active_op2 (i_active2to5),
.active_op3 (i_active3to5),
+ .active_op4 (i_active4to5),
+ .active_op5 (i_active5to5),
// Slave Address/Control Signals
.HSELM (HSEL_EXPRAM_H),
@@ -1979,9 +2569,35 @@ module nanosoc_busmatrix (
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
+ .wdata_op3 (HWDATA_DMAC_2),
.held_tran_op3 (i_held_tran3),
+ // Port 4 Signals
+ .sel_op4 (i_sel4to6),
+ .addr_op4 (i_addr4),
+ .trans_op4 (i_trans4),
+ .write_op4 (i_write4),
+ .size_op4 (i_size4),
+ .burst_op4 (i_burst4),
+ .prot_op4 (i_prot4),
+ .master_op4 (i_master4),
+ .mastlock_op4 (i_mastlock4),
+ .wdata_op4 (HWDATA_DMAC_3),
+ .held_tran_op4 (i_held_tran4),
+
+ // Port 5 Signals
+ .sel_op5 (i_sel5to6),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
+
// Slave read data and response
.HREADYOUTM (HREADYOUT_EXP),
@@ -1989,6 +2605,8 @@ module nanosoc_busmatrix (
.active_op1 (i_active1to6),
.active_op2 (i_active2to6),
.active_op3 (i_active3to6),
+ .active_op4 (i_active4to6),
+ .active_op5 (i_active5to6),
// Slave Address/Control Signals
.HSELM (HSEL_EXP),
@@ -2029,24 +2647,24 @@ module nanosoc_busmatrix (
.wdata_op0 (HWDATA_DEBUG),
.held_tran_op0 (i_held_tran0),
- // Port 3 Signals
- .sel_op3 (i_sel3to7),
- .addr_op3 (i_addr3),
- .trans_op3 (i_trans3),
- .write_op3 (i_write3),
- .size_op3 (i_size3),
- .burst_op3 (i_burst3),
- .prot_op3 (i_prot3),
- .master_op3 (i_master3),
- .mastlock_op3 (i_mastlock3),
- .wdata_op3 (HWDATA_CPU_0),
- .held_tran_op3 (i_held_tran3),
+ // Port 5 Signals
+ .sel_op5 (i_sel5to7),
+ .addr_op5 (i_addr5),
+ .trans_op5 (i_trans5),
+ .write_op5 (i_write5),
+ .size_op5 (i_size5),
+ .burst_op5 (i_burst5),
+ .prot_op5 (i_prot5),
+ .master_op5 (i_master5),
+ .mastlock_op5 (i_mastlock5),
+ .wdata_op5 (HWDATA_CPU_0),
+ .held_tran_op5 (i_held_tran5),
// Slave read data and response
.HREADYOUTM (HREADYOUT_SYSTABLE),
.active_op0 (i_active0to7),
- .active_op3 (i_active3to7),
+ .active_op5 (i_active5to7),
// Slave Address/Control Signals
.HSELM (HSEL_SYSTABLE),
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
index f96bab0acd2ced0fbee9377e9549d669cf8d0f11..1151eb12ccad0d95f10e446101a5b97c1d57afa0 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
index f10532b57d41779da310eb8beb08f555895c44fa..fab85a690fbffa5c1b8b6c8fd40f53f645e25d09 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -70,6 +70,26 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_DMAC_1,
// Input port SI3 (inputs from master 3)
+ HADDR_DMAC_2,
+ HTRANS_DMAC_2,
+ HWRITE_DMAC_2,
+ HSIZE_DMAC_2,
+ HBURST_DMAC_2,
+ HPROT_DMAC_2,
+ HWDATA_DMAC_2,
+ HMASTLOCK_DMAC_2,
+
+ // Input port SI4 (inputs from master 4)
+ HADDR_DMAC_3,
+ HTRANS_DMAC_3,
+ HWRITE_DMAC_3,
+ HSIZE_DMAC_3,
+ HBURST_DMAC_3,
+ HPROT_DMAC_3,
+ HWDATA_DMAC_3,
+ HMASTLOCK_DMAC_3,
+
+ // Input port SI5 (inputs from master 5)
HADDR_CPU_0,
HTRANS_CPU_0,
HWRITE_CPU_0,
@@ -236,6 +256,16 @@ module nanosoc_busmatrix_lite (
HRESP_DMAC_1,
// Input port SI3 (outputs to master 3)
+ HRDATA_DMAC_2,
+ HREADY_DMAC_2,
+ HRESP_DMAC_2,
+
+ // Input port SI4 (outputs to master 4)
+ HRDATA_DMAC_3,
+ HREADY_DMAC_3,
+ HRESP_DMAC_3,
+
+ // Input port SI5 (outputs to master 5)
HRDATA_CPU_0,
HREADY_CPU_0,
HRESP_CPU_0,
@@ -287,6 +317,26 @@ module nanosoc_busmatrix_lite (
input HMASTLOCK_DMAC_1; // Locked Sequence
// Input port SI3 (inputs from master 3)
+ input [31:0] HADDR_DMAC_2; // Address bus
+ input [1:0] HTRANS_DMAC_2; // Transfer type
+ input HWRITE_DMAC_2; // Transfer direction
+ input [2:0] HSIZE_DMAC_2; // Transfer size
+ input [2:0] HBURST_DMAC_2; // Burst type
+ input [3:0] HPROT_DMAC_2; // Protection control
+ input [31:0] HWDATA_DMAC_2; // Write data
+ input HMASTLOCK_DMAC_2; // Locked Sequence
+
+ // Input port SI4 (inputs from master 4)
+ input [31:0] HADDR_DMAC_3; // Address bus
+ input [1:0] HTRANS_DMAC_3; // Transfer type
+ input HWRITE_DMAC_3; // Transfer direction
+ input [2:0] HSIZE_DMAC_3; // Transfer size
+ input [2:0] HBURST_DMAC_3; // Burst type
+ input [3:0] HPROT_DMAC_3; // Protection control
+ input [31:0] HWDATA_DMAC_3; // Write data
+ input HMASTLOCK_DMAC_3; // Locked Sequence
+
+ // Input port SI5 (inputs from master 5)
input [31:0] HADDR_CPU_0; // Address bus
input [1:0] HTRANS_CPU_0; // Transfer type
input HWRITE_CPU_0; // Transfer direction
@@ -453,6 +503,16 @@ module nanosoc_busmatrix_lite (
output HRESP_DMAC_1; // Transfer response
// Input port SI3 (outputs to master 3)
+ output [31:0] HRDATA_DMAC_2; // Read data bus
+ output HREADY_DMAC_2; // HREADY feedback
+ output HRESP_DMAC_2; // Transfer response
+
+ // Input port SI4 (outputs to master 4)
+ output [31:0] HRDATA_DMAC_3; // Read data bus
+ output HREADY_DMAC_3; // HREADY feedback
+ output HRESP_DMAC_3; // Transfer response
+
+ // Input port SI5 (outputs to master 5)
output [31:0] HRDATA_CPU_0; // Read data bus
output HREADY_CPU_0; // HREADY feedback
output HRESP_CPU_0; // Transfer response
@@ -514,6 +574,34 @@ module nanosoc_busmatrix_lite (
wire HRESP_DMAC_1; // Transfer response
// Input Port SI3
+ wire [31:0] HADDR_DMAC_2; // Address bus
+ wire [1:0] HTRANS_DMAC_2; // Transfer type
+ wire HWRITE_DMAC_2; // Transfer direction
+ wire [2:0] HSIZE_DMAC_2; // Transfer size
+ wire [2:0] HBURST_DMAC_2; // Burst type
+ wire [3:0] HPROT_DMAC_2; // Protection control
+ wire [31:0] HWDATA_DMAC_2; // Write data
+ wire HMASTLOCK_DMAC_2; // Locked Sequence
+
+ wire [31:0] HRDATA_DMAC_2; // Read data bus
+ wire HREADY_DMAC_2; // HREADY feedback
+ wire HRESP_DMAC_2; // Transfer response
+
+ // Input Port SI4
+ wire [31:0] HADDR_DMAC_3; // Address bus
+ wire [1:0] HTRANS_DMAC_3; // Transfer type
+ wire HWRITE_DMAC_3; // Transfer direction
+ wire [2:0] HSIZE_DMAC_3; // Transfer size
+ wire [2:0] HBURST_DMAC_3; // Burst type
+ wire [3:0] HPROT_DMAC_3; // Protection control
+ wire [31:0] HWDATA_DMAC_3; // Write data
+ wire HMASTLOCK_DMAC_3; // Locked Sequence
+
+ wire [31:0] HRDATA_DMAC_3; // Read data bus
+ wire HREADY_DMAC_3; // HREADY feedback
+ wire HRESP_DMAC_3; // Transfer response
+
+ // Input Port SI5
wire [31:0] HADDR_CPU_0; // Address bus
wire [1:0] HTRANS_CPU_0; // Transfer type
wire HWRITE_CPU_0; // Transfer direction
@@ -665,6 +753,8 @@ module nanosoc_busmatrix_lite (
wire [1:0] i_hresp_DEBUG;
wire [1:0] i_hresp_DMAC_0;
wire [1:0] i_hresp_DMAC_1;
+ wire [1:0] i_hresp_DMAC_2;
+ wire [1:0] i_hresp_DMAC_3;
wire [1:0] i_hresp_CPU_0;
wire [3:0] i_hmaster_BOOTROM_0;
@@ -699,6 +789,10 @@ module nanosoc_busmatrix_lite (
assign HRESP_DMAC_1 = i_hresp_DMAC_1[0];
+ assign HRESP_DMAC_2 = i_hresp_DMAC_2[0];
+
+ assign HRESP_DMAC_3 = i_hresp_DMAC_3[0];
+
assign HRESP_CPU_0 = i_hresp_CPU_0[0];
assign i_hresp_BOOTROM_0 = {{1{tie_low}}, HRESP_BOOTROM_0};
@@ -765,6 +859,38 @@ module nanosoc_busmatrix_lite (
.HRESP_DMAC_1 (i_hresp_DMAC_1),
// Input port SI3 signals
+ .HSEL_DMAC_2 (tie_hi),
+ .HADDR_DMAC_2 (HADDR_DMAC_2),
+ .HTRANS_DMAC_2 (HTRANS_DMAC_2),
+ .HWRITE_DMAC_2 (HWRITE_DMAC_2),
+ .HSIZE_DMAC_2 (HSIZE_DMAC_2),
+ .HBURST_DMAC_2 (HBURST_DMAC_2),
+ .HPROT_DMAC_2 (HPROT_DMAC_2),
+ .HWDATA_DMAC_2 (HWDATA_DMAC_2),
+ .HMASTLOCK_DMAC_2 (HMASTLOCK_DMAC_2),
+ .HMASTER_DMAC_2 (tie_hi_4),
+ .HREADY_DMAC_2 (HREADY_DMAC_2),
+ .HRDATA_DMAC_2 (HRDATA_DMAC_2),
+ .HREADYOUT_DMAC_2 (HREADY_DMAC_2),
+ .HRESP_DMAC_2 (i_hresp_DMAC_2),
+
+ // Input port SI4 signals
+ .HSEL_DMAC_3 (tie_hi),
+ .HADDR_DMAC_3 (HADDR_DMAC_3),
+ .HTRANS_DMAC_3 (HTRANS_DMAC_3),
+ .HWRITE_DMAC_3 (HWRITE_DMAC_3),
+ .HSIZE_DMAC_3 (HSIZE_DMAC_3),
+ .HBURST_DMAC_3 (HBURST_DMAC_3),
+ .HPROT_DMAC_3 (HPROT_DMAC_3),
+ .HWDATA_DMAC_3 (HWDATA_DMAC_3),
+ .HMASTLOCK_DMAC_3 (HMASTLOCK_DMAC_3),
+ .HMASTER_DMAC_3 (tie_hi_4),
+ .HREADY_DMAC_3 (HREADY_DMAC_3),
+ .HRDATA_DMAC_3 (HRDATA_DMAC_3),
+ .HREADYOUT_DMAC_3 (HREADY_DMAC_3),
+ .HRESP_DMAC_3 (i_hresp_DMAC_3),
+
+ // Input port SI5 signals
.HSEL_CPU_0 (tie_hi),
.HADDR_CPU_0 (HADDR_CPU_0),
.HTRANS_CPU_0 (HTRANS_CPU_0),
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
index d770544cbae49d558bc2dc307f80a4a09ec16aa3..326dfdf1e50211db4b2f85c9c28e6d87baee1e15 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
index 56ac92a2eb48f34a05e53fa1b48c3de459426ef7..d78033903535bf8066f1c4f319015ce004811f22 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
index 19fe1e92d401eb537dea999522cbfef72adbfb5d..c13a1de726384850c6d464d7e05d99af0f58b75d 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
index 3168cdcc67e04382a2ca1d1f527368cf136937b1..bd612081b7d835f599d706ce8bfe9136bc00d7e7 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
index de20dcb82bfe62cdcc90b29355dfcf82a784f3cd..d32cc6e1002fdd529099e18bcbd016b42e19237f 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v
new file mode 100644
index 0000000000000000000000000000000000000000..2b180d1c76a2248104f506813d0c4148bc0c1c2b
--- /dev/null
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_2.v
@@ -0,0 +1,515 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_matrix_decode_DMAC_2 (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+ // Bus-switch output 0
+ active_dec0,
+ readyout_dec0,
+ resp_dec0,
+ rdata_dec0,
+
+ // Bus-switch output 1
+ active_dec1,
+ readyout_dec1,
+ resp_dec1,
+ rdata_dec1,
+
+ // Bus-switch output 2
+ active_dec2,
+ readyout_dec2,
+ resp_dec2,
+ rdata_dec2,
+
+ // Bus-switch output 3
+ active_dec3,
+ readyout_dec3,
+ resp_dec3,
+ rdata_dec3,
+
+ // Bus-switch output 4
+ active_dec4,
+ readyout_dec4,
+ resp_dec4,
+ rdata_dec4,
+
+ // Bus-switch output 5
+ active_dec5,
+ readyout_dec5,
+ resp_dec5,
+ rdata_dec5,
+
+ // Bus-switch output 6
+ active_dec6,
+ readyout_dec6,
+ resp_dec6,
+ rdata_dec6,
+
+ // Output port selection signals
+ sel_dec0,
+ sel_dec1,
+ sel_dec2,
+ sel_dec3,
+ sel_dec4,
+ sel_dec5,
+ sel_dec6,
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [31:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ input active_dec0; // Output stage MI0 active_dec signal
+ input readyout_dec0; // HREADYOUT input
+ input [1:0] resp_dec0; // HRESP input
+ input [31:0] rdata_dec0; // HRDATA input
+
+ // Bus-switch output MI1
+ input active_dec1; // Output stage MI1 active_dec signal
+ input readyout_dec1; // HREADYOUT input
+ input [1:0] resp_dec1; // HRESP input
+ input [31:0] rdata_dec1; // HRDATA input
+
+ // Bus-switch output MI2
+ input active_dec2; // Output stage MI2 active_dec signal
+ input readyout_dec2; // HREADYOUT input
+ input [1:0] resp_dec2; // HRESP input
+ input [31:0] rdata_dec2; // HRDATA input
+
+ // Bus-switch output MI3
+ input active_dec3; // Output stage MI3 active_dec signal
+ input readyout_dec3; // HREADYOUT input
+ input [1:0] resp_dec3; // HRESP input
+ input [31:0] rdata_dec3; // HRDATA input
+
+ // Bus-switch output MI4
+ input active_dec4; // Output stage MI4 active_dec signal
+ input readyout_dec4; // HREADYOUT input
+ input [1:0] resp_dec4; // HRESP input
+ input [31:0] rdata_dec4; // HRDATA input
+
+ // Bus-switch output MI5
+ input active_dec5; // Output stage MI5 active_dec signal
+ input readyout_dec5; // HREADYOUT input
+ input [1:0] resp_dec5; // HRESP input
+ input [31:0] rdata_dec5; // HRDATA input
+
+ // Bus-switch output MI6
+ input active_dec6; // Output stage MI6 active_dec signal
+ input readyout_dec6; // HREADYOUT input
+ input [1:0] resp_dec6; // HRESP input
+ input [31:0] rdata_dec6; // HRDATA input
+
+ // Output port selection signals
+ output sel_dec0; // HSEL output
+ output sel_dec1; // HSEL output
+ output sel_dec2; // HSEL output
+ output sel_dec3; // HSEL output
+ output sel_dec4; // HSEL output
+ output sel_dec5; // HSEL output
+ output sel_dec6; // HSEL output
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [1:0] HRESPS; // Transfer response
+ output [31:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [31:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ wire active_dec0; // active_dec signal
+ wire readyout_dec0; // HREADYOUT input
+ wire [1:0] resp_dec0; // HRESP input
+ wire [31:0] rdata_dec0; // HRDATA input
+ reg sel_dec0; // HSEL output
+
+ // Bus-switch output MI1
+ wire active_dec1; // active_dec signal
+ wire readyout_dec1; // HREADYOUT input
+ wire [1:0] resp_dec1; // HRESP input
+ wire [31:0] rdata_dec1; // HRDATA input
+ reg sel_dec1; // HSEL output
+
+ // Bus-switch output MI2
+ wire active_dec2; // active_dec signal
+ wire readyout_dec2; // HREADYOUT input
+ wire [1:0] resp_dec2; // HRESP input
+ wire [31:0] rdata_dec2; // HRDATA input
+ reg sel_dec2; // HSEL output
+
+ // Bus-switch output MI3
+ wire active_dec3; // active_dec signal
+ wire readyout_dec3; // HREADYOUT input
+ wire [1:0] resp_dec3; // HRESP input
+ wire [31:0] rdata_dec3; // HRDATA input
+ reg sel_dec3; // HSEL output
+
+ // Bus-switch output MI4
+ wire active_dec4; // active_dec signal
+ wire readyout_dec4; // HREADYOUT input
+ wire [1:0] resp_dec4; // HRESP input
+ wire [31:0] rdata_dec4; // HRDATA input
+ reg sel_dec4; // HSEL output
+
+ // Bus-switch output MI5
+ wire active_dec5; // active_dec signal
+ wire readyout_dec5; // HREADYOUT input
+ wire [1:0] resp_dec5; // HRESP input
+ wire [31:0] rdata_dec5; // HRDATA input
+ reg sel_dec5; // HSEL output
+
+ // Bus-switch output MI6
+ wire active_dec6; // active_dec signal
+ wire readyout_dec6; // HREADYOUT input
+ wire [1:0] resp_dec6; // HRESP input
+ wire [31:0] rdata_dec6; // HRDATA input
+ reg sel_dec6; // HSEL output
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [1:0] HRESPS; // Combinatorial HRESPS signal
+ reg [31:0] HRDATAS; // Read data bus
+
+ reg [3:0] addr_out_port; // Address output ports
+ reg [3:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ nanosoc_busmatrix_default_slave u_nanosoc_busmatrix_default_slave (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[31:10], which is not a hex character boundary
+
+ always @ (
+ decode_addr_dec or data_out_port or trans_dec
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+ // Address region 0x10000000-0x1fffffff
+ if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+ // Address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+ sel_dec0 = 1'b0;
+ sel_dec1 = 1'b0;
+ sel_dec2 = 1'b0;
+ sel_dec3 = 1'b0;
+ sel_dec4 = 1'b0;
+ sel_dec5 = 1'b0;
+ sel_dec6 = 1'b0;
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+ 4'b0000 : sel_dec0 = 1'b1;
+ 4'b0001 : sel_dec1 = 1'b1;
+ 4'b0010 : sel_dec2 = 1'b1;
+ 4'b0011 : sel_dec3 = 1'b1;
+ 4'b0100 : sel_dec4 = 1'b1;
+ 4'b0101 : sel_dec5 = 1'b1;
+ 4'b0110 : sel_dec6 = 1'b1;
+ 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+ sel_dec0 = 1'bx;
+ sel_dec1 = 1'bx;
+ sel_dec2 = 1'bx;
+ sel_dec3 = 1'bx;
+ sel_dec4 = 1'bx;
+ sel_dec5 = 1'bx;
+ sel_dec6 = 1'bx;
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+ active_dec0 or
+ active_dec1 or
+ active_dec2 or
+ active_dec3 or
+ active_dec4 or
+ active_dec5 or
+ active_dec6 or
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+ 4'b0000 : active_dec = active_dec0;
+ 4'b0001 : active_dec = active_dec1;
+ 4'b0010 : active_dec = active_dec2;
+ 4'b0011 : active_dec = active_dec3;
+ 4'b0100 : active_dec = active_dec4;
+ 4'b0101 : active_dec = active_dec5;
+ 4'b0110 : active_dec = active_dec6;
+ 4'b1000 : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= 4'b1000;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= 4'b1000;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+ readyout_dec0 or
+ readyout_dec1 or
+ readyout_dec2 or
+ readyout_dec3 or
+ readyout_dec4 or
+ readyout_dec5 or
+ readyout_dec6 or
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+ 4'b0000 : HREADYOUTS = readyout_dec0;
+ 4'b0001 : HREADYOUTS = readyout_dec1;
+ 4'b0010 : HREADYOUTS = readyout_dec2;
+ 4'b0011 : HREADYOUTS = readyout_dec3;
+ 4'b0100 : HREADYOUTS = readyout_dec4;
+ 4'b0101 : HREADYOUTS = readyout_dec5;
+ 4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+ resp_dec0 or
+ resp_dec1 or
+ resp_dec2 or
+ resp_dec3 or
+ resp_dec4 or
+ resp_dec5 or
+ resp_dec6 or
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+ 4'b0000 : HRESPS = resp_dec0;
+ 4'b0001 : HRESPS = resp_dec1;
+ 4'b0010 : HRESPS = resp_dec2;
+ 4'b0011 : HRESPS = resp_dec3;
+ 4'b0100 : HRESPS = resp_dec4;
+ 4'b0101 : HRESPS = resp_dec5;
+ 4'b0110 : HRESPS = resp_dec6;
+ 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+ rdata_dec0 or
+ rdata_dec1 or
+ rdata_dec2 or
+ rdata_dec3 or
+ rdata_dec4 or
+ rdata_dec5 or
+ rdata_dec6 or
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+ 4'b0000 : HRDATAS = rdata_dec0;
+ 4'b0001 : HRDATAS = rdata_dec1;
+ 4'b0010 : HRDATAS = rdata_dec2;
+ 4'b0011 : HRDATAS = rdata_dec3;
+ 4'b0100 : HRDATAS = rdata_dec4;
+ 4'b0101 : HRDATAS = rdata_dec5;
+ 4'b0110 : HRDATAS = rdata_dec6;
+ 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ default : HRDATAS = {32{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v
new file mode 100644
index 0000000000000000000000000000000000000000..67aa0784008b1479fbeaa6c94ed7c3d334668d7d
--- /dev/null
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_3.v
@@ -0,0 +1,515 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The MatrixDecode is used to determine which output
+// stage is required for a particular access. Addresses
+// that do not map to an Output port are diverted to
+// the local default slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_matrix_decode_DMAC_3 (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Signals from the Input stage
+ HREADYS,
+ sel_dec,
+ decode_addr_dec,
+ trans_dec,
+
+ // Bus-switch output 0
+ active_dec0,
+ readyout_dec0,
+ resp_dec0,
+ rdata_dec0,
+
+ // Bus-switch output 1
+ active_dec1,
+ readyout_dec1,
+ resp_dec1,
+ rdata_dec1,
+
+ // Bus-switch output 2
+ active_dec2,
+ readyout_dec2,
+ resp_dec2,
+ rdata_dec2,
+
+ // Bus-switch output 3
+ active_dec3,
+ readyout_dec3,
+ resp_dec3,
+ rdata_dec3,
+
+ // Bus-switch output 4
+ active_dec4,
+ readyout_dec4,
+ resp_dec4,
+ rdata_dec4,
+
+ // Bus-switch output 5
+ active_dec5,
+ readyout_dec5,
+ resp_dec5,
+ rdata_dec5,
+
+ // Bus-switch output 6
+ active_dec6,
+ readyout_dec6,
+ resp_dec6,
+ rdata_dec6,
+
+ // Output port selection signals
+ sel_dec0,
+ sel_dec1,
+ sel_dec2,
+ sel_dec3,
+ sel_dec4,
+ sel_dec5,
+ sel_dec6,
+
+ // Selected Output port data and control signals
+ active_dec,
+ HREADYOUTS,
+ HRESPS,
+ HRDATAS
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ input HREADYS; // Transfer done
+ input sel_dec; // HSEL input
+ input [31:10] decode_addr_dec; // HADDR decoder input
+ input [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ input active_dec0; // Output stage MI0 active_dec signal
+ input readyout_dec0; // HREADYOUT input
+ input [1:0] resp_dec0; // HRESP input
+ input [31:0] rdata_dec0; // HRDATA input
+
+ // Bus-switch output MI1
+ input active_dec1; // Output stage MI1 active_dec signal
+ input readyout_dec1; // HREADYOUT input
+ input [1:0] resp_dec1; // HRESP input
+ input [31:0] rdata_dec1; // HRDATA input
+
+ // Bus-switch output MI2
+ input active_dec2; // Output stage MI2 active_dec signal
+ input readyout_dec2; // HREADYOUT input
+ input [1:0] resp_dec2; // HRESP input
+ input [31:0] rdata_dec2; // HRDATA input
+
+ // Bus-switch output MI3
+ input active_dec3; // Output stage MI3 active_dec signal
+ input readyout_dec3; // HREADYOUT input
+ input [1:0] resp_dec3; // HRESP input
+ input [31:0] rdata_dec3; // HRDATA input
+
+ // Bus-switch output MI4
+ input active_dec4; // Output stage MI4 active_dec signal
+ input readyout_dec4; // HREADYOUT input
+ input [1:0] resp_dec4; // HRESP input
+ input [31:0] rdata_dec4; // HRDATA input
+
+ // Bus-switch output MI5
+ input active_dec5; // Output stage MI5 active_dec signal
+ input readyout_dec5; // HREADYOUT input
+ input [1:0] resp_dec5; // HRESP input
+ input [31:0] rdata_dec5; // HRDATA input
+
+ // Bus-switch output MI6
+ input active_dec6; // Output stage MI6 active_dec signal
+ input readyout_dec6; // HREADYOUT input
+ input [1:0] resp_dec6; // HRESP input
+ input [31:0] rdata_dec6; // HRDATA input
+
+ // Output port selection signals
+ output sel_dec0; // HSEL output
+ output sel_dec1; // HSEL output
+ output sel_dec2; // HSEL output
+ output sel_dec3; // HSEL output
+ output sel_dec4; // HSEL output
+ output sel_dec5; // HSEL output
+ output sel_dec6; // HSEL output
+
+ // Selected Output port data and control signals
+ output active_dec; // Combinatorial active_dec O/P
+ output HREADYOUTS; // HREADY feedback output
+ output [1:0] HRESPS; // Transfer response
+ output [31:0] HRDATAS; // Read Data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // Signals from the Input stage
+ wire HREADYS; // Transfer done
+ wire sel_dec; // HSEL input
+ wire [31:10] decode_addr_dec; // HADDR input
+ wire [1:0] trans_dec; // Input port HTRANS signal
+
+ // Bus-switch output MI0
+ wire active_dec0; // active_dec signal
+ wire readyout_dec0; // HREADYOUT input
+ wire [1:0] resp_dec0; // HRESP input
+ wire [31:0] rdata_dec0; // HRDATA input
+ reg sel_dec0; // HSEL output
+
+ // Bus-switch output MI1
+ wire active_dec1; // active_dec signal
+ wire readyout_dec1; // HREADYOUT input
+ wire [1:0] resp_dec1; // HRESP input
+ wire [31:0] rdata_dec1; // HRDATA input
+ reg sel_dec1; // HSEL output
+
+ // Bus-switch output MI2
+ wire active_dec2; // active_dec signal
+ wire readyout_dec2; // HREADYOUT input
+ wire [1:0] resp_dec2; // HRESP input
+ wire [31:0] rdata_dec2; // HRDATA input
+ reg sel_dec2; // HSEL output
+
+ // Bus-switch output MI3
+ wire active_dec3; // active_dec signal
+ wire readyout_dec3; // HREADYOUT input
+ wire [1:0] resp_dec3; // HRESP input
+ wire [31:0] rdata_dec3; // HRDATA input
+ reg sel_dec3; // HSEL output
+
+ // Bus-switch output MI4
+ wire active_dec4; // active_dec signal
+ wire readyout_dec4; // HREADYOUT input
+ wire [1:0] resp_dec4; // HRESP input
+ wire [31:0] rdata_dec4; // HRDATA input
+ reg sel_dec4; // HSEL output
+
+ // Bus-switch output MI5
+ wire active_dec5; // active_dec signal
+ wire readyout_dec5; // HREADYOUT input
+ wire [1:0] resp_dec5; // HRESP input
+ wire [31:0] rdata_dec5; // HRDATA input
+ reg sel_dec5; // HSEL output
+
+ // Bus-switch output MI6
+ wire active_dec6; // active_dec signal
+ wire readyout_dec6; // HREADYOUT input
+ wire [1:0] resp_dec6; // HRESP input
+ wire [31:0] rdata_dec6; // HRDATA input
+ reg sel_dec6; // HSEL output
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+
+ // Selected Output port data and control signals
+ reg active_dec; // Combinatorial active_dec O/P signal
+ reg HREADYOUTS; // Combinatorial HREADYOUT signal
+ reg [1:0] HRESPS; // Combinatorial HRESPS signal
+ reg [31:0] HRDATAS; // Read data bus
+
+ reg [3:0] addr_out_port; // Address output ports
+ reg [3:0] data_out_port; // Data output ports
+
+ // Default slave signals
+ reg sel_dft_slv; // HSEL signal
+ wire readyout_dft_slv; // HREADYOUT signal
+ wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Default slave (accessed when HADDR is unmapped)
+//------------------------------------------------------------------------------
+
+ nanosoc_busmatrix_default_slave u_nanosoc_busmatrix_default_slave (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // AHB Control signals
+ .HSEL (sel_dft_slv),
+ .HTRANS (trans_dec),
+ .HREADY (HREADYS),
+ .HREADYOUT (readyout_dft_slv),
+ .HRESP (resp_dft_slv)
+
+ );
+
+
+//------------------------------------------------------------------------------
+// Address phase signals
+//------------------------------------------------------------------------------
+
+// The address decode is done in two stages. This is so that the address
+// decode occurs in only one process, p_addr_out_portComb, and then the select
+// signal is factored in.
+//
+// Note that the hexadecimal address values are reformatted to align with the
+// lower bound of decode_addr_dec[31:10], which is not a hex character boundary
+
+ always @ (
+ decode_addr_dec or data_out_port or trans_dec
+ )
+ begin : p_addr_out_port_comb
+
+ // Only switch if there is an active transfer
+ if (trans_dec != 2'b00)
+ begin
+
+ // Address region 0x10000000-0x1fffffff
+ if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 4'b0000; // Select Output port MI0
+
+ // Address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+ // Address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 4'b0001; // Select Output port MI1
+
+ // Address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 4'b0010; // Select Output port MI2
+
+ // Address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 4'b0011; // Select Output port MI3
+
+ // Address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 4'b0100; // Select Output port MI4
+
+ // Address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 4'b0101; // Select Output port MI5
+
+ // Address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+ // Address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 4'b0110; // Select Output port MI6
+
+ else
+ addr_out_port = 4'b1000; // Select the default slave
+
+ end // if (trans_dec != 2'b00)
+ else
+ addr_out_port = data_out_port; // Stay on last port if no activity
+
+ end // block: p_addr_out_port_comb
+
+ // Select signal decode
+ always @ (sel_dec or addr_out_port)
+ begin : p_sel_comb
+ sel_dec0 = 1'b0;
+ sel_dec1 = 1'b0;
+ sel_dec2 = 1'b0;
+ sel_dec3 = 1'b0;
+ sel_dec4 = 1'b0;
+ sel_dec5 = 1'b0;
+ sel_dec6 = 1'b0;
+ sel_dft_slv = 1'b0;
+
+ if (sel_dec)
+ case (addr_out_port)
+ 4'b0000 : sel_dec0 = 1'b1;
+ 4'b0001 : sel_dec1 = 1'b1;
+ 4'b0010 : sel_dec2 = 1'b1;
+ 4'b0011 : sel_dec3 = 1'b1;
+ 4'b0100 : sel_dec4 = 1'b1;
+ 4'b0101 : sel_dec5 = 1'b1;
+ 4'b0110 : sel_dec6 = 1'b1;
+ 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ default : begin
+ sel_dec0 = 1'bx;
+ sel_dec1 = 1'bx;
+ sel_dec2 = 1'bx;
+ sel_dec3 = 1'bx;
+ sel_dec4 = 1'bx;
+ sel_dec5 = 1'bx;
+ sel_dec6 = 1'bx;
+ sel_dft_slv = 1'bx;
+ end
+ endcase // case(addr_out_port)
+ end // block: p_sel_comb
+
+// The decoder selects the appropriate active_dec signal depending on which
+// output stage is required for the transfer.
+ always @ (
+ active_dec0 or
+ active_dec1 or
+ active_dec2 or
+ active_dec3 or
+ active_dec4 or
+ active_dec5 or
+ active_dec6 or
+ addr_out_port
+ )
+ begin : p_active_comb
+ case (addr_out_port)
+ 4'b0000 : active_dec = active_dec0;
+ 4'b0001 : active_dec = active_dec1;
+ 4'b0010 : active_dec = active_dec2;
+ 4'b0011 : active_dec = active_dec3;
+ 4'b0100 : active_dec = active_dec4;
+ 4'b0101 : active_dec = active_dec5;
+ 4'b0110 : active_dec = active_dec6;
+ 4'b1000 : active_dec = 1'b1; // Select the default slave
+ default : active_dec = 1'bx;
+ endcase // case(addr_out_port)
+ end // block: p_active_comb
+
+
+//------------------------------------------------------------------------------
+// Data phase signals
+//------------------------------------------------------------------------------
+
+// The data_out_port needs to be updated when HREADY from the input stage is high.
+// Note: HREADY must be used, not HREADYOUT, because there are occaisions
+// (namely when the holding register gets loaded) when HREADYOUT may be low
+// but HREADY is high, and in this case it is important that the data_out_port
+// gets updated.
+// When the port is inactive, the default slave is selected to prevent toggling.
+
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_out_port_seq
+ if (~HRESETn)
+ data_out_port <= 4'b1000;
+ else
+ if (HREADYS)
+ if (sel_dec & trans_dec[1])
+ data_out_port <= addr_out_port;
+ else
+ data_out_port <= 4'b1000;
+ end // block: p_data_out_port_seq
+
+ // HREADYOUTS output decode
+ always @ (
+ readyout_dft_slv or
+ readyout_dec0 or
+ readyout_dec1 or
+ readyout_dec2 or
+ readyout_dec3 or
+ readyout_dec4 or
+ readyout_dec5 or
+ readyout_dec6 or
+ data_out_port
+ )
+ begin : p_ready_comb
+ case (data_out_port)
+ 4'b0000 : HREADYOUTS = readyout_dec0;
+ 4'b0001 : HREADYOUTS = readyout_dec1;
+ 4'b0010 : HREADYOUTS = readyout_dec2;
+ 4'b0011 : HREADYOUTS = readyout_dec3;
+ 4'b0100 : HREADYOUTS = readyout_dec4;
+ 4'b0101 : HREADYOUTS = readyout_dec5;
+ 4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ default : HREADYOUTS = 1'bx;
+ endcase // case(data_out_port)
+ end // block: p_ready_comb
+
+ // HRESPS output decode
+ always @ (
+ resp_dft_slv or
+ resp_dec0 or
+ resp_dec1 or
+ resp_dec2 or
+ resp_dec3 or
+ resp_dec4 or
+ resp_dec5 or
+ resp_dec6 or
+ data_out_port
+ )
+ begin : p_resp_comb
+ case (data_out_port)
+ 4'b0000 : HRESPS = resp_dec0;
+ 4'b0001 : HRESPS = resp_dec1;
+ 4'b0010 : HRESPS = resp_dec2;
+ 4'b0011 : HRESPS = resp_dec3;
+ 4'b0100 : HRESPS = resp_dec4;
+ 4'b0101 : HRESPS = resp_dec5;
+ 4'b0110 : HRESPS = resp_dec6;
+ 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ default : HRESPS = {2{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_resp_comb
+
+ // HRDATAS output decode
+ always @ (
+ rdata_dec0 or
+ rdata_dec1 or
+ rdata_dec2 or
+ rdata_dec3 or
+ rdata_dec4 or
+ rdata_dec5 or
+ rdata_dec6 or
+ data_out_port
+ )
+ begin : p_rdata_comb
+ case (data_out_port)
+ 4'b0000 : HRDATAS = rdata_dec0;
+ 4'b0001 : HRDATAS = rdata_dec1;
+ 4'b0010 : HRDATAS = rdata_dec2;
+ 4'b0011 : HRDATAS = rdata_dec3;
+ 4'b0100 : HRDATAS = rdata_dec4;
+ 4'b0101 : HRDATAS = rdata_dec5;
+ 4'b0110 : HRDATAS = rdata_dec6;
+ 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ default : HRDATAS = {32{1'bx}};
+ endcase // case (data_out_port)
+ end // block: p_rdata_comb
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
index d8f6faa12de9f41fe2e523e6f1c3f42ce9be1749..44c1f623ffcefd7bfac6bc52ed644abc1f806e03 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_BOOTROM_0 (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_BOOTROM_0 (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_BOOTROM_0 (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_BOOTROM_0 (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_BOOTROM_0 (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_BOOTROM_0 (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_BOOTROM_0 u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_BOOTROM_0 (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_BOOTROM_0 (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_BOOTROM_0 (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_BOOTROM_0 (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_BOOTROM_0 (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_BOOTROM_0 (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_BOOTROM_0 (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_BOOTROM_0 (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_BOOTROM_0 (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_BOOTROM_0 (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_BOOTROM_0 (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
index e06782c3c5bb7e27fafcd09541cfaecdabd7f178..a57cac80567c4479bda9523bf5b6f0e7a1985dbb 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_DMEM_0 (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_DMEM_0 (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_DMEM_0 (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_DMEM_0 (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_DMEM_0 (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_DMEM_0 (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_DMEM_0 u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_DMEM_0 (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_DMEM_0 (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_DMEM_0 (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_DMEM_0 (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_DMEM_0 (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_DMEM_0 (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_DMEM_0 (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_DMEM_0 (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_DMEM_0 (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_DMEM_0 (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_DMEM_0 (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
index aabb3151cda23a9bdb48506f3778e9aa527d824d..1b62c892574fc10dc8b03712b418cf444df672a7 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_EXP (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_EXP (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_EXP (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_EXP (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_EXP (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_EXP (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_EXP u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_EXP (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_EXP (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_EXP (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_EXP (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_EXP (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_EXP (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_EXP (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_EXP (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_EXP (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_EXP (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_EXP (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
index fa9842dbd9cf78a3b9af2d406ce5b92509716610..310718431dddcae8056fbd7518e8e46a796710b2 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_EXPRAM_H (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_EXPRAM_H (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_EXPRAM_H (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_EXPRAM_H (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_EXPRAM_H (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_EXPRAM_H (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_EXPRAM_H u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_EXPRAM_H (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_EXPRAM_H (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_EXPRAM_H (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_EXPRAM_H (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_EXPRAM_H (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_EXPRAM_H (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_EXPRAM_H (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_EXPRAM_H (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_EXPRAM_H (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_EXPRAM_H (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_EXPRAM_H (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
index d772da2bafc3b613335fb2230de3618b6f7b5b56..e892138bfbb8aafe0986fe3de4f954068bf92e9e 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_EXPRAM_L (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_EXPRAM_L (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_EXPRAM_L (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_EXPRAM_L (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_EXPRAM_L (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_EXPRAM_L (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_EXPRAM_L u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_EXPRAM_L (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_EXPRAM_L (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_EXPRAM_L (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_EXPRAM_L (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_EXPRAM_L (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_EXPRAM_L (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_EXPRAM_L (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_EXPRAM_L (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_EXPRAM_L (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_EXPRAM_L (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_EXPRAM_L (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
index b369f495bc2a930c3d4e1ceabdd53eee88cee5a9..e02a9495c43251b94fc5bcc6b96d15d25ae82268 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_IMEM_0 (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_IMEM_0 (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_IMEM_0 (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_IMEM_0 (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_IMEM_0 (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_IMEM_0 (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_IMEM_0 u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_IMEM_0 (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_IMEM_0 (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_IMEM_0 (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_IMEM_0 (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_IMEM_0 (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_IMEM_0 (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_IMEM_0 (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_IMEM_0 (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_IMEM_0 (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_IMEM_0 (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_IMEM_0 (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
index 86b47f186ec24ae027cac3849a5d248a28fab80e..446bd157061874abfe4801e8e7e19394efda916d 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -90,6 +90,32 @@ module nanosoc_target_output_SYSIO (
wdata_op3,
held_tran_op3,
+ // Port 4 Signals
+ sel_op4,
+ addr_op4,
+ trans_op4,
+ write_op4,
+ size_op4,
+ burst_op4,
+ prot_op4,
+ master_op4,
+ mastlock_op4,
+ wdata_op4,
+ held_tran_op4,
+
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
+
// Slave read data and response
HREADYOUTM,
@@ -97,6 +123,8 @@ module nanosoc_target_output_SYSIO (
active_op1,
active_op2,
active_op3,
+ active_op4,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -174,12 +202,40 @@ module nanosoc_target_output_SYSIO (
input [31:0] wdata_op3; // Port 3 HWDATA signal
input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 4
+ input sel_op4; // Port 4 HSEL signal
+ input [31:0] addr_op4; // Port 4 HADDR signal
+ input [1:0] trans_op4; // Port 4 HTRANS signal
+ input write_op4; // Port 4 HWRITE signal
+ input [2:0] size_op4; // Port 4 HSIZE signal
+ input [2:0] burst_op4; // Port 4 HBURST signal
+ input [3:0] prot_op4; // Port 4 HPROT signal
+ input [3:0] master_op4; // Port 4 HMASTER signal
+ input mastlock_op4; // Port 4 HMASTLOCK signal
+ input [31:0] wdata_op4; // Port 4 HWDATA signal
+ input held_tran_op4; // Port 4 HeldTran signal
+
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
+
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
output active_op1; // Port 1 Active signal
output active_op2; // Port 2 Active signal
output active_op3; // Port 3 Active signal
+ output active_op4; // Port 4 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -257,6 +313,34 @@ module nanosoc_target_output_SYSIO (
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
+ // Bus-switch input 4
+ wire sel_op4; // Port 4 HSEL signal
+ wire [31:0] addr_op4; // Port 4 HADDR signal
+ wire [1:0] trans_op4; // Port 4 HTRANS signal
+ wire write_op4; // Port 4 HWRITE signal
+ wire [2:0] size_op4; // Port 4 HSIZE signal
+ wire [2:0] burst_op4; // Port 4 HBURST signal
+ wire [3:0] prot_op4; // Port 4 HPROT signal
+ wire [3:0] master_op4; // Port 4 HMASTER signal
+ wire mastlock_op4; // Port 4 HMASTLOCK signal
+ wire [31:0] wdata_op4; // Port 4 HWDATA signal
+ wire held_tran_op4; // Port 4 HeldTran signal
+ reg active_op4; // Port 4 Active signal
+
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
+
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
@@ -279,9 +363,11 @@ module nanosoc_target_output_SYSIO (
wire req_port1; // Port 1 request signal
wire req_port2; // Port 2 request signal
wire req_port3; // Port 3 request signal
+ wire req_port4; // Port 4 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -309,6 +395,8 @@ module nanosoc_target_output_SYSIO (
assign req_port1 = held_tran_op1 & sel_op1;
assign req_port2 = held_tran_op2 & sel_op2;
assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port4 = held_tran_op4 & sel_op4;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_SYSIO u_output_arb (
@@ -320,6 +408,8 @@ module nanosoc_target_output_SYSIO (
.req_port1 (req_port1),
.req_port2 (req_port2),
.req_port3 (req_port3),
+ .req_port4 (req_port4),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -341,19 +431,25 @@ module nanosoc_target_output_SYSIO (
active_op1 = 1'b0;
active_op2 = 1'b0;
active_op3 = 1'b0;
+ active_op4 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b01 : active_op1 = 1'b1;
- 2'b10 : active_op2 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b001 : active_op1 = 1'b1;
+ 3'b010 : active_op2 = 1'b1;
+ 3'b011 : active_op3 = 1'b1;
+ 3'b100 : active_op4 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
active_op1 = 1'bx;
active_op2 = 1'bx;
active_op3 = 1'bx;
+ active_op4 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -373,6 +469,12 @@ module nanosoc_target_output_SYSIO (
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
master_op3 or mastlock_op3 or
+ sel_op4 or addr_op4 or trans_op4 or write_op4 or
+ size_op4 or burst_op4 or prot_op4 or
+ master_op4 or mastlock_op4 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -391,7 +493,7 @@ module nanosoc_target_output_SYSIO (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -402,10 +504,10 @@ module nanosoc_target_output_SYSIO (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
// Bus-switch input 1
- 2'b01 :
+ 3'b001 :
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
@@ -416,10 +518,10 @@ module nanosoc_target_output_SYSIO (
HPROTM = prot_op1;
HMASTERM = master_op1;
i_hmastlockm= mastlock_op1;
- end // case: 4'b01
+ end // case: 4'b001
// Bus-switch input 2
- 2'b10 :
+ 3'b010 :
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
@@ -430,10 +532,10 @@ module nanosoc_target_output_SYSIO (
HPROTM = prot_op2;
HMASTERM = master_op2;
i_hmastlockm= mastlock_op2;
- end // case: 4'b10
+ end // case: 4'b010
// Bus-switch input 3
- 2'b11 :
+ 3'b011 :
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
@@ -444,7 +546,35 @@ module nanosoc_target_output_SYSIO (
HPROTM = prot_op3;
HMASTERM = master_op3;
i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ end // case: 4'b011
+
+ // Bus-switch input 4
+ 3'b100 :
+ begin
+ i_hselm = sel_op4;
+ HADDRM = addr_op4;
+ i_htransm = trans_op4;
+ HWRITEM = write_op4;
+ HSIZEM = size_op4;
+ i_hburstm = burst_op4;
+ HPROTM = prot_op4;
+ HMASTERM = master_op4;
+ i_hmastlockm= mastlock_op4;
+ end // case: 4'b100
+
+ // Bus-switch input 5
+ 3'b101 :
+ begin
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -494,7 +624,7 @@ module nanosoc_target_output_SYSIO (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -517,6 +647,8 @@ module nanosoc_target_output_SYSIO (
wdata_op1 or
wdata_op2 or
wdata_op3 or
+ wdata_op4 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -527,10 +659,12 @@ module nanosoc_target_output_SYSIO (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b01 : HWDATAM = wdata_op1;
- 2'b10 : HWDATAM = wdata_op2;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b001 : HWDATAM = wdata_op1;
+ 3'b010 : HWDATAM = wdata_op2;
+ 3'b011 : HWDATAM = wdata_op3;
+ 3'b100 : HWDATAM = wdata_op4;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
index f84cb2b2650c823d1e90d3e4d224fbec97983e41..9292fc37e30027731f3e42f85ec5355fc4522365 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2024 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -51,24 +51,24 @@ module nanosoc_target_output_SYSTABLE (
wdata_op0,
held_tran_op0,
- // Port 3 Signals
- sel_op3,
- addr_op3,
- trans_op3,
- write_op3,
- size_op3,
- burst_op3,
- prot_op3,
- master_op3,
- mastlock_op3,
- wdata_op3,
- held_tran_op3,
+ // Port 5 Signals
+ sel_op5,
+ addr_op5,
+ trans_op5,
+ write_op5,
+ size_op5,
+ burst_op5,
+ prot_op5,
+ master_op5,
+ mastlock_op5,
+ wdata_op5,
+ held_tran_op5,
// Slave read data and response
HREADYOUTM,
active_op0,
- active_op3,
+ active_op5,
// Slave Address/Control Signals
HSELM,
@@ -107,23 +107,23 @@ module nanosoc_target_output_SYSTABLE (
input [31:0] wdata_op0; // Port 0 HWDATA signal
input held_tran_op0; // Port 0 HeldTran signal
- // Bus-switch input 3
- input sel_op3; // Port 3 HSEL signal
- input [31:0] addr_op3; // Port 3 HADDR signal
- input [1:0] trans_op3; // Port 3 HTRANS signal
- input write_op3; // Port 3 HWRITE signal
- input [2:0] size_op3; // Port 3 HSIZE signal
- input [2:0] burst_op3; // Port 3 HBURST signal
- input [3:0] prot_op3; // Port 3 HPROT signal
- input [3:0] master_op3; // Port 3 HMASTER signal
- input mastlock_op3; // Port 3 HMASTLOCK signal
- input [31:0] wdata_op3; // Port 3 HWDATA signal
- input held_tran_op3; // Port 3 HeldTran signal
+ // Bus-switch input 5
+ input sel_op5; // Port 5 HSEL signal
+ input [31:0] addr_op5; // Port 5 HADDR signal
+ input [1:0] trans_op5; // Port 5 HTRANS signal
+ input write_op5; // Port 5 HWRITE signal
+ input [2:0] size_op5; // Port 5 HSIZE signal
+ input [2:0] burst_op5; // Port 5 HBURST signal
+ input [3:0] prot_op5; // Port 5 HPROT signal
+ input [3:0] master_op5; // Port 5 HMASTER signal
+ input mastlock_op5; // Port 5 HMASTLOCK signal
+ input [31:0] wdata_op5; // Port 5 HWDATA signal
+ input held_tran_op5; // Port 5 HeldTran signal
input HREADYOUTM; // HREADY feedback
output active_op0; // Port 0 Active signal
- output active_op3; // Port 3 Active signal
+ output active_op5; // Port 5 Active signal
// Slave Address/Control Signals
output HSELM; // Slave select line
@@ -159,19 +159,19 @@ module nanosoc_target_output_SYSTABLE (
wire held_tran_op0; // Port 0 HeldTran signal
reg active_op0; // Port 0 Active signal
- // Bus-switch input 3
- wire sel_op3; // Port 3 HSEL signal
- wire [31:0] addr_op3; // Port 3 HADDR signal
- wire [1:0] trans_op3; // Port 3 HTRANS signal
- wire write_op3; // Port 3 HWRITE signal
- wire [2:0] size_op3; // Port 3 HSIZE signal
- wire [2:0] burst_op3; // Port 3 HBURST signal
- wire [3:0] prot_op3; // Port 3 HPROT signal
- wire [3:0] master_op3; // Port 3 HMASTER signal
- wire mastlock_op3; // Port 3 HMASTLOCK signal
- wire [31:0] wdata_op3; // Port 3 HWDATA signal
- wire held_tran_op3; // Port 3 HeldTran signal
- reg active_op3; // Port 3 Active signal
+ // Bus-switch input 5
+ wire sel_op5; // Port 5 HSEL signal
+ wire [31:0] addr_op5; // Port 5 HADDR signal
+ wire [1:0] trans_op5; // Port 5 HTRANS signal
+ wire write_op5; // Port 5 HWRITE signal
+ wire [2:0] size_op5; // Port 5 HSIZE signal
+ wire [2:0] burst_op5; // Port 5 HBURST signal
+ wire [3:0] prot_op5; // Port 5 HPROT signal
+ wire [3:0] master_op5; // Port 5 HMASTER signal
+ wire mastlock_op5; // Port 5 HMASTLOCK signal
+ wire [31:0] wdata_op5; // Port 5 HWDATA signal
+ wire held_tran_op5; // Port 5 HeldTran signal
+ reg active_op5; // Port 5 Active signal
// Slave Address/Control Signals
wire HSELM; // Slave select line
@@ -192,10 +192,10 @@ module nanosoc_target_output_SYSTABLE (
// Signal declarations
// -----------------------------------------------------------------------------
wire req_port0; // Port 0 request signal
- wire req_port3; // Port 3 request signal
+ wire req_port5; // Port 5 request signal
- wire [1:0] addr_in_port; // Address input port
- reg [1:0] data_in_port; // Data input port
+ wire [2:0] addr_in_port; // Address input port
+ reg [2:0] data_in_port; // Data input port
wire no_port; // No port selected signal
reg slave_sel; // Slave select signal
reg wdata_phase; // Used to prevent unnecesary toggling
@@ -220,7 +220,7 @@ module nanosoc_target_output_SYSTABLE (
// -----------------------------------------------------------------------------
assign req_port0 = held_tran_op0 & sel_op0;
- assign req_port3 = held_tran_op3 & sel_op3;
+ assign req_port5 = held_tran_op5 & sel_op5;
// Arbiter instance for resolving requests to this output stage
nanosoc_arbiter_SYSTABLE u_output_arb (
@@ -229,7 +229,7 @@ module nanosoc_target_output_SYSTABLE (
.HRESETn (HRESETn),
.req_port0 (req_port0),
- .req_port3 (req_port3),
+ .req_port5 (req_port5),
.HREADYM (i_hreadymuxm),
.HSELM (i_hselm),
@@ -248,16 +248,16 @@ module nanosoc_target_output_SYSTABLE (
begin : p_active_comb
// Default value(s)
active_op0 = 1'b0;
- active_op3 = 1'b0;
+ active_op5 = 1'b0;
// Decode selection when enabled
if (~no_port)
case (addr_in_port)
- 2'b00 : active_op0 = 1'b1;
- 2'b11 : active_op3 = 1'b1;
+ 3'b000 : active_op0 = 1'b1;
+ 3'b101 : active_op5 = 1'b1;
default : begin
active_op0 = 1'bx;
- active_op3 = 1'bx;
+ active_op5 = 1'bx;
end
endcase // case(addr_in_port)
end // block: p_active_comb
@@ -268,9 +268,9 @@ module nanosoc_target_output_SYSTABLE (
sel_op0 or addr_op0 or trans_op0 or write_op0 or
size_op0 or burst_op0 or prot_op0 or
master_op0 or mastlock_op0 or
- sel_op3 or addr_op3 or trans_op3 or write_op3 or
- size_op3 or burst_op3 or prot_op3 or
- master_op3 or mastlock_op3 or
+ sel_op5 or addr_op5 or trans_op5 or write_op5 or
+ size_op5 or burst_op5 or prot_op5 or
+ master_op5 or mastlock_op5 or
addr_in_port or no_port
)
begin : p_addr_mux
@@ -289,7 +289,7 @@ module nanosoc_target_output_SYSTABLE (
if (~no_port)
case (addr_in_port)
// Bus-switch input 0
- 2'b00 :
+ 3'b000 :
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
@@ -300,21 +300,21 @@ module nanosoc_target_output_SYSTABLE (
HPROTM = prot_op0;
HMASTERM = master_op0;
i_hmastlockm= mastlock_op0;
- end // case: 4'b00
+ end // case: 4'b000
- // Bus-switch input 3
- 2'b11 :
+ // Bus-switch input 5
+ 3'b101 :
begin
- i_hselm = sel_op3;
- HADDRM = addr_op3;
- i_htransm = trans_op3;
- HWRITEM = write_op3;
- HSIZEM = size_op3;
- i_hburstm = burst_op3;
- HPROTM = prot_op3;
- HMASTERM = master_op3;
- i_hmastlockm= mastlock_op3;
- end // case: 4'b11
+ i_hselm = sel_op5;
+ HADDRM = addr_op5;
+ i_htransm = trans_op5;
+ HWRITEM = write_op5;
+ HSIZEM = size_op5;
+ i_hburstm = burst_op5;
+ HPROTM = prot_op5;
+ HMASTERM = master_op5;
+ i_hmastlockm= mastlock_op5;
+ end // case: 4'b101
default :
begin
@@ -364,7 +364,7 @@ module nanosoc_target_output_SYSTABLE (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_in_port_reg
if (~HRESETn)
- data_in_port <= 2'b11;
+ data_in_port <= 3'b101;
else
if (i_hreadymuxm)
data_in_port <= addr_in_port;
@@ -384,7 +384,7 @@ module nanosoc_target_output_SYSTABLE (
// HWDATAM output decode
always @ (
wdata_op0 or
- wdata_op3 or
+ wdata_op5 or
data_in_port or wdata_phase
)
begin : p_data_mux
@@ -395,8 +395,8 @@ module nanosoc_target_output_SYSTABLE (
if (wdata_phase)
// Decode selection
case (data_in_port)
- 2'b00 : HWDATAM = wdata_op0;
- 2'b11 : HWDATAM = wdata_op3;
+ 3'b000 : HWDATAM = wdata_op0;
+ 3'b101 : HWDATAM = wdata_op5;
default : HWDATAM = {32{1'bx}};
endcase // case(data_in_port)
end // block: p_data_mux
diff --git a/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml b/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml
index eb0be4dd0b6576eb1ebbae716f2e7256a4994573..ec31292b1393c0ffdce0a9b1613973e7d58bcad4 100644
--- a/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml
+++ b/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml
@@ -121,6 +121,44 @@
<address_region interface="_EXP" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
</slave_interface>
+ <slave_interface name="_DMAC_2">
+ <sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_IMEM_0"/>
+ <sparse_connect interface="_DMEM_0"/>
+ <sparse_connect interface="_SYSIO"/>
+ <sparse_connect interface="_EXP"/>
+ <sparse_connect interface="_EXPRAM_L"/>
+ <sparse_connect interface="_EXPRAM_H"/>
+ <address_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_EXP" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_EXPRAM_L" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_EXPRAM_H" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_EXP" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ </slave_interface>
+
+ <slave_interface name="_DMAC_3">
+ <sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_IMEM_0"/>
+ <sparse_connect interface="_DMEM_0"/>
+ <sparse_connect interface="_SYSIO"/>
+ <sparse_connect interface="_EXP"/>
+ <sparse_connect interface="_EXPRAM_L"/>
+ <sparse_connect interface="_EXPRAM_H"/>
+ <address_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_EXP" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_EXPRAM_L" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_EXPRAM_H" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_EXP" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ </slave_interface>
+
<slave_interface name="_CPU_0">
<sparse_connect interface="_BOOTROM_0"/>
<sparse_connect interface="_IMEM_0"/>
diff --git a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
index 877d5dc4f44df47bbcd17781f6981cb08a3e49b6..d234bed56bded5293eb656e2742b89d1b58408b0 100644
--- a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+++ b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -76,6 +76,33 @@ module nanosoc_ss_dma #(
output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data
output wire DMAC_1_PREADY, // APB Ready
output wire DMAC_1_PSLVERR, // APB Slave Error
+
+ // DMAC 2 AHB Lite Port
+ output wire [SYS_ADDR_W-1:0] DMAC_2_HADDR, // Address bus
+ output wire [1:0] DMAC_2_HTRANS, // Transfer type
+ output wire DMAC_2_HWRITE, // Transfer direction
+ output wire [2:0] DMAC_2_HSIZE, // Transfer size
+ output wire [2:0] DMAC_2_HBURST, // Burst type
+ output wire [3:0] DMAC_2_HPROT, // Protection control
+ output wire [SYS_DATA_W-1:0] DMAC_2_HWDATA, // Write data
+ output wire DMAC_2_HMASTLOCK, // Locked Sequence
+ input wire [SYS_DATA_W-1:0] DMAC_2_HRDATA, // Read data bus
+ input wire DMAC_2_HREADY, // HREADY feedback
+ input wire DMAC_2_HRESP, // Transfer response
+
+ // DMAC 3 AHB Lite Port
+ output wire [SYS_ADDR_W-1:0] DMAC_3_HADDR, // Address bus
+ output wire [1:0] DMAC_3_HTRANS, // Transfer type
+ output wire DMAC_3_HWRITE, // Transfer direction
+ output wire [2:0] DMAC_3_HSIZE, // Transfer size
+ output wire [2:0] DMAC_3_HBURST, // Burst type
+ output wire [3:0] DMAC_3_HPROT, // Protection control
+ output wire [SYS_DATA_W-1:0] DMAC_3_HWDATA, // Write data
+ output wire DMAC_3_HMASTLOCK, // Locked Sequence
+ input wire [SYS_DATA_W-1:0] DMAC_3_HRDATA, // Read data bus
+ input wire DMAC_3_HREADY, // HREADY feedback
+ input wire DMAC_3_HRESP, // Transfer response
+
`ifdef DMAC_DMA350
`ifdef DMA350_STREAM_2
@@ -133,6 +160,26 @@ module nanosoc_ss_dma #(
output wire DMAC_1_DMA_ERR // DMA slave response not OK
);
+// tie-offs ready for DMA 2/3
+
+ assign DMAC_2_HADDR = {SYS_ADDR_W{1'b0}}; // Address bus
+ assign DMAC_2_HTRANS = {2{1'b0}}; // Transfer type
+ assign DMAC_2_HWRITE = 1'b0; // Transfer direction
+ assign DMAC_2_HSIZE = {3{1'b0}}; // Transfer size
+ assign DMAC_2_HBURST = {3{1'b0}}; // Burst type
+ assign DMAC_2_HPROT = {4{1'b0}}; // Protection control
+ assign DMAC_2_HWDATA = {SYS_DATA_W{1'b0}}; // Write data
+ assign DMAC_2_HMASTLOCK = 1'b0; // Locked Sequence
+
+ assign DMAC_3_HADDR = {SYS_ADDR_W{1'b0}}; // Address bus
+ assign DMAC_3_HTRANS = {2{1'b0}}; // Transfer type
+ assign DMAC_3_HWRITE = 1'b0; // Transfer direction
+ assign DMAC_3_HSIZE = {3{1'b0}}; // Transfer size
+ assign DMAC_3_HBURST = {3{1'b0}}; // Burst type
+ assign DMAC_3_HPROT = {4{1'b0}}; // Protection control
+ assign DMAC_3_HWDATA = {SYS_DATA_W{1'b0}}; // Write data
+ assign DMAC_3_HMASTLOCK = 1'b0; // Locked Sequence
+
`ifdef DMAC_DMA350
//-------------------------------
//DMA Controller 0 Instantiation
@@ -234,7 +281,6 @@ module nanosoc_ss_dma #(
.DMA_ERR(DMAC_0_DMA_ERR)
);
-
// APB Tie-off signals
assign DMAC_0_PREADY = 1'b1;
@@ -386,4 +432,4 @@ module nanosoc_ss_dma #(
`endif
`endif
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v b/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
index 155dbee0e9911fefc95548ed8d6da8716232f6da..b3cbe0c6542aeb8403c6ec11a4f4dfe6e8f2cf26 100644
--- a/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
+++ b/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
@@ -50,7 +50,6 @@ module nanosoc_ss_interconnect #(
output wire DMAC_0_HREADY, // HREADY feedback
output wire DMAC_0_HRESP, // Transfer response
-
// DMAC Controller 1 Master Port
input wire [31:0] DMAC_1_HADDR, // Address bus
input wire [1:0] DMAC_1_HTRANS, // Transfer type
@@ -64,6 +63,32 @@ module nanosoc_ss_interconnect #(
output wire DMAC_1_HREADY, // HREADY feedback
output wire DMAC_1_HRESP, // Transfer response
+ // DMAC Controller 2 Master Port
+ input wire [31:0] DMAC_2_HADDR, // Address bus
+ input wire [1:0] DMAC_2_HTRANS, // Transfer type
+ input wire DMAC_2_HWRITE, // Transfer direction
+ input wire [2:0] DMAC_2_HSIZE, // Transfer size
+ input wire [2:0] DMAC_2_HBURST, // Burst type
+ input wire [3:0] DMAC_2_HPROT, // Protection control
+ input wire [31:0] DMAC_2_HWDATA, // Write data
+ input wire DMAC_2_HMASTLOCK, // Locked Sequence
+ output wire [31:0] DMAC_2_HRDATA, // Read data bus
+ output wire DMAC_2_HREADY, // HREADY feedback
+ output wire DMAC_2_HRESP, // Transfer response
+
+ // DMAC Controller 3 Master Port
+ input wire [31:0] DMAC_3_HADDR, // Address bus
+ input wire [1:0] DMAC_3_HTRANS, // Transfer type
+ input wire DMAC_3_HWRITE, // Transfer direction
+ input wire [2:0] DMAC_3_HSIZE, // Transfer size
+ input wire [2:0] DMAC_3_HBURST, // Burst type
+ input wire [3:0] DMAC_3_HPROT, // Protection control
+ input wire [31:0] DMAC_3_HWDATA, // Write data
+ input wire DMAC_3_HMASTLOCK, // Locked Sequence
+ output wire [31:0] DMAC_3_HRDATA, // Read data bus
+ output wire DMAC_3_HREADY, // HREADY feedback
+ output wire DMAC_3_HRESP, // Transfer response
+
// CPU 0 Master Port
input wire [31:0] CPU_0_HADDR, // Address bus
input wire [1:0] CPU_0_HTRANS, // Transfer type
@@ -250,7 +275,33 @@ module nanosoc_ss_interconnect #(
.HREADY_DMAC_1 (DMAC_1_HREADY), // HREADY feedback
.HRESP_DMAC_1 (DMAC_1_HRESP), // Transfer response
- // DMA Controller 1 Master Port
+ // DMA Controller 2 Master Port
+ .HADDR_DMAC_2 (DMAC_2_HADDR), // Address bus
+ .HTRANS_DMAC_2 (DMAC_2_HTRANS), // Transfer type
+ .HWRITE_DMAC_2 (DMAC_2_HWRITE), // Transfer direction
+ .HSIZE_DMAC_2 (DMAC_2_HSIZE), // Transfer size
+ .HBURST_DMAC_2 (DMAC_2_HBURST), // Burst type
+ .HPROT_DMAC_2 (DMAC_2_HPROT), // Protection control
+ .HWDATA_DMAC_2 (DMAC_2_HWDATA), // Write data
+ .HMASTLOCK_DMAC_2 (DMAC_2_HMASTLOCK), // Locked Sequence
+ .HRDATA_DMAC_2 (DMAC_2_HRDATA), // Read data bus
+ .HREADY_DMAC_2 (DMAC_2_HREADY), // HREADY feedback
+ .HRESP_DMAC_2 (DMAC_2_HRESP), // Transfer response
+
+ // DMA Controller 3 Master Port
+ .HADDR_DMAC_3 (DMAC_3_HADDR), // Address bus
+ .HTRANS_DMAC_3 (DMAC_3_HTRANS), // Transfer type
+ .HWRITE_DMAC_3 (DMAC_3_HWRITE), // Transfer direction
+ .HSIZE_DMAC_3 (DMAC_3_HSIZE), // Transfer size
+ .HBURST_DMAC_3 (DMAC_3_HBURST), // Burst type
+ .HPROT_DMAC_3 (DMAC_3_HPROT), // Protection control
+ .HWDATA_DMAC_3 (DMAC_3_HWDATA), // Write data
+ .HMASTLOCK_DMAC_3 (DMAC_3_HMASTLOCK), // Locked Sequence
+ .HRDATA_DMAC_3 (DMAC_3_HRDATA), // Read data bus
+ .HREADY_DMAC_3 (DMAC_3_HREADY), // HREADY feedback
+ .HRESP_DMAC_3 (DMAC_3_HRESP), // Transfer response
+
+ // CPU Controller 0 Master Port
.HADDR_CPU_0 (CPU_0_HADDR), // Address bus
.HTRANS_CPU_0 (CPU_0_HTRANS), // Transfer type
.HWRITE_CPU_0 (CPU_0_HWRITE), // Transfer direction
@@ -383,4 +434,4 @@ module nanosoc_ss_interconnect #(
.HMASTLOCK_SYSTABLE (SYSTABLE_HMASTLOCK), // Locked Sequence
.HREADYMUX_SYSTABLE (SYSTABLE_HREADYMUX) // Transfer done
);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index d45e5bf573ed33172e1bb77262b9569e5107202d..4057c4455a32b09e176ff2ef0a19c40785423a2d 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -422,12 +422,38 @@ module nanosoc_system #(
wire [SYS_DATA_W-1:0] DMAC_1_PRDATA; // APB read data
wire DMAC_1_PREADY; // APB Ready Signal
wire DMAC_1_PSLVERR; // APB Error Signal
-
+
// DMAC 1 DMA Request and Status Port - To Expansion Subsystem
wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ; // DMA transfer request
wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_DONE; // DMA transfer done
wire DMAC_1_DMA_ERR; // DMA slave response not OK
+ // DMAC 2 AHB Lite Port - To Interconnect Subsystem
+ wire [SYS_ADDR_W-1:0] DMAC_2_HADDR; // Address bus
+ wire [1:0] DMAC_2_HTRANS; // Transfer type
+ wire DMAC_2_HWRITE; // Transfer direction
+ wire [2:0] DMAC_2_HSIZE; // Transfer size
+ wire [2:0] DMAC_2_HBURST; // Burst type
+ wire [3:0] DMAC_2_HPROT; // Protection control
+ wire [SYS_DATA_W-1:0] DMAC_2_HWDATA; // Write data
+ wire DMAC_2_HMASTLOCK; // Locked Sequence
+ wire [SYS_DATA_W-1:0] DMAC_2_HRDATA; // Read data bus
+ wire DMAC_2_HREADY; // HREADY feedback
+ wire DMAC_2_HRESP; // Transfer response
+
+ // DMAC 3 AHB Lite Port - To Interconnect Subsystem
+ wire [SYS_ADDR_W-1:0] DMAC_3_HADDR; // Address bus
+ wire [1:0] DMAC_3_HTRANS; // Transfer type
+ wire DMAC_3_HWRITE; // Transfer direction
+ wire [2:0] DMAC_3_HSIZE; // Transfer size
+ wire [2:0] DMAC_3_HBURST; // Burst type
+ wire [3:0] DMAC_3_HPROT; // Protection control
+ wire [SYS_DATA_W-1:0] DMAC_3_HWDATA; // Write data
+ wire DMAC_3_HMASTLOCK; // Locked Sequence
+ wire [SYS_DATA_W-1:0] DMAC_3_HRDATA; // Read data bus
+ wire DMAC_3_HREADY; // HREADY feedback
+ wire DMAC_3_HRESP; // Transfer response
+
// DMA Request Wiring
//--------------------------
@@ -562,6 +588,32 @@ module nanosoc_system #(
.DMAC_1_PRDATA(DMAC_1_PRDATA),
.DMAC_1_PREADY(DMAC_1_PREADY),
.DMAC_1_PSLVERR(DMAC_1_PSLVERR),
+
+ // DMAC 2 AHB Lite Port
+ .DMAC_2_HADDR(DMAC_2_HADDR),
+ .DMAC_2_HTRANS(DMAC_2_HTRANS),
+ .DMAC_2_HWRITE(DMAC_2_HWRITE),
+ .DMAC_2_HSIZE(DMAC_2_HSIZE),
+ .DMAC_2_HBURST(DMAC_2_HBURST),
+ .DMAC_2_HPROT(DMAC_2_HPROT),
+ .DMAC_2_HWDATA(DMAC_2_HWDATA),
+ .DMAC_2_HMASTLOCK(DMAC_2_HMASTLOCK),
+ .DMAC_2_HRDATA(DMAC_2_HRDATA),
+ .DMAC_2_HREADY(DMAC_2_HREADY),
+ .DMAC_2_HRESP(DMAC_2_HRESP),
+
+ // DMAC 3 AHB Lite Port
+ .DMAC_3_HADDR(DMAC_3_HADDR),
+ .DMAC_3_HTRANS(DMAC_3_HTRANS),
+ .DMAC_3_HWRITE(DMAC_3_HWRITE),
+ .DMAC_3_HSIZE(DMAC_3_HSIZE),
+ .DMAC_3_HBURST(DMAC_3_HBURST),
+ .DMAC_3_HPROT(DMAC_3_HPROT),
+ .DMAC_3_HWDATA(DMAC_3_HWDATA),
+ .DMAC_3_HMASTLOCK(DMAC_3_HMASTLOCK),
+ .DMAC_3_HRDATA(DMAC_3_HRDATA),
+ .DMAC_3_HREADY(DMAC_3_HREADY),
+ .DMAC_3_HRESP(DMAC_3_HRESP),
`ifdef DMAC_DMA350
`ifdef DMA350_STREAM_2
@@ -1169,6 +1221,32 @@ module nanosoc_system #(
.DMAC_1_HREADY(DMAC_1_HREADY),
.DMAC_1_HRESP(DMAC_1_HRESP),
+ // DMAC Controller 2 Master Port
+ .DMAC_2_HADDR(DMAC_2_HADDR),
+ .DMAC_2_HTRANS(DMAC_2_HTRANS),
+ .DMAC_2_HWRITE(DMAC_2_HWRITE),
+ .DMAC_2_HSIZE(DMAC_2_HSIZE),
+ .DMAC_2_HBURST(DMAC_2_HBURST),
+ .DMAC_2_HPROT(DMAC_2_HPROT),
+ .DMAC_2_HWDATA(DMAC_2_HWDATA),
+ .DMAC_2_HMASTLOCK(DMAC_2_HMASTLOCK),
+ .DMAC_2_HRDATA(DMAC_2_HRDATA),
+ .DMAC_2_HREADY(DMAC_2_HREADY),
+ .DMAC_2_HRESP(DMAC_2_HRESP),
+
+ // DMAC Controller 1 Master Port
+ .DMAC_3_HADDR(DMAC_3_HADDR),
+ .DMAC_3_HTRANS(DMAC_3_HTRANS),
+ .DMAC_3_HWRITE(DMAC_3_HWRITE),
+ .DMAC_3_HSIZE(DMAC_3_HSIZE),
+ .DMAC_3_HBURST(DMAC_3_HBURST),
+ .DMAC_3_HPROT(DMAC_3_HPROT),
+ .DMAC_3_HWDATA(DMAC_3_HWDATA),
+ .DMAC_3_HMASTLOCK(DMAC_3_HMASTLOCK),
+ .DMAC_3_HRDATA(DMAC_3_HRDATA),
+ .DMAC_3_HREADY(DMAC_3_HREADY),
+ .DMAC_3_HRESP(DMAC_3_HRESP),
+
// CPU 0 Master Port
.CPU_0_HADDR(CPU_0_HADDR),
.CPU_0_HTRANS(CPU_0_HTRANS),
@@ -1303,4 +1381,4 @@ module nanosoc_system #(
.SYSTABLE_HREADYMUX(SYSTABLE_HREADY)
);
-endmodule
\ No newline at end of file
+endmodule