From 0a94d2df0006d74e219b96fe130181f022cc95d3 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 4 Jul 2023 12:06:46 +0100
Subject: [PATCH] Moved build_design script into soctools
---
fpga/build_design.tcl | 98 -------------------
fpga/makefile | 5 +-
.../vivado_script/2021_1/nanosoc_design.tcl | 32 +++---
nanosoc/socdebug_tech | 2 +-
4 files changed, 19 insertions(+), 118 deletions(-)
delete mode 100644 fpga/build_design.tcl
diff --git a/fpga/build_design.tcl b/fpga/build_design.tcl
deleted file mode 100644
index c33f78b..0000000
--- a/fpga/build_design.tcl
+++ /dev/null
@@ -1,98 +0,0 @@
-###-----------------------------------------------------------------------------
-### Build Design Viviado FPGA Script
-### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-###
-### Contributors
-###
-### David Mapstone (d.a.mapstone@soton.ac.uk)
-###
-### Copyright 2023, SoC Labs (www.soclabs.org)
-###-----------------------------------------------------------------------------
-#
-# Developed & Tested using vivado_version 2021.1
-#
-
-# Get Environmnet Variables from Makefile
-set fpga_name $env(FPGA_NAME)
-set xilinx_part $env(FPGA_PART)
-set project_dir $env(FPGA_PROJECT_DIR)
-set import_dir $env(FPGA_TARGET)
-set target_tcl_dir $env(FPGA_TARGET_TCL)
-set design_name $env(FPGA_DESIGN_NAME)
-
-set socket_lib $env(FPGA_SOCKET_LIB)
-set nanosoc_lib $env(FPGA_NANOSOC_LIB)
-set output_dir $env(FPGA_OUTPUT_DIR)
-
-set wrapper_name $env(FPGA_WRAPPER_NAME)
-set pinmap_file $env(FPGA_PINMAP)
-
-#
-# STEP#1: setup design sources and constraints
-#
-set_part $xilinx_part
-set_property TARGET_LANGUAGE Verilog [current_project]
-set_property DEFAULT_LIB work [current_project]
-
-# TODO: Generalise this stage
-set paths [list \
- $socket_lib\
- $nanosoc_lib\
- ]
-
-# Set IP repository paths
-set obj [get_filesets sources_1]
-if { $obj != {} } {
- set_property "ip_repo_paths" "[file normalize $socket_lib] [file normalize $nanosoc_lib]" $obj
- # Rebuild user ip_repo's index before adding any source files
- update_ip_catalog -rebuild
-}
-
-report_ip_status
-
-# #
-# # STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
-# #
-# # using script written out from GUI capture
-
-create_bd_design $design_name
-
-read_verilog $import_dir/$wrapper_name.v
-source $target_tcl_dir/$design_name.tcl
-create_root_design ""
-
-
-add_files $pinmap_file
-
-set_property top $wrapper_name [current_fileset]
-
-# #
-# # STEP#3: save in Project mode to complete flow
-# #
-save_project_as $fpga_name $project_dir -exclude_run_results -force
-
-update_compile_order -fileset sources_1
-
-# #
-# # STEP#4: synthesize project
-# #
-set_property part $xilinx_part [get_runs synth_1]
-launch_runs synth_1 -jobs 8
-
-wait_on_run synth_1
-
-# #
-# # STEP#5: place and route project
-# #
-set_property part $xilinx_part [get_runs impl_1]
-launch_runs impl_1 -to_step write_bitstream -jobs 8
-
-wait_on_run impl_1
-
-# #
-# # STEP#6: export $design_name.bit and $design_name.hwh files for PYNQ
-# #
-
-write_hw_platform -fixed -include_bit -force -file $project_dir/$design_name.xsa
-
-exit 0
diff --git a/fpga/makefile b/fpga/makefile
index cdef33b..0ee3a77 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -113,16 +113,15 @@ build_nanosoc_design: export FPGA_TARGET = $(TARGET_DIR)
build_nanosoc_design: export FPGA_TARGET_TCL = $(TARGET_TCL_DIR)
build_nanosoc_design: export FPGA_DESIGN_NAME = $(DESIGN_NAME)
build_nanosoc_design: export FPGA_WRAPPER_NAME = $(DESIGN_NAME)_wrapper
-build_nanosoc_design: export FPGA_NANOSOC_LIB = $(IMP_NANOSOC_DIR)
-build_nanosoc_design: export FPGA_SOCKET_LIB = $(IMP_SOCKET_DIR)
build_nanosoc_design: export FPGA_OUTPUT_DIR = $(OUTPUT_DIR)
build_nanosoc_design: export FPGA_PINMAP = $(PINMAP_FILE)
+build_nanosoc_design: export FPGA_IMP_DIR = $(IMPLEMENTATION_DIR)
# Synthesise and Implement an FPGA Bitfile
build_nanosoc_design:
@echo Building NanoSoC Design
@mkdir -p $(RUN_DIR)
- @cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_design.tcl
+ @cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/build_design.tcl
@cp $(RUN_DIR)/vivado.log $(TARGET_DIR)
@echo Built NanoSoC Design
diff --git a/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
index 00240ee..36fca6c 100644
--- a/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
@@ -408,8 +408,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.NUM_SI {1} \
] $smartconnect_0
- # Create instance: uart_to_AXI_master_0, and set properties
- set uart_to_AXI_master_0 [ create_bd_cell -type ip -vlnv user.org:user:uart_to_AXI_master:1.0 uart_to_AXI_master_0 ]
+ # Create instance: uart_axi_master_0, and set properties
+ set uart_axi_master_0 [ create_bd_cell -type ip -vlnv ultraembedded:user:uart_axi_master:1.0 uart_axi_master_0 ]
set_property -dict [ list \
CONFIG.CLK_SPEED {50000000} \
CONFIG.C_M00_AXI_ARUSER_WIDTH {4} \
@@ -418,7 +418,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.C_M00_AXI_ID_WIDTH {4} \
CONFIG.C_M00_AXI_RUSER_WIDTH {4} \
CONFIG.C_M00_AXI_WUSER_WIDTH {4} \
- ] $uart_to_AXI_master_0
+ ] $uart_axi_master_0
# Create instance: xlconstant_0, and set properties
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
@@ -453,12 +453,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
- connect_bd_intf_net -intf_net uart_to_AXI_master_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins uart_to_AXI_master_0/M00_AXI]
+ connect_bd_intf_net -intf_net uart_axi_master_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins uart_axi_master_0/M00_AXI]
# Create port connections
connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
- connect_bd_net -net UART_RX_1 [get_bd_pins UART_RX] [get_bd_pins uart_to_AXI_master_0/UART_RX]
+ connect_bd_net -net UART_RX_1 [get_bd_pins UART_RX] [get_bd_pins uart_axi_master_0/UART_RX]
connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
@@ -492,12 +492,12 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ext_reset_in] [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins uart_to_AXI_master_0/m00_axi_aresetn]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ext_reset_in] [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins uart_axi_master_0/m00_axi_aresetn]
connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
- connect_bd_net -net uart_to_AXI_master_0_UART_TX [get_bd_pins UART_TX] [get_bd_pins uart_to_AXI_master_0/UART_TX]
+ connect_bd_net -net uart_axi_master_0_UART_TX [get_bd_pins UART_TX] [get_bd_pins uart_axi_master_0/UART_TX]
connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins uart_to_AXI_master_0/m00_axi_aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins uart_axi_master_0/m00_axi_aclk]
# Restore current instance
current_bd_instance $oldCurInst
@@ -578,14 +578,14 @@ proc create_root_design { parentCell } {
# Create address segments
assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
- assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
- assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_axi_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
# Restore current instance
diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech
index dd99431..2714083 160000
--- a/nanosoc/socdebug_tech
+++ b/nanosoc/socdebug_tech
@@ -1 +1 @@
-Subproject commit dd9943174e8cb8953e9b0972f35a72c1e54a9609
+Subproject commit 271408340856541f00d3e0b68151711299b0a09c
--
GitLab