diff --git a/flist/nanosoc_FPGA.flist b/flist/nanosoc_FPGA.flist
new file mode 100644
index 0000000000000000000000000000000000000000..3d54da0e5c88a029483dfd14bf64b5439ed4476a
--- /dev/null
+++ b/flist/nanosoc_FPGA.flist
@@ -0,0 +1,39 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Top-level Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC IP search path    =============
+
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
+
+// Include NanoSoC IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
+
+// Include Corstone IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_ip.flist
+
+// SLCore Files
+-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0.flist
+
+// Debug IP
+-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
+
+// DMAC IP (better included at top level configuration)
+//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+//-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
diff --git a/flows/makefile.fpga b/flows/makefile.fpga
index 14b851d6152cc750517986095dfa819643ab1d69..9805f98e236a7462dd4040bb252f9699eaf9262a 100644
--- a/flows/makefile.fpga
+++ b/flows/makefile.fpga
@@ -68,7 +68,7 @@ code:
 flist_tcl_nanosoc: gen_defs
 	@mkdir -p $(TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC_FPGA) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
 
 # Package NanoSoC Socket Components
 package_socket:
diff --git a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
index 02d87350b4c2fde7ffa1ed710f4f792c77463d5c..843182e2ea223b5a56112364c92c4ba3febfd7be 100644
--- a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
@@ -20,15 +20,15 @@ set script_folder [_tcl::get_script_folder]
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2021.1
-set current_vivado_version [version -short]
-
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-   puts ""
-   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-
-   return 1
-}
+# set scripts_vivado_version 2021.1
+# set current_vivado_version [version -short]
+# 
+# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+#    puts ""
+#    catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+# 
+#    return 1
+# }
 
 ################################################################
 # START
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
index c60c93afbcb62542005af3edc76642c2d81bc675..ff003e351d9178114809a19d9d5364def0e984c0 100644
--- a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
@@ -20,15 +20,15 @@ set script_folder [_tcl::get_script_folder]
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2021.1
-set current_vivado_version [version -short]
+# set scripts_vivado_version 2021.1
+# set current_vivado_version [version -short]
 
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-   puts ""
-   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+#    puts ""
+#    catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
 
-   return 1
-}
+#    return 1
+# }
 
 ################################################################
 # START
@@ -46,7 +46,7 @@ if { $bCheckIPs == 1 } {
    set list_check_ips "\ 
 soclabs.org:user:nanosoc_chip:1.0\
 xilinx.com:ip:xlconstant:1.1\
-xilinx.com:ip:zynq_ultra_ps_e:3.3\
+xilinx.com:ip:zynq_ultra_ps_e:3.5\
 xilinx.com:ip:axi_gpio:2.0\
 soclabs.org:user:axi_stream_io:1.0\
 xilinx.com:ip:axis_data_fifo:2.0\
@@ -373,7 +373,7 @@ proc create_root_design { parentCell } {
  ] $xlconstant_zerox4
 
   # Create instance: zynq_ultra_ps_e_0, and set properties
-  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
   set_property -dict [ list \
    CONFIG.CAN0_BOARD_INTERFACE {custom} \
    CONFIG.CAN1_BOARD_INTERFACE {custom} \
diff --git a/makefile b/makefile
index 5d35c1248258fac15017f8d2e0fc2b134c989902..efac2e8618cee082f899ddcff94080dc139e734e 100644
--- a/makefile
+++ b/makefile
@@ -185,6 +185,7 @@ else
 	endif
 endif
 
+DESIGN_VC_FPGA ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_FPGA.flist
 # Make variables visible to target shells
 export ARM_CORTEX_M0_DIR
 export ARM_CORSTONE_101_DIR