From 024583a1d26299ec725d4045bfe19c24e2279e7b Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 4 Jul 2023 09:51:47 +0100
Subject: [PATCH] Further reworking of FPGA flow
---
fpga/build_nanosoc.tcl | 54 -------------
...uild_fpga.tcl => build_nanosoc_design.tcl} | 11 +--
fpga/makefile | 79 +++++++++++--------
fpga/nanosoc_defines.tcl | 13 +++
nanosoc/socdebug_tech | 2 +-
5 files changed, 64 insertions(+), 95 deletions(-)
delete mode 100644 fpga/build_nanosoc.tcl
rename fpga/{build_fpga.tcl => build_nanosoc_design.tcl} (92%)
create mode 100644 fpga/nanosoc_defines.tcl
diff --git a/fpga/build_nanosoc.tcl b/fpga/build_nanosoc.tcl
deleted file mode 100644
index e38f6b4..0000000
--- a/fpga/build_nanosoc.tcl
+++ /dev/null
@@ -1,54 +0,0 @@
-###-----------------------------------------------------------------------------
-### Build NanoSoC FPGA TCL File
-### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-###
-### Contributors
-###
-### David Flynn (d.w.flynn@soton.ac.uk)
-###
-### Copyright � 2022, SoC Labs (www.soclabs.org)
-###-----------------------------------------------------------------------------
-#
-# developed & tested using vivado_version 2021.1
-#
-
-
-#
-# STEP#0: setup design sources and constraints
-#
-source $env(FPGA_TCL_FILELIST)
-
-
-set_property generic {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
-set_property verilog_define {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
-set_property top $env(FPGA_DESIGN_TOP) [current_fileset]
-
-#
-# STEP#1: run synthesis, report utilization and timing estimates, write checkpoint design
-#
-
-update_compile_order -fileset sources_1
-
-ipx::package_project -root_dir $nanosoc_lib -vendor $env(FPGA_VENDOR) -library user -taxonomy /UserIP -import_files -set_current false -force -force_update_compile_order
-
-ipx::unload_core $nanosoc_lib/component.xml
-ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $nanosoc_lib $nanosoc_lib/component.xml
-
-update_compile_order -fileset sources_1
-set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
-ipx::merge_project_changes files [ipx::current_core]
-
-set_property core_revision $env(FPGA_CORE_REV) [ipx::current_core]
-ipx::update_source_project_archive -component [ipx::current_core]
-ipx::create_xgui_files [ipx::current_core]
-ipx::update_checksums [ipx::current_core]
-ipx::check_integrity [ipx::current_core]
-
-ipx::save_core [ipx::current_core]
-ipx::check_integrity -quiet -xrt [ipx::current_core]
-ipx::move_temp_component_back -component [ipx::current_core]
-close_project
-
-set_property ip_repo_paths " $socket_lib $nanosoc_lib" [current_project]
-update_ip_catalog
-close_project
diff --git a/fpga/build_fpga.tcl b/fpga/build_nanosoc_design.tcl
similarity index 92%
rename from fpga/build_fpga.tcl
rename to fpga/build_nanosoc_design.tcl
index 17adbd3..94d2a62 100644
--- a/fpga/build_fpga.tcl
+++ b/fpga/build_nanosoc_design.tcl
@@ -15,21 +15,15 @@
# Get Environmnet Variables from Makefile
set fpga_name $env(FPGA_NAME)
set xilinx_part $env(FPGA_PART)
-set import_dir $env(FPGA_TARGET)
set project_dir $env(FPGA_PROJECT_DIR)
-set flow_dir $env(FPGA_FLOW_DIR)
-set design_name $env(FPGA_DESIGN_NAME)
+set import_dir $env(FPGA_TARGET)
set target_tcl_dir $env(FPGA_TARGET_TCL)
+set design_name $env(FPGA_DESIGN_NAME)
set socket_lib $env(FPGA_SOCKET_LIB)
set nanosoc_lib $env(FPGA_NANOSOC_LIB)
set output_dir $env(FPGA_OUTPUT_DIR)
-#
-# STEP#0: Build NanoSoC Design (without pads) as an "IP" library component for the testbench (in nanosoc_lib)
-#
-source $flow_dir/build_nanosoc.tcl
-
#
# STEP#1: setup design sources and constraints
#
@@ -102,5 +96,4 @@ exec mkdir -p $output_dir
exec cp -p $project_dir/export/$design_name.bit $output_dir
exec cp -p $project_dir/export/$design_name.hwh $output_dir
-exec rm -r $nanosoc_lib
exit 0
diff --git a/fpga/makefile b/fpga/makefile
index 7bff7df..be5892e 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -35,23 +35,26 @@ DESIGN_NAME ?= nanosoc_design
# Location to build FPGA files
IMPLEMENTATION_DIR ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
RUN_DIR := $(IMPLEMENTATION_DIR)/run
-TEMP_RTL_NANOSOC_DIR := $(IMPLEMENTATION_DIR)/nanosoc_lib
-TEMP_RTL_SOCKET_DIR := $(IMPLEMENTATION_DIR)/socket
+IMP_NANOSOC_DIR := $(IMPLEMENTATION_DIR)/nanosoc
+IMP_SOCKET_DIR := $(IMPLEMENTATION_DIR)/socket
PROJECT_DIR := $(IMPLEMENTATION_DIR)/targets/$(BOARD_NAME)
# Name of generated filelist by python script
-TCL_FLIST_DIR := $(TEMP_RTL_NANOSOC_DIR)/flist
+TCL_FLIST_DIR := $(IMP_NANOSOC_DIR)/flist
TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
# NanoSoC Tech Flow Dependencies
NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
+# NanoSoC Defines File
+NANOSOC_DEFINES ?= $(NANOSOC_FPGA_FLOW_DIR)/nanosoc_defines.tcl
+
# Directory to look for FPGA specific implementation files
TARGET_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
TARGET_TCL_DIR := $(TARGET_DIR)/vivado_script/$(VIVIADO_VERSION)
# NanoSoC Tech Socket Design Dependencies
-RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_lib
+RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
# Define Bitfile Output Directory depending on Platform
ifeq ($(PLATFORM), bare)
@@ -69,46 +72,60 @@ else
ACCELERATOR_SUBSYSTEM = 0
endif
-# Export Environment Variables so FPGA TCL scripts can access values
-build_fpga: export FPGA_NAME = $(BOARD_NAME)
-build_fpga: export FPGA_PART = $(XILINX_PART)
-build_fpga: export FPGA_PROJECT_DIR = $(PROJECT_DIR)
-build_fpga: export FPGA_TARGET = $(TARGET_DIR)
-build_fpga: export FPGA_TARGET_TCL = $(TARGET_TCL_DIR)
-build_fpga: export FPGA_TCL_FILELIST = $(TCL_OUTPUT_FILELIST)
-build_fpga: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM)
-build_fpga: export FPGA_DESIGN_TOP = $(FPGA_TOP)
-build_fpga: export FPGA_VENDOR = $(VENDOR)
-build_fpga: export FPGA_CORE_REV = $(NANOSOC_CORE_REV)
-build_fpga: export FPGA_NANOSOC_LIB = $(TEMP_RTL_NANOSOC_DIR)
-build_fpga: export FPGA_SOCKET_LIB = $(RTL_SOCKET_DIR)
-build_fpga: export FPGA_IMPLEMENTATION_DIR = $(IMPLEMENTATION_DIR)
-build_fpga: export FPGA_FLOW_DIR = $(NANOSOC_FPGA_FLOW_DIR)
-build_fpga: export FPGA_DESIGN_NAME = $(DESIGN_NAME)
-build_fpga: export FPGA_OUTPUT_DIR = $(OUTPUT_DIR)
-
# Generate TCL filelist from flists
-tcl_flist:
+nanosoc_flist:
@mkdir -p $(TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(TEMP_RTL_NANOSOC_DIR);)
-
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR);)
+
+# Package NanoSoC Socket Components
package_socket:
- $(MAKE) -C $(SOCLABS_SOCDEBUG_TECH_DIR)/fpga package_socket TEMP_RTL_SOCKET_DIR=$(TEMP_RTL_SOCKET_DIR) RTL_SOCKET_DIR=$(RTL_SOCKET_DIR)
+ $(MAKE) -C $(SOCLABS_SOCDEBUG_TECH_DIR)/fpga package_socket IMP_SOCKET_DIR=$(IMP_SOCKET_DIR) RTL_SOCKET_DIR=$(RTL_SOCKET_DIR)
+
+# Environment Variables for Packaging NanoSoC
+package_nanosoc: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
+package_nanosoc: export FPGA_COMPONENT_DEFINES = $(NANOSOC_DEFINES)
+package_nanosoc: export FPGA_COMPONENT_LIB = $(IMP_NANOSOC_DIR)
+package_nanosoc: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM)
+package_nanosoc: export FPGA_DESIGN_TOP = $(FPGA_TOP)
+package_nanosoc: export FPGA_VENDOR = $(VENDOR)
+package_nanosoc: export FPGA_CORE_REV = $(NANOSOC_CORE_REV)
+
+# Package NanoSoC IP
+package_nanosoc: nanosoc_flist
+ @echo Packaging NanoSoC
+ @mkdir -p $(RUN_DIR)
+ @cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
+ @mkdir -p $(IMP_NANOSOC_DIR)/logs
+ @cp $(RUN_DIR)/vivado.log $(IMP_NANOSOC_DIR)/logs
+ @echo NanoSoC Packaged
+
+# Environment Variables for Build NanoSoC Design
+build_nanosoc_design: export FPGA_NAME = $(BOARD_NAME)
+build_nanosoc_design: export FPGA_PART = $(XILINX_PART)
+build_nanosoc_design: export FPGA_PROJECT_DIR = $(PROJECT_DIR)
+build_nanosoc_design: export FPGA_TARGET = $(TARGET_DIR)
+build_nanosoc_design: export FPGA_TARGET_TCL = $(TARGET_TCL_DIR)
+build_nanosoc_design: export FPGA_DESIGN_NAME = $(DESIGN_NAME)
+build_nanosoc_design: export FPGA_NANOSOC_LIB = $(IMP_NANOSOC_DIR)
+build_nanosoc_design: export FPGA_SOCKET_LIB = $(IMP_SOCKET_DIR)
+build_nanosoc_design: export FPGA_OUTPUT_DIR = $(OUTPUT_DIR)
# Synthesise and Implement an FPGA Bitfile
-build_fpga: tcl_flist clean_fpga
- @echo Starting Vivado Run
+build_nanosoc_design:
+ @echo Building NanoSoC Design
@mkdir -p $(RUN_DIR)
- @cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_fpga.tcl
+ @cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_nanosoc_design.tcl
@cp $(RUN_DIR)/vivado.log $(TARGET_DIR)
- @echo Vivado Build Complete
+ @echo Built NanoSoC Design
+
+# Build NanoSoC Design Flow
+build_fpga: clean_fpga package_socket package_nanosoc build_nanosoc_design
# Clean FPGA Run
clean_fpga:
@echo Cleaning Previous Runs of $(BOARD_NAME)
@rm -rf $(PROJECT_DIR)
- @rm -rf $(TEMP_RTL_NANOSOC_DIR)
@rm -rf $(RUN_DIR)
# Clean ALL FPGA Implementation Directory
diff --git a/fpga/nanosoc_defines.tcl b/fpga/nanosoc_defines.tcl
new file mode 100644
index 0000000..63769af
--- /dev/null
+++ b/fpga/nanosoc_defines.tcl
@@ -0,0 +1,13 @@
+###-----------------------------------------------------------------------------
+### NanoSoC Defines Script
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Mapstone (d.a.mapstone@soton.ac.uk)
+###
+### Copyright 2023, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+
+set_property generic {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
+set_property verilog_define {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
\ No newline at end of file
diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech
index abe4e2c..6afabad 160000
--- a/nanosoc/socdebug_tech
+++ b/nanosoc/socdebug_tech
@@ -1 +1 @@
-Subproject commit abe4e2cbb68fde22cac578f15943b1e7e61a51d7
+Subproject commit 6afabad6b246d01a7feb1c4348982eeb9479f5e1
--
GitLab