From 010b49d623ffd7f657dd5c4bc8e50771b7ff98d4 Mon Sep 17 00:00:00 2001 From: dwf1m12 <d.w.flynn@soton.ac.uk> Date: Thu, 28 Sep 2023 14:09:34 +0100 Subject: [PATCH] clean up include paths in file-lists --- flist/corstone101_ip.flist | 6 +++--- flist/corstone101_vip.flist | 12 ++++++------ flist/corstone101_vip_qs.flist | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/flist/corstone101_ip.flist b/flist/corstone101_ip.flist index 8ba90b2..f73c70d 100644 --- a/flist/corstone101_ip.flist +++ b/flist/corstone101_ip.flist @@ -18,7 +18,7 @@ // ============= Corstone-101 search path ============= +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ ++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories // CMSDK APB Timer IP //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog @@ -74,7 +74,7 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v // CMSDK Memory Models -//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ +//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v @@ -87,4 +87,4 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_sram256 // CMSDK AHB to SRAM bridge IP //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v \ No newline at end of file +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v diff --git a/flist/corstone101_vip.flist b/flist/corstone101_vip.flist index b97dab2..ed83292 100644 --- a/flist/corstone101_vip.flist +++ b/flist/corstone101_vip.flist @@ -21,15 +21,15 @@ +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog // CMSDK Debug Tester VIP -//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_ahb_interconnect.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_trace_capture.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v +-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_ahb_interconnect.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_trace_capture.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v // CMSDK AHB Lite Protocol Checker VIP //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v // CMSDK APB Protocol Checker VIP //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog -// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v \ No newline at end of file +// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v diff --git a/flist/corstone101_vip_qs.flist b/flist/corstone101_vip_qs.flist index 880db86..a89597c 100644 --- a/flist/corstone101_vip_qs.flist +++ b/flist/corstone101_vip_qs.flist @@ -28,8 +28,8 @@ $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_debug_test // CMSDK AHB Lite Protocol Checker VIP //-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/AhbLitePC/verilog -$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v // CMSDK APB Protocol Checker VIP //-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/ApbPC/verilog -// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v \ No newline at end of file +// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v -- GitLab