//-----------------------------------------------------------------------------
// customised top-level Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//
module nanosoc_chip_pads
(
`ifdef POWER_PINS
inout wire VDDIO,
inout wire VSSIO,
inout wire VDD,
inout wire VSS,
`endif
inout wire XTAL1, // input
inout wire XTAL2, // output
inout wire NRST, // active low reset
inout wire [15:0] P0,
inout wire [15:0] P1,
inout wire SWDIOTMS,
inout wire SWCLKTCK);
//------------------------------------
// internal wires
wire xtal_clk_i;
wire xtal_clk_o;
wire nrst_i;
wire [15:0] p0_i; // level-shifted input from pad
wire [15:0] p0_o; // output port drive
wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
wire [15:0] p1_i; // level-shifted input from pad
wire [15:0] p1_o; // output port drive
wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
wire swdio_i;
wire swdio_o;
wire swdio_e;
wire swdio_z;
wire swdclk_i;
// --------------------------------------------------------------------------------
// Cortex-M0 nanosoc Microcontroller
// --------------------------------------------------------------------------------
nanosoc_chip
u_nanosoc_chip (
`ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
`endif
.xtal_clk_i(xtal_clk_i),
.xtal_clk_o(xtal_clk_o),
.nrst_i(nrst_i),
.p0_i(p0_i), // level-shifted input from pad
.p0_o(p0_o), // output port drive
.p0_e(p0_e), // active high output drive enable (pad tech dependent)
.p0_z(p0_z), // active low output drive enable (pad tech dependent)
.p1_i(p1_i), // level-shifted input from pad
.p1_o(p1_o), // output port drive
.p1_e(p1_e), // active high output drive enable (pad tech dependent)
.p1_z(p1_z), // active low output drive enable (pad tech dependent)
.swdio_i(swdio_i),
.swdio_o(swdio_o),
.swdio_e(swdio_e),
.swdio_z(swdio_z),
.swdclk_i(swdclk_i)
);
//TIE_HI uTIEHI (.tiehi(tiehi));
wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
// --------------------------------------------------------------------------------
// IO pad (GLIB Generic Library napping)
// --------------------------------------------------------------------------------
`ifdef POWER_PINS
// Pad IO power supplies
PAD_VDDIO uPAD_VDDIO_1(
.PAD(VDDIO)
);
PAD_VSSIO uPAD_VSSIO_1(
.PAD(VSSIO)
);
// Core power supplies
PAD_VDDSOC uPAD_VDD_1(
.PAD(VDD)
);
PAD_VSS uPAD_VSS_1(
.PAD(VSS)
);
`endif
// Clock, Reset and Serial Wire Debug ports
PAD_INOUT8MA_NOE uPAD_XTAL_I (
.PAD (XTAL1),
.O (tielo),
.I (xtal_clk_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_XTAL_O (
.PAD (XTAL2),
.O (xtal_clk_o),
.I ( ),
.NOE (tielo)
);
PAD_INOUT8MA_NOE uPAD_NRST_I (
.PAD (NRST),
.O (tielo),
.I (nrst_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_SWDIO_I (
.PAD (SWDIOTMS),
.O (swdio_o),
.I (swdio_i),
.NOE (swdio_z)
);
PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
.PAD (SWCLKTCK),
.O (tielo),
.I (swdclk_i),
.NOE (tiehi)
);
// GPI.I Port 0 x 16
PAD_INOUT8MA_NOE uPAD_P0_00 (
.PAD (P0[00]),
.O (p0_o[00]),
.I (p0_i[00]),
.NOE (p0_z[00])
);
PAD_INOUT8MA_NOE uPAD_P0_01 (
.PAD (P0[01]),
.O (p0_o[01]),
.I (p0_i[01]),
.NOE (p0_z[01])
);
PAD_INOUT8MA_NOE uPAD_P0_02 (
.PAD (P0[02]),
.O (p0_o[02]),
.I (p0_i[02]),
.NOE (p0_z[02])
);
PAD_INOUT8MA_NOE uPAD_P0_03 (
.PAD (P0[03]),
.O (p0_o[03]),
.I (p0_i[03]),
.NOE (p0_z[03])
);
PAD_INOUT8MA_NOE uPAD_P0_04 (
.PAD (P0[04]),
.O (p0_o[04]),
.I (p0_i[04]),
.NOE (p0_z[04])
);
PAD_INOUT8MA_NOE uPAD_P0_05 (
.PAD (P0[05]),
.O (p0_o[05]),
.I (p0_i[05]),
.NOE (p0_z[05])
);
PAD_INOUT8MA_NOE uPAD_P0_06 (
.PAD (P0[06]),
.O (p0_o[06]),
.I (p0_i[06]),
.NOE (p0_z[06])
);
PAD_INOUT8MA_NOE uPAD_P0_07 (
.PAD (P0[07]),
.O (p0_o[07]),
.I (p0_i[07]),
.NOE (p0_z[07])
);
PAD_INOUT8MA_NOE uPAD_P0_08 (
.PAD (P0[08]),
.O (p0_o[08]),
.I (p0_i[08]),
.NOE (p0_z[08])
);
PAD_INOUT8MA_NOE uPAD_P0_09 (
.PAD (P0[09]),
.O (p0_o[09]),
.I (p0_i[09]),
.NOE (p0_z[09])
);
PAD_INOUT8MA_NOE uPAD_P0_10 (
.PAD (P0[10]),
.O (p0_o[10]),
.I (p0_i[10]),
.NOE (p0_z[10])
);
PAD_INOUT8MA_NOE uPAD_P0_11 (
.PAD (P0[11]),
.O (p0_o[11]),
.I (p0_i[11]),
.NOE (p0_z[11])
);
PAD_INOUT8MA_NOE uPAD_P0_12 (
.PAD (P0[12]),
.O (p0_o[12]),
.I (p0_i[12]),
.NOE (p0_z[12])
);
PAD_INOUT8MA_NOE uPAD_P0_13 (
.PAD (P0[13]),
.O (p0_o[13]),
.I (p0_i[13]),
.NOE (p0_z[13])
);
PAD_INOUT8MA_NOE uPAD_P0_14 (
.PAD (P0[14]),
.O (p0_o[14]),
.I (p0_i[14]),
.NOE (p0_z[14])
);
PAD_INOUT8MA_NOE uPAD_P0_15 (
.PAD (P0[15]),
.O (p0_o[15]),
.I (p0_i[15]),
.NOE (p0_z[15])
);
// GPI.I Port 1 x 16
PAD_INOUT8MA_NOE uPAD_P1_00 (
.PAD (P1[00]),
.O (p1_o[00]),
.I (p1_i[00]),
.NOE (p1_z[00])
);
PAD_INOUT8MA_NOE uPAD_P1_01 (
.PAD (P1[01]),
.O (p1_o[01]),
.I (p1_i[01]),
.NOE (p1_z[01])
);
PAD_INOUT8MA_NOE uPAD_P1_02 (
.PAD (P1[02]),
.O (p1_o[02]),
.I (p1_i[02]),
.NOE (p1_z[02])
);
PAD_INOUT8MA_NOE uPAD_P1_03 (
.PAD (P1[03]),
.O (p1_o[03]),
.I (p1_i[03]),
.NOE (p1_z[03])
);
PAD_INOUT8MA_NOE uPAD_P1_04 (
.PAD (P1[04]),
.O (p1_o[04]),
.I (p1_i[04]),
.NOE (p1_z[04])
);
PAD_INOUT8MA_NOE uPAD_P1_05 (
.PAD (P1[05]),
.O (p1_o[05]),
.I (p1_i[05]),
.NOE (p1_z[05])
);
PAD_INOUT8MA_NOE uPAD_P1_06 (
.PAD (P1[06]),
.O (p1_o[06]),
.I (p1_i[06]),
.NOE (p1_z[06])
);
PAD_INOUT8MA_NOE uPAD_P1_07 (
.PAD (P1[07]),
.O (p1_o[07]),
.I (p1_i[07]),
.NOE (p1_z[07])
);
PAD_INOUT8MA_NOE uPAD_P1_08 (
.PAD (P1[08]),
.O (p1_o[08]),
.I (p1_i[08]),
.NOE (p1_z[08])
);
PAD_INOUT8MA_NOE uPAD_P1_09 (
.PAD (P1[09]),
.O (p1_o[09]),
.I (p1_i[09]),
.NOE (p1_z[09])
);
PAD_INOUT8MA_NOE uPAD_P1_10 (
.PAD (P1[10]),
.O (p1_o[10]),
.I (p1_i[10]),
.NOE (p1_z[10])
);
PAD_INOUT8MA_NOE uPAD_P1_11 (
.PAD (P1[11]),
.O (p1_o[11]),
.I (p1_i[11]),
.NOE (p1_z[11])
);
PAD_INOUT8MA_NOE uPAD_P1_12 (
.PAD (P1[12]),
.O (p1_o[12]),
.I (p1_i[12]),
.NOE (p1_z[12])
);
PAD_INOUT8MA_NOE uPAD_P1_13 (
.PAD (P1[13]),
.O (p1_o[13]),
.I (p1_i[13]),
.NOE (p1_z[13])
);
PAD_INOUT8MA_NOE uPAD_P1_14 (
.PAD (P1[14]),
.O (p1_o[14]),
.I (p1_i[14]),
.NOE (p1_z[14])
);
PAD_INOUT8MA_NOE uPAD_P1_15 (
.PAD (P1[15]),
.O (p1_o[15]),
.I (p1_i[15]),
.NOE (p1_z[15])
);
endmodule
This page: |
Created: | Wed Feb 22 13:33:07 2023 |
|
From: |
../verilog/nanosoc_chip_pads.v |