.HREADYOUTS (HREADYOUT_adp),
.HRESPS (HRESP_adp),
// Internal Address/Control Signals
.sel_ip (i_sel0),
.addr_ip (i_addr0),
.auser_ip (i_auser0),
.trans_ip (i_trans0),
.write_ip (i_write0),
.size_ip (i_size0),
.burst_ip (i_burst0),
.prot_ip (i_prot0),
.master_ip (i_master0),
.mastlock_ip (i_mastlock0),
.held_tran_ip (i_held_tran0)
);
// Input stage for SI1
soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_1 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input Port Address/Control Signals
.HSELS (HSEL_dma),
.HADDRS (HADDR_dma),
.HTRANSS (HTRANS_dma),
.HWRITES (HWRITE_dma),
.HSIZES (HSIZE_dma),
.HBURSTS (HBURST_dma),
.HPROTS (HPROT_dma),
.HMASTERS (HMASTER_dma),
.HMASTLOCKS (HMASTLOCK_dma),
.HREADYS (HREADY_dma),
.HAUSERS (HAUSER_dma),
// Internal Response
.active_ip (i_active1),
.readyout_ip (i_readyout1),
.resp_ip (i_resp1),
// Input Port Response
.HREADYOUTS (HREADYOUT_dma),
.HRESPS (HRESP_dma),
// Internal Address/Control Signals
.sel_ip (i_sel1),
.addr_ip (i_addr1),
.auser_ip (i_auser1),
.trans_ip (i_trans1),
.write_ip (i_write1),
.size_ip (i_size1),
.burst_ip (i_burst1),
.prot_ip (i_prot1),
.master_ip (i_master1),
.mastlock_ip (i_mastlock1),
.held_tran_ip (i_held_tran1)
);
// Input stage for SI2
soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_2 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input Port Address/Control Signals
.HSELS (HSEL_dma2),
.HADDRS (HADDR_dma2),
.HTRANSS (HTRANS_dma2),
.HWRITES (HWRITE_dma2),
.HSIZES (HSIZE_dma2),
.HBURSTS (HBURST_dma2),
.HPROTS (HPROT_dma2),
.HMASTERS (HMASTER_dma2),
.HMASTLOCKS (HMASTLOCK_dma2),
.HREADYS (HREADY_dma2),
.HAUSERS (HAUSER_dma2),
// Internal Response
.active_ip (i_active2),
.readyout_ip (i_readyout2),
.resp_ip (i_resp2),
// Input Port Response
.HREADYOUTS (HREADYOUT_dma2),
.HRESPS (HRESP_dma2),
// Internal Address/Control Signals
.sel_ip (i_sel2),
.addr_ip (i_addr2),
.auser_ip (i_auser2),
.trans_ip (i_trans2),
.write_ip (i_write2),
.size_ip (i_size2),
.burst_ip (i_burst2),
.prot_ip (i_prot2),
.master_ip (i_master2),
.mastlock_ip (i_mastlock2),
.held_tran_ip (i_held_tran2)
);
// Input stage for SI3
soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_3 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input Port Address/Control Signals
.HSELS (HSEL_cpu),
.HADDRS (HADDR_cpu),
.HTRANSS (HTRANS_cpu),
.HWRITES (HWRITE_cpu),
.HSIZES (HSIZE_cpu),
.HBURSTS (HBURST_cpu),
.HPROTS (HPROT_cpu),
.HMASTERS (HMASTER_cpu),
.HMASTLOCKS (HMASTLOCK_cpu),
.HREADYS (HREADY_cpu),
.HAUSERS (HAUSER_cpu),
// Internal Response
.active_ip (i_active3),
.readyout_ip (i_readyout3),
.resp_ip (i_resp3),
// Input Port Response
.HREADYOUTS (HREADYOUT_cpu),
.HRESPS (HRESP_cpu),
// Internal Address/Control Signals
.sel_ip (i_sel3),
.addr_ip (i_addr3),
.auser_ip (i_auser3),
.trans_ip (i_trans3),
.write_ip (i_write3),
.size_ip (i_size3),
.burst_ip (i_burst3),
.prot_ip (i_prot3),
.master_ip (i_master3),
.mastlock_ip (i_mastlock3),
.held_tran_ip (i_held_tran3)
);
// Matrix decoder for SI0
soclabs_4x7_MatrixDecode_adp u_soclabs_4x7_matrixdecode_adp (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Internal address remapping control
.remapping_dec ( REMAP[0] ),
// Signals from Input stage SI0
.HREADYS (HREADY_adp),
.sel_dec (i_sel0),
.decode_addr_dec (i_addr0[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans0),
// Control/Response for Output Stage MI0
.active_dec0 (i_active0to0),
.readyout_dec0 (i_hready_mux__rom1),
.resp_dec0 (HRESP_rom1),
.rdata_dec0 (HRDATA_rom1),
.ruser_dec0 (HRUSER_rom1),
// Control/Response for Output Stage MI1
.active_dec1 (i_active0to1),
.readyout_dec1 (i_hready_mux__ram2),
.resp_dec1 (HRESP_ram2),
.rdata_dec1 (HRDATA_ram2),
.ruser_dec1 (HRUSER_ram2),
// Control/Response for Output Stage MI2
.active_dec2 (i_active0to2),
.readyout_dec2 (i_hready_mux__ram3),
.resp_dec2 (HRESP_ram3),
.rdata_dec2 (HRDATA_ram3),
.ruser_dec2 (HRUSER_ram3),
// Control/Response for Output Stage MI3
.active_dec3 (i_active0to3),
.readyout_dec3 (i_hready_mux__sys),
.resp_dec3 (HRESP_sys),
.rdata_dec3 (HRDATA_sys),
.ruser_dec3 (HRUSER_sys),
// Control/Response for Output Stage MI4
.active_dec4 (i_active0to4),
.readyout_dec4 (i_hready_mux__ram8),
.resp_dec4 (HRESP_ram8),
.rdata_dec4 (HRDATA_ram8),
.ruser_dec4 (HRUSER_ram8),
// Control/Response for Output Stage MI5
.active_dec5 (i_active0to5),
.readyout_dec5 (i_hready_mux__ram9),
.resp_dec5 (HRESP_ram9),
.rdata_dec5 (HRDATA_ram9),
.ruser_dec5 (HRUSER_ram9),
// Control/Response for Output Stage MI6
.active_dec6 (i_active0to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
.ruser_dec6 (HRUSER_exp),
.sel_dec0 (i_sel0to0),
.sel_dec1 (i_sel0to1),
.sel_dec2 (i_sel0to2),
.sel_dec3 (i_sel0to3),
.sel_dec4 (i_sel0to4),
.sel_dec5 (i_sel0to5),
.sel_dec6 (i_sel0to6),
.active_dec (i_active0),
.HREADYOUTS (i_readyout0),
.HRESPS (i_resp0),
.HRUSERS (HRUSER_adp),
.HRDATAS (HRDATA_adp)
);
// Matrix decoder for SI1
soclabs_4x7_MatrixDecode_dma u_soclabs_4x7_matrixdecode_dma (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Signals from Input stage SI1
.HREADYS (HREADY_dma),
.sel_dec (i_sel1),
.decode_addr_dec (i_addr1[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans1),
// Control/Response for Output Stage MI0
.active_dec0 (i_active1to0),
.readyout_dec0 (i_hready_mux__rom1),
.resp_dec0 (HRESP_rom1),
.rdata_dec0 (HRDATA_rom1),
.ruser_dec0 (HRUSER_rom1),
// Control/Response for Output Stage MI1
.active_dec1 (i_active1to1),
.readyout_dec1 (i_hready_mux__ram2),
.resp_dec1 (HRESP_ram2),
.rdata_dec1 (HRDATA_ram2),
.ruser_dec1 (HRUSER_ram2),
// Control/Response for Output Stage MI2
.active_dec2 (i_active1to2),
.readyout_dec2 (i_hready_mux__ram3),
.resp_dec2 (HRESP_ram3),
.rdata_dec2 (HRDATA_ram3),
.ruser_dec2 (HRUSER_ram3),
// Control/Response for Output Stage MI3
.active_dec3 (i_active1to3),
.readyout_dec3 (i_hready_mux__sys),
.resp_dec3 (HRESP_sys),
.rdata_dec3 (HRDATA_sys),
.ruser_dec3 (HRUSER_sys),
// Control/Response for Output Stage MI4
.active_dec4 (i_active1to4),
.readyout_dec4 (i_hready_mux__ram8),
.resp_dec4 (HRESP_ram8),
.rdata_dec4 (HRDATA_ram8),
.ruser_dec4 (HRUSER_ram8),
// Control/Response for Output Stage MI5
.active_dec5 (i_active1to5),
.readyout_dec5 (i_hready_mux__ram9),
.resp_dec5 (HRESP_ram9),
.rdata_dec5 (HRDATA_ram9),
.ruser_dec5 (HRUSER_ram9),
// Control/Response for Output Stage MI6
.active_dec6 (i_active1to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
.ruser_dec6 (HRUSER_exp),
.sel_dec0 (i_sel1to0),
.sel_dec1 (i_sel1to1),
.sel_dec2 (i_sel1to2),
.sel_dec3 (i_sel1to3),
.sel_dec4 (i_sel1to4),
.sel_dec5 (i_sel1to5),
.sel_dec6 (i_sel1to6),
.active_dec (i_active1),
.HREADYOUTS (i_readyout1),
.HRESPS (i_resp1),
.HRUSERS (HRUSER_dma),
.HRDATAS (HRDATA_dma)
);
// Matrix decoder for SI2
soclabs_4x7_MatrixDecode_dma2 u_soclabs_4x7_matrixdecode_dma2 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Signals from Input stage SI2
.HREADYS (HREADY_dma2),
.sel_dec (i_sel2),
.decode_addr_dec (i_addr2[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans2),
// Control/Response for Output Stage MI0
.active_dec0 (i_active2to0),
.readyout_dec0 (i_hready_mux__rom1),
.resp_dec0 (HRESP_rom1),
.rdata_dec0 (HRDATA_rom1),
.ruser_dec0 (HRUSER_rom1),
// Control/Response for Output Stage MI1
.active_dec1 (i_active2to1),
.readyout_dec1 (i_hready_mux__ram2),
.resp_dec1 (HRESP_ram2),
.rdata_dec1 (HRDATA_ram2),
.ruser_dec1 (HRUSER_ram2),
// Control/Response for Output Stage MI2
.active_dec2 (i_active2to2),
.readyout_dec2 (i_hready_mux__ram3),
.resp_dec2 (HRESP_ram3),
.rdata_dec2 (HRDATA_ram3),
.ruser_dec2 (HRUSER_ram3),
// Control/Response for Output Stage MI3
.active_dec3 (i_active2to3),
.readyout_dec3 (i_hready_mux__sys),
.resp_dec3 (HRESP_sys),
.rdata_dec3 (HRDATA_sys),
.ruser_dec3 (HRUSER_sys),
// Control/Response for Output Stage MI4
.active_dec4 (i_active2to4),
.readyout_dec4 (i_hready_mux__ram8),
.resp_dec4 (HRESP_ram8),
.rdata_dec4 (HRDATA_ram8),
.ruser_dec4 (HRUSER_ram8),
// Control/Response for Output Stage MI5
.active_dec5 (i_active2to5),
.readyout_dec5 (i_hready_mux__ram9),
.resp_dec5 (HRESP_ram9),
.rdata_dec5 (HRDATA_ram9),
.ruser_dec5 (HRUSER_ram9),
// Control/Response for Output Stage MI6
.active_dec6 (i_active2to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
.ruser_dec6 (HRUSER_exp),
.sel_dec0 (i_sel2to0),
.sel_dec1 (i_sel2to1),
.sel_dec2 (i_sel2to2),
.sel_dec3 (i_sel2to3),
.sel_dec4 (i_sel2to4),
.sel_dec5 (i_sel2to5),
.sel_dec6 (i_sel2to6),
.active_dec (i_active2),
.HREADYOUTS (i_readyout2),
.HRESPS (i_resp2),
.HRUSERS (HRUSER_dma2),
.HRDATAS (HRDATA_dma2)
);
// Matrix decoder for SI3
soclabs_4x7_MatrixDecode_cpu u_soclabs_4x7_matrixdecode_cpu (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Internal address remapping control
.remapping_dec ( REMAP[0] ),
// Signals from Input stage SI3
.HREADYS (HREADY_cpu),
.sel_dec (i_sel3),
.decode_addr_dec (i_addr3[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans3),
// Control/Response for Output Stage MI0
.active_dec0 (i_active3to0),
.readyout_dec0 (i_hready_mux__rom1),
.resp_dec0 (HRESP_rom1),
.rdata_dec0 (HRDATA_rom1),
.ruser_dec0 (HRUSER_rom1),
// Control/Response for Output Stage MI1
.active_dec1 (i_active3to1),
.readyout_dec1 (i_hready_mux__ram2),
.resp_dec1 (HRESP_ram2),
.rdata_dec1 (HRDATA_ram2),
.ruser_dec1 (HRUSER_ram2),
// Control/Response for Output Stage MI2
.active_dec2 (i_active3to2),
.readyout_dec2 (i_hready_mux__ram3),
.resp_dec2 (HRESP_ram3),
.rdata_dec2 (HRDATA_ram3),
.ruser_dec2 (HRUSER_ram3),
// Control/Response for Output Stage MI3
.active_dec3 (i_active3to3),
.readyout_dec3 (i_hready_mux__sys),
.resp_dec3 (HRESP_sys),
.rdata_dec3 (HRDATA_sys),
.ruser_dec3 (HRUSER_sys),
// Control/Response for Output Stage MI4
.active_dec4 (i_active3to4),
.readyout_dec4 (i_hready_mux__ram8),
.resp_dec4 (HRESP_ram8),
.rdata_dec4 (HRDATA_ram8),
.ruser_dec4 (HRUSER_ram8),
// Control/Response for Output Stage MI5
.active_dec5 (i_active3to5),
.readyout_dec5 (i_hready_mux__ram9),
.resp_dec5 (HRESP_ram9),
.rdata_dec5 (HRDATA_ram9),
.ruser_dec5 (HRUSER_ram9),
// Control/Response for Output Stage MI6
.active_dec6 (i_active3to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
.ruser_dec6 (HRUSER_exp),
.sel_dec0 (i_sel3to0),
.sel_dec1 (i_sel3to1),
.sel_dec2 (i_sel3to2),
.sel_dec3 (i_sel3to3),
.sel_dec4 (i_sel3to4),
.sel_dec5 (i_sel3to5),
.sel_dec6 (i_sel3to6),
.active_dec (i_active3),
.HREADYOUTS (i_readyout3),
.HRESPS (i_resp3),
.HRUSERS (HRUSER_cpu),
.HRDATAS (HRDATA_cpu)
);
// Output stage for MI0
soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_0 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
.sel_op0 (i_sel0to0),
.addr_op0 (i_addr0),
.auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
.burst_op0 (i_burst0),
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
.wdata_op0 (HWDATA_adp),
.wuser_op0 (HWUSER_adp),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to0),
.addr_op1 (i_addr1),
.auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
.burst_op1 (i_burst1),
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
.wdata_op1 (HWDATA_dma),
.wuser_op1 (HWUSER_dma),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to0),
.addr_op2 (i_addr2),
.auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
.burst_op2 (i_burst2),
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
.wdata_op2 (HWDATA_dma2),
.wuser_op2 (HWUSER_dma2),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to0),
.addr_op3 (i_addr3),
.auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
.burst_op3 (i_burst3),
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
.wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
.HREADYOUTM (HREADYOUT_rom1),
.active_op0 (i_active0to0),
.active_op1 (i_active1to0),
.active_op2 (i_active2to0),
.active_op3 (i_active3to0),
// Slave Address/Control Signals
.HSELM (HSEL_rom1),
.HADDRM (HADDR_rom1),
.HAUSERM (HAUSER_rom1),
.HTRANSM (HTRANS_rom1),
.HWRITEM (HWRITE_rom1),
.HSIZEM (HSIZE_rom1),
.HBURSTM (HBURST_rom1),
.HPROTM (HPROT_rom1),
.HMASTERM (HMASTER_rom1),
.HMASTLOCKM (HMASTLOCK_rom1),
.HREADYMUXM (i_hready_mux__rom1),
.HWUSERM (HWUSER_rom1),
.HWDATAM (HWDATA_rom1)
);
// Drive output with internal version
assign HREADYMUX_rom1 = i_hready_mux__rom1;
// Output stage for MI1
soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_1 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
.sel_op0 (i_sel0to1),
.addr_op0 (i_addr0),
.auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
.burst_op0 (i_burst0),
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
.wdata_op0 (HWDATA_adp),
.wuser_op0 (HWUSER_adp),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to1),
.addr_op1 (i_addr1),
.auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
.burst_op1 (i_burst1),
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
.wdata_op1 (HWDATA_dma),
.wuser_op1 (HWUSER_dma),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to1),
.addr_op2 (i_addr2),
.auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
.burst_op2 (i_burst2),
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
.wdata_op2 (HWDATA_dma2),
.wuser_op2 (HWUSER_dma2),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to1),
.addr_op3 (i_addr3),
.auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
.burst_op3 (i_burst3),
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
.wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
.HREADYOUTM (HREADYOUT_ram2),
.active_op0 (i_active0to1),
.active_op1 (i_active1to1),
.active_op2 (i_active2to1),
.active_op3 (i_active3to1),
// Slave Address/Control Signals
.HSELM (HSEL_ram2),
.HADDRM (HADDR_ram2),
.HAUSERM (HAUSER_ram2),
.HTRANSM (HTRANS_ram2),
.HWRITEM (HWRITE_ram2),
.HSIZEM (HSIZE_ram2),
.HBURSTM (HBURST_ram2),
.HPROTM (HPROT_ram2),
.HMASTERM (HMASTER_ram2),
.HMASTLOCKM (HMASTLOCK_ram2),
.HREADYMUXM (i_hready_mux__ram2),
.HWUSERM (HWUSER_ram2),
.HWDATAM (HWDATA_ram2)
);
// Drive output with internal version
assign HREADYMUX_ram2 = i_hready_mux__ram2;
// Output stage for MI2
soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_2 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
.sel_op0 (i_sel0to2),
.addr_op0 (i_addr0),
.auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
.burst_op0 (i_burst0),
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
.wdata_op0 (HWDATA_adp),
.wuser_op0 (HWUSER_adp),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to2),
.addr_op1 (i_addr1),
.auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
.burst_op1 (i_burst1),
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
.wdata_op1 (HWDATA_dma),
.wuser_op1 (HWUSER_dma),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to2),
.addr_op2 (i_addr2),
.auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
.burst_op2 (i_burst2),
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
.wdata_op2 (HWDATA_dma2),
.wuser_op2 (HWUSER_dma2),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to2),
.addr_op3 (i_addr3),
.auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
.burst_op3 (i_burst3),
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
.wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
.HREADYOUTM (HREADYOUT_ram3),
.active_op0 (i_active0to2),
.active_op1 (i_active1to2),
.active_op2 (i_active2to2),
.active_op3 (i_active3to2),
// Slave Address/Control Signals
.HSELM (HSEL_ram3),
.HADDRM (HADDR_ram3),
.HAUSERM (HAUSER_ram3),
.HTRANSM (HTRANS_ram3),
.HWRITEM (HWRITE_ram3),
.HSIZEM (HSIZE_ram3),
.HBURSTM (HBURST_ram3),
.HPROTM (HPROT_ram3),
.HMASTERM (HMASTER_ram3),
.HMASTLOCKM (HMASTLOCK_ram3),
.HREADYMUXM (i_hready_mux__ram3),
.HWUSERM (HWUSER_ram3),
.HWDATAM (HWDATA_ram3)
);
// Drive output with internal version
assign HREADYMUX_ram3 = i_hready_mux__ram3;
// Output stage for MI3
soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_3 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
.sel_op0 (i_sel0to3),
.addr_op0 (i_addr0),
.auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
.burst_op0 (i_burst0),
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
.wdata_op0 (HWDATA_adp),
.wuser_op0 (HWUSER_adp),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to3),
.addr_op1 (i_addr1),
.auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
.burst_op1 (i_burst1),
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
.wdata_op1 (HWDATA_dma),
.wuser_op1 (HWUSER_dma),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to3),
.addr_op2 (i_addr2),
.auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
.burst_op2 (i_burst2),
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
.wdata_op2 (HWDATA_dma2),
.wuser_op2 (HWUSER_dma2),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to3),
.addr_op3 (i_addr3),
.auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
.burst_op3 (i_burst3),
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
.wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
.HREADYOUTM (HREADYOUT_sys),
.active_op0 (i_active0to3),
.active_op1 (i_active1to3),
.active_op2 (i_active2to3),
.active_op3 (i_active3to3),
// Slave Address/Control Signals
.HSELM (HSEL_sys),
.HADDRM (HADDR_sys),
.HAUSERM (HAUSER_sys),
.HTRANSM (HTRANS_sys),
.HWRITEM (HWRITE_sys),
.HSIZEM (HSIZE_sys),
.HBURSTM (HBURST_sys),
.HPROTM (HPROT_sys),
.HMASTERM (HMASTER_sys),
.HMASTLOCKM (HMASTLOCK_sys),
.HREADYMUXM (i_hready_mux__sys),
.HWUSERM (HWUSER_sys),
.HWDATAM (HWDATA_sys)
);
// Drive output with internal version
assign HREADYMUX_sys = i_hready_mux__sys;
// Output stage for MI4
soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_4 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
.sel_op0 (i_sel0to4),
.addr_op0 (i_addr0),
.auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
.burst_op0 (i_burst0),
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
.wdata_op0 (HWDATA_adp),
.wuser_op0 (HWUSER_adp),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to4),
.addr_op1 (i_addr1),
.auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
.burst_op1 (i_burst1),
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
.wdata_op1 (HWDATA_dma),
.wuser_op1 (HWUSER_dma),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to4),
.addr_op2 (i_addr2),
.auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
.burst_op2 (i_burst2),
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
.wdata_op2 (HWDATA_dma2),
.wuser_op2 (HWUSER_dma2),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to4),
.addr_op3 (i_addr3),
.auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
.burst_op3 (i_burst3),
.prot_op3 (i_prot3),
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
.wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
.HREADYOUTM (HREADYOUT_ram8),
.active_op0 (i_active0to4),
.active_op1 (i_active1to4),
.active_op2 (i_active2to4),
.active_op3 (i_active3to4),
// Slave Address/Control Signals
.HSELM (HSEL_ram8),
.HADDRM (HADDR_ram8),
.HAUSERM (HAUSER_ram8),
.HTRANSM (HTRANS_ram8),
.HWRITEM (HWRITE_ram8),
.HSIZEM (HSIZE_ram8),
.HBURSTM (HBURST_ram8),
.HPROTM (HPROT_ram8),
.HMASTERM (HMASTER_ram8),
.HMASTLOCKM (HMASTLOCK_ram8),
.HREADYMUXM (i_hready_mux__ram8),
.HWUSERM (HWUSER_ram8),
.HWDATAM (HWDATA_ram8)
);
// Drive output with internal version
assign HREADYMUX_ram8 = i_hready_mux__ram8;
// Output stage for MI5
soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_5 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
.sel_op0 (i_sel0to5),
.addr_op0 (i_addr0),
.auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
.burst_op0 (i_burst0),
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
.wdata_op0 (HWDATA_adp),
.wuser_op0 (HWUSER_adp),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to5),
.addr_op1 (i_addr1),
.auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
.burst_op1 (i_burst1),
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
.wdata_op1 (HWDATA_dma),
.wuser_op1 (HWUSER_dma),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to5),
.addr_op2 (i_addr2),
.auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
This page: |
Created: | Wed Feb 22 13:33:08 2023 |
|
From: |
../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v |