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//-----------------------------------------------------------------------------
// customised top-level Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
//            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
//      SVN Information
//
//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
//      Revision            : $Revision: 371321 $
//
//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//

[Up: nanosoc_chip_pads u_nanosoc_chip]
module nanosoc_chipIndex
 (
`ifdef POWER_PINS
  inout  wire          VDDIO,
  inout  wire          VSSIO,
  inout  wire          VDD,
  inout  wire          VSS,
`endif
  input  wire          xtal_clk_i,
  output wire          xtal_clk_o,
  input  wire          nrst_i,
  input  wire  [15:0]  p0_i, // level-shifted input from pad
  output wire  [15:0]  p0_o, // output port drive
  output wire  [15:0]  p0_e, // active high output drive enable (pad tech dependent)
  output wire  [15:0]  p0_z, // active low output drive enable (pad tech dependent)
  input  wire  [15:0]  p1_i, // level-shifted input from pad
  output wire  [15:0]  p1_o, // output port drive
  output wire  [15:0]  p1_e, // active high output drive enable (pad tech dependent)
  output wire  [15:0]  p1_z, // active low output drive enable (pad tech dependent)
  input  wire          swdio_i,
  output wire          swdio_o,
  output wire          swdio_e,
  output wire          swdio_z,
  input  wire          swdclk_i
  );

localparam    CLKGATE_PRESENT = 0;
localparam    DMA_CHANNEL_NUM = 1;
localparam    INCLUDE_DMA = 1;
localparam    CORTEX_M0 = 1;

//------------------------------------
// CMSDK internal wire naming preserved

  wire          xtal_clk_in = xtal_clk_i;
  wire          xtal_clk_out;
  wire          pll_clk;
  wire          CLK;
  
  assign        xtal_clk_o = xtal_clk_out;
  wire          nrst_in = nrst_i;
  wire  [15:0]  p0_in;             // level-shifted input from pad
  wire  [15:0]  p0_out;            // output port drive
  wire  [15:0]  p0_out_en;         // active high output drive enable (pad tech dependent)
  wire  [15:0]  p0_out_nen;        // active low output drive enable (pad tech dependent)

  wire  [15:0]  p1_in;            // level-shifted input from pad
  wire  [15:0]  p1_out;           // output port drive
  wire  [15:0]  p1_out_en;        // active high output drive enable (pad tech dependent)
  wire  [15:0]  p1_out_nen;       // active low output drive enable (pad tech dependent)
  wire  [15:0]  p1_in_mux;        // level-shifted input from pad
  wire  [15:0]  p1_out_mux;       // output port drive
  wire  [15:0]  p1_out_en_mux;    // active high output drive enable (pad tech dependent)
  wire  [15:0]  p1_out_nen_mux;   // active low output drive enable (pad tech dependent)

  wire          swdio_in;
  wire          swdio_out;
  wire          swdio_out_en;
  wire          swdio_out_nen;
  wire          swdclk_in;

  wire          ft_clk_o;
  wire          ft_ssn_o;
  wire          ft_miso_i;
  wire          ft_miosio_o;
  wire          ft_miosio_e;
  wire          ft_miosio_z;
  wire          ft_miosio_i;

 // --------------------------------------------------------------------------------
 // Port-0 IO pad driver mapping
 // --------------------------------------------------------------------------------

  assign        p0_in = p0_i;      // level-shifted input from pad
  assign        p0_o = p0_out;     // output port drive
  assign        p0_e = p0_out_en;  // active high output drive enable (pad tech dependent)
  assign        p0_z = p0_out_nen; // active low output drive enable (pad tech dependent)


 // --------------------------------------------------------------------------------
 // Port-1 IO pad driver mapping
 // --------------------------------------------------------------------------------

// modify p1_mux [3:0] for ft1248 interface
//  assign        p1_in_mux[3:0] = p1_i[3:0]; // IO MUX controlled bidirectionals
//  assign        p1_o[3:0] = p1_out_mux[3:0];    
//  assign        p1_e[3:0] = p1_out_en_mux[3:0];
//  assign        p1_z[3:0] = p1_out_nen_mux[3:0];

  assign        ft_miso_i = p1_i[0]; // FT_MISO INPUT pad configuration
  assign        p1_in_mux[0] = p1_i[0];
  assign        p1_o[0] = 1'b0;    
  assign        p1_e[0] = 1'b0;
  assign        p1_z[0] = 1'b1;
  
  assign        p1_in_mux[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
  assign        p1_o[1] = ft_clk_o;    
  assign        p1_e[1] = 1'b1; 
  assign        p1_z[1] = 1'b0;

  assign        ft_miosio_i = p1_i[2]; // FT_MIOSIO INOUT pad configuration
  assign        p1_in_mux[2] = p1_i[2];
  assign        p1_o[2] = ft_miosio_o;    
  assign        p1_e[2] = ft_miosio_e;
  assign        p1_z[2] = ft_miosio_z;

  assign        p1_in_mux[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
  assign        p1_o[3] = ft_ssn_o;    
  assign        p1_e[3] = 1'b1; 
  assign        p1_z[3] = 1'b0;

  assign        p1_in_mux[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
  assign        p1_o[15:4] = p1_out_mux[15:4];    
  assign        p1_e[15:4] = p1_out_en_mux[15:4];
  assign        p1_z[15:4] = p1_out_nen_mux[15:4];


//TIE_HI uTIEHI (.tiehi(tiehi));
 wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
 wire tielo = 1'b0;



//----------------------------------------
// SOC clock and reset management
//----------------------------------------
//

    wire         PORESETn;// Power on reset
    wire         HRESETn; // AHB reset
    wire         PRESETn; // APB and peripheral reset
    wire         DBGRESETn; // Debug system reset
    wire         FCLK;    // Free running system clock
    wire         HCLK;    // System clock from PMU
    wire         DCLK;
    wire         SCLK;
    wire         PCLK;    // Peripheral clock
    wire         PCLKG;   // Gated PCLK for APB
    wire         PCLKEN;  // Clock divider for AHB to APB bridge
    wire         APBACTIVE;
  // event signals
    wire         TXEV;
    wire         RXEV;
    wire         nTRST;            // JTAG - Test reset (active low)
    wire         SWDI;          // JTAG/SWD - TMS / SWD data input
    wire         SWCLK;         // JTAG/SWD - TCK / SWCLK
    wire         SWDO;             // SWD - SWD data output
    wire         SWDOEN;           // SWD - SWD data output enable
    wire         SYSRESETREQ;    // processor system reset request
    wire         WDOGRESETREQ;   // watchdog system reset request
    wire         HRESETREQ;      // Combined system reset request
    wire         cmsdk_SYSRESETREQ; // Combined system reset request
    wire         clk_ctrl_sys_reset_req;
    wire         PMUHRESETREQ;
    wire         PMUDBGRESETREQ;
    wire         LOCKUP;
    wire         LOCKUPRESET;
    wire         SLEEPING;
    wire         GATEHCLK;         // Processor status - safe to gate HCLK
    wire         WAKEUP;           // Wake up request from WIC
    wire         WICENREQ;         // WIC enable request from PMU
    wire         WICENACK;         // WIC enable ack to PMU
    wire         PMUENABLE;
    wire         CDBGPWRUPREQ;     // Debug Power Up request to PMU
    wire         CDBGPWRUPACK;     // Debug Power Up ACK from PMU
    wire         SLEEPHOLDREQn;    // Sleep extension request from PMU
    wire         SLEEPHOLDACKn;    // Sleep extension request to PMU
    wire         SYSPWRDOWNACK;
    wire         DBGPWRDOWNACK;
    wire         SYSPWRDOWN;
    wire         DBGPWRDOWN;
    wire         SYSISOLATEn;
    wire         SYSRETAINn;
    wire         DBGISOLATEn;
    wire         SLEEPDEEP;
    wire         ADPRESETREQ;
    // Scan test dummy signals; not connected until scan insertion
    wire          TESTMODE;        // Test mode enable signal (override synchronizers etc)
    wire          SCANENABLE;      // Scan enable signal
    wire          SCANINHCLK;      // HCLK scan input
    wire          SCANOUTHCLK;     // Scan Chain wire  

// not required for FPGA
    assign        TESTMODE = 1'b0; 
    assign        SCANENABLE = 1'b0; 
    assign        SCANINHCLK = 1'b0; 
    assign        SCANOUTHCLK = 1'b0;

// Technology-specific PLL/Frequecy synthesizer would generate
//   CLK, FCLK (Free running system clock)
// from
//    xtal_clk_in

    assign  pll_clk = xtal_clk_in; // default to no PLL
    
    assign  CLK = (TESTMODE) ? xtal_clk_in : pll_clk;
  

//?    assign   HCLKSYS  = (INCLUDE_DMA!=0) ? SCLK : HCLK;
    assign   HCLK  = FCLK;
  
   // System Reset request can be from processor or watchdog
   // or when lockup happens and the control flag is set.
   assign  cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
                               ADPRESETREQ |
                               (LOCKUP & LOCKUPRESET);
   assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;

  // Clock controller to generate reset and clock signals
  cmsdk_mcu_clkctrl
   #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
   u_cmsdk_mcu_clkctrl(
     // inputs
    .XTAL1            (CLK),
    .NRST             (nrst_in),

    .APBACTIVE        (APBACTIVE),
    .SLEEPING         (SLEEPING),
    .SLEEPDEEP        (SLEEPDEEP),
    .LOCKUP           (LOCKUP),
    .LOCKUPRESET      (LOCKUPRESET),
    .SYSRESETREQ      (clk_ctrl_sys_reset_req),
    .DBGRESETREQ      (PMUDBGRESETREQ),
    .CGBYPASS         (TESTMODE),
    .RSTBYPASS        (TESTMODE),

     // outputs
    .XTAL2            (xtal_clk_out),

    .FCLK             (FCLK),

    .PCLK             (PCLK),
    .PCLKG            (PCLKG),
    .PCLKEN           (PCLKEN),
//?`ifdef CORTEX_M0DESIGNSTART
//?    .PORESETn         (PORESETn),  // for cm0 designstart
//?    .HRESETn          (HRESETn),   // for cm0 designstart
//?`endif
    .PRESETn          (PRESETn)
    );

    wire   gated_hclk;
    wire   gated_dclk;
    wire   gated_sclk;

  cortexm0_rst_ctl u_rst_ctl
  (// Inputs
   .GLOBALRESETn      (nrst_in),
   .FCLK              (FCLK),
   .HCLK              (gated_hclk),
   .DCLK              (gated_dclk),
   .SYSRESETREQ       (cmsdk_SYSRESETREQ),
   .PMUHRESETREQ      (PMUHRESETREQ),
   .PMUDBGRESETREQ    (PMUDBGRESETREQ),
   .RSTBYPASS         (TESTMODE),
   .SE                (SCANENABLE),

   // Outputs
   .PORESETn          (PORESETn),
   .HRESETn           (HRESETn),
   .DBGRESETn         (DBGRESETn),
   .HRESETREQ         (HRESETREQ));


  // Cortex-M0 Power management unit
  cortexm0_pmu u_cortexm0_pmu
  ( // Inputs
    .FCLK             (FCLK),
    .PORESETn         (PORESETn),
    .HRESETREQ        (cmsdk_SYSRESETREQ), // from processor / watchdog
    .PMUENABLE        (PMUENABLE),       // from System Controller
    .WICENACK         (WICENACK),        // from WIC in integration

    .WAKEUP           (WAKEUP),          // from WIC in integration
    .CDBGPWRUPREQ     (CDBGPWRUPREQ),

    .SLEEPDEEP        (SLEEPDEEP),
    .SLEEPHOLDACKn    (SLEEPHOLDACKn),
    .GATEHCLK         (GATEHCLK),
    .SYSPWRDOWNACK    (SYSPWRDOWNACK),
    .DBGPWRDOWNACK    (DBGPWRDOWNACK),
    .CGBYPASS         (TESTMODE),

   // Outputs
    .HCLK             (gated_hclk),
    .DCLK             (gated_dclk),
    .SCLK             (gated_sclk),
    .WICENREQ         (WICENREQ),
    .CDBGPWRUPACK     (CDBGPWRUPACK),
    .SYSISOLATEn      (SYSISOLATEn),
    .SYSRETAINn       (SYSRETAINn),
    .SYSPWRDOWN       (SYSPWRDOWN),
    .DBGISOLATEn      (DBGISOLATEn),
    .DBGPWRDOWN       (DBGPWRDOWN),
    .SLEEPHOLDREQn    (SLEEPHOLDREQn),
    .PMUDBGRESETREQ   (PMUDBGRESETREQ),
    .PMUHRESETREQ     (PMUHRESETREQ)
   );

  // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
  assign  HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
  assign  DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
  assign  SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;


  // In this example system, power control takes place immediately.
  // In a real circuit you might need to add delays in the next two
  // signal assignments for correct operation.
  assign   SYSPWRDOWNACK = SYSPWRDOWN;
  assign   DBGPWRDOWNACK = DBGPWRDOWN;

  wire              exp_penable;
  wire              exp_pwrite;
  wire  [11:0]      exp_paddr;
  wire  [31:0]      exp_pwdata;
  wire              exp12_psel;
  wire              exp12_pready;
  wire              exp12_pslverr;
  wire     [31:0]   exp12_prdata;
  wire              exp13_psel;
  wire              exp13_pready;
  wire              exp13_pslverr;
  wire     [31:0]   exp13_prdata;
  wire              exp14_psel;
  wire              exp14_pready;
  wire              exp14_pslverr;
  wire     [31:0]   exp14_prdata;
  wire              exp15_psel;
  wire              exp15_pready;
  wire              exp15_pslverr;
  wire     [31:0]   exp15_prdata;


  // internal peripheral signals
  wire               uart0_rxd;
  wire               uart0_txd;
  wire               uart0_txen;
  wire               uart1_rxd;
  wire               uart1_txd;
  wire               uart1_txen;
  wire               uart2_rxd;
  wire               uart2_txd;
  wire               uart2_txen;
  wire               timer0_extin;
  wire               timer1_extin;

  wire  [15:0]       p0_altfunc;

  wire  [15:0]       p1_altfunc;


// -----------------------------------------------------------------------------
// AHB Interconnect declarations
// Upper-case AMBA naming convention maintained
// -----------------------------------------------------------------------------

    // System Address Remap control
    wire    [3:0] REMAP;           // System Address REMAP control, bit-0 set on POR
    wire          ROM_MAP;
    
    // Manager port SI0 (inputs from master 0)
    wire   [31:0] HADDR_adp;         // Address bus
    wire    [1:0] HTRANS_adp;        // Transfer type
    wire          HWRITE_adp;        // Transfer direction
    wire    [2:0] HSIZE_adp;         // Transfer size
    wire    [2:0] HBURST_adp;        // Burst type
    wire    [3:0] HPROT_adp;         // Protection control
    wire   [31:0] HWDATA_adp;        // Write data
    wire          HMASTLOCK_adp;     // Locked Sequence
    wire    [1:0] HAUSER_adp;        // Address USER signals
    wire    [1:0] HWUSER_adp;        // Write-data USER signals
    // Manager port SI0 (outputs to master 0)
    wire   [31:0] HRDATA_adp;        // Read data bus
    wire          HREADY_adp;        // HREADY feedback
    wire          HRESP_adp;         // Transfer response
    wire    [1:0] HRUSER_adp;        // Read-data USER signals

    // Manager port SI1 (inputs from master 1)
    wire   [31:0] HADDR_dma;         // Address bus
    wire    [1:0] HTRANS_dma;        // Transfer type
    wire          HWRITE_dma;        // Transfer direction
    wire    [2:0] HSIZE_dma;         // Transfer size
    wire    [2:0] HBURST_dma;        // Burst type
    wire    [3:0] HPROT_dma;         // Protection control
    wire   [31:0] HWDATA_dma;        // Write data
    wire          HMASTLOCK_dma;     // Locked Sequence
    wire    [1:0] HAUSER_dma;        // Address USER signals
    wire    [1:0] HWUSER_dma;        // Write-data USER signals
    // Manager port SI1 (outputs to master 1)
    wire   [31:0] HRDATA_dma;        // Read data bus
    wire          HREADY_dma;        // HREADY feedback
    wire          HRESP_dma;         // Transfer response
    wire    [1:0] HRUSER_dma;        // Read-data USER signals

    // Manager port SI2 (inputs from master 2)
    wire   [31:0] HADDR_dma2;         // Address bus
    wire    [1:0] HTRANS_dma2;        // Transfer type
    wire          HWRITE_dma2;        // Transfer direction
    wire    [2:0] HSIZE_dma2;         // Transfer size
    wire    [2:0] HBURST_dma2;        // Burst type
    wire    [3:0] HPROT_dma2;         // Protection control
    wire   [31:0] HWDATA_dma2;        // Write data
    wire          HMASTLOCK_dma2;     // Locked Sequence
    wire    [1:0] HAUSER_dma2;        // Address USER signals
    wire    [1:0] HWUSER_dma2;        // Write-data USER signals
    // Manager port SI2 (outputs to master 2)
    wire   [31:0] HRDATA_dma2;        // Read data bus
    wire          HREADY_dma2;        // HREADY feedback
    wire          HRESP_dma2;         // Transfer response
    wire    [1:0] HRUSER_dma2;        // Read-data USER signals

    // Manager port SI3 (inputs from master 3)
    wire   [31:0] HADDR_cpu;         // Address bus
    wire    [1:0] HTRANS_cpu;        // Transfer type
    wire          HWRITE_cpu;        // Transfer direction
    wire    [2:0] HSIZE_cpu;         // Transfer size
    wire    [2:0] HBURST_cpu;        // Burst type
    wire    [3:0] HPROT_cpu;         // Protection control
    wire   [31:0] HWDATA_cpu;        // Write data
    wire          HMASTLOCK_cpu;     // Locked Sequence
    wire    [1:0] HAUSER_cpu;        // Address USER signals
    wire    [1:0] HWUSER_cpu;        // Write-data USER signals
    // Manager port SI3 (outputs to master 3)
    wire   [31:0] HRDATA_cpu;        // Read data bus
    wire          HREADY_cpu;        // HREADY feedback
    wire          HRESP_cpu;         // Transfer response
    wire    [1:0] HRUSER_cpu;        // Read-data USER signals

    // Subordinate port MI0 (outputs to slave 0)
    wire          HSEL_rom1;          // Slave Select
    wire   [31:0] HADDR_rom1;         // Address bus
    wire    [1:0] HTRANS_rom1;        // Transfer type
    wire          HWRITE_rom1;        // Transfer direction
    wire    [2:0] HSIZE_rom1;         // Transfer size
    wire    [2:0] HBURST_rom1;        // Burst type
    wire    [3:0] HPROT_rom1;         // Protection control
    wire   [31:0] HWDATA_rom1;        // Write data
    wire          HMASTLOCK_rom1;     // Locked Sequence
    wire          HREADYMUX_rom1;     // Transfer done
    wire    [1:0] HAUSER_rom1;        // Address USER signals
    wire    [1:0] HWUSER_rom1;        // Write-data USER signals
    // Subordinate port MI0 (inputs from slave 0)
    wire   [31:0] HRDATA_rom1;        // Read data bus
    wire          HREADYOUT_rom1;     // HREADY feedback
    wire          HRESP_rom1;         // Transfer response
    wire    [1:0] HRUSER_rom1;        // Read-data USER signals

    // Subordinate port MI1 (outputs to slave 1)
    wire          HSEL_ram2;          // Slave Select
    wire   [31:0] HADDR_ram2;         // Address bus
    wire    [1:0] HTRANS_ram2;        // Transfer type
    wire          HWRITE_ram2;        // Transfer direction
    wire    [2:0] HSIZE_ram2;         // Transfer size
    wire    [2:0] HBURST_ram2;        // Burst type
    wire    [3:0] HPROT_ram2;         // Protection control
    wire   [31:0] HWDATA_ram2;        // Write data
    wire          HMASTLOCK_ram2;     // Locked Sequence
    wire          HREADYMUX_ram2;     // Transfer done
    wire    [1:0] HAUSER_ram2;        // Address USER signals
    wire    [1:0] HWUSER_ram2;        // Write-data USER signals
    // Subordinate port MI1 (inputs from slave 1)
    wire   [31:0] HRDATA_ram2;        // Read data bus
    wire          HREADYOUT_ram2;     // HREADY feedback
    wire          HRESP_ram2;         // Transfer response
    wire    [1:0] HRUSER_ram2;        // Read-data USER signals

    // Subordinate port MI2 (outputs to slave 2)
    wire          HSEL_ram3;          // Slave Select
    wire   [31:0] HADDR_ram3;         // Address bus
    wire    [1:0] HTRANS_ram3;        // Transfer type
    wire          HWRITE_ram3;        // Transfer direction
    wire    [2:0] HSIZE_ram3;         // Transfer size
    wire    [2:0] HBURST_ram3;        // Burst type
    wire    [3:0] HPROT_ram3;         // Protection control
    wire   [31:0] HWDATA_ram3;        // Write data
    wire          HMASTLOCK_ram3;     // Locked Sequence
    wire          HREADYMUX_ram3;     // Transfer done
    wire    [1:0] HAUSER_ram3;        // Address USER signals
    wire    [1:0] HWUSER_ram3;        // Write-data USER signals
    // Subordinate port MI2 (inputs from slave 2)
    wire   [31:0] HRDATA_ram3;        // Read data bus
    wire          HREADYOUT_ram3;     // HREADY feedback
    wire          HRESP_ram3;         // Transfer response
    wire    [1:0] HRUSER_ram3;        // Read-data USER signals

    // Subordinate port MI3 (outputs to slave 3)
    wire          HSEL_sys;          // Slave Select
    wire   [31:0] HADDR_sys;         // Address bus
    wire    [1:0] HTRANS_sys;        // Transfer type
    wire          HWRITE_sys;        // Transfer direction
    wire    [2:0] HSIZE_sys;         // Transfer size
    wire    [2:0] HBURST_sys;        // Burst type
    wire    [3:0] HPROT_sys;         // Protection control
    wire   [31:0] HWDATA_sys;        // Write data
    wire          HMASTLOCK_sys;     // Locked Sequence
    wire          HREADYMUX_sys;     // Transfer done
    wire    [1:0] HAUSER_sys;        // Address USER signals
    wire    [1:0] HWUSER_sys;        // Write-data USER signals
    // Subordinate port MI3 (inputs from slave 3)
    wire   [31:0] HRDATA_sys;        // Read data bus
    wire          HREADYOUT_sys;     // HREADY feedback
    wire          HRESP_sys;         // Transfer response
    wire    [1:0] HRUSER_sys;        // Read-data USER signals

    // Subordinate port MI4 (outputs to slave 4)
    wire          HSEL_ram8;          // Slave Select
    wire   [31:0] HADDR_ram8;         // Address bus
    wire    [1:0] HTRANS_ram8;        // Transfer type
    wire          HWRITE_ram8;        // Transfer direction
    wire    [2:0] HSIZE_ram8;         // Transfer size
    wire    [2:0] HBURST_ram8;        // Burst type
    wire    [3:0] HPROT_ram8;         // Protection control
    wire   [31:0] HWDATA_ram8;        // Write data
    wire          HMASTLOCK_ram8;     // Locked Sequence
    wire          HREADYMUX_ram8;     // Transfer done
    wire    [1:0] HAUSER_ram8;        // Address USER signals
    wire    [1:0] HWUSER_ram8;        // Write-data USER signals
    // Subordinate port MI4 (inputs from slave 4)
    wire   [31:0] HRDATA_ram8;        // Read data bus
    wire          HREADYOUT_ram8;     // HREADY feedback
    wire          HRESP_ram8;         // Transfer response
    wire    [1:0] HRUSER_ram8;        // Read-data USER signals

    // Subordinate   port MI5 (outputs to slave 5)
    wire          HSEL_ram9;          // Slave Select
    wire   [31:0] HADDR_ram9;         // Address bus
    wire    [1:0] HTRANS_ram9;        // Transfer type
    wire          HWRITE_ram9;        // Transfer direction
    wire    [2:0] HSIZE_ram9;         // Transfer size
    wire    [2:0] HBURST_ram9;        // Burst type
    wire    [3:0] HPROT_ram9;         // Protection control
    wire   [31:0] HWDATA_ram9;        // Write data
    wire          HMASTLOCK_ram9;     // Locked Sequence
    wire          HREADYMUX_ram9;     // Transfer done
    wire    [1:0] HAUSER_ram9;        // Address USER signals
    wire    [1:0] HWUSER_ram9;        // Write-data USER signals
    // Subordinate port MI5 (inputs from slave 5)
    wire   [31:0] HRDATA_ram9;        // Read data bus
    wire          HREADYOUT_ram9;     // HREADY feedback
    wire          HRESP_ram9;         // Transfer response
    wire    [1:0] HRUSER_ram9;        // Read-data USER signals

     // Subordinate   port MI6 (outputs to slave 6)
    wire          HSEL_exp;           // Slave Select
    wire   [31:0] HADDR_exp;          // Address bus
    wire    [1:0] HTRANS_exp;         // Transfer type
    wire          HWRITE_exp;         // Transfer direction
    wire    [2:0] HSIZE_exp;          // Transfer size
    wire    [2:0] HBURST_exp;         // Burst type
    wire    [3:0] HPROT_exp;          // Protection control
    wire   [31:0] HWDATA_exp;         // Write data
    wire          HMASTLOCK_exp;      // Locked Sequence
    wire          HREADYMUX_exp;      // Transfer done
    wire    [1:0] HAUSER_exp;         // Address USER signals
    wire    [1:0] HWUSER_exp;         // Write-data USER signals
    // Subordinate port MI5 (inputs from slave 5)
    wire   [31:0] HRDATA_exp;         // Read data bus
    wire          HREADYOUT_exp;      // HREADY feedback
    wire          HRESP_exp;          // Transfer response
    wire    [1:0] HRUSER_exp;         // Read-data USER signals


//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Interconnect matrix
// 4 AHB-lite managers, 7 AHB-lite layer interfaces
//------------------------------------------------------------------------------

// BusMatrix instance
  soclabs_4x7_AhbMatrix_lite
   u_soclabs_4x7_AhbMatrix_lite (
    .HCLK       (HCLK),
    .HRESETn    (HRESETn),
    .REMAP      (REMAP),

    // Input port SI0 signals
    .HADDR_adp       (HADDR_adp),
    .HTRANS_adp      (HTRANS_adp),
    .HWRITE_adp      (HWRITE_adp),
    .HSIZE_adp       (HSIZE_adp),
    .HBURST_adp      (HBURST_adp),
    .HPROT_adp       (HPROT_adp),
    .HWDATA_adp      (HWDATA_adp),
    .HMASTLOCK_adp   (HMASTLOCK_adp),
    .HREADY_adp      (HREADY_adp),
    .HAUSER_adp      (HAUSER_adp),
    .HWUSER_adp      (HWUSER_adp),
    .HRDATA_adp      (HRDATA_adp),
    .HRESP_adp       (HRESP_adp),
    .HRUSER_adp      (HRUSER_adp),

    // Input port SI1 signals
    .HADDR_dma       (HADDR_dma),
    .HTRANS_dma      (HTRANS_dma),
    .HWRITE_dma      (HWRITE_dma),
    .HSIZE_dma       (HSIZE_dma),
    .HBURST_dma      (HBURST_dma),
    .HPROT_dma       (HPROT_dma),
    .HWDATA_dma      (HWDATA_dma),
    .HMASTLOCK_dma   (HMASTLOCK_dma),
    .HREADY_dma      (HREADY_dma),
    .HAUSER_dma      (HAUSER_dma),
    .HWUSER_dma      (HWUSER_dma),
    .HRDATA_dma      (HRDATA_dma),
    .HRESP_dma       (HRESP_dma),
    .HRUSER_dma      (HRUSER_dma),

    // Input port SI2 signals
    .HADDR_dma2      (HADDR_dma2),
    .HTRANS_dma2     (HTRANS_dma2),
    .HWRITE_dma2     (HWRITE_dma2),
    .HSIZE_dma2      (HSIZE_dma2),
    .HBURST_dma2     (HBURST_dma2),
    .HPROT_dma2      (HPROT_dma2),
    .HWDATA_dma2     (HWDATA_dma2),
    .HMASTLOCK_dma2  (HMASTLOCK_dma2),
    .HREADY_dma2     (HREADY_dma2),
    .HAUSER_dma2     (HAUSER_dma2),
    .HWUSER_dma2     (HWUSER_dma2),
    .HRDATA_dma2     (HRDATA_dma2),
    .HRESP_dma2      (HRESP_dma2),
    .HRUSER_dma2     (HRUSER_dma2),

    // Input port SI3 signals
    .HADDR_cpu       (HADDR_cpu),
    .HTRANS_cpu      (HTRANS_cpu),
    .HWRITE_cpu      (HWRITE_cpu),
    .HSIZE_cpu       (HSIZE_cpu),
    .HBURST_cpu      (HBURST_cpu),
    .HPROT_cpu       (HPROT_cpu),
    .HWDATA_cpu      (HWDATA_cpu),
    .HMASTLOCK_cpu   (HMASTLOCK_cpu),
    .HREADY_cpu      (HREADY_cpu),
    .HAUSER_cpu      (HAUSER_cpu),
    .HWUSER_cpu      (HWUSER_cpu),
    .HRDATA_cpu      (HRDATA_cpu),
    .HRESP_cpu       (HRESP_cpu),
    .HRUSER_cpu      (HRUSER_cpu),

    // Output port MI0 signals
    .HSEL_rom1       (HSEL_rom1),
    .HADDR_rom1      (HADDR_rom1),
    .HTRANS_rom1     (HTRANS_rom1),
    .HWRITE_rom1     (HWRITE_rom1),
    .HSIZE_rom1      (HSIZE_rom1),
    .HBURST_rom1     (HBURST_rom1),
    .HPROT_rom1      (HPROT_rom1),
    .HWDATA_rom1     (HWDATA_rom1),
    .HMASTLOCK_rom1  (HMASTLOCK_rom1),
    .HREADYMUX_rom1  (HREADYMUX_rom1),
    .HAUSER_rom1     (HAUSER_rom1),
    .HWUSER_rom1     (HWUSER_rom1),
    .HRDATA_rom1     (HRDATA_rom1),
    .HREADYOUT_rom1  (HREADYOUT_rom1),
    .HRESP_rom1      (HRESP_rom1),
    .HRUSER_rom1     (HRUSER_rom1),

    // Output port MI1 signals
    .HSEL_ram2       (HSEL_ram2),
    .HADDR_ram2      (HADDR_ram2),
    .HTRANS_ram2     (HTRANS_ram2),
    .HWRITE_ram2     (HWRITE_ram2),
    .HSIZE_ram2      (HSIZE_ram2),
    .HBURST_ram2     (HBURST_ram2),
    .HPROT_ram2      (HPROT_ram2),
    .HWDATA_ram2     (HWDATA_ram2),
    .HMASTLOCK_ram2  (HMASTLOCK_ram2),
    .HREADYMUX_ram2  (HREADYMUX_ram2),
    .HAUSER_ram2     (HAUSER_ram2),
    .HWUSER_ram2     (HWUSER_ram2),
    .HRDATA_ram2     (HRDATA_ram2),
    .HREADYOUT_ram2  (HREADYOUT_ram2),
    .HRESP_ram2      (HRESP_ram2),
    .HRUSER_ram2     (HRUSER_ram2),

    // Output port MI2 signals
    .HSEL_ram3       (HSEL_ram3),
    .HADDR_ram3      (HADDR_ram3),
    .HTRANS_ram3     (HTRANS_ram3),
    .HWRITE_ram3     (HWRITE_ram3),
    .HSIZE_ram3      (HSIZE_ram3),
    .HBURST_ram3     (HBURST_ram3),
    .HPROT_ram3      (HPROT_ram3),
    .HWDATA_ram3     (HWDATA_ram3),
    .HMASTLOCK_ram3  (HMASTLOCK_ram3),
    .HREADYMUX_ram3  (HREADYMUX_ram3),
    .HAUSER_ram3     (HAUSER_ram3),
    .HWUSER_ram3     (HWUSER_ram3),
    .HRDATA_ram3     (HRDATA_ram3),
    .HREADYOUT_ram3  (HREADYOUT_ram3),
    .HRESP_ram3      (HRESP_ram3),
    .HRUSER_ram3     (HRUSER_ram3),

    // Output port MI3 signals
    .HSEL_sys        (HSEL_sys),
    .HADDR_sys       (HADDR_sys),
    .HTRANS_sys      (HTRANS_sys),
    .HWRITE_sys      (HWRITE_sys),
    .HSIZE_sys       (HSIZE_sys),
    .HBURST_sys      (HBURST_sys),
    .HPROT_sys       (HPROT_sys),
    .HWDATA_sys      (HWDATA_sys),
    .HMASTLOCK_sys   (HMASTLOCK_sys),
    .HREADYMUX_sys   (HREADYMUX_sys),
    .HAUSER_sys      (HAUSER_sys),
    .HWUSER_sys      (HWUSER_sys),
    .HRDATA_sys      (HRDATA_sys),
    .HREADYOUT_sys   (HREADYOUT_sys),
    .HRESP_sys       (HRESP_sys),
    .HRUSER_sys      (HRUSER_sys),

    // Output port MI4 signals
    .HSEL_ram8       (HSEL_ram8),
    .HADDR_ram8      (HADDR_ram8),
    .HTRANS_ram8     (HTRANS_ram8),
    .HWRITE_ram8     (HWRITE_ram8),
    .HSIZE_ram8      (HSIZE_ram8),
    .HBURST_ram8     (HBURST_ram8),
    .HPROT_ram8      (HPROT_ram8),
    .HWDATA_ram8     (HWDATA_ram8),
    .HMASTLOCK_ram8  (HMASTLOCK_ram8),
    .HREADYMUX_ram8  (HREADYMUX_ram8),
    .HAUSER_ram8     (HAUSER_ram8),
    .HWUSER_ram8     (HWUSER_ram8),
    .HRDATA_ram8     (HRDATA_ram8),
    .HREADYOUT_ram8  (HREADYOUT_ram8),
    .HRESP_ram8      (HRESP_ram8),
    .HRUSER_ram8     (HRUSER_ram8),

    // Output port MI5 signals
    .HSEL_ram9       (HSEL_ram9),
    .HADDR_ram9      (HADDR_ram9),
    .HTRANS_ram9     (HTRANS_ram9),
    .HWRITE_ram9     (HWRITE_ram9),
    .HSIZE_ram9      (HSIZE_ram9),
    .HBURST_ram9     (HBURST_ram9),
    .HPROT_ram9      (HPROT_ram9),
    .HWDATA_ram9     (HWDATA_ram9),
    .HMASTLOCK_ram9  (HMASTLOCK_ram9),
    .HREADYMUX_ram9  (HREADYMUX_ram9),
    .HAUSER_ram9     (HAUSER_ram9),
    .HWUSER_ram9     (HWUSER_ram9),
    .HRDATA_ram9     (HRDATA_ram9),
    .HREADYOUT_ram9  (HREADYOUT_ram9),
    .HRESP_ram9      (HRESP_ram9),
    .HRUSER_ram9     (HRUSER_ram9),

    // Output port MI6 signals
    .HSEL_exp        (HSEL_exp),
    .HADDR_exp       (HADDR_exp),
    .HTRANS_exp      (HTRANS_exp),
    .HWRITE_exp      (HWRITE_exp),
    .HSIZE_exp       (HSIZE_exp),
    .HBURST_exp      (HBURST_exp),
    .HPROT_exp       (HPROT_exp),
    .HWDATA_exp      (HWDATA_exp),
    .HMASTLOCK_exp   (HMASTLOCK_exp),
    .HREADYMUX_exp   (HREADYMUX_exp),
    .HAUSER_exp      (HAUSER_exp),
    .HWUSER_exp      (HWUSER_exp),
    .HRDATA_exp      (HRDATA_exp),
    .HREADYOUT_exp   (HREADYOUT_exp),
    .HRESP_exp       (HRESP_exp),
    .HRUSER_exp      (HRUSER_exp),

    // Scan test dummy signals; not connected until scan insertion
    .SCANENABLE      (SCANENABLE),
    .SCANINHCLK      (SCANINHCLK),
    .SCANOUTHCLK     (SCANOUTHCLK)
  );


//----------------------------------------
// Boot ROM "rom1" firmware
// mapped 0x10000000-0x1fffffff
// and on REMAP[0]
// mapped 0x00000000-0x0000ffff
//----------------------------------------

ahb_bootrom
//  #(.AW(10)  ) // 1K bytes ROM
   u_ahb_bootloader (
    .HCLK             (HCLK),
    .HRESETn          (HRESETn),
    .HSEL             (HSEL_rom1),
    .HADDR            (HADDR_rom1[ 9:0]),
    .HTRANS           (HTRANS_rom1),
    .HSIZE            (HSIZE_rom1),
    .HWRITE           (HWRITE_rom1),
    .HWDATA           (HWDATA_rom1),
    .HREADY           (HREADYMUX_rom1),
    .HREADYOUT        (HREADYOUT_rom1),
    .HRDATA           (HRDATA_rom1),
    .HRESP            (HRESP_rom1)
  );

//----------------------------------------
// CODE/DATA "ram2"
// mapped 0x20000000-0x2fffffff
//----------------------------------------

//localparam AWRAM2 = 9; // 512B
//localparam AWRAM2 = 10; // 1024B
localparam AWRAM2 = 14; // 16KB
//localparam AWRAM2 = 16; // 64KB
  wire  [AWRAM2-3:0] addr_ram2;
  wire    [31:0] wdata_ram2;
  wire    [31:0] rdata_ram2;
  wire     [3:0] wen_ram2;
  wire           cs_ram2;

  // AHB to SRAM bridge
  cmsdk_ahb_to_sram #(.AW(AWRAM2)) u_ahb_to_sram2
  (
    // AHB Inputs
    .HCLK       (HCLK),
    .HRESETn    (HRESETn),
    .HSEL       (HSEL_ram2),  // AHB inputs
    .HADDR      (HADDR_ram2[AWRAM2-1:0]),
    .HTRANS     (HTRANS_ram2),
    .HSIZE      (HSIZE_ram2),
    .HWRITE     (HWRITE_ram2),
    .HWDATA     (HWDATA_ram2),
    .HREADY     (HREADYMUX_ram2),

    // AHB Outputs
    .HREADYOUT  (HREADYOUT_ram2), // Outputs
    .HRDATA     (HRDATA_ram2),
    .HRESP      (HRESP_ram2),

   // SRAM input
    .SRAMRDATA  (rdata_ram2),
   // SRAM Outputs
    .SRAMADDR   (addr_ram2),
    .SRAMWDATA  (wdata_ram2),
    .SRAMWEN    (wen_ram2),
    .SRAMCS     (cs_ram2)
   );

  // SRAM model
//  cmsdk_fpga_sram #(.AW(AWRAM2)) u_fpga_ram2
  cmsdk_fpga_rom #(.AW(AWRAM2), .filename("../rtl_sim/image.hex") ) u_fpga_ram2
   (
   // SRAM Inputs
    .CLK        (HCLK),
    .ADDR       (addr_ram2),
    .WDATA      (wdata_ram2),
    .WREN       (wen_ram2),
    .CS         (cs_ram2),
   // SRAM Output
    .RDATA      (rdata_ram2)
   );


//----------------------------------------
// DATA "ram3" 
// mapped 0x30000000-0x3fffffff
//----------------------------------------

//localparam AWRAM3 = 9; // 512B
//localparam AWRAM3 = 10; // 1024B
localparam AWRAM3 = 14; // 16KB
//localparam AWRAM3 = 16; // 64KB
  wire  [AWRAM3-3:0] addr_ram3;
  wire    [31:0] wdata_ram3;
  wire    [31:0] rdata_ram3;
  wire     [3:0] wen_ram3;
  wire           cs_ram3;

  // AHB to SRAM bridge
  cmsdk_ahb_to_sram #(.AW(AWRAM3)) u_ahb_to_sram3
  (
    // AHB Inputs
    .HCLK       (HCLK),
    .HRESETn    (HRESETn),
    .HSEL       (HSEL_ram3),  // AHB inputs
    .HADDR      (HADDR_ram3[AWRAM3-1:0]),
    .HTRANS     (HTRANS_ram3),
    .HSIZE      (HSIZE_ram3),
    .HWRITE     (HWRITE_ram3),
    .HWDATA     (HWDATA_ram3),
    .HREADY     (HREADYMUX_ram3),

    // AHB Outputs
    .HREADYOUT  (HREADYOUT_ram3), // Outputs
    .HRDATA     (HRDATA_ram3),
    .HRESP      (HRESP_ram3),

   // SRAM input
    .SRAMRDATA  (rdata_ram3),
   // SRAM Outputs
    .SRAMADDR   (addr_ram3),
    .SRAMWDATA  (wdata_ram3),
    .SRAMWEN    (wen_ram3),
    .SRAMCS     (cs_ram3)
   );

  // SRAM model
  cmsdk_fpga_sram #(.AW(AWRAM3)) u_fpga_ram3
   (
   // SRAM Inputs
    .CLK        (HCLK),
    .ADDR       (addr_ram3),
    .WDATA      (wdata_ram3),
    .WREN       (wen_ram3),
    .CS         (cs_ram3),
   // SRAM Output
    .RDATA      (rdata_ram3)
   );

//----------------------------------------
// Expansion/DMA "ram8,ram9" RAM instances
//----------------------------------------

//localparam AWRAM8 = 9; // 512B
//localparam AWRAM8 = 10; // 1024B
localparam AWRAM8 = 14; // 16KB
//localparam AWRAM8 = 16; // 64KB
  wire  [AWRAM8-3:0] addr_ram8;
  wire    [31:0] wdata_ram8;
  wire    [31:0] rdata_ram8;
  wire     [3:0] wen_ram8;
  wire           cs_ram8;

  // AHB to SRAM bridge
  cmsdk_ahb_to_sram #(.AW(AWRAM8)) u_ahb_to_sram8
  (
    // AHB Inputs
    .HCLK       (HCLK),
    .HRESETn    (HRESETn),
    .HSEL       (HSEL_ram8),  // AHB inputs
    .HADDR      (HADDR_ram8[AWRAM8-1:0]),
    .HTRANS     (HTRANS_ram8),
    .HSIZE      (HSIZE_ram8),
    .HWRITE     (HWRITE_ram8),
    .HWDATA     (HWDATA_ram8),
    .HREADY     (HREADYMUX_ram8),

    // AHB Outputs
    .HREADYOUT  (HREADYOUT_ram8), // Outputs
    .HRDATA     (HRDATA_ram8),
    .HRESP      (HRESP_ram8),

   // SRAM input
    .SRAMRDATA  (rdata_ram8),
   // SRAM Outputs
    .SRAMADDR   (addr_ram8),
    .SRAMWDATA  (wdata_ram8),
    .SRAMWEN    (wen_ram8),
    .SRAMCS     (cs_ram8)
   );

  // SRAM model
  cmsdk_fpga_sram #(.AW(AWRAM8)) u_fpga_ram8
   (
   // SRAM Inputs
    .CLK        (HCLK),
    .ADDR       (addr_ram8),
    .WDATA      (wdata_ram8),
    .WREN       (wen_ram8),
    .CS         (cs_ram8),
Next12
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