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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
//            (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
//      SVN Information
//
//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
//      Revision            : $Revision: 371321 $
//
//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
//  Abstract            : BusMatrix is the top-level which connects together
//                        the required Input Stages, MatrixDecodes, Output
//                        Stages and Output Arbitration blocks.
//
//                        Supports the following configured options:
//
//                         - Architecture type 'ahb2',
//                         - 4 slave ports (connecting to masters),
//                         - 7 master ports (connecting to slaves),
//                         - Routing address width of 32 bits,
//                         - Routing data width of 32 bits,
//                         - xUSER signal width of 2 bits,
//                         - Arbiter type 'burst',
//                         - Connectivity mapping:
//                             S<0..3> -> M<0..6>,
//                         - Connectivity type 'full'.
//
//------------------------------------------------------------------------------


`timescale 1ns/1ps


[Up: soclabs_4x7_AhbMatrix_lite usoclabs_4x7_AhbMatrix]
module soclabs_4x7_AhbMatrixIndex (

    // Common AHB signals
    HCLK,
    HRESETn,

    // System address remapping control
    REMAP,

    // Input port SI0 (inputs from master 0)
    HSEL_adp,
    HADDR_adp,
    HTRANS_adp,
    HWRITE_adp,
    HSIZE_adp,
    HBURST_adp,
    HPROT_adp,
    HMASTER_adp,
    HWDATA_adp,
    HMASTLOCK_adp,
    HREADY_adp,
    HAUSER_adp,
    HWUSER_adp,

    // Input port SI1 (inputs from master 1)
    HSEL_dma,
    HADDR_dma,
    HTRANS_dma,
    HWRITE_dma,
    HSIZE_dma,
    HBURST_dma,
    HPROT_dma,
    HMASTER_dma,
    HWDATA_dma,
    HMASTLOCK_dma,
    HREADY_dma,
    HAUSER_dma,
    HWUSER_dma,

    // Input port SI2 (inputs from master 2)
    HSEL_dma2,
    HADDR_dma2,
    HTRANS_dma2,
    HWRITE_dma2,
    HSIZE_dma2,
    HBURST_dma2,
    HPROT_dma2,
    HMASTER_dma2,
    HWDATA_dma2,
    HMASTLOCK_dma2,
    HREADY_dma2,
    HAUSER_dma2,
    HWUSER_dma2,

    // Input port SI3 (inputs from master 3)
    HSEL_cpu,
    HADDR_cpu,
    HTRANS_cpu,
    HWRITE_cpu,
    HSIZE_cpu,
    HBURST_cpu,
    HPROT_cpu,
    HMASTER_cpu,
    HWDATA_cpu,
    HMASTLOCK_cpu,
    HREADY_cpu,
    HAUSER_cpu,
    HWUSER_cpu,

    // Output port MI0 (inputs from slave 0)
    HRDATA_rom1,
    HREADYOUT_rom1,
    HRESP_rom1,
    HRUSER_rom1,

    // Output port MI1 (inputs from slave 1)
    HRDATA_ram2,
    HREADYOUT_ram2,
    HRESP_ram2,
    HRUSER_ram2,

    // Output port MI2 (inputs from slave 2)
    HRDATA_ram3,
    HREADYOUT_ram3,
    HRESP_ram3,
    HRUSER_ram3,

    // Output port MI3 (inputs from slave 3)
    HRDATA_sys,
    HREADYOUT_sys,
    HRESP_sys,
    HRUSER_sys,

    // Output port MI4 (inputs from slave 4)
    HRDATA_ram8,
    HREADYOUT_ram8,
    HRESP_ram8,
    HRUSER_ram8,

    // Output port MI5 (inputs from slave 5)
    HRDATA_ram9,
    HREADYOUT_ram9,
    HRESP_ram9,
    HRUSER_ram9,

    // Output port MI6 (inputs from slave 6)
    HRDATA_exp,
    HREADYOUT_exp,
    HRESP_exp,
    HRUSER_exp,

    // Scan test dummy signals; not connected until scan insertion
    SCANENABLE,   // Scan Test Mode Enable
    SCANINHCLK,   // Scan Chain Input


    // Output port MI0 (outputs to slave 0)
    HSEL_rom1,
    HADDR_rom1,
    HTRANS_rom1,
    HWRITE_rom1,
    HSIZE_rom1,
    HBURST_rom1,
    HPROT_rom1,
    HMASTER_rom1,
    HWDATA_rom1,
    HMASTLOCK_rom1,
    HREADYMUX_rom1,
    HAUSER_rom1,
    HWUSER_rom1,

    // Output port MI1 (outputs to slave 1)
    HSEL_ram2,
    HADDR_ram2,
    HTRANS_ram2,
    HWRITE_ram2,
    HSIZE_ram2,
    HBURST_ram2,
    HPROT_ram2,
    HMASTER_ram2,
    HWDATA_ram2,
    HMASTLOCK_ram2,
    HREADYMUX_ram2,
    HAUSER_ram2,
    HWUSER_ram2,

    // Output port MI2 (outputs to slave 2)
    HSEL_ram3,
    HADDR_ram3,
    HTRANS_ram3,
    HWRITE_ram3,
    HSIZE_ram3,
    HBURST_ram3,
    HPROT_ram3,
    HMASTER_ram3,
    HWDATA_ram3,
    HMASTLOCK_ram3,
    HREADYMUX_ram3,
    HAUSER_ram3,
    HWUSER_ram3,

    // Output port MI3 (outputs to slave 3)
    HSEL_sys,
    HADDR_sys,
    HTRANS_sys,
    HWRITE_sys,
    HSIZE_sys,
    HBURST_sys,
    HPROT_sys,
    HMASTER_sys,
    HWDATA_sys,
    HMASTLOCK_sys,
    HREADYMUX_sys,
    HAUSER_sys,
    HWUSER_sys,

    // Output port MI4 (outputs to slave 4)
    HSEL_ram8,
    HADDR_ram8,
    HTRANS_ram8,
    HWRITE_ram8,
    HSIZE_ram8,
    HBURST_ram8,
    HPROT_ram8,
    HMASTER_ram8,
    HWDATA_ram8,
    HMASTLOCK_ram8,
    HREADYMUX_ram8,
    HAUSER_ram8,
    HWUSER_ram8,

    // Output port MI5 (outputs to slave 5)
    HSEL_ram9,
    HADDR_ram9,
    HTRANS_ram9,
    HWRITE_ram9,
    HSIZE_ram9,
    HBURST_ram9,
    HPROT_ram9,
    HMASTER_ram9,
    HWDATA_ram9,
    HMASTLOCK_ram9,
    HREADYMUX_ram9,
    HAUSER_ram9,
    HWUSER_ram9,

    // Output port MI6 (outputs to slave 6)
    HSEL_exp,
    HADDR_exp,
    HTRANS_exp,
    HWRITE_exp,
    HSIZE_exp,
    HBURST_exp,
    HPROT_exp,
    HMASTER_exp,
    HWDATA_exp,
    HMASTLOCK_exp,
    HREADYMUX_exp,
    HAUSER_exp,
    HWUSER_exp,

    // Input port SI0 (outputs to master 0)
    HRDATA_adp,
    HREADYOUT_adp,
    HRESP_adp,
    HRUSER_adp,

    // Input port SI1 (outputs to master 1)
    HRDATA_dma,
    HREADYOUT_dma,
    HRESP_dma,
    HRUSER_dma,

    // Input port SI2 (outputs to master 2)
    HRDATA_dma2,
    HREADYOUT_dma2,
    HRESP_dma2,
    HRUSER_dma2,

    // Input port SI3 (outputs to master 3)
    HRDATA_cpu,
    HREADYOUT_cpu,
    HRESP_cpu,
    HRUSER_cpu,

    // Scan test dummy signals; not connected until scan insertion
    SCANOUTHCLK   // Scan Chain Output

    );


// -----------------------------------------------------------------------------
// Input and Output declarations
// -----------------------------------------------------------------------------

    // Common AHB signals
    input         HCLK;            // AHB System Clock
    input         HRESETn;         // AHB System Reset

    // System address remapping control
    input   [3:0] REMAP;           // REMAP input

    // Input port SI0 (inputs from master 0)
    input         HSEL_adp;          // Slave Select
    input  [31:0] HADDR_adp;         // Address bus
    input   [1:0] HTRANS_adp;        // Transfer type
    input         HWRITE_adp;        // Transfer direction
    input   [2:0] HSIZE_adp;         // Transfer size
    input   [2:0] HBURST_adp;        // Burst type
    input   [3:0] HPROT_adp;         // Protection control
    input   [3:0] HMASTER_adp;       // Master select
    input  [31:0] HWDATA_adp;        // Write data
    input         HMASTLOCK_adp;     // Locked Sequence
    input         HREADY_adp;        // Transfer done
    input  [1:0] HAUSER_adp;        // Address USER signals
    input  [1:0] HWUSER_adp;        // Write-data USER signals

    // Input port SI1 (inputs from master 1)
    input         HSEL_dma;          // Slave Select
    input  [31:0] HADDR_dma;         // Address bus
    input   [1:0] HTRANS_dma;        // Transfer type
    input         HWRITE_dma;        // Transfer direction
    input   [2:0] HSIZE_dma;         // Transfer size
    input   [2:0] HBURST_dma;        // Burst type
    input   [3:0] HPROT_dma;         // Protection control
    input   [3:0] HMASTER_dma;       // Master select
    input  [31:0] HWDATA_dma;        // Write data
    input         HMASTLOCK_dma;     // Locked Sequence
    input         HREADY_dma;        // Transfer done
    input  [1:0] HAUSER_dma;        // Address USER signals
    input  [1:0] HWUSER_dma;        // Write-data USER signals

    // Input port SI2 (inputs from master 2)
    input         HSEL_dma2;          // Slave Select
    input  [31:0] HADDR_dma2;         // Address bus
    input   [1:0] HTRANS_dma2;        // Transfer type
    input         HWRITE_dma2;        // Transfer direction
    input   [2:0] HSIZE_dma2;         // Transfer size
    input   [2:0] HBURST_dma2;        // Burst type
    input   [3:0] HPROT_dma2;         // Protection control
    input   [3:0] HMASTER_dma2;       // Master select
    input  [31:0] HWDATA_dma2;        // Write data
    input         HMASTLOCK_dma2;     // Locked Sequence
    input         HREADY_dma2;        // Transfer done
    input  [1:0] HAUSER_dma2;        // Address USER signals
    input  [1:0] HWUSER_dma2;        // Write-data USER signals

    // Input port SI3 (inputs from master 3)
    input         HSEL_cpu;          // Slave Select
    input  [31:0] HADDR_cpu;         // Address bus
    input   [1:0] HTRANS_cpu;        // Transfer type
    input         HWRITE_cpu;        // Transfer direction
    input   [2:0] HSIZE_cpu;         // Transfer size
    input   [2:0] HBURST_cpu;        // Burst type
    input   [3:0] HPROT_cpu;         // Protection control
    input   [3:0] HMASTER_cpu;       // Master select
    input  [31:0] HWDATA_cpu;        // Write data
    input         HMASTLOCK_cpu;     // Locked Sequence
    input         HREADY_cpu;        // Transfer done
    input  [1:0] HAUSER_cpu;        // Address USER signals
    input  [1:0] HWUSER_cpu;        // Write-data USER signals

    // Output port MI0 (inputs from slave 0)
    input  [31:0] HRDATA_rom1;        // Read data bus
    input         HREADYOUT_rom1;     // HREADY feedback
    input   [1:0] HRESP_rom1;         // Transfer response
    input  [1:0] HRUSER_rom1;        // Read-data USER signals

    // Output port MI1 (inputs from slave 1)
    input  [31:0] HRDATA_ram2;        // Read data bus
    input         HREADYOUT_ram2;     // HREADY feedback
    input   [1:0] HRESP_ram2;         // Transfer response
    input  [1:0] HRUSER_ram2;        // Read-data USER signals

    // Output port MI2 (inputs from slave 2)
    input  [31:0] HRDATA_ram3;        // Read data bus
    input         HREADYOUT_ram3;     // HREADY feedback
    input   [1:0] HRESP_ram3;         // Transfer response
    input  [1:0] HRUSER_ram3;        // Read-data USER signals

    // Output port MI3 (inputs from slave 3)
    input  [31:0] HRDATA_sys;        // Read data bus
    input         HREADYOUT_sys;     // HREADY feedback
    input   [1:0] HRESP_sys;         // Transfer response
    input  [1:0] HRUSER_sys;        // Read-data USER signals

    // Output port MI4 (inputs from slave 4)
    input  [31:0] HRDATA_ram8;        // Read data bus
    input         HREADYOUT_ram8;     // HREADY feedback
    input   [1:0] HRESP_ram8;         // Transfer response
    input  [1:0] HRUSER_ram8;        // Read-data USER signals

    // Output port MI5 (inputs from slave 5)
    input  [31:0] HRDATA_ram9;        // Read data bus
    input         HREADYOUT_ram9;     // HREADY feedback
    input   [1:0] HRESP_ram9;         // Transfer response
    input  [1:0] HRUSER_ram9;        // Read-data USER signals

    // Output port MI6 (inputs from slave 6)
    input  [31:0] HRDATA_exp;        // Read data bus
    input         HREADYOUT_exp;     // HREADY feedback
    input   [1:0] HRESP_exp;         // Transfer response
    input  [1:0] HRUSER_exp;        // Read-data USER signals

    // Scan test dummy signals; not connected until scan insertion
    input         SCANENABLE;      // Scan enable signal
    input         SCANINHCLK;      // HCLK scan input


    // Output port MI0 (outputs to slave 0)
    output        HSEL_rom1;          // Slave Select
    output [31:0] HADDR_rom1;         // Address bus
    output  [1:0] HTRANS_rom1;        // Transfer type
    output        HWRITE_rom1;        // Transfer direction
    output  [2:0] HSIZE_rom1;         // Transfer size
    output  [2:0] HBURST_rom1;        // Burst type
    output  [3:0] HPROT_rom1;         // Protection control
    output  [3:0] HMASTER_rom1;       // Master select
    output [31:0] HWDATA_rom1;        // Write data
    output        HMASTLOCK_rom1;     // Locked Sequence
    output        HREADYMUX_rom1;     // Transfer done
    output [1:0] HAUSER_rom1;        // Address USER signals
    output [1:0] HWUSER_rom1;        // Write-data USER signals

    // Output port MI1 (outputs to slave 1)
    output        HSEL_ram2;          // Slave Select
    output [31:0] HADDR_ram2;         // Address bus
    output  [1:0] HTRANS_ram2;        // Transfer type
    output        HWRITE_ram2;        // Transfer direction
    output  [2:0] HSIZE_ram2;         // Transfer size
    output  [2:0] HBURST_ram2;        // Burst type
    output  [3:0] HPROT_ram2;         // Protection control
    output  [3:0] HMASTER_ram2;       // Master select
    output [31:0] HWDATA_ram2;        // Write data
    output        HMASTLOCK_ram2;     // Locked Sequence
    output        HREADYMUX_ram2;     // Transfer done
    output [1:0] HAUSER_ram2;        // Address USER signals
    output [1:0] HWUSER_ram2;        // Write-data USER signals

    // Output port MI2 (outputs to slave 2)
    output        HSEL_ram3;          // Slave Select
    output [31:0] HADDR_ram3;         // Address bus
    output  [1:0] HTRANS_ram3;        // Transfer type
    output        HWRITE_ram3;        // Transfer direction
    output  [2:0] HSIZE_ram3;         // Transfer size
    output  [2:0] HBURST_ram3;        // Burst type
    output  [3:0] HPROT_ram3;         // Protection control
    output  [3:0] HMASTER_ram3;       // Master select
    output [31:0] HWDATA_ram3;        // Write data
    output        HMASTLOCK_ram3;     // Locked Sequence
    output        HREADYMUX_ram3;     // Transfer done
    output [1:0] HAUSER_ram3;        // Address USER signals
    output [1:0] HWUSER_ram3;        // Write-data USER signals

    // Output port MI3 (outputs to slave 3)
    output        HSEL_sys;          // Slave Select
    output [31:0] HADDR_sys;         // Address bus
    output  [1:0] HTRANS_sys;        // Transfer type
    output        HWRITE_sys;        // Transfer direction
    output  [2:0] HSIZE_sys;         // Transfer size
    output  [2:0] HBURST_sys;        // Burst type
    output  [3:0] HPROT_sys;         // Protection control
    output  [3:0] HMASTER_sys;       // Master select
    output [31:0] HWDATA_sys;        // Write data
    output        HMASTLOCK_sys;     // Locked Sequence
    output        HREADYMUX_sys;     // Transfer done
    output [1:0] HAUSER_sys;        // Address USER signals
    output [1:0] HWUSER_sys;        // Write-data USER signals

    // Output port MI4 (outputs to slave 4)
    output        HSEL_ram8;          // Slave Select
    output [31:0] HADDR_ram8;         // Address bus
    output  [1:0] HTRANS_ram8;        // Transfer type
    output        HWRITE_ram8;        // Transfer direction
    output  [2:0] HSIZE_ram8;         // Transfer size
    output  [2:0] HBURST_ram8;        // Burst type
    output  [3:0] HPROT_ram8;         // Protection control
    output  [3:0] HMASTER_ram8;       // Master select
    output [31:0] HWDATA_ram8;        // Write data
    output        HMASTLOCK_ram8;     // Locked Sequence
    output        HREADYMUX_ram8;     // Transfer done
    output [1:0] HAUSER_ram8;        // Address USER signals
    output [1:0] HWUSER_ram8;        // Write-data USER signals

    // Output port MI5 (outputs to slave 5)
    output        HSEL_ram9;          // Slave Select
    output [31:0] HADDR_ram9;         // Address bus
    output  [1:0] HTRANS_ram9;        // Transfer type
    output        HWRITE_ram9;        // Transfer direction
    output  [2:0] HSIZE_ram9;         // Transfer size
    output  [2:0] HBURST_ram9;        // Burst type
    output  [3:0] HPROT_ram9;         // Protection control
    output  [3:0] HMASTER_ram9;       // Master select
    output [31:0] HWDATA_ram9;        // Write data
    output        HMASTLOCK_ram9;     // Locked Sequence
    output        HREADYMUX_ram9;     // Transfer done
    output [1:0] HAUSER_ram9;        // Address USER signals
    output [1:0] HWUSER_ram9;        // Write-data USER signals

    // Output port MI6 (outputs to slave 6)
    output        HSEL_exp;          // Slave Select
    output [31:0] HADDR_exp;         // Address bus
    output  [1:0] HTRANS_exp;        // Transfer type
    output        HWRITE_exp;        // Transfer direction
    output  [2:0] HSIZE_exp;         // Transfer size
    output  [2:0] HBURST_exp;        // Burst type
    output  [3:0] HPROT_exp;         // Protection control
    output  [3:0] HMASTER_exp;       // Master select
    output [31:0] HWDATA_exp;        // Write data
    output        HMASTLOCK_exp;     // Locked Sequence
    output        HREADYMUX_exp;     // Transfer done
    output [1:0] HAUSER_exp;        // Address USER signals
    output [1:0] HWUSER_exp;        // Write-data USER signals

    // Input port SI0 (outputs to master 0)
    output [31:0] HRDATA_adp;        // Read data bus
    output        HREADYOUT_adp;     // HREADY feedback
    output  [1:0] HRESP_adp;         // Transfer response
    output [1:0] HRUSER_adp;        // Read-data USER signals

    // Input port SI1 (outputs to master 1)
    output [31:0] HRDATA_dma;        // Read data bus
    output        HREADYOUT_dma;     // HREADY feedback
    output  [1:0] HRESP_dma;         // Transfer response
    output [1:0] HRUSER_dma;        // Read-data USER signals

    // Input port SI2 (outputs to master 2)
    output [31:0] HRDATA_dma2;        // Read data bus
    output        HREADYOUT_dma2;     // HREADY feedback
    output  [1:0] HRESP_dma2;         // Transfer response
    output [1:0] HRUSER_dma2;        // Read-data USER signals

    // Input port SI3 (outputs to master 3)
    output [31:0] HRDATA_cpu;        // Read data bus
    output        HREADYOUT_cpu;     // HREADY feedback
    output  [1:0] HRESP_cpu;         // Transfer response
    output [1:0] HRUSER_cpu;        // Read-data USER signals

    // Scan test dummy signals; not connected until scan insertion
    output        SCANOUTHCLK;     // Scan Chain Output


// -----------------------------------------------------------------------------
// Wire declarations
// -----------------------------------------------------------------------------

    // Common AHB signals
    wire         HCLK;            // AHB System Clock
    wire         HRESETn;         // AHB System Reset

    // System address remapping control
    wire   [3:0] REMAP;           // REMAP signal

    // Input Port SI0
    wire         HSEL_adp;          // Slave Select
    wire  [31:0] HADDR_adp;         // Address bus
    wire   [1:0] HTRANS_adp;        // Transfer type
    wire         HWRITE_adp;        // Transfer direction
    wire   [2:0] HSIZE_adp;         // Transfer size
    wire   [2:0] HBURST_adp;        // Burst type
    wire   [3:0] HPROT_adp;         // Protection control
    wire   [3:0] HMASTER_adp;       // Master select
    wire  [31:0] HWDATA_adp;        // Write data
    wire         HMASTLOCK_adp;     // Locked Sequence
    wire         HREADY_adp;        // Transfer done

    wire  [31:0] HRDATA_adp;        // Read data bus
    wire         HREADYOUT_adp;     // HREADY feedback
    wire   [1:0] HRESP_adp;         // Transfer response
    wire  [1:0] HAUSER_adp;        // Address USER signals
    wire  [1:0] HWUSER_adp;        // Write-data USER signals
    wire  [1:0] HRUSER_adp;        // Read-data USER signals

    // Input Port SI1
    wire         HSEL_dma;          // Slave Select
    wire  [31:0] HADDR_dma;         // Address bus
    wire   [1:0] HTRANS_dma;        // Transfer type
    wire         HWRITE_dma;        // Transfer direction
    wire   [2:0] HSIZE_dma;         // Transfer size
    wire   [2:0] HBURST_dma;        // Burst type
    wire   [3:0] HPROT_dma;         // Protection control
    wire   [3:0] HMASTER_dma;       // Master select
    wire  [31:0] HWDATA_dma;        // Write data
    wire         HMASTLOCK_dma;     // Locked Sequence
    wire         HREADY_dma;        // Transfer done

    wire  [31:0] HRDATA_dma;        // Read data bus
    wire         HREADYOUT_dma;     // HREADY feedback
    wire   [1:0] HRESP_dma;         // Transfer response
    wire  [1:0] HAUSER_dma;        // Address USER signals
    wire  [1:0] HWUSER_dma;        // Write-data USER signals
    wire  [1:0] HRUSER_dma;        // Read-data USER signals

    // Input Port SI2
    wire         HSEL_dma2;          // Slave Select
    wire  [31:0] HADDR_dma2;         // Address bus
    wire   [1:0] HTRANS_dma2;        // Transfer type
    wire         HWRITE_dma2;        // Transfer direction
    wire   [2:0] HSIZE_dma2;         // Transfer size
    wire   [2:0] HBURST_dma2;        // Burst type
    wire   [3:0] HPROT_dma2;         // Protection control
    wire   [3:0] HMASTER_dma2;       // Master select
    wire  [31:0] HWDATA_dma2;        // Write data
    wire         HMASTLOCK_dma2;     // Locked Sequence
    wire         HREADY_dma2;        // Transfer done

    wire  [31:0] HRDATA_dma2;        // Read data bus
    wire         HREADYOUT_dma2;     // HREADY feedback
    wire   [1:0] HRESP_dma2;         // Transfer response
    wire  [1:0] HAUSER_dma2;        // Address USER signals
    wire  [1:0] HWUSER_dma2;        // Write-data USER signals
    wire  [1:0] HRUSER_dma2;        // Read-data USER signals

    // Input Port SI3
    wire         HSEL_cpu;          // Slave Select
    wire  [31:0] HADDR_cpu;         // Address bus
    wire   [1:0] HTRANS_cpu;        // Transfer type
    wire         HWRITE_cpu;        // Transfer direction
    wire   [2:0] HSIZE_cpu;         // Transfer size
    wire   [2:0] HBURST_cpu;        // Burst type
    wire   [3:0] HPROT_cpu;         // Protection control
    wire   [3:0] HMASTER_cpu;       // Master select
    wire  [31:0] HWDATA_cpu;        // Write data
    wire         HMASTLOCK_cpu;     // Locked Sequence
    wire         HREADY_cpu;        // Transfer done

    wire  [31:0] HRDATA_cpu;        // Read data bus
    wire         HREADYOUT_cpu;     // HREADY feedback
    wire   [1:0] HRESP_cpu;         // Transfer response
    wire  [1:0] HAUSER_cpu;        // Address USER signals
    wire  [1:0] HWUSER_cpu;        // Write-data USER signals
    wire  [1:0] HRUSER_cpu;        // Read-data USER signals

    // Output Port MI0
    wire         HSEL_rom1;          // Slave Select
    wire  [31:0] HADDR_rom1;         // Address bus
    wire   [1:0] HTRANS_rom1;        // Transfer type
    wire         HWRITE_rom1;        // Transfer direction
    wire   [2:0] HSIZE_rom1;         // Transfer size
    wire   [2:0] HBURST_rom1;        // Burst type
    wire   [3:0] HPROT_rom1;         // Protection control
    wire   [3:0] HMASTER_rom1;       // Master select
    wire  [31:0] HWDATA_rom1;        // Write data
    wire         HMASTLOCK_rom1;     // Locked Sequence
    wire         HREADYMUX_rom1;     // Transfer done

    wire  [31:0] HRDATA_rom1;        // Read data bus
    wire         HREADYOUT_rom1;     // HREADY feedback
    wire   [1:0] HRESP_rom1;         // Transfer response
    wire  [1:0] HAUSER_rom1;        // Address USER signals
    wire  [1:0] HWUSER_rom1;        // Write-data USER signals
    wire  [1:0] HRUSER_rom1;        // Read-data USER signals

    // Output Port MI1
    wire         HSEL_ram2;          // Slave Select
    wire  [31:0] HADDR_ram2;         // Address bus
    wire   [1:0] HTRANS_ram2;        // Transfer type
    wire         HWRITE_ram2;        // Transfer direction
    wire   [2:0] HSIZE_ram2;         // Transfer size
    wire   [2:0] HBURST_ram2;        // Burst type
    wire   [3:0] HPROT_ram2;         // Protection control
    wire   [3:0] HMASTER_ram2;       // Master select
    wire  [31:0] HWDATA_ram2;        // Write data
    wire         HMASTLOCK_ram2;     // Locked Sequence
    wire         HREADYMUX_ram2;     // Transfer done

    wire  [31:0] HRDATA_ram2;        // Read data bus
    wire         HREADYOUT_ram2;     // HREADY feedback
    wire   [1:0] HRESP_ram2;         // Transfer response
    wire  [1:0] HAUSER_ram2;        // Address USER signals
    wire  [1:0] HWUSER_ram2;        // Write-data USER signals
    wire  [1:0] HRUSER_ram2;        // Read-data USER signals

    // Output Port MI2
    wire         HSEL_ram3;          // Slave Select
    wire  [31:0] HADDR_ram3;         // Address bus
    wire   [1:0] HTRANS_ram3;        // Transfer type
    wire         HWRITE_ram3;        // Transfer direction
    wire   [2:0] HSIZE_ram3;         // Transfer size
    wire   [2:0] HBURST_ram3;        // Burst type
    wire   [3:0] HPROT_ram3;         // Protection control
    wire   [3:0] HMASTER_ram3;       // Master select
    wire  [31:0] HWDATA_ram3;        // Write data
    wire         HMASTLOCK_ram3;     // Locked Sequence
    wire         HREADYMUX_ram3;     // Transfer done

    wire  [31:0] HRDATA_ram3;        // Read data bus
    wire         HREADYOUT_ram3;     // HREADY feedback
    wire   [1:0] HRESP_ram3;         // Transfer response
    wire  [1:0] HAUSER_ram3;        // Address USER signals
    wire  [1:0] HWUSER_ram3;        // Write-data USER signals
    wire  [1:0] HRUSER_ram3;        // Read-data USER signals

    // Output Port MI3
    wire         HSEL_sys;          // Slave Select
    wire  [31:0] HADDR_sys;         // Address bus
    wire   [1:0] HTRANS_sys;        // Transfer type
    wire         HWRITE_sys;        // Transfer direction
    wire   [2:0] HSIZE_sys;         // Transfer size
    wire   [2:0] HBURST_sys;        // Burst type
    wire   [3:0] HPROT_sys;         // Protection control
    wire   [3:0] HMASTER_sys;       // Master select
    wire  [31:0] HWDATA_sys;        // Write data
    wire         HMASTLOCK_sys;     // Locked Sequence
    wire         HREADYMUX_sys;     // Transfer done

    wire  [31:0] HRDATA_sys;        // Read data bus
    wire         HREADYOUT_sys;     // HREADY feedback
    wire   [1:0] HRESP_sys;         // Transfer response
    wire  [1:0] HAUSER_sys;        // Address USER signals
    wire  [1:0] HWUSER_sys;        // Write-data USER signals
    wire  [1:0] HRUSER_sys;        // Read-data USER signals

    // Output Port MI4
    wire         HSEL_ram8;          // Slave Select
    wire  [31:0] HADDR_ram8;         // Address bus
    wire   [1:0] HTRANS_ram8;        // Transfer type
    wire         HWRITE_ram8;        // Transfer direction
    wire   [2:0] HSIZE_ram8;         // Transfer size
    wire   [2:0] HBURST_ram8;        // Burst type
    wire   [3:0] HPROT_ram8;         // Protection control
    wire   [3:0] HMASTER_ram8;       // Master select
    wire  [31:0] HWDATA_ram8;        // Write data
    wire         HMASTLOCK_ram8;     // Locked Sequence
    wire         HREADYMUX_ram8;     // Transfer done

    wire  [31:0] HRDATA_ram8;        // Read data bus
    wire         HREADYOUT_ram8;     // HREADY feedback
    wire   [1:0] HRESP_ram8;         // Transfer response
    wire  [1:0] HAUSER_ram8;        // Address USER signals
    wire  [1:0] HWUSER_ram8;        // Write-data USER signals
    wire  [1:0] HRUSER_ram8;        // Read-data USER signals

    // Output Port MI5
    wire         HSEL_ram9;          // Slave Select
    wire  [31:0] HADDR_ram9;         // Address bus
    wire   [1:0] HTRANS_ram9;        // Transfer type
    wire         HWRITE_ram9;        // Transfer direction
    wire   [2:0] HSIZE_ram9;         // Transfer size
    wire   [2:0] HBURST_ram9;        // Burst type
    wire   [3:0] HPROT_ram9;         // Protection control
    wire   [3:0] HMASTER_ram9;       // Master select
    wire  [31:0] HWDATA_ram9;        // Write data
    wire         HMASTLOCK_ram9;     // Locked Sequence
    wire         HREADYMUX_ram9;     // Transfer done

    wire  [31:0] HRDATA_ram9;        // Read data bus
    wire         HREADYOUT_ram9;     // HREADY feedback
    wire   [1:0] HRESP_ram9;         // Transfer response
    wire  [1:0] HAUSER_ram9;        // Address USER signals
    wire  [1:0] HWUSER_ram9;        // Write-data USER signals
    wire  [1:0] HRUSER_ram9;        // Read-data USER signals

    // Output Port MI6
    wire         HSEL_exp;          // Slave Select
    wire  [31:0] HADDR_exp;         // Address bus
    wire   [1:0] HTRANS_exp;        // Transfer type
    wire         HWRITE_exp;        // Transfer direction
    wire   [2:0] HSIZE_exp;         // Transfer size
    wire   [2:0] HBURST_exp;        // Burst type
    wire   [3:0] HPROT_exp;         // Protection control
    wire   [3:0] HMASTER_exp;       // Master select
    wire  [31:0] HWDATA_exp;        // Write data
    wire         HMASTLOCK_exp;     // Locked Sequence
    wire         HREADYMUX_exp;     // Transfer done

    wire  [31:0] HRDATA_exp;        // Read data bus
    wire         HREADYOUT_exp;     // HREADY feedback
    wire   [1:0] HRESP_exp;         // Transfer response
    wire  [1:0] HAUSER_exp;        // Address USER signals
    wire  [1:0] HWUSER_exp;        // Write-data USER signals
    wire  [1:0] HRUSER_exp;        // Read-data USER signals


// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------

    // Bus-switch input SI0
    wire         i_sel0;            // HSEL signal
    wire  [31:0] i_addr0;           // HADDR signal
    wire   [1:0] i_trans0;          // HTRANS signal
    wire         i_write0;          // HWRITE signal
    wire   [2:0] i_size0;           // HSIZE signal
    wire   [2:0] i_burst0;          // HBURST signal
    wire   [3:0] i_prot0;           // HPROTS signal
    wire   [3:0] i_master0;         // HMASTER signal
    wire         i_mastlock0;       // HMASTLOCK signal
    wire         i_active0;         // Active signal
    wire         i_held_tran0;       // HeldTran signal
    wire         i_readyout0;       // Readyout signal
    wire   [1:0] i_resp0;           // Response signal
    wire  [1:0] i_auser0;          // HAUSER signal

    // Bus-switch input SI1
    wire         i_sel1;            // HSEL signal
    wire  [31:0] i_addr1;           // HADDR signal
    wire   [1:0] i_trans1;          // HTRANS signal
    wire         i_write1;          // HWRITE signal
    wire   [2:0] i_size1;           // HSIZE signal
    wire   [2:0] i_burst1;          // HBURST signal
    wire   [3:0] i_prot1;           // HPROTS signal
    wire   [3:0] i_master1;         // HMASTER signal
    wire         i_mastlock1;       // HMASTLOCK signal
    wire         i_active1;         // Active signal
    wire         i_held_tran1;       // HeldTran signal
    wire         i_readyout1;       // Readyout signal
    wire   [1:0] i_resp1;           // Response signal
    wire  [1:0] i_auser1;          // HAUSER signal

    // Bus-switch input SI2
    wire         i_sel2;            // HSEL signal
    wire  [31:0] i_addr2;           // HADDR signal
    wire   [1:0] i_trans2;          // HTRANS signal
    wire         i_write2;          // HWRITE signal
    wire   [2:0] i_size2;           // HSIZE signal
    wire   [2:0] i_burst2;          // HBURST signal
    wire   [3:0] i_prot2;           // HPROTS signal
    wire   [3:0] i_master2;         // HMASTER signal
    wire         i_mastlock2;       // HMASTLOCK signal
    wire         i_active2;         // Active signal
    wire         i_held_tran2;       // HeldTran signal
    wire         i_readyout2;       // Readyout signal
    wire   [1:0] i_resp2;           // Response signal
    wire  [1:0] i_auser2;          // HAUSER signal

    // Bus-switch input SI3
    wire         i_sel3;            // HSEL signal
    wire  [31:0] i_addr3;           // HADDR signal
    wire   [1:0] i_trans3;          // HTRANS signal
    wire         i_write3;          // HWRITE signal
    wire   [2:0] i_size3;           // HSIZE signal
    wire   [2:0] i_burst3;          // HBURST signal
    wire   [3:0] i_prot3;           // HPROTS signal
    wire   [3:0] i_master3;         // HMASTER signal
    wire         i_mastlock3;       // HMASTLOCK signal
    wire         i_active3;         // Active signal
    wire         i_held_tran3;       // HeldTran signal
    wire         i_readyout3;       // Readyout signal
    wire   [1:0] i_resp3;           // Response signal
    wire  [1:0] i_auser3;          // HAUSER signal

    // Bus-switch SI0 to MI0 signals
    wire         i_sel0to0;         // Routing selection signal
    wire         i_active0to0;      // Active signal

    // Bus-switch SI0 to MI1 signals
    wire         i_sel0to1;         // Routing selection signal
    wire         i_active0to1;      // Active signal

    // Bus-switch SI0 to MI2 signals
    wire         i_sel0to2;         // Routing selection signal
    wire         i_active0to2;      // Active signal

    // Bus-switch SI0 to MI3 signals
    wire         i_sel0to3;         // Routing selection signal
    wire         i_active0to3;      // Active signal

    // Bus-switch SI0 to MI4 signals
    wire         i_sel0to4;         // Routing selection signal
    wire         i_active0to4;      // Active signal

    // Bus-switch SI0 to MI5 signals
    wire         i_sel0to5;         // Routing selection signal
    wire         i_active0to5;      // Active signal

    // Bus-switch SI0 to MI6 signals
    wire         i_sel0to6;         // Routing selection signal
    wire         i_active0to6;      // Active signal

    // Bus-switch SI1 to MI0 signals
    wire         i_sel1to0;         // Routing selection signal
    wire         i_active1to0;      // Active signal

    // Bus-switch SI1 to MI1 signals
    wire         i_sel1to1;         // Routing selection signal
    wire         i_active1to1;      // Active signal

    // Bus-switch SI1 to MI2 signals
    wire         i_sel1to2;         // Routing selection signal
    wire         i_active1to2;      // Active signal

    // Bus-switch SI1 to MI3 signals
    wire         i_sel1to3;         // Routing selection signal
    wire         i_active1to3;      // Active signal

    // Bus-switch SI1 to MI4 signals
    wire         i_sel1to4;         // Routing selection signal
    wire         i_active1to4;      // Active signal

    // Bus-switch SI1 to MI5 signals
    wire         i_sel1to5;         // Routing selection signal
    wire         i_active1to5;      // Active signal

    // Bus-switch SI1 to MI6 signals
    wire         i_sel1to6;         // Routing selection signal
    wire         i_active1to6;      // Active signal

    // Bus-switch SI2 to MI0 signals
    wire         i_sel2to0;         // Routing selection signal
    wire         i_active2to0;      // Active signal

    // Bus-switch SI2 to MI1 signals
    wire         i_sel2to1;         // Routing selection signal
    wire         i_active2to1;      // Active signal

    // Bus-switch SI2 to MI2 signals
    wire         i_sel2to2;         // Routing selection signal
    wire         i_active2to2;      // Active signal

    // Bus-switch SI2 to MI3 signals
    wire         i_sel2to3;         // Routing selection signal
    wire         i_active2to3;      // Active signal

    // Bus-switch SI2 to MI4 signals
    wire         i_sel2to4;         // Routing selection signal
    wire         i_active2to4;      // Active signal

    // Bus-switch SI2 to MI5 signals
    wire         i_sel2to5;         // Routing selection signal
    wire         i_active2to5;      // Active signal

    // Bus-switch SI2 to MI6 signals
    wire         i_sel2to6;         // Routing selection signal
    wire         i_active2to6;      // Active signal

    // Bus-switch SI3 to MI0 signals
    wire         i_sel3to0;         // Routing selection signal
    wire         i_active3to0;      // Active signal

    // Bus-switch SI3 to MI1 signals
    wire         i_sel3to1;         // Routing selection signal
    wire         i_active3to1;      // Active signal

    // Bus-switch SI3 to MI2 signals
    wire         i_sel3to2;         // Routing selection signal
    wire         i_active3to2;      // Active signal

    // Bus-switch SI3 to MI3 signals
    wire         i_sel3to3;         // Routing selection signal
    wire         i_active3to3;      // Active signal

    // Bus-switch SI3 to MI4 signals
    wire         i_sel3to4;         // Routing selection signal
    wire         i_active3to4;      // Active signal

    // Bus-switch SI3 to MI5 signals
    wire         i_sel3to5;         // Routing selection signal
    wire         i_active3to5;      // Active signal

    // Bus-switch SI3 to MI6 signals
    wire         i_sel3to6;         // Routing selection signal
    wire         i_active3to6;      // Active signal

    wire         i_hready_mux__rom1;    // Internal HREADYMUXM for MI0
    wire         i_hready_mux__ram2;    // Internal HREADYMUXM for MI1
    wire         i_hready_mux__ram3;    // Internal HREADYMUXM for MI2
    wire         i_hready_mux__sys;    // Internal HREADYMUXM for MI3
    wire         i_hready_mux__ram8;    // Internal HREADYMUXM for MI4
    wire         i_hready_mux__ram9;    // Internal HREADYMUXM for MI5
    wire         i_hready_mux__exp;    // Internal HREADYMUXM for MI6


// -----------------------------------------------------------------------------
// Beginning of main code
// -----------------------------------------------------------------------------

  // Input stage for SI0
  soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_0 (

    // Common AHB signals
    .HCLK       (HCLK),
    .HRESETn    (HRESETn),

    // Input Port Address/Control Signals
    .HSELS      (HSEL_adp),
    .HADDRS     (HADDR_adp),
    .HTRANSS    (HTRANS_adp),
    .HWRITES    (HWRITE_adp),
    .HSIZES     (HSIZE_adp),
    .HBURSTS    (HBURST_adp),
    .HPROTS     (HPROT_adp),
    .HMASTERS   (HMASTER_adp),
    .HMASTLOCKS (HMASTLOCK_adp),
    .HREADYS    (HREADY_adp),
    .HAUSERS    (HAUSER_adp),

    // Internal Response
    .active_ip     (i_active0),
    .readyout_ip   (i_readyout0),
    .resp_ip       (i_resp0),

    // Input Port Response
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This page: Created:Wed Feb 22 13:33:07 2023
From: ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v

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