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// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

module PAD_VDDIOIndex (
   PAD
   );
   inout PAD;
   assign PAD = 1'b1;
 endmodule // PAD_VDDIO

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This page: Created:Wed Feb 22 13:33:07 2023
From: ../../../../../GLIB/pads/verilog/PAD_VDDIO.v

Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis).Help