// SRAM Output
.RDATA (rdata_ram8)
);
// instandiate expansion RAM instance to appear at 0x90000000
//localparam AWRAM9 = 9; // 512B
//localparam AWRAM9 = 10; // 1024B
localparam AWRAM9 = 14; // 16KB
//localparam AWRAM9 = 16; // 64KB
wire [AWRAM9-3:0] addr_ram9;
wire [31:0] wdata_ram9;
wire [31:0] rdata_ram9;
wire [3:0] wen_ram9;
wire cs_ram9;
// AHB to SRAM bridge
cmsdk_ahb_to_sram #(.AW(AWRAM9)) u_ahb_to_sram9
(
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL_ram9), // AHB inputs
.HADDR (HADDR_ram9[AWRAM9-1:0]),
.HTRANS (HTRANS_ram9),
.HSIZE (HSIZE_ram9),
.HWRITE (HWRITE_ram9),
.HWDATA (HWDATA_ram9),
.HREADY (HREADYMUX_ram9),
// AHB Outputs
.HREADYOUT (HREADYOUT_ram9), // Outputs
.HRDATA (HRDATA_ram9),
.HRESP (HRESP_ram9),
// SRAM input
.SRAMRDATA (rdata_ram9),
// SRAM Outputs
.SRAMADDR (addr_ram9),
.SRAMWDATA (wdata_ram9),
.SRAMWEN (wen_ram9),
.SRAMCS (cs_ram9)
);
// SRAM model
cmsdk_fpga_sram #(.AW(AWRAM9)) u_fpga_ram9
(
// SRAM Inputs
.CLK (HCLK),
.ADDR (addr_ram9),
.WDATA (wdata_ram9),
.WREN (wen_ram9),
.CS (cs_ram9),
// SRAM Output
.RDATA (rdata_ram9)
);
// assign [31:0] HRDATA_ram8 = 32'hdead8888; // Read data bus
// assign HREADYOUT_ram8 = 1'b1; // HREADY feedback
// assign HRESP_ram8 = 1'b0; // Transfer response
// assign [1:0] HRUSER_ram8 = 00; // Read-data USER signals
//
// assign [31:0] HRDATA_ram9 = 32'hdead9999; // Read data bus
// assign HREADYOUT_ram9 = 1'b1; // HREADY feedback
// assign HRESP_ram9 = 1'b0; // Transfer response
// assign [1:0] HRUSER_ram9 = 00; // Read-data USER signals
//----------------------------------------
// ADP ASCII DEBUG PROTOCOL controller
// AHB MANAGER 0
//----------------------------------------
// -------------------------------
// ADP engine stream and control interfaces
// -------------------------------
wire comio_tx_ready;
wire [7:0] comio_tx_data8;
wire comio_tx_valid;
wire comio_rx_ready;
wire [7:0] comio_rx_data8;
wire comio_rx_valid;
wire stdio_tx_ready;
wire [7:0] stdio_tx_data8;
wire stdio_tx_valid;
wire stdio_rx_ready;
wire [7:0] stdio_rx_data8;
wire stdio_rx_valid;
wire [7:0] adp_gpo8;
wire [7:0] adp_gpi8;
assign adp_gpi8 = adp_gpo8;
assign ADPRESETREQ = adp_gpo8[0];
// DMA controller present
ADPcontrol_v1_0 u_ADP (
// Clock and Reset
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
// DMA Control
.com_rx_tready (comio_rx_ready),
.com_rx_tdata (comio_rx_data8),
.com_rx_tvalid (comio_rx_valid),
.com_tx_tready (comio_tx_ready),
.com_tx_tdata (comio_tx_data8),
.com_tx_tvalid (comio_tx_valid),
.stdio_rx_tready (stdio_rx_ready),
.stdio_rx_tdata (stdio_rx_data8),
.stdio_rx_tvalid (stdio_rx_valid),
.stdio_tx_tready (stdio_tx_ready),
.stdio_tx_tdata (stdio_tx_data8),
.stdio_tx_tvalid (stdio_tx_valid),
.gpo8 (adp_gpo8),
.gpi8 (adp_gpi8),
// AHB-Lite Master Interface
.ahb_hready (HREADY_adp),
.ahb_hresp (HRESP_adp),
.ahb_hrdata (HRDATA_adp),
.ahb_htrans (HTRANS_adp),
.ahb_hwrite (HWRITE_adp),
.ahb_haddr (HADDR_adp),
.ahb_hsize (HSIZE_adp),
.ahb_hburst (HBURST_adp),
.ahb_hmastlock (HMASTLOCK_adp),
.ahb_hprot (HPROT_adp),
.ahb_hwdata (HWDATA_adp)
);
assign HAUSER_adp [1:0] = 2'b00; // Address USER signals
assign HWUSER_adp [1:0] = 2'b00; // Write-data USER signals
cmsdk_apb_usrt u_apb_usrt_com (
.PCLK (PCLK), // Peripheral clock
.PCLKG (PCLKG), // Gated PCLK for bus
.PRESETn (PRESETn), // Reset
.PSEL (exp14_psel), // APB interface inputs
.PADDR (exp_paddr[11:2]),
.PENABLE (exp_penable),
.PWRITE (exp_pwrite),
.PWDATA (exp_pwdata),
.PRDATA (exp14_prdata), // APB interface outputs
.PREADY (exp14_pready),
.PSLVERR (exp14_pslverr),
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
.TX_VALID_o (stdio_rx_valid),
.TX_DATA8_o (stdio_rx_data8),
.TX_READY_i (stdio_rx_ready),
.RX_VALID_i (stdio_tx_valid),
.RX_DATA8_i (stdio_tx_data8),
.RX_READY_o (stdio_tx_ready),
.TXINT ( ), // Transmit Interrupt
.RXINT ( ), // Receive Interrupt
.TXOVRINT ( ), // Transmit Overrun Interrupt
.RXOVRINT ( ), // Receive Overrun Interrupt
.UARTINT ( ) // Combined Interrupt
);
wire [7:0] ft_clkdiv = 8'd03;
ft1248_streamio_v1_0 #
(.FT1248_WIDTH (1),
.FT1248_CLKON(0) )
u_ftdio_com (
.clk (HCLK),
.resetn (HRESETn),
.ft_clkdiv (ft_clkdiv ),
.ft_clk_o (ft_clk_o ),
.ft_ssn_o (ft_ssn_o ),
.ft_miso_i (ft_miso_i ),
.ft_miosio_o (ft_miosio_o ),
.ft_miosio_e (ft_miosio_e ),
.ft_miosio_z (ft_miosio_z ),
.ft_miosio_i (ft_miosio_i ),
.rxd_tready (comio_tx_ready),
.rxd_tdata (comio_tx_data8),
.rxd_tvalid (comio_tx_valid),
.rxd_tlast (1'b0),
.txd_tready (comio_rx_ready),
.txd_tdata (comio_rx_data8),
.txd_tvalid (comio_rx_valid),
.txd_tlast ( )
);
//----------------------------------------
// DIRECT MEMORY ACCESS controller
// AHB MANAGER 1
//----------------------------------------
// DMA interface not used in this example system
wire [DMA_CHANNEL_NUM-1:0] dma230_tie0; // tie off signal.
assign dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
// DMA done per channel
wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
wire dmac_done;
wire dmac_err;
///generate if (INCLUDE_DMA != 0) begin : gen_dma
// DMA controller present
pl230_udma u_pl230_udma (
// Clock and Reset
.hclk (HCLK),
.hresetn (HRESETn),
// DMA Control
.dma_req (dma230_tie0),
.dma_sreq (dma230_tie0),
.dma_waitonreq (dma230_tie0),
.dma_stall (1'b0),
.dma_active (),
.dma_done (dma230_done_ch),
.dma_err (dmac_err),
// AHB-Lite Master Interface
.hready (HREADY_dma),
.hresp (HRESP_dma),
.hrdata (HRDATA_dma),
.htrans (HTRANS_dma),
.hwrite (HWRITE_dma),
.haddr (HADDR_dma),
.hsize (HSIZE_dma),
.hburst (HBURST_dma),
.hmastlock (HMASTLOCK_dma),
.hprot (HPROT_dma),
.hwdata (HWDATA_dma),
// APB Slave Interface
.pclken (PCLKEN),
.psel (exp15_psel),
.pen (exp_penable),
.pwrite (exp_pwrite),
.paddr (exp_paddr[11:0]),
.pwdata (exp_pwdata[31:0]),
.prdata (exp15_prdata)
);
assign exp15_pready = 1'b1;
assign exp15_pslverr = 1'b0;
assign dmac_done = |dma230_done_ch; // OR all the DMA done together
/* end else begin : gen_no_pl230_udma
// DMA controller not present
assign HADDR_dma [31:0] = 32'ha2a2a2a2; // Address bus
assign HTRANS_dma [1:0] = 2'b00; // Transfer type
assign HWRITE_dma = 1'b0; // Transfer direction
assign HSIZE_dma [2:0] = 3'b010; // Transfer size
assign HBURST_dma [2:0] = 3'b001; // Burst type
assign HPROT_dma [3:0] = 4'b0010; // Protection control
assign HWDATA_dma [31:0] = 32'hd2d2d2d2; // Write data
assign HMASTLOCK_dma = 1'b0; // Locked Sequence
assign HAUSER_dma [1:0] = 2'b00; // Address USER signals
assign HWUSER_dma [1:0] = 2'b00; // Write-data USER signals
assign dmac_done = 1'b0;
assign dmac_err = 1'b0;
assign exp15_pready = 1'b1;
assign exp15_pslverr = 1'b0;
assign exp15_prdata = 32'h00000000;
assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
end endgenerate
*/
//----------------------------------------
// DIRECT MEMORY ACCESS controller 2
// AHB MANAGER 2
//----------------------------------------
// Manager port SI2 (inputs from master 2)
assign HADDR_dma2 [31:0] = 32'ha2a2a2a2; // Address bus
assign HTRANS_dma2 [1:0] = 2'b00; // Transfer type
assign HWRITE_dma2 = 1'b0; // Transfer direction
assign HSIZE_dma2 [2:0] = 3'b010; // Transfer size
assign HBURST_dma2 [2:0] = 3'b000; // Burst type
assign HPROT_dma2 [3:0] = 4'b0010; // Protection control
assign HWDATA_dma2 [31:0] = 32'hd2d2d2d2; // Write data
assign HMASTLOCK_dma2 = 1'b0; // Locked Sequence
assign HAUSER_dma2 [1:0] = 2'b00; // Address USER signals
assign HWUSER_dma2 [1:0] = 2'b00; // Write-data USER signals
//----------------------------------------
// CORTEX-M0 CPU controller
// AHB MANAGER 3
//----------------------------------------
wire SYS_NMI; // Watchdog nin-maskable interrupt
wire [31:0] SYS_APB_IRQ; // APB subsystem IRQs
wire [15:0] SYS_GPIO0_IRQ; // GPIO-0 IRQs
wire [15:0] SYS_GPIO1_IRQ; // GPIO-1 IRQs
wire gpio0_combintr;
wire gpio1_combintr;
assign gpio0_combintr = |SYS_GPIO0_IRQ[15:0];
assign gpio1_combintr = |SYS_GPIO1_IRQ[15:0];
wire intnmi_cm0;
wire [31:0] intisr_cm0;
// match interrupts to CMSDK for validation code reuse
assign intnmi_cm0 = SYS_NMI;
assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
assign intisr_cm0[ 6] = SYS_APB_IRQ[ 6] | gpio0_combintr;
assign intisr_cm0[ 7] = SYS_APB_IRQ[ 7] | gpio1_combintr;
assign intisr_cm0[14: 8] = SYS_APB_IRQ[14: 8];
assign intisr_cm0[15] = SYS_APB_IRQ[15] | dmac_done | dmac_err;
assign intisr_cm0[31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
assign HAUSER_cpu [1:0] = 2'b00; // Address USER signals
assign HWUSER_cpu [1:0] = 2'b00; // Write-data USER signals
// Cortex-M0 integration level
nanosoc_cpu
u_nanosoc_cpu (
.HCLK (gated_hclk), //HCLK),
.FCLK (FCLK),
.DCLK (DCLK),
.SCLK (SCLK),
.HRESETn (HRESETn),
.PORESETn (PORESETn),
.DBGRESETn (DBGRESETn),
.RSTBYPASS (TESTMODE),
.DFTSE (SCANENABLE),
// AHB port
.HADDR (HADDR_cpu),
.HTRANS (HTRANS_cpu),
.HWRITE (HWRITE_cpu),
.HSIZE (HSIZE_cpu),
.HBURST (HBURST_cpu),
.HPROT (HPROT_cpu),
.HWDATA (HWDATA_cpu),
.HMASTLOCK (HMASTLOCK_cpu),
.HREADY (HREADY_cpu),
// .HAUSER (HAUSER_cpu),
// .HWUSER (HWUSER_cpu),
.HRDATA (HRDATA_cpu),
.HRESP (HRESP_cpu),
// .HRUSER (HRUSER_cpu),
// sideband signals
.NMI (intnmi_cm0), // Non-maskable interrupt input
.IRQ (intisr_cm0[31:0]), // Interrupt request inputs
.TXEV (TXEV), // Event output (SEV executed)
.RXEV (RXEV), // Event input
// MISCELLANEOUS ---------------------
.SLEEPING (SLEEPING),
.SLEEPDEEP (SLEEPDEEP),
.WAKEUP (WAKEUP ), // Wake up request from WIC
.WICENREQ (WICENREQ ), // WIC enable request from PMU
.WICENACK (WICENACK ), // WIC enable ack to PMU
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.SLEEPHOLDACKn (SLEEPHOLDACKn),
.CDBGPWRUPACK (CDBGPWRUPACK),
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.LOCKUP (LOCKUP), // Core is locked-up
.GATEHCLK (GATEHCLK),
.SYSRESETREQ (SYSRESETREQ), // System reset request
.WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
.ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
// Debug - JTAG or Serial wire
// inputs
.SWDI (SWDI),
.SWCLK (SWCLK),
// outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN)
);
assign RXEV = dmac_done; // Generate event when a DMA operation completed.
//------------------------------------
// internal wires
assign p0_out_nen = ~p0_out_en; //active low pad drive option
assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
// Common AHB signals
wire [31:0] HADDR;
wire [1:0] HTRANS;
wire [2:0] HSIZE;
wire HWRITE;
wire [31:0] HWDATA;
wire HREADY;
localparam BASEADDR_GPIO0 = 32'h4001_0000;
localparam BASEADDR_GPIO1 = 32'h4001_1000;
localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
nanosoc_sysio
u_nanosoc_sysio (
.FCLK (FCLK ), // free-running clock
.PORESETn (PORESETn ), // Power-On-Reset (active-low)
.TESTMODE (TESTMODE ), // Test-mode override for testability
.HCLK (HCLK ), // AHB interconnect clock
.HRESETn (HRESETn ), // AHB interconnect reset (active-low)
// Common AHB signals
.HSEL (HSEL_sys ),
.HADDR (HADDR_sys ),
.HBURST (HBURST_sys ),
.HMASTLOCK (HMASTLOCK_sys),
.HPROT (HPROT_sys ),
.HSIZE (HSIZE_sys ),
.HTRANS (HTRANS_sys ),
.HWDATA (HWDATA_sys ),
.HWRITE (HWRITE_sys ),
.HREADY (HREADYMUX_sys),
.HRDATA (HRDATA_sys ),
.HRESP (HRESP_sys ),
.HREADYOUT (HREADYOUT_sys),
// APB clocking
.PCLK (PCLK ),
.PCLKG (PCLKG ),
.PRESETn (PRESETn ),
.PCLKEN (PCLKEN ),
// APB expansion select outputs
.exp12_psel (exp12_psel ),
.exp13_psel (exp13_psel ),
.exp14_psel (exp14_psel ),
.exp15_psel (exp15_psel ),
.exp_pwdata (exp_pwdata ),
.exp_paddr (exp_paddr ),
.exp_pwrite (exp_pwrite ),
.exp_penable (exp_penable ),
// APB expansion interface inputs
.exp12_prdata (exp12_prdata ),
.exp12_pready (exp12_pready ),
.exp12_pslverr (exp12_pslverr),
.exp13_prdata (exp13_prdata ),
.exp13_pready (exp13_pready ),
.exp13_pslverr (exp13_pslverr),
.exp14_prdata (exp14_prdata ),
.exp14_pready (exp14_pready ),
.exp14_pslverr (exp14_pslverr),
.exp15_prdata (exp15_prdata ),
.exp15_pready (exp15_pready ),
.exp15_pslverr (exp15_pslverr),
// CPU sideband signalling
.SYS_NMI (SYS_NMI ),
.SYS_APB_IRQ (SYS_APB_IRQ ),
// CPU specific power/reset control
.REMAP_CTRL (ROM_MAP ),
.APBACTIVE (APBACTIVE ),
.SYSRESETREQ (SYSRESETREQ ),
.WDOGRESETREQ (WDOGRESETREQ ),
.LOCKUP (LOCKUP ),
.LOCKUPRESET (LOCKUPRESET ),
.PMUENABLE (PMUENABLE ),
// chip IO
.SYS_GPIO0_IRQ (SYS_GPIO0_IRQ ),
.SYS_GPIO1_IRQ (SYS_GPIO1_IRQ ),
// IO signalling
.uart0_rxd (uart1_txd), //(uart0_rxd ), // crossover
.uart0_txd (uart0_txd ),
.uart0_txen (uart0_txen ),
.uart1_rxd (uart0_txd), //uart1_rxd ), // crossover
.uart1_txd (uart1_txd ),
.uart1_txen (uart1_txen ),
.uart2_rxd (uart2_rxd ),
.uart2_txd (uart2_txd ),
.uart2_txen (uart2_txen ),
.timer0_extin (timer0_extin ),
.timer1_extin (timer1_extin ),
// GPIO port signalling
.p0_in (p0_in ),
.p0_out (p0_out ),
.p0_outen (p0_out_en ),
.p0_altfunc (p0_altfunc ),
.p1_in (p1_in ),
.p1_out (p1_out ),
.p1_outen (p1_out_en ),
.p1_altfunc (p1_altfunc )
);
assign REMAP[3] = 1'b0;
assign REMAP[2] = 1'b0;
assign REMAP[1] = 1'b0;
assign REMAP[0] =!ROM_MAP;
assign exp12_pready = 1'b1;
assign exp13_pready = 1'b1;
assign exp12_pslverr = 1'b0;
assign exp13_pslverr = 1'b0;
assign exp12_prdata = 32'h0;
assign exp13_prdata = 32'h0;
// Serial wire debug is used. nTRST, TDI and TDO are not needed
//----------------------------------------
// I/O port pin muxing and tristate
//----------------------------------------
assign SWCLK = swdclk_i;
assign SWDI = swdio_i;
assign swdio_o = SWDO;
assign swdio_e = SWDOEN;
assign swdio_z = !SWDOEN;
cmsdk_mcu_pin_mux
u_pin_mux (
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
// Timer
.timer0_extin (timer0_extin),
.timer1_extin (timer1_extin),
// IO Ports
.p0_in ( ), // was (p0_in) now from pad inputs),
.p0_out (p0_out),
.p0_outen (p0_out_en),
.p0_altfunc (p0_altfunc),
.p1_in ( ), // was(p1_in) now from pad inputs),
.p1_out (p1_out),
.p1_outen (p1_out_en),
.p1_altfunc (p1_altfunc),
// Debug
.i_trst_n ( ),
.i_swditms ( ), //i_swditms),
.i_swclktck ( ), //i_swclktck),
.i_tdi ( ),
.i_tdo ( ),
.i_tdoen_n ( ),
.i_swdo ( ),
.i_swdoen ( ),
// IO pads
.p1_out_mux (p1_out_mux),
.p1_out_en_mux (p1_out_en_mux),
.P0 ( ), //P0),
.P1 ( ), //P1),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (1'b0), // Not needed if serial-wire debug is used
.SWDIOTMS ( ), //SWDIOTMS),
.SWCLKTCK ( ), //SWCLKTCK),
.TDO ( ) // Not needed if serial-wire debug is used
);
endmodule
This page: |
Created: | Wed Feb 22 13:33:07 2023 |
|
From: |
../verilog/nanosoc_chip.v |