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//-----------------------------------------------------------------------------
// customised Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
//            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
//      SVN Information
//
//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
//      Revision            : $Revision: 371321 $
//
//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : System level design for the example Cortex-M0 system
//-----------------------------------------------------------------------------

[Up: nanosoc_chip u_nanosoc_sysio]
module nanosoc_sysioIndex
(
  input  wire         FCLK,             // Free-running system clock
  input  wire         PORESETn,         // Power-On-Reset reset (active-low)
  input  wire         TESTMODE,         // Reset bypass in scan test
// AHB interface
  input  wire         HCLK,             // AHB clock
  input  wire         HRESETn,          // AHB reset (active-low)
  input  wire         HSEL,             // AHB region select
  input  wire  [31:0] HADDR,            // AHB address
  input  wire  [ 2:0] HBURST,           // AHB burst
  input  wire         HMASTLOCK,        // AHB lock
  input  wire  [ 3:0] HPROT,            // AHB prot
  input  wire  [ 2:0] HSIZE,            // AHB size
  input  wire  [ 1:0] HTRANS,           // AHB transfer
  input  wire  [31:0] HWDATA,           // AHB write data
  input  wire         HWRITE,           // AHB write
  input  wire         HREADY,           // AHB ready
  output  wire [31:0] HRDATA,           // AHB read-data
  output  wire        HRESP,            // AHB response
  output  wire        HREADYOUT,        // AHB ready out
  // APB clocking control
  input  wire         PCLK,             // Peripheral clock
  input  wire         PCLKG,            // Gated Peripheral bus clock
  input  wire         PRESETn,          // Peripheral system and APB reset
  input  wire         PCLKEN,           // Clock divide control for AHB to APB bridge
  // APB external Slave Interface
  output wire         exp12_psel,
  output wire         exp13_psel,
  output wire         exp14_psel,
  output wire         exp15_psel,
  output wire         exp_penable,
  output wire         exp_pwrite,
  output wire  [11:0] exp_paddr,
  output wire  [31:0] exp_pwdata,
  input  wire  [31:0] exp12_prdata,
  input  wire         exp12_pready,
  input  wire         exp12_pslverr,
  input  wire  [31:0] exp13_prdata,
  input  wire         exp13_pready,
  input  wire         exp13_pslverr,
  input  wire  [31:0] exp14_prdata,
  input  wire         exp14_pready,
  input  wire         exp14_pslverr,
  input  wire  [31:0] exp15_prdata,
  input  wire         exp15_pready,
  input  wire         exp15_pslverr,

  // CPU sideband signalling
  output wire         SYS_NMI,          // watchdog_interrupt;
  output wire [31:0]  SYS_APB_IRQ,      // apbsubsys_interrupt;
  output wire [15:0]  SYS_GPIO0_IRQ,    // GPIO 0 irqs
  output wire [15:0]  SYS_GPIO1_IRQ,    // GPIO 0 irqs
  
  // CPU power/reset control
  output wire         REMAP_CTRL,       // REMAP control bit
  output wire         APBACTIVE,        // APB bus active (for clock gating of PCLKG)
  output wire         SYSRESETREQ,      // Processor control - system reset request
  output wire         WDOGRESETREQ,     // Watchdog reset request
  input  wire         LOCKUP,           // Processor status - Locked up
  output wire         LOCKUPRESET,      // System Controller cfg - reset if lockup
  output wire         PMUENABLE,        // System Controller cfg - Enable PMU

  // IO signalling
  input  wire         uart0_rxd,        // Uart 0 receive data
  output wire         uart0_txd,        // Uart 0 transmit data
  output wire         uart0_txen,       // Uart 0 transmit data enable
  input  wire         uart1_rxd,        // Uart 1 receive data
  output wire         uart1_txd,        // Uart 1 transmit data
  output wire         uart1_txen,       // Uart 1 transmit data enable
  input  wire         uart2_rxd,        // Uart 2 receive data
  output wire         uart2_txd,        // Uart 2 transmit data
  output wire         uart2_txen,       // Uart 2 transmit data enable
  input  wire         timer0_extin,     // Timer 0 external input
  input  wire         timer1_extin,     // Timer 1 external input

  // GPIO
  input  wire  [15:0] p0_in,            // GPIO 0 inputs
  output wire  [15:0] p0_out,           // GPIO 0 outputs
  output wire  [15:0] p0_outen,         // GPIO 0 output enables
  output wire  [15:0] p0_altfunc,       // GPIO 0 alternate function (pin mux)
  input  wire  [15:0] p1_in,            // GPIO 1 inputs
  output wire  [15:0] p1_out,           // GPIO 1 outputs
  output wire  [15:0] p1_outen,         // GPIO 1 output enables
  output wire  [15:0] p1_altfunc       // GPIO 1 alternate function (pin mux)
);


  localparam BASEADDR_GPIO0  = 32'h4001_0000; // GPIO0 peripheral base address
  localparam BASEADDR_GPIO1  = 32'h4001_1000; // GPIO1 peripheral base address
  localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
  localparam BE              = 0;
  
   // ------------------------------------------------------------
   // Local wires
   // ------------------------------------------------------------

  wire              defslv_hsel;   // AHB default slave signals
  wire              defslv_hreadyout;
  wire     [31:0]   defslv_hrdata;
  wire              defslv_hresp;

  wire              apbsys_hsel;  // APB subsystem AHB interface signals
  wire              apbsys_hreadyout;
  wire     [31:0]   apbsys_hrdata;
  wire              apbsys_hresp;

  wire              gpio0_hsel;   // AHB GPIO bus interface signals
  wire              gpio0_hreadyout;
  wire     [31:0]   gpio0_hrdata;
  wire              gpio0_hresp;

  wire              gpio1_hsel;   // AHB GPIO bus interface signals
  wire              gpio1_hreadyout;
  wire     [31:0]   gpio1_hrdata;
  wire              gpio1_hresp;

  wire              sysctrl_hsel;  // System control bus interface signals
  wire              sysctrl_hreadyout;
  wire     [31:0]   sysctrl_hrdata;
  wire              sysctrl_hresp;

  // System ROM Table
  wire              sysrom_hsel;      // AHB to System ROM Table - select
  wire              sysrom_hreadyout; 
  wire     [31:0]   sysrom_hrdata;
  wire              sysrom_hresp;


  // AHB address decode
  nanosoc_sys_ahb_decode #(
     .BASEADDR_GPIO0       (BASEADDR_GPIO0),
     .BASEADDR_GPIO1       (BASEADDR_GPIO1),
     .BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
    )
    u_addr_decode (
    // System Address
    .hsel         (HSEL),
    .haddr        (HADDR),
    .apbsys_hsel  (apbsys_hsel),
    .gpio0_hsel   (gpio0_hsel),
    .gpio1_hsel   (gpio1_hsel),
    .sysctrl_hsel (sysctrl_hsel),
    .sysrom_hsel  (sysrom_hsel),
    .defslv_hsel  (defslv_hsel)
  );

  // AHB slave multiplexer
  cmsdk_ahb_slave_mux #(
    .PORT0_ENABLE  (1), // APB subsystem bridge
    .PORT1_ENABLE  (1), // GPIO Port 0
    .PORT2_ENABLE  (1), // GPIO Port 1
    .PORT3_ENABLE  (1), // SYS control
    .PORT4_ENABLE  (1), // SYS ROM table
    .PORT5_ENABLE  (1), // default
    .PORT6_ENABLE  (0),
    .PORT7_ENABLE  (0),
    .PORT8_ENABLE  (0),
    .PORT9_ENABLE  (0),
    .DW            (32)
    )
    u_ahb_slave_mux_sys_bus (
    .HCLK         (HCLK),
    .HRESETn      (HRESETn),
    .HREADY       (HREADY),
    .HSEL0        (apbsys_hsel),     // Input Port 0
    .HREADYOUT0   (apbsys_hreadyout),
    .HRESP0       (apbsys_hresp),
    .HRDATA0      (apbsys_hrdata),
    .HSEL1        (gpio0_hsel),      // Input Port 1
    .HREADYOUT1   (gpio0_hreadyout),
    .HRESP1       (gpio0_hresp),
    .HRDATA1      (gpio0_hrdata),
    .HSEL2        (gpio1_hsel),      // Input Port 2
    .HREADYOUT2   (gpio1_hreadyout),
    .HRESP2       (gpio1_hresp),
    .HRDATA2      (gpio1_hrdata),
    .HSEL3        (sysctrl_hsel),    // Input Port 3
    .HREADYOUT3   (sysctrl_hreadyout),
    .HRESP3       (sysctrl_hresp),
    .HRDATA3      (sysctrl_hrdata),
    .HSEL4        (sysrom_hsel),     // Input Port 4
    .HREADYOUT4   (sysrom_hreadyout),
    .HRESP4       (sysrom_hresp),
    .HRDATA4      (sysrom_hrdata),
    .HSEL5        (defslv_hsel),     // Input Port 5
    .HREADYOUT5   (defslv_hreadyout),
    .HRESP5       (defslv_hresp),
    .HRDATA5      (defslv_hrdata),
    .HSEL6        (1'b0),     // Input Port 6
    .HREADYOUT6   (defslv_hreadyout),
    .HRESP6       (defslv_hresp),
    .HRDATA6      (defslv_hrdata),
    .HSEL7        (1'b0),     // Input Port 7
    .HREADYOUT7   (defslv_hreadyout),
    .HRESP7       (defslv_hresp),
    .HRDATA7      (defslv_hrdata),
    .HSEL8        (1'b0),     // Input Port 8
    .HREADYOUT8   (defslv_hreadyout),
    .HRESP8       (defslv_hresp),
    .HRDATA8      (defslv_hrdata),
    .HSEL9        (1'b0),     // Input Port 9
    .HREADYOUT9   (defslv_hreadyout),
    .HRESP9       (defslv_hresp),
    .HRDATA9      (defslv_hrdata),

    .HREADYOUT    (HREADYOUT),   // Outputs
    .HRESP        (HRESP),
    .HRDATA       (HRDATA)
  );

  // Default slave
  cmsdk_ahb_default_slave u_ahb_default_slave_1 (
    .HCLK         (HCLK),
    .HRESETn      (HRESETn),
    .HSEL         (defslv_hsel),
    .HTRANS       (HTRANS),
    .HREADY       (HREADY),
    .HREADYOUT    (defslv_hreadyout),
    .HRESP        (defslv_hresp)
  );

  assign   defslv_hrdata = 32'h00000000; // Default slave do not have read data

  // -------------------------------
  // System ROM Table
  // -------------------------------
  cmsdk_ahb_cs_rom_table
   #(//.JEPID                             (),
     //.JEPCONTINUATION                   (),
     //.PARTNUMBER                        (),
     //.REVISION                          (),
     .BASE              (BASEADDR_SYSROMTABLE),
     // Entry 0 = Cortex-M0+ Processor
     .ENTRY0BASEADDR    (32'hE00FF000),
     .ENTRY0PRESENT     (1'b1),
     // Entry 1 = CoreSight MTB-M0+
     .ENTRY1BASEADDR    (32'hF0200000),
     .ENTRY1PRESENT     (0))
    u_system_rom_table
    (//Outputs
     .HRDATA                            (sysrom_hrdata[31:0]),
     .HREADYOUT                         (sysrom_hreadyout),
     .HRESP                             (sysrom_hresp),
     //Inputs
     .HCLK                              (HCLK),
     .HSEL                              (sysrom_hsel),
     .HADDR                             (HADDR[31:0]),
     .HBURST                            (HBURST[2:0]),
     .HMASTLOCK                         (HMASTLOCK),
     .HPROT                             (HPROT[3:0]),
     .HSIZE                             (HSIZE[2:0]),
     .HTRANS                            (HTRANS[1:0]),
     .HWDATA                            (HWDATA[31:0]),
     .HWRITE                            (HWRITE),
     .HREADY                            (HREADY),
     .ECOREVNUM                         (4'h0));

  // -------------------------------
  // Peripherals
  // -------------------------------

  cmsdk_mcu_sysctrl #(.BE (BE))
    u_cmsdk_mcu_sysctrl
  (
   // AHB Inputs
    .HCLK         (HCLK),
    .HRESETn      (HRESETn),
    .FCLK         (FCLK),
    .PORESETn     (PORESETn),
    .HSEL         (sysctrl_hsel),
    .HREADY       (HREADY),
    .HTRANS       (HTRANS),
    .HSIZE        (HSIZE),
    .HWRITE       (HWRITE),
    .HADDR        (HADDR[11:0]),
    .HWDATA       (HWDATA),
   // AHB Outputs
    .HREADYOUT    (sysctrl_hreadyout),
    .HRESP        (sysctrl_hresp),
    .HRDATA       (sysctrl_hrdata),
   // Reset information
    .SYSRESETREQ  (SYSRESETREQ),
    .WDOGRESETREQ (WDOGRESETREQ),
    .LOCKUP       (LOCKUP),
    // Engineering-change-order revision bits
    .ECOREVNUM    (4'h0),
   // System control signals
    .REMAP        (REMAP_CTRL),
    .PMUENABLE    (PMUENABLE),
    .LOCKUPRESET  (LOCKUPRESET)
   );

  // GPIO is driven from the AHB
  cmsdk_ahb_gpio #(
    .ALTERNATE_FUNC_MASK     (16'h0000), // No pin muxing for Port #0
    .ALTERNATE_FUNC_DEFAULT  (16'h0000), // All pins default to GPIO
    .BE                      (BE)
    )
    u_ahb_gpio_0  (
   // AHB Inputs
    .HCLK         (HCLK),
    .HRESETn      (HRESETn),
    .FCLK         (FCLK),
    .HSEL         (gpio0_hsel),
    .HREADY       (HREADY),
    .HTRANS       (HTRANS),
    .HSIZE        (HSIZE),
    .HWRITE       (HWRITE),
    .HADDR        (HADDR[11:0]),
    .HWDATA       (HWDATA),
   // AHB Outputs
    .HREADYOUT    (gpio0_hreadyout),
    .HRESP        (gpio0_hresp),
    .HRDATA       (gpio0_hrdata),

    .ECOREVNUM    (4'h0),// Engineering-change-order revision bits

    .PORTIN       (p0_in),   // GPIO Interface inputs
    .PORTOUT      (p0_out),  // GPIO Interface outputs
    .PORTEN       (p0_outen),
    .PORTFUNC     (p0_altfunc), // Alternate function control

    .GPIOINT      (SYS_GPIO0_IRQ[15:0]),  // Interrupt outputs
    .COMBINT      ( )
  );


  cmsdk_ahb_gpio #(
    .ALTERNATE_FUNC_MASK     (16'h002A), // pin muxing for Port #1
    .ALTERNATE_FUNC_DEFAULT  (16'h0000), // All pins default to GPIO
    .BE                      (BE)
    )
    u_ahb_gpio_1  (
   // AHB Inputs
    .HCLK         (HCLK),
    .HRESETn      (HRESETn),
    .FCLK         (FCLK),
    .HSEL         (gpio1_hsel),
    .HREADY       (HREADY),
    .HTRANS       (HTRANS),
    .HSIZE        (HSIZE),
    .HWRITE       (HWRITE),
    .HADDR        (HADDR[11:0]),
    .HWDATA       (HWDATA),
   // AHB Outputs
    .HREADYOUT    (gpio1_hreadyout),
    .HRESP        (gpio1_hresp),
    .HRDATA       (gpio1_hrdata),

    .ECOREVNUM    (4'h0),// Engineering-change-order revision bits

    .PORTIN       (p1_in),   // GPIO Interface inputs
    .PORTOUT      (p1_out),  // GPIO Interface outputs
    .PORTEN       (p1_outen),
    .PORTFUNC     (p1_altfunc), // Alternate function control

    .GPIOINT      (SYS_GPIO1_IRQ[15:0]),  // Interrupt outputs
    .COMBINT      ( )
  );

  // APB subsystem for timers, UARTs
  cmsdk_apb_subsystem #(
    .APB_EXT_PORT12_ENABLE   (1),
    .APB_EXT_PORT13_ENABLE   (1),
    .APB_EXT_PORT14_ENABLE   (1),
    .APB_EXT_PORT15_ENABLE   (1),
    .INCLUDE_IRQ_SYNCHRONIZER(0),
    .INCLUDE_APB_TEST_SLAVE  (1),
    .INCLUDE_APB_TIMER0      (1),  // Include simple timer #0
    .INCLUDE_APB_TIMER1      (1),  // Include simple timer #1
    .INCLUDE_APB_DUALTIMER0  (1),  // Include dual timer module
    .INCLUDE_APB_UART0       (1),  // Include simple UART #0
    .INCLUDE_APB_UART1       (1),  // Include simple UART #1
    .INCLUDE_APB_UART2       (1),  // Include simple UART #2.
    .INCLUDE_APB_WATCHDOG    (1),  // Include APB watchdog module
    .BE                      (BE)
     )
  u_apb_subsystem(

  // AHB interface for AHB to APB bridge
    .HCLK          (HCLK),
    .HRESETn       (HRESETn),

    .HSEL          (apbsys_hsel),
    .HADDR         (HADDR[15:0]),
    .HTRANS        (HTRANS[1:0]),
    .HWRITE        (HWRITE),
    .HSIZE         (HSIZE),
    .HPROT         (HPROT),
    .HREADY        (HREADY),
    .HWDATA        (HWDATA[31:0]),

    .HREADYOUT     (apbsys_hreadyout),
    .HRDATA        (apbsys_hrdata),
    .HRESP         (apbsys_hresp),

  // APB clock and reset
    .PCLK          (PCLK),
    .PCLKG         (PCLKG),
    .PCLKEN        (PCLKEN),
    .PRESETn       (PRESETn),

  // APB extension ports
    .PADDR         (exp_paddr[11:0]),
    .PWRITE        (exp_pwrite),
    .PWDATA        (exp_pwdata[31:0]),
    .PENABLE       (exp_penable),

    .ext12_psel    (exp12_psel),
    .ext13_psel    (exp13_psel),
    .ext14_psel    (exp14_psel),
    .ext15_psel    (exp15_psel),

  // Input from APB devices on APB expansion ports
    .ext12_prdata  (exp12_prdata),
    .ext12_pready  (exp12_pready),
    .ext12_pslverr (exp12_pslverr),
    .ext13_prdata  (exp13_prdata),
    .ext13_pready  (exp13_pready),
    .ext13_pslverr (exp13_pslverr),
    .ext14_prdata  (exp14_prdata),
    .ext14_pready  (exp14_pready),
    .ext14_pslverr (exp14_pslverr),
    .ext15_prdata  (exp15_prdata),
    .ext15_pready  (exp15_pready),
    .ext15_pslverr (exp15_pslverr),

    .APBACTIVE     (APBACTIVE),  // Status Output for clock gating

  // Peripherals
    // UART
    .uart0_rxd     (uart0_rxd),
    .uart0_txd     (uart0_txd),
    .uart0_txen    (uart0_txen),

    .uart1_rxd     (uart1_rxd),
    .uart1_txd     (uart1_txd),
    .uart1_txen    (uart1_txen),

    .uart2_rxd     (uart2_rxd),
    .uart2_txd     (uart2_txd),
    .uart2_txen    (uart2_txen),

    // Timer
    .timer0_extin  (timer0_extin),
    .timer1_extin  (timer1_extin),

  // Interrupt outputs
    .apbsubsys_interrupt (SYS_APB_IRQ),
    .watchdog_interrupt  (SYS_NMI),
   // reset output
    .watchdog_reset      (WDOGRESETREQ)
  );

endmodule

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