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C
 can_pdw_dbg : cortexm0_pmu : wire
 can_pdw_sys : cortexm0_pmu : wire
 CDBGPWRUPACK : CORTEXM0INTEGRATION : input
Connects up to:nanosoc_cpu:u_cortex_m0_integration:CDBGPWRUPACK 
 CDBGPWRUPACK : cortexm0_pmu : output
Connects down to:cm0_pmu_cdc_send_reset:u_cdbgpwrupack:REGDO 
Connects up to:nanosoc_chip:u_cortexm0_pmu:CDBGPWRUPACK 
 CDBGPWRUPACK : nanosoc_chip : wire
Connects down to:cortexm0_pmu:u_cortexm0_pmu:CDBGPWRUPACK , nanosoc_cpu:u_nanosoc_cpu:CDBGPWRUPACK 
 CDBGPWRUPACK : nanosoc_cpu : output
Connects down to:CORTEXM0INTEGRATION:u_cortex_m0_integration:CDBGPWRUPACK 
Connects up to:nanosoc_chip:u_nanosoc_cpu:CDBGPWRUPACK 
 CDBGPWRUPREQ : CORTEXM0INTEGRATION : output
Connects up to:nanosoc_cpu:u_cortex_m0_integration:CDBGPWRUPREQ 
 CDBGPWRUPREQ : cortexm0_pmu : input
Connects down to:cm0_pmu_sync_reset:u_dbg_pupreq_sync:SYNCDI 
Connects up to:nanosoc_chip:u_cortexm0_pmu:CDBGPWRUPREQ 
 CDBGPWRUPREQ : nanosoc_chip : wire
Connects down to:cortexm0_pmu:u_cortexm0_pmu:CDBGPWRUPREQ , nanosoc_cpu:u_nanosoc_cpu:CDBGPWRUPREQ 
 CDBGPWRUPREQ : nanosoc_cpu : input
Connects down to:CORTEXM0INTEGRATION:u_cortex_m0_integration:CDBGPWRUPREQ 
Connects up to:nanosoc_chip:u_nanosoc_cpu:CDBGPWRUPREQ 
 cdbgpwrupreq_s : cortexm0_pmu : wire
Connects down to:cm0_pmu_sync_reset:u_dbg_pupreq_sync:SYNCDO 
 cdbg_pwrup_ack : CORTEXM0INTEGRATION : wire
Connects down to:CORTEXM0DAP:u_dap:CDBGPWRUPACK 
 cdbg_pwrup_req : CORTEXM0INTEGRATION : wire
Connects down to:CORTEXM0DAP:u_dap:CDBGPWRUPREQ 
 cfg_acg : cm0_pmu_acg : wire
 cfg_dbg : CORTEXM0INTEGRATION : wire
 cfg_present : cm0_dbg_reset_sync : wire
 cfg_wic : cortexm0_wic : wire
 cfg_wiclines : cortexm0_wic : wire
 CGBYPASS : cmsdk_mcu_clkctrl : input
Connects up to:nanosoc_chip:u_cmsdk_mcu_clkctrl:TESTMODE 
 CGBYPASS : cortexm0_pmu : input
Connects down to:cm0_pmu_acg:u_hclk:BYPASS , cm0_pmu_acg:u_dclk:BYPASS , cm0_pmu_acg:u_fclk:BYPASS 
Connects up to:nanosoc_chip:u_cortexm0_pmu:TESTMODE 
 ch : cmsdk_ft1248x1_adpio : integer
 channel_cfg : pl230_ahb_ctrl : reg
 channel_cfg_load : pl230_ahb_ctrl : wire
 channel_cfg_nxt : pl230_ahb_ctrl : wire
 channel_cfg_store : pl230_ahb_ctrl : wire
 char_received : cmsdk_uart_capture : wire
 check_addr : soclabs_4x7_MasterInput : reg
 chnl_ctrl_hprot3to1 : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_ctrl_hprot3to1 
 chnl_ctrl_hprot3to1 : pl230_apb_regs : output
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_ctrl_hprot3to1 
 chnl_ctrl_hprot3to1 : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_ctrl_hprot3to1 , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_ctrl_hprot3to1 
 chnl_enable_status : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_enable_status 
 chnl_enable_status : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_enable_status 
 chnl_enable_status : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_enable_status , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_enable_status 
 chnl_enable_status_nxt : pl230_apb_regs : reg
 chnl_enable_status_wen : pl230_apb_regs : wire
 chnl_priority_status : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_priority_status 
 chnl_priority_status : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_priority_status 
 chnl_priority_status : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_priority_status , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_priority_status 
 chnl_priority_status_nxt : pl230_apb_regs : wire
 chnl_priority_status_wen : pl230_apb_regs : wire
 chnl_pri_alt_status : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_pri_alt_status 
 chnl_pri_alt_status : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_pri_alt_status 
 chnl_pri_alt_status : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_pri_alt_status , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_pri_alt_status 
 chnl_pri_alt_status_nxt : pl230_apb_regs : reg
 chnl_pri_alt_status_wen : pl230_apb_regs : wire
 chnl_req_mask_status : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_req_mask_status 
 chnl_req_mask_status : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_req_mask_status 
 chnl_req_mask_status : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_req_mask_status , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_req_mask_status 
 chnl_req_mask_status_nxt : pl230_apb_regs : wire
 chnl_req_mask_status_wen : pl230_apb_regs : wire
 chnl_req_wait : pl230_ahb_ctrl : reg
 chnl_sw_request : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_sw_request 
 chnl_sw_request : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_sw_request 
 chnl_sw_request : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_sw_request , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_sw_request 
 chnl_sw_request_nxt : pl230_apb_regs : wire
 chnl_sw_request_wen : pl230_apb_regs : wire
 chnl_useburst_status : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:chnl_useburst_status 
 chnl_useburst_status : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:chnl_useburst_status 
 chnl_useburst_status : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:chnl_useburst_status , pl230_ahb_ctrl:u_pl230_ahb_ctrl:chnl_useburst_status 
 chnl_useburst_status_nxt : pl230_apb_regs : reg
 chnl_useburst_status_wen : pl230_apb_regs : wire
 cid0_en : cmsdk_ahb_cs_rom_table : wire
 cid1_en : cmsdk_ahb_cs_rom_table : wire
 cid2_en : cmsdk_ahb_cs_rom_table : wire
 cid3_en : cmsdk_ahb_cs_rom_table : wire
 CLK : bootrom : input (used in @posedge)
Connects up to:ahb_bootrom:u_bootrom:HCLK 
 CLK : cm0_dbg_reset_sync : input (used in @posedge)
Connects up to:CORTEXM0INTEGRATION:u_dpreset_sync:SWCLKTCK 
 CLK : cm0_rst_send_set : input (used in @posedge)
Connects up to:cortexm0_rst_ctl:u_hreset_req:FCLK , cortexm0_rst_ctl:u_dbgreset_req:FCLK 
 CLK : cm0_rst_sync : input (used in @posedge)
Connects up to:cortexm0_rst_ctl:u_dbgresetn_sync:DCLK , cortexm0_rst_ctl:u_poresetn_sync:FCLK , cortexm0_rst_ctl:u_hresetn_sync:HCLK 
 CLK : cmsdk_clkreset : output
Connects up to:tb_cmsdk_mcu:u_cmsdk_clkreset:XTAL1 
 CLK : cmsdk_debug_tester : input (used in @posedge)
Connects down to:CORTEXM0INTEGRATION:u_cortex_m0_int:FCLK , CORTEXM0INTEGRATION:u_cortex_m0_int:SCLK , CORTEXM0INTEGRATION:u_cortex_m0_int:HCLK , CORTEXM0INTEGRATION:u_cortex_m0_int:DCLK , cmsdk_ahb_rom:u_rom:HCLK , cmsdk_ahb_ram:u_ram:HCLK , cmsdk_debug_tester_ahb_interconnect:u_ahb_interconnect:HCLK , cmsdk_ahb_default_slave:u_ahb_def_slv:HCLK , cmsdk_ahb_gpio:u_gpio_0:HCLK , cmsdk_ahb_gpio:u_gpio_0:FCLK , cmsdk_ahb_gpio:u_gpio_1:HCLK , cmsdk_ahb_gpio:u_gpio_1:FCLK 
Connects up to:tb_cmsdk_mcu:u_cmsdk_debug_tester:XTAL1 
 CLK : cmsdk_fpga_rom : input (used in @posedge)
Connects up to:nanosoc_chip:u_fpga_ram2:HCLK 
 CLK : cmsdk_fpga_sram : input (used in @posedge)
Connects up to:nanosoc_chip:u_fpga_ram3:HCLK , nanosoc_chip:u_fpga_ram8:HCLK , nanosoc_chip:u_fpga_ram9:HCLK 
 clk : cmsdk_mcu_clkctrl : wire (used in @posedge)
 CLK : cmsdk_uart_capture : input (used in @posedge)
Connects up to:tb_cmsdk_mcu:u_cmsdk_uart_capture1:ft_clk2uart , tb_cmsdk_mcu:u_cmsdk_uart_capture2:ft_clk2uart , tb_cmsdk_mcu:u_cmsdk_uart_capture:uart_clk 
 clk : ft1248_streamio_v1_0 : input (used in @posedge)
Connects up to:nanosoc_chip:u_ftdio_com:HCLK 
 CLK : nanosoc_chip : wire
Connects down to:cmsdk_mcu_clkctrl:u_cmsdk_mcu_clkctrl:XTAL1 
 CLK : SROM_Ax32 : input (used in @posedge)
Connects up to:tb_cmsdk_mcu:u_BOOTROM:XTAL1 
 CLKIN : cm0_pmu_acg : input
Connects up to:cortexm0_pmu:u_hclk:FCLK , cortexm0_pmu:u_dclk:FCLK , cortexm0_pmu:u_fclk:FCLK 
 CLKOUT : cm0_pmu_acg : output
Connects up to:cortexm0_pmu:u_dclk:DCLK , cortexm0_pmu:u_hclk:HCLK , cortexm0_pmu:u_fclk:SCLK 
 clk_ctrl_sys_reset_req : nanosoc_chip : wire
Connects down to:cmsdk_mcu_clkctrl:u_cmsdk_mcu_clkctrl:SYSRESETREQ 
 clk_en : cm0_pmu_acg : reg
 clk_en_nxt : cm0_pmu_acg : wire
 clk_out : cm0_pmu_acg : wire
 clock_q : cmsdk_clkreset : reg
 clr_sleepholdreq : cortexm0_pmu : wire
 clr_useburst : pl230_ahb_ctrl : output
Connects up to:pl230_udma:u_pl230_ahb_ctrl:clr_useburst 
 clr_useburst : pl230_apb_regs : input
Connects up to:pl230_udma:u_pl230_apb_regs:clr_useburst 
 clr_useburst : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:clr_useburst , pl230_ahb_ctrl:u_pl230_ahb_ctrl:clr_useburst 
 clr_wicreq : cortexm0_pmu : wire
 cmsdk_SYSRESETREQ : nanosoc_chip : wire
Connects down to:cortexm0_rst_ctl:u_rst_ctl:SYSRESETREQ , cortexm0_pmu:u_cortexm0_pmu:HRESETREQ 
 CODEHINTDE : CORTEXM0INTEGRATION : output
Connects down to:CORTEXM0:u_cortexm0:CODEHINTDE 
Connects up to:nanosoc_cpu:u_cortex_m0_integration:CODEHINTDE 
 CODEHINTDE : nanosoc_cpu : wire
Connects down to:CORTEXM0INTEGRATION:u_cortex_m0_integration:CODEHINTDE 
 CODENSEQ : CORTEXM0INTEGRATION : output
Connects down to:CORTEXM0:u_cortexm0:CODENSEQ 
Connects up to:nanosoc_cpu:u_cortex_m0_integration:CODENSEQ 
 CODENSEQ : nanosoc_cpu : wire
Connects down to:CORTEXM0INTEGRATION:u_cortex_m0_integration:CODENSEQ 
 COMBINT : cmsdk_ahb_gpio : output
Connects down to:cmsdk_iop_gpio:u_iop_gpio:COMBINT 
 COMBINT : cmsdk_iop_gpio : output
Connects up to:cmsdk_ahb_gpio:u_iop_gpio:COMBINT 
 comb_rst_n : cm0_rst_sync : wire (used in @negedge)
 comio_rx_data8 : nanosoc_chip : wire
Connects down to:ADPcontrol_v1_0:u_ADP:com_rx_tdata , ft1248_streamio_v1_0:u_ftdio_com:txd_tdata 
 comio_rx_ready : nanosoc_chip : wire
Connects down to:ADPcontrol_v1_0:u_ADP:com_rx_tready , ft1248_streamio_v1_0:u_ftdio_com:txd_tready 
 comio_rx_valid : nanosoc_chip : wire
Connects down to:ADPcontrol_v1_0:u_ADP:com_rx_tvalid , ft1248_streamio_v1_0:u_ftdio_com:txd_tvalid 
 comio_tx_data8 : nanosoc_chip : wire
Connects down to:ADPcontrol_v1_0:u_ADP:com_tx_tdata , ft1248_streamio_v1_0:u_ftdio_com:rxd_tdata 
 comio_tx_ready : nanosoc_chip : wire
Connects down to:ADPcontrol_v1_0:u_ADP:com_tx_tready , ft1248_streamio_v1_0:u_ftdio_com:rxd_tready 
 comio_tx_valid : nanosoc_chip : wire
Connects down to:ADPcontrol_v1_0:u_ADP:com_tx_tvalid , ft1248_streamio_v1_0:u_ftdio_com:rxd_tvalid 
 COMRX_TDATA_i : ADPmanager : input
Connects up to:ADPcontrol_v1_0:ADPmanager:com_rx_tdata 
 COMRX_TREADY_o : ADPmanager : output
Connects up to:ADPcontrol_v1_0:ADPmanager:com_rx_tready 
 COMRX_TVALID_i : ADPmanager : input
Connects up to:ADPcontrol_v1_0:ADPmanager:com_rx_tvalid 
 COMTX_TDATA_o : ADPmanager : output
Connects up to:ADPcontrol_v1_0:ADPmanager:com_tx_tdata 
 COMTX_TREADY_i : ADPmanager : input
Connects up to:ADPcontrol_v1_0:ADPmanager:com_tx_tready 
 COMTX_TVALID_o : ADPmanager : output
Connects up to:ADPcontrol_v1_0:ADPmanager:com_tx_tvalid 
 COM_RXE_i : ADPmanager : wire
 com_rx_ack : ADPmanager : reg
 com_rx_byte : ADPmanager : wire
 com_rx_done : ADPmanager : wire
 com_rx_req : ADPmanager : wire
 com_rx_tdata : ADPcontrol_v1_0 : input
Connects down to:ADPmanager:ADPmanager:COMRX_TDATA_i 
Connects up to:nanosoc_chip:u_ADP:comio_rx_data8 
 com_rx_tready : ADPcontrol_v1_0 : output
Connects down to:ADPmanager:ADPmanager:COMRX_TREADY_o 
Connects up to:nanosoc_chip:u_ADP:comio_rx_ready 
 com_rx_tvalid : ADPcontrol_v1_0 : input
Connects down to:ADPmanager:ADPmanager:COMRX_TVALID_i 
Connects up to:nanosoc_chip:u_ADP:comio_rx_valid 
 COM_TXF_i : ADPmanager : wire
 com_tx_ack : ADPmanager : wire
 com_tx_byte : ADPmanager : reg
 com_tx_done : ADPmanager : wire
 com_tx_req : ADPmanager : reg
 com_tx_tdata : ADPcontrol_v1_0 : output
Connects down to:ADPmanager:ADPmanager:COMTX_TDATA_o 
Connects up to:nanosoc_chip:u_ADP:comio_tx_data8 
 com_tx_tready : ADPcontrol_v1_0 : input
Connects down to:ADPmanager:ADPmanager:COMTX_TREADY_i 
Connects up to:nanosoc_chip:u_ADP:comio_tx_ready 
 com_tx_tvalid : ADPcontrol_v1_0 : output
Connects down to:ADPmanager:ADPmanager:COMTX_TVALID_o 
Connects up to:nanosoc_chip:u_ADP:comio_tx_valid 
 counter_decrement : pl230_ahb_ctrl : wire
 CS : cmsdk_fpga_rom : input
Connects up to:nanosoc_chip:u_fpga_ram2:cs_ram2 
 CS : cmsdk_fpga_sram : input
Connects up to:nanosoc_chip:u_fpga_ram3:cs_ram3 , nanosoc_chip:u_fpga_ram8:cs_ram8 , nanosoc_chip:u_fpga_ram9:cs_ram9 
 cs_ram2 : nanosoc_chip : wire
Connects down to:cmsdk_ahb_to_sram:u_ahb_to_sram2:SRAMCS , cmsdk_fpga_rom:u_fpga_ram2:CS 
 cs_ram3 : nanosoc_chip : wire
Connects down to:cmsdk_ahb_to_sram:u_ahb_to_sram3:SRAMCS , cmsdk_fpga_sram:u_fpga_ram3:CS 
 cs_ram8 : nanosoc_chip : wire
Connects down to:cmsdk_ahb_to_sram:u_ahb_to_sram8:SRAMCS , cmsdk_fpga_sram:u_fpga_ram8:CS 
 cs_ram9 : nanosoc_chip : wire
Connects down to:cmsdk_ahb_to_sram:u_ahb_to_sram9:SRAMCS , cmsdk_fpga_sram:u_fpga_ram9:CS 
 cs_reg : cmsdk_fpga_rom : reg
 cs_reg : cmsdk_fpga_sram : reg
 ctrl_base_ptr : pl230_ahb_ctrl : input
Connects up to:pl230_udma:u_pl230_ahb_ctrl:ctrl_base_ptr 
 ctrl_base_ptr : pl230_apb_regs : output reg
Connects up to:pl230_udma:u_pl230_apb_regs:ctrl_base_ptr 
 ctrl_base_ptr : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:ctrl_base_ptr , pl230_ahb_ctrl:u_pl230_ahb_ctrl:ctrl_base_ptr 
 ctrl_base_ptr_nxt : pl230_apb_regs : wire
 ctrl_base_ptr_wen : pl230_apb_regs : wire
 ctrl_dat_addr : pl230_ahb_ctrl : wire
 ctrl_dat_sel : pl230_ahb_ctrl : reg
 ctrl_offset : pl230_ahb_ctrl : reg
 ctrl_state : pl230_ahb_ctrl : output reg
Connects up to:pl230_udma:u_pl230_ahb_ctrl:ctrl_state 
 ctrl_state : pl230_apb_regs : input
Connects up to:pl230_udma:u_pl230_apb_regs:ctrl_state 
 ctrl_state : pl230_udma : wire
Connects down to:pl230_apb_regs:u_pl230_apb_regs:ctrl_state , pl230_ahb_ctrl:u_pl230_ahb_ctrl:ctrl_state 
 ctrl_state_nxt : pl230_ahb_ctrl : reg
 current_chnl_en : pl230_ahb_ctrl : wire
 current_chnl_onehot : pl230_ahb_ctrl : wire
 current_chnl_valid : pl230_ahb_ctrl : reg
 current_chnl_valid_nxt : pl230_ahb_ctrl : wire
 current_dout_padded : cmsdk_iop_gpio : wire
 current_slave_err : pl230_ahb_ctrl : reg
 current_slave_err_en : pl230_ahb_ctrl : wire
 current_slave_err_nxt : pl230_ahb_ctrl : wire
 cycle_ctrl : pl230_ahb_ctrl : wire
 cycle_ctrl_override : pl230_ahb_ctrl : wire
 cycle_ctrl_writeback : pl230_ahb_ctrl : wire
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