// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_VSSIO
(
PAD
);
inout PAD;
assign PAD = 1'b0;
endmodule // PAD_VSSIO
This page: |
Created: | Wed Feb 22 13:33:07 2023 |
|
From: |
../../../../../GLIB/pads/verilog/PAD_VSSIO.v |