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    .burst_op2     (i_burst2),
    .prot_op2      (i_prot2),
    .master_op2    (i_master2),
    .mastlock_op2  (i_mastlock2),
    .wdata_op2     (HWDATA_dma2),
    .wuser_op2     (HWUSER_dma2),
    .held_tran_op2  (i_held_tran2),

    // Port 3 Signals
    .sel_op3       (i_sel3to5),
    .addr_op3      (i_addr3),
    .auser_op3     (i_auser3),
    .trans_op3     (i_trans3),
    .write_op3     (i_write3),
    .size_op3      (i_size3),
    .burst_op3     (i_burst3),
    .prot_op3      (i_prot3),
    .master_op3    (i_master3),
    .mastlock_op3  (i_mastlock3),
    .wdata_op3     (HWDATA_cpu),
    .wuser_op3     (HWUSER_cpu),
    .held_tran_op3  (i_held_tran3),

    // Slave read data and response
    .HREADYOUTM (HREADYOUT_ram9),

    .active_op0    (i_active0to5),
    .active_op1    (i_active1to5),
    .active_op2    (i_active2to5),
    .active_op3    (i_active3to5),

    // Slave Address/Control Signals
    .HSELM      (HSEL_ram9),
    .HADDRM     (HADDR_ram9),
    .HAUSERM    (HAUSER_ram9),
    .HTRANSM    (HTRANS_ram9),
    .HWRITEM    (HWRITE_ram9),
    .HSIZEM     (HSIZE_ram9),
    .HBURSTM    (HBURST_ram9),
    .HPROTM     (HPROT_ram9),
    .HMASTERM   (HMASTER_ram9),
    .HMASTLOCKM (HMASTLOCK_ram9),
    .HREADYMUXM (i_hready_mux__ram9),
    .HWUSERM    (HWUSER_ram9),
    .HWDATAM    (HWDATA_ram9)

    );

  // Drive output with internal version
  assign HREADYMUX_ram9 = i_hready_mux__ram9;


  // Output stage for MI6
  soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_6 (

    // Common AHB signals
    .HCLK       (HCLK),
    .HRESETn    (HRESETn),

    // Port 0 Signals
    .sel_op0       (i_sel0to6),
    .addr_op0      (i_addr0),
    .auser_op0     (i_auser0),
    .trans_op0     (i_trans0),
    .write_op0     (i_write0),
    .size_op0      (i_size0),
    .burst_op0     (i_burst0),
    .prot_op0      (i_prot0),
    .master_op0    (i_master0),
    .mastlock_op0  (i_mastlock0),
    .wdata_op0     (HWDATA_adp),
    .wuser_op0     (HWUSER_adp),
    .held_tran_op0  (i_held_tran0),

    // Port 1 Signals
    .sel_op1       (i_sel1to6),
    .addr_op1      (i_addr1),
    .auser_op1     (i_auser1),
    .trans_op1     (i_trans1),
    .write_op1     (i_write1),
    .size_op1      (i_size1),
    .burst_op1     (i_burst1),
    .prot_op1      (i_prot1),
    .master_op1    (i_master1),
    .mastlock_op1  (i_mastlock1),
    .wdata_op1     (HWDATA_dma),
    .wuser_op1     (HWUSER_dma),
    .held_tran_op1  (i_held_tran1),

    // Port 2 Signals
    .sel_op2       (i_sel2to6),
    .addr_op2      (i_addr2),
    .auser_op2     (i_auser2),
    .trans_op2     (i_trans2),
    .write_op2     (i_write2),
    .size_op2      (i_size2),
    .burst_op2     (i_burst2),
    .prot_op2      (i_prot2),
    .master_op2    (i_master2),
    .mastlock_op2  (i_mastlock2),
    .wdata_op2     (HWDATA_dma2),
    .wuser_op2     (HWUSER_dma2),
    .held_tran_op2  (i_held_tran2),

    // Port 3 Signals
    .sel_op3       (i_sel3to6),
    .addr_op3      (i_addr3),
    .auser_op3     (i_auser3),
    .trans_op3     (i_trans3),
    .write_op3     (i_write3),
    .size_op3      (i_size3),
    .burst_op3     (i_burst3),
    .prot_op3      (i_prot3),
    .master_op3    (i_master3),
    .mastlock_op3  (i_mastlock3),
    .wdata_op3     (HWDATA_cpu),
    .wuser_op3     (HWUSER_cpu),
    .held_tran_op3  (i_held_tran3),

    // Slave read data and response
    .HREADYOUTM (HREADYOUT_exp),

    .active_op0    (i_active0to6),
    .active_op1    (i_active1to6),
    .active_op2    (i_active2to6),
    .active_op3    (i_active3to6),

    // Slave Address/Control Signals
    .HSELM      (HSEL_exp),
    .HADDRM     (HADDR_exp),
    .HAUSERM    (HAUSER_exp),
    .HTRANSM    (HTRANS_exp),
    .HWRITEM    (HWRITE_exp),
    .HSIZEM     (HSIZE_exp),
    .HBURSTM    (HBURST_exp),
    .HPROTM     (HPROT_exp),
    .HMASTERM   (HMASTER_exp),
    .HMASTLOCKM (HMASTLOCK_exp),
    .HREADYMUXM (i_hready_mux__exp),
    .HWUSERM    (HWUSER_exp),
    .HWDATAM    (HWDATA_exp)

    );

  // Drive output with internal version
  assign HREADYMUX_exp = i_hready_mux__exp;


endmodule

// --================================= End ===================================--

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HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Created:Wed Feb 22 13:33:08 2023
From: ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v

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