diff --git a/flist/IP/ARM_Cortex_A53.flist b/flist/IP/ARM_Cortex_A53.flist
index f368fbe6eabc1b30b3ced5474a4cd68c28abc04e..ad5c270ab88bcd8a3b3e18aa606cb2e0e295bc3c 100644
--- a/flist/IP/ARM_Cortex_A53.flist
+++ b/flist/IP/ARM_Cortex_A53.flist
@@ -13,353 +13,353 @@
// Abstract : Verilog Command File for Arm Cortex A53 IP
//-----------------------------------------------------------------------------
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53gic/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53ifu/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53scu/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53stb/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53tlb/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/dapapbap/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/dapapbmux/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/daplite/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/daprom/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/dapswjdp/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/shared/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53biu/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53dcu/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53dpu/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53etm/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53gic/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53stb/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbap/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/daplite/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/daprom/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_addr_req_arbiter.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_data_read_buffers.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_data_write_buffers.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_dcu_alloc_mngmt.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_devsplit_mngmt.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_dvm_enc.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_linefill_descriptor.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_linefills_mngmt.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53biu/verilog/ca53biu_prefetch_stream_mngmt.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53cti/verilog/ca53cti.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53cti/verilog/ca53cti_apbif.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53cti/verilog/ca53cti_ci.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53cti/verilog/ca53cti_clkgate.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53cti/verilog/ca53cti_mapper.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53cti/verilog/ca53cti_ti.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_cachearb.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_cachearb_seq_state.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_ccbctl.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_cp15.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_dvm.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_ecc_correction.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dcu/verilog/ca53dcu_lspipe.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_unpack_opb.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_agu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_iq.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_au.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_iq_dih.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_clz.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_ldst.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_crc32.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec_imm_other.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_extract.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec_late_neon.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_extract_64.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_div.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_gen_sat.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_mac.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_lu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_div_csa.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_mask_imm.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_maskgen.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_div_quot.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_masksel.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_ld.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_rbit.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_early_exception.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_rbit_64.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_etmif.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_sat_dbl.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_lu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_sbitx.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_perm_ctl.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_shift.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_exception.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_alu_simd_sat.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_br.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_cp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_permutation.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_cpsr.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_polymul.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_ctl.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_ctl_reg_aa32_aa64.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_clz54.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_ctl_reg_trans.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_clz64.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_ctl_regexpand.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_reduce.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dbg.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_de.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_shift.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_de_pc.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_div.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_de_reg_extract.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_dp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_de_reg_trans.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_mul.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_de_regexpand.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_shift8.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_de_rp_dec.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_shift_sat.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec0_br.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_swap_max.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec0_dp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_vector_maxmin.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec0_ls.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_neon_vrec_est.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec0_neon.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec0_other.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_pmu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec1.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_psr_regfile.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec1_br.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_mul_array.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec1_late_neon.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_regbank.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec1_ls.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_search_rl.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec1_neon.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_regbank.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec_forceop.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_special.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec_imm_dp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_store.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_dec_imm_ls.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_alu.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_shift7.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_alu_denorm.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_unpack_opa.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_alu_renorm.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_swizzle_load.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_cg.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_swizzle_store.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_clz106.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_utlb_intf_entry.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_fp_clz24.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53dpu/verilog/ca53dpu_utlb_main_entry.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_apb.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_clk.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_cmp.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_counter.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_derived_res.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_event.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53etm/verilog/ca53etm_extin.v
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+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53gov/verilog/ca53governor_slice.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_cp15.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_ctl.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_lfb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_lfb_ctl.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_a32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_a64.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_debug_dec.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_debug_dec_a64.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_debug_dec_t32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_slice.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_t16.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_t32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pd_thumb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pdc.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pdc_t16.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pdc_t32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_bpd.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_btac.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_btic.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_crs.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_dec_branch.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_dec_branch_s32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_dec_class.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_dec_d1.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_dec_t16t32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_iq_format_i0.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_iq_format_i1.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_iq_format_ret.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_it_undef.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_pdc_checker.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_throttle.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_utlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_utlb_intf_entry.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53ifu/verilog/ca53ifu_pf_utlb_main_entry.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_acpslv.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_afb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_buf_age.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_clk.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_config.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_cpuslv.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_dvmcomp.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_l2db.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_lfsr.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_lfsr_arb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_master.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_master_ace.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_master_retries.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_master_skyros.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_ramctl.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_reqbuf_acp.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_reqbuf_cpu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_reqbuf_ecc.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_reqbuf_snp.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_reqbuf_sync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_sam.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_snpslv.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_tagctl.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_tagctl_ecc.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53scu/verilog/ca53scu_victimctl.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53stb/verilog/ca53stb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53stb/verilog/ca53stb_slot.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_cp_regs.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_dbg.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_dbg_bkpt.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_dbg_wpt.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_lookup.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_pagewalk.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_ramctl.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53tlb/verilog/ca53tlb_remap.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/ca53_cpu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/ca53_cpu_reset.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/ca53_l2.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/ca53_l2noram.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/ca53_noram.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/verilog/CORTEXA53.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbap/verilog/DAPAPBAP.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbap/verilog/DAPApbApApbIf.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbap/verilog/DAPApbApDapIf.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPAPBMUX.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxArbiter.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxCLAMP.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxClBit0.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxClBit1.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxClBus0.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxSync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapapbmux/verilog/DAPApbMuxSysSlv.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/daplite/verilog/DAPLITE.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/daplite/verilog/DAPLiteDecoder.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/daplite/verilog/DAPLiteMux.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/daplite/verilog/DAPLiteRomMux.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/daprom/verilog/DAPROM.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPDpApbIfClamp.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPDpApbSync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPDpClamp0.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPDpEnSync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPDpIMux.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPDpSync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPJtagDpProtocol.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPSWJDP.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPSwDpApbIf.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPSwDpProtocol.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPSwDpSync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/dapswjdp/verilog/DAPSwjWatcher.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/cells/generic/ca53_cell_clkgate.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/cells/generic/ca53_cell_inter_clkgate.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/cells/generic/ca53_cell_sync.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/rams/generic/ca53_caches_tlb_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/rams/generic/ca53_generic_ram.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/rams/generic/ca53_l2_datarams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/rams/generic/ca53_l2_tagrams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/models/rams/generic/ca53scu_l1d_tagrams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gic_ext.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_biu_dpu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gic_gov.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_biu_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gicarb_ext.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gov_scu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_biu_scu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gov_stb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_biu_tlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gov_tlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dcu_biu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ifu_biu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dcu_ifu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ifu_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dcu_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ifu_tlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dcu_stb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_rr_arb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dcu_tlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_rr_reg_arb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_scu_dcu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_dcu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_scu_ext.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_etm.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_scu_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_gic.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_stb_biu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_gov.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_stb_dpu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_ifu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_stb_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_l2rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_repair64.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_stb_scu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_scu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_tlb_etm.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_dpu_tlb.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_tlb_rams.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_check32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_check33.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_check64.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_fatal32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_fatal33.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_fatal64.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_etm_gov.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_generate32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_generate33.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_generate64.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_repair32.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_ecc_repair33.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gov_biu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gov_dcu.v
+$(CORTEX_A53_IP_LOGICAL_DIR)/shared/verilog/ca53_gov_ifu.v
diff --git a/flist/IP/CA53_tarmac.flist b/flist/IP/CA53_tarmac.flist
index 5a7e84a89947bfcff562a23a1dcdcc59b4bad35c..56d004754e91687510718097fc5281bed27a1ef8 100644
--- a/flist/IP/CA53_tarmac.flist
+++ b/flist/IP/CA53_tarmac.flist
@@ -2,5 +2,5 @@
//+define+CORTEXA53_UNIVENT_DPI_CAPTURE
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/verilog
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/verilog/ca53_follower.sv
\ No newline at end of file
++incdir+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/verilog
+$(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/verilog/ca53_follower.sv
\ No newline at end of file
diff --git a/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v b/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
index 7ddd5e40554d059a316d12ef1b43e141d2f69f0e..8d80fcd5bc4c0ca6aef5fbcf3b972f65dd2270b0 100644
--- a/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
+++ b/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
@@ -186,7 +186,7 @@ module megasoc_cpu_ss #(
assign AWIDM[5] = 1'b0;
assign WIDM[5] = 1'b0;
assign BIDM[5] = 1'b0;
- CortexA53_1
+ CORTEXA53
u_cortexa53
(// Clocks and resets
.CLKIN (CPU_CLK),
diff --git a/make.cfg b/make.cfg
index fe49a3cafc89b3b3d8ac277245570e4b881d9ae3..b47d755789b772f98fd4af6ea1d310a3e97e04ca 100644
--- a/make.cfg
+++ b/make.cfg
@@ -1,4 +1,4 @@
-Cortex_M55_IP_DIR:=/research/AAA/ip_library/Cortex-M55/AT634-r1p1-00rel6-0/AT633-BU-50000-r1p1-00rel1
+CORTEX_A53_IP_LOGICAL_DIR:=/research/AAA/ip_library/Cortex-A53/MP030-r0p4-52rel2/MP030-BU-50000-r0p4-52rel2/cortexa53/logical
SOC600_IP_DIR:=/research/AAA/ip_library/TM200/TM200-BU-50000-r4p1-00rel0/css600
PCK_600_IP_DIR:=/research/AAA/ip_library/PCK-600/PL608-BU-50000-r0p5-00rel0/pck600
SIE300_IP_LOGICAL_DIR:=$(ARM_IP_LIBRARY_PATH)/BP301/BP301-BU-50000-r1p2-00rel0/sie300/logical
diff --git a/makefile b/makefile
index ee5fde858cb12dcc6ae2210e8fb8ff5f1a77fb16..dc9ebe04ffe8b55463416b31cf1462dbe52e0b54 100644
--- a/makefile
+++ b/makefile
@@ -12,14 +12,16 @@
include ./make.cfg
-build_pck600:
- socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=pck600_clk_ctrl_1
- socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=pck600_ppu_1
build_sie300_sram_ctrl:
- @$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
+ @$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/sie300/
build_nic400:
socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=nic400_megasoc_main
-build_ip:
+build_cortex_a53:
+ mkdir $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/
+ mkdir $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/verilog
+ @$(CORTEX_A53_IP_LOGICAL_DIR)/shared/tools/bin/RenderCORTEXA53.pl -config $(SOCLABS_MEGASOC_TECH_DIR)/socrates/CortexA53_1/CORTEXA53.cfg -input $(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/CORTEXA53_unconfigured.v -output $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/verilog/CORTEXA53.v
+
+build_ip: build_nic400 build_cortex_a53 build_sie300_sram_ctrl
make_project:
socrates_cli --project megasoc_tech -data ../ --flow AddNewProject
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index e4838bb620df6846b5bc273920e4cd28be0b0d0c..59786c262ee0fa40a8ebd59afb2a0e9ddc369b2e 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -11,130 +11,18 @@
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#----------------------------------------------------------------------------
-#
-# Version Information
-#
-# Checked In : Mon Jul 15 17:15:15 2019 +0100
-#
-# Revision : 828f11fd
-#
-# Release Information : CoreLink SIE-300 Generic Global Bundle r1p2-00rel0
-#
-#----------------------------------------------------------------------------
-# Abstract : Configuration file for SIE-300 AXI5 SRAM Controller
-#----------------------------------------------------------------------------
-
-# -----------------------------
-# User Configuration
-# -----------------------------
-
-
-#
-# COMPONENT: Name of the component to configure.
-# Valid values:
-# [sie300_axi5_sram_ctrl]
-#
-COMPONENT: sie300_axi5_sram_ctrl
-
-
-#
-# CONFIG_NAME: Name of the configuration.
-# Each unifiqued element and top is suffixed with
-# _${CONFIG_NAME}
-#
-CONFIG_NAME: millisoc_sys
-
-
-#
-# ADDR_WIDTH: AXI5 Address Bus width
-# Valid values:
-# 14-24
-ADDR_WIDTH: 14
-
-
-#
-# DATA_WIDTH: AXI5 Data Bus width
-# Valid values:
-# [32,64,128,256]
-DATA_WIDTH: 64
-
-
-#
-# ID_WIDTH: AXI5 ID width for all channels
-# Valid values:
-# 2-32
-ID_WIDTH: 5
-
-
-#
-# QCLK_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
-# Valid values:
-# - 0 : no synchronizer
-# - 1 : added synchronizer
-QCLK_SYNC_EN: 1
-
-
-#
-# QPWR_SYNC_EN: Add 2 DFF synchronizer on inputs of power Q-channel
-# Valid values:
-# - 0 : no synchronizer
-# - 1 : added synchronizer
-QPWR_SYNC_EN: 1
-
-
-#
-# QEXT_SYNC_EN: Add 2 DFF synchronizer on inputs of external gating Q-channel
-# Valid values:
-# - 0 : no synchronizer
-# - 1 : added synchronizer
-QEXT_SYNC_EN: 1
-
-
-#
-# EXCLUSIVE_MONITORS: Number of Exclusive Access Monitors to observe
-# and track AXI locked transactions
-# Valid values:
-# 0-16 (0 means no locked transaction support)
-EXCLUSIVE_MONITORS: 2
-
-
-#
-# AR_BUF_SIZE: Size of FIFO on AR channel
-# Valid values:
-# 1-16
-AR_BUF_SIZE: 1
-
-
-#
-# AW_BUF_SIZE: Size of FIFO on AW channel
-# Valid values:
-# 1-16
-AW_BUF_SIZE: 2
-
-
-#
-# W_BUF_SIZE: Size of FIFO on W channel
-# Valid values:
-# 1-16
-W_BUF_SIZE: 8
-
-
-#
-# REGISTER_AXI_AR: Enables / disables register stage at the AR FIFO
-# Valid values:
-# [BYPASS,FULL]
-REGISTER_AXI_AR: BYPASS
-
-
-#
-# REGISTER_AXI_R: Enables / disables register stage at the R FIFO
-# Valid values:
-# [BYPASS,FULL]
-REGISTER_AXI_R: BYPASS
-
-
-#
-# AXI5_POISON_EN: Enables / disables AXI5 Data Poisoning support
-# Valid values:
-# [0,1]
-AXI5_POISON_EN: 0
+COMPONENT : sie300_axi5_sram_ctrl
+CONFIG_NAME : 1
+ADDR_WIDTH : 20
+DATA_WIDTH : 64
+ID_WIDTH : 7
+QCLK_SYNC_EN : 1
+QPWR_SYNC_EN : 1
+QEXT_SYNC_EN : 1
+EXCLUSIVE_MONITORS : 2
+AR_BUF_SIZE : 1
+AW_BUF_SIZE : 2
+W_BUF_SIZE : 8
+AXI5_POISON_EN : 1
+REGISTER_AXI_AR : BYPASS
+REGISTER_AXI_R : BYPASS
diff --git a/socrates/CortexA53_1/CORTEXA53.cfg b/socrates/CortexA53_1/CORTEXA53.cfg
new file mode 100755
index 0000000000000000000000000000000000000000..ae236fce9743aae2836653773d73f93e87037317
--- /dev/null
+++ b/socrates/CortexA53_1/CORTEXA53.cfg
@@ -0,0 +1,95 @@
+
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2012-2016 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2014-07-25 12:42:21 +0100 (Fri, 25 Jul 2014) $
+#
+# Revision : $Revision: 285827 $
+#
+# Release Information : CORTEXA53-r0p4-52rel0
+#
+#-----------------------------------------------------------------------------
+#
+# This is the config file which must be edited prior to render the CORTEXA53_unconfigured.v
+#
+# This config file was auto generated by IP Catalog:
+# Generation Date : 2024-10-04 11:18:28.687422
+# IP Catalog : ip-catalog
+#
+# declare private package
+package PARAM;
+BEGIN {}
+
+
+$parameter{NUM_CPUS} = 1; # Choose the number of CPUs in the cluster
+
+$parameter{NEON_FP} = "TRUE"; # Include the NEON & Floating-Point unit in each CPU
+
+$parameter{CRYPTO} = "FALSE"; # Include the Crypto extensions in the NEON & Floating-Point unit in each CPU
+
+$parameter{CPU_CACHE_PROTECTION} = "FALSE"; # Protect the CPU cache RAMs with parity/ECC
+
+$parameter{ACE} = "TRUE"; # Choose ACE for the main bus interface. If FALSE, CHI will be chosen.
+
+$parameter{L2_CACHE} = "TRUE"; # Include L2 Cache
+
+$parameter{ACP} = "FALSE"; # Include an ACP interface on the SCU
+
+$parameter{SCU_CACHE_PROTECTION} = "FALSE"; # Protect the L2 cache RAMs with ECC
+
+$parameter{LEGACY_V7_DEBUG_MAP} = "FALSE"; # Use a v7 memory map for the debug components
+
+ # L1 Instruction and Data Cache Size
+ #
+ # 8kB $
+ # 16kB $
+ # 32kB $
+ # 64kB $
+
+$parameter{L1_ICACHE_SIZE} = "16KB";
+$parameter{L1_DCACHE_SIZE} = "16KB";
+
+ # L2 Cache Size
+ #
+ # 128kB $
+ # 256kB $
+ # 512kB $
+ # 1024kB $
+ # 2048kB $
+
+$parameter{L2_CACHE_SIZE} = "256KB";
+
+ # L2 Data RAMs Input Latency
+ #
+ # 1 : 1 cycle latency
+ # 2 : 2 cycles latency
+
+$parameter{L2_INPUT_LATENCY} = "1";
+
+ # L2 Data RAMs Output Latency
+ #
+ # 2 : 2 cycles latency
+ # 3 : 3 cycles latency
+
+$parameter{L2_OUTPUT_LATENCY} = "2";
+
+
+
+################################################################################
+# return successful requisition
+return 1;
+
+END {}
+__END__
diff --git a/socrates/CortexA53_1/CortexA53_1.xml b/socrates/CortexA53_1/CortexA53_1.xml
deleted file mode 100644
index df65dfd421f823c5f62c25654195b21fc74c980c..0000000000000000000000000000000000000000
--- a/socrates/CortexA53_1/CortexA53_1.xml
+++ /dev/null
@@ -1,671 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<ConfiguredComponent version="r1p0">
- <Name>CortexA53_1</Name>
- <Suffix>1</Suffix>
- <ConfigurationGroupName></ConfigurationGroupName>
- <ConfigurableComponentRef>
- <Vendor>arm.com</Vendor>
- <Library>Cores</Library>
- <Name>CortexA53</Name>
- <Version>r0p4-52rel0</Version>
- </ConfigurableComponentRef>
- <Specification>
- <Parameters>
- <Parameter>
- <Name>L2_CACHE</Name>
- <Value>TRUE</Value>
- </Parameter>
- <Parameter>
- <Name>ACP</Name>
- <Value>FALSE</Value>
- </Parameter>
- <Parameter>
- <Name>ACE</Name>
- <Value>TRUE</Value>
- </Parameter>
- <Parameter>
- <Name>L1_ICACHE_SIZE</Name>
- <Value>16KB</Value>
- </Parameter>
- <Parameter>
- <Name>SCU_CACHE_PROTECTION</Name>
- <Value>FALSE</Value>
- </Parameter>
- <Parameter>
- <Name>L2_OUTPUT_LATENCY</Name>
- <Value>2</Value>
- </Parameter>
- <Parameter>
- <Name>L1_DCACHE_SIZE</Name>
- <Value>16KB</Value>
- </Parameter>
- <Parameter>
- <Name>CPU_CACHE_PROTECTION</Name>
- <Value>FALSE</Value>
- </Parameter>
- <Parameter>
- <Name>LEGACY_V7_DEBUG_MAP</Name>
- <Value>FALSE</Value>
- </Parameter>
- <Parameter>
- <Name>L2_CACHE_SIZE</Name>
- <Value>256KB</Value>
- </Parameter>
- <Parameter>
- <Name>L2_INPUT_LATENCY</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>NUM_CPUS</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>CRYPTO</Name>
- <Value>FALSE</Value>
- </Parameter>
- <Parameter>
- <Name>NEON_FP</Name>
- <Value>TRUE</Value>
- </Parameter>
- </Parameters>
- <Domains>
- <VoltageDomains>
- <VoltageDomain>
- <Name>vd0</Name>
- <UID>VD-vd0</UID>
- </VoltageDomain>
- </VoltageDomains>
- <PowerDomains>
- <PowerDomain>
- <Name>pd0</Name>
- <UID>PD-pd0</UID>
- <Type>AlwaysOn</Type>
- <VoltageDomainRef>VD-vd0</VoltageDomainRef>
- </PowerDomain>
- </PowerDomains>
- <ClockDomains>
- <ClockDomain>
- <Name>CLKIN</Name>
- <UID>CD-CLKIN</UID>
- <PowerDomainRef>PD-pd0</PowerDomainRef>
- </ClockDomain>
- </ClockDomains>
- </Domains>
- <Interfaces>
- <Interface>
- <Name>interrupt_master_VCPU_MNT_IRQ0</Name>
- <UID>IF-interrupt_master_VCPU_MNT_IRQ0</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>TimerEventInterface_master_CPU0</Name>
- <UID>IF-TimerEventInterface_master_CPU0</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>TimerEventInterface</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>ATB_master_CPU0</Name>
- <UID>IF-ATB_master_CPU0</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>ATB4</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>ATBDataWidth</Name>
- <Value>32</Value>
- </Parameter>
- <Parameter>
- <Name>ATBytesWidth</Name>
- <Value>2</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>AXI4Stream_master_PROCESSOR</Name>
- <UID>IF-AXI4Stream_master_PROCESSOR</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>AXI4Stream</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>TDATAWidth</Name>
- <Value>16</Value>
- </Parameter>
- <Parameter>
- <Name>TIDWidth</Name>
- <Value>2</Value>
- </Parameter>
- <Parameter>
- <Name>TDESTWidth</Name>
- <Value>0</Value>
- </Parameter>
- <Parameter>
- <Name>TUSERWidth</Name>
- <Value>0</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>Channel_master_CTI_CHOUT</Name>
- <UID>IF-Channel_master_CTI_CHOUT</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>Channel</ProtocolRef>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>Channel_master_CTI_IRQ0</Name>
- <UID>IF-Channel_master_CTI_IRQ0</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>Channel</ProtocolRef>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>ACE_master</Name>
- <UID>IF-ACE_master</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>ACE</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>ADDR_WIDTH</Name>
- <Value>44</Value>
- </Parameter>
- <Parameter>
- <Name>DATA_WIDTH</Name>
- <Value>128</Value>
- </Parameter>
- <Parameter>
- <Name>ID_R_WIDTH</Name>
- <Value>5</Value>
- </Parameter>
- <Parameter>
- <Name>ID_W_WIDTH</Name>
- <Value>5</Value>
- </Parameter>
- <Parameter>
- <Name>AWUSER_WIDTH</Name>
- <Value>0</Value>
- </Parameter>
- <Parameter>
- <Name>ARUSER_WIDTH</Name>
- <Value>0</Value>
- </Parameter>
- <Parameter>
- <Name>WUSER_WIDTH</Name>
- <Value>0</Value>
- </Parameter>
- <Parameter>
- <Name>RUSER_WIDTH</Name>
- <Value>0</Value>
- </Parameter>
- <Parameter>
- <Name>BUSER_WIDTH</Name>
- <Value>0</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>interrupt_master_COMMIRQ0</Name>
- <UID>IF-interrupt_master_COMMIRQ0</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_master_PMU_IRQ0</Name>
- <UID>IF-interrupt_master_PMU_IRQ0</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_master_EXTERRIRQ</Name>
- <UID>IF-interrupt_master_EXTERRIRQ</UID>
- <Requester/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_FIQ0</Name>
- <UID>IF-interrupt_slave_FIQ0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>AXI4Stream_slave_DISTRIBUTOR</Name>
- <UID>IF-AXI4Stream_slave_DISTRIBUTOR</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>AXI4Stream</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>TDATAWidth</Name>
- <Value>16</Value>
- </Parameter>
- <Parameter>
- <Name>TIDWidth</Name>
- <Value>0</Value>
- </Parameter>
- <Parameter>
- <Name>TDESTWidth</Name>
- <Value>2</Value>
- </Parameter>
- <Parameter>
- <Name>TUSERWidth</Name>
- <Value>0</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>RESET_slave_CPU_PORESET0</Name>
- <UID>IF-RESET_slave_CPU_PORESET0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>RESET</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>APB_slave_DEBUG</Name>
- <UID>IF-APB_slave_DEBUG</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>APB</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>AddressWidth</Name>
- <Value>21</Value>
- </Parameter>
- <Parameter>
- <Name>DataWidth</Name>
- <Value>32</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>Q-Channel_slave_L2</Name>
- <UID>IF-Q-Channel_slave_L2</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Q-Channel-generic</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_CFGEND0</Name>
- <UID>IF-Staticcfg_slave_CFGEND0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Q-Channel_slave_NEON0</Name>
- <UID>IF-Q-Channel_slave_NEON0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Q-Channel-generic</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_CFGTE0</Name>
- <UID>IF-Staticcfg_slave_CFGTE0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_VIRQ0</Name>
- <UID>IF-interrupt_slave_VIRQ0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_VFIQ0</Name>
- <UID>IF-interrupt_slave_VFIQ0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_VINITHI0</Name>
- <UID>IF-Staticcfg_slave_VINITHI0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>RESET_slave_MBIST</Name>
- <UID>IF-RESET_slave_MBIST</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>RESET</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_CLUSTERIDAFF1</Name>
- <UID>IF-Staticcfg_slave_CLUSTERIDAFF1</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Authentication_slave_CPU0</Name>
- <UID>IF-Authentication_slave_CPU0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Authentication</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_CP15SDISABLE0</Name>
- <UID>IF-Staticcfg_slave_CP15SDISABLE0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Channel_slave_CTI_CHIN</Name>
- <UID>IF-Channel_slave_CTI_CHIN</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Channel</ProtocolRef>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_SYSBARDISABLE</Name>
- <UID>IF-Staticcfg_slave_SYSBARDISABLE</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_GICC_DISABLE</Name>
- <UID>IF-Staticcfg_slave_GICC_DISABLE</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_AA64nAA32_CPU0</Name>
- <UID>IF-Staticcfg_slave_AA64nAA32_CPU0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_BROADCASTINNER</Name>
- <UID>IF-Staticcfg_slave_BROADCASTINNER</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>RESET_slave_CORE_RESET0</Name>
- <UID>IF-RESET_slave_CORE_RESET0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>RESET</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_SEI0</Name>
- <UID>IF-interrupt_slave_SEI0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_CLUSTERIDAFF2</Name>
- <UID>IF-Staticcfg_slave_CLUSTERIDAFF2</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_BROADCASTCACHEMAINT</Name>
- <UID>IF-Staticcfg_slave_BROADCASTCACHEMAINT</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_IRQ0</Name>
- <UID>IF-interrupt_slave_IRQ0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>RESET_slave_L2</Name>
- <UID>IF-RESET_slave_L2</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>RESET</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_VSEI0</Name>
- <UID>IF-interrupt_slave_VSEI0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>EVENT_slave_EDBGRQ0</Name>
- <UID>IF-EVENT_slave_EDBGRQ0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>EVENT</ProtocolRef>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_DBGROMADDR</Name>
- <UID>IF-Staticcfg_slave_DBGROMADDR</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Q-Channel_slave_CPU0</Name>
- <UID>IF-Q-Channel_slave_CPU0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Q-Channel-generic</ProtocolRef>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_BROADCASTOUTER</Name>
- <UID>IF-Staticcfg_slave_BROADCASTOUTER</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_RVB_ARADDR0</Name>
- <UID>IF-Staticcfg_slave_RVB_ARADDR0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>WTimestamp_slave</Name>
- <UID>IF-WTimestamp_slave</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>WTimestamp</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>TSVALUE_WIDTH</Name>
- <Value>64</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- <ClockDomainRef>CD-CLKIN</ClockDomainRef>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_DBGROMADDRV</Name>
- <UID>IF-Staticcfg_slave_DBGROMADDRV</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>Staticcfg_slave_PERIPHBASE</Name>
- <UID>IF-Staticcfg_slave_PERIPHBASE</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>Staticcfg</ProtocolRef>
- <Parameters>
- <Parameter>
- <Name>CONFIGURATION_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- </Protocol>
- </Interface>
- <Interface>
- <Name>interrupt_slave_REI0</Name>
- <UID>IF-interrupt_slave_REI0</UID>
- <Completer/>
- <Protocol>
- <ProtocolRef>interrupt</ProtocolRef>
- </Protocol>
- </Interface>
- </Interfaces>
- </Specification>
-</ConfiguredComponent>
diff --git a/socrates/sie300/sie300_axi5_sram_ctrl_1/sie300_axi5_sram_ctrl_1.xml b/socrates/sie300/sie300_axi5_sram_ctrl_1/sie300_axi5_sram_ctrl_1.xml
deleted file mode 100644
index 1e38efdc21855bfbd3a4046139a095c2787db215..0000000000000000000000000000000000000000
--- a/socrates/sie300/sie300_axi5_sram_ctrl_1/sie300_axi5_sram_ctrl_1.xml
+++ /dev/null
@@ -1,111 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<ConfiguredComponent version="r1p0">
- <Name>sie300_axi5_sram_ctrl_1</Name>
- <Suffix>1</Suffix>
- <ConfigurationGroupName>sie300</ConfigurationGroupName>
- <ConfigurableComponentRef>
- <Vendor>arm.com</Vendor>
- <Library>CoreLink</Library>
- <Name>sie300_axi5_sram_ctrl</Name>
- <Version>r1p0_0</Version>
- </ConfigurableComponentRef>
- <Specification>
- <Parameters>
- <Parameter>
- <Name>ADDR_WIDTH</Name>
- <Value>20</Value>
- </Parameter>
- <Parameter>
- <Name>DATA_WIDTH</Name>
- <Value>64</Value>
- </Parameter>
- <Parameter>
- <Name>ID_WIDTH</Name>
- <Value>6</Value>
- </Parameter>
- <Parameter>
- <Name>QCLK_SYNC_EN</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>QPWR_SYNC_EN</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>QEXT_SYNC_EN</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>EXCLUSIVE_MONITORS</Name>
- <Value>2</Value>
- </Parameter>
- <Parameter>
- <Name>AR_BUF_SIZE</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>AW_BUF_SIZE</Name>
- <Value>2</Value>
- </Parameter>
- <Parameter>
- <Name>W_BUF_SIZE</Name>
- <Value>8</Value>
- </Parameter>
- <Parameter>
- <Name>AXI5_POISON_EN</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>REGISTER_AXI_AR</Name>
- <Value>BYPASS</Value>
- </Parameter>
- <Parameter>
- <Name>REGISTER_AXI_R</Name>
- <Value>BYPASS</Value>
- </Parameter>
- <Parameter>
- <Name>STRB_WIDTH</Name>
- <Value>8</Value>
- </Parameter>
- <Parameter>
- <Name>POIS_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>AW_CNTR_WIDTH</Name>
- <Value>5</Value>
- </Parameter>
- <Parameter>
- <Name>MDAT_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- <Parameter>
- <Name>MSTR_WIDTH</Name>
- <Value>1</Value>
- </Parameter>
- </Parameters>
- <Domains>
- <VoltageDomains>
- <VoltageDomain>
- <Name>vd0</Name>
- <UID>VD-vd0</UID>
- </VoltageDomain>
- </VoltageDomains>
- <PowerDomains>
- <PowerDomain>
- <Name>pd0</Name>
- <UID>PD-pd0</UID>
- <Type>AlwaysOn</Type>
- <VoltageDomainRef>VD-vd0</VoltageDomainRef>
- </PowerDomain>
- </PowerDomains>
- <ClockDomains>
- <ClockDomain>
- <Name>clk0</Name>
- <UID>CD-clk0</UID>
- <PowerDomainRef>PD-pd0</PowerDomainRef>
- </ClockDomain>
- </ClockDomains>
- </Domains>
- </Specification>
-</ConfiguredComponent>