diff --git a/flist/megasoc_tech_BEHAV.flist b/flist/megasoc_tech_BEHAV.flist
index 51769c06b89b6dd72c83fd5c3634bb4b6dfbd7c4..4adcd79e132d4144ef522184462b4ba336ede1b8 100644
--- a/flist/megasoc_tech_BEHAV.flist
+++ b/flist/megasoc_tech_BEHAV.flist
@@ -18,6 +18,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/meg
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/behavioural/ROM_wrapper.v
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM_wrapper.v
diff --git a/flist/megasoc_tech_FPGA.flist b/flist/megasoc_tech_FPGA.flist
index 5e1fd497a1a5a8a023af38857bc3146bd56d7d49..051caecbdd192120e86ff7371cb946aaf620534b 100644
--- a/flist/megasoc_tech_FPGA.flist
+++ b/flist/megasoc_tech_FPGA.flist
@@ -17,9 +17,10 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/top_megasoc_tech/megasoc_tech_wrapper.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/ROM_wrapper.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/behavioural/ROM_wrapper.v
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/logical/SRAM.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/logical/SRAM_wrapper.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/fpga/SRAM_wrapper.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
diff --git a/logical/DRAM/behavioural/megasoc_dram_wrapper.v b/logical/DRAM/behavioural/megasoc_dram_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..b1d6dd906780519f197822b848df52a10fc8910e
--- /dev/null
+++ b/logical/DRAM/behavioural/megasoc_dram_wrapper.v
@@ -0,0 +1,84 @@
+
+module megasoc_dram_wrapper #(
+ parameter ID_W=6
+ )(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire [ID_W-1:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [3:0] AWCACHE,
+ input wire [2:0] AWPROT,
+ input wire AWVALID,
+ output wire AWREADY,
+
+ input wire [63:0] WDATA,
+ input wire [7:0] WSTRB,
+ input wire WLAST,
+ input wire WVALID,
+ output wire WREADY,
+
+ output wire [ID_W-1:0] BID,
+ output wire [1:0] BRESP,
+ output wire BVALID,
+ input wire BREADY,
+
+ input wire [ID_W-1:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [3:0] ARCACHE,
+ input wire [2:0] ARPROT,
+ input wire ARVALID,
+ output wire ARREADY,
+
+ output wire [ID_W-1:0] RID,
+ output wire [63:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire RVALID,
+ input wire RREADY,
+
+ // DDR4 signals
+ output wire DDR4_CK_T,
+ output wire DDR4_CK_C,
+
+ output wire [16:0] DDR4_ADR,
+ output wire [1:0] DDR4_BA,
+ output wire [1:0] DDR4_BG,
+
+ output wire DDR4_ACT_n,
+ output wire [1:0] DDR4_CKE,
+ output wire [1:0] DDR4_CS_N,
+ output wire [1:0] DDR4_ODT,
+ output wire DDR_PARITY,
+
+ input wire [63:0] DDR4_DQ_I,
+ output wire [63:0] DDR4_DQ_O,
+ output wire DDR4_DQ_E,
+ input wire [7:0] DDR4_DM_DBI_N_I,
+ output wire [7:0] DDR4_DM_DBI_N_O,
+ output wire DDR4_DM_DBI_E,
+ input wire [7:0] DDR4_DQS_T_I,
+ output wire [7:0] DDR4_DQS_T_O,
+ output wire DDR4_DQS_T_E,
+ input wire [7:0] DDR4_DQS_C_I,
+ output wire [7:0] DDR4_DQS_C_O,
+ output wire DDR4_DQS_C_E,
+
+ output wire DDR4_RESET_N,
+
+ input wire DDR_nALERT,
+ input wire DDR_nEVENT
+);
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/logical/DRAM/fpga/megasoc_dram_wrapper.v b/logical/DRAM/fpga/megasoc_dram_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..b1d6dd906780519f197822b848df52a10fc8910e
--- /dev/null
+++ b/logical/DRAM/fpga/megasoc_dram_wrapper.v
@@ -0,0 +1,84 @@
+
+module megasoc_dram_wrapper #(
+ parameter ID_W=6
+ )(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire [ID_W-1:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [3:0] AWCACHE,
+ input wire [2:0] AWPROT,
+ input wire AWVALID,
+ output wire AWREADY,
+
+ input wire [63:0] WDATA,
+ input wire [7:0] WSTRB,
+ input wire WLAST,
+ input wire WVALID,
+ output wire WREADY,
+
+ output wire [ID_W-1:0] BID,
+ output wire [1:0] BRESP,
+ output wire BVALID,
+ input wire BREADY,
+
+ input wire [ID_W-1:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [3:0] ARCACHE,
+ input wire [2:0] ARPROT,
+ input wire ARVALID,
+ output wire ARREADY,
+
+ output wire [ID_W-1:0] RID,
+ output wire [63:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire RVALID,
+ input wire RREADY,
+
+ // DDR4 signals
+ output wire DDR4_CK_T,
+ output wire DDR4_CK_C,
+
+ output wire [16:0] DDR4_ADR,
+ output wire [1:0] DDR4_BA,
+ output wire [1:0] DDR4_BG,
+
+ output wire DDR4_ACT_n,
+ output wire [1:0] DDR4_CKE,
+ output wire [1:0] DDR4_CS_N,
+ output wire [1:0] DDR4_ODT,
+ output wire DDR_PARITY,
+
+ input wire [63:0] DDR4_DQ_I,
+ output wire [63:0] DDR4_DQ_O,
+ output wire DDR4_DQ_E,
+ input wire [7:0] DDR4_DM_DBI_N_I,
+ output wire [7:0] DDR4_DM_DBI_N_O,
+ output wire DDR4_DM_DBI_E,
+ input wire [7:0] DDR4_DQS_T_I,
+ output wire [7:0] DDR4_DQS_T_O,
+ output wire DDR4_DQS_T_E,
+ input wire [7:0] DDR4_DQS_C_I,
+ output wire [7:0] DDR4_DQS_C_O,
+ output wire DDR4_DQS_C_E,
+
+ output wire DDR4_RESET_N,
+
+ input wire DDR_nALERT,
+ input wire DDR_nEVENT
+);
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/logical/ROM/behavioural/ROM_wrapper.v b/logical/ROM/behavioural/ROM_wrapper.v
index 9a98e98d88bbb8f4b73d3780cc161ea966c454f8..b490ed0a15ba971b901463b427e6fef7d2483499 100644
--- a/logical/ROM/behavioural/ROM_wrapper.v
+++ b/logical/ROM/behavioural/ROM_wrapper.v
@@ -134,20 +134,18 @@ sie300_axi5_sram_ctrl_1 u_SMC(
.ext_gt_qacceptn(ext_gt_qacceptn),
.cfg_gate_resp(cfg_gate_resp),
.memaddr(memaddr),
- .memd(memd),
+ .memd(),
.memq(memq),
.memcen(memcen),
.memwen(memwen)
);
-SRAM #(.MEM_DEPTH(1<<14)) u_ROM (
- .clk(ACLK),
- .memaddr(memaddr),
- .memd(memd),
- .memq(memq),
- .memcen(memcen),
- .memwen(memwen)
-);
+bootrom u_ROM (
+ .CLK(ACLK),
+ .W_ADDR(memaddr[19:3]),
+ .RDATA(memq),
+ .EN(~memcen)
+ );
endmodule
\ No newline at end of file
diff --git a/logical/ROM/fpga/ROM_wrapper.v b/logical/ROM/fpga/ROM_wrapper.v
deleted file mode 100644
index 5ca6f54013a761a955bc85d535ad257788bdeb67..0000000000000000000000000000000000000000
--- a/logical/ROM/fpga/ROM_wrapper.v
+++ /dev/null
@@ -1,162 +0,0 @@
-//-----------------------------------------------------------------------------
-// Expansion Subsystem SRAM Wrapper
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// Daniel Newbrook (d.newbrook@soton.ac.uk)
-//
-// Copyright � 2021-4, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// Modules instantiated:
-// sie300_axi5_sram_ctrl_expansion_subsystem
-// SRAM
-
-module ROM_wrapper(
- input wire ACLK,
- input wire ARESETn,
-
- input wire AWVALID,
- output wire AWREADY,
- input wire [5:0] AWID,
- input wire [31:0] AWADDR,
- input wire [7:0] AWLEN,
- input wire [2:0] AWSIZE,
- input wire [1:0] AWBURST,
- input wire AWLOCK,
- input wire [2:0] AWPROT,
- input wire [3:0] AWQOS,
-
- input wire WVALID,
- output wire WREADY,
- input wire [63:0] WDATA,
- input wire [7:0] WSTRB,
- input wire WLAST,
- input wire WPOISON,
-
- output wire BVALID,
- input wire BREADY,
- output wire [5:0] BID,
- output wire [1:0] BRESP,
-
- input wire ARVALID,
- output wire ARREADY,
- input wire [5:0] ARID,
- input wire [31:0] ARADDR,
- input wire [7:0] ARLEN,
- input wire [2:0] ARSIZE,
- input wire [1:0] ARBURST,
- input wire ARLOCK,
- input wire [2:0] ARPROT,
- input wire [3:0] ARQOS,
-
- output wire RVALID,
- input wire RREADY,
- output wire [5:0] RID,
- output wire [63:0] RDATA,
- output wire [1:0] RRESP,
- output wire RLAST,
- output wire RPOISON,
- input wire AWAKEUP,
-
- input wire clk_qreqn,
- output wire clk_qacceptn,
- output wire clk_qdeny,
- output wire clk_qactive,
-
- input wire pwr_qreqn,
- output wire pwr_qacceptn,
- output wire pwr_qdeny,
- output wire pwr_qactive,
-
- input wire ext_gt_qreqn,
- output wire ext_gt_qacceptn,
- input wire cfg_gate_resp
-);
-
-
-wire [19:0] memaddr;
-wire [64:0] memd;
-wire [64:0] memq;
-wire memcen;
-wire [7:0] memwen;
-
-sie300_axi5_sram_ctrl_1 u_SMC(
- .aclk(ACLK),
- .aresetn(ARESETn),
- .awvalid_s(AWVALID),
- .awready_s(AWREADY),
- .awid_s(AWID),
- .awaddr_s(AWADDR[19:0]),
- .awlen_s(AWLEN),
- .awsize_s(AWSIZE),
- .awburst_s(AWBURST),
- .awlock_s(AWLOCK),
- .awprot_s(AWPROT),
- .awqos_s(AWQOS),
- .wvalid_s(WVALID),
- .wready_s(WREADY),
- .wdata_s(WDATA),
- .wstrb_s(WSTRB),
- .wlast_s(WLAST),
- .wpoison_s(WPOISON),
- .bvalid_s(BVALID),
- .bready_s(BREADY),
- .bid_s(BID),
- .bresp_s(BRESP),
- .arvalid_s(ARVALID),
- .arready_s(ARREADY),
- .arid_s(ARID),
- .araddr_s(ARADDR[19:0]),
- .arlen_s(ARLEN),
- .arsize_s(ARSIZE),
- .arburst_s(ARBURST),
- .arlock_s(ARLOCK),
- .arprot_s(ARPROT),
- .arqos_s(ARQOS),
- .rvalid_s(RVALID),
- .rready_s(RREADY),
- .rid_s(RID),
- .rdata_s(RDATA),
- .rresp_s(RRESP),
- .rlast_s(RLAST),
- .rpoison_s(RPOISON),
- .awakeup_s(AWAKEUP),
- .clk_qreqn(clk_qreqn),
- .clk_qacceptn(clk_qacceptn),
- .clk_qdeny(clk_qdeny),
- .clk_qactive(clk_qactive),
- .pwr_qreqn(pwr_qreqn),
- .pwr_qacceptn(pwr_qacceptn),
- .pwr_qdeny(pwr_qdeny),
- .pwr_qactive(pwr_qactive),
- .ext_gt_qreqn(ext_gt_qreqn),
- .ext_gt_qacceptn(ext_gt_qacceptn),
- .cfg_gate_resp(cfg_gate_resp),
- .memaddr(memaddr),
- .memd(memd),
- .memq(memq),
- .memcen(memcen),
- .memwen(memwen)
-);
-
-cmsdk_fpga_sram #(.AW(15)) u_fpga_sram_0(
- .CLK(ACLK),
- .ADDR(memaddr),
- .WDATA(memd[31:0]),
- .WREN(memwen[3:0]),
- .CS(memcen),
- .RDATA(memq[31:0])
-);
-
-cmsdk_fpga_sram #(.AW(15)) u_fpga_sram_1(
- .CLK(ACLK),
- .ADDR(memaddr),
- .WDATA(memd[63:32]),
- .WREN(memwen[7:4]),
- .CS(memcen),
- .RDATA(memq[63:32])
-);
-
-
-endmodule
\ No newline at end of file
diff --git a/logical/SRAM/logical/SRAM_wrapper.v b/logical/SRAM/fpga/SRAM_wrapper.v
similarity index 100%
rename from logical/SRAM/logical/SRAM_wrapper.v
rename to logical/SRAM/fpga/SRAM_wrapper.v
diff --git a/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v b/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
index 387800e6b113f7e85f9746a0d5a8dcb4045d38d4..7ddd5e40554d059a316d12ef1b43e141d2f69f0e 100644
--- a/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
+++ b/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
@@ -158,7 +158,7 @@ module megasoc_cpu_ss #(
assign cfg_aa64naa32 = {NUM_CPUS{1'b1}};
assign cfg_vinithi = {NUM_CPUS{1'b1}};
assign cfg_cfgte = {NUM_CPUS{1'b1}};
- assign cfg_periphbase = 22'b0000000001000000000000;
+ assign cfg_periphbase = 22'h000044; // Base address for GIC 0x01100000UL
assign cfg_clusterid = 8'h00;
@@ -217,7 +217,7 @@ module megasoc_cpu_ss #(
.nVSEI ({NUM_CPUS{1'b1}}),
.nREI ({NUM_CPUS{1'b1}}),
.nVCPUMNTIRQ (),
- .PERIPHBASE (cfg_periphbase),
+ .PERIPHBASE (cfg_periphbase), // Base address for GIC
.GICCDISABLE (1'b1),
.ICDTVALID (1'b0),
.ICDTREADY (),
@@ -364,8 +364,8 @@ module megasoc_cpu_ss #(
.PSLVERRDBG (PSLVERRDBG_CPU),
// Miscellaneous debug signals
- .DBGROMADDR ({28{1'b0}}),
- .DBGROMADDRV (1'b0),
+ .DBGROMADDR (28'h0060000), //0x60000000
+ .DBGROMADDRV (1'b1),
.DBGACK (),
.nCOMMIRQ (),
.COMMRX (),
diff --git a/logical/sl_ahb_qspi b/logical/sl_ahb_qspi
index 85fdd66f1e488f4e689b62a7afe14f4f26d567ad..bd0c4aa7cca45ea538739faabc45ffe15a84ddf8 160000
--- a/logical/sl_ahb_qspi
+++ b/logical/sl_ahb_qspi
@@ -1 +1 @@
-Subproject commit 85fdd66f1e488f4e689b62a7afe14f4f26d567ad
+Subproject commit bd0c4aa7cca45ea538739faabc45ffe15a84ddf8
diff --git a/logical/top_megasoc_tech/megasoc_tech_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
index 031913ddc5bd676a3cda6f0832c5993c62d6fc74..339dc4490ce4f4446fe274b2ef53358846fe7e90 100644
--- a/logical/top_megasoc_tech/megasoc_tech_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
@@ -71,41 +71,41 @@ module megasoc_tech_wrapper(
// Millisoc system AXI Subordinate
- input wire AXI_EXP_SYS_awid,
- input wire [31:0] AXI_EXP_SYS_awaddr,
- input wire [7:0] AXI_EXP_SYS_awlen,
- input wire [2:0] AXI_EXP_SYS_awsize,
- input wire [1:0] AXI_EXP_SYS_awburst,
- input wire AXI_EXP_SYS_awlock,
- input wire [3:0] AXI_EXP_SYS_awcache,
- input wire [2:0] AXI_EXP_SYS_awprot,
- input wire AXI_EXP_SYS_awvalid,
- output wire AXI_EXP_SYS_awready,
- input wire [63:0] AXI_EXP_SYS_wdata,
- input wire [7:0] AXI_EXP_SYS_wstrb,
- input wire AXI_EXP_SYS_wlast,
- input wire AXI_EXP_SYS_wvalid,
- output wire AXI_EXP_SYS_wready,
- output wire AXI_EXP_SYS_bid,
- output wire [1:0] AXI_EXP_SYS_bresp,
- output wire AXI_EXP_SYS_bvalid,
- input wire AXI_EXP_SYS_bready,
- input wire AXI_EXP_SYS_arid,
- input wire [31:0] AXI_EXP_SYS_araddr,
- input wire [7:0] AXI_EXP_SYS_arlen,
- input wire [2:0] AXI_EXP_SYS_arsize,
- input wire [1:0] AXI_EXP_SYS_arburst,
- input wire AXI_EXP_SYS_arlock,
- input wire [3:0] AXI_EXP_SYS_arcache,
- input wire [2:0] AXI_EXP_SYS_arprot,
- input wire AXI_EXP_SYS_arvalid,
- output wire AXI_EXP_SYS_arready,
- output wire AXI_EXP_SYS_rid,
- output wire [63:0] AXI_EXP_SYS_rdata,
- output wire [1:0] AXI_EXP_SYS_rresp,
- output wire AXI_EXP_SYS_rlast,
- output wire AXI_EXP_SYS_rvalid,
- input wire AXI_EXP_SYS_rready,
+ input wire AXI_EXP_SYS_awid,
+ input wire [31:0] AXI_EXP_SYS_awaddr,
+ input wire [7:0] AXI_EXP_SYS_awlen,
+ input wire [2:0] AXI_EXP_SYS_awsize,
+ input wire [1:0] AXI_EXP_SYS_awburst,
+ input wire AXI_EXP_SYS_awlock,
+ input wire [3:0] AXI_EXP_SYS_awcache,
+ input wire [2:0] AXI_EXP_SYS_awprot,
+ input wire AXI_EXP_SYS_awvalid,
+ output wire AXI_EXP_SYS_awready,
+ input wire [63:0] AXI_EXP_SYS_wdata,
+ input wire [7:0] AXI_EXP_SYS_wstrb,
+ input wire AXI_EXP_SYS_wlast,
+ input wire AXI_EXP_SYS_wvalid,
+ output wire AXI_EXP_SYS_wready,
+ output wire AXI_EXP_SYS_bid,
+ output wire [1:0] AXI_EXP_SYS_bresp,
+ output wire AXI_EXP_SYS_bvalid,
+ input wire AXI_EXP_SYS_bready,
+ input wire AXI_EXP_SYS_arid,
+ input wire [31:0] AXI_EXP_SYS_araddr,
+ input wire [7:0] AXI_EXP_SYS_arlen,
+ input wire [2:0] AXI_EXP_SYS_arsize,
+ input wire [1:0] AXI_EXP_SYS_arburst,
+ input wire AXI_EXP_SYS_arlock,
+ input wire [3:0] AXI_EXP_SYS_arcache,
+ input wire [2:0] AXI_EXP_SYS_arprot,
+ input wire AXI_EXP_SYS_arvalid,
+ output wire AXI_EXP_SYS_arready,
+ output wire AXI_EXP_SYS_rid,
+ output wire [63:0] AXI_EXP_SYS_rdata,
+ output wire [1:0] AXI_EXP_SYS_rresp,
+ output wire AXI_EXP_SYS_rlast,
+ output wire AXI_EXP_SYS_rvalid,
+ input wire AXI_EXP_SYS_rready,
// QSPI Signals
output wire QSPI_SCLK,
@@ -152,7 +152,7 @@ wire [ 15: 0] CPU_WSTRBM;
wire CPU_WLASTM;
wire CPU_BREADYM;
wire CPU_BVALIDM;
-wire [ 4: 0] CPU_BIDM;
+wire [ 5: 0] CPU_BIDM;
wire [ 1: 0] CPU_BRESPM;
wire CPU_ARREADYM;
wire CPU_ARVALIDM;
@@ -172,7 +172,7 @@ wire [ 1: 0] CPU_RRESPM;
wire CPU_RLASTM;
wire [ID_W-1:0] GIC_ARID;
-wire [14:0] GIC_ARADDR;
+wire [31:0] GIC_ARADDR;
wire [7:0] GIC_ARLEN;
wire [2:0] GIC_ARSIZE;
wire [1:0] GIC_ARBURST;
@@ -187,7 +187,7 @@ wire [1:0] GIC_RRESP;
wire GIC_RVALID;
wire GIC_RREADY;
wire [ID_W-1:0] GIC_AWID;
-wire [14:0] GIC_AWADDR;
+wire [31:0] GIC_AWADDR;
wire [7:0] GIC_AWLEN;
wire [2:0] GIC_AWSIZE;
wire [1:0] GIC_AWBURST;
@@ -445,7 +445,7 @@ megasoc_cpu_ss #(
.SWDOEN(SWDOEN),
.GIC_ARID(GIC_ARID),
- .GIC_ARADDR(GIC_ARADDR),
+ .GIC_ARADDR(GIC_ARADDR[14:0]),
.GIC_ARLEN(GIC_ARLEN),
.GIC_ARSIZE(GIC_ARSIZE),
.GIC_ARBURST(GIC_ARBURST),
@@ -462,7 +462,7 @@ megasoc_cpu_ss #(
.GIC_RREADY(GIC_RREADY),
.GIC_AWID(GIC_AWID),
- .GIC_AWADDR(GIC_AWADDR),
+ .GIC_AWADDR(GIC_AWADDR[14:0]),
.GIC_AWLEN(GIC_AWLEN),
.GIC_AWSIZE(GIC_AWSIZE),
.GIC_AWBURST(GIC_AWBURST),
@@ -540,14 +540,14 @@ nic400_megasoc_main u_nic400_megasoc_main(
.AWLEN_GIC(GIC_AWLEN),
.AWSIZE_GIC(GIC_AWSIZE),
.AWBURST_GIC(GIC_AWBURST),
- .AWLOCK_GIC(GIC_AWLOCK),
- .AWCACHE_GIC(GIC_AWCACHE),
+ .AWLOCK_GIC(),
+ .AWCACHE_GIC(),
.AWPROT_GIC(GIC_AWPROT),
.AWVALID_GIC(GIC_AWVALID),
.AWREADY_GIC(GIC_AWREADY),
.WDATA_GIC(GIC_WDATA),
.WSTRB_GIC(GIC_WSTRB),
- .WLAST_GIC(GIC_WLAST),
+ .WLAST_GIC(),
.WVALID_GIC(GIC_WVALID),
.WREADY_GIC(GIC_WREADY),
.BID_GIC(GIC_BID),
@@ -559,8 +559,8 @@ nic400_megasoc_main u_nic400_megasoc_main(
.ARLEN_GIC(GIC_ARLEN),
.ARSIZE_GIC(GIC_ARSIZE),
.ARBURST_GIC(GIC_ARBURST),
- .ARLOCK_GIC(GIC_ARLOCK),
- .ARCACHE_GIC(GIC_ARCACHE),
+ .ARLOCK_GIC(),
+ .ARCACHE_GIC(),
.ARPROT_GIC(GIC_ARPROT),
.ARVALID_GIC(GIC_ARVALID),
.ARREADY_GIC(GIC_ARREADY),
@@ -787,7 +787,7 @@ top_ahb_qspi #(.DATA_W(32)) u_sl_ahb_qspi(
.HREADY(HREADY_FLASH),
.HREADYOUT(HREADYOUT_FLASH),
.HRESP(HRESP_FLASH),
- .PADDR(PADDR_FLASH_CTRL),
+ .PADDR(PADDR_FLASH_CTRL[15:0]),
.PPROT(PPROT_FLASH_CTRL),
.PSEL(PSELx_FLASH_CTRL),
.PENABLE(PENABLE_FLASH_CTRL),
diff --git a/software/lib/common/Makefile.c_host b/software/lib/common/Makefile.c_host
index ea6db5c51e24a0c16563d690061c86e15c414f74..86c55d15f40d27bab62f1331c760578f61efb67e 100644
--- a/software/lib/common/Makefile.c_host
+++ b/software/lib/common/Makefile.c_host
@@ -222,7 +222,9 @@ $(BUILD_DIR)/app_flash.v8-a.hex: $(BUILD_DIR)/app.v8-a.elf
$(BUILD_DIR)/bootloader.hex: $(BUILD_DIR)/app.v8-a.elf
@echo -e "\n------------------- Executing make target $(@F) -------------------"
- $(EM) window,0x00000000,0x400000,0x00000000:vmem,64,1 $^ --compact --output $@
+ fromelf --vhx -a --output $@ $^
+ # $(EM) window,0x00000000,0x400000,0x00000000:vmem,64,1 $^ --compact --output $@
+
# ------------------------------------------------------------------------------
# End of Makefile
diff --git a/software/src/bootloader/bootrom_gen.py b/software/src/bootloader/bootrom_gen.py
new file mode 100755
index 0000000000000000000000000000000000000000..fa65f688ed02881c6e02fabcd23ed2805d5679ed
--- /dev/null
+++ b/software/src/bootloader/bootrom_gen.py
@@ -0,0 +1,124 @@
+#!/usr/bin/env python3
+#------------------------------------------------------------------------------------
+# Verilog and Binary Bootrom Generation Script
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+# Copyright (c) 2023, SoC Labs (www.soclabs.org)
+#------------------------------------------------------------------------------------
+
+import argparse
+import math
+from string import Template
+from datetime import datetime
+
+v_template_head = f"""//------------------------------------------------------------------------------------
+// Auto-generated synthesizable Bootrom
+//
+// Generated from bootrom_gen.py
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+// Date: $date
+// Copyright (c) 2021-3, SoC Labs (www.soclabs.org)
+//------------------------------------------------------------------------------------
+module bootrom (
+ input wire CLK,
+ input wire EN,
+ input wire [$word_address_width:0] W_ADDR,
+ output reg [63:0] RDATA );
+always @(posedge CLK) begin
+if (EN) begin
+ case(W_ADDR)
+"""
+
+v_template_foot = """ default : RDATA <= 64'd0;
+ endcase
+ end
+ end
+endmodule"""
+
+
+def bootrom_gen(args):
+ # Extract Data from Parsed Arguments
+ input_hex = args.input_hex
+ address_width = args.address_width
+ output_verilog = args.verilog_output
+ output_binary = args.binary_output
+
+ # Create Binary and Verilog Outputs
+ print(f"Generating Bootrom {input_hex}")
+ bootrom_verilog, bootrom_binary = output_construct(input_hex, address_width)
+
+ # Write Out Verilog File
+ f_verilog = open(output_verilog, "w")
+ f_verilog.write(bootrom_verilog)
+ f_verilog.close()
+
+ # Write Out Binary File
+ f_binary = open(output_binary, "w")
+ f_binary.write(bootrom_binary)
+ f_binary.close()
+
+def output_construct(input_hex, address_width):
+ # Read in Hex File
+ f = open(input_hex, "r")
+ hex_bytes = f.readlines()
+ f.close()
+
+ # Number of bytes expected depending on address_width
+ address_bytes = 1 << (address_width + 2)
+
+ # Fill hex_bytes with zeros for addresses than aren't in the hex file
+ while (len(hex_bytes) < address_bytes): hex_bytes.append("00")
+ hex_words = math.ceil(len(hex_bytes)/8)
+ hex_data = []
+
+ # Combine bytes into words
+ for i in range(hex_words):
+ temp_hex_word= f"{hex_bytes[i*8+7].rstrip()}{hex_bytes[(i*8)+6].rstrip()}{hex_bytes[(i*8)+5].rstrip()}{hex_bytes[(i*8)+4].rstrip()}{hex_bytes[(i*8)+3].rstrip()}{hex_bytes[(i*8)+2].rstrip()}{hex_bytes[(i*8)+1].rstrip()}{hex_bytes[(i*8)].rstrip()}"
+ hex_data.append(int(temp_hex_word, 16))
+
+ # Get Date and Time to put in Generated Header
+ date_str = datetime.today().strftime('%Y-%m-%d %H:%M:%S')
+
+ # Generate Verilog Header from Template
+ temp_bootrom_obj = Template(v_template_head)
+ temp_verilog = temp_bootrom_obj.substitute(
+ address_width=address_width+1,
+ word_address_width=address_width-1,
+ date=date_str
+ )
+ bootrom_verilog = temp_verilog
+
+ bootrom_binary = ""
+
+ # Append Hex Data to File
+ for i, word in enumerate(hex_data):
+ if address_width > 8:
+ temp_verilog = f""" {address_width:d}'h{i:03x} : RDATA <= 64'h{word:08x}; // 0x{i*8:04x}\n"""
+ else:
+ temp_verilog = f""" {address_width:d}'h{i:02x} : RDATA <= 64'h{word:08x}; // 0x{i*8:04x}\n"""
+ temp_binary = f"""{word:032b}\n"""
+ bootrom_verilog += temp_verilog
+ bootrom_binary += temp_binary
+
+ # Append footer to Verilog file
+ bootrom_verilog += v_template_foot
+
+ return bootrom_verilog, bootrom_binary
+
+if __name__ == "__main__":
+ # Capture Arguments from Command Line
+ parser = argparse.ArgumentParser(description='Generates NanoSoC CPU Bootrom File')
+ parser.add_argument("-i", "--input_hex", type=str, help="Input Hex File to Generate Bootrom from")
+ parser.add_argument("-a", "--address_width", type=int, help="Address Width (In 32bit Words) of Bootrom")
+ parser.add_argument("-v", "--verilog_output", type=str, help="Output Bootrom verilog file")
+ parser.add_argument("-b", "--binary_output", type=str, help="Output Bootrom binary file")
+ args = parser.parse_args()
+ bootrom_gen(args)
\ No newline at end of file