diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..e3ca1255d6abe4850c88b2deeca7f1c0cbedf55a
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+logical/CortexA53_1
+logical/sie300
+logical/shared
\ No newline at end of file
diff --git a/flist/megasoc_tech.flist b/flist/megasoc_tech.flist
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/logical/SRAM/logical/SRAM.v b/logical/SRAM/logical/SRAM.v
new file mode 100644
index 0000000000000000000000000000000000000000..e9d7b460d6f62885cb89a32788196f2525c25064
--- /dev/null
+++ b/logical/SRAM/logical/SRAM.v
@@ -0,0 +1,76 @@
+
+
+module SRAM (
+ input wire clk,
+ input wire [13:0] memaddr,
+ input wire [63:0] memd,
+ output wire [63:0] memq,
+ input wire memcen,
+ input wire [7:0] memwen
+);
+ parameter MEM_DEPTH = (1<<10);
+
+ wire WriteEnable; // Write data update
+ wire [10:0] Addr;
+ reg [63:0] DataAtAddress; // Current write-data at address
+ reg [63:0] Mask; // Write data-mask
+ reg [63:0] NextData; // Next write-data
+ reg [63:0] iQ; // Memory output data (pipelined)
+
+ integer i; // Write-strobe loop variable
+ integer j; // Mask-bit loop variable
+ assign Addr = memaddr[13:4];
+ // -------------
+ // Memory arrays
+ // -------------
+
+ // Memory array 0 - used in both 32-bit and 64-bit modes
+ reg [63:0] mem [MEM_DEPTH-1:0];
+ assign WriteEnable = (memwen != {8{1'b1}}) ? 1'b1 : 1'b0;
+
+ always @ (posedge clk)
+ begin : p_memaccess
+ // Only access the memory when the chip is enabled
+ if (!memcen)
+ begin
+ // Look-up the data at the current address
+ DataAtAddress[63:0] = mem[Addr];
+
+ // Update the memory and the data output only when permitted
+ if (WriteEnable)
+ begin
+
+ // Determine the byte-lane mask value by testing the individual
+ // bits of the active-low write strobes
+ for (i = 0; i < 8; i = i + 1)
+ for (j = i * 8; j <= (i * 8) + 7; j = j + 1)
+ Mask[j] = ~memwen[i];
+
+ // Determine the value of the next write-data. Term (a) clears
+ // the required byte lanes and term (b) selects the required
+ // byte-lanes of the AXI write data. The two data words are
+ // bit-wise OR'ed together to form the new data word
+ NextData = (DataAtAddress & ~Mask) | // (a)
+ (memd & Mask); // (b)
+
+ mem[Addr] = NextData[63:0]; // Always assign mem array 0
+
+ // Update the data output with new data
+ iQ <= NextData;
+
+ end
+ else
+ // Update the data output with the original data value
+ iQ <= DataAtAddress;
+
+ end
+
+
+ end
+
+
+ // Drive read data output port at the selected stage of the pipeline
+ assign memq = iQ;
+
+
+endmodule
diff --git a/logical/SRAM/logical/SRAM_wrapper.v b/logical/SRAM/logical/SRAM_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..c34c7a5bf6fd669c3e1776ce3009eea1ca9e50f6
--- /dev/null
+++ b/logical/SRAM/logical/SRAM_wrapper.v
@@ -0,0 +1,153 @@
+//-----------------------------------------------------------------------------
+// Expansion Subsystem SRAM Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// sie300_axi5_sram_ctrl_expansion_subsystem
+// SRAM
+
+module SRAM_wrapper(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire AWVALID,
+ output wire AWREADY,
+ input wire [3:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [2:0] AWPROT,
+ input wire [3:0] AWQOS,
+
+ input wire WVALID,
+ output wire WREADY,
+ input wire [63:0] WDATA,
+ input wire [7:0] WSTRB,
+ input wire WLAST,
+ input wire WPOISON,
+
+ output wire BVALID,
+ input wire BREADY,
+ output wire [3:0] BID,
+ output wire [1:0] BRESP,
+
+ input wire ARVALID,
+ output wire ARREADY,
+ input wire [3:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [2:0] ARPROT,
+ input wire [3:0] ARQOS,
+
+ output wire RVALID,
+ input wire RREADY,
+ output wire [3:0] RID,
+ output wire [63:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire [1:0] RPOISON,
+ input wire AWAKEUP,
+
+ input wire clk_qreqn,
+ output wire clk_qacceptn,
+ output wire clk_qdeny,
+ output wire clk_qactive,
+
+ input wire pwr_qreqn,
+ output wire pwr_qacceptn,
+ output wire pwr_qdeny,
+ output wire pwr_qactive,
+
+ input wire ext_gt_qreqn,
+ output wire ext_gt_qacceptn,
+ input wire cfg_gate_resp
+);
+
+
+wire [13:0] memaddr;
+wire [63:0] memd;
+wire [63:0] memq;
+wire memcen;
+wire [7:0] memwen;
+
+sie300_axi5_sram_ctrl_expansion_subsystem u_SMC(
+ .aclk(ACLK),
+ .aresetn(ARESETn),
+ .awvalid_s(AWVALID),
+ .awready_s(AWREADY),
+ .awid_s(AWID),
+ .awaddr_s(AWADDR[13:0]),
+ .awlen_s(AWLEN),
+ .awsize_s(AWSIZE),
+ .awburst_s(AWBURST),
+ .awlock_s(AWLOCK),
+ .awprot_s(AWPROT),
+ .awqos_s(AWQOS),
+ .wvalid_s(WVALID),
+ .wready_s(WREADY),
+ .wdata_s(WDATA),
+ .wstrb_s(WSTRB),
+ .wlast_s(WLAST),
+ .wpoison_s(WPOISON),
+ .bvalid_s(BVALID),
+ .bready_s(BREADY),
+ .bid_s(BID),
+ .bresp_s(BRESP),
+ .arvalid_s(ARVALID),
+ .arready_s(ARREADY),
+ .arid_s(ARID),
+ .araddr_s(ARADDR[13:0]),
+ .arlen_s(ARLEN),
+ .arsize_s(ARSIZE),
+ .arburst_s(ARBURST),
+ .arlock_s(ARLOCK),
+ .arprot_s(ARPROT),
+ .arqos_s(ARQOS),
+ .rvalid_s(RVALID),
+ .rready_s(RREADY),
+ .rid_s(RID),
+ .rdata_s(RDATA),
+ .rresp_s(RRESP),
+ .rlast_s(RLAST),
+ .rpoison_s(RPOISON),
+ .awakeup_s(AWAKEUP),
+ .clk_qreqn(clk_qreqn),
+ .clk_qacceptn(clk_qacceptn),
+ .clk_qdeny(clk_qdeny),
+ .clk_qactive(clk_qactive),
+ .pwr_qreqn(pwr_qreqn),
+ .pwr_qacceptn(pwr_qacceptn),
+ .pwr_qdeny(pwr_qdeny),
+ .pwr_qactive(pwr_qactive),
+ .ext_gt_qreqn(ext_gt_qreqn),
+ .ext_gt_qacceptn(ext_gt_qacceptn),
+ .cfg_gate_resp(cfg_gate_resp),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+SRAM u_SRAM(
+ .clk(ACLK),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+
+endmodule
\ No newline at end of file
diff --git a/logical/top_megasoc_tech/megasoc_tech_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..7799519add12261b319b349c657d54b92dc54e1e
--- /dev/null
+++ b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
@@ -0,0 +1,97 @@
+//-----------------------------------------------------------------------------
+// MegaSoC Tech Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+
+`timescale 1ns/1ps
+
+module megasoc_tech_wrapper(
+ input wire SYS_CLK,
+ input wire SYS_CLKEN,
+ input wire SYS_RESETn,
+
+ // Millisoc system AXI Manager
+ output wire [1:0] AXI_SYS_EXP_awid,
+ output wire [31:0] AXI_SYS_EXP_awaddr,
+ output wire [7:0] AXI_SYS_EXP_awlen,
+ output wire [2:0] AXI_SYS_EXP_awsize,
+ output wire [1:0] AXI_SYS_EXP_awburst,
+ output wire AXI_SYS_EXP_awlock,
+ output wire [3:0] AXI_SYS_EXP_awcache,
+ output wire [2:0] AXI_SYS_EXP_awprot,
+ output wire AXI_SYS_EXP_awvalid,
+ input wire AXI_SYS_EXP_awready,
+ output wire [63:0] AXI_SYS_EXP_wdata,
+ output wire [7:0] AXI_SYS_EXP_wstrb,
+ output wire AXI_SYS_EXP_wlast,
+ output wire AXI_SYS_EXP_wvalid,
+ input wire AXI_SYS_EXP_wready,
+ input wire [1:0] AXI_SYS_EXP_bid,
+ input wire [1:0] AXI_SYS_EXP_bresp,
+ input wire AXI_SYS_EXP_bvalid,
+ output wire AXI_SYS_EXP_bready,
+ output wire [1:0] AXI_SYS_EXP_arid,
+ output wire [31:0] AXI_SYS_EXP_araddr,
+ output wire [7:0] AXI_SYS_EXP_arlen,
+ output wire [2:0] AXI_SYS_EXP_arsize,
+ output wire [1:0] AXI_SYS_EXP_arburst,
+ output wire AXI_SYS_EXP_arlock,
+ output wire [3:0] AXI_SYS_EXP_arcache,
+ output wire [2:0] AXI_SYS_EXP_arprot,
+ output wire AXI_SYS_EXP_arvalid,
+ input wire AXI_SYS_EXP_arready,
+ input wire [1:0] AXI_SYS_EXP_rid,
+ input wire [63:0] AXI_SYS_EXP_rdata,
+ input wire [1:0] AXI_SYS_EXP_rresp,
+ input wire AXI_SYS_EXP_rlast,
+ input wire AXI_SYS_EXP_rvalid,
+ output wire AXI_SYS_EXP_rready,
+
+
+ // Millisoc system AXI Subordinate
+ input wire AXI_EXP_SYS_awid,
+ input wire [31:0] AXI_EXP_SYS_awaddr,
+ input wire [7:0] AXI_EXP_SYS_awlen,
+ input wire [2:0] AXI_EXP_SYS_awsize,
+ input wire [1:0] AXI_EXP_SYS_awburst,
+ input wire AXI_EXP_SYS_awlock,
+ input wire [3:0] AXI_EXP_SYS_awcache,
+ input wire [2:0] AXI_EXP_SYS_awprot,
+ input wire AXI_EXP_SYS_awvalid,
+ output wire AXI_EXP_SYS_awready,
+ input wire [63:0] AXI_EXP_SYS_wdata,
+ input wire [7:0] AXI_EXP_SYS_wstrb,
+ input wire AXI_EXP_SYS_wlast,
+ input wire AXI_EXP_SYS_wvalid,
+ output wire AXI_EXP_SYS_wready,
+ output wire AXI_EXP_SYS_bid,
+ output wire [1:0] AXI_EXP_SYS_bresp,
+ output wire AXI_EXP_SYS_bvalid,
+ input wire AXI_EXP_SYS_bready,
+ input wire AXI_EXP_SYS_arid,
+ input wire [31:0] AXI_EXP_SYS_araddr,
+ input wire [7:0] AXI_EXP_SYS_arlen,
+ input wire [2:0] AXI_EXP_SYS_arsize,
+ input wire [1:0] AXI_EXP_SYS_arburst,
+ input wire AXI_EXP_SYS_arlock,
+ input wire [3:0] AXI_EXP_SYS_arcache,
+ input wire [2:0] AXI_EXP_SYS_arprot,
+ input wire AXI_EXP_SYS_arvalid,
+ output wire AXI_EXP_SYS_arready,
+ output wire AXI_EXP_SYS_rid,
+ output wire [63:0] AXI_EXP_SYS_rdata,
+ output wire [1:0] AXI_EXP_SYS_rresp,
+ output wire AXI_EXP_SYS_rlast,
+ output wire AXI_EXP_SYS_rvalid,
+ input wire AXI_EXP_SYS_rready
+
+);
+
+endmodule
\ No newline at end of file
diff --git a/make.cfg b/make.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fe49a3cafc89b3b3d8ac277245570e4b881d9ae3
--- /dev/null
+++ b/make.cfg
@@ -0,0 +1,4 @@
+Cortex_M55_IP_DIR:=/research/AAA/ip_library/Cortex-M55/AT634-r1p1-00rel6-0/AT633-BU-50000-r1p1-00rel1
+SOC600_IP_DIR:=/research/AAA/ip_library/TM200/TM200-BU-50000-r4p1-00rel0/css600
+PCK_600_IP_DIR:=/research/AAA/ip_library/PCK-600/PL608-BU-50000-r0p5-00rel0/pck600
+SIE300_IP_LOGICAL_DIR:=$(ARM_IP_LIBRARY_PATH)/BP301/BP301-BU-50000-r1p2-00rel0/sie300/logical
diff --git a/makefile b/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..cdf4b487b09e5a392ad5681eac9adac603035032
--- /dev/null
+++ b/makefile
@@ -0,0 +1,36 @@
+#-----------------------------------------------------------------------------
+# megaSoC System Top-Level Makefile
+# - Includes other Makefiles in flow directory
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+include ./make.cfg
+
+build_m55:
+ $(Cortex_M55_IP_DIR)/yamin/logical/generate -config ./socrates/Cortex-M55/yamin.yaml -output ./logical/Cortex-M55 -daplite2 $(Cortex_M55_IP_DIR)/daplite2 -tpium $(Cortex_M55_IP_DIR)/tpium -verbose -pmc100 none -soc600m $(SOC600_IP_DIR)/
+build_pck600:
+ socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=pck600_clk_ctrl_1
+ socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=pck600_ppu_1
+build_sie300_sram_ctrl:
+ @$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
+build_nic400:
+ socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=nic400_millisoc_system
+build_ip:
+
+make_project:
+ socrates_cli --project megasoc_tech -data ../ --flow AddNewProject
+
+first_time_setup: make_project build_ip
+
+all: make_project build_ip
+
+clean:
+ @rm -rf ./logical/Cortex-M55
+ @rm -rf ./logical/nic400_millisoc_system
+ @rm -rf ./logical/shared
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..22a2341307b3d3e4d2bef2bad3a7b48e7e46e15d
--- /dev/null
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -0,0 +1,140 @@
+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2019 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Version Information
+#
+# Checked In : Mon Jul 15 17:15:15 2019 +0100
+#
+# Revision : 828f11fd
+#
+# Release Information : CoreLink SIE-300 Generic Global Bundle r1p2-00rel0
+#
+#----------------------------------------------------------------------------
+# Abstract : Configuration file for SIE-300 AXI5 SRAM Controller
+#----------------------------------------------------------------------------
+
+# -----------------------------
+# User Configuration
+# -----------------------------
+
+
+#
+# COMPONENT: Name of the component to configure.
+# Valid values:
+# [sie300_axi5_sram_ctrl]
+#
+COMPONENT: sie300_axi5_sram_ctrl
+
+
+#
+# CONFIG_NAME: Name of the configuration.
+# Each unifiqued element and top is suffixed with
+# _${CONFIG_NAME}
+#
+CONFIG_NAME: millisoc_sys
+
+
+#
+# ADDR_WIDTH: AXI5 Address Bus width
+# Valid values:
+# 14-24
+ADDR_WIDTH: 14
+
+
+#
+# DATA_WIDTH: AXI5 Data Bus width
+# Valid values:
+# [32,64,128,256]
+DATA_WIDTH: 64
+
+
+#
+# ID_WIDTH: AXI5 ID width for all channels
+# Valid values:
+# 2-32
+ID_WIDTH: 4
+
+
+#
+# QCLK_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
+# Valid values:
+# - 0 : no synchronizer
+# - 1 : added synchronizer
+QCLK_SYNC_EN: 1
+
+
+#
+# QPWR_SYNC_EN: Add 2 DFF synchronizer on inputs of power Q-channel
+# Valid values:
+# - 0 : no synchronizer
+# - 1 : added synchronizer
+QPWR_SYNC_EN: 1
+
+
+#
+# QEXT_SYNC_EN: Add 2 DFF synchronizer on inputs of external gating Q-channel
+# Valid values:
+# - 0 : no synchronizer
+# - 1 : added synchronizer
+QEXT_SYNC_EN: 1
+
+
+#
+# EXCLUSIVE_MONITORS: Number of Exclusive Access Monitors to observe
+# and track AXI locked transactions
+# Valid values:
+# 0-16 (0 means no locked transaction support)
+EXCLUSIVE_MONITORS: 2
+
+
+#
+# AR_BUF_SIZE: Size of FIFO on AR channel
+# Valid values:
+# 1-16
+AR_BUF_SIZE: 1
+
+
+#
+# AW_BUF_SIZE: Size of FIFO on AW channel
+# Valid values:
+# 1-16
+AW_BUF_SIZE: 2
+
+
+#
+# W_BUF_SIZE: Size of FIFO on W channel
+# Valid values:
+# 1-16
+W_BUF_SIZE: 8
+
+
+#
+# REGISTER_AXI_AR: Enables / disables register stage at the AR FIFO
+# Valid values:
+# [BYPASS,FULL]
+REGISTER_AXI_AR: BYPASS
+
+
+#
+# REGISTER_AXI_R: Enables / disables register stage at the R FIFO
+# Valid values:
+# [BYPASS,FULL]
+REGISTER_AXI_R: BYPASS
+
+
+#
+# AXI5_POISON_EN: Enables / disables AXI5 Data Poisoning support
+# Valid values:
+# [0,1]
+AXI5_POISON_EN: 0
diff --git a/socrates/CortexA53_1/CortexA53_1.xml b/socrates/CortexA53_1/CortexA53_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4044349d46a62e1444d44d2ce7be86ce608b4b19
--- /dev/null
+++ b/socrates/CortexA53_1/CortexA53_1.xml
@@ -0,0 +1,1338 @@
+<?xml version='1.0' encoding='utf-8'?>
+<ConfiguredComponent version="r1p0">
+ <Name>CortexA53_1</Name>
+ <Suffix>1</Suffix>
+ <ConfigurationGroupName></ConfigurationGroupName>
+ <ConfigurableComponentRef>
+ <Vendor>arm.com</Vendor>
+ <Library>Cores</Library>
+ <Name>CortexA53</Name>
+ <Version>r0p4-52rel0</Version>
+ </ConfigurableComponentRef>
+ <Specification>
+ <Parameters>
+ <Parameter>
+ <Name>L2_CACHE</Name>
+ <Value>TRUE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>ACP</Name>
+ <Value>TRUE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>ACE</Name>
+ <Value>FALSE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>L1_ICACHE_SIZE</Name>
+ <Value>16KB</Value>
+ </Parameter>
+ <Parameter>
+ <Name>SCU_CACHE_PROTECTION</Name>
+ <Value>FALSE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>L2_OUTPUT_LATENCY</Name>
+ <Value>2</Value>
+ </Parameter>
+ <Parameter>
+ <Name>L1_DCACHE_SIZE</Name>
+ <Value>16KB</Value>
+ </Parameter>
+ <Parameter>
+ <Name>CPU_CACHE_PROTECTION</Name>
+ <Value>FALSE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>LEGACY_V7_DEBUG_MAP</Name>
+ <Value>FALSE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>L2_CACHE_SIZE</Name>
+ <Value>512KB</Value>
+ </Parameter>
+ <Parameter>
+ <Name>L2_INPUT_LATENCY</Name>
+ <Value>1</Value>
+ </Parameter>
+ <Parameter>
+ <Name>NUM_CPUS</Name>
+ <Value>2</Value>
+ </Parameter>
+ <Parameter>
+ <Name>CRYPTO</Name>
+ <Value>FALSE</Value>
+ </Parameter>
+ <Parameter>
+ <Name>NEON_FP</Name>
+ <Value>TRUE</Value>
+ </Parameter>
+ </Parameters>
+ <Domains>
+ <VoltageDomains>
+ <VoltageDomain>
+ <Name>vd0</Name>
+ <UID>VD-vd0</UID>
+ </VoltageDomain>
+ </VoltageDomains>
+ <PowerDomains>
+ <PowerDomain>
+ <Name>pd0</Name>
+ <UID>PD-pd0</UID>
+ <Type>AlwaysOn</Type>
+ <VoltageDomainRef>VD-vd0</VoltageDomainRef>
+ </PowerDomain>
+ </PowerDomains>
+ <ClockDomains>
+ <ClockDomain>
+ <Name>CLKIN</Name>
+ <UID>CD-CLKIN</UID>
+ <PowerDomainRef>PD-pd0</PowerDomainRef>
+ </ClockDomain>
+ </ClockDomains>
+ </Domains>
+ <Interfaces>
+ <Interface>
+ <Name>interrupt_master_VCPU_MNT_IRQ0</Name>
+ <UID>IF-interrupt_master_VCPU_MNT_IRQ0</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_master_VCPU_MNT_IRQ1</Name>
+ <UID>IF-interrupt_master_VCPU_MNT_IRQ1</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>TimerEventInterface_master_CPU0</Name>
+ <UID>IF-TimerEventInterface_master_CPU0</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>TimerEventInterface</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>TimerEventInterface_master_CPU1</Name>
+ <UID>IF-TimerEventInterface_master_CPU1</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>TimerEventInterface</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>ATB_master_CPU0</Name>
+ <UID>IF-ATB_master_CPU0</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>ATB4</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>ATBDataWidth</Name>
+ <Value>32</Value>
+ </Parameter>
+ <Parameter>
+ <Name>ATBytesWidth</Name>
+ <Value>2</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>CHI-RNF_master</Name>
+ <UID>IF-CHI-RNF_master</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>CHI-RNF-r0p0_0</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>AXI4Stream_master_PROCESSOR</Name>
+ <UID>IF-AXI4Stream_master_PROCESSOR</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>AXI4Stream</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>TDATAWidth</Name>
+ <Value>16</Value>
+ </Parameter>
+ <Parameter>
+ <Name>TIDWidth</Name>
+ <Value>2</Value>
+ </Parameter>
+ <Parameter>
+ <Name>TDESTWidth</Name>
+ <Value>0</Value>
+ </Parameter>
+ <Parameter>
+ <Name>TUSERWidth</Name>
+ <Value>0</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Channel_master_CTI_CHOUT</Name>
+ <UID>IF-Channel_master_CTI_CHOUT</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>Channel</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Channel_master_CTI_IRQ0</Name>
+ <UID>IF-Channel_master_CTI_IRQ0</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>Channel</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Channel_master_CTI_IRQ1</Name>
+ <UID>IF-Channel_master_CTI_IRQ1</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>Channel</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>ATB_master_CPU1</Name>
+ <UID>IF-ATB_master_CPU1</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>ATB4</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>ATBDataWidth</Name>
+ <Value>32</Value>
+ </Parameter>
+ <Parameter>
+ <Name>ATBytesWidth</Name>
+ <Value>2</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>interrupt_master_COMMIRQ0</Name>
+ <UID>IF-interrupt_master_COMMIRQ0</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_master_COMMIRQ1</Name>
+ <UID>IF-interrupt_master_COMMIRQ1</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_master_PMU_IRQ0</Name>
+ <UID>IF-interrupt_master_PMU_IRQ0</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_master_PMU_IRQ1</Name>
+ <UID>IF-interrupt_master_PMU_IRQ1</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_master_EXTERRIRQ</Name>
+ <UID>IF-interrupt_master_EXTERRIRQ</UID>
+ <Requester/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP13</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP13</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_FIQ0</Name>
+ <UID>IF-interrupt_slave_FIQ0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_FIQ1</Name>
+ <UID>IF-interrupt_slave_FIQ1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>AXI4Stream_slave_DISTRIBUTOR</Name>
+ <UID>IF-AXI4Stream_slave_DISTRIBUTOR</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>AXI4Stream</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>TDATAWidth</Name>
+ <Value>16</Value>
+ </Parameter>
+ <Parameter>
+ <Name>TIDWidth</Name>
+ <Value>0</Value>
+ </Parameter>
+ <Parameter>
+ <Name>TDESTWidth</Name>
+ <Value>2</Value>
+ </Parameter>
+ <Parameter>
+ <Name>TUSERWidth</Name>
+ <Value>0</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF1_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF1_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>RESET_slave_CPU_PORESET0</Name>
+ <UID>IF-RESET_slave_CPU_PORESET0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>RESET</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>RESET_slave_CPU_PORESET1</Name>
+ <UID>IF-RESET_slave_CPU_PORESET1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>RESET</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>APB_slave_DEBUG</Name>
+ <UID>IF-APB_slave_DEBUG</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>APB</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>AddressWidth</Name>
+ <Value>21</Value>
+ </Parameter>
+ <Parameter>
+ <Name>DataWidth</Name>
+ <Value>32</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Q-Channel_slave_L2</Name>
+ <UID>IF-Q-Channel_slave_L2</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Q-Channel-generic</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CFGEND0</Name>
+ <UID>IF-Staticcfg_slave_CFGEND0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CFGEND1</Name>
+ <UID>IF-Staticcfg_slave_CFGEND1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Q-Channel_slave_NEON0</Name>
+ <UID>IF-Q-Channel_slave_NEON0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Q-Channel-generic</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Q-Channel_slave_NEON1</Name>
+ <UID>IF-Q-Channel_slave_NEON1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Q-Channel-generic</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CFGTE0</Name>
+ <UID>IF-Staticcfg_slave_CFGTE0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CFGTE1</Name>
+ <UID>IF-Staticcfg_slave_CFGTE1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_VIRQ0</Name>
+ <UID>IF-interrupt_slave_VIRQ0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_VIRQ1</Name>
+ <UID>IF-interrupt_slave_VIRQ1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP4</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP4</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP10</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP10</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_VFIQ0</Name>
+ <UID>IF-interrupt_slave_VFIQ0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_VFIQ1</Name>
+ <UID>IF-interrupt_slave_VFIQ1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP9</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP9</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>ACP_slave</Name>
+ <UID>IF-ACP_slave</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>ACP4</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMMN_BASE</Name>
+ <UID>IF-Staticcfg_slave_SAMMN_BASE</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP5</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP5</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMMN_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMMN_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP0</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_VINITHI0</Name>
+ <UID>IF-Staticcfg_slave_VINITHI0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_VINITHI1</Name>
+ <UID>IF-Staticcfg_slave_VINITHI1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP12</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP12</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>RESET_slave_MBIST</Name>
+ <UID>IF-RESET_slave_MBIST</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>RESET</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CLUSTERIDAFF1</Name>
+ <UID>IF-Staticcfg_slave_CLUSTERIDAFF1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Authentication_slave_CPU0</Name>
+ <UID>IF-Authentication_slave_CPU0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Authentication</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Authentication_slave_CPU1</Name>
+ <UID>IF-Authentication_slave_CPU1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Authentication</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CP15SDISABLE0</Name>
+ <UID>IF-Staticcfg_slave_CP15SDISABLE0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CP15SDISABLE1</Name>
+ <UID>IF-Staticcfg_slave_CP15SDISABLE1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Channel_slave_CTI_CHIN</Name>
+ <UID>IF-Channel_slave_CTI_CHIN</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Channel</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_NODEID</Name>
+ <UID>IF-Staticcfg_slave_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP8</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP8</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP2</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP2</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF0_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF0_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_RVB_ARADDR1</Name>
+ <UID>IF-Staticcfg_slave_RVB_ARADDR1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF5_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF5_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SYSBARDISABLE</Name>
+ <UID>IF-Staticcfg_slave_SYSBARDISABLE</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_GICC_DISABLE</Name>
+ <UID>IF-Staticcfg_slave_GICC_DISABLE</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP1</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF2_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF2_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_AA64nAA32_CPU0</Name>
+ <UID>IF-Staticcfg_slave_AA64nAA32_CPU0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_AA64nAA32_CPU1</Name>
+ <UID>IF-Staticcfg_slave_AA64nAA32_CPU1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_BROADCASTINNER</Name>
+ <UID>IF-Staticcfg_slave_BROADCASTINNER</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>RESET_slave_CORE_RESET0</Name>
+ <UID>IF-RESET_slave_CORE_RESET0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>RESET</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>RESET_slave_CORE_RESET1</Name>
+ <UID>IF-RESET_slave_CORE_RESET1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>RESET</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_SEI0</Name>
+ <UID>IF-interrupt_slave_SEI0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_SEI1</Name>
+ <UID>IF-interrupt_slave_SEI1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_CLUSTERIDAFF2</Name>
+ <UID>IF-Staticcfg_slave_CLUSTERIDAFF2</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNI0_NODID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNI0_NODID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_BROADCASTCACHEMAINT</Name>
+ <UID>IF-Staticcfg_slave_BROADCASTCACHEMAINT</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF4_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF4_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP6</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP6</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SCLKEN</Name>
+ <UID>IF-Staticcfg_slave_SCLKEN</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP3</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP3</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF6_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF6_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_IRQ0</Name>
+ <UID>IF-interrupt_slave_IRQ0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_IRQ1</Name>
+ <UID>IF-interrupt_slave_IRQ1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP15</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP15</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF_MODE</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF_MODE</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>RESET_slave_L2</Name>
+ <UID>IF-RESET_slave_L2</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>RESET</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_VSEI0</Name>
+ <UID>IF-interrupt_slave_VSEI0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_VSEI1</Name>
+ <UID>IF-interrupt_slave_VSEI1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF7_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF7_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP7</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP7</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNI1_NODID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNI1_NODID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>EVENT_slave_EDBGRQ0</Name>
+ <UID>IF-EVENT_slave_EDBGRQ0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>EVENT</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>EVENT_slave_EDBGRQ1</Name>
+ <UID>IF-EVENT_slave_EDBGRQ1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>EVENT</ProtocolRef>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_DBGROMADDR</Name>
+ <UID>IF-Staticcfg_slave_DBGROMADDR</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Q-Channel_slave_CPU0</Name>
+ <UID>IF-Q-Channel_slave_CPU0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Q-Channel-generic</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Q-Channel_slave_CPU1</Name>
+ <UID>IF-Q-Channel_slave_CPU1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Q-Channel-generic</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SINACT</Name>
+ <UID>IF-Staticcfg_slave_SINACT</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_BROADCASTOUTER</Name>
+ <UID>IF-Staticcfg_slave_BROADCASTOUTER</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_RVB_ARADDR0</Name>
+ <UID>IF-Staticcfg_slave_RVB_ARADDR0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP14</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP14</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>WTimestamp_slave</Name>
+ <UID>IF-WTimestamp_slave</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>WTimestamp</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>TSVALUE_WIDTH</Name>
+ <Value>64</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ <ClockDomainRef>CD-CLKIN</ClockDomainRef>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_DBGROMADDRV</Name>
+ <UID>IF-Staticcfg_slave_DBGROMADDRV</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMADDRMAP11</Name>
+ <UID>IF-Staticcfg_slave_SAMADDRMAP11</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_PERIPHBASE</Name>
+ <UID>IF-Staticcfg_slave_PERIPHBASE</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_REI0</Name>
+ <UID>IF-interrupt_slave_REI0</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>interrupt_slave_REI1</Name>
+ <UID>IF-interrupt_slave_REI1</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>interrupt</ProtocolRef>
+ </Protocol>
+ </Interface>
+ <Interface>
+ <Name>Staticcfg_slave_SAMHNF3_NODEID</Name>
+ <UID>IF-Staticcfg_slave_SAMHNF3_NODEID</UID>
+ <Completer/>
+ <Protocol>
+ <ProtocolRef>Staticcfg</ProtocolRef>
+ <Parameters>
+ <Parameter>
+ <Name>CONFIGURATION_WIDTH</Name>
+ <Value>1</Value>
+ </Parameter>
+ </Parameters>
+ </Protocol>
+ </Interface>
+ </Interfaces>
+ </Specification>
+</ConfiguredComponent>