From 5a1f4b462dd547ce59a1e2c396105b95a8410354 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Fri, 6 Dec 2024 15:58:09 +0000
Subject: [PATCH] Add CMSDK GPIO and update peripheral bus
---
flist/IP/Corstone101.flist | 9 +-
flist/IP/nic400_megasoc_main.flist | 30 +-
flist/megasoc_tech.flist | 1 +
.../megasoc_peripheral_addr_decode.v | 32 ++
.../megasoc_peripheral_subsystem.v | 333 ++++++++++++++++--
.../top_megasoc_tech/megasoc_tech_wrapper.v | 83 +++--
.../nic400_megasoc_main.xml | 264 +++++++++++---
7 files changed, 650 insertions(+), 102 deletions(-)
create mode 100644 logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_addr_decode.v
diff --git a/flist/IP/Corstone101.flist b/flist/IP/Corstone101.flist
index 224c29c..ca94052 100644
--- a/flist/IP/Corstone101.flist
+++ b/flist/IP/Corstone101.flist
@@ -3,4 +3,11 @@
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v
\ No newline at end of file
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v
+
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
+
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file
diff --git a/flist/IP/nic400_megasoc_main.flist b/flist/IP/nic400_megasoc_main.flist
index bceb61c..0fa06af 100644
--- a/flist/IP/nic400_megasoc_main.flist
+++ b/flist/IP/nic400_megasoc_main.flist
@@ -22,6 +22,11 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_FLASH/verilog/nic400_amib_FLASH_s_gen_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_GIC/verilog/nic400_amib_GIC_chan_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_GIC/verilog/nic400_amib_GIC_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog/nic400_amib_PERIPHERAL_a_gen_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog/nic400_amib_PERIPHERAL_ahb_m_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog/nic400_amib_PERIPHERAL_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog/nic400_amib_PERIPHERAL_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog/nic400_amib_PERIPHERAL_s_gen_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_RAM/verilog/nic400_amib_RAM_chan_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_RAM/verilog/nic400_amib_RAM_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_ROM/verilog/nic400_amib_ROM_chan_slice_megasoc_main.v
@@ -52,6 +57,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml3_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml6_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_megasoc_main.v
@@ -59,6 +65,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml7_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_lrg_arb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_megasoc_main.v
@@ -67,6 +74,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml7_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_1_megasoc_main.v
@@ -79,12 +87,13 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_7_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_qv_cmp_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_spi_tt_s1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_4_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_6_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_megasoc_main.v
@@ -92,6 +101,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml7_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_megasoc_main.v
@@ -99,6 +109,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml7_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_spi_tt_s1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_megasoc_main.v
@@ -181,6 +192,20 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_itb_to_axi_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_master_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_slave_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_axi_to_itb_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_itb_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_rd_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_rd_chan_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_rd_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_resp_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_wr_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_wr_merge_buffer_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_wr_mux_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_downsize_wr_resp_block_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_itb_to_axi_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_master_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog/nic400_ib_PERIPHERAL_ib_slave_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_itb_addr_fmt_megasoc_main.v
@@ -248,9 +273,11 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_wr_reg_slice_megasoc_main.v
+
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_DRAM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_FLASH/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_GIC/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_RAM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_ROM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_apb_group0/verilog
@@ -265,6 +292,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_7/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog
diff --git a/flist/megasoc_tech.flist b/flist/megasoc_tech.flist
index 0e4dbda..6e63914 100644
--- a/flist/megasoc_tech.flist
+++ b/flist/megasoc_tech.flist
@@ -18,6 +18,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/top_megasoc_tech/megasoc_tech_system_wrapper
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_addr_decode.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_debug.v
diff --git a/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_addr_decode.v b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_addr_decode.v
new file mode 100644
index 0000000..ed6f002
--- /dev/null
+++ b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_addr_decode.v
@@ -0,0 +1,32 @@
+
+
+module megasoc_peripheral_addr_decode #(
+ parameter BASEADDR_APBSS = 32'h4000_0000,
+ parameter BASEADDR_GPIO0 = 32'h4001_0000,
+ parameter BASEADDR_GPIO1 = 32'h4002_0000
+) (
+ // System Address
+ input wire hsel,
+ input wire [31:0] haddr,
+
+ // Peripheral Selection
+ output wire apbsys_hsel,
+ output wire gpio0_hsel,
+ output wire gpio1_hsel,
+
+ // Default slave
+ output wire defslv_hsel
+);
+
+assign apbsys_hsel = hsel & (haddr[31:16]==
+ BASEADDR_APBSS[31:16]); // 0x40000000
+assign gpio0_hsel = hsel & (haddr[31:12]==
+ BASEADDR_GPIO0[31:12]); // 0x40010000
+assign gpio1_hsel = hsel & (haddr[31:12]==
+ BASEADDR_GPIO1[31:12]); // 0x40011000
+
+assign defslv_hsel = ~(apbsys_hsel |
+ gpio0_hsel | gpio1_hsel
+ );
+
+endmodule
\ No newline at end of file
diff --git a/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
index 21db585..b94e322 100644
--- a/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
+++ b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
@@ -18,7 +18,8 @@
// cmsdk_apb_timer (u_apb_timer0)
// megasoc_peripheral_debug (u_megasoc_peripheral_debug)
-module megasoc_peripheral_subsystem(
+module megasoc_peripheral_subsystem #(
+ parameter BE = 0 )(
input wire PCLK,
input wire PRESETn,
input wire HCLK,
@@ -38,15 +39,19 @@ module megasoc_peripheral_subsystem(
input wire HREADY_ADP,
input wire HRESP_ADP,
- // APB bus interface
- input wire [31:0] PADDR,
- input wire PENABLE,
- input wire PWRITE,
- input wire [31:0] PWDATA,
- input wire PSEL,
- output wire [31:0] PRDATA,
- output wire PREADY,
- output wire PSLVERR,
+ // Peripheral AHB bus interface
+ input wire HSEL,
+ input wire [31:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire HWRITE,
+ input wire [2:0] HSIZE,
+ input wire [2:0] HBURST,
+ input wire [3:0] HPROT,
+ input wire [31:0] HWDATA,
+ input wire HREADY,
+ output wire [31:0] HRDATA,
+ output wire HREADYOUT,
+ output wire HRESP,
input wire UARTRXD,
output wire UARTTXD,
@@ -60,13 +65,57 @@ module megasoc_peripheral_subsystem(
output wire FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire FT_MIOSIO_I, // MIOSIO tristate input
+ input wire [15:0] p0_in,
+ output wire [15:0] p0_out,
+ output wire [15:0] p0_en,
+ output wire [15:0] p0_func,
- output wire [5:0] PERI_IRQS // Peripheral interrupts to GIC
+ input wire [15:0] p1_in,
+ output wire [15:0] p1_out,
+ output wire [15:0] p1_en,
+ output wire [15:0] p1_func,
+
+ output wire [39:0] PERI_IRQS // Peripheral interrupts to GIC
);
+// APB bus interface
+wire [15:0] PADDR;
+wire PENABLE;
+wire PWRITE;
+wire [31:0] PWDATA;
+wire PSEL;
+wire [31:0] PRDATA;
+wire PREADY;
+wire PSLVERR;
+wire [3:0] PSTRB;
+wire [2:0] PPROT;
+
+
wire UARTCLK;
assign UARTCLK=PCLK; // TODO generate UARTCLK from elsewhere
+// AHB internal wires
+wire defslv_hsel; // AHB default slave signals
+wire defslv_hreadyout;
+wire [31:0] defslv_hrdata;
+wire defslv_hresp;
+
+wire apbsys_hsel; // APB subsystem AHB interface signals
+wire apbsys_hreadyout;
+wire [31:0] apbsys_hrdata;
+wire apbsys_hresp;
+
+wire gpio0_hsel; // AHB GPIO bus interface signals
+wire gpio0_hreadyout;
+wire [31:0] gpio0_hrdata;
+wire gpio0_hresp;
+
+wire gpio1_hsel; // AHB GPIO bus interface signals
+wire gpio1_hreadyout;
+wire [31:0] gpio1_hrdata;
+wire gpio1_hresp;
+
+
// Internal APB signals for UART0
wire PSEL_UART0;
wire PREADY_UART0;
@@ -85,6 +134,256 @@ wire PREADY_USRT;
wire [31:0] PRDATA_USRT;
wire PSLVERR_USRT;
+// Interrupt Signals
+wire [15:0] gpio0_int;
+wire gpio0_comb_int;
+wire [15:0] gpio1_int;
+wire gpio1_comb_int;
+wire timer0_int;
+wire uart0_txint;
+wire uart0_rxint;
+wire uart0_txovrint;
+wire uart0_rxovrint;
+wire uart0_combined_int;
+
+assign PERI_IRQS[0] = uart0_txint;
+assign PERI_IRQS[1] = uart0_rxint;
+assign PERI_IRQS[2] = uart0_txovrint;
+assign PERI_IRQS[3] = uart0_rxovrint;
+assign PERI_IRQS[4] = uart0_combined_int;
+assign PERI_IRQS[5] = timer0_int;
+assign PERI_IRQS[6] = gpio0_comb_int;
+assign PERI_IRQS[7] = gpio1_comb_int;
+assign PERI_IRQS[23:8] = gpio0_int;
+assign PERI_IRQS[39:24] = gpio1_int;
+
+
+megasoc_peripheral_addr_decode #(
+ .BASEADDR_APBSS(32'h4000_0000),
+ .BASEADDR_GPIO0(32'h4001_0000),
+ .BASEADDR_GPIO1(32'h4002_0000)
+) u_peripheral_addr_decode (
+ .hsel(HSEL),
+ .haddr(HADDR),
+ .apbsys_hsel(apbsys_hsel),
+ .gpio0_hsel(gpio0_hsel),
+ .gpio1_hsel(gpio1_hsel),
+ .defslv_hsel(defslv_hsel)
+);
+
+cmsdk_ahb_slave_mux #(
+ .PORT0_ENABLE (1), // APB subsystem bridge
+ .PORT1_ENABLE (1), // GPIO Port 0
+ .PORT2_ENABLE (1), // GPIO Port 1
+ .PORT3_ENABLE (0), // SYS control
+ .PORT4_ENABLE (0), // Default
+ .PORT5_ENABLE (0), //
+ .PORT6_ENABLE (0), //
+ .PORT7_ENABLE (0),
+ .PORT8_ENABLE (0),
+ .PORT9_ENABLE (0),
+ .DW (32)
+) u_ahb_slave_mux_sys_bus (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HREADY (HREADY),
+ .HSEL0 (apbsys_hsel), // Input Port 0
+ .HREADYOUT0 (apbsys_hreadyout),
+ .HRESP0 (apbsys_hresp),
+ .HRDATA0 (apbsys_hrdata),
+ .HSEL1 (gpio0_hsel), // Input Port 1
+ .HREADYOUT1 (gpio0_hreadyout),
+ .HRESP1 (gpio0_hresp),
+ .HRDATA1 (gpio0_hrdata),
+ .HSEL2 (gpio1_hsel), // Input Port 2
+ .HREADYOUT2 (gpio1_hreadyout),
+ .HRESP2 (gpio1_hresp),
+ .HRDATA2 (gpio1_hrdata),
+ .HSEL3 (1'b0), // Input Port 3
+ .HREADYOUT3 (defslv_hreadyout),
+ .HRESP3 (defslv_hresp),
+ .HRDATA3 (defslv_hrdata),
+ .HSEL4 (defslv_hsel), // Input Port 4
+ .HREADYOUT4 (defslv_hreadyout),
+ .HRESP4 (defslv_hresp),
+ .HRDATA4 (defslv_hrdata),
+ .HSEL5 (1'b0), // Input Port 5
+ .HREADYOUT5 (defslv_hreadyout),
+ .HRESP5 (defslv_hresp),
+ .HRDATA5 (defslv_hrdata),
+ .HSEL6 (1'b0), // Input Port 6
+ .HREADYOUT6 (defslv_hreadyout),
+ .HRESP6 (defslv_hresp),
+ .HRDATA6 (defslv_hrdata),
+ .HSEL7 (1'b0), // Input Port 7
+ .HREADYOUT7 (defslv_hreadyout),
+ .HRESP7 (defslv_hresp),
+ .HRDATA7 (defslv_hrdata),
+ .HSEL8 (1'b0), // Input Port 8
+ .HREADYOUT8 (defslv_hreadyout),
+ .HRESP8 (defslv_hresp),
+ .HRDATA8 (defslv_hrdata),
+ .HSEL9 (1'b0), // Input Port 9
+ .HREADYOUT9 (defslv_hreadyout),
+ .HRESP9 (defslv_hresp),
+ .HRDATA9 (defslv_hrdata),
+
+ .HREADYOUT (HREADYOUT), // Outputs
+ .HRESP (HRESP),
+ .HRDATA (HRDATA)
+);
+
+// Default slave
+cmsdk_ahb_default_slave u_ahb_default_slave_1 (
+.HCLK (HCLK),
+.HRESETn (HRESETn),
+.HSEL (defslv_hsel),
+.HTRANS (HTRANS),
+.HREADY (HREADY),
+.HREADYOUT (defslv_hreadyout),
+.HRESP (defslv_hresp)
+);
+assign defslv_hrdata = 32'hDEADBEEF; // Default slave do not have read data
+
+
+
+cmsdk_ahb_gpio #(
+ .ALTERNATE_FUNC_MASK(16'hFFFF),
+ .ALTERNATE_FUNC_DEFAULT(16'h0000),
+ .BE(0)
+) u_cmsdk_ahb_gpio_0 (
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .FCLK(HCLK),
+ .HSEL(gpio0_hsel),
+ .HREADY(HREADY),
+ .HTRANS(HTRANS),
+ .HSIZE(HSIZE),
+ .HWRITE(HWRITE),
+ .HADDR(HADDR[11:0]),
+ .HWDATA(HWDATA),
+ .HREADYOUT(gpio0_hreadyout),
+ .HRESP(gpio0_hresp),
+ .HRDATA(gpio0_hrdata),
+
+ .ECOREVNUM(4'h0),
+
+ .PORTIN(p0_in),
+ .PORTOUT(p0_out),
+ .PORTEN(p0_en),
+ .PORTFUNC(p0_func),
+
+ .GPIOINT(gpio0_int),
+ .COMBINT(gpio0_comb_int)
+);
+
+cmsdk_ahb_gpio #(
+ .ALTERNATE_FUNC_MASK(16'hFFFF),
+ .ALTERNATE_FUNC_DEFAULT(16'h0000),
+ .BE(0)
+) u_cmsdk_ahb_gpio_1 (
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .FCLK(HCLK),
+ .HSEL(gpio1_hsel),
+ .HREADY(HREADY),
+ .HTRANS(HTRANS),
+ .HSIZE(HSIZE),
+ .HWRITE(HWRITE),
+ .HADDR(HADDR[11:0]),
+ .HWDATA(HWDATA),
+ .HREADYOUT(gpio1_hreadyout),
+ .HRESP(gpio1_hresp),
+ .HRDATA(gpio1_hrdata),
+
+ .ECOREVNUM(4'h0),
+
+ .PORTIN(p1_in),
+ .PORTOUT(p1_out),
+ .PORTEN(p1_en),
+ .PORTFUNC(p1_func),
+
+ .GPIOINT(gpio1_int),
+ .COMBINT(gpio1_comb_int)
+);
+ // endian handling
+ wire bigendian;
+ assign bigendian = (BE!=0) ? 1'b1 : 1'b0;
+
+ wire [31:0] hwdata_le; // Little endian write data
+ wire [31:0] hrdata_le; // Little endian read data
+ wire reg_be_swap_ctrl_en = HSEL & HTRANS[1] & HREADY & bigendian;
+ reg [1:0] reg_be_swap_ctrl; // registered byte swap control
+ wire [1:0] nxt_be_swap_ctrl; // next state of byte swap control
+
+ assign nxt_be_swap_ctrl[1] = bigendian & (HSIZE[1:0]==2'b10); // Swap upper and lower half word
+ assign nxt_be_swap_ctrl[0] = bigendian & (HSIZE[1:0]!=2'b00); // Swap byte within hafword
+
+ // Register byte swap control for data phase
+ always @(posedge HCLK or negedge HRESETn)
+ begin
+ if (~HRESETn)
+ reg_be_swap_ctrl <= 2'b00;
+ else if (reg_be_swap_ctrl_en)
+ reg_be_swap_ctrl <= nxt_be_swap_ctrl;
+ end
+
+ // swap byte within half word
+ wire [31:0] hwdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
+ {HWDATA[23:16],HWDATA[31:24],HWDATA[7:0],HWDATA[15:8]}:
+ {HWDATA[31:24],HWDATA[23:16],HWDATA[15:8],HWDATA[7:0]};
+ // swap lower and upper half word
+ assign hwdata_le = (reg_be_swap_ctrl[1] & bigendian) ?
+ {hwdata_mux_1[15: 0],hwdata_mux_1[31:16]}:
+ {hwdata_mux_1[31:16],hwdata_mux_1[15:0]};
+ // swap byte within half word
+ wire [31:0] hrdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
+ {hrdata_le[23:16],hrdata_le[31:24],hrdata_le[ 7:0],hrdata_le[15:8]}:
+ {hrdata_le[31:24],hrdata_le[23:16],hrdata_le[15:8],hrdata_le[7:0]};
+ // swap lower and upper half word
+ assign apbsys_hrdata = (reg_be_swap_ctrl[1] & bigendian) ?
+ {hrdata_mux_1[15: 0],hrdata_mux_1[31:16]}:
+ {hrdata_mux_1[31:16],hrdata_mux_1[15:0]};
+
+// AHB to APB bus bridge
+cmsdk_ahb_to_apb #(
+ .ADDRWIDTH (16),
+ .REGISTER_RDATA (1),
+ .REGISTER_WDATA (0)
+) u_ahb_to_apb (
+ // AHB side
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (apbsys_hsel),
+ .HADDR (HADDR[15:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HPROT (HPROT),
+ .HWRITE (HWRITE),
+ .HREADY (HREADY),
+ .HWDATA (hwdata_le),
+
+ .HREADYOUT(apbsys_hreadyout), // AHB Outputs
+ .HRDATA (hrdata_le),
+ .HRESP (apb_hres),
+
+ .PADDR (PADDR[15:0]),
+ .PSEL (PSEL),
+ .PENABLE (PENABLE),
+ .PSTRB (PSTRB),
+ .PPROT (PPROT),
+ .PWRITE (PWRITE),
+ .PWDATA (PWDATA),
+
+ .APBACTIVE(APBACTIVE),
+ .PCLKEN (1'b1), // APB clock enable signal
+
+ .PRDATA (PRDATA),
+ .PREADY (PREADY),
+ .PSLVERR (PSLVERR)
+);
+
+
// CMSDK APB Slave Mux (from Corstone 101)
cmsdk_apb_slave_mux #(
.PORT0_ENABLE(1),
@@ -192,11 +491,6 @@ cmsdk_apb_slave_mux #(
.PSLVERR(PSLVERR)
);
-wire uart0_txint;
-wire uart0_rxint;
-wire uart0_txovrint;
-wire uart0_rxovrint;
-wire uart0_combined_int;
cmsdk_apb_uart u_apb_uart_0(
.PCLK (PCLK), // Peripheral clock
@@ -229,13 +523,7 @@ cmsdk_apb_uart u_apb_uart_0(
.UARTINT (uart0_combined_int) // Combined Interrupt
);
-assign PERI_IRQS[0] = uart0_txint;
-assign PERI_IRQS[1] = uart0_rxint;
-assign PERI_IRQS[2] = uart0_txovrint;
-assign PERI_IRQS[3] = uart0_rxovrint;
-assign PERI_IRQS[4] = uart0_combined_int;
-wire timer0_int;
cmsdk_apb_timer u_apb_timer0(
.PCLK(PCLK), // PCLK for timer operation
@@ -254,7 +542,6 @@ cmsdk_apb_timer u_apb_timer0(
.TIMERINT(timer0_int)
);
-assign PERI_IRQS[5] = timer0_int;
megasoc_peripheral_debug #(
.FT1248_WIDTH(1)
diff --git a/logical/top_megasoc_tech/megasoc_tech_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
index 5502956..b5c75ca 100644
--- a/logical/top_megasoc_tech/megasoc_tech_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
@@ -193,7 +193,18 @@ module megasoc_tech_wrapper(
output wire TDO,
output wire nTDOEN,
output wire SWDO,
- output wire SWDOEN
+ output wire SWDOEN,
+
+ input wire [15:0] P0_IN,
+ output wire [15:0] P0_OUT,
+ output wire [15:0] P0_EN,
+ output wire [15:0] P0_FUNC,
+
+ input wire [15:0] P1_IN,
+ output wire [15:0] P1_OUT,
+ output wire [15:0] P1_EN,
+ output wire [15:0] P1_FUNC
+
);
@@ -323,14 +334,18 @@ wire HREADYOUT_FLASH;
wire HREADY_FLASH;
wire HRESP_FLASH;
-wire [31:0] PADDR_PERIPHERAL;
-wire [31:0] PWDATA_PERIPHERAL;
-wire PWRITE_PERIPHERAL;
-wire PENABLE_PERIPHERAL;
-wire PSELx_PERIPHERAL;
-wire [31:0] PRDATA_PERIPHERAL;
-wire PSLVERR_PERIPHERAL;
-wire PREADY_PERIPHERAL;
+wire HSELx_PERIPHERAL;
+wire [31:0] HADDR_PERIPHERAL;
+wire [1:0] HTRANS_PERIPHERAL;
+wire HWRITE_PERIPHERAL;
+wire [2:0] HSIZE_PERIPHERAL;
+wire [2:0] HBURST_PERIPHERAL;
+wire [3:0] HPROT_PERIPHERAL;
+wire [31:0] HWDATA_PERIPHERAL;
+wire [31:0] HRDATA_PERIPHERAL;
+wire HREADYOUT_PERIPHERAL;
+wire HREADY_PERIPHERAL;
+wire HRESP_PERIPHERAL;
wire [ID_W-1:0] AWID_RAM;
wire [31:0] AWADDR_RAM;
@@ -649,15 +664,18 @@ nic400_megasoc_main u_nic400_megasoc_main(
.RVALID_GIC(GIC_RVALID),
.RREADY_GIC(GIC_RREADY),
- .PADDR_PERIPHERAL(PADDR_PERIPHERAL),
- .PWDATA_PERIPHERAL(PWDATA_PERIPHERAL),
- .PWRITE_PERIPHERAL(PWRITE_PERIPHERAL),
- .PENABLE_PERIPHERAL(PENABLE_PERIPHERAL),
- .PSELx_PERIPHERAL(PSELx_PERIPHERAL),
- .PRDATA_PERIPHERAL(PRDATA_PERIPHERAL),
- .PSLVERR_PERIPHERAL(PSLVERR_PERIPHERAL),
- .PREADY_PERIPHERAL(PREADY_PERIPHERAL),
-
+ .HSELx_PERIPHERAL(HSELx_PERIPHERAL),
+ .HADDR_PERIPHERAL(HADDR_PERIPHERAL),
+ .HTRANS_PERIPHERAL(HTRANS_PERIPHERAL),
+ .HWRITE_PERIPHERAL(HWRITE_PERIPHERAL),
+ .HSIZE_PERIPHERAL(HSIZE_PERIPHERAL),
+ .HBURST_PERIPHERAL(HBURST_PERIPHERAL),
+ .HPROT_PERIPHERAL(HPROT_PERIPHERAL),
+ .HWDATA_PERIPHERAL(HWDATA_PERIPHERAL),
+ .HRDATA_PERIPHERAL(HRDATA_PERIPHERAL),
+ .HREADYOUT_PERIPHERAL(HREADYOUT_PERIPHERAL),
+ .HREADY_PERIPHERAL(HREADY_PERIPHERAL),
+ .HRESP_PERIPHERAL(HRESP_PERIPHERAL),
.AWID_RAM(AWID_RAM),
.AWADDR_RAM(AWADDR_RAM),
@@ -1012,14 +1030,18 @@ megasoc_peripheral_subsystem u_megasoc_peripheral_subsystem(
.HREADY_ADP(HREADY_ADP),
.HRESP_ADP(HRESP_ADP),
- .PADDR(PADDR_PERIPHERAL),
- .PENABLE(PENABLE_PERIPHERAL),
- .PWRITE(PWRITE_PERIPHERAL),
- .PWDATA(PWDATA_PERIPHERAL),
- .PSEL(PSELx_PERIPHERAL),
- .PRDATA(PRDATA_PERIPHERAL),
- .PREADY(PREADY_PERIPHERAL),
- .PSLVERR(PSLVERR_PERIPHERAL),
+ .HSEL(HSELx_PERIPHERAL),
+ .HADDR(HADDR_PERIPHERAL),
+ .HTRANS(HTRANS_PERIPHERAL),
+ .HWRITE(HWRITE_PERIPHERAL),
+ .HSIZE(HSIZE_PERIPHERAL),
+ .HBURST(HBURST_PERIPHERAL),
+ .HPROT(HPROT_PERIPHERAL),
+ .HWDATA(HWDATA_PERIPHERAL),
+ .HREADY(HREADY_PERIPHERAL),
+ .HRDATA(HRDATA_PERIPHERAL),
+ .HREADYOUT(HREADYOUT_PERIPHERAL),
+ .HRESP(HRESP_PERIPHERAL),
.UARTRXD(UARTRXD),
.UARTTXD(UARTTXD),
@@ -1033,6 +1055,15 @@ megasoc_peripheral_subsystem u_megasoc_peripheral_subsystem(
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
+ .p0_in(P0_IN),
+ .p0_out(P0_OUT),
+ .p0_en(P0_EN),
+ .p0_func(P0_FUNC),
+ .p1_in(P1_IN),
+ .p1_out(P1_OUT),
+ .p1_en(P1_EN),
+ .p1_func(P1_FUNC),
+
.PERI_IRQS(PERI_IRQS)
);
diff --git a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
index 2b5135a..a641a02 100644
--- a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
+++ b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
@@ -150,12 +150,16 @@
</MasterInterface>
<MasterInterface>
<Name>PERIPHERAL</Name>
- <APBMasterProtocol>
+ <AHBLiteTargetMasterProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
- <TrustZoneMasterAPB>non_secure</TrustZoneMasterAPB>
- <APBGroupRef>apb_group0</APBGroupRef>
- </APBMasterProtocol>
+ <ReadIssuing>1</ReadIssuing>
+ <WriteIssuing>1</WriteIssuing>
+ <TotalIssuing>1</TotalIssuing>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <MultiPorted>false</MultiPorted>
+ <LockSupport>false</LockSupport>
+ </AHBLiteTargetMasterProtocol>
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
@@ -1479,6 +1483,101 @@
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id def="true">false</compress_id>
+ <dest_type>peripheral</dest_type>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>PERIPHERAL</name>
+ <protocol>ahb_ms</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>a</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>d</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>a</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>d</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>64</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>80</y>
+ <master_if_port_name>PERIPHERAL_m</master_if_port_name>
+ <slave_if_port_name>PERIPHERAL_s</slave_if_port_name>
+ </amib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>61</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
<master_if_addr_width>32</master_if_addr_width>
@@ -1590,13 +1689,13 @@
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
- <y>80</y>
+ <y>100</y>
<master_if_port_name>DRAM_m</master_if_port_name>
<slave_if_port_name>DRAM_s</slave_if_port_name>
</amib>
<amib>
<apb_config>false</apb_config>
- <apb_slave_no>61</apb_slave_no>
+ <apb_slave_no>60</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
@@ -1711,19 +1810,12 @@
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
- <y>100</y>
+ <y>120</y>
<master_if_port_name>GIC_m</master_if_port_name>
<slave_if_port_name>GIC_s</slave_if_port_name>
</amib>
<amib>
<apb_config>false</apb_config>
- <apb_port>
- <clock_domain>clk0</clock_domain>
- <name>PERIPHERAL</name>
- <trustzone>nsec</trustzone>
- <x>0</x>
- <y>0</y>
- </apb_port>
<apb_port>
<clock_domain>clk0</clock_domain>
<name>FLASH_CTRL</name>
@@ -1745,7 +1837,7 @@
<x>0</x>
<y>0</y>
</apb_port>
- <apb_slave_no>60</apb_slave_no>
+ <apb_slave_no>59</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
@@ -1834,15 +1926,15 @@
<vn_external def="true">none</vn_external>
<vn_external_bridge def="true">none</vn_external_bridge>
<x>0</x>
- <y>120</y>
- <master_if_port_name>PERIPHERAL,FLASH_CTRL,DEBUG,DMA_CTRL</master_if_port_name>
+ <y>140</y>
+ <master_if_port_name>FLASH_CTRL,DEBUG,DMA_CTRL</master_if_port_name>
<slave_if_port_name>apb_group0_s</slave_if_port_name>
</amib>
<inter>
<clock_domain>clk0</clock_domain>
<data_width>64</data_width>
<expanded>false</expanded>
- <height>120</height>
+ <height>140</height>
<impl>mlayer</impl>
<master_if>
<name>axi_m_0</name>
@@ -1886,6 +1978,12 @@
<x>0</x>
<y>183</y>
</master_if>
+ <master_if>
+ <name>axi_m_7</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>203</y>
+ </master_if>
<name>bm0</name>
<protocol>axi4</protocol>
<slave_if>
@@ -2098,6 +2196,34 @@
<type def="true">full</type>
</reg>
</master_if_port>
+ <master_if_port>
+ <name>axi_m_7</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
</sparse>
<sparse>
<cds>slaveperid</cds>
@@ -2243,12 +2369,40 @@
<type def="true">full</type>
</reg>
</master_if_port>
+ <master_if_port>
+ <name>axi_m_6</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
</sparse>
<type>busmatrix</type>
<width>0</width>
<x>500</x>
<y>45</y>
- <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3,axi_m_4,axi_m_5,axi_m_6</master_if_port_name>
+ <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3,axi_m_4,axi_m_5,axi_m_6,axi_m_7</master_if_port_name>
<slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
</inter>
<inter>
@@ -3043,15 +3197,15 @@
<awuser>false</awuser>
<buser>false</buser>
<dest>external</dest>
- <dest_port>DRAM</dest_port>
+ <dest_port>PERIPHERAL</dest_port>
<lock>false</lock>
<out_reads>1</out_reads>
<out_trans>1</out_trans>
<out_writes>1</out_writes>
- <protocol>axi4</protocol>
+ <protocol>ahb_ms</protocol>
<ruser>false</ruser>
- <src>DRAM</src>
- <src_port>DRAM_m</src_port>
+ <src>PERIPHERAL</src>
+ <src_port>PERIPHERAL_m</src_port>
<wuser>false</wuser>
</connect>
<connect>
@@ -3059,15 +3213,15 @@
<awuser>false</awuser>
<buser>false</buser>
<dest>external</dest>
- <dest_port>GIC</dest_port>
+ <dest_port>DRAM</dest_port>
<lock>false</lock>
<out_reads>1</out_reads>
<out_trans>1</out_trans>
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<ruser>false</ruser>
- <src>GIC</src>
- <src_port>GIC_m</src_port>
+ <src>DRAM</src>
+ <src_port>DRAM_m</src_port>
<wuser>false</wuser>
</connect>
<connect>
@@ -3075,15 +3229,15 @@
<awuser>false</awuser>
<buser>false</buser>
<dest>external</dest>
- <dest_port>PERIPHERAL</dest_port>
+ <dest_port>GIC</dest_port>
<lock>false</lock>
<out_reads>1</out_reads>
<out_trans>1</out_trans>
<out_writes>1</out_writes>
- <protocol>apb3</protocol>
+ <protocol>axi4</protocol>
<ruser>false</ruser>
- <src>apb_group0</src>
- <src_port>PERIPHERAL</src_port>
+ <src>GIC</src>
+ <src_port>GIC_m</src_port>
<wuser>false</wuser>
</connect>
<connect>
@@ -3178,6 +3332,17 @@
<src>bm0</src>
<src_port>axi_m_4</src_port>
</connect>
+ <connect>
+ <dest>PERIPHERAL</dest>
+ <dest_port>PERIPHERAL_s</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">2</out_reads>
+ <out_trans def="true">4</out_trans>
+ <out_writes def="true">2</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_5</src_port>
+ </connect>
<connect>
<dest>RAM</dest>
<dest_port>RAM_s</dest_port>
@@ -3187,7 +3352,7 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_5</src_port>
+ <src_port>axi_m_6</src_port>
</connect>
<connect>
<dest>GIC</dest>
@@ -3281,9 +3446,9 @@
<dest>ib5</dest>
<dest_port>ib5_s</dest_port>
<lock>false</lock>
- <out_reads def="true">7</out_reads>
- <out_trans>14</out_trans>
- <out_writes def="true">7</out_writes>
+ <out_reads def="true">9</out_reads>
+ <out_trans>18</out_trans>
+ <out_writes def="true">9</out_writes>
<protocol>axi4</protocol>
<src>bm2</src>
<src_port>axi_m_1</src_port>
@@ -3292,9 +3457,9 @@
<dest>bm0</dest>
<dest_port>axi_s_1</dest_port>
<lock>false</lock>
- <out_reads def="true">7</out_reads>
- <out_trans>14</out_trans>
- <out_writes def="true">7</out_writes>
+ <out_reads def="true">9</out_reads>
+ <out_trans>18</out_trans>
+ <out_writes def="true">9</out_writes>
<protocol>axi4</protocol>
<src>ib5</src>
<src_port>ib5_m</src_port>
@@ -3308,7 +3473,7 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_6</src_port>
+ <src_port>axi_m_7</src_port>
</connect>
<connect>
<dest>ds_7</dest>
@@ -3325,16 +3490,15 @@
<link>
<slave_if>
<name>A53</name>
- <master_if>DRAM</master_if>
- <master_if>ROM</master_if>
- <master_if>PERIPHERAL<parent>apb_group0</parent>
+ <master_if>FLASH_CTRL<parent>apb_group0</parent>
</master_if>
+ <master_if>PERIPHERAL</master_if>
+ <master_if>ROM</master_if>
<master_if>FLASH</master_if>
<master_if>RAM</master_if>
+ <master_if>DRAM</master_if>
<master_if>GIC</master_if>
<master_if>apb_group0</master_if>
- <master_if>FLASH_CTRL<parent>apb_group0</parent>
- </master_if>
<master_if>DEBUG<parent>apb_group0</parent>
</master_if>
<master_if>DMA_CTRL<parent>apb_group0</parent>
@@ -3344,12 +3508,11 @@
<link>
<slave_if>
<name>DMA350</name>
- <master_if>DRAM</master_if>
+ <master_if>PERIPHERAL</master_if>
<master_if>ROM</master_if>
- <master_if>PERIPHERAL<parent>apb_group0</parent>
- </master_if>
<master_if>FLASH</master_if>
<master_if>RAM</master_if>
+ <master_if>DRAM</master_if>
<master_if>apb_group0</master_if>
<master_if>DEBUG<parent>apb_group0</parent>
</master_if>
@@ -3358,16 +3521,15 @@
<link>
<slave_if>
<name>ADP</name>
- <master_if>DRAM</master_if>
- <master_if>ROM</master_if>
- <master_if>PERIPHERAL<parent>apb_group0</parent>
+ <master_if>FLASH_CTRL<parent>apb_group0</parent>
</master_if>
+ <master_if>PERIPHERAL</master_if>
+ <master_if>ROM</master_if>
<master_if>FLASH</master_if>
<master_if>RAM</master_if>
+ <master_if>DRAM</master_if>
<master_if>GIC</master_if>
<master_if>apb_group0</master_if>
- <master_if>FLASH_CTRL<parent>apb_group0</parent>
- </master_if>
<master_if>DEBUG<parent>apb_group0</parent>
</master_if>
<master_if>DMA_CTRL<parent>apb_group0</parent>
--
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