diff --git a/.gitignore b/.gitignore
index 06cc3b08b3f972c7bb0b0fce9253119438ae3862..f540484ec24caf6e90a9321d84cc296db33514bc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,6 +4,7 @@ logical/sie300
logical/SMC
logical/shared
logical/nic400_megasoc_main
+logical/nic400_megasoc_system
logical/dma350
software/build
diff --git a/.gitmodules b/.gitmodules
index 0f116cb0158facbca97929d6e3f2b3b7fb38504b..06240e76dceb6d74a522e92f91ec388a6ab665ee 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
[submodule "logical/sl_ahb_qspi"]
path = logical/sl_ahb_qspi
url = https://git.soton.ac.uk/soclabs/ahb_qspi.git
+[submodule "logical/socdebug_tech"]
+ path = logical/socdebug_tech
+ url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
diff --git a/flist/IP/SIE300_SYS_SRAM_controller.flist b/flist/IP/SIE300_SYS_SRAM_controller.flist
new file mode 100644
index 0000000000000000000000000000000000000000..76eebe0098c24bdf289800dab4acea0dcc5aab2c
--- /dev/null
+++ b/flist/IP/SIE300_SYS_SRAM_controller.flist
@@ -0,0 +1,20 @@
+
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_addr_dec.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_arb.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_arq.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_awq.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_axi_mux.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_bq.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_clamp.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_eam.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_fifo.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_fifo_core.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_lpi_ctrl.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_one_hot.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_rbeat.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_resp_gen.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_rq.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_wbeat.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/sie300/logical/sie300_axi5_sram_ctrl_sys/verilog/sie300_axi5_sram_ctrl_sys_wq.sv
\ No newline at end of file
diff --git a/flist/IP/SoCDebug_tech.flist b/flist/IP/SoCDebug_tech.flist
new file mode 100644
index 0000000000000000000000000000000000000000..588e9daa9e252043cfa7e20819002afebadcd821
--- /dev/null
+++ b/flist/IP/SoCDebug_tech.flist
@@ -0,0 +1,6 @@
+
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/socdebug_tech/controller/verilog/socdebug_ahb.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/socdebug_tech/controller/verilog/socdebug_adp_control.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/socdebug_tech/controller/verilog/socdebug_ft1248_control.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/socdebug_tech/controller/verilog/socdebug_usrt_control.v
\ No newline at end of file
diff --git a/flist/IP/nic400_megasoc_main.flist b/flist/IP/nic400_megasoc_main.flist
index 823d89cb3b1841de8f869e2458927997397b767e..bceb61c070d7e52a7ed9f5833eb020dc0a4c25fa 100644
--- a/flist/IP/nic400_megasoc_main.flist
+++ b/flist/IP/nic400_megasoc_main.flist
@@ -36,76 +36,113 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog/nic400_asib_A53_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog/nic400_asib_A53_rd_spi_cdas_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog/nic400_asib_A53_wr_spi_cdas_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_ADP/verilog/nic400_asib_ADP_ahb_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_ADP/verilog/nic400_asib_ADP_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_ADP/verilog/nic400_asib_ADP_decode_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_ADP/verilog/nic400_asib_ADP_itb_ss_cdas_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_ADP/verilog/nic400_asib_ADP_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_chan_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_decode_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_maskcntl_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_rd_spi_cdas_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_wr_spi_cdas_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_lrg_arb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml6_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_build_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_map_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_spi_tt_s0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_qv_cmp_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_spi_tt_s1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_5_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml6_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_spi_tt_s0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml5_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_spi_tt_s1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml3_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml3_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_lrg_arb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml3_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_build_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_map_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_3_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_qv_cmp_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml3_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml1_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml2_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml3_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml4_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s0_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_add_arb_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_add_arb_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_add_sel_ml0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_add_sel_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_add_sel_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_lrg_arb_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_maskcntl_ml0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_maskcntl_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_maskcntl_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_blayer_0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_blayer_1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_build_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_map_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_mlayer_0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_mlayer_1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ml_mlayer_2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_qv_cmp_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_rd_spi_tt_s0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_rd_spi_tt_s1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ret_sel_ml0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ret_sel_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_ret_sel_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_wr_sel_ml0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_wr_sel_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_wr_sel_ml2_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_wr_spi_tt_s0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog/nic400_bm2_wr_spi_tt_s1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_bypass_sync_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_capt_nosync_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_capt_sync_megasoc_main.v
@@ -116,7 +153,20 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_corrupt_gry_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_launch_gry_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_random_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_3/verilog/nic400_default_slave_ds_3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_6/verilog/nic400_default_slave_ds_6_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_7/verilog/nic400_default_slave_ds_7_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_itb_to_axi_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_maskcntl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_master_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_slave_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_itb_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_rd_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_rd_chan_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_resp_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_wr_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_wr_merge_buffer_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog/nic400_ib_ADP_ib_upsize_wr_resp_block_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_axi_to_itb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_chan_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_downsize_itb_addr_fmt_megasoc_main.v
@@ -131,20 +181,6 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_itb_to_axi_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_master_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog/nic400_ib_FLASH_ib_slave_domain_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_chan_slice_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_rd_addr_fmt_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_rd_cam_slice_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_rd_chan_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_rd_cntrl_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_resp_cam_slice_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_wr_addr_fmt_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_wr_cntrl_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_wr_merge_buffer_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_wr_mux_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_downsize_wr_resp_block_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_maskcntl_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_master_domain_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog/nic400_ib_GIC_ib_slave_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_itb_addr_fmt_megasoc_main.v
@@ -159,20 +195,48 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_to_axi_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_master_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_slave_domain_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_chan_slice_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_addr_fmt_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_cam_slice_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_chan_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_cntrl_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_resp_cam_slice_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_wr_addr_fmt_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_wr_cntrl_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_wr_merge_buffer_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_wr_mux_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_downsize_wr_resp_block_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_maskcntl_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_master_domain_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_slave_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_rd_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_rd_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_rd_chan_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_rd_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_resp_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_wr_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_wr_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_wr_merge_buffer_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_wr_mux_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_downsize_wr_resp_block_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_maskcntl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_master_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog/nic400_ib_ib3_slave_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_rd_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_rd_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_rd_chan_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_rd_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_resp_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_wr_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_wr_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_wr_merge_buffer_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_wr_mux_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_downsize_wr_resp_block_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_maskcntl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_master_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog/nic400_ib_ib4_slave_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_rd_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_rd_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_rd_chan_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_rd_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_resp_cam_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_wr_addr_fmt_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_wr_cntrl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_wr_merge_buffer_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_wr_mux_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_downsize_wr_resp_block_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_maskcntl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_master_domain_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog/nic400_ib_ib5_slave_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_ax4_reg_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_ax_reg_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_buf_reg_slice_megasoc_main.v
@@ -183,6 +247,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_rev_regd_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_wr_reg_slice_megasoc_main.v
+
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_DRAM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_FLASH/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_GIC/verilog
@@ -190,18 +255,22 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_ROM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_apb_group0/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_ADP/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm2/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_3/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_6/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_7/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ADP_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib3/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib4/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib5/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog
-
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/nic400/verilog/Axi
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/nic400/verilog/Axi4PC
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/nic400/verilog/Ahb
diff --git a/flist/IP/nic400_megasoc_system.flist b/flist/IP/nic400_megasoc_system.flist
new file mode 100644
index 0000000000000000000000000000000000000000..16357535187e9f44ed177d8d374a363295fe5a2f
--- /dev/null
+++ b/flist/IP/nic400_megasoc_system.flist
@@ -0,0 +1,83 @@
+//-----------------------------------------------------------------------------
+// MegaSoC NIC400 System side bus Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NIC400 System side bus IP
+//-----------------------------------------------------------------------------
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/nic400/verilog/nic400_megasoc_system.v
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/amib_SYS_SRAM/verilog/nic400_amib_SYS_SRAM_chan_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/amib_SYS_SRAM/verilog/nic400_amib_SYS_SRAM_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/asib_DMA/verilog/nic400_asib_DMA_chan_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/asib_DMA/verilog/nic400_asib_DMA_decode_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/asib_DMA/verilog/nic400_asib_DMA_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/asib_DMA/verilog/nic400_asib_DMA_rd_spi_cdas_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/asib_DMA/verilog/nic400_asib_DMA_wr_spi_cdas_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ml_build_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ml_map_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_rd_spi_tt_s0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog/nic400_bm0_wr_spi_tt_s0_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_bypass_sync_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_capt_nosync_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_capt_sync_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_comb_and2_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_comb_mux2_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_comb_or2_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_comb_or3_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_corrupt_gry_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_launch_gry_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog/nic400_cdc_random_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/default_slave_ds_1/verilog/nic400_default_slave_ds_1_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_chan_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_rd_addr_fmt_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_rd_cam_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_rd_chan_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_rd_cntrl_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_resp_cam_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_wr_addr_fmt_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_wr_cntrl_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_wr_merge_buffer_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_wr_mux_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_downsize_wr_resp_block_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_maskcntl_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_master_domain_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog/nic400_ib_DMA_ib_slave_domain_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_ax4_reg_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_ax_reg_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_buf_reg_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_ful_regd_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_fwd_regd_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_rd_reg_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_reg_slice_axi_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_rev_regd_slice_megasoc_system.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog/nic400_wr_reg_slice_megasoc_system.v
+
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/amib_SYS_SRAM/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/asib_DMA/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/busmatrix_bm0/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/cdc_blocks/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/default_slave_ds_1/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/ib_DMA_ib/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/reg_slice/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/nic400/verilog/Axi
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_system/logical/nic400_megasoc_system/nic400/verilog/Axi4PC
\ No newline at end of file
diff --git a/flist/megasoc_tech.flist b/flist/megasoc_tech.flist
index be2fa9195bba334eb6eb52c73d51b6e4b2615d3e..0e4dbda08c6659ab42458b0b4e01c198e74d7f0e 100644
--- a/flist/megasoc_tech.flist
+++ b/flist/megasoc_tech.flist
@@ -19,14 +19,17 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/meg
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
-
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_debug.v
// ARM IP
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/ARM_Cortex_A53.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/CA53_tarmac.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/GIC400.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/nic400_megasoc_main.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/nic400_megasoc_system.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/SIE300_SRAM_controller.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/SIE300_SYS_SRAM_controller.flist
// -f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/PL011.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/Corstone101.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/DMA350.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/SoCDebug_tech.flist
diff --git a/flist/megasoc_tech_BEHAV.flist b/flist/megasoc_tech_BEHAV.flist
index a3d51b46d989a0bd9a483c8977be0bfdd3573f05..1b279c8a87e823b1758ea5fa26f2750bbdaf4576 100644
--- a/flist/megasoc_tech_BEHAV.flist
+++ b/flist/megasoc_tech_BEHAV.flist
@@ -19,6 +19,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/behavioural/ROM_wrapper.v
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM_wrapper.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SYS_SRAM_wrapper.v
-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
diff --git a/flist/megasoc_tech_FPGA.flist b/flist/megasoc_tech_FPGA.flist
index 0961433434a336243ba01f37558502b2d49ce396..23c38328b16c5e6adba63a566025519a38833f18 100644
--- a/flist/megasoc_tech_FPGA.flist
+++ b/flist/megasoc_tech_FPGA.flist
@@ -19,5 +19,6 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/behavioural/ROM_wrapper.v
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/logical/SRAM.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/fpga/SRAM_wrapper.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/fpga/SYS_SRAM_wrapper.v
-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
diff --git a/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v b/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v
index 3e718e8db658953b80f1f93b17c1440b2759fc3b..daec2de3824ca864c54bc04fd36fdb54b1759855 100644
--- a/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v
+++ b/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v
@@ -15,13 +15,14 @@
// ToDo
// -replace SRAM with TSMC ROM
-module ROM_wrapper(
+module ROM_wrapper #(
+ parameter ID_W=8)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [6:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -39,12 +40,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [6:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [6:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -55,7 +56,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [6:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/ROM/ROM_wrapper copy.v b/logical/ROM/ROM_wrapper copy.v
index 9a98e98d88bbb8f4b73d3780cc161ea966c454f8..37b2b5f813198c688757d1fc31f2d718c0804e00 100644
--- a/logical/ROM/ROM_wrapper copy.v
+++ b/logical/ROM/ROM_wrapper copy.v
@@ -12,13 +12,14 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module ROM_wrapper(
+module ROM_wrapper #(
+ parameter ID_W=8)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [5:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +37,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [5:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [5:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +53,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [5:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/ROM/ROM_wrapper.v b/logical/ROM/ROM_wrapper.v
index cec055291e395a7f762b4fe182d6cf244fc6ca50..d83e70946a8f71915a17a603dadc6fef7684294e 100644
--- a/logical/ROM/ROM_wrapper.v
+++ b/logical/ROM/ROM_wrapper.v
@@ -12,13 +12,14 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module ROM_wrapper(
+module ROM_wrapper #(
+ parameter ID_W=8)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [6:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +37,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [6:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [6:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +53,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [6:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/ROM/behavioural/ROM_wrapper.v b/logical/ROM/behavioural/ROM_wrapper.v
index 466afbfbac98942f070374f422934e00beac537e..db6889a607b75792b28d729a7bb4b6cca24f837d 100644
--- a/logical/ROM/behavioural/ROM_wrapper.v
+++ b/logical/ROM/behavioural/ROM_wrapper.v
@@ -12,13 +12,14 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module ROM_wrapper(
+module ROM_wrapper #(
+ parameter ID_W=8)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [6:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +37,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [6:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [6:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +53,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [6:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/behavioural/SRAM_wrapper.v b/logical/SRAM/behavioural/SRAM_wrapper.v
index 668ebac5d48010f0dcc6f212b70e5195ee6a3e8a..dee3d8efc073035782872780e54096049fca859b 100644
--- a/logical/SRAM/behavioural/SRAM_wrapper.v
+++ b/logical/SRAM/behavioural/SRAM_wrapper.v
@@ -12,13 +12,14 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module SRAM_wrapper(
+module SRAM_wrapper#(
+ parameter ID_W=8)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [6:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +37,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [6:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [6:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +53,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [6:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/behavioural/SYS_SRAM_wrapper.v b/logical/SRAM/behavioural/SYS_SRAM_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..a708091a5103ea451f03a4e47049ac64f7a7d52c
--- /dev/null
+++ b/logical/SRAM/behavioural/SYS_SRAM_wrapper.v
@@ -0,0 +1,154 @@
+//-----------------------------------------------------------------------------
+// Megasoc SRAM Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// sie300_axi5_sram_ctrl_expansion_subsystem
+// SRAM
+
+module SYS_SRAM_wrapper#(
+ parameter ID_W=2)(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire AWVALID,
+ output wire AWREADY,
+ input wire [ID_W-1:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [2:0] AWPROT,
+ input wire [3:0] AWQOS,
+
+ input wire WVALID,
+ output wire WREADY,
+ input wire [63:0] WDATA,
+ input wire [7:0] WSTRB,
+ input wire WLAST,
+ input wire WPOISON,
+
+ output wire BVALID,
+ input wire BREADY,
+ output wire [ID_W-1:0] BID,
+ output wire [1:0] BRESP,
+
+ input wire ARVALID,
+ output wire ARREADY,
+ input wire [ID_W-1:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [2:0] ARPROT,
+ input wire [3:0] ARQOS,
+
+ output wire RVALID,
+ input wire RREADY,
+ output wire [ID_W-1:0] RID,
+ output wire [63:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire [1:0] RPOISON,
+ input wire AWAKEUP,
+
+ input wire clk_qreqn,
+ output wire clk_qacceptn,
+ output wire clk_qdeny,
+ output wire clk_qactive,
+
+ input wire pwr_qreqn,
+ output wire pwr_qacceptn,
+ output wire pwr_qdeny,
+ output wire pwr_qactive,
+
+ input wire ext_gt_qreqn,
+ output wire ext_gt_qacceptn,
+ input wire cfg_gate_resp
+);
+
+
+wire [19:0] memaddr;
+wire [63:0] memd;
+wire [63:0] memq;
+wire memcen;
+wire [7:0] memwen;
+
+sie300_axi5_sram_ctrl_sys u_SMC(
+ .aclk(ACLK),
+ .aresetn(ARESETn),
+ .awvalid_s(AWVALID),
+ .awready_s(AWREADY),
+ .awid_s(AWID),
+ .awaddr_s(AWADDR[19:0]),
+ .awlen_s(AWLEN),
+ .awsize_s(AWSIZE),
+ .awburst_s(AWBURST),
+ .awlock_s(AWLOCK),
+ .awprot_s(AWPROT),
+ .awqos_s(AWQOS),
+ .wvalid_s(WVALID),
+ .wready_s(WREADY),
+ .wdata_s(WDATA),
+ .wstrb_s(WSTRB),
+ .wlast_s(WLAST),
+ .wpoison_s(WPOISON),
+ .bvalid_s(BVALID),
+ .bready_s(BREADY),
+ .bid_s(BID),
+ .bresp_s(BRESP),
+ .arvalid_s(ARVALID),
+ .arready_s(ARREADY),
+ .arid_s(ARID),
+ .araddr_s(ARADDR[19:0]),
+ .arlen_s(ARLEN),
+ .arsize_s(ARSIZE),
+ .arburst_s(ARBURST),
+ .arlock_s(ARLOCK),
+ .arprot_s(ARPROT),
+ .arqos_s(ARQOS),
+ .rvalid_s(RVALID),
+ .rready_s(RREADY),
+ .rid_s(RID),
+ .rdata_s(RDATA),
+ .rresp_s(RRESP),
+ .rlast_s(RLAST),
+ .rpoison_s(RPOISON),
+ .awakeup_s(AWAKEUP),
+ .clk_qreqn(clk_qreqn),
+ .clk_qacceptn(clk_qacceptn),
+ .clk_qdeny(clk_qdeny),
+ .clk_qactive(clk_qactive),
+ .pwr_qreqn(pwr_qreqn),
+ .pwr_qacceptn(pwr_qacceptn),
+ .pwr_qdeny(pwr_qdeny),
+ .pwr_qactive(pwr_qactive),
+ .ext_gt_qreqn(ext_gt_qreqn),
+ .ext_gt_qacceptn(ext_gt_qacceptn),
+ .cfg_gate_resp(cfg_gate_resp),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+SRAM u_SRAM(
+ .clk(ACLK),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+
+endmodule
\ No newline at end of file
diff --git a/logical/SRAM/fpga/SRAM_wrapper.v b/logical/SRAM/fpga/SRAM_wrapper.v
index 334924538359b68560df137d321193cb8933942f..edf8f7a3492e5656ac80f71589347f72556fb458 100644
--- a/logical/SRAM/fpga/SRAM_wrapper.v
+++ b/logical/SRAM/fpga/SRAM_wrapper.v
@@ -12,13 +12,14 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module SRAM_wrapper(
+module SRAM_wrapper#(
+ parameter ID_W=8)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [6:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +37,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [6:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [6:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +53,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [6:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/fpga/SYS_SRAM_wrapper.v b/logical/SRAM/fpga/SYS_SRAM_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..67a2102c52c8ec92c392e9414bdd5f6b683c5093
--- /dev/null
+++ b/logical/SRAM/fpga/SYS_SRAM_wrapper.v
@@ -0,0 +1,162 @@
+//-----------------------------------------------------------------------------
+// Megasoc SRAM Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// sie300_axi5_sram_ctrl_expansion_subsystem
+// SRAM
+
+module SYS_SRAM_wrapper#(
+ parameter ID_W=2)(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire AWVALID,
+ output wire AWREADY,
+ input wire [ID_W-1:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [2:0] AWPROT,
+ input wire [3:0] AWQOS,
+
+ input wire WVALID,
+ output wire WREADY,
+ input wire [63:0] WDATA,
+ input wire [7:0] WSTRB,
+ input wire WLAST,
+ input wire WPOISON,
+
+ output wire BVALID,
+ input wire BREADY,
+ output wire [ID_W-1:0] BID,
+ output wire [1:0] BRESP,
+
+ input wire ARVALID,
+ output wire ARREADY,
+ input wire [ID_W-1:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [2:0] ARPROT,
+ input wire [3:0] ARQOS,
+
+ output wire RVALID,
+ input wire RREADY,
+ output wire [ID_W-1:0] RID,
+ output wire [63:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire [1:0] RPOISON,
+ input wire AWAKEUP,
+
+ input wire clk_qreqn,
+ output wire clk_qacceptn,
+ output wire clk_qdeny,
+ output wire clk_qactive,
+
+ input wire pwr_qreqn,
+ output wire pwr_qacceptn,
+ output wire pwr_qdeny,
+ output wire pwr_qactive,
+
+ input wire ext_gt_qreqn,
+ output wire ext_gt_qacceptn,
+ input wire cfg_gate_resp
+);
+
+
+wire [19:0] memaddr;
+wire [63:0] memd;
+wire [63:0] memq;
+wire memcen;
+wire [7:0] memwen;
+
+sie300_axi5_sram_ctrl_sys u_SMC(
+ .aclk(ACLK),
+ .aresetn(ARESETn),
+ .awvalid_s(AWVALID),
+ .awready_s(AWREADY),
+ .awid_s(AWID),
+ .awaddr_s(AWADDR[19:0]),
+ .awlen_s(AWLEN),
+ .awsize_s(AWSIZE),
+ .awburst_s(AWBURST),
+ .awlock_s(AWLOCK),
+ .awprot_s(AWPROT),
+ .awqos_s(AWQOS),
+ .wvalid_s(WVALID),
+ .wready_s(WREADY),
+ .wdata_s(WDATA),
+ .wstrb_s(WSTRB),
+ .wlast_s(WLAST),
+ .wpoison_s(WPOISON),
+ .bvalid_s(BVALID),
+ .bready_s(BREADY),
+ .bid_s(BID),
+ .bresp_s(BRESP),
+ .arvalid_s(ARVALID),
+ .arready_s(ARREADY),
+ .arid_s(ARID),
+ .araddr_s(ARADDR[19:0]),
+ .arlen_s(ARLEN),
+ .arsize_s(ARSIZE),
+ .arburst_s(ARBURST),
+ .arlock_s(ARLOCK),
+ .arprot_s(ARPROT),
+ .arqos_s(ARQOS),
+ .rvalid_s(RVALID),
+ .rready_s(RREADY),
+ .rid_s(RID),
+ .rdata_s(RDATA),
+ .rresp_s(RRESP),
+ .rlast_s(RLAST),
+ .rpoison_s(RPOISON),
+ .awakeup_s(AWAKEUP),
+ .clk_qreqn(clk_qreqn),
+ .clk_qacceptn(clk_qacceptn),
+ .clk_qdeny(clk_qdeny),
+ .clk_qactive(clk_qactive),
+ .pwr_qreqn(pwr_qreqn),
+ .pwr_qacceptn(pwr_qacceptn),
+ .pwr_qdeny(pwr_qdeny),
+ .pwr_qactive(pwr_qactive),
+ .ext_gt_qreqn(ext_gt_qreqn),
+ .ext_gt_qacceptn(ext_gt_qacceptn),
+ .cfg_gate_resp(cfg_gate_resp),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+cmsdk_fpga_sram #(.AW(19)) u_fpga_sram_0(
+ .CLK(ACLK),
+ .ADDR(memaddr),
+ .WDATA(memd[31:0]),
+ .WREN(memwen[3:0]),
+ .CS(memcen),
+ .RDATA(memq[31:0])
+);
+
+cmsdk_fpga_sram #(.AW(19)) u_fpga_sram_1(
+ .CLK(ACLK),
+ .ADDR(memaddr),
+ .WDATA(memd[63:32]),
+ .WREN(memwen[7:4]),
+ .CS(memcen),
+ .RDATA(memq[63:32])
+);
+
+endmodule
\ No newline at end of file
diff --git a/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_debug.v b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_debug.v
new file mode 100644
index 0000000000000000000000000000000000000000..7639375237ace114064c883a5ee9af8c0e4ddc86
--- /dev/null
+++ b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_debug.v
@@ -0,0 +1,156 @@
+
+module megasoc_peripheral_debug #(
+ parameter FT1248_WIDTH=1
+) (
+ input wire HCLK,
+ input wire HRESETn,
+ output wire [31:0] HADDR_ADP,
+ output wire [1:0] HTRANS_ADP,
+ output wire HWRITE_ADP,
+ output wire [2:0] HSIZE_ADP,
+ output wire [2:0] HBURST_ADP,
+ output wire [3:0] HPROT_ADP,
+ output wire [31:0] HWDATA_ADP,
+ input wire [31:0] HRDATA_ADP,
+ input wire HREADY_ADP,
+ input wire HRESP_ADP,
+
+ input wire PCLK,
+ input wire PRESETn,
+ input wire USRT_PSEL,
+ input wire [11:0] USRT_PADDRm,
+ input wire USRT_PENABLE,
+ input wire USRT_PWRITE,
+ input wire [31:0] USRT_PWDATA,
+ output wire [31:0] USRT_PRDATA,
+ output wire USRT_PREADY,
+ output wire USRT_PSLVERR,
+
+ output wire FT_CLK_O, // SCLK
+ output wire FT_SSN_O, // SS_N
+ input wire FT_MISO_I, // MISO
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
+ input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I // MIOSIO tristate input
+
+);
+
+
+ // STDIN to ADP controller
+wire STD_RXD_TVALID;
+wire [ 7:0] STD_RXD_TDATA;
+wire STD_RXD_TREADY;
+// STDOUT to ADP controller
+wire STD_TXD_TVALID;
+wire [ 7:0] STD_TXD_TDATA;
+wire STD_TXD_TREADY;
+
+wire ADP_RXD_TVALID;
+wire [ 7:0] ADP_RXD_TDATA ;
+wire ADP_RXD_TREADY;
+wire ADP_TXD_TVALID;
+wire [ 7:0] ADP_TXD_TDATA ;
+wire ADP_TXD_TREADY;
+
+wire [7:0] GPIO;
+socdebug_ahb u_socdebug_ahb(
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .HADDR32_o(HADDR_ADP),
+ .HBURST3_o(HBURST_ADP),
+ .HMASTLOCK_o(),
+ .HPROT4_o(HPROT_ADP),
+ .HSIZE3_o(HSIZE_ADP),
+ .HTRANS2_o(HTRANS_ADP),
+ .HWDATA32_o(HWDATA_ADP),
+ .HWRITE_o(HWRITE_ADP),
+ .HRDATA32_i(HRDATA_ADP),
+ .HREADY_i(HREADY_ADP),
+ .HRESP_i(HRESP_ADP),
+
+ .ADP_RXD_TVALID_o(ADP_RXD_TVALID),
+ .ADP_RXD_TDATA_o(ADP_RXD_TDATA),
+ .ADP_RXD_TREADY_i(ADP_RXD_TREADY),
+ .ADP_TXD_TVALID_i(ADP_TXD_TVALID),
+ .ADP_TXD_TDATA_i(ADP_TXD_TDATA),
+ .ADP_TXD_TREADY_o(ADP_TXD_TREADY),
+
+ .STD_RXD_TVALID_o(STD_RXD_TVALID),
+ .STD_RXD_TDATA_o(STD_RXD_TDATA),
+ .STD_RXD_TREADY_i(STD_RXD_TREADY),
+ .STD_TXD_TVALID_i(STD_TXD_TVALID),
+ .STD_TXD_TDATA_i(STD_TXD_TDATA),
+ .STD_TXD_TREADY_o(STD_TXD_TREADY),
+
+ .GPO8_o(GPIO),
+ .GPI8_i(GPIO)
+);
+
+// Instantiation of USRT Controller
+socdebug_usrt_control u_usrt_control (
+ // APB Clock and Reset Signals
+ .PCLK (PCLK),
+ .PCLKG (PCLK), // Gated PCLK for bus
+ .PRESETn (PRESETn),
+
+ // APB Interface Signals
+ .PSEL (USRT_PSEL),
+ .PADDR (USRT_PADDRm[11:2]),
+ .PENABLE (USRT_PENABLE),
+ .PWRITE (USRT_PWRITE),
+ .PWDATA (USRT_PWDATA),
+ .PRDATA (USRT_PRDATA),
+ .PREADY (USRT_PREADY),
+ .PSLVERR (USRT_PSLVERR),
+
+ .ECOREVNUM (4'h0),
+
+ // ADP Interface - From USRT to ADP
+ .TX_VALID_o (STD_TXD_TVALID),
+ .TX_DATA8_o (STD_TXD_TDATA ),
+ .TX_READY_i (STD_TXD_TREADY),
+
+ // ADP Interface - From ADP to USRT
+ .RX_VALID_i (STD_RXD_TVALID),
+ .RX_DATA8_i (STD_RXD_TDATA ),
+ .RX_READY_o (STD_RXD_TREADY),
+
+ // Interrupt Interfaces
+ .TXINT ( ), // Transmit Interrupt
+ .RXINT ( ), // Receive Interrupt
+ .TXOVRINT ( ), // Transmit Overrun Interrupt
+ .RXOVRINT ( ), // Receive Overrun Interrupt
+ .UARTINT ( ) // Combined Interrupt
+);
+
+// Instantiation of FT1248 Controller
+socdebug_ft1248_control #(
+ .FT1248_WIDTH (FT1248_WIDTH),
+ .FT1248_CLKON (1)
+) u_ft1248_control (
+ .clk (HCLK),
+ .resetn (HRESETn),
+ .ft_clkdiv (8'd15),
+ .ft_clk_o (FT_CLK_O),
+ .ft_ssn_o (FT_SSN_O),
+ .ft_miso_i (FT_MISO_I),
+ .ft_miosio_o (FT_MIOSIO_O),
+ .ft_miosio_e (FT_MIOSIO_E),
+ .ft_miosio_z (FT_MIOSIO_Z),
+ .ft_miosio_i (FT_MIOSIO_I),
+
+ // ADP Interface - FT1248 to ADP
+ .txd_tvalid (ADP_TXD_TVALID),
+ .txd_tdata (ADP_TXD_TDATA ),
+ .txd_tready (ADP_TXD_TREADY),
+ .txd_tlast ( ),
+
+ // ADP Interface - FT_ADP to FT1248
+ .rxd_tvalid (ADP_RXD_TVALID),
+ .rxd_tdata (ADP_RXD_TDATA ),
+ .rxd_tready (ADP_RXD_TREADY),
+ .rxd_tlast (1'b0)
+);
+
+endmodule
\ No newline at end of file
diff --git a/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
index b038d88ae8caff7252106e513c62a0e6221978ae..21db585475f08c04dbd0e70bf478e3a767f1c9e8 100644
--- a/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
+++ b/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
@@ -16,10 +16,27 @@
// cmsdk_apb_slave_mux (u_apb_slave_mux)
// cmsdk_apb_uart (u_apb_uart_0)
// cmsdk_apb_timer (u_apb_timer0)
+// megasoc_peripheral_debug (u_megasoc_peripheral_debug)
module megasoc_peripheral_subsystem(
input wire PCLK,
input wire PRESETn,
+ input wire HCLK,
+ input wire HRESETn,
+ input wire RT_CLK, // 32kHz real time clock
+
+
+ // ADP AHB bus interface
+ output wire [31:0] HADDR_ADP,
+ output wire [1:0] HTRANS_ADP,
+ output wire HWRITE_ADP,
+ output wire [2:0] HSIZE_ADP,
+ output wire [2:0] HBURST_ADP,
+ output wire [3:0] HPROT_ADP,
+ output wire [31:0] HWDATA_ADP,
+ input wire [31:0] HRDATA_ADP,
+ input wire HREADY_ADP,
+ input wire HRESP_ADP,
// APB bus interface
input wire [31:0] PADDR,
@@ -35,6 +52,15 @@ module megasoc_peripheral_subsystem(
output wire UARTTXD,
output wire UARTTXEN,
+ output wire FT_CLK_O, // SCLK
+ output wire FT_SSN_O, // SS_N
+ input wire FT_MISO_I, // MISO
+ output wire FT_MIOSIO_O, // MIOSIO tristate output when enabled
+ output wire FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
+ output wire FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
+ input wire FT_MIOSIO_I, // MIOSIO tristate input
+
+
output wire [5:0] PERI_IRQS // Peripheral interrupts to GIC
);
@@ -53,11 +79,17 @@ wire PREADY_TIMER0;
wire [31:0] PRDATA_TIMER0;
wire PSLVERR_TIMER0;
+// Internal APB signals for Timer0
+wire PSEL_USRT;
+wire PREADY_USRT;
+wire [31:0] PRDATA_USRT;
+wire PSLVERR_USRT;
+
// CMSDK APB Slave Mux (from Corstone 101)
cmsdk_apb_slave_mux #(
.PORT0_ENABLE(1),
.PORT1_ENABLE(1),
- .PORT2_ENABLE(0),
+ .PORT2_ENABLE(1),
.PORT3_ENABLE(0),
.PORT4_ENABLE(0),
.PORT5_ENABLE(0),
@@ -85,10 +117,10 @@ cmsdk_apb_slave_mux #(
.PRDATA1(PRDATA_TIMER0),
.PSLVERR1(PSLVERR_TIMER0),
- .PSEL2(),
- .PREADY2(1'b0),
- .PRDATA2(32'd0),
- .PSLVERR2(1'b0),
+ .PSEL2(PSEL_USRT),
+ .PREADY2(PREADY_USRT),
+ .PRDATA2(PRDATA_USRT),
+ .PSLVERR2(PSLVERR_USRT),
.PSEL3(),
.PREADY3(1'b0),
@@ -224,4 +256,40 @@ cmsdk_apb_timer u_apb_timer0(
assign PERI_IRQS[5] = timer0_int;
+megasoc_peripheral_debug #(
+ .FT1248_WIDTH(1)
+) u_megasoc_peripheral_debug(
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .HADDR_ADP(HADDR_ADP),
+ .HTRANS_ADP(HTRANS_ADP),
+ .HWRITE_ADP(HWRITE_ADP),
+ .HSIZE_ADP(HSIZE_ADP),
+ .HBURST_ADP(HBURST_ADP),
+ .HPROT_ADP(HPROT_ADP),
+ .HWDATA_ADP(HWDATA_ADP),
+ .HRDATA_ADP(HRDATA_ADP),
+ .HREADY_ADP(HREADY_ADP),
+ .HRESP_ADP(HRESP_ADP),
+
+ .PCLK(PCLK),
+ .PRESETn(PRESETn),
+ .USRT_PSEL(PSEL_USRT),
+ .USRT_PADDRm(PADDR[11:0]),
+ .USRT_PENABLE(PENABLE),
+ .USRT_PWRITE(PWRITE),
+ .USRT_PWDATA(PWDATA),
+ .USRT_PRDATA(PRDATA_USRT),
+ .USRT_PREADY(PREADY_USRT),
+ .USRT_PSLVERR(PSLVERR_USRT),
+
+ .FT_CLK_O(FT_CLK_O),
+ .FT_SSN_O(FT_SSN_O),
+ .FT_MISO_I(FT_MISO_I),
+ .FT_MIOSIO_O(FT_MIOSIO_O),
+ .FT_MIOSIO_E(FT_MIOSIO_E),
+ .FT_MIOSIO_Z(FT_MIOSIO_Z),
+ .FT_MIOSIO_I(FT_MIOSIO_I)
+);
+
endmodule
\ No newline at end of file
diff --git a/logical/socdebug_tech b/logical/socdebug_tech
new file mode 160000
index 0000000000000000000000000000000000000000..049294a8aa4385e4b2e2a03210b315a574e2a787
--- /dev/null
+++ b/logical/socdebug_tech
@@ -0,0 +1 @@
+Subproject commit 049294a8aa4385e4b2e2a03210b315a574e2a787
diff --git a/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
index ccae6fd92ddc8a8bcf2fe094f3ac74334acf0aaa..c58ebf0f3da3321c0fb7b3d03d358d78a541a685 100644
--- a/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
@@ -15,6 +15,7 @@
//-----------------------------------------------------------------------------
// Modules instantiated:
// - ada_top_sldma350_megasoc
+// - nic400_megasoc_system
//-----------------------------------------------------------------------------
// To Do
// - Everything
@@ -89,6 +90,7 @@ module megasoc_tech_system_wrapper(
);
+// DMA AXI Manager 1
wire DMA350_AWAKEUP_M1;
wire DMA350_AWVALID_M1;
wire [44-1:0] DMA350_AWADDR_M1;
@@ -132,6 +134,43 @@ wire [2-1:0] DMA350_BID_M1;
wire [1:0] DMA350_BRESP_M1;
wire DMA350_BREADY_M1;
+// SRAM AXI Signals
+wire [1:0] AWID_SYS_SRAM;
+wire [31:0] AWADDR_SYS_SRAM;
+wire [7:0] AWLEN_SYS_SRAM;
+wire [2:0] AWSIZE_SYS_SRAM;
+wire [1:0] AWBURST_SYS_SRAM;
+wire AWLOCK_SYS_SRAM;
+wire [3:0] AWCACHE_SYS_SRAM;
+wire [2:0] AWPROT_SYS_SRAM;
+wire AWVALID_SYS_SRAM;
+wire AWREADY_SYS_SRAM;
+wire [63:0] WDATA_SYS_SRAM;
+wire [7:0] WSTRB_SYS_SRAM;
+wire WLAST_SYS_SRAM;
+wire WVALID_SYS_SRAM;
+wire WREADY_SYS_SRAM;
+wire [1:0] BID_SYS_SRAM;
+wire [1:0] BRESP_SYS_SRAM;
+wire BVALID_SYS_SRAM;
+wire BREADY_SYS_SRAM;
+wire [1:0] ARID_SYS_SRAM;
+wire [31:0] ARADDR_SYS_SRAM;
+wire [7:0] ARLEN_SYS_SRAM;
+wire [2:0] ARSIZE_SYS_SRAM;
+wire [1:0] ARBURST_SYS_SRAM;
+wire ARLOCK_SYS_SRAM;
+wire [3:0] ARCACHE_SYS_SRAM;
+wire [2:0] ARPROT_SYS_SRAM;
+wire ARVALID_SYS_SRAM;
+wire ARREADY_SYS_SRAM;
+wire [1:0] RID_SYS_SRAM;
+wire [63:0] RDATA_SYS_SRAM;
+wire [1:0] RRESP_SYS_SRAM;
+wire RLAST_SYS_SRAM;
+wire RVALID_SYS_SRAM;
+wire RREADY_SYS_SRAM;
+
ada_top_sldma350_megasoc u_megasoc_dma350(
.clk(CLK),
@@ -140,13 +179,13 @@ ada_top_sldma350_megasoc u_megasoc_dma350(
.aclken_m1(1'b1),
.pclken(1'b1),
- .clk_qreqn(),
+ .clk_qreqn(1'b1),
.clk_qacceptn(),
.clk_qdeny(),
.clk_qactive(),
- .preq(),
- .pstate(),
+ .preq(1'b1),
+ .pstate(4'b1000),
.paccept(),
.pdeny(),
.pactive(),
@@ -263,8 +302,8 @@ ada_top_sldma350_megasoc u_megasoc_dma350(
.trig_out_1_req(),
.trig_out_1_ack(),
- .irq_channel(),
- .irq_comb_nonsec(),
+ .irq_channel(DMA350_irq_channel),
+ .irq_comb_nonsec(DMA350_irq_comb_nonsec),
.str_out_0_tvalid(),
.str_out_0_tready(),
@@ -292,9 +331,9 @@ ada_top_sldma350_megasoc u_megasoc_dma350(
.gpo_ch_0(),
.gpo_ch_1(),
- .allch_stop_req_nonsec(),
+ .allch_stop_req_nonsec(1'b0),
.allch_stop_ack_nonsec(),
- .allch_pause_req_nonsec(),
+ .allch_pause_req_nonsec(1'b0),
.allch_pause_ack_nonsec(),
.ch_enabled(),
@@ -303,14 +342,147 @@ ada_top_sldma350_megasoc u_megasoc_dma350(
.ch_paused(),
.ch_priv(),
- .halt_req(),
- .restart_req(),
+ .halt_req(1'b0),
+ .restart_req(1'b0),
.halted(),
- .boot_en(),
- .boot_addr(),
- .boot_memattr(),
- .boot_shareattr()
+ .boot_en(1'b0),
+ .boot_addr({42{1'b0}}),
+ .boot_memattr({8{1'b0}}),
+ .boot_shareattr({2{1'b0}})
+);
+
+
+nic400_megasoc_system u_nic400_megasoc_system(
+ .AWID_SYS_SRAM(AWID_SYS_SRAM),
+ .AWADDR_SYS_SRAM(AWADDR_SYS_SRAM),
+ .AWLEN_SYS_SRAM(AWLEN_SYS_SRAM),
+ .AWSIZE_SYS_SRAM(AWSIZE_SYS_SRAM),
+ .AWBURST_SYS_SRAM(AWBURST_SYS_SRAM),
+ .AWLOCK_SYS_SRAM(AWLOCK_SYS_SRAM),
+ .AWCACHE_SYS_SRAM(AWCACHE_SYS_SRAM),
+ .AWPROT_SYS_SRAM(AWPROT_SYS_SRAM),
+ .AWVALID_SYS_SRAM(AWVALID_SYS_SRAM),
+ .AWREADY_SYS_SRAM(AWREADY_SYS_SRAM),
+ .WDATA_SYS_SRAM(WDATA_SYS_SRAM),
+ .WSTRB_SYS_SRAM(WSTRB_SYS_SRAM),
+ .WLAST_SYS_SRAM(WLAST_SYS_SRAM),
+ .WVALID_SYS_SRAM(WVALID_SYS_SRAM),
+ .WREADY_SYS_SRAM(WREADY_SYS_SRAM),
+ .BID_SYS_SRAM(BID_SYS_SRAM),
+ .BRESP_SYS_SRAM(BRESP_SYS_SRAM),
+ .BVALID_SYS_SRAM(BVALID_SYS_SRAM),
+ .BREADY_SYS_SRAM(BREADY_SYS_SRAM),
+ .ARID_SYS_SRAM(ARID_SYS_SRAM),
+ .ARADDR_SYS_SRAM(ARADDR_SYS_SRAM),
+ .ARLEN_SYS_SRAM(ARLEN_SYS_SRAM),
+ .ARSIZE_SYS_SRAM(ARSIZE_SYS_SRAM),
+ .ARBURST_SYS_SRAM(ARBURST_SYS_SRAM),
+ .ARLOCK_SYS_SRAM(ARLOCK_SYS_SRAM),
+ .ARCACHE_SYS_SRAM(ARCACHE_SYS_SRAM),
+ .ARPROT_SYS_SRAM(ARPROT_SYS_SRAM),
+ .ARVALID_SYS_SRAM(ARVALID_SYS_SRAM),
+ .ARREADY_SYS_SRAM(ARREADY_SYS_SRAM),
+ .RID_SYS_SRAM(RID_SYS_SRAM),
+ .RDATA_SYS_SRAM(RDATA_SYS_SRAM),
+ .RRESP_SYS_SRAM(RRESP_SYS_SRAM),
+ .RLAST_SYS_SRAM(RLAST_SYS_SRAM),
+ .RVALID_SYS_SRAM(RVALID_SYS_SRAM),
+ .RREADY_SYS_SRAM(RREADY_SYS_SRAM),
+
+ .AWID_DMA(DMA350_AWID_M1),
+ .AWADDR_DMA(DMA350_AWADDR_M1),
+ .AWLEN_DMA(DMA350_AWLEN_M1),
+ .AWSIZE_DMA(DMA350_AWSIZE_M1),
+ .AWBURST_DMA(DMA350_AWBURST_M1),
+ .AWLOCK_DMA(DMA350_AWLOCK_M1),
+ .AWCACHE_DMA(DMA350_AWCACHE_M1),
+ .AWPROT_DMA(DMA350_AWPROT_M1),
+ .AWVALID_DMA(DMA350_AWVALID_M1),
+ .AWREADY_DMA(DMA350_AWREADY_M1),
+ .WDATA_DMA(DMA350_WDATA_M1),
+ .WSTRB_DMA(DMA350_WSTRB_M1),
+ .WLAST_DMA(DMA350_WLAST_M1),
+ .WVALID_DMA(DMA350_WVALID_M1),
+ .WREADY_DMA(DMA350_WREADY_M1),
+ .BID_DMA(DMA350_BID_M1),
+ .BRESP_DMA(DMA350_BRESP_M1),
+ .BVALID_DMA(DMA350_BVALID_M1),
+ .BREADY_DMA(DMA350_BREADY_M1),
+ .ARID_DMA(DMA350_ARID_M1),
+ .ARADDR_DMA(DMA350_ARADDR_M1),
+ .ARLEN_DMA(DMA350_ARLEN_M1),
+ .ARSIZE_DMA(DMA350_ARSIZE_M1),
+ .ARBURST_DMA(DMA350_ARBURST_M1),
+ .ARLOCK_DMA(DMA350_ARLOCK_M1),
+ .ARCACHE_DMA(DMA350_ARCACHE_M1),
+ .ARPROT_DMA(DMA350_ARPROT_M1),
+ .ARVALID_DMA(DMA350_ARVALID_M1),
+ .ARREADY_DMA(DMA350_ARREADY_M1),
+ .RID_DMA(DMA350_RID_M1),
+ .RDATA_DMA(DMA350_RDATA_M1),
+ .RRESP_DMA(DMA350_RRESP_M1),
+ .RLAST_DMA(DMA350_RLAST_M1),
+ .RVALID_DMA(DMA350_RVALID_M1),
+ .RREADY_DMA(DMA350_RREADY_M1),
+
+ .clk0clk(CLK),
+ .clk0resetn(RESETn)
);
+SYS_SRAM_wrapper #(
+ .ID_W(2)
+) u_SYS_SRAM_wrapper(
+ .ACLK(CLK),
+ .ARESETn(RESETn),
+ .AWVALID(AWVALID_SYS_SRAM),
+ .AWREADY(AWREADY_SYS_SRAM),
+ .AWID(AWID_SYS_SRAM),
+ .AWADDR(AWADDR_SYS_SRAM),
+ .AWLEN(AWLEN_SYS_SRAM),
+ .AWSIZE(AWSIZE_SYS_SRAM),
+ .AWBURST(AWBURST_SYS_SRAM),
+ .AWLOCK(AWLOCK_SYS_SRAM),
+ .AWPROT(AWPROT_SYS_SRAM),
+ .AWQOS(4'h0),
+ .WVALID(WVALID_SYS_SRAM),
+ .WREADY(WREADY_SYS_SRAM),
+ .WDATA(WDATA_SYS_SRAM),
+ .WSTRB(WSTRB_SYS_SRAM),
+ .WLAST(WLAST_SYS_SRAM),
+ .WPOISON(1'b0),
+ .BVALID(BVALID_SYS_SRAM),
+ .BREADY(BREADY_SYS_SRAM),
+ .BID(BID_SYS_SRAM),
+ .BRESP(BRESP_SYS_SRAM),
+ .ARVALID(ARVALID_SYS_SRAM),
+ .ARREADY(ARREADY_SYS_SRAM),
+ .ARID(ARID_SYS_SRAM),
+ .ARADDR(ARADDR_SYS_SRAM),
+ .ARLEN(ARLEN_SYS_SRAM),
+ .ARSIZE(ARSIZE_SYS_SRAM),
+ .ARBURST(ARBURST_SYS_SRAM),
+ .ARLOCK(ARLOCK_SYS_SRAM),
+ .ARPROT(ARPROT_SYS_SRAM),
+ .ARQOS(4'h0),
+ .RVALID(RVALID_SYS_SRAM),
+ .RREADY(RREADY_SYS_SRAM),
+ .RID(RID_SYS_SRAM),
+ .RDATA(RDATA_SYS_SRAM),
+ .RRESP(RRESP_SYS_SRAM),
+ .RLAST(RLAST_SYS_SRAM),
+ .RPOISON(),
+ .AWAKEUP(1'b1),
+ .clk_qreqn(1'b1),
+ .clk_qacceptn(),
+ .clk_qdeny(),
+ .clk_qactive(),
+ .pwr_qreqn(1'b1),
+ .pwr_qacceptn(),
+ .pwr_qdeny(),
+ .pwr_qactive(),
+ .ext_gt_qreqn(1'b1),
+ .ext_gt_qacceptn(),
+ .cfg_gate_resp(1'b0)
+);
endmodule
\ No newline at end of file
diff --git a/logical/top_megasoc_tech/megasoc_tech_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
index fecd4441cff427949dc49379a01b468fdd6ec3cc..5502956b9a286963cba276dc6b2d16b76edeb0be 100644
--- a/logical/top_megasoc_tech/megasoc_tech_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
@@ -28,110 +28,176 @@
`timescale 1ns/1ps
module megasoc_tech_wrapper(
- input wire SYS_CLK,
- input wire SYS_CLKEN,
- input wire SYS_RESETn,
+ input wire SYS_CLK,
+ input wire SYS_CLKEN,
+ input wire RT_CLK, // 32kHz real time clock
+ input wire SYS_RESETn,
// Millisoc system AXI Manager
- output wire [1:0] AXI_SYS_EXP_awid,
- output wire [31:0] AXI_SYS_EXP_awaddr,
- output wire [7:0] AXI_SYS_EXP_awlen,
- output wire [2:0] AXI_SYS_EXP_awsize,
- output wire [1:0] AXI_SYS_EXP_awburst,
- output wire AXI_SYS_EXP_awlock,
- output wire [3:0] AXI_SYS_EXP_awcache,
- output wire [2:0] AXI_SYS_EXP_awprot,
- output wire AXI_SYS_EXP_awvalid,
- input wire AXI_SYS_EXP_awready,
- output wire [63:0] AXI_SYS_EXP_wdata,
- output wire [7:0] AXI_SYS_EXP_wstrb,
- output wire AXI_SYS_EXP_wlast,
- output wire AXI_SYS_EXP_wvalid,
- input wire AXI_SYS_EXP_wready,
- input wire [1:0] AXI_SYS_EXP_bid,
- input wire [1:0] AXI_SYS_EXP_bresp,
- input wire AXI_SYS_EXP_bvalid,
- output wire AXI_SYS_EXP_bready,
- output wire [1:0] AXI_SYS_EXP_arid,
- output wire [31:0] AXI_SYS_EXP_araddr,
- output wire [7:0] AXI_SYS_EXP_arlen,
- output wire [2:0] AXI_SYS_EXP_arsize,
- output wire [1:0] AXI_SYS_EXP_arburst,
- output wire AXI_SYS_EXP_arlock,
- output wire [3:0] AXI_SYS_EXP_arcache,
- output wire [2:0] AXI_SYS_EXP_arprot,
- output wire AXI_SYS_EXP_arvalid,
- input wire AXI_SYS_EXP_arready,
- input wire [1:0] AXI_SYS_EXP_rid,
- input wire [63:0] AXI_SYS_EXP_rdata,
- input wire [1:0] AXI_SYS_EXP_rresp,
- input wire AXI_SYS_EXP_rlast,
- input wire AXI_SYS_EXP_rvalid,
- output wire AXI_SYS_EXP_rready,
+ output wire [1:0] AXI_SYS_EXP_awid,
+ output wire [31:0] AXI_SYS_EXP_awaddr,
+ output wire [7:0] AXI_SYS_EXP_awlen,
+ output wire [2:0] AXI_SYS_EXP_awsize,
+ output wire [1:0] AXI_SYS_EXP_awburst,
+ output wire AXI_SYS_EXP_awlock,
+ output wire [3:0] AXI_SYS_EXP_awcache,
+ output wire [2:0] AXI_SYS_EXP_awprot,
+ output wire AXI_SYS_EXP_awvalid,
+ input wire AXI_SYS_EXP_awready,
+ output wire [63:0] AXI_SYS_EXP_wdata,
+ output wire [7:0] AXI_SYS_EXP_wstrb,
+ output wire AXI_SYS_EXP_wlast,
+ output wire AXI_SYS_EXP_wvalid,
+ input wire AXI_SYS_EXP_wready,
+ input wire [1:0] AXI_SYS_EXP_bid,
+ input wire [1:0] AXI_SYS_EXP_bresp,
+ input wire AXI_SYS_EXP_bvalid,
+ output wire AXI_SYS_EXP_bready,
+ output wire [1:0] AXI_SYS_EXP_arid,
+ output wire [31:0] AXI_SYS_EXP_araddr,
+ output wire [7:0] AXI_SYS_EXP_arlen,
+ output wire [2:0] AXI_SYS_EXP_arsize,
+ output wire [1:0] AXI_SYS_EXP_arburst,
+ output wire AXI_SYS_EXP_arlock,
+ output wire [3:0] AXI_SYS_EXP_arcache,
+ output wire [2:0] AXI_SYS_EXP_arprot,
+ output wire AXI_SYS_EXP_arvalid,
+ input wire AXI_SYS_EXP_arready,
+ input wire [1:0] AXI_SYS_EXP_rid,
+ input wire [63:0] AXI_SYS_EXP_rdata,
+ input wire [1:0] AXI_SYS_EXP_rresp,
+ input wire AXI_SYS_EXP_rlast,
+ input wire AXI_SYS_EXP_rvalid,
+ output wire AXI_SYS_EXP_rready,
// Millisoc system AXI Subordinate
- input wire AXI_EXP_SYS_awid,
- input wire [31:0] AXI_EXP_SYS_awaddr,
- input wire [7:0] AXI_EXP_SYS_awlen,
- input wire [2:0] AXI_EXP_SYS_awsize,
- input wire [1:0] AXI_EXP_SYS_awburst,
- input wire AXI_EXP_SYS_awlock,
- input wire [3:0] AXI_EXP_SYS_awcache,
- input wire [2:0] AXI_EXP_SYS_awprot,
- input wire AXI_EXP_SYS_awvalid,
- output wire AXI_EXP_SYS_awready,
- input wire [63:0] AXI_EXP_SYS_wdata,
- input wire [7:0] AXI_EXP_SYS_wstrb,
- input wire AXI_EXP_SYS_wlast,
- input wire AXI_EXP_SYS_wvalid,
- output wire AXI_EXP_SYS_wready,
- output wire AXI_EXP_SYS_bid,
- output wire [1:0] AXI_EXP_SYS_bresp,
- output wire AXI_EXP_SYS_bvalid,
- input wire AXI_EXP_SYS_bready,
- input wire AXI_EXP_SYS_arid,
- input wire [31:0] AXI_EXP_SYS_araddr,
- input wire [7:0] AXI_EXP_SYS_arlen,
- input wire [2:0] AXI_EXP_SYS_arsize,
- input wire [1:0] AXI_EXP_SYS_arburst,
- input wire AXI_EXP_SYS_arlock,
- input wire [3:0] AXI_EXP_SYS_arcache,
- input wire [2:0] AXI_EXP_SYS_arprot,
- input wire AXI_EXP_SYS_arvalid,
- output wire AXI_EXP_SYS_arready,
- output wire AXI_EXP_SYS_rid,
- output wire [63:0] AXI_EXP_SYS_rdata,
- output wire [1:0] AXI_EXP_SYS_rresp,
- output wire AXI_EXP_SYS_rlast,
- output wire AXI_EXP_SYS_rvalid,
- input wire AXI_EXP_SYS_rready,
+ input wire AXI_EXP_SYS_awid,
+ input wire [31:0] AXI_EXP_SYS_awaddr,
+ input wire [7:0] AXI_EXP_SYS_awlen,
+ input wire [2:0] AXI_EXP_SYS_awsize,
+ input wire [1:0] AXI_EXP_SYS_awburst,
+ input wire AXI_EXP_SYS_awlock,
+ input wire [3:0] AXI_EXP_SYS_awcache,
+ input wire [2:0] AXI_EXP_SYS_awprot,
+ input wire AXI_EXP_SYS_awvalid,
+ output wire AXI_EXP_SYS_awready,
+ input wire [63:0] AXI_EXP_SYS_wdata,
+ input wire [7:0] AXI_EXP_SYS_wstrb,
+ input wire AXI_EXP_SYS_wlast,
+ input wire AXI_EXP_SYS_wvalid,
+ output wire AXI_EXP_SYS_wready,
+ output wire AXI_EXP_SYS_bid,
+ output wire [1:0] AXI_EXP_SYS_bresp,
+ output wire AXI_EXP_SYS_bvalid,
+ input wire AXI_EXP_SYS_bready,
+ input wire AXI_EXP_SYS_arid,
+ input wire [31:0] AXI_EXP_SYS_araddr,
+ input wire [7:0] AXI_EXP_SYS_arlen,
+ input wire [2:0] AXI_EXP_SYS_arsize,
+ input wire [1:0] AXI_EXP_SYS_arburst,
+ input wire AXI_EXP_SYS_arlock,
+ input wire [3:0] AXI_EXP_SYS_arcache,
+ input wire [2:0] AXI_EXP_SYS_arprot,
+ input wire AXI_EXP_SYS_arvalid,
+ output wire AXI_EXP_SYS_arready,
+ output wire AXI_EXP_SYS_rid,
+ output wire [63:0] AXI_EXP_SYS_rdata,
+ output wire [1:0] AXI_EXP_SYS_rresp,
+ output wire AXI_EXP_SYS_rlast,
+ output wire AXI_EXP_SYS_rvalid,
+ input wire AXI_EXP_SYS_rready,
+
+ // DMA 350 APB Interface Wires
+ output wire [31:0] PADDR_DMA_CTRL,
+ output wire [31:0] PWDATA_DMA_CTRL,
+ output wire PWRITE_DMA_CTRL,
+ output wire [2:0] PPROT_DMA_CTRL,
+ output wire [3:0] PSTRB_DMA_CTRL,
+ output wire PENABLE_DMA_CTRL,
+ output wire PSELx_DMA_CTRL,
+ input wire [31:0] PRDATA_DMA_CTRL,
+ input wire PSLVERR_DMA_CTRL,
+ input wire PREADY_DMA_CTRL,
+
+ // DMA 350 AXI Interface Wires
+ input wire [1:0] AWID_DMA350,
+ input wire [43:0] AWADDR_DMA350,
+ input wire [7:0] AWLEN_DMA350,
+ input wire [2:0] AWSIZE_DMA350,
+ input wire [1:0] AWBURST_DMA350,
+ input wire AWLOCK_DMA350,
+ input wire [3:0] AWCACHE_DMA350,
+ input wire [2:0] AWPROT_DMA350,
+ input wire AWVALID_DMA350,
+ output wire AWREADY_DMA350,
+
+ input wire [127:0] WDATA_DMA350,
+ input wire [15:0] WSTRB_DMA350,
+ input wire WLAST_DMA350,
+ input wire WVALID_DMA350,
+ output wire WREADY_DMA350,
+
+ output wire [1:0] BID_DMA350,
+ output wire [1:0] BRESP_DMA350,
+ output wire BVALID_DMA350,
+ input wire BREADY_DMA350,
+
+ input wire [1:0] ARID_DMA350,
+ input wire [43:0] ARADDR_DMA350,
+ input wire [7:0] ARLEN_DMA350,
+ input wire [2:0] ARSIZE_DMA350,
+ input wire [1:0] ARBURST_DMA350,
+ input wire ARLOCK_DMA350,
+ input wire [3:0] ARCACHE_DMA350,
+ input wire [2:0] ARPROT_DMA350,
+ input wire ARVALID_DMA350,
+ output wire ARREADY_DMA350,
+
+ output wire [1:0] RID_DMA350,
+ output wire [127:0] RDATA_DMA350,
+ output wire [1:0] RRESP_DMA350,
+ output wire RLAST_DMA350,
+ output wire RVALID_DMA350,
+ input wire RREADY_DMA350,
+
+ input wire [3:0] DMA350_irq_channel,
+ input wire DMA350_irq_comb_nonsec,
// QSPI Signals
- output wire QSPI_SCLK,
- output wire QSPI_nCS,
- output wire [3:0] QSPI_IO_o,
- input wire [3:0] QSPI_IO_i,
- output wire [3:0] QSPI_IO_e,
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+ output wire [3:0] QSPI_IO_o,
+ input wire [3:0] QSPI_IO_i,
+ output wire [3:0] QSPI_IO_e,
// UART signals
- input wire UARTRXD,
- output wire UARTTXD,
- output wire UARTTXEN,
+ input wire UARTRXD,
+ output wire UARTTXD,
+ output wire UARTTXEN,
+
+ // FT1248 Signals
+ output wire FT_CLK_O, // SCLK
+ output wire FT_SSN_O, // SS_N
+ input wire FT_MISO_I, // MISO
+ output wire FT_MIOSIO_O, // MIOSIO tristate output when enabled
+ output wire FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
+ output wire FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
+ input wire FT_MIOSIO_I, // MIOSIO tristate input
// DAP-LITE external signals
- input wire nTRST,
- input wire SWCLKTCK,
- input wire SWDITMS,
- input wire TDI,
- output wire TDO,
- output wire nTDOEN,
- output wire SWDO,
- output wire SWDOEN
+ input wire nTRST,
+ input wire SWCLKTCK,
+ input wire SWDITMS,
+ input wire TDI,
+ output wire TDO,
+ output wire nTDOEN,
+ output wire SWDO,
+ output wire SWDOEN
);
-parameter ID_W=7;
+parameter ID_W=8;
parameter NUM_SPIS=480;
wire CPU_AWREADYM;
@@ -361,58 +427,17 @@ wire [ 31: 0] CPU_PRDATADBG;
wire CPU_PREADYDBG;
wire CPU_PSLVERRDBG;
-// DMA 350 APB Interface Wires
-wire [31:0] PADDR_DMA_CTRL;
-wire [31:0] PWDATA_DMA_CTRL;
-wire PWRITE_DMA_CTRL;
-wire [2:0] PPROT_DMA_CTRL;
-wire [3:0] PSTRB_DMA_CTRL;
-wire PENABLE_DMA_CTRL;
-wire PSELx_DMA_CTRL;
-wire [31:0] PRDATA_DMA_CTRL;
-wire PSLVERR_DMA_CTRL;
-wire PREADY_DMA_CTRL;
-
-// DMA 350 AXI Interface Wires
-wire [1:0] AWID_DMA350;
-wire [43:0] AWADDR_DMA350;
-wire [7:0] AWLEN_DMA350;
-wire [2:0] AWSIZE_DMA350;
-wire [1:0] AWBURST_DMA350;
-wire AWLOCK_DMA350;
-wire [3:0] AWCACHE_DMA350;
-wire [2:0] AWPROT_DMA350;
-wire AWVALID_DMA350;
-wire AWREADY_DMA350;
-
-wire [127:0] WDATA_DMA350;
-wire [15:0] WSTRB_DMA350;
-wire WLAST_DMA350;
-wire WVALID_DMA350;
-wire WREADY_DMA350;
-
-wire [1:0] BID_DMA350;
-wire [1:0] BRESP_DMA350;
-wire BVALID_DMA350;
-wire BREADY_DMA350;
-
-wire [1:0] ARID_DMA350;
-wire [43:0] ARADDR_DMA350;
-wire [7:0] ARLEN_DMA350;
-wire [2:0] ARSIZE_DMA350;
-wire [1:0] ARBURST_DMA350;
-wire ARLOCK_DMA350;
-wire [3:0] ARCACHE_DMA350;
-wire [2:0] ARPROT_DMA350;
-wire ARVALID_DMA350;
-wire ARREADY_DMA350;
-
-wire [1:0] RID_DMA350;
-wire [127:0] RDATA_DMA350;
-wire [1:0] RRESP_DMA350;
-wire RLAST_DMA350;
-wire RVALID_DMA350;
-wire RREADY_DMA350;
+// ADP debug AHB port
+wire [31:0] HADDR_ADP;
+wire [1:0] HTRANS_ADP;
+wire HWRITE_ADP;
+wire [2:0] HSIZE_ADP;
+wire [2:0] HBURST_ADP;
+wire [3:0] HPROT_ADP;
+wire [31:0] HWDATA_ADP;
+wire [31:0] HRDATA_ADP;
+wire HREADY_ADP;
+wire HRESP_ADP;
assign CPU_nPRESETDBG = SYS_RESETn;
assign CPU_PCLKENDBG = 1'b1;
@@ -421,7 +446,7 @@ assign CPU_PADDRDBG31 = 1'b0;
wire [(NUM_SPIS-1):0] CPU_IRQS;
wire [5:0] PERI_IRQS;
-assign CPU_IRQS={{(NUM_SPIS-38){1'b0}}, PERI_IRQS};
+assign CPU_IRQS={{(NUM_SPIS-38){1'b0}}, PERI_IRQS, DMA350_irq_comb_nonsec, DMA350_irq_channel};
megasoc_cpu_ss #(
.NUM_GICRID_BITS(ID_W-1),
@@ -774,6 +799,17 @@ nic400_megasoc_main u_nic400_megasoc_main(
.RVALID_A53(CPU_RVALIDM),
.RREADY_A53(CPU_RREADYM),
+ .HADDR_ADP(HADDR_ADP),
+ .HTRANS_ADP(HTRANS_ADP),
+ .HWRITE_ADP(HWRITE_ADP),
+ .HSIZE_ADP(HSIZE_ADP),
+ .HBURST_ADP(HBURST_ADP),
+ .HPROT_ADP(HPROT_ADP),
+ .HWDATA_ADP(HWDATA_ADP),
+ .HRDATA_ADP(HRDATA_ADP),
+ .HREADY_ADP(HREADY_ADP),
+ .HRESP_ADP(HRESP_ADP),
+
.AWID_DMA350(AWID_DMA350),
.AWADDR_DMA350(AWADDR_DMA350),
.AWLEN_DMA350(AWLEN_DMA350),
@@ -961,6 +997,21 @@ SRAM_wrapper u_SRAM_wrapper(
megasoc_peripheral_subsystem u_megasoc_peripheral_subsystem(
.PCLK(SYS_CLK),
.PRESETn(SYS_RESETn),
+ .HCLK(SYS_CLK),
+ .HRESETn(SYS_RESETn),
+ .RT_CLK(RT_CLK),
+
+ .HADDR_ADP(HADDR_ADP),
+ .HTRANS_ADP(HTRANS_ADP),
+ .HWRITE_ADP(HWRITE_ADP),
+ .HSIZE_ADP(HSIZE_ADP),
+ .HBURST_ADP(HBURST_ADP),
+ .HPROT_ADP(HPROT_ADP),
+ .HWDATA_ADP(HWDATA_ADP),
+ .HRDATA_ADP(HRDATA_ADP),
+ .HREADY_ADP(HREADY_ADP),
+ .HRESP_ADP(HRESP_ADP),
+
.PADDR(PADDR_PERIPHERAL),
.PENABLE(PENABLE_PERIPHERAL),
.PWRITE(PWRITE_PERIPHERAL),
@@ -969,78 +1020,21 @@ megasoc_peripheral_subsystem u_megasoc_peripheral_subsystem(
.PRDATA(PRDATA_PERIPHERAL),
.PREADY(PREADY_PERIPHERAL),
.PSLVERR(PSLVERR_PERIPHERAL),
+
.UARTRXD(UARTRXD),
.UARTTXD(UARTTXD),
.UARTTXEN(UARTTXEN),
- .PERI_IRQS(PERI_IRQS)
-);
-megasoc_tech_system_wrapper u_megasoc_tech_system_wrapper(
- .CLK(SYS_CLK),
- .RESETn(SYS_RESETn),
+ .FT_CLK_O(FT_CLK_O),
+ .FT_SSN_O(FT_SSN_O),
+ .FT_MISO_I(FT_MISO_I),
+ .FT_MIOSIO_O(FT_MIOSIO_O),
+ .FT_MIOSIO_E(FT_MIOSIO_E),
+ .FT_MIOSIO_Z(FT_MIOSIO_Z),
+ .FT_MIOSIO_I(FT_MIOSIO_I),
- .DMA350_PWAKEUP(1'b1),
- .DMA350_PDEBUG(1'b0),
- .DMA350_PSEL(PSELx_DMA_CTRL),
- .DMA350_PENABLE(PENABLE_DMA_CTRL),
- .DMA350_PPROT(PPROT_DMA_CTRL),
- .DMA350_PWRITE(PWRITE_DMA_CTRL),
- .DMA350_PADDR(PADDR_DMA_CTRL),
- .DMA350_PWDATA(PWDATA_DMA_CTRL),
- .DMA350_PSTRB(PSTRB_DMA_CTRL),
- .DMA350_PREADY(PREADY_DMA_CTRL),
- .DMA350_PSLVERR(PSLVERR_DMA_CTRL),
- .DMA350_PRDATA(PRDATA_DMA_CTRL),
-
- .DMA350_AWAKEUP_M0(),
- .DMA350_AWVALID_M0(AWVALID_DMA350),
- .DMA350_AWADDR_M0(AWADDR_DMA350),
- .DMA350_AWBURST_M0(AWBURST_DMA350),
- .DMA350_AWID_M0(AWID_DMA350),
- .DMA350_AWLEN_M0(AWLEN_DMA350),
- .DMA350_AWSIZE_M0(AWSIZE_DMA350),
- .DMA350_AWQOS_M0(),
- .DMA350_AWPROT_M0(AWPROT_DMA350),
- .DMA350_AWREADY_M0(AWREADY_DMA350),
- .DMA350_AWCACHE_M0(AWCACHE_DMA350),
- .DMA350_AWINNER_M0(),
- .DMA350_AWDOMAIN_M0(),
-
- .DMA350_ARVALID_M0(ARVALID_DMA350),
- .DMA350_ARADDR_M0(ARADDR_DMA350),
- .DMA350_ARBURST_M0(ARBURST_DMA350),
- .DMA350_ARID_M0(ARID_DMA350),
- .DMA350_ARLEN_M0(ARLEN_DMA350),
- .DMA350_ARSIZE_M0(ARSIZE_DMA350),
- .DMA350_ARQOS_M0(),
- .DMA350_ARPROT_M0(ARPROT_DMA350),
- .DMA350_ARREADY_M0(ARREADY_DMA350),
- .DMA350_ARCACHE_M0(ARCACHE_DMA350),
- .DMA350_ARINNER_M0(),
- .DMA350_ARDOMAIN_M0(),
- .DMA350_ARCMDLINK_M0(),
-
- .DMA350_WVALID_M0(WVALID_DMA350),
- .DMA350_WLAST_M0(WLAST_DMA350),
- .DMA350_WSTRB_M0(WSTRB_DMA350),
- .DMA350_WDATA_M0(WDATA_DMA350),
- .DMA350_WREADY_M0(WREADY_DMA350),
-
- .DMA350_RVALID_M0(RVALID_DMA350),
- .DMA350_RID_M0(RID_DMA350),
- .DMA350_RLAST_M0(RLAST_DMA350),
- .DMA350_RDATA_M0(RDATA_DMA350),
- .DMA350_RPOISON_M0(2'b00),
- .DMA350_RRESP_M0(RRESP_DMA350),
- .DMA350_RREADY_M0(RREADY_DMA350),
-
- .DMA350_BVALID_M0(BVALID_DMA350),
- .DMA350_BID_M0(BID_DMA350),
- .DMA350_BRESP_M0(BRESP_DMA350),
- .DMA350_BREADY_M0(BREADY_DMA350),
-
- .DMA350_irq_channel(),
- .DMA350_irq_comb_nonsec()
+ .PERI_IRQS(PERI_IRQS)
);
+
endmodule
\ No newline at end of file
diff --git a/makefile b/makefile
index 5116330a126046d42cb76d9d97b857a7a93fad77..131182aee634b1e55435fad713b0b70ff46da3fd 100644
--- a/makefile
+++ b/makefile
@@ -14,6 +14,7 @@ include ./make.cfg
build_sie300_sram_ctrl:
@$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/sie300/
+ @$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SYS_SRAM_ctrl.yaml --output ./logical/sie300/
build_nic400:
socrates_cli --project megasoc_tech -data ../ --flow build.configured.component configuredComponentName=nic400_megasoc_main
build_cortex_a53:
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index 59786c262ee0fa40a8ebd59afb2a0e9ddc369b2e..6a19349af712c9b02c3030b00da9730e4e71f38f 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -15,14 +15,14 @@ COMPONENT : sie300_axi5_sram_ctrl
CONFIG_NAME : 1
ADDR_WIDTH : 20
DATA_WIDTH : 64
-ID_WIDTH : 7
+ID_WIDTH : 8
QCLK_SYNC_EN : 1
QPWR_SYNC_EN : 1
QEXT_SYNC_EN : 1
EXCLUSIVE_MONITORS : 2
-AR_BUF_SIZE : 1
-AW_BUF_SIZE : 2
-W_BUF_SIZE : 8
+AR_BUF_SIZE : 4
+AW_BUF_SIZE : 4
+W_BUF_SIZE : 16
AXI5_POISON_EN : 1
-REGISTER_AXI_AR : BYPASS
-REGISTER_AXI_R : BYPASS
+REGISTER_AXI_AR : FULL
+REGISTER_AXI_R : FULL
diff --git a/socrates/BP301_SRAM/config/SYS_SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SYS_SRAM_ctrl.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..fddf5c03667e60d2c948bd3067ed11fd48aab713
--- /dev/null
+++ b/socrates/BP301_SRAM/config/SYS_SRAM_ctrl.yaml
@@ -0,0 +1,28 @@
+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2019 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+COMPONENT : sie300_axi5_sram_ctrl
+CONFIG_NAME : sys
+ADDR_WIDTH : 20
+DATA_WIDTH : 64
+ID_WIDTH : 2
+QCLK_SYNC_EN : 1
+QPWR_SYNC_EN : 1
+QEXT_SYNC_EN : 1
+EXCLUSIVE_MONITORS : 2
+AR_BUF_SIZE : 4
+AW_BUF_SIZE : 4
+W_BUF_SIZE : 16
+AXI5_POISON_EN : 1
+REGISTER_AXI_AR : FULL
+REGISTER_AXI_R : FULL
diff --git a/socrates/DMA350/config/cfg_dma_megasoc.yaml b/socrates/DMA350/config/cfg_dma_megasoc.yaml
index 2de59513968b6368db571821e7d6fac56213a9ee..e6782c2b3bebf804f2f4650456a0b82b7f9140c4 100644
--- a/socrates/DMA350/config/cfg_dma_megasoc.yaml
+++ b/socrates/DMA350/config/cfg_dma_megasoc.yaml
@@ -165,4 +165,4 @@ SECEXT_PRESENT: 0
#
# Valid values:
# relative path to logical
-AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_example1.sv
+AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_megasoc.sv
diff --git a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
index ecedde4115f2c657053e672dd042e1ff9d511936..2b5135a0edd381a8836f4a76760c11d9bc1129ce 100644
--- a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
+++ b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>7</GlobalIDWidth>
+ <GlobalIDWidth>8</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -260,6 +260,31 @@
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
+ <SlaveInterface>
+ <Name>ADP</Name>
+ <AHBLiteInitiatorSlaveProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <AUSEREnabled>false</AUSEREnabled>
+ <RUSEREnabled>false</RUSEREnabled>
+ <WUSEREnabled>false</WUSEREnabled>
+ <LockSupport>false</LockSupport>
+ <TrustZoneSlaveAHB>secure</TrustZoneSlaveAHB>
+ <ReadAcceptanceAHB>1</ReadAcceptanceAHB>
+ <WriteAcceptance>4</WriteAcceptance>
+ <QoSTypeAHB>fixed</QoSTypeAHB>
+ <QoSValue>0</QoSValue>
+ <TransactionRateRegulation>false</TransactionRateRegulation>
+ <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
+ <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
+ <EnableEarlyWriteResponse>true</EnableEarlyWriteResponse>
+ </AHBLiteInitiatorSlaveProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ <MultiPorted>false</MultiPorted>
+ <CyclicDependencyAvoidanceScheme>single_slave</CyclicDependencyAvoidanceScheme>
+ <LowLatency>false</LowLatency>
+ </SlaveInterface>
</Interfaces>
<MemoryMaps>
<MemoryMap>
@@ -267,6 +292,9 @@
<MemoryMapSource>
<InterfaceRef>A53</InterfaceRef>
</MemoryMapSource>
+ <MemoryMapSource>
+ <InterfaceRef>ADP</InterfaceRef>
+ </MemoryMapSource>
<MappedBlock>
<InterfaceRef>ROM</InterfaceRef>
<Offset>0</Offset>
@@ -363,12 +391,6 @@
<Range>536870912</Range>
<Visibility>true</Visibility>
</MappedBlock>
- <MappedBlock>
- <InterfaceRef>DMA_CTRL</InterfaceRef>
- <Offset>16842752</Offset>
- <Range>8192</Range>
- <Visibility>true</Visibility>
- </MappedBlock>
</MemoryMap>
</MemoryMaps>
<Paths>
@@ -431,14 +453,47 @@
</Target>
</Targets>
</Path>
+ <Path>
+ <Source>
+ <InterfaceRef>ADP</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>ROM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>FLASH</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>RAM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>PERIPHERAL</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>DRAM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>FLASH_CTRL</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>DEBUG</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>GIC</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>DMA_CTRL</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
</Paths>
<VirtualNetworks/>
</Specification>
<Architecture>
- <NICConfigFile><?xml version="1.0" encoding="iso-8859-1" ?>
-<periph>
- <product_version_info minor_code="50000" minor_version="0" major_group="bu" minor_revision="2" major_revision="1" product_code="nic400" major_version="00" part_quality="rel"/>
- <validator_version_info minor_revision="1" major_revision="22"/>
+ <NICConfigFile><periph>
+ <product_version_info major_group="bu" major_revision="1" major_version="00" minor_code="50000" minor_revision="2" minor_version="0" part_quality="rel" product_code="nic400" />
+ <validator_version_info major_revision="22" minor_revision="1" />
<global>
<address0x0 def="true">bottom</address0x0>
<aruser_width>0</aruser_width>
@@ -453,7 +508,7 @@
<hcg_en>false</hcg_en>
<license_status>unlicensed_nic</license_status>
<periph_id3 def="true">0</periph_id3>
- <pl_id_width>7</pl_id_width>
+ <pl_id_width>8</pl_id_width>
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
@@ -462,7 +517,7 @@
<taxonomy>masterslave</taxonomy>
<thin_links_status def="true">false</thin_links_status>
<uppercase_ext_sig>true</uppercase_ext_sig>
- <virtual_networks/>
+ <virtual_networks />
<virtual_networks_status>false</virtual_networks_status>
<wuser_width>0</wuser_width>
</global>
@@ -686,8 +741,8 @@
<vid_width>6</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>110</x>
- <y>91</y>
+ <x>0</x>
+ <y>20</y>
<master_if_port_name>A53_m</master_if_port_name>
<slave_if_port_name>A53_s</slave_if_port_name>
</asib>
@@ -878,11 +933,209 @@
<vid_width>2</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>110</x>
- <y>61</y>
+ <x>0</x>
+ <y>40</y>
<master_if_port_name>DMA350_m</master_if_port_name>
<slave_if_port_name>DMA350_s</slave_if_port_name>
</asib>
+ <asib>
+ <address_ranges>
+ <name>CPU_MM</name>
+ <range>
+ <addr_max>0xFFFF</addr_max>
+ <addr_min>0x0</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>ROM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x7FFFFF</addr_max>
+ <addr_min>0x400000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>FLASH</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x80FFFF</addr_max>
+ <addr_min>0x800000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>RAM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x5FFFFFFF</addr_max>
+ <addr_min>0x40000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>PERIPHERAL</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0xFFFFFFFF</addr_max>
+ <addr_min>0x80000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>DRAM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x100FFFF</addr_max>
+ <addr_min>0x1000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>FLASH_CTRL</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x7FFFFFFF</addr_max>
+ <addr_min>0x60000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>DEBUG</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x1107FFF</addr_max>
+ <addr_min>0x1100000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>GIC</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x1011FFF</addr_max>
+ <addr_min>0x1010000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>DMA_CTRL</target>
+ </remap>
+ </range>
+ </address_ranges>
+ <apb_config>false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <broken_bursts>false</broken_bursts>
+ <cds>singleslave</cds>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <ewr_incr_promotion>true</ewr_incr_promotion>
+ <master_if_data_width>64</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>ADP</name>
+ <protocol>ahb_mm</protocol>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <qv>
+ <type>fixed</type>
+ <value>0</value>
+ </qv>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>a</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>d</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>a</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>d</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_addr_width>32</slave_if_addr_width>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>sec</trustzone>
+ <vid_width>0</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>60</y>
+ <master_if_port_name>ADP_m</master_if_port_name>
+ <slave_if_port_name>ADP_s</slave_if_port_name>
+ </asib>
<amib>
<apb_config>false</apb_config>
<apb_slave_no>65</apb_slave_no>
@@ -891,7 +1144,6 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
- <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>64</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1000,8 +1252,8 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>890</x>
- <y>296</y>
+ <x>0</x>
+ <y>20</y>
<master_if_port_name>ROM_m</master_if_port_name>
<slave_if_port_name>ROM_s</slave_if_port_name>
</amib>
@@ -1013,7 +1265,6 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id def="true">false</compress_id>
<dest_type>peripheral</dest_type>
- <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1090,14 +1341,14 @@
<name>w</name>
<type>fifo</type>
</reg>
- <slave_if_data_width>128</slave_if_data_width>
+ <slave_if_data_width>64</slave_if_data_width>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>sec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>890</x>
- <y>176</y>
+ <x>0</x>
+ <y>40</y>
<master_if_port_name>FLASH_m</master_if_port_name>
<slave_if_port_name>FLASH_s</slave_if_port_name>
</amib>
@@ -1109,7 +1360,6 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
- <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>64</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1218,8 +1468,8 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>890</x>
- <y>388</y>
+ <x>0</x>
+ <y>60</y>
<master_if_port_name>RAM_m</master_if_port_name>
<slave_if_port_name>RAM_s</slave_if_port_name>
</amib>
@@ -1231,7 +1481,6 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
- <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>64</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1340,8 +1589,8 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>890</x>
- <y>342</y>
+ <x>0</x>
+ <y>80</y>
<master_if_port_name>DRAM_m</master_if_port_name>
<slave_if_port_name>DRAM_s</slave_if_port_name>
</amib>
@@ -1353,7 +1602,6 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
- <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1380,16 +1628,10 @@
<type>rev</type>
</reg>
<reg>
- <impl>present</impl>
+ <impl def="true">absent</impl>
<location>slave_port</location>
<name>aw</name>
- <type>rev</type>
- </reg>
- <reg>
- <impl>present</impl>
- <location>slave_port</location>
- <name>ar</name>
- <type>rev</type>
+ <type def="true">full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -1404,6 +1646,12 @@
<name>aw</name>
<type def="true">full</type>
</reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
<reg>
<depth def="true">2</depth>
<impl def="true">absent</impl>
@@ -1456,14 +1704,14 @@
<name>b</name>
<type>fifo</type>
</reg>
- <slave_if_data_width>128</slave_if_data_width>
+ <slave_if_data_width>32</slave_if_data_width>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>sec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>890</x>
- <y>222</y>
+ <x>0</x>
+ <y>100</y>
<master_if_port_name>GIC_m</master_if_port_name>
<slave_if_port_name>GIC_s</slave_if_port_name>
</amib>
@@ -1473,29 +1721,29 @@
<clock_domain>clk0</clock_domain>
<name>PERIPHERAL</name>
<trustzone>nsec</trustzone>
- <x>902</x>
- <y>61</y>
+ <x>0</x>
+ <y>0</y>
</apb_port>
<apb_port>
<clock_domain>clk0</clock_domain>
<name>FLASH_CTRL</name>
<trustzone>nsec</trustzone>
- <x>902</x>
- <y>81</y>
+ <x>0</x>
+ <y>0</y>
</apb_port>
<apb_port>
<clock_domain>clk0</clock_domain>
<name>DEBUG</name>
<trustzone>nsec</trustzone>
- <x>902</x>
- <y>101</y>
+ <x>0</x>
+ <y>0</y>
</apb_port>
<apb_port>
<clock_domain>clk0</clock_domain>
<name>DMA_CTRL</name>
<trustzone>nsec</trustzone>
- <x>902</x>
- <y>121</y>
+ <x>0</x>
+ <y>0</y>
</apb_port>
<apb_slave_no>60</apb_slave_no>
<clock_boundary>none</clock_boundary>
@@ -1503,7 +1751,6 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id def="true">false</compress_id>
<dest_type>peripheral</dest_type>
- <expanded>true</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1580,50 +1827,79 @@
<name>w</name>
<type>fifo</type>
</reg>
- <slave_if_data_width>128</slave_if_data_width>
+ <slave_if_data_width>64</slave_if_data_width>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
<vn_external def="true">none</vn_external>
<vn_external_bridge def="true">none</vn_external_bridge>
- <x>890</x>
- <y>61</y>
+ <x>0</x>
+ <y>120</y>
<master_if_port_name>PERIPHERAL,FLASH_CTRL,DEBUG,DMA_CTRL</master_if_port_name>
<slave_if_port_name>apb_group0_s</slave_if_port_name>
</amib>
<inter>
<clock_domain>clk0</clock_domain>
<data_width>64</data_width>
- <expanded>true</expanded>
- <height>127</height>
+ <expanded>false</expanded>
+ <height>120</height>
<impl>mlayer</impl>
<master_if>
<name>axi_m_0</name>
<post_arb_reg>absent</post_arb_reg>
- <x>673</x>
- <y>296</y>
+ <x>0</x>
+ <y>63</y>
</master_if>
<master_if>
<name>axi_m_1</name>
<post_arb_reg>absent</post_arb_reg>
- <x>673</x>
- <y>342</y>
+ <x>0</x>
+ <y>83</y>
</master_if>
<master_if>
<name>axi_m_2</name>
<post_arb_reg>absent</post_arb_reg>
- <x>673</x>
- <y>388</y>
+ <x>0</x>
+ <y>103</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_3</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>123</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_4</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>143</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_5</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>163</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_6</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>183</y>
</master_if>
<name>bm0</name>
<protocol>axi4</protocol>
<slave_if>
<name>axi_s_0</name>
- <x>580</x>
- <y>296</y>
+ <x>0</x>
+ <y>63</y>
+ </slave_if>
+ <slave_if>
+ <name>axi_s_1</name>
+ <x>0</x>
+ <y>83</y>
</slave_if>
<sparse>
- <cds>slaveperid</cds>
+ <cds>singleslave</cds>
<sas def="true">false</sas>
<slave_if_port>axi_s_0</slave_if_port>
<master_if_port>
@@ -1710,68 +1986,8 @@
<type def="true">full</type>
</reg>
</master_if_port>
- </sparse>
- <type>busmatrix</type>
- <width>94</width>
- <x>626</x>
- <y>342</y>
- <master_if_port_name>axi_m_0,axi_m_1,axi_m_2</master_if_port_name>
- <slave_if_port_name>axi_s_0</slave_if_port_name>
- </inter>
- <inter>
- <clock_domain>clk0</clock_domain>
- <data_width>128</data_width>
- <expanded>true</expanded>
- <height>242</height>
- <impl>mlayer</impl>
- <master_if>
- <name>axi_m_0</name>
- <post_arb_reg>absent</post_arb_reg>
- <x>420</x>
- <y>176</y>
- </master_if>
- <master_if>
- <name>axi_m_1</name>
- <post_arb_reg>absent</post_arb_reg>
- <x>420</x>
- <y>61</y>
- </master_if>
- <master_if>
- <name>axi_m_2</name>
- <post_arb_reg>absent</post_arb_reg>
- <x>420</x>
- <y>222</y>
- </master_if>
- <master_if>
- <name>axi_m_3</name>
- <post_arb_reg>absent</post_arb_reg>
- <x>420</x>
- <y>268</y>
- </master_if>
- <master_if>
- <name>axi_m_4</name>
- <post_arb_reg>absent</post_arb_reg>
- <x>420</x>
- <y>91</y>
- </master_if>
- <name>bm1</name>
- <protocol>axi4</protocol>
- <slave_if>
- <name>axi_s_0</name>
- <x>327</x>
- <y>61</y>
- </slave_if>
- <slave_if>
- <name>axi_s_1</name>
- <x>327</x>
- <y>91</y>
- </slave_if>
- <sparse>
- <cds>slaveperid</cds>
- <sas def="true">false</sas>
- <slave_if_port>axi_s_0</slave_if_port>
<master_if_port>
- <name>axi_m_0</name>
+ <name>axi_m_3</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -1799,7 +2015,7 @@
</reg>
</master_if_port>
<master_if_port>
- <name>axi_m_1</name>
+ <name>axi_m_4</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -1827,7 +2043,7 @@
</reg>
</master_if_port>
<master_if_port>
- <name>axi_m_3</name>
+ <name>axi_m_5</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -1855,7 +2071,7 @@
</reg>
</master_if_port>
<master_if_port>
- <name>axi_m_4</name>
+ <name>axi_m_6</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -1944,7 +2160,7 @@
</reg>
</master_if_port>
<master_if_port>
- <name>axi_m_2</name>
+ <name>axi_m_3</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -1972,7 +2188,7 @@
</reg>
</master_if_port>
<master_if_port>
- <name>axi_m_3</name>
+ <name>axi_m_4</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -2000,7 +2216,7 @@
</reg>
</master_if_port>
<master_if_port>
- <name>axi_m_4</name>
+ <name>axi_m_5</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -2029,197 +2245,766 @@
</master_if_port>
</sparse>
<type>busmatrix</type>
- <width>94</width>
- <x>373</x>
- <y>164</y>
- <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3,axi_m_4</master_if_port_name>
+ <width>0</width>
+ <x>500</x>
+ <y>45</y>
+ <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3,axi_m_4,axi_m_5,axi_m_6</master_if_port_name>
<slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
</inter>
<inter>
- <apb_config def="true">false</apb_config>
- <apb_slave_no def="true">2</apb_slave_no>
- <clock_boundary>none</clock_boundary>
- <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
- <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <clock_domain>clk0</clock_domain>
+ <data_width>32</data_width>
+ <expanded>false</expanded>
+ <height>20</height>
+ <impl>mlayer</impl>
<master_if>
- <name>ib2_m</name>
- <x>515</x>
- <y>282</y>
+ <name>axi_m_0</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>108</y>
</master_if>
- <master_if_data_width>64</master_if_data_width>
- <name>ib2</name>
- <qos_config>
- <hard>disable</hard>
- <lqv>disable</lqv>
- <pot>disable</pot>
- </qos_config>
- <reg>
- <impl>present</impl>
- <location>slave_port</location>
- <name>aw</name>
- <type>rev</type>
- </reg>
- <reg>
- <impl>present</impl>
- <location>slave_port</location>
- <name>ar</name>
- <type>rev</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>aw</name>
- <type>fifo</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
- <name>aw</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>ar</name>
- <type>fifo</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
- <name>ar</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>slave_port</location>
- <name>r</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>r</name>
- <type>fifo</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
- <name>r</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>slave_port</location>
- <name>w</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>w</name>
- <type>fifo</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
- <name>w</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>slave_port</location>
- <name>b</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>b</name>
- <type>fifo</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
- <name>b</name>
- <type def="true">full</type>
- </reg>
+ <name>bm1</name>
+ <protocol>axi4</protocol>
<slave_if>
- <name>ib2_s</name>
- <x>486</x>
- <y>282</y>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>108</y>
</slave_if>
- <slave_if_data_width>128</slave_if_data_width>
- <type>ib</type>
- <x>500</x>
- <y>282</y>
- <master_if_port_name>ib2_m</master_if_port_name>
- <slave_if_port_name>ib2_s</slave_if_port_name>
- </inter>
- <inter>
- <name>ds_3</name>
<slave_if>
- <name>axi_s_0</name>
- <x>436</x>
- <y>101</y>
+ <name>axi_s_1</name>
+ <x>0</x>
+ <y>128</y>
</slave_if>
- <type>default_slave</type>
- <x>450</x>
- <y>101</y>
- <master_if_port_name></master_if_port_name>
- <slave_if_port_name>axi_s_0</slave_if_port_name>
- </inter>
- <connect>
- <aruser>false</aruser>
- <awuser>false</awuser>
- <buser>false</buser>
- <dest>A53</dest>
- <dest_port>A53_s</dest_port>
- <lock>false</lock>
- <out_reads>32</out_reads>
- <out_trans>64</out_trans>
- <out_writes>32</out_writes>
- <protocol>axi4</protocol>
- <ruser>false</ruser>
- <src>external</src>
- <src_port>A53</src_port>
- <wuser>false</wuser>
- </connect>
- <connect>
- <aruser>false</aruser>
- <awuser>false</awuser>
- <buser>false</buser>
- <dest>DMA350</dest>
- <dest_port>DMA350_s</dest_port>
- <lock>false</lock>
- <out_reads>32</out_reads>
- <out_trans>64</out_trans>
- <out_writes>32</out_writes>
- <protocol>axi4</protocol>
- <ruser>false</ruser>
- <src>external</src>
- <src_port>DMA350</src_port>
- <wuser>false</wuser>
- </connect>
- <connect>
- <aruser>false</aruser>
- <awuser>false</awuser>
- <buser>false</buser>
- <dest>external</dest>
- <dest_port>ROM</dest_port>
- <lock>false</lock>
- <out_reads>1</out_reads>
- <out_trans>1</out_trans>
- <out_writes>1</out_writes>
- <protocol>axi4</protocol>
- <ruser>false</ruser>
- <src>ROM</src>
- <src_port>ROM_m</src_port>
- <wuser>false</wuser>
+ <sparse>
+ <cds>slaveperid</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_0</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <sparse>
+ <cds>slaveperid</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_1</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <type>busmatrix</type>
+ <width>0</width>
+ <x>500</x>
+ <y>90</y>
+ <master_if_port_name>axi_m_0</master_if_port_name>
+ <slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
+ </inter>
+ <inter>
+ <clock_domain>clk0</clock_domain>
+ <data_width>128</data_width>
+ <expanded>false</expanded>
+ <height>40</height>
+ <impl>mlayer</impl>
+ <master_if>
+ <name>axi_m_0</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>153</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_1</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>173</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_2</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>193</y>
+ </master_if>
+ <name>bm2</name>
+ <protocol>axi4</protocol>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>153</y>
+ </slave_if>
+ <slave_if>
+ <name>axi_s_1</name>
+ <x>0</x>
+ <y>173</y>
+ </slave_if>
+ <sparse>
+ <cds>slaveperid</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_0</slave_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_2</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <sparse>
+ <cds>slaveperid</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_1</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_2</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <type>busmatrix</type>
+ <width>0</width>
+ <x>500</x>
+ <y>135</y>
+ <master_if_port_name>axi_m_0,axi_m_1,axi_m_2</master_if_port_name>
+ <slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
+ </inter>
+ <inter>
+ <apb_config def="true">false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if>
+ <name>ib3_m</name>
+ <x>0</x>
+ <y>0</y>
+ </master_if>
+ <master_if_data_width>32</master_if_data_width>
+ <name>ib3</name>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if>
+ <name>ib3_s</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <slave_if_data_width>64</slave_if_data_width>
+ <type>ib</type>
+ <x>0</x>
+ <y>0</y>
+ <master_if_port_name>ib3_m</master_if_port_name>
+ <slave_if_port_name>ib3_s</slave_if_port_name>
+ </inter>
+ <inter>
+ <apb_config def="true">false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if>
+ <name>ib4_m</name>
+ <x>0</x>
+ <y>0</y>
+ </master_if>
+ <master_if_data_width>32</master_if_data_width>
+ <name>ib4</name>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if>
+ <name>ib4_s</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <slave_if_data_width>128</slave_if_data_width>
+ <type>ib</type>
+ <x>0</x>
+ <y>0</y>
+ <master_if_port_name>ib4_m</master_if_port_name>
+ <slave_if_port_name>ib4_s</slave_if_port_name>
+ </inter>
+ <inter>
+ <apb_config def="true">false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if>
+ <name>ib5_m</name>
+ <x>0</x>
+ <y>0</y>
+ </master_if>
+ <master_if_data_width>64</master_if_data_width>
+ <name>ib5</name>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if>
+ <name>ib5_s</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <slave_if_data_width>128</slave_if_data_width>
+ <type>ib</type>
+ <x>0</x>
+ <y>0</y>
+ <master_if_port_name>ib5_m</master_if_port_name>
+ <slave_if_port_name>ib5_s</slave_if_port_name>
+ </inter>
+ <inter>
+ <name>ds_6</name>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <type>default_slave</type>
+ <x>500</x>
+ <y>500</y>
+ <master_if_port_name />
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <inter>
+ <name>ds_7</name>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <type>default_slave</type>
+ <x>500</x>
+ <y>500</y>
+ <master_if_port_name />
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>A53</dest>
+ <dest_port>A53_s</dest_port>
+ <lock>false</lock>
+ <out_reads>32</out_reads>
+ <out_trans>64</out_trans>
+ <out_writes>32</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>A53</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>DMA350</dest>
+ <dest_port>DMA350_s</dest_port>
+ <lock>false</lock>
+ <out_reads>32</out_reads>
+ <out_trans>64</out_trans>
+ <out_writes>32</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>DMA350</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>ADP</dest>
+ <dest_port>ADP_s</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>5</out_trans>
+ <out_writes>4</out_writes>
+ <protocol>ahb_mm</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>ADP</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>ROM</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>ROM</src>
+ <src_port>ROM_m</src_port>
+ <wuser>false</wuser>
</connect>
<connect>
<aruser>false</aruser>
@@ -2349,6 +3134,17 @@
<src_port>DMA_CTRL</src_port>
<wuser>false</wuser>
</connect>
+ <connect>
+ <dest>FLASH</dest>
+ <dest_port>FLASH_s</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">2</out_reads>
+ <out_trans def="true">4</out_trans>
+ <out_writes def="true">2</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
<connect>
<dest>ROM</dest>
<dest_port>ROM_s</dest_port>
@@ -2358,7 +3154,18 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_0</src_port>
+ <src_port>axi_m_1</src_port>
+ </connect>
+ <connect>
+ <dest>apb_group0</dest>
+ <dest_port>apb_group0_s</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">2</out_reads>
+ <out_trans def="true">2</out_trans>
+ <out_writes def="true">2</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_3</src_port>
</connect>
<connect>
<dest>DRAM</dest>
@@ -2369,7 +3176,7 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_1</src_port>
+ <src_port>axi_m_4</src_port>
</connect>
<connect>
<dest>RAM</dest>
@@ -2380,10 +3187,21 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_2</src_port>
+ <src_port>axi_m_5</src_port>
</connect>
<connect>
- <dest>bm1</dest>
+ <dest>GIC</dest>
+ <dest_port>GIC_s</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm1</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
+ <connect>
+ <dest>bm2</dest>
<dest_port>axi_s_0</dest_port>
<lock>false</lock>
<out_reads def="true">32</out_reads>
@@ -2394,7 +3212,7 @@
<src_port>DMA350_m</src_port>
</connect>
<connect>
- <dest>bm1</dest>
+ <dest>bm2</dest>
<dest_port>axi_s_1</dest_port>
<lock>false</lock>
<out_reads def="true">32</out_reads>
@@ -2405,81 +3223,114 @@
<src_port>A53_m</src_port>
</connect>
<connect>
- <dest>FLASH</dest>
- <dest_port>FLASH_s</dest_port>
+ <dest>bm0</dest>
+ <dest_port>axi_s_0</dest_port>
<lock>false</lock>
- <out_reads def="true">2</out_reads>
- <out_trans def="true">4</out_trans>
+ <out_reads def="true">1</out_reads>
+ <out_trans>3</out_trans>
<out_writes def="true">2</out_writes>
<protocol>axi4</protocol>
- <src>bm1</src>
- <src_port>axi_m_0</src_port>
+ <src>ADP</src>
+ <src_port>ADP_m</src_port>
</connect>
<connect>
- <dest>apb_group0</dest>
- <dest_port>apb_group0_s</dest_port>
+ <dest>ib3</dest>
+ <dest_port>ib3_s</dest_port>
<lock>false</lock>
- <out_reads def="true">2</out_reads>
- <out_trans def="true">2</out_trans>
- <out_writes def="true">2</out_writes>
+ <out_reads def="true">1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes def="true">1</out_writes>
<protocol>axi4</protocol>
- <src>bm1</src>
- <src_port>axi_m_1</src_port>
+ <src>bm0</src>
+ <src_port>axi_m_2</src_port>
</connect>
<connect>
- <dest>GIC</dest>
- <dest_port>GIC_s</dest_port>
+ <dest>bm1</dest>
+ <dest_port>axi_s_0</dest_port>
<lock>false</lock>
<out_reads def="true">1</out_reads>
- <out_trans def="true">1</out_trans>
+ <out_trans>2</out_trans>
<out_writes def="true">1</out_writes>
<protocol>axi4</protocol>
- <src>bm1</src>
- <src_port>axi_m_2</src_port>
+ <src>ib3</src>
+ <src_port>ib3_m</src_port>
</connect>
<connect>
- <dest>ib2</dest>
- <dest_port>ib2_s</dest_port>
+ <dest>ib4</dest>
+ <dest_port>ib4_s</dest_port>
<lock>false</lock>
- <out_reads def="true">3</out_reads>
- <out_trans>6</out_trans>
- <out_writes def="true">3</out_writes>
+ <out_reads def="true">1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes def="true">1</out_writes>
<protocol>axi4</protocol>
- <src>bm1</src>
- <src_port>axi_m_3</src_port>
+ <src>bm2</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
+ <connect>
+ <dest>bm1</dest>
+ <dest_port>axi_s_1</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes def="true">1</out_writes>
+ <protocol>axi4</protocol>
+ <src>ib4</src>
+ <src_port>ib4_m</src_port>
+ </connect>
+ <connect>
+ <dest>ib5</dest>
+ <dest_port>ib5_s</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">7</out_reads>
+ <out_trans>14</out_trans>
+ <out_writes def="true">7</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm2</src>
+ <src_port>axi_m_1</src_port>
</connect>
<connect>
<dest>bm0</dest>
+ <dest_port>axi_s_1</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">7</out_reads>
+ <out_trans>14</out_trans>
+ <out_writes def="true">7</out_writes>
+ <protocol>axi4</protocol>
+ <src>ib5</src>
+ <src_port>ib5_m</src_port>
+ </connect>
+ <connect>
+ <dest>ds_6</dest>
<dest_port>axi_s_0</dest_port>
<lock>false</lock>
- <out_reads def="true">3</out_reads>
- <out_trans>6</out_trans>
- <out_writes def="true">3</out_writes>
+ <out_reads>1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes>1</out_writes>
<protocol>axi4</protocol>
- <src>ib2</src>
- <src_port>ib2_m</src_port>
+ <src>bm0</src>
+ <src_port>axi_m_6</src_port>
</connect>
<connect>
- <dest>ds_3</dest>
+ <dest>ds_7</dest>
<dest_port>axi_s_0</dest_port>
<lock>false</lock>
<out_reads>1</out_reads>
<out_trans>2</out_trans>
<out_writes>1</out_writes>
<protocol>axi4</protocol>
- <src>bm1</src>
- <src_port>axi_m_4</src_port>
+ <src>bm2</src>
+ <src_port>axi_m_2</src_port>
</connect>
<architecture>
<link>
<slave_if>
<name>A53</name>
- <master_if>RAM</master_if>
+ <master_if>DRAM</master_if>
<master_if>ROM</master_if>
<master_if>PERIPHERAL<parent>apb_group0</parent>
</master_if>
<master_if>FLASH</master_if>
- <master_if>DRAM</master_if>
+ <master_if>RAM</master_if>
<master_if>GIC</master_if>
<master_if>apb_group0</master_if>
<master_if>FLASH_CTRL<parent>apb_group0</parent>
@@ -2493,15 +3344,34 @@
<link>
<slave_if>
<name>DMA350</name>
- <master_if>RAM</master_if>
+ <master_if>DRAM</master_if>
<master_if>ROM</master_if>
<master_if>PERIPHERAL<parent>apb_group0</parent>
</master_if>
<master_if>FLASH</master_if>
+ <master_if>RAM</master_if>
+ <master_if>apb_group0</master_if>
+ <master_if>DEBUG<parent>apb_group0</parent>
+ </master_if>
+ </slave_if>
+ </link>
+ <link>
+ <slave_if>
+ <name>ADP</name>
<master_if>DRAM</master_if>
+ <master_if>ROM</master_if>
+ <master_if>PERIPHERAL<parent>apb_group0</parent>
+ </master_if>
+ <master_if>FLASH</master_if>
+ <master_if>RAM</master_if>
+ <master_if>GIC</master_if>
<master_if>apb_group0</master_if>
+ <master_if>FLASH_CTRL<parent>apb_group0</parent>
+ </master_if>
<master_if>DEBUG<parent>apb_group0</parent>
</master_if>
+ <master_if>DMA_CTRL<parent>apb_group0</parent>
+ </master_if>
</slave_if>
</link>
</architecture>
diff --git a/socrates/nic400_megasoc_system/nic400_megasoc_system.xml b/socrates/nic400_megasoc_system/nic400_megasoc_system.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c4dbdc7b2b50782792e104985fae56520f06f93b
--- /dev/null
+++ b/socrates/nic400_megasoc_system/nic400_megasoc_system.xml
@@ -0,0 +1,611 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ConfiguredComponent>
+ <Name>nic400_megasoc_system</Name>
+ <Suffix>megasoc_system</Suffix>
+ <ConfigurableComponentRef>
+ <Vendor>arm.com</Vendor>
+ <Library>CoreLink</Library>
+ <Name>nic400</Name>
+ <Version>r1p2</Version>
+ </ConfigurableComponentRef>
+ <Specification>
+ <Parameters>
+ <AWUSERWidth>0</AWUSERWidth>
+ <ARUSERWidth>0</ARUSERWidth>
+ <WUSERWidth>0</WUSERWidth>
+ <BUSERWidth>0</BUSERWidth>
+ <RUSERWidth>0</RUSERWidth>
+ <GlobalIDWidth>2</GlobalIDWidth>
+ <HierarchicalClockGating>false</HierarchicalClockGating>
+ <ClockControllerImplementation>asynchronous</ClockControllerImplementation>
+ <RSBCentralRing>false</RSBCentralRing>
+ <DefaultProtocol>axi4</DefaultProtocol>
+ <UppercaseRTLSignals>true</UppercaseRTLSignals>
+ <Taxonomy>master_slave</Taxonomy>
+ <QoSEnabled>false</QoSEnabled>
+ <QVNEnabled>false</QVNEnabled>
+ </Parameters>
+ <Domains>
+ <VoltageDomains>
+ <VoltageDomain>
+ <Name>vd0</Name>
+ </VoltageDomain>
+ </VoltageDomains>
+ <PowerDomains>
+ <PowerDomain>
+ <Name>pd0</Name>
+ <PowerDomainType>AlwaysOn</PowerDomainType>
+ <VoltageDomainRef>vd0</VoltageDomainRef>
+ </PowerDomain>
+ </PowerDomains>
+ <ClockDomains>
+ <ClockDomain>
+ <Name>clk0</Name>
+ <ClockDomainType>physical</ClockDomainType>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ </ClockDomains>
+ <ClockRelations/>
+ </Domains>
+ <Groups>
+ <ExternalGroups/>
+ <APBGroups/>
+ </Groups>
+ <Interfaces>
+ <SlaveInterface>
+ <Name>DMA</Name>
+ <AXI4SlaveProtocol>
+ <AddressWidth>44</AddressWidth>
+ <DataWidth>128</DataWidth>
+ <VIDWidth>2</VIDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneSlave>secure</TrustZoneSlave>
+ <ReadAcceptance>4</ReadAcceptance>
+ <WriteAcceptance>4</WriteAcceptance>
+ <QoSTypeAXI>fixed</QoSTypeAXI>
+ <QoSValue>0</QoSValue>
+ <TransactionRateRegulation>false</TransactionRateRegulation>
+ <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
+ <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
+ <VNExternal>false</VNExternal>
+ </AXI4SlaveProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ <MultiPorted>false</MultiPorted>
+ <CyclicDependencyAvoidanceScheme>slave_per_id</CyclicDependencyAvoidanceScheme>
+ <LowLatency>false</LowLatency>
+ </SlaveInterface>
+ <MasterInterface>
+ <Name>SYS_SRAM</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>64</DataWidth>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>secure</TrustZoneMaster>
+ <ReadIssuing>1</ReadIssuing>
+ <WriteIssuing>1</WriteIssuing>
+ <TotalIssuing>1</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>true</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
+ </Interfaces>
+ <MemoryMaps>
+ <MemoryMap>
+ <Name>mm0</Name>
+ <MemoryMapSource>
+ <InterfaceRef>DMA</InterfaceRef>
+ </MemoryMapSource>
+ <MappedBlock>
+ <InterfaceRef>SYS_SRAM</InterfaceRef>
+ <Offset>8796093022208</Offset>
+ <Range>65536</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ </MemoryMap>
+ </MemoryMaps>
+ <Paths>
+ <Path>
+ <Source>
+ <InterfaceRef>DMA</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>SYS_SRAM</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ </Paths>
+ <VirtualNetworks/>
+ </Specification>
+ <Architecture>
+ <NICConfigFile><periph>
+ <product_version_info major_group="bu" major_revision="1" major_version="00" minor_code="50000" minor_revision="2" minor_version="0" part_quality="rel" product_code="nic400" />
+ <validator_version_info major_revision="22" minor_revision="1" />
+ <global>
+ <address0x0 def="true">bottom</address0x0>
+ <aruser_width>0</aruser_width>
+ <awuser_width>0</awuser_width>
+ <buser_width>0</buser_width>
+ <cc_type>async</cc_type>
+ <default_protocol>axi4</default_protocol>
+ <dpe_glb_enable def="true">false</dpe_glb_enable>
+ <dpe_status>false</dpe_status>
+ <dpe_width def="true">5</dpe_width>
+ <gen_caps>true</gen_caps>
+ <hcg_en>false</hcg_en>
+ <license_status>unlicensed_nic</license_status>
+ <periph_id3 def="true">0</periph_id3>
+ <pl_id_width>2</pl_id_width>
+ <qos_status>false</qos_status>
+ <rsb_arch_central_ring>false</rsb_arch_central_ring>
+ <ruser_width>0</ruser_width>
+ <sas_visible def="true">false</sas_visible>
+ <start_iid>0</start_iid>
+ <taxonomy>masterslave</taxonomy>
+ <thin_links_status def="true">false</thin_links_status>
+ <uppercase_ext_sig>true</uppercase_ext_sig>
+ <virtual_networks />
+ <virtual_networks_status>false</virtual_networks_status>
+ <wuser_width>0</wuser_width>
+ </global>
+ <clocks>
+ <domain freq="100">clk0</domain>
+ </clocks>
+ <asib>
+ <address_ranges>
+ <name>mm0</name>
+ <range>
+ <addr_max>0x8000000FFFF</addr_max>
+ <addr_min>0x80000000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>SYS_SRAM</target>
+ </remap>
+ </range>
+ </address_ranges>
+ <apb_config>false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <cds>slaveperid</cds>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if_data_width>64</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>DMA</name>
+ <protocol>axi4</protocol>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <qv>
+ <type>fixed</type>
+ <value>0</value>
+ </qv>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if_addr_width>44</slave_if_addr_width>
+ <slave_if_data_width>128</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>sec</trustzone>
+ <vid_width>2</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>20</y>
+ <master_if_port_name>DMA_m</master_if_port_name>
+ <slave_if_port_name>DMA_s</slave_if_port_name>
+ </asib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>65</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id>true</compress_id>
+ <dest_type>peripheral</dest_type>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>64</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>SYS_SRAM</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>64</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>sec</trustzone>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>20</y>
+ <master_if_port_name>SYS_SRAM_m</master_if_port_name>
+ <slave_if_port_name>SYS_SRAM_s</slave_if_port_name>
+ </amib>
+ <inter>
+ <clock_domain>clk0</clock_domain>
+ <data_width>64</data_width>
+ <expanded>false</expanded>
+ <height>20</height>
+ <impl>mlayer</impl>
+ <master_if>
+ <name>axi_m_0</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>63</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_1</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>83</y>
+ </master_if>
+ <name>bm0</name>
+ <protocol>axi4</protocol>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>63</y>
+ </slave_if>
+ <sparse>
+ <cds>slaveperid</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_0</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <type>busmatrix</type>
+ <width>0</width>
+ <x>500</x>
+ <y>45</y>
+ <master_if_port_name>axi_m_0,axi_m_1</master_if_port_name>
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <inter>
+ <name>ds_1</name>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <type>default_slave</type>
+ <x>500</x>
+ <y>500</y>
+ <master_if_port_name />
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>DMA</dest>
+ <dest_port>DMA_s</dest_port>
+ <lock>false</lock>
+ <out_reads>4</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>4</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>DMA</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>SYS_SRAM</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>SYS_SRAM</src>
+ <src_port>SYS_SRAM_m</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <dest>SYS_SRAM</dest>
+ <dest_port>SYS_SRAM_s</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
+ <connect>
+ <dest>bm0</dest>
+ <dest_port>axi_s_0</dest_port>
+ <lock>false</lock>
+ <out_reads>4</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>4</out_writes>
+ <protocol>axi4</protocol>
+ <src>DMA</src>
+ <src_port>DMA_m</src_port>
+ </connect>
+ <connect>
+ <dest>ds_1</dest>
+ <dest_port>axi_s_0</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_1</src_port>
+ </connect>
+ <architecture>
+ <link>
+ <slave_if>
+ <name>DMA</name>
+ <master_if>SYS_SRAM</master_if>
+ </slave_if>
+ </link>
+ </architecture>
+</periph>
+</NICConfigFile>
+ </Architecture>
+ <Deliverables>
+ <IPXACT/>
+ <RTL/>
+ <TestBench/>
+ <Reports/>
+ </Deliverables>
+</ConfiguredComponent>
\ No newline at end of file
diff --git a/socrates/nic400_tlx_megasoc/nic400_tlx_megasoc.xml b/socrates/nic400_tlx_megasoc/nic400_tlx_megasoc.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6bf2489eb092fd3205e522c36d00857c560a43fd
--- /dev/null
+++ b/socrates/nic400_tlx_megasoc/nic400_tlx_megasoc.xml
@@ -0,0 +1,420 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ConfiguredComponent>
+ <Name>nic400_tlx_megasoc</Name>
+ <Suffix>megasoc</Suffix>
+ <ConfigurableComponentRef>
+ <Vendor>arm.com</Vendor>
+ <Library>CoreLink</Library>
+ <Name>nic400_tlx</Name>
+ <Version>r1p2</Version>
+ </ConfigurableComponentRef>
+ <Specification>
+ <Parameters>
+ <ARUSERWidth>0</ARUSERWidth>
+ <AWUSERWidth>0</AWUSERWidth>
+ <RUSERWidth>0</RUSERWidth>
+ <WUSERWidth>0</WUSERWidth>
+ <BUSERWidth>0</BUSERWidth>
+ <IDWidth>12</IDWidth>
+ <AddressWidth>32</AddressWidth>
+ <SlaveDataWidth>32</SlaveDataWidth>
+ <MasterDataWidth>32</MasterDataWidth>
+ <SlaveReadAcceptance>16</SlaveReadAcceptance>
+ <SlaveWriteAcceptance>16</SlaveWriteAcceptance>
+ <MasterReadIssuing>16</MasterReadIssuing>
+ <MasterWriteIssuing>16</MasterWriteIssuing>
+ <MasterTotalIssuing>16</MasterTotalIssuing>
+ <MultiRegion>false</MultiRegion>
+ <LockSupport>false</LockSupport>
+ <SLAVE_PROTOCOL>AXI4</SLAVE_PROTOCOL>
+ <MASTER_PROTOCOL>AXI4</MASTER_PROTOCOL>
+ <EarlyWriteResponse>true</EarlyWriteResponse>
+ <AllowBrokenBurst>false</AllowBrokenBurst>
+ <SLAVE_CLOCK>clk_s</SLAVE_CLOCK>
+ <MASTER_CLOCK>clk_m</MASTER_CLOCK>
+ <FW_USER_DEFINED_WIDTH>16</FW_USER_DEFINED_WIDTH>
+ <FW_PACKING_STRATEGY>user_def_bytes</FW_PACKING_STRATEGY>
+ <FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
+ <REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
+ <REV_USER_DEFINED_WIDTH>8</REV_USER_DEFINED_WIDTH>
+ <REV_TLX_TIMING_CLOSURE>false</REV_TLX_TIMING_CLOSURE>
+ <AWSlavePortRegister>present</AWSlavePortRegister>
+ <AWSlavePortRegisterType>rev</AWSlavePortRegisterType>
+ <AWMasterPortRegister>absent</AWMasterPortRegister>
+ <AWMasterPortRegisterType>fwd</AWMasterPortRegisterType>
+ <AWBoundaryBuffering>absent</AWBoundaryBuffering>
+ <AWBoundaryBufferingDepth>2</AWBoundaryBufferingDepth>
+ <AWCreditBuffers>6</AWCreditBuffers>
+ <ARSlavePortRegister>present</ARSlavePortRegister>
+ <ARSlavePortRegisterType>rev</ARSlavePortRegisterType>
+ <ARMasterPortRegister>absent</ARMasterPortRegister>
+ <ARMasterPortRegisterType>fwd</ARMasterPortRegisterType>
+ <ARBoundaryBuffering>absent</ARBoundaryBuffering>
+ <ARBoundaryBufferingDepth>2</ARBoundaryBufferingDepth>
+ <ARCreditBuffers>6</ARCreditBuffers>
+ <WSlavePortRegister>present</WSlavePortRegister>
+ <WSlavePortRegisterType>rev</WSlavePortRegisterType>
+ <WMasterPortRegister>absent</WMasterPortRegister>
+ <WMasterPortRegisterType>fwd</WMasterPortRegisterType>
+ <WBoundaryBuffering>absent</WBoundaryBuffering>
+ <WBoundaryBufferingDepth>2</WBoundaryBufferingDepth>
+ <WCreditBuffers>6</WCreditBuffers>
+ <RSlavePortRegister>absent</RSlavePortRegister>
+ <RSlavePortRegisterType>fwd</RSlavePortRegisterType>
+ <RMasterPortRegister>absent</RMasterPortRegister>
+ <RMasterPortRegisterType>fwd</RMasterPortRegisterType>
+ <RBoundaryBuffering>absent</RBoundaryBuffering>
+ <RBoundaryBufferingDepth>2</RBoundaryBufferingDepth>
+ <RCreditBuffers>6</RCreditBuffers>
+ <BSlavePortRegister>absent</BSlavePortRegister>
+ <BSlavePortRegisterType>fwd</BSlavePortRegisterType>
+ <BMasterPortRegister>absent</BMasterPortRegister>
+ <BMasterPortRegisterType>fwd</BMasterPortRegisterType>
+ <BBoundaryBuffering>absent</BBoundaryBuffering>
+ <BBoundaryBufferingDepth>2</BBoundaryBufferingDepth>
+ <BCreditBuffers>6</BCreditBuffers>
+ <ASlavePortRegister>absent</ASlavePortRegister>
+ <ASlavePortRegisterType>fwd</ASlavePortRegisterType>
+ <AMasterPortRegister>absent</AMasterPortRegister>
+ <AMasterPortRegisterType>fwd</AMasterPortRegisterType>
+ <ABoundaryBuffering>absent</ABoundaryBuffering>
+ <ABoundaryBufferingDepth>2</ABoundaryBufferingDepth>
+ <ACreditBuffers>6</ACreditBuffers>
+ <DSlavePortRegister>absent</DSlavePortRegister>
+ <DSlavePortRegisterType>fwd</DSlavePortRegisterType>
+ <DMasterPortRegister>absent</DMasterPortRegister>
+ <DMasterPortRegisterType>fwd</DMasterPortRegisterType>
+ <DBoundaryBuffering>absent</DBoundaryBuffering>
+ <DBoundaryBufferingDepth>2</DBoundaryBufferingDepth>
+ <DCreditBuffers>6</DCreditBuffers>
+ <FwdChannelPLRegisterSlices>0</FwdChannelPLRegisterSlices>
+ <RevChannelPLRegisterSlices>0</RevChannelPLRegisterSlices>
+ <POWER_DOMAIN_CROSSING>false</POWER_DOMAIN_CROSSING>
+ <HierarchicalClockGating>false</HierarchicalClockGating>
+ <ClockControllerImplementation>asynchronous</ClockControllerImplementation>
+ <QoSEnabled>false</QoSEnabled>
+ <OutputSignals>false</OutputSignals>
+ <QVNEnabled>false</QVNEnabled>
+ <VNExternal>false</VNExternal>
+ <VNExternalBridge>false</VNExternalBridge>
+ <MASTER_PREALLOC_1>false</MASTER_PREALLOC_1>
+ <MASTER_PREALLOC_2>false</MASTER_PREALLOC_2>
+ <MASTER_PREALLOC_3>false</MASTER_PREALLOC_3>
+ <MASTER_PREALLOC_4>false</MASTER_PREALLOC_4>
+ <SLAVE_PREALLOC_1>false</SLAVE_PREALLOC_1>
+ <SLAVE_PREALLOC_2>false</SLAVE_PREALLOC_2>
+ <SLAVE_PREALLOC_3>false</SLAVE_PREALLOC_3>
+ <SLAVE_PREALLOC_4>false</SLAVE_PREALLOC_4>
+ <FW_PHYSICAL_LINK>16</FW_PHYSICAL_LINK>
+ <REV_PHYSICAL_LINK>16</REV_PHYSICAL_LINK>
+ <FW_AXI_SIGNAL>167</FW_AXI_SIGNAL>
+ <REV_AXI_SIGNAL>61</REV_AXI_SIGNAL>
+ <FW_BANDWIDTH_PERCENTAGE>19</FW_BANDWIDTH_PERCENTAGE>
+ <FW_UTILIZATION_PERCENTAGE>79</FW_UTILIZATION_PERCENTAGE>
+ <FW_REDUCTION_PERCENTAGE>90</FW_REDUCTION_PERCENTAGE>
+ <REV_BANDWIDTH_PERCENTAGE>23</REV_BANDWIDTH_PERCENTAGE>
+ <REV_UTILIZATION_PERCENTAGE>96</REV_UTILIZATION_PERCENTAGE>
+ <REV_REDUCTION_PERCENTAGE>80</REV_REDUCTION_PERCENTAGE>
+ <DPEEnabled>false</DPEEnabled>
+ <ParityBitWidth>5</ParityBitWidth>
+ </Parameters>
+ <Domains>
+ <VoltageDomains>
+ <VoltageDomain>
+ <Name>vd0</Name>
+ </VoltageDomain>
+ </VoltageDomains>
+ <PowerDomains>
+ <PowerDomain>
+ <Name>pd0</Name>
+ <PowerDomainType>AlwaysOn</PowerDomainType>
+ <VoltageDomainRef>vd0</VoltageDomainRef>
+ </PowerDomain>
+ </PowerDomains>
+ <ClockDomains>
+ <ClockDomain>
+ <Name>clk_s</Name>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ <ClockDomain>
+ <Name>clk_m</Name>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ </ClockDomains>
+ <ClockRelations/>
+ <GeographicDomains>
+ <GeographicDomain>
+ <Name>gd0</Name>
+ </GeographicDomain>
+ <GeographicDomain>
+ <Name>gd1</Name>
+ </GeographicDomain>
+ </GeographicDomains>
+ </Domains>
+ <Groups>
+ <ExternalGroups/>
+ </Groups>
+ <Interfaces>
+ <SlaveInterface>
+ <Name>M1_s</Name>
+ <AXI4SlaveProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <ARUSEREnabled>false</ARUSEREnabled>
+ <AWUSEREnabled>false</AWUSEREnabled>
+ <RUSEREnabled>false</RUSEREnabled>
+ <WUSEREnabled>false</WUSEREnabled>
+ <BUSEREnabled>false</BUSEREnabled>
+ </AXI4SlaveProtocol>
+ <ClockRef>clk_s</ClockRef>
+ </SlaveInterface>
+ <MasterInterface>
+ <Name>M1_m</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <ARUSEREnabled>false</ARUSEREnabled>
+ <AWUSEREnabled>false</AWUSEREnabled>
+ <RUSEREnabled>false</RUSEREnabled>
+ <WUSEREnabled>false</WUSEREnabled>
+ <BUSEREnabled>false</BUSEREnabled>
+ </AXI4MasterProtocol>
+ <ClockRef>clk_m</ClockRef>
+ </MasterInterface>
+ </Interfaces>
+ <MemoryMaps>
+ <MemoryMap>
+ <Name>mm0</Name>
+ <MemoryMapSource>
+ <InterfaceRef>M1_s</InterfaceRef>
+ </MemoryMapSource>
+ <MappedBlock>
+ <InterfaceRef>M1_m</InterfaceRef>
+ <Offset>0</Offset>
+ <Range>4000000000000</Range>
+ </MappedBlock>
+ </MemoryMap>
+ </MemoryMaps>
+ <Paths>
+ <Path>
+ <Source>
+ <InterfaceRef>M1_s</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>M1_m</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ </Paths>
+ <VirtualNetworks/>
+ </Specification>
+ <Architecture>
+ <NICConfigFile><?xml version="1.0" encoding="iso-8859-1" ?>
+<periph>
+<product_version_info major_version="00" minor_revision="2" major_revision="1" minor_version="0" part_quality="rel" minor_code="50000" major_group="bu" product_code="nic400_tlx"/>
+<validator_version_info minor_revision="1" major_revision="22" />
+ <global>
+ <qos_status>false</qos_status>
+ <buser_width>0</buser_width>
+ <hcg_en>false</hcg_en>
+ <virtual_networks_status>false</virtual_networks_status>
+ <rsb_arch_central_ring>false</rsb_arch_central_ring>
+ <thin_links_status>true</thin_links_status>
+ <awuser_width>0</awuser_width>
+ <license_status>unlicensed_nic</license_status>
+ <dpe_status>false</dpe_status>
+ <aruser_width>0</aruser_width>
+ <cc_type>async</cc_type>
+ <pl_id_width>12</pl_id_width>
+ <ruser_width>0</ruser_width>
+ <wuser_width>0</wuser_width>
+ </global>
+ <amib>
+ <master_if_port_name>M1_m_m</master_if_port_name>
+ <multi_region>false</multi_region>
+ <tide>0</tide>
+ <tlx>
+ <power_domain_crossing>false</power_domain_crossing>
+ <fwd_tlx>
+ <pl_clock_ratio>1</pl_clock_ratio>
+ <dll_link_user_def_width>16</dll_link_user_def_width>
+ <pl_reg_stages>0</pl_reg_stages>
+ <dll_link_width_option>user_def_bytes</dll_link_width_option>
+ </fwd_tlx>
+ <rev_tlx>
+ <pl_clock_ratio>1</pl_clock_ratio>
+ <dll_link_user_def_width>8</dll_link_user_def_width>
+ <pl_reg_stages>0</pl_reg_stages>
+ <dll_link_width_option>widest_div_4</dll_link_width_option>
+ </rev_tlx>
+ <tlx_enable>true</tlx_enable>
+ <ahb_bridge>false</ahb_bridge>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>aw</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>w</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>b</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>ar</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>r</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>d</name>
+ <location>tlx_fwd</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>d</name>
+ <location>tlx_rev</location>
+ </reg>
+ </tlx>
+ <slave_if_data_width>32</slave_if_data_width>
+ <multi_ported>false</multi_ported>
+ <vn_external>none</vn_external>
+ <vid_width>12</vid_width>
+ <apb_config>false</apb_config>
+ <qv_out>false</qv_out>
+ <master_if_addr_width>32</master_if_addr_width>
+ <clock_domain_name_slave_if>clk_s</clock_domain_name_slave_if>
+ <clock_domain_name_master_if>clk_m</clock_domain_name_master_if>
+ <protocol>axi4</protocol>
+ <dest_type>peripheral</dest_type>
+ <name>M1_m</name>
+ <vn_external_bridge>none</vn_external_bridge>
+ <trustzone>nsec</trustzone>
+ <slave_if_port_name>M1_m_s</slave_if_port_name>
+ <clock_boundary>async</clock_boundary>
+ <master_if_data_width>32</master_if_data_width>
+ <reg>
+ <type>rev</type>
+ <impl>present</impl>
+ <name>aw</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>rev</type>
+ <impl>present</impl>
+ <name>w</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>rev</type>
+ <impl>present</impl>
+ <name>ar</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>b</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>r</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>aw</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>w</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>ar</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>b</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>r</name>
+ <location>master_port</location>
+ </reg>
+ </amib>
+ <connect>
+ <ruser>false</ruser>
+ <wuser>false</wuser>
+ <src>M1_m</src>
+ <awuser>false</awuser>
+ <out_trans>16</out_trans>
+ <dest>external</dest>
+ <src_port>M1_m_m</src_port>
+ <protocol>axi4</protocol>
+ <buser>false</buser>
+ <out_reads>16</out_reads>
+ <lock>false</lock>
+ <out_writes>16</out_writes>
+ <dest_port>M1_m_m</dest_port>
+ <aruser>false</aruser>
+ </connect>
+ <connect>
+ <ruser>false</ruser>
+ <wuser>false</wuser>
+ <src>external</src>
+ <awuser>false</awuser>
+ <out_trans>32</out_trans>
+ <dest>M1_m</dest>
+ <src_port>M1_m_s</src_port>
+ <protocol>axi4</protocol>
+ <buser>false</buser>
+ <out_reads>16</out_reads>
+ <lock>false</lock>
+ <out_writes>16</out_writes>
+ <dest_port>M1_m_s</dest_port>
+ <aruser>false</aruser>
+ </connect>
+</periph>
+</NICConfigFile>
+ </Architecture>
+ <Deliverables>
+ <IPXACT/>
+ <RTL/>
+ <TestBench/>
+ <Reports/>
+ </Deliverables>
+</ConfiguredComponent>
\ No newline at end of file
diff --git a/software/lib/common/Makefile.c_host b/software/lib/common/Makefile.c_host
index 86c55d15f40d27bab62f1331c760578f61efb67e..2ed547787d409181f188a71d18c1e100cc2805bb 100644
--- a/software/lib/common/Makefile.c_host
+++ b/software/lib/common/Makefile.c_host
@@ -95,12 +95,13 @@ APP_SRC += $(SW_LIB_PATH)/apps/src/irq.s
APP_SRC += $(SW_LIB_PATH)/apps/src/vect_64.s
APP_SRC += $(SW_LIB_PATH)/apps/src/page_table.s
-# APP_SRC += $(SW_LIB_PATH)/devices/src/dma_350_command_lib.c
# APP_SRC += $(SW_LIB_PATH)/devices/src/pl011_uart.c
# APP_SRC += $(SW_LIB_PATH)/devices/src/intr_rtr_1.c
-# APP_SRC += $(SW_LIB_PATH)/devices/src/firewall_1.c
-APP_SRC += $(SW_LIB_PATH)/devices/src/gic400.c
# APP_SRC += $(SW_LIB_PATH)/devices/src/watchdog_generic.c
+
+APP_SRC += $(SW_LIB_PATH)/devices/src/gic400.c
+APP_SRC += $(SW_LIB_PATH)/devices/src/dma_350_command_lib.c
+
APP_SRC += $(SW_LIB_PATH)/host/src/sys_utils.c
APP_SRC += $(SW_LIB_PATH)/devices/src/qspi_flash.c
APP_SRC += $(SW_LIB_PATH)/common/src/system_level_functions.c
@@ -213,7 +214,7 @@ endif
$(BUILD_DIR)/app_ram.v8-a.hex: $(BUILD_DIR)/app.v8-a.elf
@echo -e "\n------------------- Executing make target $(@F) -------------------"
- $(EM) window,0x00800000,0x600000,0x00800000:vmem,64,1 $^ --compact -v 3 --output $@
+ $(EM) window,0x00800000,0x800000,0x00800000:vmem,64,1 $^ --compact -v 3 --output $@
$(BUILD_DIR)/app_flash.v8-a.hex: $(BUILD_DIR)/app.v8-a.elf
@echo -e "\n------------------- Executing make target $(@F) -------------------"
diff --git a/software/lib/sw_lib/devices/include/CMSDK.h b/software/lib/sw_lib/devices/include/CMSDK.h
index 10e6fab6a92f05473c3133fb148bed05181b2685..cd53052b0bb59778793d32424231c0c93f609969 100644
--- a/software/lib/sw_lib/devices/include/CMSDK.h
+++ b/software/lib/sw_lib/devices/include/CMSDK.h
@@ -80,6 +80,7 @@ typedef struct
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) SYS_UART0_BASE )
+#define CMSDK_USRT2 ((CMSDK_UART_TypeDef *) SYS_USRT0_BASE )
/*----------------------------- Timer (TIMER) -------------------------------*/
/** @addtogroup CMSDK_TIMER CMSDK Timer
diff --git a/software/lib/sw_lib/devices/include/dma_350_command_lib.h b/software/lib/sw_lib/devices/include/dma_350_command_lib.h
new file mode 100755
index 0000000000000000000000000000000000000000..3faf649021442b32f9c1c309164b082412b8c941
--- /dev/null
+++ b/software/lib/sw_lib/devices/include/dma_350_command_lib.h
@@ -0,0 +1,530 @@
+/******************************************************************************/
+/* The confidential and proprietary information contained in this file may */
+/* only be used by a person authorised under and to the extent permitted */
+/* by a subsisting licensing agreement from Arm Limited or its affiliates. */
+/* */
+/* (C) COPYRIGHT 2022 Arm Limited or its affiliates. */
+/* ALL RIGHTS RESERVED */
+/* */
+/* This entire notice must be reproduced on all copies of this file */
+/* and copies of this file may only be made by a person if such person is */
+/* permitted to do so under the terms of a subsisting license agreement */
+/* from Arm Limited or its affiliates. */
+/* */
+/* Release Information : DMA350-r0p0-00rel0 */
+/* */
+/******************************************************************************/
+
+#ifndef __DMA_COMMAND_LIB_H
+#define __DMA_COMMAND_LIB_H
+
+#include "dma_350_regdef.h"
+#include "dma_350_reg_typedef.h"
+
+#ifndef ADA_MAX_CH_NUM
+#define ADA_MAX_CH_NUM 8
+#endif
+
+// DMA command related types
+
+ typedef struct {
+ uint32_t SRCMEMATTRLO:4; /*!< bit: 0.. 3 SRCMEMATTRLO[ 3:0] */
+ uint32_t SRCMEMATTRHI:4; /*!< bit: 4.. 7 SRCMEMATTRHI[ 3:0] */
+ uint32_t SRCSHAREATTR:2; /*!< bit: 8.. 9 SRCSHAREATTR[ 1:0] */
+ uint32_t SRCNONSECATTR:1; /*!< bit: 10 SRCNONSECATTR */
+ uint32_t SRCPRIVATTR:1; /*!< bit: 11 SRCPRIVATTR */
+ } AdaChannelSrcAttrType;
+
+ typedef struct {
+ uint32_t DESMEMATTRLO:4; /*!< bit: 0.. 3 DESMEMATTRLO[ 3:0] */
+ uint32_t DESMEMATTRHI:4; /*!< bit: 4.. 7 DESMEMATTRHI[ 3:0] */
+ uint32_t DESSHAREATTR:2; /*!< bit: 8.. 9 DESSHAREATTR[ 1:0] */
+ uint32_t DESNONSECATTR:1; /*!< bit: 10 DESNONSECATTR */
+ uint32_t DESPRIVATTR:1; /*!< bit: 11 DESPRIVATTR */
+ } AdaChannelDesAttrType;
+
+ typedef struct {
+ uint32_t CHPRIO:4; /*!< bit: 4.. 7 CHPRIO[ 3:0] */
+ uint32_t CLEARCMD:1; /*!< bit: 1 CLEARCMD */
+ uint32_t REGRELOADTYPE:3; /*!< bit: 18..20 REGRELOADTYPE[ 2:0] */
+ uint32_t DONETYPE:3; /*!< bit: 21..23 DONETYPE[ 2:0] */
+ uint32_t DONEPAUSEEN:1; /*!< bit: 24 DONEPAUSEEN */
+ uint32_t SRCMAXBURSTLEN:4; /*!< bit: 16..19 SRCMAXBURSTLEN[ 3:0] */
+ uint32_t DESMAXBURSTLEN:4; /*!< bit: 16..19 DESMAXBURSTLEN[ 3:0] */
+ } AdaChannelSettingsType;
+
+ typedef struct {
+ uint64_t SRCADDR:64; /*!< bit: 0..31 SRCADDRHI[31:0] + SRCADDR[31:0] */
+ uint64_t DESADDR:64; /*!< bit: 0..31 DESADDRHI[31:0] + DESADDR[31:0] */
+ uint32_t SRCXSIZE:32; /*!< bit: 0..15 SRCXSIZEHI[15:0] + SRCXSIZE[15:0] */
+ uint32_t DESXSIZE:32; /*!< bit: 16..31 DESXSIZEHI[15:0] + DESXSIZE[15:0] */
+ uint32_t TRANSIZE:3; /*!< bit: 0.. 2 TRANSIZE[ 2:0] */
+ } AdaBaseCommandType;
+
+
+ typedef struct {
+ uint32_t SRCXADDRINC:16; /*!< bit: 1..15 SRCXADDRINC[14:0] + 0 SRCXADDRINCLSB */
+ uint32_t DESXADDRINC:16; /*!< bit: 17..31 DESXADDRINC[14:0] + 16 DESXADDRINCLSB */
+ } Ada1DIncrCommandType;
+
+ typedef struct {
+ uint32_t SRCYSIZE:16; /*!< bit: 0..15 SRCYSIZE[15:0] */
+ uint32_t DESYSIZE:16; /*!< bit: 16..31 DESYSIZE[15:0] */
+ uint32_t SRCYADDRSTRIDE:16; /*!< bit: 0..15 SRCYADDRSTRIDE[15:0] */
+ uint32_t DESYADDRSTRIDE:16; /*!< bit: 16..31 DESYADDRSTRIDE[15:0] */
+ } Ada2DCommandType;
+
+ typedef struct {
+ uint32_t FILLVAL:32; /*!< bit: 0..31 FILLVAL[31:0] */
+ uint32_t XTYPE:3; /*!< bit: 9..11 XTYPE[ 2:0] */
+ uint32_t YTYPE:3; /*!< bit: 12..14 YTYPE[ 2:0] */
+ } AdaWrapCommandType;
+
+ typedef struct {
+ uint32_t SRCTMPLTSIZE:5; /*!< bit: 8..12 SRCTMPLTSIZE[ 4:0] */
+ uint32_t DESTMPLTSIZE:5; /*!< bit: 16..20 DESTMPLTSIZE[ 4:0] */
+ uint32_t SRCTMPLT:32; /*!< bit: 0..31 SRCTMPLT[31:0] */
+ uint32_t DESTMPLT:32; /*!< bit: 0..31 DESTMPLT[31:0] */
+ } AdaTMPLTCommandType;
+
+ typedef struct {
+ uint32_t STAT_DONE:1; /*!< bit: 16 STAT_DONE */
+ uint32_t STAT_ERR:1; /*!< bit: 17 STAT_ERR */
+ uint32_t STAT_DISABLED:1; /*!< bit: 18 STAT_DISABLED */
+ uint32_t STAT_STOPPED:1; /*!< bit: 19 STAT_STOPPED */
+ uint32_t STAT_PAUSED:1; /*!< bit: 20 STAT_PAUSED */
+ uint32_t STAT_RESUMEWAIT:1; /*!< bit: 21 STAT_RESUMEWAIT */
+ } AdaStatType;
+
+ typedef struct {
+ uint32_t STAT_SRCTRIGINWAIT:1; /*!< bit: 24 STAT_SRCTRIGINWAIT */
+ uint32_t STAT_DESTRIGINWAIT:1; /*!< bit: 25 STAT_DESTRIGINWAIT */
+ uint32_t STAT_TRIGOUTACKWAIT:1; /*!< bit: 26 STAT_TRIGOUTACKWAIT */
+ } AdaTrigStatType;
+
+
+ typedef struct {
+ uint32_t INTR_DONE:1; /*!< bit: 0 INTR_DONE */
+ uint32_t INTR_ERR:1; /*!< bit: 1 INTR_ERR */
+ uint32_t INTR_DISABLED:1; /*!< bit: 2 INTR_DISABLED */
+ uint32_t INTR_STOPPED:1; /*!< bit: 3 INTR_STOPPED */
+ uint32_t INTR_SRCTRIGINWAIT:1; /*!< bit: 8 INTR_SRCTRIGINWAIT */
+ uint32_t INTR_DESTRIGINWAIT:1; /*!< bit: 9 INTR_DESTRIGINWAIT */
+ uint32_t INTR_TRIGOUTACKWAIT:1; /*!< bit: 10 INTR_TRIGOUTACKWAIT */
+ } AdaIrqType;
+
+ typedef struct {
+ uint32_t INTREN_DONE:1; /*!< bit: 0 INTREN_DONE */
+ uint32_t INTREN_ERR:1; /*!< bit: 1 INTREN_ERR */
+ uint32_t INTREN_DISABLED:1; /*!< bit: 2 INTREN_DISABLED */
+ uint32_t INTREN_STOPPED:1; /*!< bit: 3 INTREN_STOPPED */
+ } AdaIrqEnType;
+
+ typedef struct {
+ uint32_t INTREN_SRCTRIGINWAIT:1; /*!< bit: 8 INTREN_SRCTRIGINWAIT */
+ uint32_t INTREN_DESTRIGINWAIT:1; /*!< bit: 9 INTREN_DESTRIGINWAIT */
+ uint32_t INTREN_TRIGOUTACKWAIT:1; /*!< bit: 10 INTREN_TRIGOUTACKWAIT */
+ } AdaTrigIrqEnType;
+
+ typedef struct {
+ uint32_t BUSERR:1; /*!< bit: 0 BUSERR */
+ uint32_t CFGERR:1; /*!< bit: 1 CFGERR */
+ uint32_t SRCTRIGINSELERR:1; /*!< bit: 2 SRCTRIGINSELERR */
+ uint32_t DESTRIGINSELERR:1; /*!< bit: 3 DESTRIGINSELERR */
+ uint32_t TRIGOUTSELERR:1; /*!< bit: 4 TRIGOUTSELERR */
+ uint32_t STREAMERR:1; /*!< bit: 7 STREAMERR */
+ uint32_t ERRINFO:16; /*!< bit: 16..31 ERRINFO[15:0] */
+ } AdaErrInfoType;
+
+ typedef struct {
+ uint32_t SWTRIGINREQ:1; /*!< bit: 16/20 SWTRIGINREQ */
+ uint32_t SWTRIGINTYPE:2; /*!< bit: 17..18/21..22 SWTRIGINTYPE[ 1:0] */
+ } AdaSwTrigInType;
+
+ typedef struct {
+ uint32_t USETRIGIN:1; /*!< bit: 25/26 USE*TRIGIN */
+ uint32_t TRIGINSEL:8; /*!< bit: 0.. 7 TRIGINSEL[ 7:0] */
+ uint32_t TRIGINTYPE:2; /*!< bit: 8.. 9 TRIGINTYPE[ 1:0] */
+ uint32_t TRIGINMODE:2; /*!< bit: 10..11 TRIGINMODE[ 1:0] */
+ uint32_t TRIGINBLKSIZE:8; /*!< bit: 16..23 TRIGINBLKSIZE[ 7:0] */
+ } AdaTrigInType;
+
+ typedef struct {
+ uint32_t USETRIGOUT:1; /*!< bit: 27 USETRIGOUT */
+ uint32_t TRIGOUTSEL:6; /*!< bit: 0.. 5 TRIGOUTSEL[ 5:0] */
+ uint32_t TRIGOUTTYPE:2; /*!< bit: 8.. 9 TRIGOUTTYPE[ 1:0] */
+ } AdaTrigOutType;
+
+ typedef struct {
+ uint32_t USEGPO:1; /*!< bit: 28 USEGPO */
+ uint32_t GPOEN0:32; /*!< bit: 0..31 GPOEN0[31:0] */
+ uint32_t GPOEN1:32; /*!< bit: 0..31 GPOEN1[31:0] */
+ uint32_t GPOVAL0:32; /*!< bit: 0..31 GPOVAL0[31:0] */
+ uint32_t GPOVAL1:32; /*!< bit: 0..31 GPOVAL1[31:0] */
+ } AdaGpoType;
+
+ typedef struct {
+ uint32_t STREAMTYPE:2; /*!< bit: 9..10 STREAMTYPE[ 1:0] */
+ } AdaStreamType;
+
+ typedef struct {
+ uint32_t LINKMEMATTRLO:4; /*!< bit: 0.. 3 SRCMEMATTRLO[ 3:0] */
+ uint32_t LINKMEMATTRHI:4; /*!< bit: 4.. 7 SRCMEMATTRHI[ 3:0] */
+ uint32_t LINKSHAREATTR:2; /*!< bit: 8.. 9 LINKSHAREATTR[ 1:0] */
+ } AdaChannelLinkAttrType;
+
+ typedef struct {
+ uint32_t LINKADDREN:1; /*!< bit: 0 LINKADDREN */
+ uint64_t LINKADDR:62; /*!< bit: LINKADDRHI[31:0] + LINKADDR[29:0] */
+ } AdaCmdLinkType;
+
+ typedef struct {
+ uint32_t CMDRESTARTCNT:16; /*!< bit: 0..15 CMDRESTARTCNT[15:0] */
+ uint32_t CMDRESTARTINFEN:1; /*!< bit: 16 CMDRESTARTINFEN */
+ } AdaAutoRestartType;
+
+ // Non-secure and Secure frame related typedefs
+
+ typedef struct {
+ uint32_t INTR_ANYCHINTR:1; /*!< bit: 0 INTR_ANYCHINTR */
+ uint32_t INTR_ALLCHIDLE:1; /*!< bit: 1 INTR_ALLCHIDLE */
+ uint32_t INTR_ALLCHSTOPPED:1; /*!< bit: 2 INTR_ALLCHSTOPPED */
+ uint32_t INTR_ALLCHPAUSED:1; /*!< bit: 3 INTR_ALLCHPAUSED */
+ } AdaCombIrqType;
+
+ typedef struct {
+ uint32_t STAT_ALLCHIDLE:1; /*!< bit: 16 STAT_ALLCHIDLE */
+ uint32_t STAT_ALLCHSTOPPED:1; /*!< bit: 17 STAT_ALLCHSTOPPED */
+ uint32_t STAT_ALLCHPAUSED:1; /*!< bit: 18 STAT_ALLCHPAUSED */
+ } AdaCombIrqClrType;
+
+ typedef struct {
+ uint32_t INTREN_ANYCHINTR:1; /*!< bit: 0 INTREN_ANYCHINTR */
+ uint32_t INTREN_ALLCHIDLE:1; /*!< bit: 1 INTREN_ALLCHIDLE */
+ uint32_t INTREN_ALLCHSTOPPED:1; /*!< bit: 2 INTREN_ALLCHSTOPPED */
+ uint32_t INTREN_ALLCHPAUSED:1; /*!< bit: 3 INTREN_ALLCHPAUSED */
+ } AdaCombIrqEnType;
+
+ typedef struct {
+ uint32_t CHPTR:6; /*!< bit: 0.. 5 CHSEL[ 5:0] */
+ uint32_t CHID:16; /*!< bit: 0..15 CHID[15:0] */
+ uint32_t CHIDVLD:1; /*!< bit: 16 CHIDVLD */
+ uint32_t CHPRIV:1; /*!< bit: 17 CHPRIV */
+ } AdaCombChCfgType;
+
+
+// Command Link Header Register type definition
+ typedef union {
+ struct {
+ uint32_t REGCLEAR:1; /*< bit: 0 Not referencing any registers. Used for the REGCLEAR bit */
+ uint32_t RESERVED0:1; /*< bit: 1 Reserved for future use */
+ uint32_t INTREN:1; /*< bit: 2 Same as in register bank */
+ uint32_t CTRL:1; /*< bit: 3 Same as in register bank */
+ uint32_t SRCADDR:1; /*< bit: 4 Same as in register bank */
+ uint32_t SRCADDRHI:1; /*< bit: 5 Only present when 40-bit address width is used */
+ uint32_t DESADDR:1; /*< bit: 6 Same as in register bank */
+ uint32_t DESADDRHI:1; /*< bit: 7 Only present when 40-bit address width is used */
+ uint32_t XSIZE:1; /*< bit: 8 Same as in register bank */
+ uint32_t XSIZEHI:1; /*< bit: 9 Same as in register bank */
+ uint32_t SRCTRANSCFG:1; /*< bit: 10 Same as in register bank */
+ uint32_t DESTRANSCFG:1; /*< bit: 11 Same as in register bank */
+ uint32_t XADDRINC:1; /*< bit: 12 Same as in register bank */
+ uint32_t YADDRSTRIDE:1; /*< bit: 13 Same as in register bank */
+ uint32_t FILLVAL:1; /*< bit: 14 Same as in register bank */
+ uint32_t YSIZE:1; /*< bit: 15 Same as in register bank */
+ uint32_t TMPLTCFG:1; /*< bit: 16 Same as in register bank */
+ uint32_t SRCTMPLT:1; /*< bit: 17 Same as in register bank */
+ uint32_t DESTMPLT:1; /*< bit: 18 Same as in register bank */
+ uint32_t SRCTRIGINCFG:1; /*< bit: 19 Same as in register bank */
+ uint32_t DESTRIGINCFG:1; /*< bit: 20 Same as in register bank */
+ uint32_t TRIGOUTCFG:1; /*< bit: 21 Same as in register bank */
+ uint32_t GPOEN0:1; /*< bit: 22 Same as in register bank */
+ uint32_t GPOEN1:1; /*< bit: 23 Only present when more than 32 GPO present */
+ uint32_t GPOVAL0:1; /*< bit: 24 Same as in register bank, only [GPOWIDTH-1:0] are implemented. */
+ uint32_t GPOVAL1:1; /*< bit: 25 Only present when more than 32 GPO present */
+ uint32_t STREAMINTCFG:1; /*< bit: 26 Same as in register bank */
+ uint32_t LINKATTR:1; /*< bit: 27 Same as in register bank */
+ uint32_t RESERVED1:2; /*< bit: 28..29 Not used */
+ uint32_t LINKADDR:1; /*< bit: 30 Same as in register bank */
+ uint32_t LINKADDRHI:1; /*< bit: 31 Only present when 40-bit address width is used */
+ } b;
+ uint32_t w;
+ } AdaCmdLinkHeaderType;
+
+ typedef enum AdaTransizeType_t
+ {
+ BYTE = 0,
+ BITS_8 = 0,
+ HALFWORD = 1,
+ BITS_16 = 1,
+ WORD = 2,
+ BITS_32 = 2,
+ DOUBLEWORD = 3,
+ BITS_64 = 3,
+ BITS_128 = 4,
+ BITS_256 = 5,
+ BITS_512 = 6,
+ BITS_1024 = 7
+ } AdaTransizeType_t;
+
+ typedef enum AdaCommandOperationType_t
+ {
+ OPTYPE_DISABLE = 0,
+ OPTYPE_CONTINUE = 1,
+ OPTYPE_WRAP = 2,
+ OPTYPE_FILL = 3
+ } AdaCommandOperationType_t;
+
+ typedef enum AdaReloadType_t
+ {
+ RELOAD_DISABLED = 0,
+ RELOAD_SIZES = 1,
+ RELOAD_SRC_ADDR_AND_SIZES = 3,
+ RELOAD_DST_ADDR_AND_SIZES = 5,
+ RELOAD_ADDRS_AND_SIZES = 7
+ } AdaReloadType_t;
+
+ typedef enum AdaDoneType_t
+ {
+ DONETYPE_DISABLED = 0,
+ DONETYPE_EOF_CMD = 1,
+ DONETYPE_EOF_AUTORESTART = 3
+ } AdaDoneType_t;
+
+ typedef enum AdaTriggerType_t
+ {
+ TRIGTYPE_SW_ONLY = 0,
+ TRIGTYPE_HW_EXTERNAL = 2,
+ TRIGTYPE_HW_INTERNAL = 3
+ } AdaTriggerType_t;
+
+ typedef enum AdaTriggerInMode_t
+ {
+ TRIGINMODE_CMD = 0,
+ TRIGINMODE_DMA_FLW = 2,
+ TRIGINMODE_PER_FLW = 3
+ } AdaTriggerInMode_t;
+
+ typedef enum AdaTriggerOutType_t
+ {
+ TRIGOUTTYPE_SW = 0,
+ TRIGOUTTYPE_HW = 2,
+ TRIGOUTTYPE_INT = 3
+ } AdaTriggerOutType_t;
+
+ typedef enum AdaSwTriggerType_t
+ {
+ SINGLE = 0,
+ LAST_SINGLE = 1,
+ BLOCK = 2,
+ LAST_BLOCK = 3
+ } AdaSwTriggerType_t;
+
+
+ typedef enum AdaStreamType_t
+ {
+ IN_AND_OUT = 0,
+ OUT_ONLY = 1,
+ IN_ONLY = 2
+ } AdaStreamType_t;
+
+ typedef enum AdaSecurityType_t
+ {
+ SECURE = 0,
+ NON_SECURE = 1
+ } AdaSecurityType_t;
+
+ typedef enum AdaSecurityViolationResp_t
+ {
+ RAZWI = 0,
+ ERR_RESP = 1
+ } AdaSecurityViolationResp_t;
+
+// External variables
+// Channel pointers
+extern DMACH_TypeDef *sec_dma_channels[3];
+extern DMACH_TypeDef *nsec_dma_channels[3];
+
+//Functions
+DMACH_TypeDef* GetChannelPtr(uint32_t ch_num, uint8_t security);
+void AdaEnable(uint32_t ch_num, uint8_t security);
+uint8_t AdaGetEnable( uint32_t ch_num, uint8_t security);
+void AdaStop(uint32_t ch_num, uint8_t security);
+void AdaDisable(uint32_t ch_num, uint8_t security);
+void AdaClear(uint32_t ch_num, uint8_t security);
+void AdaPause(uint32_t ch_num, uint8_t security);
+void AdaResume(uint32_t ch_num, uint8_t security);
+
+void Ada1DCommand(AdaBaseCommandType command_params, uint32_t ch_num, uint8_t security);
+uint32_t GetAdaActualSrcXSize(uint32_t ch_num, uint8_t security);
+uint32_t GetAdaActualDesXSize(uint32_t ch_num, uint8_t security);
+void SetAdaLong1DRegs(AdaBaseCommandType command_params, uint32_t ch_num, uint8_t security);
+void AdaLong1DCommand(AdaBaseCommandType command_params, uint32_t ch_num, uint8_t security);
+
+void AdaSetSrcTranAttrs(AdaChannelSrcAttrType src_attr, uint32_t ch_num, uint8_t security);
+void AdaSetDesTranAttrs(AdaChannelDesAttrType des_attr, uint32_t ch_num, uint8_t security);
+void AdaChannelSettings(AdaChannelSettingsType ch_params, uint32_t ch_num, uint8_t security);
+
+void AdaChannelInit(AdaChannelSettingsType ch_params, AdaChannelSrcAttrType src_attr, AdaChannelDesAttrType des_attr, uint32_t ch_num, uint8_t security);
+void SetAda1DIncrRegs(Ada1DIncrCommandType incr_params, uint32_t ch_num, uint8_t security);
+void Ada1DIncrCommand(AdaBaseCommandType command_params, Ada1DIncrCommandType incr_params, uint32_t ch_num, uint8_t security);
+
+void SetAda2DRegs(Ada2DCommandType y_params, uint32_t ch_num, uint8_t security);
+void Ada2DCommand(AdaBaseCommandType command_params, Ada2DCommandType y_params, uint32_t ch_num, uint8_t security);
+
+void SetAdaWrapRegs(AdaWrapCommandType wrap_params, uint32_t ch_num, uint8_t security);
+void AdaWrapCommand(AdaBaseCommandType command_params, AdaWrapCommandType wrap_params, uint32_t ch_num, uint8_t security);
+void AdaWrap2DCommand(AdaBaseCommandType command_params, Ada2DCommandType y_params, AdaWrapCommandType wrap_params, uint32_t ch_num, uint8_t security);
+
+void SetAdaTmpltRegs(AdaTMPLTCommandType tmplt_params, uint32_t ch_num, uint8_t security);
+void AdaTmpltCommand(AdaBaseCommandType command_params, AdaTMPLTCommandType tmplt_params, uint32_t ch_num, uint8_t security);
+
+AdaStatType AdaReadStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChDoneStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChErrorStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChDisabledStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChStoppedStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChPausedStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChResumeWaitStatus(uint32_t ch_num, uint8_t security);
+
+void AdaClearChDone(uint32_t ch_num, uint8_t security);
+void AdaClearChError(uint32_t ch_num, uint8_t security);
+void AdaClearChDisabled(uint32_t ch_num, uint8_t security);
+void AdaClearChStopped(uint32_t ch_num, uint8_t security);
+void AdaClearAllChIrq(uint32_t ch_num, uint8_t security);
+
+AdaTrigStatType AdaReadTrigStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChSrcTrigInWaitStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChDesTrigInWaitStatus(uint32_t ch_num, uint8_t security);
+uint8_t AdaChTrigOutAckWaitStatus(uint32_t ch_num, uint8_t security);
+
+AdaIrqType AdaReadIrqStatus(uint32_t ch_num, uint8_t security);
+
+void AdaSetIntEn(AdaIrqEnType int_en_params, uint32_t ch_num, uint8_t security);
+void AdaSetDoneIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+void AdaSetErrorIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+void AdaSetDisabledIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+void AdaSetStoppedIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+
+void AdaSetTrigIntEn(AdaTrigIrqEnType trig_int_en_params, uint32_t ch_num, uint8_t security);
+void AdaSetSrcTrigInWaitIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+void AdaSetDestTrigInWaitIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+void AdaSetTrigOutAckWaitIntEn(uint8_t en, uint32_t ch_num, uint8_t security);
+
+AdaErrInfoType AdaReadErrorInfo(uint32_t ch_num, uint8_t security);
+
+AdaSwTrigInType AdaSrcSwTigInState(uint32_t ch_num, uint8_t security);
+AdaSwTrigInType AdaDesSwTigInState(uint32_t ch_num, uint8_t security);
+uint8_t AdaSwTrigOutState(uint32_t ch_num, uint8_t security);
+void AdaDesSwTrigInReq(AdaSwTriggerType_t trigin_type, uint32_t ch_num, uint8_t security);
+void AdaSrcSwTrigInReq(AdaSwTriggerType_t trigin_type, uint32_t ch_num, uint8_t security);
+void AdaSwTrigOutAck(uint32_t ch_num, uint8_t security);
+
+void AdaSrcTrigInInit(AdaTrigInType src_trigin_params, uint32_t ch_num, uint8_t security);
+void AdaSrcTrigInEnable(uint8_t en, uint32_t ch_num, uint8_t security);
+void AdaDesTrigInInit(AdaTrigInType des_trigin_params, uint32_t ch_num, uint8_t security);
+void AdaDesTrigInEnable(uint8_t en, uint32_t ch_num, uint8_t security);
+
+void AdaTrigOutInit(AdaTrigOutType trigout_params, uint32_t ch_num, uint8_t security);
+void AdaTrigOutEnable(uint8_t en, uint32_t ch_num, uint8_t security);
+
+void AdaStreamInit(AdaStreamType stream_params, uint32_t ch_num, uint8_t security);
+void AdaStreamEnable(uint8_t en, uint32_t ch_num, uint8_t security);
+
+void AdaSetLinkTranAttrs(AdaChannelLinkAttrType link_attr, uint32_t ch_num, uint8_t security);
+void AdaSetCmdLink(AdaCmdLinkType cmd_link_params, uint32_t ch_num, uint8_t security);
+
+uint8_t AdaGetLinkTranMemAttrs(uint32_t ch_num, uint8_t security);
+uint8_t AdaGetLinkTranShareAttrs(uint32_t ch_num, uint8_t security);
+uint64_t AdaGetCmdLinkAddr(uint32_t ch_num, uint8_t security);
+
+void AdaAutoRestart(AdaAutoRestartType restart_params, uint32_t ch_num, uint8_t security);
+void AdaSetRestartCntr(uint16_t restartcnt, uint32_t ch_num, uint8_t security);
+void AdaInfRestart(uint8_t inf_restart_en, uint32_t ch_num, uint8_t security);
+
+void AdaSetGPO(uint64_t gpo_value, uint32_t width, uint32_t ch_num, uint8_t security);
+
+//Secure / Non-Secure Frame related functions
+uint32_t GetNonSecCollIrqStat(void);
+uint32_t GetSecCollIrqStat(void);
+AdaCombIrqType AdaReadNSecCombIrqStatus(void);
+AdaCombIrqType AdaReadSecCombIrqStatus(void);
+uint8_t AdaNSecCombinedIrqState(void);
+uint8_t AdaSecCombinedIrqState(void);
+uint8_t AdaNSecAllIdleIrqState(void);
+uint8_t AdaSecAllIdleIrqState(void);
+uint8_t AdaNSecAllStoppedIrqState(void);
+uint8_t AdaSecAllStoppedIrqState(void);
+uint8_t AdaNSecAllPausedIrqState(void);
+uint8_t AdaSecAllPausedIrqState(void);
+
+AdaCombIrqClrType AdaReadSecCombStatus(void);
+AdaCombIrqClrType AdaReadNSecCombStatus(void);
+void AdaClrSecCombIrq(AdaCombIrqClrType clr_state);
+void AdaClrNSecCombIrq(AdaCombIrqClrType clr_state);
+void AdaClrSecAllChIdleIrq(void);
+void AdaClrNSecAllChIdleIrq(void);
+void AdaClrSecAllChStoppedIrq(void);
+void AdaClrNSecAllChStoppedIrq(void);
+void AdaClrSecAllChPausedIrq(void);
+void AdaClrNSecAllChPausedIrq(void);
+
+void AdaSecCombIrqEn(AdaCombIrqEnType irq_en);
+void AdaNSecCombIrqEn(AdaCombIrqEnType irq_en);
+void AdaSecCombCtrlIrqEn(uint8_t irq_en);
+void AdaNSecCombCtrlIrqEn(uint8_t irq_en);
+void AdaSecAllChIdleIrqEn(uint8_t irq_en);
+void AdaNSecAllChIdleIrqEn(uint8_t irq_en);
+void AdaSecAllChStoppedIrqEn(uint8_t irq_en);
+void AdaNSecAllChStoppedIrqEn(uint8_t irq_en);
+void AdaSecAllChPausedIrqEn(uint8_t irq_en);
+void AdaNSecAllChPausedIrqEn(uint8_t irq_en);
+void AdaSecIrqCombine(uint8_t en);
+void AdaNSecIrqCombine(uint8_t en);
+
+void AdaSecAllChStopReq(void);
+void AdaNSecAllChStopReq(void);
+
+void AdaSecAllChPauseReq(void);
+void AdaNSecAllChPauseReq(void);
+
+void AdaSecDisMinPwr(uint8_t dis_min_pwr);
+void AdaNSecDisMinPwr(uint8_t dis_min_pwr);
+
+void AdaSecSetChParams(AdaCombChCfgType ch_params);
+void AdaNSecSetChParams(AdaCombChCfgType ch_params);
+
+//Set channel Security Configuration
+void AdaSetChSecMappig(uint32_t mapping);
+void AdaSetChSecurity(uint32_t ch_num, uint32_t security);
+
+void AdaSetTrigInSecMappig(uint32_t mapping);
+void AdaSetTrigInSecurity(uint32_t trig_num, uint8_t security);
+
+void AdaSetTrigOutSecMappig(uint32_t mapping);
+void AdaSetTrigOutSecurity(uint32_t trig_num, uint8_t security);
+
+void AdaSecSetChPtr(uint8_t ch);
+void AdaNSecSetChPtr(uint8_t ch);
+void AdaSecSetChId(uint8_t ch, uint16_t chid);
+void AdaNSecSetChId(uint8_t ch, uint16_t chid);
+void AdaSecSetChPrivileged(uint8_t ch, uint8_t privileged);
+void AdaNSecSetChPrivileged(uint8_t ch, uint8_t privileged);
+
+void AdaSecViolationIrqEn(uint8_t en);
+void AdaSecViolationResp(uint8_t resp);
+void AdaSecConfigLock(void);
+uint8_t AdaSecViolationIrqState(void);
+void AdaClrSecViolationIrq(void);
+
+uint8_t AdaNSecAllPausedState(void);
+uint8_t AdaSecAllPausedState(void);
+
+uint32_t AdaGetChNum(uint8_t security);
+uint32_t AdaGetTrigInNum(uint8_t security);
+uint32_t AdaGetTrigOutNum(uint8_t security);
+
+uint32_t AdaSecurityViolationTestRead(void);
+
+#endif /* __DMA_COMMAND_LIB_H */
+
diff --git a/software/lib/sw_lib/devices/include/dma_350_reg_typedef.h b/software/lib/sw_lib/devices/include/dma_350_reg_typedef.h
new file mode 100755
index 0000000000000000000000000000000000000000..dbfd225f277d19f389bfa6131d85ecfc96b030d4
--- /dev/null
+++ b/software/lib/sw_lib/devices/include/dma_350_reg_typedef.h
@@ -0,0 +1,805 @@
+/******************************************************************************/
+/* The confidential and proprietary information contained in this file may */
+/* only be used by a person authorised under and to the extent permitted */
+/* by a subsisting licensing agreement from Arm Limited or its affiliates. */
+/* */
+/* (C) COPYRIGHT 2022 Arm Limited or its affiliates. */
+/* ALL RIGHTS RESERVED */
+/* */
+/* This entire notice must be reproduced on all copies of this file */
+/* and copies of this file may only be made by a person if such person is */
+/* permitted to do so under the terms of a subsisting license agreement */
+/* from Arm Limited or its affiliates. */
+/* */
+/* Release Information : DMA350-r0p0-00rel0 */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Abstract : Generated register type definition header file */
+/******************************************************************************/
+
+#ifndef __ADA_DMA_REG_TYPEDEF_H
+#define __ADA_DMA_REG_TYPEDEF_H
+
+#include <stdint.h>
+/******************************************************************************/
+/* Type definitions for ADA_DMA register blocks */
+/******************************************************************************/
+/******************* Register type definitions for DMACH ********************/
+
+typedef union {
+ struct {
+ uint32_t ENABLECMD:1; /*!< bit: 0 ENABLECMD */
+ uint32_t CLEARCMD:1; /*!< bit: 1 CLEARCMD */
+ uint32_t DISABLECMD:1; /*!< bit: 2 DISABLECMD */
+ uint32_t STOPCMD:1; /*!< bit: 3 STOPCMD */
+ uint32_t PAUSECMD:1; /*!< bit: 4 PAUSECMD */
+ uint32_t RESUMECMD:1; /*!< bit: 5 RESUMECMD */
+ uint32_t RESERVED0:10; /*!< bit: 6..15 RESERVED0[ 9:0] */
+ uint32_t SRCSWTRIGINREQ:1; /*!< bit: 16 SRCSWTRIGINREQ */
+ uint32_t SRCSWTRIGINTYPE:2; /*!< bit: 17..18 SRCSWTRIGINTYPE[ 1:0] */
+ uint32_t RESERVED1:1; /*!< bit: 19 RESERVED1 */
+ uint32_t DESSWTRIGINREQ:1; /*!< bit: 20 DESSWTRIGINREQ */
+ uint32_t DESSWTRIGINTYPE:2; /*!< bit: 21..22 DESSWTRIGINTYPE[ 1:0] */
+ uint32_t RESERVED2:1; /*!< bit: 23 RESERVED2 */
+ uint32_t SWTRIGOUTACK:1; /*!< bit: 24 SWTRIGOUTACK */
+ uint32_t RESERVED3:7; /*!< bit: 25..31 RESERVED3[ 6:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_CMD_Type;
+
+typedef union {
+ struct {
+ uint32_t INTR_DONE:1; /*!< bit: 0 INTR_DONE */
+ uint32_t INTR_ERR:1; /*!< bit: 1 INTR_ERR */
+ uint32_t INTR_DISABLED:1; /*!< bit: 2 INTR_DISABLED */
+ uint32_t INTR_STOPPED:1; /*!< bit: 3 INTR_STOPPED */
+ uint32_t RESERVED0:4; /*!< bit: 4.. 7 RESERVED0[ 3:0] */
+ uint32_t INTR_SRCTRIGINWAIT:1; /*!< bit: 8 INTR_SRCTRIGINWAIT */
+ uint32_t INTR_DESTRIGINWAIT:1; /*!< bit: 9 INTR_DESTRIGINWAIT */
+ uint32_t INTR_TRIGOUTACKWAIT:1; /*!< bit: 10 INTR_TRIGOUTACKWAIT */
+ uint32_t RESERVED1:5; /*!< bit: 11..15 RESERVED1[ 4:0] */
+ uint32_t STAT_DONE:1; /*!< bit: 16 STAT_DONE */
+ uint32_t STAT_ERR:1; /*!< bit: 17 STAT_ERR */
+ uint32_t STAT_DISABLED:1; /*!< bit: 18 STAT_DISABLED */
+ uint32_t STAT_STOPPED:1; /*!< bit: 19 STAT_STOPPED */
+ uint32_t STAT_PAUSED:1; /*!< bit: 20 STAT_PAUSED */
+ uint32_t STAT_RESUMEWAIT:1; /*!< bit: 21 STAT_RESUMEWAIT */
+ uint32_t RESERVED2:2; /*!< bit: 22..23 RESERVED2[ 1:0] */
+ uint32_t STAT_SRCTRIGINWAIT:1; /*!< bit: 24 STAT_SRCTRIGINWAIT */
+ uint32_t STAT_DESTRIGINWAIT:1; /*!< bit: 25 STAT_DESTRIGINWAIT */
+ uint32_t STAT_TRIGOUTACKWAIT:1; /*!< bit: 26 STAT_TRIGOUTACKWAIT */
+ uint32_t RESERVED3:5; /*!< bit: 27..31 RESERVED3[ 4:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_STATUS_Type;
+
+typedef union {
+ struct {
+ uint32_t INTREN_DONE:1; /*!< bit: 0 INTREN_DONE */
+ uint32_t INTREN_ERR:1; /*!< bit: 1 INTREN_ERR */
+ uint32_t INTREN_DISABLED:1; /*!< bit: 2 INTREN_DISABLED */
+ uint32_t INTREN_STOPPED:1; /*!< bit: 3 INTREN_STOPPED */
+ uint32_t RESERVED0:4; /*!< bit: 4.. 7 RESERVED0[ 3:0] */
+ uint32_t INTREN_SRCTRIGINWAIT:1; /*!< bit: 8 INTREN_SRCTRIGINWAIT */
+ uint32_t INTREN_DESTRIGINWAIT:1; /*!< bit: 9 INTREN_DESTRIGINWAIT */
+ uint32_t INTREN_TRIGOUTACKWAIT:1; /*!< bit: 10 INTREN_TRIGOUTACKWAIT */
+ uint32_t RESERVED1:21; /*!< bit: 11..31 RESERVED1[20:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_INTREN_Type;
+
+typedef union {
+ struct {
+ uint32_t TRANSIZE:3; /*!< bit: 0.. 2 TRANSIZE[ 2:0] */
+ uint32_t RESERVED0:1; /*!< bit: 3 RESERVED0 */
+ uint32_t CHPRIO:4; /*!< bit: 4.. 7 CHPRIO[ 3:0] */
+ uint32_t RESERVED1:1; /*!< bit: 8 RESERVED1 */
+ uint32_t XTYPE:3; /*!< bit: 9..11 XTYPE[ 2:0] */
+ uint32_t YTYPE:3; /*!< bit: 12..14 YTYPE[ 2:0] */
+ uint32_t RESERVED2:3; /*!< bit: 15..17 RESERVED2[ 2:0] */
+ uint32_t REGRELOADTYPE:3; /*!< bit: 18..20 REGRELOADTYPE[ 2:0] */
+ uint32_t DONETYPE:3; /*!< bit: 21..23 DONETYPE[ 2:0] */
+ uint32_t DONEPAUSEEN:1; /*!< bit: 24 DONEPAUSEEN */
+ uint32_t USESRCTRIGIN:1; /*!< bit: 25 USESRCTRIGIN */
+ uint32_t USEDESTRIGIN:1; /*!< bit: 26 USEDESTRIGIN */
+ uint32_t USETRIGOUT:1; /*!< bit: 27 USETRIGOUT */
+ uint32_t USEGPO:1; /*!< bit: 28 USEGPO */
+ uint32_t USESTREAM:1; /*!< bit: 29 USESTREAM */
+ uint32_t RESERVED3:2; /*!< bit: 30..31 RESERVED3[ 1:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_CTRL_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 SRCADDR[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_SRCADDR_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCADDRHI:32; /*!< bit: 0..31 SRCADDRHI[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_SRCADDRHI_Type;
+
+typedef union {
+ struct {
+ uint32_t DESADDR:32; /*!< bit: 0..31 DESADDR[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_DESADDR_Type;
+
+typedef union {
+ struct {
+ uint32_t DESADDRHI:32; /*!< bit: 0..31 DESADDRHI[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_DESADDRHI_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCXSIZE:16; /*!< bit: 0..15 SRCXSIZE[15:0] */
+ uint32_t DESXSIZE:16; /*!< bit: 16..31 DESXSIZE[15:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_XSIZE_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCXSIZEHI:16; /*!< bit: 0..15 SRCXSIZEHI[15:0] */
+ uint32_t DESXSIZEHI:16; /*!< bit: 16..31 DESXSIZEHI[15:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_XSIZEHI_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCMEMATTRLO:4; /*!< bit: 0.. 3 SRCMEMATTRLO[ 3:0] */
+ uint32_t SRCMEMATTRHI:4; /*!< bit: 4.. 7 SRCMEMATTRHI[ 3:0] */
+ uint32_t SRCSHAREATTR:2; /*!< bit: 8.. 9 SRCSHAREATTR[ 1:0] */
+ uint32_t SRCNONSECATTR:1; /*!< bit: 10 SRCNONSECATTR */
+ uint32_t SRCPRIVATTR:1; /*!< bit: 11 SRCPRIVATTR */
+ uint32_t RESERVED0:4; /*!< bit: 12..15 RESERVED0[ 3:0] */
+ uint32_t SRCMAXBURSTLEN:4; /*!< bit: 16..19 SRCMAXBURSTLEN[ 3:0] */
+ uint32_t RESERVED1:12; /*!< bit: 20..31 RESERVED1[11:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_SRCTRANSCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t DESMEMATTRLO:4; /*!< bit: 0.. 3 DESMEMATTRLO[ 3:0] */
+ uint32_t DESMEMATTRHI:4; /*!< bit: 4.. 7 DESMEMATTRHI[ 3:0] */
+ uint32_t DESSHAREATTR:2; /*!< bit: 8.. 9 DESSHAREATTR[ 1:0] */
+ uint32_t DESNONSECATTR:1; /*!< bit: 10 DESNONSECATTR */
+ uint32_t DESPRIVATTR:1; /*!< bit: 11 DESPRIVATTR */
+ uint32_t RESERVED0:4; /*!< bit: 12..15 RESERVED0[ 3:0] */
+ uint32_t DESMAXBURSTLEN:4; /*!< bit: 16..19 DESMAXBURSTLEN[ 3:0] */
+ uint32_t RESERVED1:12; /*!< bit: 20..31 RESERVED1[11:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_DESTRANSCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCXADDRINC:16; /*!< bit: 0..15 SRCXADDRINC[15:0] */
+ uint32_t DESXADDRINC:16; /*!< bit: 16..31 DESXADDRINC[15:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_XADDRINC_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCYADDRSTRIDE:16; /*!< bit: 0..15 SRCYADDRSTRIDE[15:0] */
+ uint32_t DESYADDRSTRIDE:16; /*!< bit: 16..31 DESYADDRSTRIDE[15:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_YADDRSTRIDE_Type;
+
+typedef union {
+ struct {
+ uint32_t FILLVAL:32; /*!< bit: 0..31 FILLVAL[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_FILLVAL_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCYSIZE:16; /*!< bit: 0..15 SRCYSIZE[15:0] */
+ uint32_t DESYSIZE:16; /*!< bit: 16..31 DESYSIZE[15:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_YSIZE_Type;
+
+typedef union {
+ struct {
+ uint32_t RESERVED0:8; /*!< bit: 0.. 7 RESERVED0[ 7:0] */
+ uint32_t SRCTMPLTSIZE:5; /*!< bit: 8..12 SRCTMPLTSIZE[ 4:0] */
+ uint32_t RESERVED1:3; /*!< bit: 13..15 RESERVED1[ 2:0] */
+ uint32_t DESTMPLTSIZE:5; /*!< bit: 16..20 DESTMPLTSIZE[ 4:0] */
+ uint32_t RESERVED2:11; /*!< bit: 21..31 RESERVED2[10:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_TMPLTCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCTMPLTLSB:1; /*!< bit: 0 SRCTMPLTLSB */
+ uint32_t SRCTMPLT:31; /*!< bit: 1..31 SRCTMPLT[30:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_SRCTMPLT_Type;
+
+typedef union {
+ struct {
+ uint32_t DESTMPLTLSB:1; /*!< bit: 0 DESTMPLTLSB */
+ uint32_t DESTMPLT:31; /*!< bit: 1..31 DESTMPLT[30:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_DESTMPLT_Type;
+
+typedef union {
+ struct {
+ uint32_t SRCTRIGINSEL:8; /*!< bit: 0.. 7 SRCTRIGINSEL[ 7:0] */
+ uint32_t SRCTRIGINTYPE:2; /*!< bit: 8.. 9 SRCTRIGINTYPE[ 1:0] */
+ uint32_t SRCTRIGINMODE:2; /*!< bit: 10..11 SRCTRIGINMODE[ 1:0] */
+ uint32_t RESERVED0:4; /*!< bit: 12..15 RESERVED0[ 3:0] */
+ uint32_t SRCTRIGINBLKSIZE:8; /*!< bit: 16..23 SRCTRIGINBLKSIZE[ 7:0] */
+ uint32_t RESERVED1:8; /*!< bit: 24..31 RESERVED1[ 7:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_SRCTRIGINCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t DESTRIGINSEL:8; /*!< bit: 0.. 7 DESTRIGINSEL[ 7:0] */
+ uint32_t DESTRIGINTYPE:2; /*!< bit: 8.. 9 DESTRIGINTYPE[ 1:0] */
+ uint32_t DESTRIGINMODE:2; /*!< bit: 10..11 DESTRIGINMODE[ 1:0] */
+ uint32_t RESERVED0:4; /*!< bit: 12..15 RESERVED0[ 3:0] */
+ uint32_t DESTRIGINBLKSIZE:8; /*!< bit: 16..23 DESTRIGINBLKSIZE[ 7:0] */
+ uint32_t RESERVED1:8; /*!< bit: 24..31 RESERVED1[ 7:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_DESTRIGINCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t TRIGOUTSEL:6; /*!< bit: 0.. 5 TRIGOUTSEL[ 5:0] */
+ uint32_t RESERVED0:2; /*!< bit: 6.. 7 RESERVED0[ 1:0] */
+ uint32_t TRIGOUTTYPE:2; /*!< bit: 8.. 9 TRIGOUTTYPE[ 1:0] */
+ uint32_t RESERVED1:22; /*!< bit: 10..31 RESERVED1[21:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_TRIGOUTCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t GPOEN0:32; /*!< bit: 0..31 GPOEN0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_GPOEN0_Type;
+
+typedef union {
+ struct {
+ uint32_t GPOVAL0:32; /*!< bit: 0..31 GPOVAL0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_GPOVAL0_Type;
+
+typedef union {
+ struct {
+ uint32_t RESERVED0:9; /*!< bit: 0.. 8 RESERVED0[ 8:0] */
+ uint32_t STREAMTYPE:2; /*!< bit: 9..10 STREAMTYPE[ 1:0] */
+ uint32_t RESERVED1:21; /*!< bit: 11..31 RESERVED1[20:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_STREAMINTCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t LINKMEMATTRLO:4; /*!< bit: 0.. 3 LINKMEMATTRLO[ 3:0] */
+ uint32_t LINKMEMATTRHI:4; /*!< bit: 4.. 7 LINKMEMATTRHI[ 3:0] */
+ uint32_t LINKSHAREATTR:2; /*!< bit: 8.. 9 LINKSHAREATTR[ 1:0] */
+ uint32_t RESERVED0:22; /*!< bit: 10..31 RESERVED0[21:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_LINKATTR_Type;
+
+typedef union {
+ struct {
+ uint32_t CMDRESTARTCNT:16; /*!< bit: 0..15 CMDRESTARTCNT[15:0] */
+ uint32_t CMDRESTARTINFEN:1; /*!< bit: 16 CMDRESTARTINFEN */
+ uint32_t RESERVED0:15; /*!< bit: 17..31 RESERVED0[14:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_AUTOCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t LINKADDREN:1; /*!< bit: 0 LINKADDREN */
+ uint32_t RESERVED0:1; /*!< bit: 1 RESERVED0 */
+ uint32_t LINKADDR:30; /*!< bit: 2..31 LINKADDR[29:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_LINKADDR_Type;
+
+typedef union {
+ struct {
+ uint32_t LINKADDRHI:32; /*!< bit: 0..31 LINKADDRHI[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_LINKADDRHI_Type;
+
+typedef union {
+ struct {
+ uint32_t GPOREAD0:32; /*!< bit: 0..31 GPOREAD0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_GPOREAD0_Type;
+
+typedef union {
+ struct {
+ uint32_t WRKREGPTR:4; /*!< bit: 0.. 3 WRKREGPTR[ 3:0] */
+ uint32_t RESERVED0:28; /*!< bit: 4..31 RESERVED0[27:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_WRKREGPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t WRKREGVAL:32; /*!< bit: 0..31 WRKREGVAL[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_WRKREGVAL_Type;
+
+typedef union {
+ struct {
+ uint32_t BUSERR:1; /*!< bit: 0 BUSERR */
+ uint32_t CFGERR:1; /*!< bit: 1 CFGERR */
+ uint32_t SRCTRIGINSELERR:1; /*!< bit: 2 SRCTRIGINSELERR */
+ uint32_t DESTRIGINSELERR:1; /*!< bit: 3 DESTRIGINSELERR */
+ uint32_t TRIGOUTSELERR:1; /*!< bit: 4 TRIGOUTSELERR */
+ uint32_t RESERVED0:2; /*!< bit: 5.. 6 RESERVED0[ 1:0] */
+ uint32_t STREAMERR:1; /*!< bit: 7 STREAMERR */
+ uint32_t RESERVED1:8; /*!< bit: 8..15 RESERVED1[ 7:0] */
+ uint32_t ERRINFO:16; /*!< bit: 16..31 ERRINFO[15:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_ERRINFO_Type;
+
+typedef union {
+ struct {
+ uint32_t IMPLEMENTER:12; /*!< bit: 0..11 IMPLEMENTER[11:0] */
+ uint32_t REVISION:4; /*!< bit: 12..15 REVISION[ 3:0] */
+ uint32_t VARIANT:4; /*!< bit: 16..19 VARIANT[ 3:0] */
+ uint32_t PRODUCTID:12; /*!< bit: 20..31 PRODUCTID[11:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_IIDR_Type;
+
+typedef union {
+ struct {
+ uint32_t ARCH_MINOR_REV:4; /*!< bit: 0.. 3 ARCH_MINOR_REV[ 3:0] */
+ uint32_t ARCH_MAJOR_REV:4; /*!< bit: 4.. 7 ARCH_MAJOR_REV[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_AIDR_Type;
+
+typedef union {
+ struct {
+ uint32_t ISSUECAP:3; /*!< bit: 0.. 2 ISSUECAP[ 2:0] */
+ uint32_t RESERVED0:29; /*!< bit: 3..31 RESERVED0[28:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_ISSUECAP_Type;
+
+typedef union {
+ struct {
+ uint32_t DATA_BUFF_SIZE:8; /*!< bit: 0.. 7 DATA_BUFF_SIZE[ 7:0] */
+ uint32_t CMD_BUFF_SIZE:8; /*!< bit: 8..15 CMD_BUFF_SIZE[ 7:0] */
+ uint32_t ADDR_WIDTH:6; /*!< bit: 16..21 ADDR_WIDTH[ 5:0] */
+ uint32_t DATA_WIDTH:3; /*!< bit: 22..24 DATA_WIDTH[ 2:0] */
+ uint32_t RESERVED0:1; /*!< bit: 25 RESERVED0 */
+ uint32_t INC_WIDTH:4; /*!< bit: 26..29 INC_WIDTH[ 3:0] */
+ uint32_t RESERVED1:2; /*!< bit: 30..31 RESERVED1[ 1:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_BUILDCFG0_Type;
+
+typedef union {
+ struct {
+ uint32_t HAS_XSIZEHI:1; /*!< bit: 0 HAS_XSIZEHI */
+ uint32_t HAS_WRAP:1; /*!< bit: 1 HAS_WRAP */
+ uint32_t HAS_2D:1; /*!< bit: 2 HAS_2D */
+ uint32_t HAS_TMPLT:1; /*!< bit: 3 HAS_TMPLT */
+ uint32_t HAS_TRIG:1; /*!< bit: 4 HAS_TRIG */
+ uint32_t HAS_TRIGIN:1; /*!< bit: 5 HAS_TRIGIN */
+ uint32_t HAS_TRIGOUT:1; /*!< bit: 6 HAS_TRIGOUT */
+ uint32_t HAS_TRIGSEL:1; /*!< bit: 7 HAS_TRIGSEL */
+ uint32_t HAS_CMDLINK:1; /*!< bit: 8 HAS_CMDLINK */
+ uint32_t HAS_AUTO:1; /*!< bit: 9 HAS_AUTO */
+ uint32_t HAS_WRKREG:1; /*!< bit: 10 HAS_WRKREG */
+ uint32_t HAS_STREAM:1; /*!< bit: 11 HAS_STREAM */
+ uint32_t HAS_STREAMSEL:1; /*!< bit: 12 HAS_STREAMSEL */
+ uint32_t RESERVED0:5; /*!< bit: 13..17 RESERVED0[ 4:0] */
+ uint32_t HAS_GPOSEL:1; /*!< bit: 18 HAS_GPOSEL */
+ uint32_t GPO_WIDTH:7; /*!< bit: 19..25 GPO_WIDTH[ 6:0] */
+ uint32_t RESERVED1:6; /*!< bit: 26..31 RESERVED1[ 5:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMACH_CH_BUILDCFG1_Type;
+
+
+/**************** Register type definitions for DMANSECCTRL *****************/
+
+typedef union {
+ struct {
+ uint32_t CHINTRSTATUS0:32; /*!< bit: 0..31 CHINTRSTATUS0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_CHINTRSTATUS0_Type;
+
+typedef union {
+ struct {
+ uint32_t INTR_ANYCHINTR:1; /*!< bit: 0 INTR_ANYCHINTR */
+ uint32_t INTR_ALLCHIDLE:1; /*!< bit: 1 INTR_ALLCHIDLE */
+ uint32_t INTR_ALLCHSTOPPED:1; /*!< bit: 2 INTR_ALLCHSTOPPED */
+ uint32_t INTR_ALLCHPAUSED:1; /*!< bit: 3 INTR_ALLCHPAUSED */
+ uint32_t RESERVED0:13; /*!< bit: 4..16 RESERVED0[12:0] */
+ uint32_t STAT_ALLCHIDLE:1; /*!< bit: 17 STAT_ALLCHIDLE */
+ uint32_t STAT_ALLCHSTOPPED:1; /*!< bit: 18 STAT_ALLCHSTOPPED */
+ uint32_t STAT_ALLCHPAUSED:1; /*!< bit: 19 STAT_ALLCHPAUSED */
+ uint32_t RESERVED1:12; /*!< bit: 20..31 RESERVED1[11:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_STATUS_Type;
+
+typedef union {
+ struct {
+ uint32_t INTREN_ANYCHINTR:1; /*!< bit: 0 INTREN_ANYCHINTR */
+ uint32_t INTREN_ALLCHIDLE:1; /*!< bit: 1 INTREN_ALLCHIDLE */
+ uint32_t INTREN_ALLCHSTOPPED:1; /*!< bit: 2 INTREN_ALLCHSTOPPED */
+ uint32_t INTREN_ALLCHPAUSED:1; /*!< bit: 3 INTREN_ALLCHPAUSED */
+ uint32_t RESERVED0:4; /*!< bit: 4.. 7 RESERVED0[ 3:0] */
+ uint32_t ALLCHSTOP:1; /*!< bit: 8 ALLCHSTOP */
+ uint32_t ALLCHPAUSE:1; /*!< bit: 9 ALLCHPAUSE */
+ uint32_t RESERVED1:17; /*!< bit: 10..26 RESERVED1[16:0] */
+ uint32_t DBGHALTNSRO:1; /*!< bit: 27 DBGHALTNSRO */
+ uint32_t DBGHALTEN:1; /*!< bit: 28 DBGHALTEN */
+ uint32_t IDLERETEN:1; /*!< bit: 29 IDLERETEN */
+ uint32_t DISMINPWR:2; /*!< bit: 30..31 DISMINPWR[ 1:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_CTRL_Type;
+
+typedef union {
+ struct {
+ uint32_t CHPTR:6; /*!< bit: 0.. 5 CHPTR[ 5:0] */
+ uint32_t RESERVED0:26; /*!< bit: 6..31 RESERVED0[25:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_CHPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t CHID:16; /*!< bit: 0..15 CHID[15:0] */
+ uint32_t CHIDVLD:1; /*!< bit: 16 CHIDVLD */
+ uint32_t CHPRIV:1; /*!< bit: 17 CHPRIV */
+ uint32_t RESERVED0:14; /*!< bit: 18..31 RESERVED0[13:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_CHCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t NSECSTATUSPTR:4; /*!< bit: 0.. 3 NSECSTATUSPTR[ 3:0] */
+ uint32_t RESERVED0:28; /*!< bit: 4..31 RESERVED0[27:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_STATUSPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t NSECSTATUSVAL:32; /*!< bit: 0..31 NSECSTATUSVAL[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_STATUSVAL_Type;
+
+typedef union {
+ struct {
+ uint32_t NSECSIGNALPTR:4; /*!< bit: 0.. 3 NSECSIGNALPTR[ 3:0] */
+ uint32_t RESERVED0:28; /*!< bit: 4..31 RESERVED0[27:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_SIGNALPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t NSECSIGNALVAL:32; /*!< bit: 0..31 NSECSIGNALVAL[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMANSECCTRL_NSEC_SIGNALVAL_Type;
+
+
+/***************** Register type definitions for DMASECCTRL *****************/
+
+typedef union {
+ struct {
+ uint32_t CHINTRSTATUS0:32; /*!< bit: 0..31 CHINTRSTATUS0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_CHINTRSTATUS0_Type;
+
+typedef union {
+ struct {
+ uint32_t INTR_ANYCHINTR:1; /*!< bit: 0 INTR_ANYCHINTR */
+ uint32_t INTR_ALLCHIDLE:1; /*!< bit: 1 INTR_ALLCHIDLE */
+ uint32_t INTR_ALLCHSTOPPED:1; /*!< bit: 2 INTR_ALLCHSTOPPED */
+ uint32_t INTR_ALLCHPAUSED:1; /*!< bit: 3 INTR_ALLCHPAUSED */
+ uint32_t RESERVED0:13; /*!< bit: 4..16 RESERVED0[12:0] */
+ uint32_t STAT_ALLCHIDLE:1; /*!< bit: 17 STAT_ALLCHIDLE */
+ uint32_t STAT_ALLCHSTOPPED:1; /*!< bit: 18 STAT_ALLCHSTOPPED */
+ uint32_t STAT_ALLCHPAUSED:1; /*!< bit: 19 STAT_ALLCHPAUSED */
+ uint32_t RESERVED1:12; /*!< bit: 20..31 RESERVED1[11:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_STATUS_Type;
+
+typedef union {
+ struct {
+ uint32_t INTREN_ANYCHINTR:1; /*!< bit: 0 INTREN_ANYCHINTR */
+ uint32_t INTREN_ALLCHIDLE:1; /*!< bit: 1 INTREN_ALLCHIDLE */
+ uint32_t INTREN_ALLCHSTOPPED:1; /*!< bit: 2 INTREN_ALLCHSTOPPED */
+ uint32_t INTREN_ALLCHPAUSED:1; /*!< bit: 3 INTREN_ALLCHPAUSED */
+ uint32_t RESERVED0:4; /*!< bit: 4.. 7 RESERVED0[ 3:0] */
+ uint32_t ALLCHSTOP:1; /*!< bit: 8 ALLCHSTOP */
+ uint32_t ALLCHPAUSE:1; /*!< bit: 9 ALLCHPAUSE */
+ uint32_t RESERVED1:17; /*!< bit: 10..26 RESERVED1[16:0] */
+ uint32_t DBGHALTNSRO:1; /*!< bit: 27 DBGHALTNSRO */
+ uint32_t DBGHALTEN:1; /*!< bit: 28 DBGHALTEN */
+ uint32_t IDLERETEN:1; /*!< bit: 29 IDLERETEN */
+ uint32_t DISMINPWR:2; /*!< bit: 30..31 DISMINPWR[ 1:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_CTRL_Type;
+
+typedef union {
+ struct {
+ uint32_t CHPTR:6; /*!< bit: 0.. 5 CHPTR[ 5:0] */
+ uint32_t RESERVED0:26; /*!< bit: 6..31 RESERVED0[25:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_CHPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t CHID:16; /*!< bit: 0..15 CHID[15:0] */
+ uint32_t CHIDVLD:1; /*!< bit: 16 CHIDVLD */
+ uint32_t CHPRIV:1; /*!< bit: 17 CHPRIV */
+ uint32_t RESERVED0:14; /*!< bit: 18..31 RESERVED0[13:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_CHCFG_Type;
+
+typedef union {
+ struct {
+ uint32_t SECSTATUSPTR:4; /*!< bit: 0.. 3 SECSTATUSPTR[ 3:0] */
+ uint32_t RESERVED0:28; /*!< bit: 4..31 RESERVED0[27:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_STATUSPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t SECSTATUSVAL:32; /*!< bit: 0..31 SECSTATUSVAL[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_STATUSVAL_Type;
+
+typedef union {
+ struct {
+ uint32_t SECSIGNALPTR:4; /*!< bit: 0.. 3 SECSIGNALPTR[ 3:0] */
+ uint32_t RESERVED0:28; /*!< bit: 4..31 RESERVED0[27:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_SIGNALPTR_Type;
+
+typedef union {
+ struct {
+ uint32_t SECSIGNALVAL:32; /*!< bit: 0..31 SECSIGNALVAL[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCTRL_SEC_SIGNALVAL_Type;
+
+
+/***************** Register type definitions for DMASECCFG ******************/
+
+typedef union {
+ struct {
+ uint32_t SCFGCHSEC0:32; /*!< bit: 0..31 SCFGCHSEC0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCFG_SCFG_CHSEC0_Type;
+
+typedef union {
+ struct {
+ uint32_t SCFGTRIGINSEC0:32; /*!< bit: 0..31 SCFGTRIGINSEC0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCFG_SCFG_TRIGINSEC0_Type;
+
+typedef union {
+ struct {
+ uint32_t SCFGTRIGOUTSEC0:32; /*!< bit: 0..31 SCFGTRIGOUTSEC0[31:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCFG_SCFG_TRIGOUTSEC0_Type;
+
+typedef union {
+ struct {
+ uint32_t INTREN_SECACCVIO:1; /*!< bit: 0 INTREN_SECACCVIO */
+ uint32_t RSPTYPE_SECACCVIO:1; /*!< bit: 1 RSPTYPE_SECACCVIO */
+ uint32_t RESERVED0:29; /*!< bit: 2..30 RESERVED0[28:0] */
+ uint32_t SEC_CFG_LCK:1; /*!< bit: 31 SEC_CFG_LCK */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCFG_SCFG_CTRL_Type;
+
+typedef union {
+ struct {
+ uint32_t INTR_SECACCVIO:1; /*!< bit: 0 INTR_SECACCVIO */
+ uint32_t RESERVED0:15; /*!< bit: 1..15 RESERVED0[14:0] */
+ uint32_t STAT_SECACCVIO:1; /*!< bit: 16 STAT_SECACCVIO */
+ uint32_t RESERVED1:15; /*!< bit: 17..31 RESERVED1[14:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMASECCFG_SCFG_INTRSTATUS_Type;
+
+
+/****************** Register type definitions for DMAINFO *******************/
+
+typedef union {
+ struct {
+ uint32_t FRAMETYPE:3; /*!< bit: 0.. 2 FRAMETYPE[ 2:0] */
+ uint32_t RESERVED0:1; /*!< bit: 3 RESERVED0 */
+ uint32_t NUM_CHANNELS:6; /*!< bit: 4.. 9 NUM_CHANNELS[ 5:0] */
+ uint32_t ADDR_WIDTH:6; /*!< bit: 10..15 ADDR_WIDTH[ 5:0] */
+ uint32_t DATA_WIDTH:3; /*!< bit: 16..18 DATA_WIDTH[ 2:0] */
+ uint32_t RESERVED1:1; /*!< bit: 19 RESERVED1 */
+ uint32_t CHID_WIDTH:5; /*!< bit: 20..24 CHID_WIDTH[ 4:0] */
+ uint32_t RESERVED2:7; /*!< bit: 25..31 RESERVED2[ 6:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_DMA_BUILDCFG0_Type;
+
+typedef union {
+ struct {
+ uint32_t NUM_TRIGGER_IN:9; /*!< bit: 0.. 8 NUM_TRIGGER_IN[ 8:0] */
+ uint32_t NUM_TRIGGER_OUT:7; /*!< bit: 9..15 NUM_TRIGGER_OUT[ 6:0] */
+ uint32_t HAS_TRIGSEL:1; /*!< bit: 16 HAS_TRIGSEL */
+ uint32_t RESERVED0:7; /*!< bit: 17..23 RESERVED0[ 6:0] */
+ uint32_t RESERVED1:1; /*!< bit: 24 RESERVED1 */
+ uint32_t RESERVED2:7; /*!< bit: 25..31 RESERVED2[ 6:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_DMA_BUILDCFG1_Type;
+
+typedef union {
+ struct {
+ uint32_t RESERVED0:7; /*!< bit: 0.. 6 RESERVED0[ 6:0] */
+ uint32_t HAS_GPOSEL:1; /*!< bit: 7 HAS_GPOSEL */
+ uint32_t HAS_TZ:1; /*!< bit: 8 HAS_TZ */
+ uint32_t HAS_RET:1; /*!< bit: 9 HAS_RET */
+ uint32_t RESERVED1:1; /*!< bit: 10 RESERVED1 */
+ uint32_t RESERVED2:1; /*!< bit: 11 RESERVED2 */
+ uint32_t RESERVED3:20; /*!< bit: 12..31 RESERVED3[19:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_DMA_BUILDCFG2_Type;
+
+typedef union {
+ struct {
+ uint32_t IMPLEMENTER:12; /*!< bit: 0..11 IMPLEMENTER[11:0] */
+ uint32_t REVISION:4; /*!< bit: 12..15 REVISION[ 3:0] */
+ uint32_t VARIANT:4; /*!< bit: 16..19 VARIANT[ 3:0] */
+ uint32_t PRODUCTID:12; /*!< bit: 20..31 PRODUCTID[11:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_IIDR_Type;
+
+typedef union {
+ struct {
+ uint32_t ARCH_MINOR_REV:4; /*!< bit: 0.. 3 ARCH_MINOR_REV[ 3:0] */
+ uint32_t ARCH_MAJOR_REV:4; /*!< bit: 4.. 7 ARCH_MAJOR_REV[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_AIDR_Type;
+
+typedef union {
+ struct {
+ uint32_t DES_2:4; /*!< bit: 0.. 3 DES_2[ 3:0] */
+ uint32_t SIZE:4; /*!< bit: 4.. 7 SIZE[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_PIDR4_Type;
+
+typedef union {
+ struct {
+ uint32_t PART_0:8; /*!< bit: 0.. 7 PART_0[ 7:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_PIDR0_Type;
+
+typedef union {
+ struct {
+ uint32_t PART_1:4; /*!< bit: 0.. 3 PART_1[ 3:0] */
+ uint32_t DES_0:4; /*!< bit: 4.. 7 DES_0[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_PIDR1_Type;
+
+typedef union {
+ struct {
+ uint32_t DES_1:3; /*!< bit: 0.. 2 DES_1[ 2:0] */
+ uint32_t JEDEC:1; /*!< bit: 3 JEDEC */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 REVISION[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_PIDR2_Type;
+
+typedef union {
+ struct {
+ uint32_t CMOD:4; /*!< bit: 0.. 3 CMOD[ 3:0] */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 REVAND[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_PIDR3_Type;
+
+typedef union {
+ struct {
+ uint32_t PRMBL_0:8; /*!< bit: 0.. 7 PRMBL_0[ 7:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_CIDR0_Type;
+
+typedef union {
+ struct {
+ uint32_t PRMBL_1:4; /*!< bit: 0.. 3 PRMBL_1[ 3:0] */
+ uint32_t CLASS:4; /*!< bit: 4.. 7 CLASS[ 3:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_CIDR1_Type;
+
+typedef union {
+ struct {
+ uint32_t PRMBL_2:8; /*!< bit: 0.. 7 PRMBL_2[ 7:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_CIDR2_Type;
+
+typedef union {
+ struct {
+ uint32_t PRMBL_3:8; /*!< bit: 0.. 7 PRMBL_3[ 7:0] */
+ uint32_t RESERVED0:24; /*!< bit: 8..31 RESERVED0[23:0] */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+ } DMAINFO_CIDR3_Type;
+
+
+
+#endif /* __ADA_DMA_REG_TYPEDEF_H */
+
diff --git a/software/lib/sw_lib/devices/include/dma_350_regdef.h b/software/lib/sw_lib/devices/include/dma_350_regdef.h
new file mode 100755
index 0000000000000000000000000000000000000000..a6e05110ed845b3b81ade936cc8c2d776b8a6bbd
--- /dev/null
+++ b/software/lib/sw_lib/devices/include/dma_350_regdef.h
@@ -0,0 +1,1934 @@
+/******************************************************************************/
+/* The confidential and proprietary information contained in this file may */
+/* only be used by a person authorised under and to the extent permitted */
+/* by a subsisting licensing agreement from Arm Limited or its affiliates. */
+/* */
+/* (C) COPYRIGHT 2022 Arm Limited or its affiliates. */
+/* ALL RIGHTS RESERVED */
+/* */
+/* This entire notice must be reproduced on all copies of this file */
+/* and copies of this file may only be made by a person if such person is */
+/* permitted to do so under the terms of a subsisting license agreement */
+/* from Arm Limited or its affiliates. */
+/* */
+/* Release Information : DMA350-r0p0-00rel0 */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Abstract : Generated register definition header file */
+/******************************************************************************/
+
+#ifndef __ADA_DMA_REGDEF_H
+#define __ADA_DMA_REGDEF_H
+
+#include <stdint.h>
+
+#define __IM volatile const
+#define __OM volatile
+#define __IOM volatile
+
+/******************************************************************************/
+/* Type definitions for ADA_DMA register blocks */
+/******************************************************************************/
+
+typedef struct
+{
+ __IOM uint32_t CH_CMD; /*!< Address offset: 0x000, Channel DMA Command Register */
+ __IOM uint32_t CH_STATUS; /*!< Address offset: 0x004, Channel Status Register */
+ __IOM uint32_t CH_INTREN; /*!< Address offset: 0x008, Channel Interrupt Enable Register */
+ __IOM uint32_t CH_CTRL; /*!< Address offset: 0x00C, Channel Control Register */
+ __IOM uint32_t CH_SRCADDR; /*!< Address offset: 0x010, Channel Source Address Register */
+ __IOM uint32_t CH_SRCADDRHI; /*!< Address offset: 0x014, Channel Source Address Register High Bits [63:32] */
+ __IOM uint32_t CH_DESADDR; /*!< Address offset: 0x018, Channel Destination Address Register */
+ __IOM uint32_t CH_DESADDRHI; /*!< Address offset: 0x01C, Channel Destination Address Register, High Bits [63:32] */
+ __IOM uint32_t CH_XSIZE; /*!< Address offset: 0x020, Channel X Dimension Size Register, Lower Bits [15:0] */
+ __IOM uint32_t CH_XSIZEHI; /*!< Address offset: 0x024, Channel X Dimension Size Register, High Bits [31:16] */
+ __IOM uint32_t CH_SRCTRANSCFG; /*!< Address offset: 0x028, Channel Source Transfer Configuration Register */
+ __IOM uint32_t CH_DESTRANSCFG; /*!< Address offset: 0x02C, Channel Destination Transfer Configuration Register */
+ __IOM uint32_t CH_XADDRINC; /*!< Address offset: 0x030, Channel X Dimension Address Increment Register */
+ __IOM uint32_t CH_YADDRSTRIDE; /*!< Address offset: 0x034, Channel Y Dimension Address Stride Register */
+ __IOM uint32_t CH_FILLVAL; /*!< Address offset: 0x038, Channel Fill Pattern Value Register */
+ __IOM uint32_t CH_YSIZE; /*!< Address offset: 0x03C, Channel Y Dimensions Size Register */
+ __IOM uint32_t CH_TMPLTCFG; /*!< Address offset: 0x040, Channel Template Configuration Register */
+ __IOM uint32_t CH_SRCTMPLT; /*!< Address offset: 0x044, Channel Source Template Pattern Register */
+ __IOM uint32_t CH_DESTMPLT; /*!< Address offset: 0x048, Channel Destination Template Pattern Register */
+ __IOM uint32_t CH_SRCTRIGINCFG; /*!< Address offset: 0x04C, Channel Source Trigger In Configuration Register */
+ __IOM uint32_t CH_DESTRIGINCFG; /*!< Address offset: 0x050, Channel Destination Trigger In Configuration Register */
+ __IOM uint32_t CH_TRIGOUTCFG; /*!< Address offset: 0x054, Channel Trigger Out Configuration Register */
+ __IOM uint32_t CH_GPOEN0; /*!< Address offset: 0x058, Channel GPO Driving Enable Register 0 */
+ uint32_t RESERVED0[1]; /*!< Address offset: 0x5C - 0x5C, Reserved */
+ __IOM uint32_t CH_GPOVAL0; /*!< Address offset: 0x060, Channel GPO Value Register 0 */
+ uint32_t RESERVED1[1]; /*!< Address offset: 0x64 - 0x64, Reserved */
+ __IOM uint32_t CH_STREAMINTCFG; /*!< Address offset: 0x068, Channel Stream Interface Configuration Register */
+ uint32_t RESERVED2[1]; /*!< Address offset: 0x6C - 0x6C, Reserved */
+ __IOM uint32_t CH_LINKATTR; /*!< Address offset: 0x070, Channel Link Address Memory Attributes Register */
+ __IOM uint32_t CH_AUTOCFG; /*!< Address offset: 0x074, Channel Automatic Command Restart Configuration Register */
+ __IOM uint32_t CH_LINKADDR; /*!< Address offset: 0x078, Channel Link Address Register */
+ __IOM uint32_t CH_LINKADDRHI; /*!< Address offset: 0x07C, Channel Link Address Register, High Bits [63:32] */
+ __IOM uint32_t CH_GPOREAD0; /*!< Address offset: 0x080, Channel GPO Read Value Register 0 */
+ uint32_t RESERVED3[1]; /*!< Address offset: 0x84 - 0x84, Reserved */
+ __IOM uint32_t CH_WRKREGPTR; /*!< Address offset: 0x088, Channel Working Register Pointer Register */
+ __IOM uint32_t CH_WRKREGVAL; /*!< Address offset: 0x08C, Channel - Working Register Value Register */
+ __IOM uint32_t CH_ERRINFO; /*!< Address offset: 0x090, Channel Error Information Register */
+ uint32_t RESERVED4[13]; /*!< Address offset: 0x94 - 0xC4, Reserved */
+ __IOM uint32_t CH_IIDR; /*!< Address offset: 0x0C8, Channel Implementation Identification Register */
+ __IOM uint32_t CH_AIDR; /*!< Address offset: 0x0CC, Channel Architecture Identification Register */
+ uint32_t RESERVED5[6]; /*!< Address offset: 0xD0 - 0xE4, Reserved */
+ __IOM uint32_t CH_ISSUECAP; /*!< Address offset: 0x0E8, Used for setting issuing capability threshold. */
+ uint32_t RESERVED6[3]; /*!< Address offset: 0xEC - 0xF4, Reserved */
+ __IOM uint32_t CH_BUILDCFG0; /*!< Address offset: 0x0F8, Channel Build Configuration and Capability Register 0 */
+ __IOM uint32_t CH_BUILDCFG1; /*!< Address offset: 0x0FC, Channel Build Configuration and Capability Register 1 */
+} DMACH_TypeDef;
+
+
+typedef struct
+{
+ __IOM uint32_t NSEC_CHINTRSTATUS0; /*!< Address offset: 0x000, Non-Secure Channel Interrupt Status Register 0 */
+ uint32_t RESERVED0[1]; /*!< Address offset: 0x4 - 0x4, Reserved */
+ __IOM uint32_t NSEC_STATUS; /*!< Address offset: 0x008, Non-Secure Status Register */
+ __IOM uint32_t NSEC_CTRL; /*!< Address offset: 0x00C, Non-Secure Control Register */
+ uint32_t RESERVED1[1]; /*!< Address offset: 0x10 - 0x10, Reserved */
+ __IOM uint32_t NSEC_CHPTR; /*!< Address offset: 0x014, Non-Secure Channel Pointer */
+ __IOM uint32_t NSEC_CHCFG; /*!< Address offset: 0x018, Non-Secure Channel Configuration Register */
+ uint32_t RESERVED2[53]; /*!< Address offset: 0x1C - 0xEC, Reserved */
+ __IOM uint32_t NSEC_STATUSPTR; /*!< Address offset: 0x0F0, Non-Secure Unit Status Pointer Register */
+ __IOM uint32_t NSEC_STATUSVAL; /*!< Address offset: 0x0F4, Non-Secure Unit Status Value Register */
+ __IOM uint32_t NSEC_SIGNALPTR; /*!< Address offset: 0x0F8, Non-Secure Unit Signal Pointer */
+ __IOM uint32_t NSEC_SIGNALVAL; /*!< Address offset: 0x0FC, Non-Secure Unit Signal Value Register */
+} DMANSECCTRL_TypeDef;
+
+
+typedef struct
+{
+ __IOM uint32_t SEC_CHINTRSTATUS0; /*!< Address offset: 0x000, Secure Channel Interrupt Status Register 0 */
+ uint32_t RESERVED0[1]; /*!< Address offset: 0x4 - 0x4, Reserved */
+ __IOM uint32_t SEC_STATUS; /*!< Address offset: 0x008, Secure Status Register */
+ __IOM uint32_t SEC_CTRL; /*!< Address offset: 0x00C, Secure Control Register */
+ uint32_t RESERVED1[1]; /*!< Address offset: 0x10 - 0x10, Reserved */
+ __IOM uint32_t SEC_CHPTR; /*!< Address offset: 0x014, Secure Channel Pointer */
+ __IOM uint32_t SEC_CHCFG; /*!< Address offset: 0x018, Secure Channel Configuration Register */
+ uint32_t RESERVED2[53]; /*!< Address offset: 0x1C - 0xEC, Reserved */
+ __IOM uint32_t SEC_STATUSPTR; /*!< Address offset: 0x0F0, Secure Unit Status Pointer Register */
+ __IOM uint32_t SEC_STATUSVAL; /*!< Address offset: 0x0F4, Secure Unit Status Value Register */
+ __IOM uint32_t SEC_SIGNALPTR; /*!< Address offset: 0x0F8, Secure Unit Signal Pointer */
+ __IOM uint32_t SEC_SIGNALVAL; /*!< Address offset: 0x0FC, Secure Unit Signal Value Register */
+} DMASECCTRL_TypeDef;
+
+
+typedef struct
+{
+ __IOM uint32_t SCFG_CHSEC0; /*!< Address offset: 0x000, Secure Configuration Channel Security Mapping Register 0 */
+ uint32_t RESERVED0[1]; /*!< Address offset: 0x4 - 0x4, Reserved */
+ __IOM uint32_t SCFG_TRIGINSEC0; /*!< Address offset: 0x008, Secure Configuration Trigger Input Security Mapping Register 0 */
+ uint32_t RESERVED1[7]; /*!< Address offset: 0xC - 0x24, Reserved */
+ __IOM uint32_t SCFG_TRIGOUTSEC0; /*!< Address offset: 0x028, Secure Configuration Trigger Output Security Mapping Register 0 */
+ uint32_t RESERVED2[5]; /*!< Address offset: 0x2C - 0x3C, Reserved */
+ __IOM uint32_t SCFG_CTRL; /*!< Address offset: 0x040, Secure Configuration Control */
+ __IOM uint32_t SCFG_INTRSTATUS; /*!< Address offset: 0x044, Secure Configuration Interrupt Status */
+} DMASECCFG_TypeDef;
+
+
+typedef struct
+{
+ uint32_t RESERVED0[44]; /*!< Address offset: 0x0 - 0xAC, Reserved */
+ __IOM uint32_t DMA_BUILDCFG0; /*!< Address offset: 0x0B0, DMA Build Configuration Register 0 */
+ __IOM uint32_t DMA_BUILDCFG1; /*!< Address offset: 0x0B4, DMA Build Configuration Register 1 */
+ __IOM uint32_t DMA_BUILDCFG2; /*!< Address offset: 0x0B8, DMA Build Configuration Register 2 */
+ uint32_t RESERVED1[3]; /*!< Address offset: 0xBC - 0xC4, Reserved */
+ __IOM uint32_t IIDR; /*!< Address offset: 0x0C8, Implementation Identification Register */
+ __IOM uint32_t AIDR; /*!< Address offset: 0x0CC, Architecture Identification Register */
+ __IOM uint32_t PIDR4; /*!< Address offset: 0x0D0, Peripheral ID4 Register */
+ uint32_t RESERVED2[3]; /*!< Address offset: 0xD4 - 0xDC, Reserved */
+ __IOM uint32_t PIDR0; /*!< Address offset: 0x0E0, Peripheral ID0 Register */
+ __IOM uint32_t PIDR1; /*!< Address offset: 0x0E4, Peripheral ID1 Register */
+ __IOM uint32_t PIDR2; /*!< Address offset: 0x0E8, Peripheral ID2 Register */
+ __IOM uint32_t PIDR3; /*!< Address offset: 0x0EC, Peripheral ID 3 Register */
+ __IOM uint32_t CIDR0; /*!< Address offset: 0x0F0, Component ID0 Register */
+ __IOM uint32_t CIDR1; /*!< Address offset: 0x0F4, Component ID1 Register */
+ __IOM uint32_t CIDR2; /*!< Address offset: 0x0F8, Component ID2 Register */
+ __IOM uint32_t CIDR3; /*!< Address offset: 0x0FC, Component ID3 Register */
+} DMAINFO_TypeDef;
+
+
+/******************************************************************************/
+/* ADA_DMA register block memory map */
+/******************************************************************************/
+#ifndef ADA_DMA_S_BASE
+#define ADA_DMA_S_BASE 0x01010000UL
+#endif /* ADA_DMA_S_BASE */
+
+#define DMASECCFG_S_BASE (ADA_DMA_S_BASE + 0x0000UL)
+#define DMASECCTRL_S_BASE (ADA_DMA_S_BASE + 0x0100UL)
+#define DMANSECCTRL_S_BASE (ADA_DMA_S_BASE + 0x0200UL)
+#define DMAINFO_S_BASE (ADA_DMA_S_BASE + 0x0F00UL)
+#define DMACH0_S_BASE (ADA_DMA_S_BASE + 0x1000UL)
+#define DMACH1_S_BASE (ADA_DMA_S_BASE + 0x1100UL)
+#define DMACH2_S_BASE (ADA_DMA_S_BASE + 0x1200UL)
+#define DMACH3_S_BASE (ADA_DMA_S_BASE + 0x1300UL)
+// #define DMACH4_S_BASE (ADA_DMA_S_BASE + 0x1400UL)
+// #define DMACH5_S_BASE (ADA_DMA_S_BASE + 0x1500UL)
+// #define DMACH6_S_BASE (ADA_DMA_S_BASE + 0x1600UL)
+// #define DMACH7_S_BASE (ADA_DMA_S_BASE + 0x1700UL)
+
+#ifndef ADA_DMA_NS_BASE
+#define ADA_DMA_NS_BASE 0x01010000UL
+#endif /* ADA_DMA_NS_BASE */
+
+#define DMASECCFG_NS_BASE (ADA_DMA_NS_BASE + 0x0000UL)
+#define DMASECCTRL_NS_BASE (ADA_DMA_NS_BASE + 0x0100UL)
+#define DMANSECCTRL_NS_BASE (ADA_DMA_NS_BASE + 0x0200UL)
+#define DMAINFO_NS_BASE (ADA_DMA_NS_BASE + 0x0F00UL)
+#define DMACH0_NS_BASE (ADA_DMA_NS_BASE + 0x1000UL)
+#define DMACH1_NS_BASE (ADA_DMA_NS_BASE + 0x1100UL)
+#define DMACH2_NS_BASE (ADA_DMA_NS_BASE + 0x1200UL)
+#define DMACH3_NS_BASE (ADA_DMA_NS_BASE + 0x1300UL)
+// #define DMACH4_NS_BASE (ADA_DMA_NS_BASE + 0x1400UL)
+// #define DMACH5_NS_BASE (ADA_DMA_NS_BASE + 0x1500UL)
+// #define DMACH6_NS_BASE (ADA_DMA_NS_BASE + 0x1600UL)
+// #define DMACH7_NS_BASE (ADA_DMA_NS_BASE + 0x1700UL)
+
+/******************************************************************************/
+/* ADA_DMA register block declaration */
+/******************************************************************************/
+#define DMASECCFG_S ((DMASECCFG_TypeDef *) DMASECCFG_S_BASE)
+#define DMASECCTRL_S ((DMASECCTRL_TypeDef *) DMASECCTRL_S_BASE)
+#define DMANSECCTRL_S ((DMANSECCTRL_TypeDef *) DMANSECCTRL_S_BASE)
+#define DMAINFO_S ((DMAINFO_TypeDef *) DMAINFO_S_BASE)
+#define DMACH0_S ((DMACH_TypeDef *) DMACH0_S_BASE)
+#define DMACH1_S ((DMACH_TypeDef *) DMACH1_S_BASE)
+#define DMACH2_S ((DMACH_TypeDef *) DMACH2_S_BASE)
+#define DMACH3_S ((DMACH_TypeDef *) DMACH3_S_BASE)
+// #define DMACH4_S ((DMACH_TypeDef *) DMACH4_S_BASE)
+// #define DMACH5_S ((DMACH_TypeDef *) DMACH5_S_BASE)
+// #define DMACH6_S ((DMACH_TypeDef *) DMACH6_S_BASE)
+// #define DMACH7_S ((DMACH_TypeDef *) DMACH7_S_BASE)
+
+#define DMASECCFG_NS ((DMASECCFG_TypeDef *) DMASECCFG_NS_BASE)
+#define DMASECCTRL_NS ((DMASECCTRL_TypeDef *) DMASECCTRL_NS_BASE)
+#define DMANSECCTRL_NS ((DMANSECCTRL_TypeDef *) DMANSECCTRL_NS_BASE)
+#define DMAINFO_NS ((DMAINFO_TypeDef *) DMAINFO_NS_BASE)
+#define DMACH0_NS ((DMACH_TypeDef *) DMACH0_NS_BASE)
+#define DMACH1_NS ((DMACH_TypeDef *) DMACH1_NS_BASE)
+#define DMACH2_NS ((DMACH_TypeDef *) DMACH2_NS_BASE)
+#define DMACH3_NS ((DMACH_TypeDef *) DMACH3_NS_BASE)
+// #define DMACH4_NS ((DMACH_TypeDef *) DMACH4_NS_BASE)
+// #define DMACH5_NS ((DMACH_TypeDef *) DMACH5_NS_BASE)
+// #define DMACH6_NS ((DMACH_TypeDef *) DMACH6_NS_BASE)
+// #define DMACH7_NS ((DMACH_TypeDef *) DMACH7_NS_BASE)
+
+/******************************************************************************/
+/* Field Definitions of Registers */
+/******************************************************************************/
+
+/******************************************************************************/
+/* DMACH */
+/******************************************************************************/
+
+
+/****************** Field definitions for CH_CMD register *******************/
+#define DMA_CH_CMD_ENABLECMD_Pos (0U)
+#define DMA_CH_CMD_ENABLECMD_Msk (0x1UL << DMA_CH_CMD_ENABLECMD_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_CMD_ENABLECMD DMA_CH_CMD_ENABLECMD_Msk /*!< ENABLECMD bit Channel Enable. When set to '1', enables the channel to run its programmed task. When set to '1', it cannot be set back to zero, and this field will automatically clear to zero when a DMA process is completed. To force the DMA to stop prematurely, you must use CH_CMD.STOPCMD instead.*/
+#define DMA_CH_CMD_CLEARCMD_Pos (1U)
+#define DMA_CH_CMD_CLEARCMD_Msk (0x1UL << DMA_CH_CMD_CLEARCMD_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_CMD_CLEARCMD DMA_CH_CMD_CLEARCMD_Msk /*!< CLEARCMD bit DMA Clear command. When set to '1', it will remain high until all DMA channel registers and any internal queues and buffers are cleared, before returning to '0'. When set at the same time as ENABLECMD or while the DMA channel is already enabled, the clear will only occur after any ongoing DMA operation is either completed, stopped or disabled and the ENABLECMD bit is deasserted by the DMA.*/
+#define DMA_CH_CMD_DISABLECMD_Pos (2U)
+#define DMA_CH_CMD_DISABLECMD_Msk (0x1UL << DMA_CH_CMD_DISABLECMD_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_CMD_DISABLECMD DMA_CH_CMD_DISABLECMD_Msk /*!< DISABLECMD bit Disable DMA Operation at the end of the current DMA command operation. Once set to '1', this field will stay high and the current DMA command will be allowed to complete, but the DMA will not fetch the next linked command or will it auto-restart the DMA command even if they are set. Once the DMA has stopped, it will return to '0' and ENABLECMD is also cleared. When set at the same time as ENABLECMD or when the channel is not enabled then write to this register is ignored.*/
+#define DMA_CH_CMD_STOPCMD_Pos (3U)
+#define DMA_CH_CMD_STOPCMD_Msk (0x1UL << DMA_CH_CMD_STOPCMD_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_CMD_STOPCMD DMA_CH_CMD_STOPCMD_Msk /*!< STOPCMD bit Stop Current DMA Operation. Once set to '1', his will remain high until the DMA channel is stopped cleanly. Then this will return to '0' and ENABLECMD is also cleared. When set at the same time as ENABLECMD or when the channel is not enabled then write to this register is ignored. Note that each DMA channel can have other sources of a stop request and this field will not reflect the state of the other sources.*/
+#define DMA_CH_CMD_PAUSECMD_Pos (4U)
+#define DMA_CH_CMD_PAUSECMD_Msk (0x1UL << DMA_CH_CMD_PAUSECMD_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_CMD_PAUSECMD DMA_CH_CMD_PAUSECMD_Msk /*!< PAUSECMD bit Pause Current DMA Operation. Once set to '1' the status cannot change until the DMA operation reached the paused state indicated by the STAT_PAUSED and STAT_RESUMEWAIT bits. The bit can be set by SW by writing it to '1', the current active DMA operation will be paused as soon as possible, but the ENABLECMD bit will remain HIGH to show that the operation is still active. Cleared automatically when STAT_RESUMEWAIT is set and the RESUMECMD bit is written to '1', meaning that the SW continues the operation of the channel. Note that each DMA channel can have other sources of a pause request and this field will not reflect the state of the other sources. When set at the same time as ENABLECMD or when the channel is not enabled then write to this register is ignored.*/
+#define DMA_CH_CMD_RESUMECMD_Pos (5U)
+#define DMA_CH_CMD_RESUMECMD_Msk (0x1UL << DMA_CH_CMD_RESUMECMD_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_CMD_RESUMECMD DMA_CH_CMD_RESUMECMD_Msk /*!< RESUMECMD bit Resume Current DMA Operation. Writing this bit to '1' means that the DMAC can continue the operation of a paused channel. Can be set to '1' when the PAUSECMD or a STAT_DONE assertion with DONEPAUSEEN set HIGH results in pausing the current DMA channel operation indicated by the STAT_PAUSED and STAT_RESUMEWAIT bits. Otherwise, writes to this bit are ignored.*/
+#define DMA_CH_CMD_SRCSWTRIGINREQ_Pos (16U)
+#define DMA_CH_CMD_SRCSWTRIGINREQ_Msk (0x1UL << DMA_CH_CMD_SRCSWTRIGINREQ_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_CMD_SRCSWTRIGINREQ DMA_CH_CMD_SRCSWTRIGINREQ_Msk /*!< SRCSWTRIGINREQ bit Software Generated Source Trigger Input Request. Write to '1' to create a SW trigger request to the DMA with the specified type in the SRCSWTRIGINTYPE register. Once set to '1', this will remain high until the DMA accepted the trigger and will return this to '0'. It will also be cleared automatically if the current command is completed without expecting another trigger event. When the channel is not enabled, write to this register is ignored.*/
+#define DMA_CH_CMD_SRCSWTRIGINTYPE_Pos (17U)
+#define DMA_CH_CMD_SRCSWTRIGINTYPE_Msk (0x3UL << DMA_CH_CMD_SRCSWTRIGINTYPE_Pos) /*!< 0x00060000UL*/
+#define DMA_CH_CMD_SRCSWTRIGINTYPE DMA_CH_CMD_SRCSWTRIGINTYPE_Msk /*!< SRCSWTRIGINTYPE[ 1:0] bits Software Generated Source Trigger Input Request Type. Selects the trigger request type for the source trigger input when the SW triggers the SRCSWTRIGINREQ bit.
+ - 00: Single request
+ - 01: Last single request
+ - 10: Block request
+ - 11: Last block request
+This field cannot be changed while the SRCSWTRIGINREQ bit is set.*/
+#define DMA_CH_CMD_SRCSWTRIGINTYPE_0 (0x1UL << DMA_CH_CMD_SRCSWTRIGINTYPE_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_CMD_SRCSWTRIGINTYPE_1 (0x2UL << DMA_CH_CMD_SRCSWTRIGINTYPE_Pos) /*!< 0x00040000UL*/
+
+#define DMA_CH_CMD_DESSWTRIGINREQ_Pos (20U)
+#define DMA_CH_CMD_DESSWTRIGINREQ_Msk (0x1UL << DMA_CH_CMD_DESSWTRIGINREQ_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_CMD_DESSWTRIGINREQ DMA_CH_CMD_DESSWTRIGINREQ_Msk /*!< DESSWTRIGINREQ bit Software Generated Destination Trigger Input Request. Write to '1' to create a SW trigger request to the DMA with the specified type in the DESSWTRIGINTYPE register. Once set to '1', this will remain high until the DMA is accepted the trigger and will return this to '0'. It will also be cleared automatically if the current command is completed without expecting another trigger event. When the channel is not enabled, write to this register is ignored.*/
+#define DMA_CH_CMD_DESSWTRIGINTYPE_Pos (21U)
+#define DMA_CH_CMD_DESSWTRIGINTYPE_Msk (0x3UL << DMA_CH_CMD_DESSWTRIGINTYPE_Pos) /*!< 0x00600000UL*/
+#define DMA_CH_CMD_DESSWTRIGINTYPE DMA_CH_CMD_DESSWTRIGINTYPE_Msk /*!< DESSWTRIGINTYPE[ 1:0] bits Software Generated Destination Trigger Input Request Type. Selects the trigger request type for the destination trigger input when the SW triggers the DESSWTRIGINREQ bit.
+ - 00: Single request
+ - 01: Last single request
+ - 10: Block request
+ - 11: Last block request
+This field cannot be changed while the DESSWTRIGINREQ bit is set.*/
+#define DMA_CH_CMD_DESSWTRIGINTYPE_0 (0x1UL << DMA_CH_CMD_DESSWTRIGINTYPE_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_CMD_DESSWTRIGINTYPE_1 (0x2UL << DMA_CH_CMD_DESSWTRIGINTYPE_Pos) /*!< 0x00400000UL*/
+
+#define DMA_CH_CMD_SWTRIGOUTACK_Pos (24U)
+#define DMA_CH_CMD_SWTRIGOUTACK_Msk (0x1UL << DMA_CH_CMD_SWTRIGOUTACK_Pos) /*!< 0x01000000UL*/
+#define DMA_CH_CMD_SWTRIGOUTACK DMA_CH_CMD_SWTRIGOUTACK_Msk /*!< SWTRIGOUTACK bit Software Generated Trigger Output Acknowledge. Write '1' to acknowledge a Trigger Output request from the DMA. Once set to '1', this will remain high until the DMA Trigger Output is raised (either on the trigger output signal or as an interrupt) and the acknowledge is accepted. When the channel is not enabled, write to this register is ignored.*/
+
+/***************** Field definitions for CH_STATUS register *****************/
+#define DMA_CH_STATUS_INTR_DONE_Pos (0U)
+#define DMA_CH_STATUS_INTR_DONE_Msk (0x1UL << DMA_CH_STATUS_INTR_DONE_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_STATUS_INTR_DONE DMA_CH_STATUS_INTR_DONE_Msk /*!< INTR_DONE bit Done Interrupt Flag. This interrupt will be set to HIGH if the INTREN_DONE is set and the STAT_DONE status flag gets raised. Automatically cleared when STAT_DONE is cleared.*/
+#define DMA_CH_STATUS_INTR_ERR_Pos (1U)
+#define DMA_CH_STATUS_INTR_ERR_Msk (0x1UL << DMA_CH_STATUS_INTR_ERR_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_STATUS_INTR_ERR DMA_CH_STATUS_INTR_ERR_Msk /*!< INTR_ERR bit Error Interrupt Flag. This interrupt will be set to HIGH if the INTREN_ERR is set and the STAT_ERR status flag gets raised. Automatically cleared when STAT_ERR is cleared.*/
+#define DMA_CH_STATUS_INTR_DISABLED_Pos (2U)
+#define DMA_CH_STATUS_INTR_DISABLED_Msk (0x1UL << DMA_CH_STATUS_INTR_DISABLED_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_STATUS_INTR_DISABLED DMA_CH_STATUS_INTR_DISABLED_Msk /*!< INTR_DISABLED bit Disabled Interrupt Flag. This interrupt will be set to HIGH if the INTREN_DISABLED is set and the STAT_DISABLED flag gets raised. Automatically cleared when STAT_DISABLED is cleared.*/
+#define DMA_CH_STATUS_INTR_STOPPED_Pos (3U)
+#define DMA_CH_STATUS_INTR_STOPPED_Msk (0x1UL << DMA_CH_STATUS_INTR_STOPPED_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_STATUS_INTR_STOPPED DMA_CH_STATUS_INTR_STOPPED_Msk /*!< INTR_STOPPED bit Stopped Interrupt Flag. This interrupt will be set to HIGH if the INTREN_STOPPED is set and the STAT_STOPPED flag gets raised. Automatically cleared when STAT_STOPPED is cleared.*/
+#define DMA_CH_STATUS_INTR_SRCTRIGINWAIT_Pos (8U)
+#define DMA_CH_STATUS_INTR_SRCTRIGINWAIT_Msk (0x1UL << DMA_CH_STATUS_INTR_SRCTRIGINWAIT_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_STATUS_INTR_SRCTRIGINWAIT DMA_CH_STATUS_INTR_SRCTRIGINWAIT_Msk /*!< INTR_SRCTRIGINWAIT bit Channel is waiting for Source Trigger Interrupt Flag. This interrupt will be set to HIGH if the INTREN_SRCTRIGINWAIT is set and the STAT_SRCTRIGINWAIT status flag is asserted. Automatically cleared when STAT_SRCTRIGINWAIT is cleared.*/
+#define DMA_CH_STATUS_INTR_DESTRIGINWAIT_Pos (9U)
+#define DMA_CH_STATUS_INTR_DESTRIGINWAIT_Msk (0x1UL << DMA_CH_STATUS_INTR_DESTRIGINWAIT_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_STATUS_INTR_DESTRIGINWAIT DMA_CH_STATUS_INTR_DESTRIGINWAIT_Msk /*!< INTR_DESTRIGINWAIT bit Channel is waiting for Destination Trigger Interrupt Flag. This interrupt will be set to HIGH if the INTREN_DESTRIGINWAIT is set and the STAT_DESTRIGINWAIT status flag is asserted. Automatically cleared when STAT_DESTRIGINWAIT is cleared.*/
+#define DMA_CH_STATUS_INTR_TRIGOUTACKWAIT_Pos (10U)
+#define DMA_CH_STATUS_INTR_TRIGOUTACKWAIT_Msk (0x1UL << DMA_CH_STATUS_INTR_TRIGOUTACKWAIT_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_STATUS_INTR_TRIGOUTACKWAIT DMA_CH_STATUS_INTR_TRIGOUTACKWAIT_Msk /*!< INTR_TRIGOUTACKWAIT bit Channel is waiting for output Trigger Acknowledgement Interrupt Flag. This interrupt will be set to HIGH if the INTREN_TRIGOUTACKWAIT is set and the STAT_TRIGOUTACKWAIT status flag is asserted. Automatically cleared when STAT_TRIGOUTACKWAIT is cleared.*/
+#define DMA_CH_STATUS_STAT_DONE_Pos (16U)
+#define DMA_CH_STATUS_STAT_DONE_Msk (0x1UL << DMA_CH_STATUS_STAT_DONE_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_STATUS_STAT_DONE DMA_CH_STATUS_STAT_DONE_Msk /*!< STAT_DONE bit Done Status Flag. This flag will be set to HIGH when the DMA command reaches the state defined by the DONETYPE settings. When DONEPAUSEEN is set the DMA command operation is paused when this flag is asserted. Write '1' to this bit to clear it. Automatically cleared when the ENABLECMD is set.*/
+#define DMA_CH_STATUS_STAT_ERR_Pos (17U)
+#define DMA_CH_STATUS_STAT_ERR_Msk (0x1UL << DMA_CH_STATUS_STAT_ERR_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_STATUS_STAT_ERR DMA_CH_STATUS_STAT_ERR_Msk /*!< STAT_ERR bit Error Status Flag. This flag will be set to HIGH if the DMA encounters an error during its operation. The details about the error event can be found in the ERRINFO register. Write '1' to this bit to clear it. When cleared, it also clears the ERRINFO register. Automatically cleared when the ENABLECMD is set.*/
+#define DMA_CH_STATUS_STAT_DISABLED_Pos (18U)
+#define DMA_CH_STATUS_STAT_DISABLED_Msk (0x1UL << DMA_CH_STATUS_STAT_DISABLED_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_STATUS_STAT_DISABLED DMA_CH_STATUS_STAT_DISABLED_Msk /*!< STAT_DISABLED bit Disabled Status Flag. This flag will be set to HIGH if the DMA channel is successfully disabled using the DISABLECMD command. Write '1' to this bit to clear it. Automatically cleared when the ENABLECMD is set.*/
+#define DMA_CH_STATUS_STAT_STOPPED_Pos (19U)
+#define DMA_CH_STATUS_STAT_STOPPED_Msk (0x1UL << DMA_CH_STATUS_STAT_STOPPED_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_STATUS_STAT_STOPPED DMA_CH_STATUS_STAT_STOPPED_Msk /*!< STAT_STOPPED bit Stopped Status Flag. This flag will be set to HIGH if the DMA channel successfully reached the stopped state. The stop request can come from many internal or external sources. Write '1' to this bit to clear it. Automatically cleared when the ENABLECMD is set.*/
+#define DMA_CH_STATUS_STAT_PAUSED_Pos (20U)
+#define DMA_CH_STATUS_STAT_PAUSED_Msk (0x1UL << DMA_CH_STATUS_STAT_PAUSED_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_STATUS_STAT_PAUSED DMA_CH_STATUS_STAT_PAUSED_Msk /*!< STAT_PAUSED bit Paused Status Flag. This flag will be set to HIGH if the DMA channel successfully paused the operation of the command. The pause request can come from many internal or external sources. When the request to pause is not asserted anymore the bit will be cleared automatically and the command operation can continue.*/
+#define DMA_CH_STATUS_STAT_RESUMEWAIT_Pos (21U)
+#define DMA_CH_STATUS_STAT_RESUMEWAIT_Msk (0x1UL << DMA_CH_STATUS_STAT_RESUMEWAIT_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_STATUS_STAT_RESUMEWAIT DMA_CH_STATUS_STAT_RESUMEWAIT_Msk /*!< STAT_RESUMEWAIT bit Waiting for resume from software Flag. This flag indicates that the DMA channel successfully paused the operation of the command and needs SW acknowledgment to resume the operation. Will be set to HIGH if STAT_PAUSED is asserted and the PAUSECMD bit set in the command register or when the STAT_DONE is asserted and the DONEPAUSEEN bit is set. Cleared when the RESUMECMD bit is set in the command register.*/
+#define DMA_CH_STATUS_STAT_SRCTRIGINWAIT_Pos (24U)
+#define DMA_CH_STATUS_STAT_SRCTRIGINWAIT_Msk (0x1UL << DMA_CH_STATUS_STAT_SRCTRIGINWAIT_Pos) /*!< 0x01000000UL*/
+#define DMA_CH_STATUS_STAT_SRCTRIGINWAIT DMA_CH_STATUS_STAT_SRCTRIGINWAIT_Msk /*!< STAT_SRCTRIGINWAIT bit Channel is waiting for Source Trigger Status. This bit is set to HIGH when DMA channel starts waiting for source input trigger request. Automatically cleared when the source trigger request is received either from HW or SW source. */
+#define DMA_CH_STATUS_STAT_DESTRIGINWAIT_Pos (25U)
+#define DMA_CH_STATUS_STAT_DESTRIGINWAIT_Msk (0x1UL << DMA_CH_STATUS_STAT_DESTRIGINWAIT_Pos) /*!< 0x02000000UL*/
+#define DMA_CH_STATUS_STAT_DESTRIGINWAIT DMA_CH_STATUS_STAT_DESTRIGINWAIT_Msk /*!< STAT_DESTRIGINWAIT bit Channel is waiting for Destination Trigger Status. This bit is set to HIGH when DMA channel starts waiting for destination input trigger request. Automatically cleared when the destination trigger request is received either from HW or SW source.*/
+#define DMA_CH_STATUS_STAT_TRIGOUTACKWAIT_Pos (26U)
+#define DMA_CH_STATUS_STAT_TRIGOUTACKWAIT_Msk (0x1UL << DMA_CH_STATUS_STAT_TRIGOUTACKWAIT_Pos) /*!< 0x04000000UL*/
+#define DMA_CH_STATUS_STAT_TRIGOUTACKWAIT DMA_CH_STATUS_STAT_TRIGOUTACKWAIT_Msk /*!< STAT_TRIGOUTACKWAIT bit Channel is waiting for output Trigger Acknowledgement Status. This bit is set to HIGH when DMA channel starts waiting for output trigger acknowledgement. Automatically cleared when the output trigger acknowledgement is received either from HW or SW source.*/
+
+/***************** Field definitions for CH_INTREN register *****************/
+#define DMA_CH_INTREN_INTREN_DONE_Pos (0U)
+#define DMA_CH_INTREN_INTREN_DONE_Msk (0x1UL << DMA_CH_INTREN_INTREN_DONE_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_INTREN_INTREN_DONE DMA_CH_INTREN_INTREN_DONE_Msk /*!< INTREN_DONE bit Done Interrupt Enable. When set to HIGH, enables the INTR_DONE to be set and raise an interrupt when the STAT_DONE status flag is asserted. When set to LOW, it prevents INTR_DONE to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+#define DMA_CH_INTREN_INTREN_ERR_Pos (1U)
+#define DMA_CH_INTREN_INTREN_ERR_Msk (0x1UL << DMA_CH_INTREN_INTREN_ERR_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_INTREN_INTREN_ERR DMA_CH_INTREN_INTREN_ERR_Msk /*!< INTREN_ERR bit Error Interrupt Enable. When set to HIGH, enables INTR_ERROR to be set and raise an interrupt when the STAT_ERR status flag is asserted. When set to LOW, it prevents INTR_ERR to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+#define DMA_CH_INTREN_INTREN_DISABLED_Pos (2U)
+#define DMA_CH_INTREN_INTREN_DISABLED_Msk (0x1UL << DMA_CH_INTREN_INTREN_DISABLED_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_INTREN_INTREN_DISABLED DMA_CH_INTREN_INTREN_DISABLED_Msk /*!< INTREN_DISABLED bit Disabled Interrupt Enable. When set to HIGH, enables INTR_DISABLED to be set and raise an interrupt when STAT_DISABLED status flag is asserted. When set to LOW, it prevents INTR_DISABLED to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+#define DMA_CH_INTREN_INTREN_STOPPED_Pos (3U)
+#define DMA_CH_INTREN_INTREN_STOPPED_Msk (0x1UL << DMA_CH_INTREN_INTREN_STOPPED_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_INTREN_INTREN_STOPPED DMA_CH_INTREN_INTREN_STOPPED_Msk /*!< INTREN_STOPPED bit Stopped Interrupt Enable. When set to HIGH, enables INTR_STOPPED to be set and raise an interrupt when STAT_STOPPED status flag is asserted. When set to LOW, it prevents INTR_STOPPED to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+#define DMA_CH_INTREN_INTREN_SRCTRIGINWAIT_Pos (8U)
+#define DMA_CH_INTREN_INTREN_SRCTRIGINWAIT_Msk (0x1UL << DMA_CH_INTREN_INTREN_SRCTRIGINWAIT_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_INTREN_INTREN_SRCTRIGINWAIT DMA_CH_INTREN_INTREN_SRCTRIGINWAIT_Msk /*!< INTREN_SRCTRIGINWAIT bit Channel is waiting for Source Trigger Interrupt Enable. When set to HIGH, enables INTR_SRCTRIGINWAIT to be set and raise an interrupt when STAT_SRCTRIGINWAIT status flag is asserted. When set to LOW, it prevents INTR_SRCTRIGINWAIT to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+#define DMA_CH_INTREN_INTREN_DESTRIGINWAIT_Pos (9U)
+#define DMA_CH_INTREN_INTREN_DESTRIGINWAIT_Msk (0x1UL << DMA_CH_INTREN_INTREN_DESTRIGINWAIT_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_INTREN_INTREN_DESTRIGINWAIT DMA_CH_INTREN_INTREN_DESTRIGINWAIT_Msk /*!< INTREN_DESTRIGINWAIT bit Channel is waiting for destination Trigger Interrupt Enable. When set to HIGH, enables INTR_DESTRIGINWAIT to be set and raise an interrupt when STAT_DESTRIGINWAIT status flag is asserted. When set to LOW, it prevents INTR_DESTRIGINWAIT to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+#define DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT_Pos (10U)
+#define DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT_Msk (0x1UL << DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT_Msk /*!< INTREN_TRIGOUTACKWAIT bit Channel is waiting for output Trigger Acknowledgement Interrupt Enable. When set to HIGH, enables INTR_TRIGOUTACKWAIT to be set and raise an interrupt when STAT_TRIGOUTACKWAIT status flag is asserted. When set to LOW, it prevents INTR_TRIGOUTACKWAIT to be asserted. Currently pending interrupts are not affected by clearing this bit.*/
+
+/****************** Field definitions for CH_CTRL register ******************/
+#define DMA_CH_CTRL_TRANSIZE_Pos (0U)
+#define DMA_CH_CTRL_TRANSIZE_Msk (0x7UL << DMA_CH_CTRL_TRANSIZE_Pos) /*!< 0x00000007UL*/
+#define DMA_CH_CTRL_TRANSIZE DMA_CH_CTRL_TRANSIZE_Msk /*!< TRANSIZE[ 2:0] bits Transfer Entity Size. Size in bytes = 2^TRANSIZE.
+ - 000: Byte
+ - 001: Halfworld
+ - 010: Word
+ - 011: Doubleword
+ - 100: 128bits
+ - 101: 256bits
+ - 110: 512bits
+ - 111: 1024bits
+Note that DATA_WIDTH limits this field. Address will be aligned to TRANSIZE by the DMAC by ignoring the lower bits.*/
+#define DMA_CH_CTRL_TRANSIZE_0 (0x1UL << DMA_CH_CTRL_TRANSIZE_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_CTRL_TRANSIZE_1 (0x2UL << DMA_CH_CTRL_TRANSIZE_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_CTRL_TRANSIZE_2 (0x4UL << DMA_CH_CTRL_TRANSIZE_Pos) /*!< 0x00000004UL*/
+
+#define DMA_CH_CTRL_CHPRIO_Pos (4U)
+#define DMA_CH_CTRL_CHPRIO_Msk (0xFUL << DMA_CH_CTRL_CHPRIO_Pos) /*!< 0x000000F0UL*/
+#define DMA_CH_CTRL_CHPRIO DMA_CH_CTRL_CHPRIO_Msk /*!< CHPRIO[ 3:0] bits Channel Priority.
+ - 0: Lowest Priority
+ - 15: Highest Priority*/
+#define DMA_CH_CTRL_CHPRIO_0 (0x1UL << DMA_CH_CTRL_CHPRIO_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_CTRL_CHPRIO_1 (0x2UL << DMA_CH_CTRL_CHPRIO_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_CTRL_CHPRIO_2 (0x4UL << DMA_CH_CTRL_CHPRIO_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_CTRL_CHPRIO_3 (0x8UL << DMA_CH_CTRL_CHPRIO_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_CTRL_XTYPE_Pos (9U)
+#define DMA_CH_CTRL_XTYPE_Msk (0x7UL << DMA_CH_CTRL_XTYPE_Pos) /*!< 0x00000E00UL*/
+#define DMA_CH_CTRL_XTYPE DMA_CH_CTRL_XTYPE_Msk /*!< XTYPE[ 2:0] bits Operation type for X direction:
+ - 000: "disable" - No data transfer will take place for this command. This mode can be used to create empty commands that wait for an event or set GPOs.
+ - 001: "continue" - Copy data in a continuous manner from source to the destination. For 1D operations it is expected that SRCXSIZE is equal to DESXSIZE, other combinations result in UNPREDICTABLE behavior. For 2D operations, this mode can be used for simple 2D to 2D copy but it also allows the reshaping of the data like 1D to 2D or 2D to 1D conversions. If the DESXSIZE is smaller than SRCXSIZE then the read data from the current source line goes to the next destination line. If SRCXSIZE is smaller than DESXSIZE then the reads start on the next line and data is written to the remainder of the current destination line. Note: For 1D to 2D the SRCYSIZE for 2D to 1D conversion the DESYSIZE needs to be set to 1 when using this mode.
+ - 010: "wrap" - Wrap source data within a destination line when the end of the source line is reached. Read starts again from the beginning of the source line and copied to the remainder of the destination line. If the DESXSIZE is smaller than SRCXSIZE then the behavior is UNPREDICTABLE. Not supported when HAS_WRAP is 0 in HW
+ - 011: "fill" - Fill the remainder of the destination line with FILLVAL when the end of the source line is reached. If the DESXSIZE is smaller than SRCXSIZE then the behavior is UNPREDICTABLE. Not supported when HAS_WRAP is 0 in HW.
+ - Others: Reserved.*/
+#define DMA_CH_CTRL_XTYPE_0 (0x1UL << DMA_CH_CTRL_XTYPE_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_CTRL_XTYPE_1 (0x2UL << DMA_CH_CTRL_XTYPE_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_CTRL_XTYPE_2 (0x4UL << DMA_CH_CTRL_XTYPE_Pos) /*!< 0x00000800UL*/
+
+#define DMA_CH_CTRL_YTYPE_Pos (12U)
+#define DMA_CH_CTRL_YTYPE_Msk (0x7UL << DMA_CH_CTRL_YTYPE_Pos) /*!< 0x00007000UL*/
+#define DMA_CH_CTRL_YTYPE DMA_CH_CTRL_YTYPE_Msk /*!< YTYPE[ 2:0] bits Operation type for Y direction:
+ - 000: "disable" - Only do 1D transfers. When HAS_2D is 0, meaning 2D capability is not supported in HW, the YTYPE is always "000".
+ - 001: "continue" - Copy 2D data in a continuous manner from source area to the destination area by using the YSIZE registers. The copy stops when the source runs out of data or the destination runs out of space. Not supported when HAS_2D is 0 in HW.
+ - 010: "wrap" - Wrap the 2D source area within the destination 2D area by starting to copy data from the beginning of the first source line to the remaining space in the destination area. If the destination area is smaller than the source area then the behavior is UNPREDICTABLE. Not supported when HAS_WRAP or HAS_2D is 0 in HW.
+ - 011: Fill the remainder of the destination area with FILLVAL when the source area runs out of data. If the destination area is smaller than the source area then the behavior is UNPREDICTABLE. Not supported when HAS_WRAP or HAS_2D is 0 in HW
+ - Others: Reserved*/
+#define DMA_CH_CTRL_YTYPE_0 (0x1UL << DMA_CH_CTRL_YTYPE_Pos) /*!< 0x00001000UL*/
+#define DMA_CH_CTRL_YTYPE_1 (0x2UL << DMA_CH_CTRL_YTYPE_Pos) /*!< 0x00002000UL*/
+#define DMA_CH_CTRL_YTYPE_2 (0x4UL << DMA_CH_CTRL_YTYPE_Pos) /*!< 0x00004000UL*/
+
+#define DMA_CH_CTRL_REGRELOADTYPE_Pos (18U)
+#define DMA_CH_CTRL_REGRELOADTYPE_Msk (0x7UL << DMA_CH_CTRL_REGRELOADTYPE_Pos) /*!< 0x001C0000UL*/
+#define DMA_CH_CTRL_REGRELOADTYPE DMA_CH_CTRL_REGRELOADTYPE_Msk /*!< REGRELOADTYPE[ 2:0] bits Automatic register reload type. Defines how the DMA command reloads initial values at the end of a DMA command before autorestarting, ending or linking to a new DMA command:
+ - 000: Reload Disabled.
+ - 001: Reload source and destination size registers only.
+ - 011: Reload source address only and all source and destination size registers.
+ - 101: Reload destination address only and all source and destination size registers.
+ - 111: Reload source and destination address and all source and destination size registers.
+ - Others: Reserved.
+NOTE: When CLEARCMD is set, the reloaded registers will also be cleared.*/
+#define DMA_CH_CTRL_REGRELOADTYPE_0 (0x1UL << DMA_CH_CTRL_REGRELOADTYPE_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_CTRL_REGRELOADTYPE_1 (0x2UL << DMA_CH_CTRL_REGRELOADTYPE_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_CTRL_REGRELOADTYPE_2 (0x4UL << DMA_CH_CTRL_REGRELOADTYPE_Pos) /*!< 0x00100000UL*/
+
+#define DMA_CH_CTRL_DONETYPE_Pos (21U)
+#define DMA_CH_CTRL_DONETYPE_Msk (0x7UL << DMA_CH_CTRL_DONETYPE_Pos) /*!< 0x00E00000UL*/
+#define DMA_CH_CTRL_DONETYPE DMA_CH_CTRL_DONETYPE_Msk /*!< DONETYPE[ 2:0] bits Done type selection. This field defines when the STAT_DONE status flag is asserted during the command operation.
+ - 000: STAT_DONE flag is not asserted for this command.
+ - 001: End of a command, before jumping to the next linked command. (default)
+ - 011: End of an autorestart cycle, before starting the next cycle.
+ - Others : Reserved.*/
+#define DMA_CH_CTRL_DONETYPE_0 (0x1UL << DMA_CH_CTRL_DONETYPE_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_CTRL_DONETYPE_1 (0x2UL << DMA_CH_CTRL_DONETYPE_Pos) /*!< 0x00400000UL*/
+#define DMA_CH_CTRL_DONETYPE_2 (0x4UL << DMA_CH_CTRL_DONETYPE_Pos) /*!< 0x00800000UL*/
+
+#define DMA_CH_CTRL_DONEPAUSEEN_Pos (24U)
+#define DMA_CH_CTRL_DONEPAUSEEN_Msk (0x1UL << DMA_CH_CTRL_DONEPAUSEEN_Pos) /*!< 0x01000000UL*/
+#define DMA_CH_CTRL_DONEPAUSEEN DMA_CH_CTRL_DONEPAUSEEN_Msk /*!< DONEPAUSEEN bit Done pause enable. When set to HIGH the assertion of the STAT_DONE flag results in an automatic pause request for the current DMA operation. When the paused state is reached the STAT_RESUMEWAIT flag is also set. When set to LOW the assertion of the STAT_DONE does not pause the progress of the command and the next operation of the channel will be started immediately after the STAT_DONE flag is set.*/
+#define DMA_CH_CTRL_USESRCTRIGIN_Pos (25U)
+#define DMA_CH_CTRL_USESRCTRIGIN_Msk (0x1UL << DMA_CH_CTRL_USESRCTRIGIN_Pos) /*!< 0x02000000UL*/
+#define DMA_CH_CTRL_USESRCTRIGIN DMA_CH_CTRL_USESRCTRIGIN_Msk /*!< USESRCTRIGIN bit Enable Source Trigger Input use for this command.
+ - 0: disable
+ - 1: enable*/
+#define DMA_CH_CTRL_USEDESTRIGIN_Pos (26U)
+#define DMA_CH_CTRL_USEDESTRIGIN_Msk (0x1UL << DMA_CH_CTRL_USEDESTRIGIN_Pos) /*!< 0x04000000UL*/
+#define DMA_CH_CTRL_USEDESTRIGIN DMA_CH_CTRL_USEDESTRIGIN_Msk /*!< USEDESTRIGIN bit Enable Destination Trigger Input use for this command.
+ - 0: disable
+ - 1: enable*/
+#define DMA_CH_CTRL_USETRIGOUT_Pos (27U)
+#define DMA_CH_CTRL_USETRIGOUT_Msk (0x1UL << DMA_CH_CTRL_USETRIGOUT_Pos) /*!< 0x08000000UL*/
+#define DMA_CH_CTRL_USETRIGOUT DMA_CH_CTRL_USETRIGOUT_Msk /*!< USETRIGOUT bit Enable Trigger Output use for this command.
+ - 0: disable
+ - 1: enable*/
+#define DMA_CH_CTRL_USEGPO_Pos (28U)
+#define DMA_CH_CTRL_USEGPO_Msk (0x1UL << DMA_CH_CTRL_USEGPO_Pos) /*!< 0x10000000UL*/
+#define DMA_CH_CTRL_USEGPO DMA_CH_CTRL_USEGPO_Msk /*!< USEGPO bit Enable GPO use for this command.
+ - 0: disable
+ - 1: enable*/
+#define DMA_CH_CTRL_USESTREAM_Pos (29U)
+#define DMA_CH_CTRL_USESTREAM_Msk (0x1UL << DMA_CH_CTRL_USESTREAM_Pos) /*!< 0x20000000UL*/
+#define DMA_CH_CTRL_USESTREAM DMA_CH_CTRL_USESTREAM_Msk /*!< USESTREAM bit Enable Stream Interface use for this command.
+ - 0: disable
+ - 1: enable*/
+
+/**************** Field definitions for CH_SRCADDR register *****************/
+#define DMA_CH_SRCADDR_SRCADDR_Pos (0U)
+#define DMA_CH_SRCADDR_SRCADDR_Msk (0xFFFFFFFFUL << DMA_CH_SRCADDR_SRCADDR_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_SRCADDR_SRCADDR DMA_CH_SRCADDR_SRCADDR_Msk /*!< SRCADDR[31:0] bits Source Address [31:0].*/
+
+
+/*************** Field definitions for CH_SRCADDRHI register ****************/
+#define DMA_CH_SRCADDRHI_SRCADDRHI_Pos (0U)
+#define DMA_CH_SRCADDRHI_SRCADDRHI_Msk (0xFFFFFFFFUL << DMA_CH_SRCADDRHI_SRCADDRHI_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_SRCADDRHI_SRCADDRHI DMA_CH_SRCADDRHI_SRCADDRHI_Msk /*!< SRCADDRHI[31:0] bits Source Address [63:32]. Allows 64-bit addressing but the system might need less address bits defined by ADDR_WIDTH. The not implemented bits remain reserved.*/
+
+
+/**************** Field definitions for CH_DESADDR register *****************/
+#define DMA_CH_DESADDR_DESADDR_Pos (0U)
+#define DMA_CH_DESADDR_DESADDR_Msk (0xFFFFFFFFUL << DMA_CH_DESADDR_DESADDR_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_DESADDR_DESADDR DMA_CH_DESADDR_DESADDR_Msk /*!< DESADDR[31:0] bits Destination Address[31:0]*/
+
+
+/*************** Field definitions for CH_DESADDRHI register ****************/
+#define DMA_CH_DESADDRHI_DESADDRHI_Pos (0U)
+#define DMA_CH_DESADDRHI_DESADDRHI_Msk (0xFFFFFFFFUL << DMA_CH_DESADDRHI_DESADDRHI_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_DESADDRHI_DESADDRHI DMA_CH_DESADDRHI_DESADDRHI_Msk /*!< DESADDRHI[31:0] bits Destination Address[63:32]. Allows 64-bit addressing but the system might need less address bits defined by ADDR_WIDTH. The not implemented bits remain reserved.*/
+
+
+/***************** Field definitions for CH_XSIZE register ******************/
+#define DMA_CH_XSIZE_SRCXSIZE_Pos (0U)
+#define DMA_CH_XSIZE_SRCXSIZE_Msk (0xFFFFUL << DMA_CH_XSIZE_SRCXSIZE_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_CH_XSIZE_SRCXSIZE DMA_CH_XSIZE_SRCXSIZE_Msk /*!< SRCXSIZE[15:0] bits Source Number of Transfers in the X Dimension lower bits [15:0]. This register along with SRCXSIZEHI defines the source data block size of the DMA operation for any 1D operation, and defines the X dimension of the 2D source block for 2D operation.*/
+
+#define DMA_CH_XSIZE_DESXSIZE_Pos (16U)
+#define DMA_CH_XSIZE_DESXSIZE_Msk (0xFFFFUL << DMA_CH_XSIZE_DESXSIZE_Pos) /*!< 0xFFFF0000UL*/
+#define DMA_CH_XSIZE_DESXSIZE DMA_CH_XSIZE_DESXSIZE_Msk /*!< DESXSIZE[15:0] bits Destination Number of Transfers in the X Dimension lower bits [15:0]. This register along with DESXSIZEHI defines the destination data block size of the DMA operation for or any 1D operation, and defines the X dimension of the 2D destination block for a 2D operation. HAS_WRAP or HAS_STREAM configuration needs to be set to allow writes to this register, otherwise it is read-only and writing to SRCXSIZE will also update the value of this register.*/
+
+
+/**************** Field definitions for CH_XSIZEHI register *****************/
+#define DMA_CH_XSIZEHI_SRCXSIZEHI_Pos (0U)
+#define DMA_CH_XSIZEHI_SRCXSIZEHI_Msk (0xFFFFUL << DMA_CH_XSIZEHI_SRCXSIZEHI_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_CH_XSIZEHI_SRCXSIZEHI DMA_CH_XSIZEHI_SRCXSIZEHI_Msk /*!< SRCXSIZEHI[15:0] bits Source Number of Transfers in the X Dimension high bits [31:16]. This register along with SRCXSIZE defines the source data block size of the DMA operation for any 1D operation, and defines the X dimension of the 2D source block for 2D operation.*/
+
+#define DMA_CH_XSIZEHI_DESXSIZEHI_Pos (16U)
+#define DMA_CH_XSIZEHI_DESXSIZEHI_Msk (0xFFFFUL << DMA_CH_XSIZEHI_DESXSIZEHI_Pos) /*!< 0xFFFF0000UL*/
+#define DMA_CH_XSIZEHI_DESXSIZEHI DMA_CH_XSIZEHI_DESXSIZEHI_Msk /*!< DESXSIZEHI[15:0] bits Destination Number of Transfers in the X Dimension high bits [31:16]. This register along with DESXSIZE defines the destination data block size of the DMA operation for or any 1D operation, and defines the X dimension of the 2D destination block for a 2D operation. HAS_WRAP or HAS_STREAM configuration needs to be set to allow writes to this register, otherwise it is read-only and writing to SRCXSIZEHI will also update the value of this register.*/
+
+
+/************** Field definitions for CH_SRCTRANSCFG register ***************/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos (0U)
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Msk (0xFUL << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos) /*!< 0x0000000FUL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Msk /*!< SRCMEMATTRLO[ 3:0] bits Source Transfer Memory Attribute field [3:0].
+When SRCMEMATTRHI is Device type (0000) then this field means:
+ - 0000: Device-nGnRnE
+ - 0100: Device-nGnRE
+ - 1000: Device-nGRE
+ - 1100: Device-GRE
+ - Others: Invalid resulting in UNPREDICTABLE behavior
+When SRCMEMATTRHI is Normal memory type (other than 0000) then this field means:
+ - 0000: Reserved
+ - 0001: Normal memory, Inner Write allocate, Inner Write-through transient
+ - 0010: Normal memory, Inner Read allocate, Inner Write-through transient
+ - 0011: Normal memory, Inner Read/Write allocate, Inner Write-through transient
+ - 0100: Normal memory, Inner non-cacheable
+ - 0101: Normal memory, Inner Write allocate, Inner Write-back transient
+ - 0110: Normal memory, Inner Read allocate, Inner Write-back transient
+ - 0111: Normal memory, Inner Read/Write allocate, Inner Write-back transient
+ - 1000: Normal memory, Inner Write-through non-transient
+ - 1001: Normal memory, Inner Write allocate, Inner Write-through non-transient
+ - 1010: Normal memory, Inner Read allocate, Inner Write-through non-transient
+ - 1011: Normal memory, Inner Read/Write allocate, Inner Write-through non-transient
+ - 1100: Normal memory, Inner Write-back non-transient
+ - 1101: Normal memory, Inner Write allocate, Inner Write-back non-transient
+ - 1110: Normal memory, Inner Read allocate, Inner Write-back non-transient
+ - 1111: Normal memory, Inner Read/Write allocate, Inner Write-back non-transient*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_0 (0x1UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_1 (0x2UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_2 (0x4UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_3 (0x8UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos) /*!< 0x00000008UL*/
+
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos (4U)
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Msk (0xFUL << DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos) /*!< 0x000000F0UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Msk /*!< SRCMEMATTRHI[ 3:0] bits Source Transfer Memory Attribute field [7:4].
+ - 0000: Device memory
+ - 0001: Normal memory, Outer Write allocate, Outer Write-through transient
+ - 0010: Normal memory, Outer Read allocate, Outer Write-through transient
+ - 0011: Normal memory, Outer Read/Write allocate, Outer Write-through transient
+ - 0100: Normal memory, Outer non-cacheable
+ - 0101: Normal memory, Outer Write allocate, Outer Write-back transient
+ - 0110: Normal memory, Outer Read allocate, Outer Write-back transient
+ - 0111: Normal memory, Outer Read/Write allocate, Outer Write-back transient
+ - 1000: Normal memory, Outer Write-through non-transient
+ - 1001: Normal memory, Outer Write allocate, Outer Write-through non-transient
+ - 1010: Normal memory, Outer Read allocate, Outer Write-through non-transient
+ - 1011: Normal memory, Outer Read/Write allocate, Outer Write-through non-transient
+ - 1100: Normal memory, Outer Write-back non-transient
+ - 1101: Normal memory, Outer Write allocate, Outer Write-back non-transient
+ - 1110: Normal memory, Outer Read allocate, Outer Write-back non-transient
+ - 1111: Normal memory, Outer Read/Write allocate, Outer Write-back non-transient*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_0 (0x1UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_1 (0x2UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_2 (0x4UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_3 (0x8UL << DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos (8U)
+#define DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Msk (0x3UL << DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos) /*!< 0x00000300UL*/
+#define DMA_CH_SRCTRANSCFG_SRCSHAREATTR DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Msk /*!< SRCSHAREATTR[ 1:0] bits Source Transfer Shareability Attribute.
+ - 00: Non-shareable
+ - 01: Reserved
+ - 10: Outer shareable
+ - 11: Inner shareable */
+#define DMA_CH_SRCTRANSCFG_SRCSHAREATTR_0 (0x1UL << DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_SRCTRANSCFG_SRCSHAREATTR_1 (0x2UL << DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos) /*!< 0x00000200UL*/
+
+#define DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Pos (10U)
+#define DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Msk (0x1UL << DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_SRCTRANSCFG_SRCNONSECATTR DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Msk /*!< SRCNONSECATTR bit Source Transfer Non-secure Attribute.
+ - 0: Secure
+ - 1: Non-secure
+ When a channel is Non-secure this bit is tied to 1. */
+#define DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Pos (11U)
+#define DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Msk (0x1UL << DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Pos) /*!< 0x00000800UL*/
+#define DMA_CH_SRCTRANSCFG_SRCPRIVATTR DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Msk /*!< SRCPRIVATTR bit Source Transfer Privilege Attribute.
+ - 0: Unprivileged
+ - 1: Privileged
+ When a channel is unprivileged this bit is tied to 0.*/
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos (16U)
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Msk (0xFUL << DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos) /*!< 0x000F0000UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Msk /*!< SRCMAXBURSTLEN[ 3:0] bits Source Max Burst Length. Hint for the DMA on what is the maximum allowed burst size it can use for read transfers. The maximum number of beats sent by the DMA for a read burst is equal to SRCMAXBURSTLEN + 1. Default value is 16 beats, which allows the DMA to set all burst sizes. Note: Limited by the DATA_BUFF_SIZE so larger settings may not always result in larger bursts.*/
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_0 (0x1UL << DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_1 (0x2UL << DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_2 (0x4UL << DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_3 (0x8UL << DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos) /*!< 0x00080000UL*/
+
+
+/************** Field definitions for CH_DESTRANSCFG register ***************/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos (0U)
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO_Msk (0xFUL << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos) /*!< 0x0000000FUL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO DMA_CH_DESTRANSCFG_DESMEMATTRLO_Msk /*!< DESMEMATTRLO[ 3:0] bits Destination Transfer Memory Attribute field [3:0].
+When DESMEMATTRHI is Device type (0000) then this field means:
+ - 0000: Device-nGnRnE
+ - 0100: Device-nGnRE
+ - 1000: Device-nGRE
+ - 1100: Device-GRE
+ - Others: Invalid resulting in UNPREDICTABLE behavior
+When DESMEMATTRHI is Normal Memory type (other than 0000) then this field means:
+ - 0000: Reserved
+ - 0001: Normal memory, Inner Write allocate, Inner Write-through transient
+ - 0010: Normal memory, Inner Read allocate, Inner Write-through transient
+ - 0011: Normal memory, Inner Read/Write allocate, Inner Write-through transient
+ - 0100: Normal memory, Inner non-cacheable
+ - 0101: Normal memory, Inner Write allocate, Inner Write-back transient
+ - 0110: Normal memory, Inner Read allocate, Inner Write-back transient
+ - 0111: Normal memory, Inner Read/Write allocate, Inner Write-back transient
+ - 1000: Normal memory, Inner Write-through non-transient
+ - 1001: Normal memory, Inner Write allocate, Inner Write-through non-transient
+ - 1010: Normal memory, Inner Read allocate, Inner Write-through non-transient
+ - 1011: Normal memory, Inner Read/Write allocate, Inner Write-through non-transient
+ - 1100: Normal memory, Inner Write-back non-transient
+ - 1101: Normal memory, Inner Write allocate, Inner Write-back non-transient
+ - 1110: Normal memory, Inner Read allocate, Inner Write-back non-transient
+ - 1111: Normal memory, Inner Read/Write allocate, Inner Write-back non-transient*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO_0 (0x1UL << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO_1 (0x2UL << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO_2 (0x4UL << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRLO_3 (0x8UL << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos) /*!< 0x00000008UL*/
+
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos (4U)
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI_Msk (0xFUL << DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos) /*!< 0x000000F0UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI DMA_CH_DESTRANSCFG_DESMEMATTRHI_Msk /*!< DESMEMATTRHI[ 3:0] bits Destination Transfer Memory Attribute field [7:4].
+ - 0000: Device memory
+ - 0001: Normal memory, Outer Write allocate, Outer Write-through transient
+ - 0010: Normal memory, Outer Read allocate, Outer Write-through transient
+ - 0011: Normal memory, Outer Read/Write allocate, Outer Write-through transient
+ - 0100: Normal memory, Outer non-cacheable
+ - 0101: Normal memory, Outer Write allocate, Outer Write-back transient
+ - 0110: Normal memory, Outer Read allocate, Outer Write-back transient
+ - 0111: Normal memory, Outer Read/Write allocate, Outer Write-back transient
+ - 1000: Normal memory, Outer Write-through non-transient
+ - 1001: Normal memory, Outer Write allocate, Outer Write-through non-transient
+ - 1010: Normal memory, Outer Read allocate, Outer Write-through non-transient
+ - 1011: Normal memory, Outer Read/Write allocate, Outer Write-through non-transient
+ - 1100: Normal memory, Outer Write-back non-transient
+ - 1101: Normal memory, Outer Write allocate, Outer Write-back non-transient
+ - 1110: Normal memory, Outer Read allocate, Outer Write-back non-transient
+ - 1111: Normal memory, Outer Read/Write allocate, Outer Write-back non-transient*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI_0 (0x1UL << DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI_1 (0x2UL << DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI_2 (0x4UL << DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_DESTRANSCFG_DESMEMATTRHI_3 (0x8UL << DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos (8U)
+#define DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk (0x3UL << DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos) /*!< 0x00000300UL*/
+#define DMA_CH_DESTRANSCFG_DESSHAREATTR DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk /*!< DESSHAREATTR[ 1:0] bits Destination Transfer Shareability Attribute.
+ - 00: Non-shareable
+ - 01: Reserved
+ - 10: Outer shareable
+ - 11: Inner shareable*/
+#define DMA_CH_DESTRANSCFG_DESSHAREATTR_0 (0x1UL << DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_DESTRANSCFG_DESSHAREATTR_1 (0x2UL << DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos) /*!< 0x00000200UL*/
+
+#define DMA_CH_DESTRANSCFG_DESNONSECATTR_Pos (10U)
+#define DMA_CH_DESTRANSCFG_DESNONSECATTR_Msk (0x1UL << DMA_CH_DESTRANSCFG_DESNONSECATTR_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_DESTRANSCFG_DESNONSECATTR DMA_CH_DESTRANSCFG_DESNONSECATTR_Msk /*!< DESNONSECATTR bit Destination Transfer Non-secure Attribute.
+ - 0: Secure
+ - 1: Non-secure
+ When a channel is Non-secure this bit is tied to 1. */
+#define DMA_CH_DESTRANSCFG_DESPRIVATTR_Pos (11U)
+#define DMA_CH_DESTRANSCFG_DESPRIVATTR_Msk (0x1UL << DMA_CH_DESTRANSCFG_DESPRIVATTR_Pos) /*!< 0x00000800UL*/
+#define DMA_CH_DESTRANSCFG_DESPRIVATTR DMA_CH_DESTRANSCFG_DESPRIVATTR_Msk /*!< DESPRIVATTR bit Destination Transfer Privilege Attribute.
+ - 0: Unprivileged
+ - 1: Privileged
+ When a channel is unprivileged this bit is tied to 0.*/
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos (16U)
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Msk (0xFUL << DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos) /*!< 0x000F0000UL*/
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Msk /*!< DESMAXBURSTLEN[ 3:0] bits Destination Max Burst Length. Hint for the DMA on what is the maximum allowed burst size it can use for write transfers. The maximum number of beats sent by the DMA for a write burst is equal to DESMAXBURSTLEN + 1. Default value is 16 beats, which allows the DMA to set all burst sizes. Note: Limited by the DATA_BUFF_SIZE so larger settings may not always result in larger bursts.*/
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_0 (0x1UL << DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_1 (0x2UL << DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_2 (0x4UL << DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_3 (0x8UL << DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos) /*!< 0x00080000UL*/
+
+
+/**************** Field definitions for CH_XADDRINC register ****************/
+#define DMA_CH_XADDRINC_SRCXADDRINC_Pos (0U)
+#define DMA_CH_XADDRINC_SRCXADDRINC_Msk (0xFFFFUL << DMA_CH_XADDRINC_SRCXADDRINC_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_CH_XADDRINC_SRCXADDRINC DMA_CH_XADDRINC_SRCXADDRINC_Msk /*!< SRCXADDRINC[15:0] bits Source X dimension Address Increment. This value is used as the increment between each TRANSIZE transfer. When a single bit is used then only 0 and 1 can be set. For wider increment registers, two's complement used with a range between -32768 to 32767 when the counter is 16-bits wide. The width of the register is indicated by the INC_WIDTH parameter. SRCADDR_next = SRCADDR + 2^TRANSIZE * SRCXADDRINC*/
+
+#define DMA_CH_XADDRINC_DESXADDRINC_Pos (16U)
+#define DMA_CH_XADDRINC_DESXADDRINC_Msk (0xFFFFUL << DMA_CH_XADDRINC_DESXADDRINC_Pos) /*!< 0xFFFF0000UL*/
+#define DMA_CH_XADDRINC_DESXADDRINC DMA_CH_XADDRINC_DESXADDRINC_Msk /*!< DESXADDRINC[15:0] bits Destination X dimension Address Increment. This value is used as the increment between each TRANSIZE transfer. When a single bit is used then only 0 and 1 can be set. For wider increment registers, two's complement used with a range between -32768 to 32767 when the counter is 16-bits wide. The width of the register is indicated by the INC_WIDTH parameter. DESADDR_next = DESADDR + 2^TRANSIZE * DESXADDRINC*/
+
+
+/************** Field definitions for CH_YADDRSTRIDE register ***************/
+#define DMA_CH_YADDRSTRIDE_SRCYADDRSTRIDE_Pos (0U)
+#define DMA_CH_YADDRSTRIDE_SRCYADDRSTRIDE_Msk (0xFFFFUL << DMA_CH_YADDRSTRIDE_SRCYADDRSTRIDE_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_CH_YADDRSTRIDE_SRCYADDRSTRIDE DMA_CH_YADDRSTRIDE_SRCYADDRSTRIDE_Msk /*!< SRCYADDRSTRIDE[15:0] bits Source Address Stride between lines. Calculated in TRANSIZE aligned steps. This value is used to increment the SRCADDR after completing the transfer of a source line. SRCADDR_next_line_base = SRCADDR_line_base + 2^TRANSIZE * SRCYADDRSTRIDE. Two's complement used with a range between -32768 to 32767. When set to 0 the SRCADDR is not incremented after completing one line. Not present when HAS_2D is 0.*/
+
+#define DMA_CH_YADDRSTRIDE_DESYADDRSTRIDE_Pos (16U)
+#define DMA_CH_YADDRSTRIDE_DESYADDRSTRIDE_Msk (0xFFFFUL << DMA_CH_YADDRSTRIDE_DESYADDRSTRIDE_Pos) /*!< 0xFFFF0000UL*/
+#define DMA_CH_YADDRSTRIDE_DESYADDRSTRIDE DMA_CH_YADDRSTRIDE_DESYADDRSTRIDE_Msk /*!< DESYADDRSTRIDE[15:0] bits Destination Address Stride between lines. Calculated in TRANSIZE aligned steps. This value is used to increment the DESADDR after completing the transfer of a destination line. DESADDR_next_line_base = DESADDR_line_base + 2^TRANSIZE * DESYADDRSTRIDE. Two's complement used with a range between -32768 to 32767. When set to 0 the DESADDR is not incremented after completing one line. Not present when HAS_2D is 0.*/
+
+
+/**************** Field definitions for CH_FILLVAL register *****************/
+#define DMA_CH_FILLVAL_FILLVAL_Pos (0U)
+#define DMA_CH_FILLVAL_FILLVAL_Msk (0xFFFFFFFFUL << DMA_CH_FILLVAL_FILLVAL_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_FILLVAL_FILLVAL DMA_CH_FILLVAL_FILLVAL_Msk /*!< FILLVAL[31:0] bits Fill pattern value. When XTYPE or YTYPE is set to fill mode, then this register value is used on the write data bus when the command starts to fill the memory area. The TRANSIZE defines the width of the FILLVAL used for the command. For byte transfers the FILLVAL[7:0] is used, other bits are ignored. For halfword transfers the FILLVAL[15:0] is used, other bits are ignored. For 64-bit and wider transfers the FILLVAL[31:0] pattern is repeated on the full width of the data bus. Not present when HAS_WRAP is 0.*/
+
+
+/***************** Field definitions for CH_YSIZE register ******************/
+#define DMA_CH_YSIZE_SRCYSIZE_Pos (0U)
+#define DMA_CH_YSIZE_SRCYSIZE_Msk (0xFFFFUL << DMA_CH_YSIZE_SRCYSIZE_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_CH_YSIZE_SRCYSIZE DMA_CH_YSIZE_SRCYSIZE_Msk /*!< SRCYSIZE[15:0] bits Source Y dimension or number of lines. Not present when HAS_2D is 0.*/
+
+#define DMA_CH_YSIZE_DESYSIZE_Pos (16U)
+#define DMA_CH_YSIZE_DESYSIZE_Msk (0xFFFFUL << DMA_CH_YSIZE_DESYSIZE_Pos) /*!< 0xFFFF0000UL*/
+#define DMA_CH_YSIZE_DESYSIZE DMA_CH_YSIZE_DESYSIZE_Msk /*!< DESYSIZE[15:0] bits Destination Y dimension or number of lines. Not present when HAS_2D is 0. HAS_WRAP or HAS_STREAM configuration needs to be set to allow writes to this register, otherwise it is read-only.*/
+
+
+/**************** Field definitions for CH_TMPLTCFG register ****************/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos (8U)
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Msk (0x1FUL << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos) /*!< 0x00001F00UL*/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Msk /*!< SRCTMPLTSIZE[ 4:0] bits Source Template Size in number of transfers plus one.
+ - 0: Source template is disabled.
+ - 1 to 31: Bits SRCTMPLT[SRCTMPLTSIZE:0] is used as the source template. Not present when HAS_TMPLT is 0.*/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_0 (0x1UL << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_1 (0x2UL << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_2 (0x4UL << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_3 (0x8UL << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos) /*!< 0x00000800UL*/
+#define DMA_CH_TMPLTCFG_SRCTMPLTSIZE_4 (0x10UL << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos) /*!< 0x00001000UL*/
+
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos (16U)
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_Msk (0x1FUL << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos) /*!< 0x001F0000UL*/
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE DMA_CH_TMPLTCFG_DESTMPLTSIZE_Msk /*!< DESTMPLTSIZE[ 4:0] bits Destination Template Size in number of transfers plus one.
+ - 0: Destination template is disabled.
+ - 1 to 31: DESTMPLT[DESTMPLTSIZE:0] is used as the destination template. Not present when HAS_TMPLT is 0.*/
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_0 (0x1UL << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_1 (0x2UL << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_2 (0x4UL << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_3 (0x8UL << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_TMPLTCFG_DESTMPLTSIZE_4 (0x10UL << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos) /*!< 0x00100000UL*/
+
+
+/**************** Field definitions for CH_SRCTMPLT register ****************/
+#define DMA_CH_SRCTMPLT_SRCTMPLTLSB_Pos (0U)
+#define DMA_CH_SRCTMPLT_SRCTMPLTLSB_Msk (0x1UL << DMA_CH_SRCTMPLT_SRCTMPLTLSB_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_SRCTMPLT_SRCTMPLTLSB DMA_CH_SRCTMPLT_SRCTMPLTLSB_Msk /*!< SRCTMPLTLSB bit Source Packing Template Least Significant Bit. This bit of the template is read only and always set to 1 as template patterns can only start from the base address of the transfer. Not present when HAS_TMPLT is 0.*/
+#define DMA_CH_SRCTMPLT_SRCTMPLT_Pos (1U)
+#define DMA_CH_SRCTMPLT_SRCTMPLT_Msk (0x7FFFFFFFUL << DMA_CH_SRCTMPLT_SRCTMPLT_Pos) /*!< 0xFFFFFFFEUL*/
+#define DMA_CH_SRCTMPLT_SRCTMPLT DMA_CH_SRCTMPLT_SRCTMPLT_Msk /*!< SRCTMPLT[30:0] bits Source Packing Template. Bit[0] is read only and always set to 1 as template patterns can only start from the base address of the transfer. Not present when HAS_TMPLT is 0.*/
+
+
+/**************** Field definitions for CH_DESTMPLT register ****************/
+#define DMA_CH_DESTMPLT_DESTMPLTLSB_Pos (0U)
+#define DMA_CH_DESTMPLT_DESTMPLTLSB_Msk (0x1UL << DMA_CH_DESTMPLT_DESTMPLTLSB_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_DESTMPLT_DESTMPLTLSB DMA_CH_DESTMPLT_DESTMPLTLSB_Msk /*!< DESTMPLTLSB bit Destination Packing Template Least Significant Bit. This bit of the template is read only and always set to 1 as template patterns can only start from the base address of the transfer. Not present when HAS_TMPLT is 0.*/
+#define DMA_CH_DESTMPLT_DESTMPLT_Pos (1U)
+#define DMA_CH_DESTMPLT_DESTMPLT_Msk (0x7FFFFFFFUL << DMA_CH_DESTMPLT_DESTMPLT_Pos) /*!< 0xFFFFFFFEUL*/
+#define DMA_CH_DESTMPLT_DESTMPLT DMA_CH_DESTMPLT_DESTMPLT_Msk /*!< DESTMPLT[30:0] bits Destination Packing Template. Bit[0] is read only and always set to 1 as template patterns can only start from the base address of the transfer. Not present when HAS_TMPLT is 0.*/
+
+
+/************** Field definitions for CH_SRCTRIGINCFG register **************/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos (0U)
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Msk (0xFFUL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x000000FFUL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Msk /*!< SRCTRIGINSEL[ 7:0] bits Source Trigger Input Select*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_0 (0x1UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_1 (0x2UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_2 (0x4UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_3 (0x8UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_4 (0x10UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_5 (0x20UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_6 (0x40UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_7 (0x80UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Pos (8U)
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Msk (0x3UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Pos) /*!< 0x00000300UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Msk /*!< SRCTRIGINTYPE[ 1:0] bits Source Trigger Input Type:
+ - 00: Software only Trigger Request. SRCTRIGINSEL is ignored.
+ - 01: Reserved
+ - 10: HW Trigger Request. Only allowed when HAS_TRIGIN is enabled. SRCTRIGINSEL selects between external trigger inputs if HAS_TRIGSEL is enabled.
+ - 11: Internal Trigger Request. Only allowed when HAS_TRIGSEL is enabled and the DMAC has multiple channels, otherwise treated as HW Trigger Request. SRCTRIGINSEL selects between DMA channels.
+Note: SW triggers are also available when HW or Internal types are selected, but is is not recommended and caution must be taken when the these modes are combined.*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_0 (0x1UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_1 (0x2UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Pos) /*!< 0x00000200UL*/
+
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Pos (10U)
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Msk (0x3UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Pos) /*!< 0x00000C00UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Msk /*!< SRCTRIGINMODE[ 1:0] bits Source Trigger Input Mode:
+ - 00: Command
+ - 01: Reserved
+ - 10: DMA driven Flow control. Only allowed when HAS_TRIGIN is enabled.
+ - 11: Peripheral driven Flow control. Only allowed when HAS_TRIGIN is enabled.
+Note: This field is ignored for Internal triggers as they only support Command triggers.*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_0 (0x1UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_1 (0x2UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Pos) /*!< 0x00000800UL*/
+
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos (16U)
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Msk (0xFFUL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00FF0000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Msk /*!< SRCTRIGINBLKSIZE[ 7:0] bits Source Trigger Input Default Transfer Size. Defined transfer size per trigger + 1.*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_0 (0x1UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_1 (0x2UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_2 (0x4UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_3 (0x8UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_4 (0x10UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_5 (0x20UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_6 (0x40UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00400000UL*/
+#define DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_7 (0x80UL << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) /*!< 0x00800000UL*/
+
+
+/************** Field definitions for CH_DESTRIGINCFG register **************/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos (0U)
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Msk (0xFFUL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x000000FFUL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Msk /*!< DESTRIGINSEL[ 7:0] bits Destination Trigger Input Select*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_0 (0x1UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_1 (0x2UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_2 (0x4UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_3 (0x8UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_4 (0x10UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_5 (0x20UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_6 (0x40UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINSEL_7 (0x80UL << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Pos (8U)
+#define DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Msk (0x3UL << DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Pos) /*!< 0x00000300UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINTYPE DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Msk /*!< DESTRIGINTYPE[ 1:0] bits Destination Trigger Input Type:
+ - 00: Software only Trigger Request. DESTRIGINSEL is ignored.
+ - 01: Reserved
+ - 10: HW Trigger Request. Only allowed when HAS_TRIGIN is enabled. DESTRIGINSEL selects between external trigger inputs if HAS_TRIGSEL is enabled.
+ - 11: Internal Trigger Request. Only allowed when HAS_TRIGSEL is enabled and the DMAC has multiple channels, otherwise treated as HW Trigger Request. DESTRIGINSEL selects between DMA channels.
+Note: SW triggers are also available when HW or Internal types are selected, but is is not recommended and caution must be taken when the these modes are combined.*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_0 (0x1UL << DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_1 (0x2UL << DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Pos) /*!< 0x00000200UL*/
+
+#define DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Pos (10U)
+#define DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Msk (0x3UL << DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Pos) /*!< 0x00000C00UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINMODE DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Msk /*!< DESTRIGINMODE[ 1:0] bits Destination Trigger Input Mode:
+ - 00: Command
+ - 01: Reserved
+ - 10: DMA driven Flow control. Only allowed when HAS_TRIGIN is enabled.
+ - 11: Peripheral driven Flow control. Only allowed when HAS_TRIGIN is enabled.
+Note: This field is ignored for Internal triggers as they only support Command triggers.*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINMODE_0 (0x1UL << DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINMODE_1 (0x2UL << DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Pos) /*!< 0x00000800UL*/
+
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos (16U)
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Msk (0xFFUL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00FF0000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Msk /*!< DESTRIGINBLKSIZE[ 7:0] bits Destination Trigger Input Default Transfer Size. Defined transfer size per trigger + 1.*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_0 (0x1UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_1 (0x2UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_2 (0x4UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_3 (0x8UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_4 (0x10UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_5 (0x20UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_6 (0x40UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00400000UL*/
+#define DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_7 (0x80UL << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) /*!< 0x00800000UL*/
+
+
+/*************** Field definitions for CH_TRIGOUTCFG register ***************/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos (0U)
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Msk (0x3FUL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x0000003FUL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Msk /*!< TRIGOUTSEL[ 5:0] bits Trigger Output Select*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_0 (0x1UL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_1 (0x2UL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_2 (0x4UL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_3 (0x8UL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_4 (0x10UL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTSEL_5 (0x20UL << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) /*!< 0x00000020UL*/
+
+#define DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Pos (8U)
+#define DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Msk (0x3UL << DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Pos) /*!< 0x00000300UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTTYPE DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Msk /*!< TRIGOUTTYPE[ 1:0] bits Trigger Output Type
+ - 00: Software only Trigger Acknowledgement.
+ - 01: Reserved
+ - 10: HW Trigger Acknowledgement. Only allowed when HAS_TRIGOUT is enabled.
+ - 11: Internal Trigger Acknowledgement. Only allowed when HAS_TRIGSEL is enabled and the DMAC has multiple channels, otherwise treated as HW Trigger Acknowledgement.*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_0 (0x1UL << DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_1 (0x2UL << DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Pos) /*!< 0x00000200UL*/
+
+
+/***************** Field definitions for CH_GPOEN0 register *****************/
+#define DMA_CH_GPOEN0_GPOEN0_Pos (0U)
+#define DMA_CH_GPOEN0_GPOEN0_Msk (0xFFFFFFFFUL << DMA_CH_GPOEN0_GPOEN0_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_GPOEN0_GPOEN0 DMA_CH_GPOEN0_GPOEN0_Msk /*!< GPOEN0[31:0] bits Channel General Purpose Output (GPO) bit 0 to 31 enable mask. If bit n is '1', then GPO[n] is selected for driving by GPOVAL0[n]. If bit 'n' is '0', then GPO[n] keeps its previous value. Only [GPO_WIDTH-1:0] are implemented. All unimplemented bits are RAZWI.*/
+
+
+
+/**************** Field definitions for CH_GPOVAL0 register *****************/
+#define DMA_CH_GPOVAL0_GPOVAL0_Pos (0U)
+#define DMA_CH_GPOVAL0_GPOVAL0_Msk (0xFFFFFFFFUL << DMA_CH_GPOVAL0_GPOVAL0_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_GPOVAL0_GPOVAL0 DMA_CH_GPOVAL0_GPOVAL0_Msk /*!< GPOVAL0[31:0] bits General Purpose Output Value GPO[31:0]. Write to set output value. The actual value on the GPO port will become active when the command is enabled. Read returns the register value which might be different from the actual GPO port status. Only [GPO_WIDTH-1:0] are implemented. All unimplemented bits are RAZWI.*/
+
+
+
+/************** Field definitions for CH_STREAMINTCFG register **************/
+#define DMA_CH_STREAMINTCFG_STREAMTYPE_Pos (9U)
+#define DMA_CH_STREAMINTCFG_STREAMTYPE_Msk (0x3UL << DMA_CH_STREAMINTCFG_STREAMTYPE_Pos) /*!< 0x00000600UL*/
+#define DMA_CH_STREAMINTCFG_STREAMTYPE DMA_CH_STREAMINTCFG_STREAMTYPE_Msk /*!< STREAMTYPE[ 1:0] bits Stream Interface operation Type
+ - 00: Stream in and out used.
+ - 01: Stream out only
+ - 10: Stream in only
+ - 11: Reserved*/
+#define DMA_CH_STREAMINTCFG_STREAMTYPE_0 (0x1UL << DMA_CH_STREAMINTCFG_STREAMTYPE_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_STREAMINTCFG_STREAMTYPE_1 (0x2UL << DMA_CH_STREAMINTCFG_STREAMTYPE_Pos) /*!< 0x00000400UL*/
+
+
+
+/**************** Field definitions for CH_LINKATTR register ****************/
+#define DMA_CH_LINKATTR_LINKMEMATTRLO_Pos (0U)
+#define DMA_CH_LINKATTR_LINKMEMATTRLO_Msk (0xFUL << DMA_CH_LINKATTR_LINKMEMATTRLO_Pos) /*!< 0x0000000FUL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRLO DMA_CH_LINKATTR_LINKMEMATTRLO_Msk /*!< LINKMEMATTRLO[ 3:0] bits Link Address Read Transfer Memory Attribute field [3:0].
+When LINKMEMATTRHI is Device type (0000) then this field means:
+ - 0000: Device-nGnRnE
+ - 0100: Device-nGnRE
+ - 1000: Device-nGRE
+ - 1100: Device-GRE
+ - Others: Invalid resulting in UNPREDICTABLE behavior
+When LINKMEMATTRHI is Normal memory type (other than 0000) then this field means:
+ - 0000: Reserved
+ - 0001: Normal memory, Inner Write allocate, Inner Write-through transient
+ - 0010: Normal memory, Inner Read allocate, Inner Write-through transient
+ - 0011: Normal memory, Inner Read/Write allocate, Inner Write-through transient
+ - 0100: Normal memory, Inner non-cacheable
+ - 0101: Normal memory, Inner Write allocate, Inner Write-back transient
+ - 0110: Normal memory, Inner Read allocate, Inner Write-back transient
+ - 0111: Normal memory, Inner Read/Write allocate, Inner Write-back transient
+ - 1000: Normal memory, Inner Write-through non-transient
+ - 1001: Normal memory, Inner Write allocate, Inner Write-through non-transient
+ - 1010: Normal memory, Inner Read allocate, Inner Write-through non-transient
+ - 1011: Normal memory, Inner Read/Write allocate, Inner Write-through non-transient
+ - 1100: Normal memory, Inner Write-back non-transient
+ - 1101: Normal memory, Inner Write allocate, Inner Write-back non-transient
+ - 1110: Normal memory, Inner Read allocate, Inner Write-back non-transient
+ - 1111: Normal memory, Inner Read/Write allocate, Inner Write-back non-transient*/
+#define DMA_CH_LINKATTR_LINKMEMATTRLO_0 (0x1UL << DMA_CH_LINKATTR_LINKMEMATTRLO_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRLO_1 (0x2UL << DMA_CH_LINKATTR_LINKMEMATTRLO_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRLO_2 (0x4UL << DMA_CH_LINKATTR_LINKMEMATTRLO_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRLO_3 (0x8UL << DMA_CH_LINKATTR_LINKMEMATTRLO_Pos) /*!< 0x00000008UL*/
+
+#define DMA_CH_LINKATTR_LINKMEMATTRHI_Pos (4U)
+#define DMA_CH_LINKATTR_LINKMEMATTRHI_Msk (0xFUL << DMA_CH_LINKATTR_LINKMEMATTRHI_Pos) /*!< 0x000000F0UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRHI DMA_CH_LINKATTR_LINKMEMATTRHI_Msk /*!< LINKMEMATTRHI[ 3:0] bits Link Address Read Transfer Memory Attribute field [7:4].
+ - 0000: Device memory
+ - 0001: Normal memory, Outer Write allocate, Outer Write-through transient
+ - 0010: Normal memory, Outer Read allocate, Outer Write-through transient
+ - 0011: Normal memory, Outer Read/Write allocate, Outer Write-through transient
+ - 0100: Normal memory, Outer non-cacheable
+ - 0101: Normal memory, Outer Write allocate, Outer Write-back transient
+ - 0110: Normal memory, Outer Read allocate, Outer Write-back transient
+ - 0111: Normal memory, Outer Read/Write allocate, Outer Write-back transient
+ - 1000: Normal memory, Outer Write-through non-transient
+ - 1001: Normal memory, Outer Write allocate, Outer Write-through non-transient
+ - 1010: Normal memory, Outer Read allocate, Outer Write-through non-transient
+ - 1011: Normal memory, Outer Read/Write allocate, Outer Write-through non-transient
+ - 1100: Normal memory, Outer Write-back non-transient
+ - 1101: Normal memory, Outer Write allocate, Outer Write-back non-transient
+ - 1110: Normal memory, Outer Read allocate, Outer Write-back non-transient
+ - 1111: Normal memory, Outer Read/Write allocate, Outer Write-back non-transient*/
+#define DMA_CH_LINKATTR_LINKMEMATTRHI_0 (0x1UL << DMA_CH_LINKATTR_LINKMEMATTRHI_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRHI_1 (0x2UL << DMA_CH_LINKATTR_LINKMEMATTRHI_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRHI_2 (0x4UL << DMA_CH_LINKATTR_LINKMEMATTRHI_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_LINKATTR_LINKMEMATTRHI_3 (0x8UL << DMA_CH_LINKATTR_LINKMEMATTRHI_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_LINKATTR_LINKSHAREATTR_Pos (8U)
+#define DMA_CH_LINKATTR_LINKSHAREATTR_Msk (0x3UL << DMA_CH_LINKATTR_LINKSHAREATTR_Pos) /*!< 0x00000300UL*/
+#define DMA_CH_LINKATTR_LINKSHAREATTR DMA_CH_LINKATTR_LINKSHAREATTR_Msk /*!< LINKSHAREATTR[ 1:0] bits Link Address Transfer Shareability Attribute.
+ - 00: Non-shareable
+ - 01: Reserved
+ - 10: Outer shareable
+ - 11: Inner shareable */
+#define DMA_CH_LINKATTR_LINKSHAREATTR_0 (0x1UL << DMA_CH_LINKATTR_LINKSHAREATTR_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_LINKATTR_LINKSHAREATTR_1 (0x2UL << DMA_CH_LINKATTR_LINKSHAREATTR_Pos) /*!< 0x00000200UL*/
+
+
+/**************** Field definitions for CH_AUTOCFG register *****************/
+#define DMA_CH_AUTOCFG_CMDRESTARTCNT_Pos (0U)
+#define DMA_CH_AUTOCFG_CMDRESTARTCNT_Msk (0xFFFFUL << DMA_CH_AUTOCFG_CMDRESTARTCNT_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_CH_AUTOCFG_CMDRESTARTCNT DMA_CH_AUTOCFG_CMDRESTARTCNT_Msk /*!< CMDRESTARTCNT[15:0] bits Automatic Command Restart Counter. Defines the number of times automatic restarting will occur at end of DMA command. Auto restarting will occur after the command is completed, including output triggering if enabled and autoreloading the registers, but it will only perfrom a link to the next command when CMDRESTARTCNT == 0. When CMDRESTARTCNT and CMDRESTARTINF are both set to '0', autorestart is disabled.*/
+
+#define DMA_CH_AUTOCFG_CMDRESTARTINFEN_Pos (16U)
+#define DMA_CH_AUTOCFG_CMDRESTARTINFEN_Msk (0x1UL << DMA_CH_AUTOCFG_CMDRESTARTINFEN_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_AUTOCFG_CMDRESTARTINFEN DMA_CH_AUTOCFG_CMDRESTARTINFEN_Msk /*!< CMDRESTARTINFEN bit Enable Infinite Automatic Command Restart. When set, CMDRESTARTCNT is ignored and the command is always restarted after it is completed, including output triggering if enabled and autoreloading the registers but it will not perform a link to the next command. This means that the infinite loop of automatic restarts can only be broken by DISABLECMD or STOPCMD. When CMDRESTARTINFEN is set to '0', then the autorestarting of a command depends on CMDRESTARTCNT and when that counter is set to 0 the autorestarting is finished. In this case the next linked command is read or the command is complete.*/
+
+/**************** Field definitions for CH_LINKADDR register ****************/
+#define DMA_CH_LINKADDR_LINKADDREN_Pos (0U)
+#define DMA_CH_LINKADDR_LINKADDREN_Msk (0x1UL << DMA_CH_LINKADDR_LINKADDREN_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_LINKADDR_LINKADDREN DMA_CH_LINKADDR_LINKADDREN_Msk /*!< LINKADDREN bit Enable Link Address. When set to '1', the DMAC fetches the next command defined by LINKADDR. When set to '0' the DMAC will return to idle at the end of the current command.
+
+NOTE: the linked command fetched by the DMAC needs to clear this field to mark the end of the command chain. Otherwise it may result in an infinite loop of the same command.
+*/
+#define DMA_CH_LINKADDR_LINKADDR_Pos (2U)
+#define DMA_CH_LINKADDR_LINKADDR_Msk (0x3FFFFFFFUL << DMA_CH_LINKADDR_LINKADDR_Pos) /*!< 0xFFFFFFFCUL*/
+#define DMA_CH_LINKADDR_LINKADDR DMA_CH_LINKADDR_LINKADDR_Msk /*!< LINKADDR[29:0] bits Link Address Pointer [31:2]. The DMAC fetches the next command from this address if LINKADDREN is set.
+NOTE: Commands are fetched with the security and privilege attribute of the channel and cannot be adjusted for the command link reads.
+*/
+
+
+/*************** Field definitions for CH_LINKADDRHI register ***************/
+#define DMA_CH_LINKADDRHI_LINKADDRHI_Pos (0U)
+#define DMA_CH_LINKADDRHI_LINKADDRHI_Msk (0xFFFFFFFFUL << DMA_CH_LINKADDRHI_LINKADDRHI_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_LINKADDRHI_LINKADDRHI DMA_CH_LINKADDRHI_LINKADDRHI_Msk /*!< LINKADDRHI[31:0] bits Link Address Pointer [63:32]. Allows 64-bit addressing but the system might need less address bits. Limited by ADDR_WIDTH and the not implemented bits remain reserved.*/
+
+
+/**************** Field definitions for CH_GPOREAD0 register ****************/
+#define DMA_CH_GPOREAD0_GPOREAD0_Pos (0U)
+#define DMA_CH_GPOREAD0_GPOREAD0_Msk (0xFFFFFFFFUL << DMA_CH_GPOREAD0_GPOREAD0_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_GPOREAD0_GPOREAD0 DMA_CH_GPOREAD0_GPOREAD0_Msk /*!< GPOREAD0[31:0] bits General Purpose Output Read Value for GPO[31:0]. Read returns the actual value of the GPO ports. Only [GPO_WIDTH-1:0] are implemented. All unimplemented bits are set to 0.*/
+
+
+
+/*************** Field definitions for CH_WRKREGPTR register ****************/
+#define DMA_CH_WRKREGPTR_WRKREGPTR_Pos (0U)
+#define DMA_CH_WRKREGPTR_WRKREGPTR_Msk (0xFUL << DMA_CH_WRKREGPTR_WRKREGPTR_Pos) /*!< 0x0000000FUL*/
+#define DMA_CH_WRKREGPTR_WRKREGPTR DMA_CH_WRKREGPTR_WRKREGPTR_Msk /*!< WRKREGPTR[ 3:0] bits Internal Working Register Pointer. These pointer refers to the following:
+ - 0: Reserved
+ - 1: SRCADDR_INITIAL
+ - 2: SRCADDRHI_INITIAL
+ - 3: DESADDR_INITIAL
+ - 4: DESADDRHI_INITIAL
+ - 5: SRCXSIZEHI_INITIAL, SRCXSIZE_INITIAL
+ - 6: DESXSIZEHI_INITIAL, DESXSIZE_INITIAL
+ - 7: SRCADDR_LINEINITIAL
+ - 8: SRCADDRHI_LINEINITIAL
+ - 9: DESADDR_LINEINITIAL
+ - 10: DESADDRHI_LINEINITIAL
+ - 11: SRCYSIZE_INITIAL (HAS_2D only)
+ - 12: DESYSIZE_INITIAL (HAS_2D only)
+ - Others: Reserved.
+NOTE: When the selected register is not supported by the DMA then it is read as 0 in the CH_WRKREGVAL register. For 1D modes the INITIAL and LINEINITIAL registers contain the same values.*/
+#define DMA_CH_WRKREGPTR_WRKREGPTR_0 (0x1UL << DMA_CH_WRKREGPTR_WRKREGPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_WRKREGPTR_WRKREGPTR_1 (0x2UL << DMA_CH_WRKREGPTR_WRKREGPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_WRKREGPTR_WRKREGPTR_2 (0x4UL << DMA_CH_WRKREGPTR_WRKREGPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_WRKREGPTR_WRKREGPTR_3 (0x8UL << DMA_CH_WRKREGPTR_WRKREGPTR_Pos) /*!< 0x00000008UL*/
+
+
+/*************** Field definitions for CH_WRKREGVAL register ****************/
+#define DMA_CH_WRKREGVAL_WRKREGVAL_Pos (0U)
+#define DMA_CH_WRKREGVAL_WRKREGVAL_Msk (0xFFFFFFFFUL << DMA_CH_WRKREGVAL_WRKREGVAL_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_CH_WRKREGVAL_WRKREGVAL DMA_CH_WRKREGVAL_WRKREGVAL_Msk /*!< WRKREGVAL[31:0] bits Internal Working Register Values. WRKREGPTR points to the register that is visible here. The values are only guaranteed to be stable for the current command when STAT_PAUSED is asserted, otherwise they depend on the current status of the channel which makes them UNPREDICTABLE.*/
+
+
+/**************** Field definitions for CH_ERRINFO register *****************/
+#define DMA_CH_ERRINFO_BUSERR_Pos (0U)
+#define DMA_CH_ERRINFO_BUSERR_Msk (0x1UL << DMA_CH_ERRINFO_BUSERR_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_ERRINFO_BUSERR DMA_CH_ERRINFO_BUSERR_Msk /*!< BUSERR bit Bus Error Flag. Set when the DMA encounters a bus error during data or command read transfers.*/
+#define DMA_CH_ERRINFO_CFGERR_Pos (1U)
+#define DMA_CH_ERRINFO_CFGERR_Msk (0x1UL << DMA_CH_ERRINFO_CFGERR_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_ERRINFO_CFGERR DMA_CH_ERRINFO_CFGERR_Msk /*!< CFGERR bit Configuration Error Flag. Set when the DMA command is enabled or a linked command is read but it is configured in a mode that is not supported by the implementation.*/
+#define DMA_CH_ERRINFO_SRCTRIGINSELERR_Pos (2U)
+#define DMA_CH_ERRINFO_SRCTRIGINSELERR_Msk (0x1UL << DMA_CH_ERRINFO_SRCTRIGINSELERR_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_ERRINFO_SRCTRIGINSELERR DMA_CH_ERRINFO_SRCTRIGINSELERR_Msk /*!< SRCTRIGINSELERR bit Source Trigger Input Selection Error Flag. Set when the command selects a source trigger input that is not allowed for this channel.*/
+#define DMA_CH_ERRINFO_DESTRIGINSELERR_Pos (3U)
+#define DMA_CH_ERRINFO_DESTRIGINSELERR_Msk (0x1UL << DMA_CH_ERRINFO_DESTRIGINSELERR_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_ERRINFO_DESTRIGINSELERR DMA_CH_ERRINFO_DESTRIGINSELERR_Msk /*!< DESTRIGINSELERR bit Destination Trigger Input Selection Error Flag. Set when the command selects a destination trigger input that is not allowed for this channel.*/
+#define DMA_CH_ERRINFO_TRIGOUTSELERR_Pos (4U)
+#define DMA_CH_ERRINFO_TRIGOUTSELERR_Msk (0x1UL << DMA_CH_ERRINFO_TRIGOUTSELERR_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_ERRINFO_TRIGOUTSELERR DMA_CH_ERRINFO_TRIGOUTSELERR_Msk /*!< TRIGOUTSELERR bit Trigger Output Selection Error Flag. Set when the command selects a trigger output that is not allowed for this channel.*/
+#define DMA_CH_ERRINFO_STREAMERR_Pos (7U)
+#define DMA_CH_ERRINFO_STREAMERR_Msk (0x1UL << DMA_CH_ERRINFO_STREAMERR_Pos) /*!< 0x00000080UL*/
+#define DMA_CH_ERRINFO_STREAMERR DMA_CH_ERRINFO_STREAMERR_Msk /*!< STREAMERR bit Stream Interface Error Flag. Set when the stream interface encountered an error.*/
+#define DMA_CH_ERRINFO_ERRINFO_Pos (16U)
+#define DMA_CH_ERRINFO_ERRINFO_Msk (0xFFFFUL << DMA_CH_ERRINFO_ERRINFO_Pos) /*!< 0xFFFF0000UL*/
+#define DMA_CH_ERRINFO_ERRINFO DMA_CH_ERRINFO_ERRINFO_Msk /*!< ERRINFO[15:0] bits Error information Register. Additional information for the error that is encountered by the DMA. The meaning of the bits are detailed in the Error Handling section.*/
+
+
+
+/****************** Field definitions for CH_IIDR register ******************/
+#define DMA_CH_IIDR_IMPLEMENTER_Pos (0U)
+#define DMA_CH_IIDR_IMPLEMENTER_Msk (0xFFFUL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000FFFUL*/
+#define DMA_CH_IIDR_IMPLEMENTER DMA_CH_IIDR_IMPLEMENTER_Msk /*!< IMPLEMENTER[11:0] bits Contains the JEP106 code of the company that implemented the IP:
+ - [11:8]: JEP106 continuation code of implementer.
+ - [7]: Always 0.
+ - [6:0]: JEP106 identity code of implementer.
+For Arm this field reads as 0x43B.*/
+#define DMA_CH_IIDR_IMPLEMENTER_0 (0x1UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_1 (0x2UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_2 (0x4UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_3 (0x8UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_4 (0x10UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_5 (0x20UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_6 (0x40UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_7 (0x80UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000080UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_8 (0x100UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_9 (0x200UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_10 (0x400UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_IIDR_IMPLEMENTER_11 (0x800UL << DMA_CH_IIDR_IMPLEMENTER_Pos) /*!< 0x00000800UL*/
+
+#define DMA_CH_IIDR_REVISION_Pos (12U)
+#define DMA_CH_IIDR_REVISION_Msk (0xFUL << DMA_CH_IIDR_REVISION_Pos) /*!< 0x0000F000UL*/
+#define DMA_CH_IIDR_REVISION DMA_CH_IIDR_REVISION_Msk /*!< REVISION[ 3:0] bits Indicates the minor revision of the product rxpy identifier*/
+#define DMA_CH_IIDR_REVISION_0 (0x1UL << DMA_CH_IIDR_REVISION_Pos) /*!< 0x00001000UL*/
+#define DMA_CH_IIDR_REVISION_1 (0x2UL << DMA_CH_IIDR_REVISION_Pos) /*!< 0x00002000UL*/
+#define DMA_CH_IIDR_REVISION_2 (0x4UL << DMA_CH_IIDR_REVISION_Pos) /*!< 0x00004000UL*/
+#define DMA_CH_IIDR_REVISION_3 (0x8UL << DMA_CH_IIDR_REVISION_Pos) /*!< 0x00008000UL*/
+
+#define DMA_CH_IIDR_VARIANT_Pos (16U)
+#define DMA_CH_IIDR_VARIANT_Msk (0xFUL << DMA_CH_IIDR_VARIANT_Pos) /*!< 0x000F0000UL*/
+#define DMA_CH_IIDR_VARIANT DMA_CH_IIDR_VARIANT_Msk /*!< VARIANT[ 3:0] bits Indicates the major revision, or variant, of the product rxpy identifier*/
+#define DMA_CH_IIDR_VARIANT_0 (0x1UL << DMA_CH_IIDR_VARIANT_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_IIDR_VARIANT_1 (0x2UL << DMA_CH_IIDR_VARIANT_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_IIDR_VARIANT_2 (0x4UL << DMA_CH_IIDR_VARIANT_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_IIDR_VARIANT_3 (0x8UL << DMA_CH_IIDR_VARIANT_Pos) /*!< 0x00080000UL*/
+
+#define DMA_CH_IIDR_PRODUCTID_Pos (20U)
+#define DMA_CH_IIDR_PRODUCTID_Msk (0xFFFUL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0xFFF00000UL*/
+#define DMA_CH_IIDR_PRODUCTID DMA_CH_IIDR_PRODUCTID_Msk /*!< PRODUCTID[11:0] bits Indicates the product ID*/
+#define DMA_CH_IIDR_PRODUCTID_0 (0x1UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_IIDR_PRODUCTID_1 (0x2UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_IIDR_PRODUCTID_2 (0x4UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x00400000UL*/
+#define DMA_CH_IIDR_PRODUCTID_3 (0x8UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x00800000UL*/
+#define DMA_CH_IIDR_PRODUCTID_4 (0x10UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x01000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_5 (0x20UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x02000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_6 (0x40UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x04000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_7 (0x80UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x08000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_8 (0x100UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x10000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_9 (0x200UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x20000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_10 (0x400UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x40000000UL*/
+#define DMA_CH_IIDR_PRODUCTID_11 (0x800UL << DMA_CH_IIDR_PRODUCTID_Pos) /*!< 0x80000000UL*/
+
+
+/****************** Field definitions for CH_AIDR register ******************/
+#define DMA_CH_AIDR_ARCH_MINOR_REV_Pos (0U)
+#define DMA_CH_AIDR_ARCH_MINOR_REV_Msk (0xFUL << DMA_CH_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x0000000FUL*/
+#define DMA_CH_AIDR_ARCH_MINOR_REV DMA_CH_AIDR_ARCH_MINOR_REV_Msk /*!< ARCH_MINOR_REV[ 3:0] bits Architecture Minor Revision.*/
+#define DMA_CH_AIDR_ARCH_MINOR_REV_0 (0x1UL << DMA_CH_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_AIDR_ARCH_MINOR_REV_1 (0x2UL << DMA_CH_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_AIDR_ARCH_MINOR_REV_2 (0x4UL << DMA_CH_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_AIDR_ARCH_MINOR_REV_3 (0x8UL << DMA_CH_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000008UL*/
+
+#define DMA_CH_AIDR_ARCH_MAJOR_REV_Pos (4U)
+#define DMA_CH_AIDR_ARCH_MAJOR_REV_Msk (0xFUL << DMA_CH_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x000000F0UL*/
+#define DMA_CH_AIDR_ARCH_MAJOR_REV DMA_CH_AIDR_ARCH_MAJOR_REV_Msk /*!< ARCH_MAJOR_REV[ 3:0] bits Architecture Major Revision.*/
+#define DMA_CH_AIDR_ARCH_MAJOR_REV_0 (0x1UL << DMA_CH_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_AIDR_ARCH_MAJOR_REV_1 (0x2UL << DMA_CH_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_AIDR_ARCH_MAJOR_REV_2 (0x4UL << DMA_CH_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_AIDR_ARCH_MAJOR_REV_3 (0x8UL << DMA_CH_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000080UL*/
+
+
+
+/**************** Field definitions for CH_ISSUECAP register ****************/
+#define DMA_CH_ISSUECAP_ISSUECAP_Pos (0U)
+#define DMA_CH_ISSUECAP_ISSUECAP_Msk (0x7UL << DMA_CH_ISSUECAP_ISSUECAP_Pos) /*!< 0x00000007UL*/
+#define DMA_CH_ISSUECAP_ISSUECAP DMA_CH_ISSUECAP_ISSUECAP_Msk /*!< ISSUECAP[ 2:0] bits ISSUECAP can be used by software to place a constraint on allowed issuing capability in both read and write direction.*/
+#define DMA_CH_ISSUECAP_ISSUECAP_0 (0x1UL << DMA_CH_ISSUECAP_ISSUECAP_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_ISSUECAP_ISSUECAP_1 (0x2UL << DMA_CH_ISSUECAP_ISSUECAP_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_ISSUECAP_ISSUECAP_2 (0x4UL << DMA_CH_ISSUECAP_ISSUECAP_Pos) /*!< 0x00000004UL*/
+
+
+
+/*************** Field definitions for CH_BUILDCFG0 register ****************/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos (0U)
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Msk (0xFFUL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x000000FFUL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Msk /*!< DATA_BUFF_SIZE[ 7:0] bits Data Buffer Size in entries - 1. Total Size = ((DATA_BUFF_SIZE + 1) * DATA_WIDTH /8) bytes.*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_0 (0x1UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_1 (0x2UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_2 (0x4UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_3 (0x8UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_4 (0x10UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_5 (0x20UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_6 (0x40UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_7 (0x80UL << DMA_CH_BUILDCFG0_DATA_BUFF_SIZE_Pos) /*!< 0x00000080UL*/
+
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos (8U)
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Msk (0xFFUL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x0000FF00UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Msk /*!< CMD_BUFF_SIZE[ 7:0] bits Command Buffer Size in command words - 1. Total Size = (CMD_BUFF_SIZE + 1) * 4 bytes.*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_0 (0x1UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_1 (0x2UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_2 (0x4UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_3 (0x8UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00000800UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_4 (0x10UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00001000UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_5 (0x20UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00002000UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_6 (0x40UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00004000UL*/
+#define DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_7 (0x80UL << DMA_CH_BUILDCFG0_CMD_BUFF_SIZE_Pos) /*!< 0x00008000UL*/
+
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos (16U)
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_Msk (0x3FUL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x003F0000UL*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH DMA_CH_BUILDCFG0_ADDR_WIDTH_Msk /*!< ADDR_WIDTH[ 5:0] bits Address Width in bits = ADDR_WIDTH + 1*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_0 (0x1UL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00010000UL*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_1 (0x2UL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00020000UL*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_2 (0x4UL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_3 (0x8UL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_4 (0x10UL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_BUILDCFG0_ADDR_WIDTH_5 (0x20UL << DMA_CH_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00200000UL*/
+
+#define DMA_CH_BUILDCFG0_DATA_WIDTH_Pos (22U)
+#define DMA_CH_BUILDCFG0_DATA_WIDTH_Msk (0x7UL << DMA_CH_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x01C00000UL*/
+#define DMA_CH_BUILDCFG0_DATA_WIDTH DMA_CH_BUILDCFG0_DATA_WIDTH_Msk /*!< DATA_WIDTH[ 2:0] bits Data Width.
+ - 000: 8-bit
+ - 001: 16-bit
+ - 010: 32-bit
+ - 011: 64-bit
+ - 100: 128-bit
+ - 101: 256-bit
+ - 110: 512-bit
+ - 111: 1024-bit*/
+#define DMA_CH_BUILDCFG0_DATA_WIDTH_0 (0x1UL << DMA_CH_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x00400000UL*/
+#define DMA_CH_BUILDCFG0_DATA_WIDTH_1 (0x2UL << DMA_CH_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x00800000UL*/
+#define DMA_CH_BUILDCFG0_DATA_WIDTH_2 (0x4UL << DMA_CH_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x01000000UL*/
+
+#define DMA_CH_BUILDCFG0_INC_WIDTH_Pos (26U)
+#define DMA_CH_BUILDCFG0_INC_WIDTH_Msk (0xFUL << DMA_CH_BUILDCFG0_INC_WIDTH_Pos) /*!< 0x3C000000UL*/
+#define DMA_CH_BUILDCFG0_INC_WIDTH DMA_CH_BUILDCFG0_INC_WIDTH_Msk /*!< INC_WIDTH[ 3:0] bits Width of the increment register = INC_WIDTH + 1.
+When set to 0, then only 0 and 1 can be set as an increment. When larger values are used, then negative increments can be set using 2's complement:
+INC_WIDTH = 0: 0..1
+INC_WIDTH = 1: -2..1
+INC_WIDTH = 2: -4..3
+INC_WIDTH = 3: -8..7
+…
+INC_WIDTH = 15: -32768..32767*/
+#define DMA_CH_BUILDCFG0_INC_WIDTH_0 (0x1UL << DMA_CH_BUILDCFG0_INC_WIDTH_Pos) /*!< 0x04000000UL*/
+#define DMA_CH_BUILDCFG0_INC_WIDTH_1 (0x2UL << DMA_CH_BUILDCFG0_INC_WIDTH_Pos) /*!< 0x08000000UL*/
+#define DMA_CH_BUILDCFG0_INC_WIDTH_2 (0x4UL << DMA_CH_BUILDCFG0_INC_WIDTH_Pos) /*!< 0x10000000UL*/
+#define DMA_CH_BUILDCFG0_INC_WIDTH_3 (0x8UL << DMA_CH_BUILDCFG0_INC_WIDTH_Pos) /*!< 0x20000000UL*/
+
+
+/*************** Field definitions for CH_BUILDCFG1 register ****************/
+#define DMA_CH_BUILDCFG1_HAS_XSIZEHI_Pos (0U)
+#define DMA_CH_BUILDCFG1_HAS_XSIZEHI_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_XSIZEHI_Pos) /*!< 0x00000001UL*/
+#define DMA_CH_BUILDCFG1_HAS_XSIZEHI DMA_CH_BUILDCFG1_HAS_XSIZEHI_Msk /*!< HAS_XSIZEHI bit Has 32-bit XSIZE counters.*/
+#define DMA_CH_BUILDCFG1_HAS_WRAP_Pos (1U)
+#define DMA_CH_BUILDCFG1_HAS_WRAP_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_WRAP_Pos) /*!< 0x00000002UL*/
+#define DMA_CH_BUILDCFG1_HAS_WRAP DMA_CH_BUILDCFG1_HAS_WRAP_Msk /*!< HAS_WRAP bit Has wrap capability.*/
+#define DMA_CH_BUILDCFG1_HAS_2D_Pos (2U)
+#define DMA_CH_BUILDCFG1_HAS_2D_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_2D_Pos) /*!< 0x00000004UL*/
+#define DMA_CH_BUILDCFG1_HAS_2D DMA_CH_BUILDCFG1_HAS_2D_Msk /*!< HAS_2D bit Has 2D capability.*/
+#define DMA_CH_BUILDCFG1_HAS_TMPLT_Pos (3U)
+#define DMA_CH_BUILDCFG1_HAS_TMPLT_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_TMPLT_Pos) /*!< 0x00000008UL*/
+#define DMA_CH_BUILDCFG1_HAS_TMPLT DMA_CH_BUILDCFG1_HAS_TMPLT_Msk /*!< HAS_TMPLT bit Has template based pack and unpack capability.*/
+#define DMA_CH_BUILDCFG1_HAS_TRIG_Pos (4U)
+#define DMA_CH_BUILDCFG1_HAS_TRIG_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_TRIG_Pos) /*!< 0x00000010UL*/
+#define DMA_CH_BUILDCFG1_HAS_TRIG DMA_CH_BUILDCFG1_HAS_TRIG_Msk /*!< HAS_TRIG bit Has trigger capability.*/
+#define DMA_CH_BUILDCFG1_HAS_TRIGIN_Pos (5U)
+#define DMA_CH_BUILDCFG1_HAS_TRIGIN_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_TRIGIN_Pos) /*!< 0x00000020UL*/
+#define DMA_CH_BUILDCFG1_HAS_TRIGIN DMA_CH_BUILDCFG1_HAS_TRIGIN_Msk /*!< HAS_TRIGIN bit Has hardware trigger input ports.*/
+#define DMA_CH_BUILDCFG1_HAS_TRIGOUT_Pos (6U)
+#define DMA_CH_BUILDCFG1_HAS_TRIGOUT_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_TRIGOUT_Pos) /*!< 0x00000040UL*/
+#define DMA_CH_BUILDCFG1_HAS_TRIGOUT DMA_CH_BUILDCFG1_HAS_TRIGOUT_Msk /*!< HAS_TRIGOUT bit Has hardware trigger output port.*/
+#define DMA_CH_BUILDCFG1_HAS_TRIGSEL_Pos (7U)
+#define DMA_CH_BUILDCFG1_HAS_TRIGSEL_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_TRIGSEL_Pos) /*!< 0x00000080UL*/
+#define DMA_CH_BUILDCFG1_HAS_TRIGSEL DMA_CH_BUILDCFG1_HAS_TRIGSEL_Msk /*!< HAS_TRIGSEL bit Has selectable triggers.*/
+#define DMA_CH_BUILDCFG1_HAS_CMDLINK_Pos (8U)
+#define DMA_CH_BUILDCFG1_HAS_CMDLINK_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_CMDLINK_Pos) /*!< 0x00000100UL*/
+#define DMA_CH_BUILDCFG1_HAS_CMDLINK DMA_CH_BUILDCFG1_HAS_CMDLINK_Msk /*!< HAS_CMDLINK bit Has command link list capability.*/
+#define DMA_CH_BUILDCFG1_HAS_AUTO_Pos (9U)
+#define DMA_CH_BUILDCFG1_HAS_AUTO_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_AUTO_Pos) /*!< 0x00000200UL*/
+#define DMA_CH_BUILDCFG1_HAS_AUTO DMA_CH_BUILDCFG1_HAS_AUTO_Msk /*!< HAS_AUTO bit Has automatic reload and restart capability.*/
+#define DMA_CH_BUILDCFG1_HAS_WRKREG_Pos (10U)
+#define DMA_CH_BUILDCFG1_HAS_WRKREG_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_WRKREG_Pos) /*!< 0x00000400UL*/
+#define DMA_CH_BUILDCFG1_HAS_WRKREG DMA_CH_BUILDCFG1_HAS_WRKREG_Msk /*!< HAS_WRKREG bit Has internal register view capability.*/
+#define DMA_CH_BUILDCFG1_HAS_STREAM_Pos (11U)
+#define DMA_CH_BUILDCFG1_HAS_STREAM_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_STREAM_Pos) /*!< 0x00000800UL*/
+#define DMA_CH_BUILDCFG1_HAS_STREAM DMA_CH_BUILDCFG1_HAS_STREAM_Msk /*!< HAS_STREAM bit Has stream interface support.*/
+#define DMA_CH_BUILDCFG1_HAS_STREAMSEL_Pos (12U)
+#define DMA_CH_BUILDCFG1_HAS_STREAMSEL_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_STREAMSEL_Pos) /*!< 0x00001000UL*/
+#define DMA_CH_BUILDCFG1_HAS_STREAMSEL DMA_CH_BUILDCFG1_HAS_STREAMSEL_Msk /*!< HAS_STREAMSEL bit Has selectable stream interfaces.*/
+#define DMA_CH_BUILDCFG1_HAS_GPOSEL_Pos (18U)
+#define DMA_CH_BUILDCFG1_HAS_GPOSEL_Msk (0x1UL << DMA_CH_BUILDCFG1_HAS_GPOSEL_Pos) /*!< 0x00040000UL*/
+#define DMA_CH_BUILDCFG1_HAS_GPOSEL DMA_CH_BUILDCFG1_HAS_GPOSEL_Msk /*!< HAS_GPOSEL bit Has shared GPO ports between channels.*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_Pos (19U)
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_Msk (0x7FUL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x03F80000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH DMA_CH_BUILDCFG1_GPO_WIDTH_Msk /*!< GPO_WIDTH[ 6:0] bits General Purpose Output Width. 0 to 64.*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_0 (0x1UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x00080000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_1 (0x2UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x00100000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_2 (0x4UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x00200000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_3 (0x8UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x00400000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_4 (0x10UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x00800000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_5 (0x20UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x01000000UL*/
+#define DMA_CH_BUILDCFG1_GPO_WIDTH_6 (0x40UL << DMA_CH_BUILDCFG1_GPO_WIDTH_Pos) /*!< 0x02000000UL*/
+
+/******************************************************************************/
+/* DMANSECCTRL */
+/******************************************************************************/
+
+
+/************ Field definitions for NSEC_CHINTRSTATUS0 register *************/
+#define DMA_NSEC_CHINTRSTATUS0_CHINTRSTATUS0_Pos (0U)
+#define DMA_NSEC_CHINTRSTATUS0_CHINTRSTATUS0_Msk (0xFFFFFFFFUL << DMA_NSEC_CHINTRSTATUS0_CHINTRSTATUS0_Pos)/*!< 0xFFFFFFFFUL*/
+#define DMA_NSEC_CHINTRSTATUS0_CHINTRSTATUS0 DMA_NSEC_CHINTRSTATUS0_CHINTRSTATUS0_Msk /*!< CHINTRSTATUS0[31:0] bits Collated Non-Secure Channel Interrupt flags for channel 0 to channel 31. Limited by NUM_CHANNELS, all unimplemented bits are reserved.*/
+
+
+
+/**************** Field definitions for NSEC_STATUS register ****************/
+#define DMA_NSEC_STATUS_INTR_ANYCHINTR_Pos (0U)
+#define DMA_NSEC_STATUS_INTR_ANYCHINTR_Msk (0x1UL << DMA_NSEC_STATUS_INTR_ANYCHINTR_Pos) /*!< 0x00000001UL*/
+#define DMA_NSEC_STATUS_INTR_ANYCHINTR DMA_NSEC_STATUS_INTR_ANYCHINTR_Msk /*!< INTR_ANYCHINTR bit Combined Non-Secure Channel Interrupt Flag. Set to '1' when any Non-secure channel has an interrupt request in CHINTRSTATUS0 and NSECCTRL.INTREN_ANYCHINTR = 1. Cleared automatically when the source of the channel interrupt is cleared.*/
+#define DMA_NSEC_STATUS_INTR_ALLCHIDLE_Pos (1U)
+#define DMA_NSEC_STATUS_INTR_ALLCHIDLE_Msk (0x1UL << DMA_NSEC_STATUS_INTR_ALLCHIDLE_Pos) /*!< 0x00000002UL*/
+#define DMA_NSEC_STATUS_INTR_ALLCHIDLE DMA_NSEC_STATUS_INTR_ALLCHIDLE_Msk /*!< INTR_ALLCHIDLE bit All Non-Secure Channel Idle Interrupt Status. Set to '1' when NSECCTRL.STAT_ALLCHIDLE is asserted and NSECCTRL.INTREN_ALLCHIDLE = 1. Cleared automatically when STAT_ALLCHIDLE is cleared.*/
+#define DMA_NSEC_STATUS_INTR_ALLCHSTOPPED_Pos (2U)
+#define DMA_NSEC_STATUS_INTR_ALLCHSTOPPED_Msk (0x1UL << DMA_NSEC_STATUS_INTR_ALLCHSTOPPED_Pos) /*!< 0x00000004UL*/
+#define DMA_NSEC_STATUS_INTR_ALLCHSTOPPED DMA_NSEC_STATUS_INTR_ALLCHSTOPPED_Msk /*!< INTR_ALLCHSTOPPED bit All Non-Secure Channel Stopped Interrupt Status. Set to '1' when NSECCTRL.STAT_ALLCHSTOPPED is asserted and NSECCTRL.INTREN_ALLCHSTOPPED = 1. Cleared automatically when STAT_ALLCHSTOPPED is cleared.*/
+#define DMA_NSEC_STATUS_INTR_ALLCHPAUSED_Pos (3U)
+#define DMA_NSEC_STATUS_INTR_ALLCHPAUSED_Msk (0x1UL << DMA_NSEC_STATUS_INTR_ALLCHPAUSED_Pos) /*!< 0x00000008UL*/
+#define DMA_NSEC_STATUS_INTR_ALLCHPAUSED DMA_NSEC_STATUS_INTR_ALLCHPAUSED_Msk /*!< INTR_ALLCHPAUSED bit All Non-Secure Channel Paused Interrupt Status. Set to '1' when NSECCTRL.STAT_ALLCHPAUSED is asserted and NSECCTRL.INTREN_ALLCHPAUSED = 1. Cleared automatically when STAT_ALLCHPAUSED is cleared.*/
+#define DMA_NSEC_STATUS_STAT_ALLCHIDLE_Pos (17U)
+#define DMA_NSEC_STATUS_STAT_ALLCHIDLE_Msk (0x1UL << DMA_NSEC_STATUS_STAT_ALLCHIDLE_Pos) /*!< 0x00020000UL*/
+#define DMA_NSEC_STATUS_STAT_ALLCHIDLE DMA_NSEC_STATUS_STAT_ALLCHIDLE_Msk /*!< STAT_ALLCHIDLE bit All Non-Secure Channel Idle Status. Set to '1' whenever all Non-secure DMA channel is in idle state after at least one channel was running. Cleared by writing '1' to this bit.*/
+#define DMA_NSEC_STATUS_STAT_ALLCHSTOPPED_Pos (18U)
+#define DMA_NSEC_STATUS_STAT_ALLCHSTOPPED_Msk (0x1UL << DMA_NSEC_STATUS_STAT_ALLCHSTOPPED_Pos) /*!< 0x00040000UL*/
+#define DMA_NSEC_STATUS_STAT_ALLCHSTOPPED DMA_NSEC_STATUS_STAT_ALLCHSTOPPED_Msk /*!< STAT_ALLCHSTOPPED bit All Non-Secure Channel Stopped Status. Set to '1' whenever all Non-secure DMA channels are in stopped or inactive state and the ALLCHSTOP request is active. Not set when channels reach the stopped state for other reasons. All Non-secure channels are forced to an immediate stopped state until ALLCHSTOP request is asserted even if they were enabled after the request. Cleared by writing '1' to this bit. The ALLCHSTOP request is also cleared when this bit is cleared.*/
+#define DMA_NSEC_STATUS_STAT_ALLCHPAUSED_Pos (19U)
+#define DMA_NSEC_STATUS_STAT_ALLCHPAUSED_Msk (0x1UL << DMA_NSEC_STATUS_STAT_ALLCHPAUSED_Pos) /*!< 0x00080000UL*/
+#define DMA_NSEC_STATUS_STAT_ALLCHPAUSED DMA_NSEC_STATUS_STAT_ALLCHPAUSED_Msk /*!< STAT_ALLCHPAUSED bit All Non-Secure Channel Paused Status. Set to '1' whenever all Non-secure DMA channel is in paused or inactive state and the ALLCHPAUSE request is active. Not set when channels reach the paused state for other reasons. All Non-secure channels are forced to an immediate pause until ALLCHPAUSE request is asserted even if they were enabled after the request. Cleared by writing '1' to this bit which results in all Non-secure channels to resume their operation. The ALLCHPAUSE request is also cleared when this bit is cleared.*/
+
+/***************** Field definitions for NSEC_CTRL register *****************/
+#define DMA_NSEC_CTRL_INTREN_ANYCHINTR_Pos (0U)
+#define DMA_NSEC_CTRL_INTREN_ANYCHINTR_Msk (0x1UL << DMA_NSEC_CTRL_INTREN_ANYCHINTR_Pos) /*!< 0x00000001UL*/
+#define DMA_NSEC_CTRL_INTREN_ANYCHINTR DMA_NSEC_CTRL_INTREN_ANYCHINTR_Msk /*!< INTREN_ANYCHINTR bit Combined Non-Secure Channel Interrupt Enable*/
+#define DMA_NSEC_CTRL_INTREN_ALLCHIDLE_Pos (1U)
+#define DMA_NSEC_CTRL_INTREN_ALLCHIDLE_Msk (0x1UL << DMA_NSEC_CTRL_INTREN_ALLCHIDLE_Pos) /*!< 0x00000002UL*/
+#define DMA_NSEC_CTRL_INTREN_ALLCHIDLE DMA_NSEC_CTRL_INTREN_ALLCHIDLE_Msk /*!< INTREN_ALLCHIDLE bit All Non-Secure Channel Idle Interrupt Enable*/
+#define DMA_NSEC_CTRL_INTREN_ALLCHSTOPPED_Pos (2U)
+#define DMA_NSEC_CTRL_INTREN_ALLCHSTOPPED_Msk (0x1UL << DMA_NSEC_CTRL_INTREN_ALLCHSTOPPED_Pos) /*!< 0x00000004UL*/
+#define DMA_NSEC_CTRL_INTREN_ALLCHSTOPPED DMA_NSEC_CTRL_INTREN_ALLCHSTOPPED_Msk /*!< INTREN_ALLCHSTOPPED bit All Non-Secure Channels Stopped Interrupt Enable*/
+#define DMA_NSEC_CTRL_INTREN_ALLCHPAUSED_Pos (3U)
+#define DMA_NSEC_CTRL_INTREN_ALLCHPAUSED_Msk (0x1UL << DMA_NSEC_CTRL_INTREN_ALLCHPAUSED_Pos) /*!< 0x00000008UL*/
+#define DMA_NSEC_CTRL_INTREN_ALLCHPAUSED DMA_NSEC_CTRL_INTREN_ALLCHPAUSED_Msk /*!< INTREN_ALLCHPAUSED bit All Non-Secure Channel Paused Interrupt Enable*/
+#define DMA_NSEC_CTRL_ALLCHSTOP_Pos (8U)
+#define DMA_NSEC_CTRL_ALLCHSTOP_Msk (0x1UL << DMA_NSEC_CTRL_ALLCHSTOP_Pos) /*!< 0x00000100UL*/
+#define DMA_NSEC_CTRL_ALLCHSTOP DMA_NSEC_CTRL_ALLCHSTOP_Msk /*!< ALLCHSTOP bit Non-Secure All Channel Stop Request. When set to '1', all Non-secure channels get a stop request. Stays asserted until the STAT_ALLCHSTOPPED status flag is set. Cleared automatically when the STAT_ALLCHSTOPPED status flag is cleared.*/
+#define DMA_NSEC_CTRL_ALLCHPAUSE_Pos (9U)
+#define DMA_NSEC_CTRL_ALLCHPAUSE_Msk (0x1UL << DMA_NSEC_CTRL_ALLCHPAUSE_Pos) /*!< 0x00000200UL*/
+#define DMA_NSEC_CTRL_ALLCHPAUSE DMA_NSEC_CTRL_ALLCHPAUSE_Msk /*!< ALLCHPAUSE bit Non-Secure All Channel Pause Request. When set to '1', all Non-secure channels get a pause request. Stays asserted until the channels are paused and the STAT_ALLCHPAUSED status flag is set. Cleared automatically when the STAT_ALLCHPAUSED status flag is cleared.*/
+#define DMA_NSEC_CTRL_DBGHALTNSRO_Pos (27U)
+#define DMA_NSEC_CTRL_DBGHALTNSRO_Msk (0x1UL << DMA_NSEC_CTRL_DBGHALTNSRO_Pos) /*!< 0x08000000UL*/
+#define DMA_NSEC_CTRL_DBGHALTNSRO DMA_NSEC_CTRL_DBGHALTNSRO_Msk /*!< DBGHALTNSRO bit Debug Halt Enable Non-Secure Read Only. When set to '1', the NSEC_CTRL.DBGHALTEN register becomes read-only. When set to '0', NSEC_CTRL.DBGHALTEN has read-write access. This register is read-only for the non-secure SW.*/
+#define DMA_NSEC_CTRL_DBGHALTEN_Pos (28U)
+#define DMA_NSEC_CTRL_DBGHALTEN_Msk (0x1UL << DMA_NSEC_CTRL_DBGHALTEN_Pos) /*!< 0x10000000UL*/
+#define DMA_NSEC_CTRL_DBGHALTEN DMA_NSEC_CTRL_DBGHALTEN_Msk /*!< DBGHALTEN bit Debug Halt Enabled. When set to '0', the DMA ignores the halt request from an external debugger. Clearing this bit while halt is ongoing results in continuing the operation. When set to '1', the debugger request to halt the DMA is allowed. This field is common for non-secure and secure side of the DMA, but access to this register is limited by the DBGHALTNSRO register field.*/
+#define DMA_NSEC_CTRL_IDLERETEN_Pos (29U)
+#define DMA_NSEC_CTRL_IDLERETEN_Msk (0x1UL << DMA_NSEC_CTRL_IDLERETEN_Pos) /*!< 0x20000000UL*/
+#define DMA_NSEC_CTRL_IDLERETEN DMA_NSEC_CTRL_IDLERETEN_Msk /*!< IDLERETEN bit Idle Channel Retention Enable. Allows retention for non-secure channels that are enabled and waiting for an event in IDLE state.
+ - 0: disabled
+ - 1: enabled*/
+#define DMA_NSEC_CTRL_DISMINPWR_Pos (30U)
+#define DMA_NSEC_CTRL_DISMINPWR_Msk (0x3UL << DMA_NSEC_CTRL_DISMINPWR_Pos) /*!< 0xC0000000UL*/
+#define DMA_NSEC_CTRL_DISMINPWR DMA_NSEC_CTRL_DISMINPWR_Msk /*!< DISMINPWR[ 1:0] bits Minimum Power state of the DMAC when at least one non-secure channel is present.
+ - 00: OFF
+ - 01: Retention
+ - 10: ON
+ - Others: Reserved*/
+#define DMA_NSEC_CTRL_DISMINPWR_0 (0x1UL << DMA_NSEC_CTRL_DISMINPWR_Pos) /*!< 0x40000000UL*/
+#define DMA_NSEC_CTRL_DISMINPWR_1 (0x2UL << DMA_NSEC_CTRL_DISMINPWR_Pos) /*!< 0x80000000UL*/
+
+
+
+/**************** Field definitions for NSEC_CHPTR register *****************/
+#define DMA_NSEC_CHPTR_CHPTR_Pos (0U)
+#define DMA_NSEC_CHPTR_CHPTR_Msk (0x3FUL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x0000003FUL*/
+#define DMA_NSEC_CHPTR_CHPTR DMA_NSEC_CHPTR_CHPTR_Msk /*!< CHPTR[ 5:0] bits Non-Secure Channel Pointer. Selects which channel settings can be adjusted by the following registers.*/
+#define DMA_NSEC_CHPTR_CHPTR_0 (0x1UL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_NSEC_CHPTR_CHPTR_1 (0x2UL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_NSEC_CHPTR_CHPTR_2 (0x4UL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_NSEC_CHPTR_CHPTR_3 (0x8UL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x00000008UL*/
+#define DMA_NSEC_CHPTR_CHPTR_4 (0x10UL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x00000010UL*/
+#define DMA_NSEC_CHPTR_CHPTR_5 (0x20UL << DMA_NSEC_CHPTR_CHPTR_Pos) /*!< 0x00000020UL*/
+
+
+/**************** Field definitions for NSEC_CHCFG register *****************/
+#define DMA_NSEC_CHCFG_CHID_Pos (0U)
+#define DMA_NSEC_CHCFG_CHID_Msk (0xFFFFUL << DMA_NSEC_CHCFG_CHID_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_NSEC_CHCFG_CHID DMA_NSEC_CHCFG_CHID_Msk /*!< CHID[15:0] bits Non-Secure Channel ID value. NSECCHPTR selects the channel ID value to be read or written via this register. CHID_WIDTH limits this field, unused bits are RAZWI.*/
+
+#define DMA_NSEC_CHCFG_CHIDVLD_Pos (16U)
+#define DMA_NSEC_CHCFG_CHIDVLD_Msk (0x1UL << DMA_NSEC_CHCFG_CHIDVLD_Pos) /*!< 0x00010000UL*/
+#define DMA_NSEC_CHCFG_CHIDVLD DMA_NSEC_CHCFG_CHIDVLD_Msk /*!< CHIDVLD bit Non-Secure Channel ID valid. NSECCHPTR selects the channel. Set to '1' to drive the channel ID value in CHID for all the transfers by the selected channel.*/
+#define DMA_NSEC_CHCFG_CHPRIV_Pos (17U)
+#define DMA_NSEC_CHCFG_CHPRIV_Msk (0x1UL << DMA_NSEC_CHCFG_CHPRIV_Pos) /*!< 0x00020000UL*/
+#define DMA_NSEC_CHCFG_CHPRIV DMA_NSEC_CHCFG_CHPRIV_Msk /*!< CHPRIV bit Non-Secure Channel Privilege Enable. NSECCHPTR selects the channel. When set to '1' it allows the channel to send transfers marked as Privileged only. The configuration registers of the selected channel are also given privileged only access rights. When set to '0' the channel is only allowed to send unprivileged transfers and the channel registers can be accessed by both privileged and unprivileged register accesses.*/
+
+
+/************** Field definitions for NSEC_STATUSPTR register ***************/
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Pos (0U)
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Msk (0xFUL << DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Pos) /*!< 0x0000000FUL*/
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Msk /*!< NSECSTATUSPTR[ 3:0] bits Non-Secure DMA Unit status pointer used to select which status value to view using STATUSVALUE register. Pointer values are:
+ - 0: Channel Enabled Status for channel numbers [31 : 0].
+ - 1: Reserved
+ - 2: Channel Stopped Status for channel numbers [31 : 0].
+ - 3: Reserved
+ - 4: Channel Paused Status for channel numbers [31 : 0].
+ - Others: Reserved.*/
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR_0 (0x1UL << DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR_1 (0x2UL << DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR_2 (0x4UL << DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_NSEC_STATUSPTR_NSECSTATUSPTR_3 (0x8UL << DMA_NSEC_STATUSPTR_NSECSTATUSPTR_Pos) /*!< 0x00000008UL*/
+
+
+/************** Field definitions for NSEC_STATUSVAL register ***************/
+#define DMA_NSEC_STATUSVAL_NSECSTATUSVAL_Pos (0U)
+#define DMA_NSEC_STATUSVAL_NSECSTATUSVAL_Msk (0xFFFFFFFFUL << DMA_NSEC_STATUSVAL_NSECSTATUSVAL_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_NSEC_STATUSVAL_NSECSTATUSVAL DMA_NSEC_STATUSVAL_NSECSTATUSVAL_Msk /*!< NSECSTATUSVAL[31:0] bits Non-Secure DMA Unit status value. Can be used for reading internal status values of the DMA Unit for debug purposes. Values shown here are dependent on STATUSPTR. Note that inputs are masked by security mapping before being presented here. This means that only status values mapped to Non-secure world are visible as non-Zero values.
+All unimplemented bits are RAZWI. */
+
+
+/************** Field definitions for NSEC_SIGNALPTR register ***************/
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Pos (0U)
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Msk (0xFUL << DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Pos) /*!< 0x0000000FUL*/
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Msk /*!< NSECSIGNALPTR[ 3:0] bits Non-Secure DMA Unit signal pointer used to select which inputs or outputs to view using SIGNALVAL register. Pointer values, x, are:
+ - 0 to 7: Trigger Input Requests [31+32*x : 32*x]
+ - 8 to 9: Trigger output Acknowledges [31+32*(x-8) : 32*(x-8)]
+ - 10 to 11: GPO output value [31+32*(x-10) : 32*(x-10)], only present when HAS_GPOSEL is set
+ - Others: Reserved*/
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_0 (0x1UL << DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_1 (0x2UL << DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_2 (0x4UL << DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_3 (0x8UL << DMA_NSEC_SIGNALPTR_NSECSIGNALPTR_Pos) /*!< 0x00000008UL*/
+
+
+/************** Field definitions for NSEC_SIGNALVAL register ***************/
+#define DMA_NSEC_SIGNALVAL_NSECSIGNALVAL_Pos (0U)
+#define DMA_NSEC_SIGNALVAL_NSECSIGNALVAL_Msk (0xFFFFFFFFUL << DMA_NSEC_SIGNALVAL_NSECSIGNALVAL_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_NSEC_SIGNALVAL_NSECSIGNALVAL DMA_NSEC_SIGNALVAL_NSECSIGNALVAL_Msk /*!< NSECSIGNALVAL[31:0] bits Non-Secure DMA Unit signal status. Can be used for reading signal values of triggers and GPOs for debug. Values shown here are dependent on SIGNALPTR. Note that inputs are masked by security mapping before being presented here. This means that only signals mapped to Non-secure world are visible as non-zero values. Writing to this register has the following effect:
+ - Writing '1' to a Non-secure Trigger Input Request that are not selected by any DMA channel will cause a deny response for it. This can attempt to clear an unwanted trigger input.
+ - Writing '1' to any Trigger Output Acknowledges status, GPO status and all Trigger Input Request already selected by any DMA channel is ignored.
+All unimplemented bits are RAZWI. */
+
+/******************************************************************************/
+/* DMASECCTRL */
+/******************************************************************************/
+
+
+/************* Field definitions for SEC_CHINTRSTATUS0 register *************/
+#define DMA_SEC_CHINTRSTATUS0_CHINTRSTATUS0_Pos (0U)
+#define DMA_SEC_CHINTRSTATUS0_CHINTRSTATUS0_Msk (0xFFFFFFFFUL << DMA_SEC_CHINTRSTATUS0_CHINTRSTATUS0_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_SEC_CHINTRSTATUS0_CHINTRSTATUS0 DMA_SEC_CHINTRSTATUS0_CHINTRSTATUS0_Msk /*!< CHINTRSTATUS0[31:0] bits Collated Secure Channel Interrupt flags for channel 0 to Channel 31. Limited by NUM_CHANNELS, all unimplemented bits are reserved.*/
+
+
+
+/**************** Field definitions for SEC_STATUS register *****************/
+#define DMA_SEC_STATUS_INTR_ANYCHINTR_Pos (0U)
+#define DMA_SEC_STATUS_INTR_ANYCHINTR_Msk (0x1UL << DMA_SEC_STATUS_INTR_ANYCHINTR_Pos) /*!< 0x00000001UL*/
+#define DMA_SEC_STATUS_INTR_ANYCHINTR DMA_SEC_STATUS_INTR_ANYCHINTR_Msk /*!< INTR_ANYCHINTR bit Combined Secure Channel Interrupt Flag. Set to '1' when any Secure channel has an interrupt request in CHINTRSTATUS0 and SECCTRL.INTREN_ANYCHINTR = 1. Cleared automatically when the source of the channel interrupt is cleared.*/
+#define DMA_SEC_STATUS_INTR_ALLCHIDLE_Pos (1U)
+#define DMA_SEC_STATUS_INTR_ALLCHIDLE_Msk (0x1UL << DMA_SEC_STATUS_INTR_ALLCHIDLE_Pos) /*!< 0x00000002UL*/
+#define DMA_SEC_STATUS_INTR_ALLCHIDLE DMA_SEC_STATUS_INTR_ALLCHIDLE_Msk /*!< INTR_ALLCHIDLE bit All Secure Channel Idle Interrupt Status. Set to '1' when SECCTRL.STAT_ALLCHIDLE is asserted and SECCTRL.INTREN_ALLCHIDLE = 1. Cleared automatically when STAT_ALLCHIDLE is cleared.*/
+#define DMA_SEC_STATUS_INTR_ALLCHSTOPPED_Pos (2U)
+#define DMA_SEC_STATUS_INTR_ALLCHSTOPPED_Msk (0x1UL << DMA_SEC_STATUS_INTR_ALLCHSTOPPED_Pos) /*!< 0x00000004UL*/
+#define DMA_SEC_STATUS_INTR_ALLCHSTOPPED DMA_SEC_STATUS_INTR_ALLCHSTOPPED_Msk /*!< INTR_ALLCHSTOPPED bit All Secure Channel Stopped Interrupt Status. Set to '1' when SECCTRL.STAT_ALLCHSTOPPED is asserted and SECCTRL.INTREN_ALLCHSTOPPED = 1. Cleared automatically when STAT_ALLCHSTOPPED is cleared.*/
+#define DMA_SEC_STATUS_INTR_ALLCHPAUSED_Pos (3U)
+#define DMA_SEC_STATUS_INTR_ALLCHPAUSED_Msk (0x1UL << DMA_SEC_STATUS_INTR_ALLCHPAUSED_Pos) /*!< 0x00000008UL*/
+#define DMA_SEC_STATUS_INTR_ALLCHPAUSED DMA_SEC_STATUS_INTR_ALLCHPAUSED_Msk /*!< INTR_ALLCHPAUSED bit All Secure Channel Paused Interrupt Status. Set to '1' when SECCTRL.STAT_ALLCHPAUSED is asserted and SECCTRL.INTREN_ALLCHPAUSED = 1. Cleared automatically when STAT_ALLCHPAUSED is cleared.*/
+#define DMA_SEC_STATUS_STAT_ALLCHIDLE_Pos (17U)
+#define DMA_SEC_STATUS_STAT_ALLCHIDLE_Msk (0x1UL << DMA_SEC_STATUS_STAT_ALLCHIDLE_Pos) /*!< 0x00020000UL*/
+#define DMA_SEC_STATUS_STAT_ALLCHIDLE DMA_SEC_STATUS_STAT_ALLCHIDLE_Msk /*!< STAT_ALLCHIDLE bit All Secure Channel Idle Status. Set to '1' whenever all Secure DMA channel is in idle state after at least one channel was running. Cleared by writing '1' to this bit.*/
+#define DMA_SEC_STATUS_STAT_ALLCHSTOPPED_Pos (18U)
+#define DMA_SEC_STATUS_STAT_ALLCHSTOPPED_Msk (0x1UL << DMA_SEC_STATUS_STAT_ALLCHSTOPPED_Pos) /*!< 0x00040000UL*/
+#define DMA_SEC_STATUS_STAT_ALLCHSTOPPED DMA_SEC_STATUS_STAT_ALLCHSTOPPED_Msk /*!< STAT_ALLCHSTOPPED bit All Secure Channel Stopped Status. Set to '1' whenever all Secure DMA channels are in stopped or inactive state and the ALLCHSTOP request is active. Not set when channels reach the stopped state for other reasons. All Secure channels are forced to an immediate stopped state until ALLCHSTOP request is asserted even if they were enabled after the request. Cleared by writing '1' to this bit. The ALLCHSTOP request is also cleared when this bit is cleared.*/
+#define DMA_SEC_STATUS_STAT_ALLCHPAUSED_Pos (19U)
+#define DMA_SEC_STATUS_STAT_ALLCHPAUSED_Msk (0x1UL << DMA_SEC_STATUS_STAT_ALLCHPAUSED_Pos) /*!< 0x00080000UL*/
+#define DMA_SEC_STATUS_STAT_ALLCHPAUSED DMA_SEC_STATUS_STAT_ALLCHPAUSED_Msk /*!< STAT_ALLCHPAUSED bit All Secure Channel Paused Status. Set to '1' whenever all Secure DMA channel is in paused or inactive state and the ALLCHPAUSE request is active. Not set when channels reach the paused state for other reasons. All Secure channels are forced to an immediate pause until ALLCHPAUSE request is asserted even if they were enabled after the request. Cleared by writing '1' to this bit which results in all secure channels to resume their operation. The ALLCHPAUSE request is also cleared when this bit is cleared.*/
+
+/***************** Field definitions for SEC_CTRL register ******************/
+#define DMA_SEC_CTRL_INTREN_ANYCHINTR_Pos (0U)
+#define DMA_SEC_CTRL_INTREN_ANYCHINTR_Msk (0x1UL << DMA_SEC_CTRL_INTREN_ANYCHINTR_Pos) /*!< 0x00000001UL*/
+#define DMA_SEC_CTRL_INTREN_ANYCHINTR DMA_SEC_CTRL_INTREN_ANYCHINTR_Msk /*!< INTREN_ANYCHINTR bit Combined Secure Channel Interrupt Enable*/
+#define DMA_SEC_CTRL_INTREN_ALLCHIDLE_Pos (1U)
+#define DMA_SEC_CTRL_INTREN_ALLCHIDLE_Msk (0x1UL << DMA_SEC_CTRL_INTREN_ALLCHIDLE_Pos) /*!< 0x00000002UL*/
+#define DMA_SEC_CTRL_INTREN_ALLCHIDLE DMA_SEC_CTRL_INTREN_ALLCHIDLE_Msk /*!< INTREN_ALLCHIDLE bit All Secure Channel Idle Interrupt Enable*/
+#define DMA_SEC_CTRL_INTREN_ALLCHSTOPPED_Pos (2U)
+#define DMA_SEC_CTRL_INTREN_ALLCHSTOPPED_Msk (0x1UL << DMA_SEC_CTRL_INTREN_ALLCHSTOPPED_Pos) /*!< 0x00000004UL*/
+#define DMA_SEC_CTRL_INTREN_ALLCHSTOPPED DMA_SEC_CTRL_INTREN_ALLCHSTOPPED_Msk /*!< INTREN_ALLCHSTOPPED bit All Secure Channels Stopped Interrupt Enable*/
+#define DMA_SEC_CTRL_INTREN_ALLCHPAUSED_Pos (3U)
+#define DMA_SEC_CTRL_INTREN_ALLCHPAUSED_Msk (0x1UL << DMA_SEC_CTRL_INTREN_ALLCHPAUSED_Pos) /*!< 0x00000008UL*/
+#define DMA_SEC_CTRL_INTREN_ALLCHPAUSED DMA_SEC_CTRL_INTREN_ALLCHPAUSED_Msk /*!< INTREN_ALLCHPAUSED bit All Secure Channel Paused Interrupt Enable*/
+#define DMA_SEC_CTRL_ALLCHSTOP_Pos (8U)
+#define DMA_SEC_CTRL_ALLCHSTOP_Msk (0x1UL << DMA_SEC_CTRL_ALLCHSTOP_Pos) /*!< 0x00000100UL*/
+#define DMA_SEC_CTRL_ALLCHSTOP DMA_SEC_CTRL_ALLCHSTOP_Msk /*!< ALLCHSTOP bit Secure All Channel Stop Request. When set to '1', all Secure channels get a stop request. Stays asserted until the STAT_ALLCHSTOPPED status flag is set. Cleared automatically when the STAT_ALLCHSTOPPED status flag is cleared.*/
+#define DMA_SEC_CTRL_ALLCHPAUSE_Pos (9U)
+#define DMA_SEC_CTRL_ALLCHPAUSE_Msk (0x1UL << DMA_SEC_CTRL_ALLCHPAUSE_Pos) /*!< 0x00000200UL*/
+#define DMA_SEC_CTRL_ALLCHPAUSE DMA_SEC_CTRL_ALLCHPAUSE_Msk /*!< ALLCHPAUSE bit Secure All Channel Pause Request. When set to '1', all Secure channels get a pause request. Stays asserted until the channels are paused and the STAT_ALLCHPAUSED status flag is set. Cleared automatically when the STAT_ALLCHPAUSED status flag is cleared.*/
+#define DMA_SEC_CTRL_DBGHALTNSRO_Pos (27U)
+#define DMA_SEC_CTRL_DBGHALTNSRO_Msk (0x1UL << DMA_SEC_CTRL_DBGHALTNSRO_Pos) /*!< 0x08000000UL*/
+#define DMA_SEC_CTRL_DBGHALTNSRO DMA_SEC_CTRL_DBGHALTNSRO_Msk /*!< DBGHALTNSRO bit Debug Halt Enable Non-Secure Read Only. When set to '1', the NSEC_CTRL.DBGHALTEN register becomes read-only. When set to '0', NSEC_CTRL.DBGHALTEN has read-write access. This register allows the secure SW to limit the non-secure SW adjusting the common DBGHALTEN register bit.*/
+#define DMA_SEC_CTRL_DBGHALTEN_Pos (28U)
+#define DMA_SEC_CTRL_DBGHALTEN_Msk (0x1UL << DMA_SEC_CTRL_DBGHALTEN_Pos) /*!< 0x10000000UL*/
+#define DMA_SEC_CTRL_DBGHALTEN DMA_SEC_CTRL_DBGHALTEN_Msk /*!< DBGHALTEN bit Debug Halt Enabled. When set to '0', the DMA ignores the halt request from an external debugger. Clearing this bit while halt is ongoing results in continuing the operation. When set to '1', the debugger request to halt the DMA is allowed for all channels. This field is common for non-secure and secure side of the DMA, but control can be limited by the SEC_CTRL.DBGHALTNSRO register field.*/
+#define DMA_SEC_CTRL_IDLERETEN_Pos (29U)
+#define DMA_SEC_CTRL_IDLERETEN_Msk (0x1UL << DMA_SEC_CTRL_IDLERETEN_Pos) /*!< 0x20000000UL*/
+#define DMA_SEC_CTRL_IDLERETEN DMA_SEC_CTRL_IDLERETEN_Msk /*!< IDLERETEN bit Idle Channel Retention Enable. Allows retention for Secure channels that are enabled and waiting for an event in IDLE state.
+ - 0: disabled
+ - 1: enabled*/
+#define DMA_SEC_CTRL_DISMINPWR_Pos (30U)
+#define DMA_SEC_CTRL_DISMINPWR_Msk (0x3UL << DMA_SEC_CTRL_DISMINPWR_Pos) /*!< 0xC0000000UL*/
+#define DMA_SEC_CTRL_DISMINPWR DMA_SEC_CTRL_DISMINPWR_Msk /*!< DISMINPWR[ 1:0] bits Minimum Power state of the DMAC when at least one secure channel is present.
+ - 00: OFF
+ - 01: Retention
+ - 10: ON
+ - Others: Reserved*/
+#define DMA_SEC_CTRL_DISMINPWR_0 (0x1UL << DMA_SEC_CTRL_DISMINPWR_Pos) /*!< 0x40000000UL*/
+#define DMA_SEC_CTRL_DISMINPWR_1 (0x2UL << DMA_SEC_CTRL_DISMINPWR_Pos) /*!< 0x80000000UL*/
+
+
+
+/***************** Field definitions for SEC_CHPTR register *****************/
+#define DMA_SEC_CHPTR_CHPTR_Pos (0U)
+#define DMA_SEC_CHPTR_CHPTR_Msk (0x3FUL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x0000003FUL*/
+#define DMA_SEC_CHPTR_CHPTR DMA_SEC_CHPTR_CHPTR_Msk /*!< CHPTR[ 5:0] bits Secure Channel Pointer. Selects which channel settings can be adjusted by the following registers.*/
+#define DMA_SEC_CHPTR_CHPTR_0 (0x1UL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_SEC_CHPTR_CHPTR_1 (0x2UL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_SEC_CHPTR_CHPTR_2 (0x4UL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_SEC_CHPTR_CHPTR_3 (0x8UL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x00000008UL*/
+#define DMA_SEC_CHPTR_CHPTR_4 (0x10UL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x00000010UL*/
+#define DMA_SEC_CHPTR_CHPTR_5 (0x20UL << DMA_SEC_CHPTR_CHPTR_Pos) /*!< 0x00000020UL*/
+
+
+/***************** Field definitions for SEC_CHCFG register *****************/
+#define DMA_SEC_CHCFG_CHID_Pos (0U)
+#define DMA_SEC_CHCFG_CHID_Msk (0xFFFFUL << DMA_SEC_CHCFG_CHID_Pos) /*!< 0x0000FFFFUL*/
+#define DMA_SEC_CHCFG_CHID DMA_SEC_CHCFG_CHID_Msk /*!< CHID[15:0] bits Secure Channel ID value. SECCHPTR selects the channel ID value to be read or written via this register. CHID_WIDTH limits this field, unused bits are RAZWI.*/
+
+#define DMA_SEC_CHCFG_CHIDVLD_Pos (16U)
+#define DMA_SEC_CHCFG_CHIDVLD_Msk (0x1UL << DMA_SEC_CHCFG_CHIDVLD_Pos) /*!< 0x00010000UL*/
+#define DMA_SEC_CHCFG_CHIDVLD DMA_SEC_CHCFG_CHIDVLD_Msk /*!< CHIDVLD bit Secure Channel ID valid. SECCHPTR selects the channel. Set to '1' to drive the channel ID value in CHID for all the transfers by the selected channel.*/
+#define DMA_SEC_CHCFG_CHPRIV_Pos (17U)
+#define DMA_SEC_CHCFG_CHPRIV_Msk (0x1UL << DMA_SEC_CHCFG_CHPRIV_Pos) /*!< 0x00020000UL*/
+#define DMA_SEC_CHCFG_CHPRIV DMA_SEC_CHCFG_CHPRIV_Msk /*!< CHPRIV bit Secure Channel Privilege Enable. SECCHPTR selects the channel. When set to '1' it allows the channel to send transfers marked as Privileged only. The configuration registers of the selected channel are also given privileged only access rights. When set to '0' the channel is only allowed to send unprivileged transfers and the channel registers can be accessed by both privileged and unprivileged register accesses.*/
+
+
+/*************** Field definitions for SEC_STATUSPTR register ***************/
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR_Pos (0U)
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR_Msk (0xFUL << DMA_SEC_STATUSPTR_SECSTATUSPTR_Pos) /*!< 0x0000000FUL*/
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR DMA_SEC_STATUSPTR_SECSTATUSPTR_Msk /*!< SECSTATUSPTR[ 3:0] bits Secure DMA Unit status pointer used to select which status value to view using STATUSVALUE register. Pointer values are:
+ - 0: Channel Enabled Status for channel numbers [31 : 0].
+ - 1: Reserved
+ - 2: Channel Stopped Status for channel numbers [31 : 0].
+ - 3: Reserved
+ - 4: Channel Paused Status for channel numbers [31 : 0].
+ - Others: Reserved.*/
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR_0 (0x1UL << DMA_SEC_STATUSPTR_SECSTATUSPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR_1 (0x2UL << DMA_SEC_STATUSPTR_SECSTATUSPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR_2 (0x4UL << DMA_SEC_STATUSPTR_SECSTATUSPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_SEC_STATUSPTR_SECSTATUSPTR_3 (0x8UL << DMA_SEC_STATUSPTR_SECSTATUSPTR_Pos) /*!< 0x00000008UL*/
+
+
+/*************** Field definitions for SEC_STATUSVAL register ***************/
+#define DMA_SEC_STATUSVAL_SECSTATUSVAL_Pos (0U)
+#define DMA_SEC_STATUSVAL_SECSTATUSVAL_Msk (0xFFFFFFFFUL << DMA_SEC_STATUSVAL_SECSTATUSVAL_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_SEC_STATUSVAL_SECSTATUSVAL DMA_SEC_STATUSVAL_SECSTATUSVAL_Msk /*!< SECSTATUSVAL[31:0] bits Secure DMA Unit status value. Can be used for reading internal status values of the DMA Unit for debug purposes. Values shown here are dependent on STATUSPTR. Note that inputs are masked by security mapping before being presented here. This means that only status values mapped to Secure world are visible as non-Zero values.
+All unimplemented bits are RAZWI. */
+
+
+/*************** Field definitions for SEC_SIGNALPTR register ***************/
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR_Pos (0U)
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR_Msk (0xFUL << DMA_SEC_SIGNALPTR_SECSIGNALPTR_Pos) /*!< 0x0000000FUL*/
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR DMA_SEC_SIGNALPTR_SECSIGNALPTR_Msk /*!< SECSIGNALPTR[ 3:0] bits Secure DMA Unit signal pointer used to select which inputs to view using SIGNALVAL register. Pointer values, x, are:
+ - 0 to 7: Trigger Input Requests [31+32*x : 32*x]
+ - 8 to 9: Trigger output Acknowledges [31+32*(x-8) : 32*(x-8)]
+ - 10 to 11: GPO output value [31+32*(x-10) : 32*(x-10)], only present when HAS_GPOSEL is set.
+ - Others: Reserved*/
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR_0 (0x1UL << DMA_SEC_SIGNALPTR_SECSIGNALPTR_Pos) /*!< 0x00000001UL*/
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR_1 (0x2UL << DMA_SEC_SIGNALPTR_SECSIGNALPTR_Pos) /*!< 0x00000002UL*/
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR_2 (0x4UL << DMA_SEC_SIGNALPTR_SECSIGNALPTR_Pos) /*!< 0x00000004UL*/
+#define DMA_SEC_SIGNALPTR_SECSIGNALPTR_3 (0x8UL << DMA_SEC_SIGNALPTR_SECSIGNALPTR_Pos) /*!< 0x00000008UL*/
+
+
+/*************** Field definitions for SEC_SIGNALVAL register ***************/
+#define DMA_SEC_SIGNALVAL_SECSIGNALVAL_Pos (0U)
+#define DMA_SEC_SIGNALVAL_SECSIGNALVAL_Msk (0xFFFFFFFFUL << DMA_SEC_SIGNALVAL_SECSIGNALVAL_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_SEC_SIGNALVAL_SECSIGNALVAL DMA_SEC_SIGNALVAL_SECSIGNALVAL_Msk /*!< SECSIGNALVAL[31:0] bits Secure DMA Unit signal status. Can be used for reading signal values of triggers and GPOs for debug. Values shown here are dependent on SIGNALPTR. Note that inputs are masked by security mapping before being presented here. This means that only signal values mapped to Secure world are visible as non-zero values. Writing to this register has the following effect:
+ - Writing '1' to a Trigger Input Request that are not selected by any DMA channel will cause a deny response for it. This can attempt to clear an unwanted trigger input.
+ - Writing '1' to any Trigger Output Acknowledges status, GPO value and all Trigger Input Request selected by any DMA channel is ignored.
+All unimplemented bits are RAZWI. */
+
+/******************************************************************************/
+/* DMASECCFG */
+/******************************************************************************/
+
+
+/**************** Field definitions for SCFG_CHSEC0 register ****************/
+#define DMA_SCFG_CHSEC0_SCFGCHSEC0_Pos (0U)
+#define DMA_SCFG_CHSEC0_SCFGCHSEC0_Msk (0xFFFFFFFFUL << DMA_SCFG_CHSEC0_SCFGCHSEC0_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_SCFG_CHSEC0_SCFGCHSEC0 DMA_SCFG_CHSEC0_SCFGCHSEC0_Msk /*!< SCFGCHSEC0[31:0] bits Secure Configuration Channel Security Mapping for Channel 0 to 31. When [i] set to '1', CH<i> is Non-secure world, else Secure world. The NUM_CHANNELS parameter limits this field, unused bits are RAZWI. Value for bit[i] can only be changed if the selected channel is not enabled, so reading back the register content is needed to check the success of the change.*/
+
+
+
+/************** Field definitions for SCFG_TRIGINSEC0 register **************/
+#define DMA_SCFG_TRIGINSEC0_SCFGTRIGINSEC0_Pos (0U)
+#define DMA_SCFG_TRIGINSEC0_SCFGTRIGINSEC0_Msk (0xFFFFFFFFUL << DMA_SCFG_TRIGINSEC0_SCFGTRIGINSEC0_Pos) /*!< 0xFFFFFFFFUL*/
+#define DMA_SCFG_TRIGINSEC0_SCFGTRIGINSEC0 DMA_SCFG_TRIGINSEC0_SCFGTRIGINSEC0_Msk /*!< SCFGTRIGINSEC0[31:0] bits Secure Configuration Tigger Input Security Mapping. When [i] set to '1', Trigger Input <i> is Non-secure world, else Secure world. The NUM_TRIGGER_IN parameter limits this field, unused bits are RAZWI. Value for bit[i] can only be changed if the trigger input port is not in use, so reading back the register content is needed to check the success of the change.*/
+
+
+
+/************* Field definitions for SCFG_TRIGOUTSEC0 register **************/
+#define DMA_SCFG_TRIGOUTSEC0_SCFGTRIGOUTSEC0_Pos (0U)
+#define DMA_SCFG_TRIGOUTSEC0_SCFGTRIGOUTSEC0_Msk (0xFFFFFFFFUL << DMA_SCFG_TRIGOUTSEC0_SCFGTRIGOUTSEC0_Pos)/*!< 0xFFFFFFFFUL*/
+#define DMA_SCFG_TRIGOUTSEC0_SCFGTRIGOUTSEC0 DMA_SCFG_TRIGOUTSEC0_SCFGTRIGOUTSEC0_Msk /*!< SCFGTRIGOUTSEC0[31:0] bits Secure Configuration Tigger Output Security Mapping. When [i] set to '1', Trigger Output <i> is Non-secure world, else Secure world. The NUM_TRIGGER_OUT parameter limits this field, unused bits are RAZWI. Value for bit[i] can only be changed if the trigger output port is not in use, so reading back the register content is needed to check the success of the change.*/
+
+
+
+/***************** Field definitions for SCFG_CTRL register *****************/
+#define DMA_SCFG_CTRL_INTREN_SECACCVIO_Pos (0U)
+#define DMA_SCFG_CTRL_INTREN_SECACCVIO_Msk (0x1UL << DMA_SCFG_CTRL_INTREN_SECACCVIO_Pos) /*!< 0x00000001UL*/
+#define DMA_SCFG_CTRL_INTREN_SECACCVIO DMA_SCFG_CTRL_INTREN_SECACCVIO_Msk /*!< INTREN_SECACCVIO bit Secure Access Violation Interrupt Enable.
+ - 0: no interrupt
+ - 1: interrupt raised for security violation.*/
+#define DMA_SCFG_CTRL_RSPTYPE_SECACCVIO_Pos (1U)
+#define DMA_SCFG_CTRL_RSPTYPE_SECACCVIO_Msk (0x1UL << DMA_SCFG_CTRL_RSPTYPE_SECACCVIO_Pos) /*!< 0x00000002UL*/
+#define DMA_SCFG_CTRL_RSPTYPE_SECACCVIO DMA_SCFG_CTRL_RSPTYPE_SECACCVIO_Msk /*!< RSPTYPE_SECACCVIO bit Secure Access Violation response type configuration.
+ - 0: RAZWI
+ - 1: bus error.*/
+#define DMA_SCFG_CTRL_SEC_CFG_LCK_Pos (31U)
+#define DMA_SCFG_CTRL_SEC_CFG_LCK_Msk (0x1UL << DMA_SCFG_CTRL_SEC_CFG_LCK_Pos) /*!< 0x80000000UL*/
+#define DMA_SCFG_CTRL_SEC_CFG_LCK DMA_SCFG_CTRL_SEC_CFG_LCK_Msk /*!< SEC_CFG_LCK bit Security Configuration Lock. When set to '1', only SCFG.STAT_SECACCVIO can be cleared, all other register fields in the this block become read-only. Once set to '1', this field can only be set back to '0' by reset.*/
+
+/************** Field definitions for SCFG_INTRSTATUS register **************/
+#define DMA_SCFG_INTRSTATUS_INTR_SECACCVIO_Pos (0U)
+#define DMA_SCFG_INTRSTATUS_INTR_SECACCVIO_Msk (0x1UL << DMA_SCFG_INTRSTATUS_INTR_SECACCVIO_Pos) /*!< 0x00000001UL*/
+#define DMA_SCFG_INTRSTATUS_INTR_SECACCVIO DMA_SCFG_INTRSTATUS_INTR_SECACCVIO_Msk /*!< INTR_SECACCVIO bit Secure Access Violation Interrupt Status. Set to '1' when SCFG.STAT_SECACCVIO is asserted and SCFG.INTREN_SECACCVIO = 1. Cleared automatically when STAT_SECACCVIO is cleared.*/
+#define DMA_SCFG_INTRSTATUS_STAT_SECACCVIO_Pos (16U)
+#define DMA_SCFG_INTRSTATUS_STAT_SECACCVIO_Msk (0x1UL << DMA_SCFG_INTRSTATUS_STAT_SECACCVIO_Pos) /*!< 0x00010000UL*/
+#define DMA_SCFG_INTRSTATUS_STAT_SECACCVIO DMA_SCFG_INTRSTATUS_STAT_SECACCVIO_Msk /*!< STAT_SECACCVIO bit Secure Access Violation Status. Set to '1' when a security violation occurred. Write '1' to clear.*/
+/******************************************************************************/
+/* DMAINFO */
+/******************************************************************************/
+
+
+
+/*************** Field definitions for DMA_BUILDCFG0 register ***************/
+#define DMA_DMA_BUILDCFG0_FRAMETYPE_Pos (0U)
+#define DMA_DMA_BUILDCFG0_FRAMETYPE_Msk (0x7UL << DMA_DMA_BUILDCFG0_FRAMETYPE_Pos) /*!< 0x00000007UL*/
+#define DMA_DMA_BUILDCFG0_FRAMETYPE DMA_DMA_BUILDCFG0_FRAMETYPE_Msk /*!< FRAMETYPE[ 2:0] bits Register Frame Type.
+ - 000: Combined Frame,
+ - 001: Security Configuration Frame,
+ - 010: Secure Control Frame, or if TrustZone not implemented, Control Frame.
+ - 011: Non-Secure Control Frame,
+ - 100: DMA Channel Frame.
+Note that each frame replicates the Information fields.*/
+#define DMA_DMA_BUILDCFG0_FRAMETYPE_0 (0x1UL << DMA_DMA_BUILDCFG0_FRAMETYPE_Pos) /*!< 0x00000001UL*/
+#define DMA_DMA_BUILDCFG0_FRAMETYPE_1 (0x2UL << DMA_DMA_BUILDCFG0_FRAMETYPE_Pos) /*!< 0x00000002UL*/
+#define DMA_DMA_BUILDCFG0_FRAMETYPE_2 (0x4UL << DMA_DMA_BUILDCFG0_FRAMETYPE_Pos) /*!< 0x00000004UL*/
+
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos (4U)
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_Msk (0x3FUL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x000003F0UL*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS DMA_DMA_BUILDCFG0_NUM_CHANNELS_Msk /*!< NUM_CHANNELS[ 5:0] bits Number of Channels + 1 supported by the DMAC*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_0 (0x1UL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x00000010UL*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_1 (0x2UL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x00000020UL*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_2 (0x4UL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x00000040UL*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_3 (0x8UL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x00000080UL*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_4 (0x10UL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x00000100UL*/
+#define DMA_DMA_BUILDCFG0_NUM_CHANNELS_5 (0x20UL << DMA_DMA_BUILDCFG0_NUM_CHANNELS_Pos) /*!< 0x00000200UL*/
+
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos (10U)
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_Msk (0x3FUL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x0000FC00UL*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH DMA_DMA_BUILDCFG0_ADDR_WIDTH_Msk /*!< ADDR_WIDTH[ 5:0] bits Address Width in bits = ADDR_WIDTH + 1*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_0 (0x1UL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00000400UL*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_1 (0x2UL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00000800UL*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_2 (0x4UL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00001000UL*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_3 (0x8UL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00002000UL*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_4 (0x10UL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00004000UL*/
+#define DMA_DMA_BUILDCFG0_ADDR_WIDTH_5 (0x20UL << DMA_DMA_BUILDCFG0_ADDR_WIDTH_Pos) /*!< 0x00008000UL*/
+
+#define DMA_DMA_BUILDCFG0_DATA_WIDTH_Pos (16U)
+#define DMA_DMA_BUILDCFG0_DATA_WIDTH_Msk (0x7UL << DMA_DMA_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x00070000UL*/
+#define DMA_DMA_BUILDCFG0_DATA_WIDTH DMA_DMA_BUILDCFG0_DATA_WIDTH_Msk /*!< DATA_WIDTH[ 2:0] bits Data Width.
+ - 000: 8-bit
+ - 001: 16-bit
+ - 010: 32-bit
+ - 011: 64-bit
+ - 100: 128-bit
+ - 101: 256-bit
+ - 110: 512-bit
+ - 111: 1024-bit*/
+#define DMA_DMA_BUILDCFG0_DATA_WIDTH_0 (0x1UL << DMA_DMA_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x00010000UL*/
+#define DMA_DMA_BUILDCFG0_DATA_WIDTH_1 (0x2UL << DMA_DMA_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x00020000UL*/
+#define DMA_DMA_BUILDCFG0_DATA_WIDTH_2 (0x4UL << DMA_DMA_BUILDCFG0_DATA_WIDTH_Pos) /*!< 0x00040000UL*/
+
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos (20U)
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_Msk (0x1FUL << DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos) /*!< 0x01F00000UL*/
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH DMA_DMA_BUILDCFG0_CHID_WIDTH_Msk /*!< CHID_WIDTH[ 4:0] bits Channel ID Width. '0' means CHID is not present.*/
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_0 (0x1UL << DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos) /*!< 0x00100000UL*/
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_1 (0x2UL << DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos) /*!< 0x00200000UL*/
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_2 (0x4UL << DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos) /*!< 0x00400000UL*/
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_3 (0x8UL << DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos) /*!< 0x00800000UL*/
+#define DMA_DMA_BUILDCFG0_CHID_WIDTH_4 (0x10UL << DMA_DMA_BUILDCFG0_CHID_WIDTH_Pos) /*!< 0x01000000UL*/
+
+
+/*************** Field definitions for DMA_BUILDCFG1 register ***************/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos (0U)
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Msk (0x1FFUL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x000001FFUL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Msk /*!< NUM_TRIGGER_IN[ 8:0] bits Number of Triggers Inputs. '0' means that no input triggers are present.*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_0 (0x1UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000001UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_1 (0x2UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000002UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_2 (0x4UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000004UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_3 (0x8UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000008UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_4 (0x10UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000010UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_5 (0x20UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000020UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_6 (0x40UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000040UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_7 (0x80UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000080UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_8 (0x100UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_IN_Pos) /*!< 0x00000100UL*/
+
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos (9U)
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Msk (0x7FUL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x0000FE00UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Msk /*!< NUM_TRIGGER_OUT[ 6:0] bits Number of Triggers Outputs. '0' means that no output triggers are present.*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_0 (0x1UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00000200UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_1 (0x2UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00000400UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_2 (0x4UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00000800UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_3 (0x8UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00001000UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_4 (0x10UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00002000UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_5 (0x20UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00004000UL*/
+#define DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_6 (0x40UL << DMA_DMA_BUILDCFG1_NUM_TRIGGER_OUT_Pos) /*!< 0x00008000UL*/
+
+#define DMA_DMA_BUILDCFG1_HAS_TRIGSEL_Pos (16U)
+#define DMA_DMA_BUILDCFG1_HAS_TRIGSEL_Msk (0x1UL << DMA_DMA_BUILDCFG1_HAS_TRIGSEL_Pos) /*!< 0x00010000UL*/
+#define DMA_DMA_BUILDCFG1_HAS_TRIGSEL DMA_DMA_BUILDCFG1_HAS_TRIGSEL_Msk /*!< HAS_TRIGSEL bit Has Selectable Trigger Support*/
+
+/*************** Field definitions for DMA_BUILDCFG2 register ***************/
+#define DMA_DMA_BUILDCFG2_HAS_GPOSEL_Pos (7U)
+#define DMA_DMA_BUILDCFG2_HAS_GPOSEL_Msk (0x1UL << DMA_DMA_BUILDCFG2_HAS_GPOSEL_Pos) /*!< 0x00000080UL*/
+#define DMA_DMA_BUILDCFG2_HAS_GPOSEL DMA_DMA_BUILDCFG2_HAS_GPOSEL_Msk /*!< HAS_GPOSEL bit Has Shared and hence Selectable GPO Support.*/
+#define DMA_DMA_BUILDCFG2_HAS_TZ_Pos (8U)
+#define DMA_DMA_BUILDCFG2_HAS_TZ_Msk (0x1UL << DMA_DMA_BUILDCFG2_HAS_TZ_Pos) /*!< 0x00000100UL*/
+#define DMA_DMA_BUILDCFG2_HAS_TZ DMA_DMA_BUILDCFG2_HAS_TZ_Msk /*!< HAS_TZ bit Has TrustZone Support*/
+#define DMA_DMA_BUILDCFG2_HAS_RET_Pos (9U)
+#define DMA_DMA_BUILDCFG2_HAS_RET_Msk (0x1UL << DMA_DMA_BUILDCFG2_HAS_RET_Pos) /*!< 0x00000200UL*/
+#define DMA_DMA_BUILDCFG2_HAS_RET DMA_DMA_BUILDCFG2_HAS_RET_Msk /*!< HAS_RET bit Has Retention Support*/
+
+
+/******************* Field definitions for IIDR register ********************/
+#define DMA_IIDR_IMPLEMENTER_Pos (0U)
+#define DMA_IIDR_IMPLEMENTER_Msk (0xFFFUL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000FFFUL*/
+#define DMA_IIDR_IMPLEMENTER DMA_IIDR_IMPLEMENTER_Msk /*!< IMPLEMENTER[11:0] bits Contains the JEP106 code of the company that implemented the IP:
+ - [11:8]: JEP106 continuation code of implementer.
+ - [7]: Always 0.
+ - [6:0]: JEP106 identity code of implementer.
+For Arm this field reads as 0x43B.*/
+#define DMA_IIDR_IMPLEMENTER_0 (0x1UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000001UL*/
+#define DMA_IIDR_IMPLEMENTER_1 (0x2UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000002UL*/
+#define DMA_IIDR_IMPLEMENTER_2 (0x4UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000004UL*/
+#define DMA_IIDR_IMPLEMENTER_3 (0x8UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000008UL*/
+#define DMA_IIDR_IMPLEMENTER_4 (0x10UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000010UL*/
+#define DMA_IIDR_IMPLEMENTER_5 (0x20UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000020UL*/
+#define DMA_IIDR_IMPLEMENTER_6 (0x40UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000040UL*/
+#define DMA_IIDR_IMPLEMENTER_7 (0x80UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000080UL*/
+#define DMA_IIDR_IMPLEMENTER_8 (0x100UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000100UL*/
+#define DMA_IIDR_IMPLEMENTER_9 (0x200UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000200UL*/
+#define DMA_IIDR_IMPLEMENTER_10 (0x400UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000400UL*/
+#define DMA_IIDR_IMPLEMENTER_11 (0x800UL << DMA_IIDR_IMPLEMENTER_Pos) /*!< 0x00000800UL*/
+
+#define DMA_IIDR_REVISION_Pos (12U)
+#define DMA_IIDR_REVISION_Msk (0xFUL << DMA_IIDR_REVISION_Pos) /*!< 0x0000F000UL*/
+#define DMA_IIDR_REVISION DMA_IIDR_REVISION_Msk /*!< REVISION[ 3:0] bits Indicates the minor revision of the product rxpy identifier*/
+#define DMA_IIDR_REVISION_0 (0x1UL << DMA_IIDR_REVISION_Pos) /*!< 0x00001000UL*/
+#define DMA_IIDR_REVISION_1 (0x2UL << DMA_IIDR_REVISION_Pos) /*!< 0x00002000UL*/
+#define DMA_IIDR_REVISION_2 (0x4UL << DMA_IIDR_REVISION_Pos) /*!< 0x00004000UL*/
+#define DMA_IIDR_REVISION_3 (0x8UL << DMA_IIDR_REVISION_Pos) /*!< 0x00008000UL*/
+
+#define DMA_IIDR_VARIANT_Pos (16U)
+#define DMA_IIDR_VARIANT_Msk (0xFUL << DMA_IIDR_VARIANT_Pos) /*!< 0x000F0000UL*/
+#define DMA_IIDR_VARIANT DMA_IIDR_VARIANT_Msk /*!< VARIANT[ 3:0] bits Indicates the major revision, or variant, of the product rxpy identifier*/
+#define DMA_IIDR_VARIANT_0 (0x1UL << DMA_IIDR_VARIANT_Pos) /*!< 0x00010000UL*/
+#define DMA_IIDR_VARIANT_1 (0x2UL << DMA_IIDR_VARIANT_Pos) /*!< 0x00020000UL*/
+#define DMA_IIDR_VARIANT_2 (0x4UL << DMA_IIDR_VARIANT_Pos) /*!< 0x00040000UL*/
+#define DMA_IIDR_VARIANT_3 (0x8UL << DMA_IIDR_VARIANT_Pos) /*!< 0x00080000UL*/
+
+#define DMA_IIDR_PRODUCTID_Pos (20U)
+#define DMA_IIDR_PRODUCTID_Msk (0xFFFUL << DMA_IIDR_PRODUCTID_Pos) /*!< 0xFFF00000UL*/
+#define DMA_IIDR_PRODUCTID DMA_IIDR_PRODUCTID_Msk /*!< PRODUCTID[11:0] bits Indicates the product ID*/
+#define DMA_IIDR_PRODUCTID_0 (0x1UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x00100000UL*/
+#define DMA_IIDR_PRODUCTID_1 (0x2UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x00200000UL*/
+#define DMA_IIDR_PRODUCTID_2 (0x4UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x00400000UL*/
+#define DMA_IIDR_PRODUCTID_3 (0x8UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x00800000UL*/
+#define DMA_IIDR_PRODUCTID_4 (0x10UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x01000000UL*/
+#define DMA_IIDR_PRODUCTID_5 (0x20UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x02000000UL*/
+#define DMA_IIDR_PRODUCTID_6 (0x40UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x04000000UL*/
+#define DMA_IIDR_PRODUCTID_7 (0x80UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x08000000UL*/
+#define DMA_IIDR_PRODUCTID_8 (0x100UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x10000000UL*/
+#define DMA_IIDR_PRODUCTID_9 (0x200UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x20000000UL*/
+#define DMA_IIDR_PRODUCTID_10 (0x400UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x40000000UL*/
+#define DMA_IIDR_PRODUCTID_11 (0x800UL << DMA_IIDR_PRODUCTID_Pos) /*!< 0x80000000UL*/
+
+
+/******************* Field definitions for AIDR register ********************/
+#define DMA_AIDR_ARCH_MINOR_REV_Pos (0U)
+#define DMA_AIDR_ARCH_MINOR_REV_Msk (0xFUL << DMA_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x0000000FUL*/
+#define DMA_AIDR_ARCH_MINOR_REV DMA_AIDR_ARCH_MINOR_REV_Msk /*!< ARCH_MINOR_REV[ 3:0] bits Architecture Minor Revision.*/
+#define DMA_AIDR_ARCH_MINOR_REV_0 (0x1UL << DMA_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000001UL*/
+#define DMA_AIDR_ARCH_MINOR_REV_1 (0x2UL << DMA_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000002UL*/
+#define DMA_AIDR_ARCH_MINOR_REV_2 (0x4UL << DMA_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000004UL*/
+#define DMA_AIDR_ARCH_MINOR_REV_3 (0x8UL << DMA_AIDR_ARCH_MINOR_REV_Pos) /*!< 0x00000008UL*/
+
+#define DMA_AIDR_ARCH_MAJOR_REV_Pos (4U)
+#define DMA_AIDR_ARCH_MAJOR_REV_Msk (0xFUL << DMA_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x000000F0UL*/
+#define DMA_AIDR_ARCH_MAJOR_REV DMA_AIDR_ARCH_MAJOR_REV_Msk /*!< ARCH_MAJOR_REV[ 3:0] bits Architecture Major Revision.*/
+#define DMA_AIDR_ARCH_MAJOR_REV_0 (0x1UL << DMA_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000010UL*/
+#define DMA_AIDR_ARCH_MAJOR_REV_1 (0x2UL << DMA_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000020UL*/
+#define DMA_AIDR_ARCH_MAJOR_REV_2 (0x4UL << DMA_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000040UL*/
+#define DMA_AIDR_ARCH_MAJOR_REV_3 (0x8UL << DMA_AIDR_ARCH_MAJOR_REV_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for PIDR4 register *******************/
+#define DMA_PIDR4_DES_2_Pos (0U)
+#define DMA_PIDR4_DES_2_Msk (0xFUL << DMA_PIDR4_DES_2_Pos) /*!< 0x0000000FUL*/
+#define DMA_PIDR4_DES_2 DMA_PIDR4_DES_2_Msk /*!< DES_2[ 3:0] bits JEP106 Continuation Code*/
+#define DMA_PIDR4_DES_2_0 (0x1UL << DMA_PIDR4_DES_2_Pos) /*!< 0x00000001UL*/
+#define DMA_PIDR4_DES_2_1 (0x2UL << DMA_PIDR4_DES_2_Pos) /*!< 0x00000002UL*/
+#define DMA_PIDR4_DES_2_2 (0x4UL << DMA_PIDR4_DES_2_Pos) /*!< 0x00000004UL*/
+#define DMA_PIDR4_DES_2_3 (0x8UL << DMA_PIDR4_DES_2_Pos) /*!< 0x00000008UL*/
+
+#define DMA_PIDR4_SIZE_Pos (4U)
+#define DMA_PIDR4_SIZE_Msk (0xFUL << DMA_PIDR4_SIZE_Pos) /*!< 0x000000F0UL*/
+#define DMA_PIDR4_SIZE DMA_PIDR4_SIZE_Msk /*!< SIZE[ 3:0] bits 4KB Count - the number of 4K pages used.
+ - 0x00: 4K
+ - 0x01: 8K
+ - 0x02: 16K
+ - 0x03: 32K*/
+#define DMA_PIDR4_SIZE_0 (0x1UL << DMA_PIDR4_SIZE_Pos) /*!< 0x00000010UL*/
+#define DMA_PIDR4_SIZE_1 (0x2UL << DMA_PIDR4_SIZE_Pos) /*!< 0x00000020UL*/
+#define DMA_PIDR4_SIZE_2 (0x4UL << DMA_PIDR4_SIZE_Pos) /*!< 0x00000040UL*/
+#define DMA_PIDR4_SIZE_3 (0x8UL << DMA_PIDR4_SIZE_Pos) /*!< 0x00000080UL*/
+
+
+
+/******************* Field definitions for PIDR0 register *******************/
+#define DMA_PIDR0_PART_0_Pos (0U)
+#define DMA_PIDR0_PART_0_Msk (0xFFUL << DMA_PIDR0_PART_0_Pos) /*!< 0x000000FFUL*/
+#define DMA_PIDR0_PART_0 DMA_PIDR0_PART_0_Msk /*!< PART_0[ 7:0] bits Part Number [7:0]*/
+#define DMA_PIDR0_PART_0_0 (0x1UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000001UL*/
+#define DMA_PIDR0_PART_0_1 (0x2UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000002UL*/
+#define DMA_PIDR0_PART_0_2 (0x4UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000004UL*/
+#define DMA_PIDR0_PART_0_3 (0x8UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000008UL*/
+#define DMA_PIDR0_PART_0_4 (0x10UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000010UL*/
+#define DMA_PIDR0_PART_0_5 (0x20UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000020UL*/
+#define DMA_PIDR0_PART_0_6 (0x40UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000040UL*/
+#define DMA_PIDR0_PART_0_7 (0x80UL << DMA_PIDR0_PART_0_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for PIDR1 register *******************/
+#define DMA_PIDR1_PART_1_Pos (0U)
+#define DMA_PIDR1_PART_1_Msk (0xFUL << DMA_PIDR1_PART_1_Pos) /*!< 0x0000000FUL*/
+#define DMA_PIDR1_PART_1 DMA_PIDR1_PART_1_Msk /*!< PART_1[ 3:0] bits Part Number [11:8].*/
+#define DMA_PIDR1_PART_1_0 (0x1UL << DMA_PIDR1_PART_1_Pos) /*!< 0x00000001UL*/
+#define DMA_PIDR1_PART_1_1 (0x2UL << DMA_PIDR1_PART_1_Pos) /*!< 0x00000002UL*/
+#define DMA_PIDR1_PART_1_2 (0x4UL << DMA_PIDR1_PART_1_Pos) /*!< 0x00000004UL*/
+#define DMA_PIDR1_PART_1_3 (0x8UL << DMA_PIDR1_PART_1_Pos) /*!< 0x00000008UL*/
+
+#define DMA_PIDR1_DES_0_Pos (4U)
+#define DMA_PIDR1_DES_0_Msk (0xFUL << DMA_PIDR1_DES_0_Pos) /*!< 0x000000F0UL*/
+#define DMA_PIDR1_DES_0 DMA_PIDR1_DES_0_Msk /*!< DES_0[ 3:0] bits JEP106 Identity Code [3:0]*/
+#define DMA_PIDR1_DES_0_0 (0x1UL << DMA_PIDR1_DES_0_Pos) /*!< 0x00000010UL*/
+#define DMA_PIDR1_DES_0_1 (0x2UL << DMA_PIDR1_DES_0_Pos) /*!< 0x00000020UL*/
+#define DMA_PIDR1_DES_0_2 (0x4UL << DMA_PIDR1_DES_0_Pos) /*!< 0x00000040UL*/
+#define DMA_PIDR1_DES_0_3 (0x8UL << DMA_PIDR1_DES_0_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for PIDR2 register *******************/
+#define DMA_PIDR2_DES_1_Pos (0U)
+#define DMA_PIDR2_DES_1_Msk (0x7UL << DMA_PIDR2_DES_1_Pos) /*!< 0x00000007UL*/
+#define DMA_PIDR2_DES_1 DMA_PIDR2_DES_1_Msk /*!< DES_1[ 2:0] bits JEP106 Identity Code [6:4]*/
+#define DMA_PIDR2_DES_1_0 (0x1UL << DMA_PIDR2_DES_1_Pos) /*!< 0x00000001UL*/
+#define DMA_PIDR2_DES_1_1 (0x2UL << DMA_PIDR2_DES_1_Pos) /*!< 0x00000002UL*/
+#define DMA_PIDR2_DES_1_2 (0x4UL << DMA_PIDR2_DES_1_Pos) /*!< 0x00000004UL*/
+
+#define DMA_PIDR2_JEDEC_Pos (3U)
+#define DMA_PIDR2_JEDEC_Msk (0x1UL << DMA_PIDR2_JEDEC_Pos) /*!< 0x00000008UL*/
+#define DMA_PIDR2_JEDEC DMA_PIDR2_JEDEC_Msk /*!< JEDEC bit JEDEC*/
+#define DMA_PIDR2_REVISION_Pos (4U)
+#define DMA_PIDR2_REVISION_Msk (0xFUL << DMA_PIDR2_REVISION_Pos) /*!< 0x000000F0UL*/
+#define DMA_PIDR2_REVISION DMA_PIDR2_REVISION_Msk /*!< REVISION[ 3:0] bits Revision Code*/
+#define DMA_PIDR2_REVISION_0 (0x1UL << DMA_PIDR2_REVISION_Pos) /*!< 0x00000010UL*/
+#define DMA_PIDR2_REVISION_1 (0x2UL << DMA_PIDR2_REVISION_Pos) /*!< 0x00000020UL*/
+#define DMA_PIDR2_REVISION_2 (0x4UL << DMA_PIDR2_REVISION_Pos) /*!< 0x00000040UL*/
+#define DMA_PIDR2_REVISION_3 (0x8UL << DMA_PIDR2_REVISION_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for PIDR3 register *******************/
+#define DMA_PIDR3_CMOD_Pos (0U)
+#define DMA_PIDR3_CMOD_Msk (0xFUL << DMA_PIDR3_CMOD_Pos) /*!< 0x0000000FUL*/
+#define DMA_PIDR3_CMOD DMA_PIDR3_CMOD_Msk /*!< CMOD[ 3:0] bits Customer Modified*/
+#define DMA_PIDR3_CMOD_0 (0x1UL << DMA_PIDR3_CMOD_Pos) /*!< 0x00000001UL*/
+#define DMA_PIDR3_CMOD_1 (0x2UL << DMA_PIDR3_CMOD_Pos) /*!< 0x00000002UL*/
+#define DMA_PIDR3_CMOD_2 (0x4UL << DMA_PIDR3_CMOD_Pos) /*!< 0x00000004UL*/
+#define DMA_PIDR3_CMOD_3 (0x8UL << DMA_PIDR3_CMOD_Pos) /*!< 0x00000008UL*/
+
+#define DMA_PIDR3_REVAND_Pos (4U)
+#define DMA_PIDR3_REVAND_Msk (0xFUL << DMA_PIDR3_REVAND_Pos) /*!< 0x000000F0UL*/
+#define DMA_PIDR3_REVAND DMA_PIDR3_REVAND_Msk /*!< REVAND[ 3:0] bits Manufacturer revision number*/
+#define DMA_PIDR3_REVAND_0 (0x1UL << DMA_PIDR3_REVAND_Pos) /*!< 0x00000010UL*/
+#define DMA_PIDR3_REVAND_1 (0x2UL << DMA_PIDR3_REVAND_Pos) /*!< 0x00000020UL*/
+#define DMA_PIDR3_REVAND_2 (0x4UL << DMA_PIDR3_REVAND_Pos) /*!< 0x00000040UL*/
+#define DMA_PIDR3_REVAND_3 (0x8UL << DMA_PIDR3_REVAND_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for CIDR0 register *******************/
+#define DMA_CIDR0_PRMBL_0_Pos (0U)
+#define DMA_CIDR0_PRMBL_0_Msk (0xFFUL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x000000FFUL*/
+#define DMA_CIDR0_PRMBL_0 DMA_CIDR0_PRMBL_0_Msk /*!< PRMBL_0[ 7:0] bits Preamble*/
+#define DMA_CIDR0_PRMBL_0_0 (0x1UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000001UL*/
+#define DMA_CIDR0_PRMBL_0_1 (0x2UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000002UL*/
+#define DMA_CIDR0_PRMBL_0_2 (0x4UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000004UL*/
+#define DMA_CIDR0_PRMBL_0_3 (0x8UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000008UL*/
+#define DMA_CIDR0_PRMBL_0_4 (0x10UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000010UL*/
+#define DMA_CIDR0_PRMBL_0_5 (0x20UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000020UL*/
+#define DMA_CIDR0_PRMBL_0_6 (0x40UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000040UL*/
+#define DMA_CIDR0_PRMBL_0_7 (0x80UL << DMA_CIDR0_PRMBL_0_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for CIDR1 register *******************/
+#define DMA_CIDR1_PRMBL_1_Pos (0U)
+#define DMA_CIDR1_PRMBL_1_Msk (0xFUL << DMA_CIDR1_PRMBL_1_Pos) /*!< 0x0000000FUL*/
+#define DMA_CIDR1_PRMBL_1 DMA_CIDR1_PRMBL_1_Msk /*!< PRMBL_1[ 3:0] bits Preamble*/
+#define DMA_CIDR1_PRMBL_1_0 (0x1UL << DMA_CIDR1_PRMBL_1_Pos) /*!< 0x00000001UL*/
+#define DMA_CIDR1_PRMBL_1_1 (0x2UL << DMA_CIDR1_PRMBL_1_Pos) /*!< 0x00000002UL*/
+#define DMA_CIDR1_PRMBL_1_2 (0x4UL << DMA_CIDR1_PRMBL_1_Pos) /*!< 0x00000004UL*/
+#define DMA_CIDR1_PRMBL_1_3 (0x8UL << DMA_CIDR1_PRMBL_1_Pos) /*!< 0x00000008UL*/
+
+#define DMA_CIDR1_CLASS_Pos (4U)
+#define DMA_CIDR1_CLASS_Msk (0xFUL << DMA_CIDR1_CLASS_Pos) /*!< 0x000000F0UL*/
+#define DMA_CIDR1_CLASS DMA_CIDR1_CLASS_Msk /*!< CLASS[ 3:0] bits Component class*/
+#define DMA_CIDR1_CLASS_0 (0x1UL << DMA_CIDR1_CLASS_Pos) /*!< 0x00000010UL*/
+#define DMA_CIDR1_CLASS_1 (0x2UL << DMA_CIDR1_CLASS_Pos) /*!< 0x00000020UL*/
+#define DMA_CIDR1_CLASS_2 (0x4UL << DMA_CIDR1_CLASS_Pos) /*!< 0x00000040UL*/
+#define DMA_CIDR1_CLASS_3 (0x8UL << DMA_CIDR1_CLASS_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for CIDR2 register *******************/
+#define DMA_CIDR2_PRMBL_2_Pos (0U)
+#define DMA_CIDR2_PRMBL_2_Msk (0xFFUL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x000000FFUL*/
+#define DMA_CIDR2_PRMBL_2 DMA_CIDR2_PRMBL_2_Msk /*!< PRMBL_2[ 7:0] bits Preamble*/
+#define DMA_CIDR2_PRMBL_2_0 (0x1UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000001UL*/
+#define DMA_CIDR2_PRMBL_2_1 (0x2UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000002UL*/
+#define DMA_CIDR2_PRMBL_2_2 (0x4UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000004UL*/
+#define DMA_CIDR2_PRMBL_2_3 (0x8UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000008UL*/
+#define DMA_CIDR2_PRMBL_2_4 (0x10UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000010UL*/
+#define DMA_CIDR2_PRMBL_2_5 (0x20UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000020UL*/
+#define DMA_CIDR2_PRMBL_2_6 (0x40UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000040UL*/
+#define DMA_CIDR2_PRMBL_2_7 (0x80UL << DMA_CIDR2_PRMBL_2_Pos) /*!< 0x00000080UL*/
+
+
+/******************* Field definitions for CIDR3 register *******************/
+#define DMA_CIDR3_PRMBL_3_Pos (0U)
+#define DMA_CIDR3_PRMBL_3_Msk (0xFFUL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x000000FFUL*/
+#define DMA_CIDR3_PRMBL_3 DMA_CIDR3_PRMBL_3_Msk /*!< PRMBL_3[ 7:0] bits Preamble*/
+#define DMA_CIDR3_PRMBL_3_0 (0x1UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000001UL*/
+#define DMA_CIDR3_PRMBL_3_1 (0x2UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000002UL*/
+#define DMA_CIDR3_PRMBL_3_2 (0x4UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000004UL*/
+#define DMA_CIDR3_PRMBL_3_3 (0x8UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000008UL*/
+#define DMA_CIDR3_PRMBL_3_4 (0x10UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000010UL*/
+#define DMA_CIDR3_PRMBL_3_5 (0x20UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000020UL*/
+#define DMA_CIDR3_PRMBL_3_6 (0x40UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000040UL*/
+#define DMA_CIDR3_PRMBL_3_7 (0x80UL << DMA_CIDR3_PRMBL_3_Pos) /*!< 0x00000080UL*/
+
+#endif /* __ADA_DMA_REGDEF_H */
+
diff --git a/software/lib/sw_lib/devices/src/dma_350_command_lib.c b/software/lib/sw_lib/devices/src/dma_350_command_lib.c
new file mode 100755
index 0000000000000000000000000000000000000000..4d45e3fd1ce2d4f7ee784a22828f662803a59751
--- /dev/null
+++ b/software/lib/sw_lib/devices/src/dma_350_command_lib.c
@@ -0,0 +1,2450 @@
+/******************************************************************************/
+/* The confidential and proprietary information contained in this file may */
+/* only be used by a person authorised under and to the extent permitted */
+/* by a subsisting licensing agreement from Arm Limited or its affiliates. */
+/* */
+/* (C) COPYRIGHT 2022 Arm Limited or its affiliates. */
+/* ALL RIGHTS RESERVED */
+/* */
+/* This entire notice must be reproduced on all copies of this file */
+/* and copies of this file may only be made by a person if such person is */
+/* permitted to do so under the terms of a subsisting license agreement */
+/* from Arm Limited or its affiliates. */
+/* */
+/* Release Information : DMA350-r0p0-00rel0 */
+/* */
+/******************************************************************************/
+
+ #ifndef __DMA_COMMAND_LIB_C
+ #define __DMA_COMMAND_LIB_C
+
+#include <stdio.h>
+#include "dma_350_command_lib.h"
+
+// Channel pointers
+DMACH_TypeDef *sec_dma_channels[3] = { DMACH0_S, DMACH1_S, DMACH2_S};
+
+DMACH_TypeDef *nsec_dma_channels[3] = { DMACH0_NS, DMACH1_NS, DMACH2_NS};
+
+//
+// Get DMA channel register frame based on security and channel number
+//
+DMACH_TypeDef* GetChannelPtr(uint32_t ch_num, uint8_t security)
+{
+ if (ch_num<ADA_MAX_CH_NUM)
+ {
+ if (security==0)
+ {
+ return sec_dma_channels[ch_num];
+ }
+ else if (security==1)
+ {
+ return nsec_dma_channels[ch_num];
+ }
+ else
+ {
+ printf("Error - Security must be 0 or 1");
+ return sec_dma_channels[ch_num];
+ }
+ }
+ else
+ {
+ printf("Error - Pointer for Channel %d is not defined", ch_num);
+ return sec_dma_channels[0];
+ }
+}
+
+//
+// Dma Enable a Channel
+// Channel Enable. When set to '1', enable to channel to run its programmed task. When set to '1', it cannot be set back to zero,
+// and this field will automatically clears to zero when a DMA process is completed. To force the DMA to stop prematurely,
+// you must use CH_CMD.STOPCMD instead.
+//
+void AdaEnable(uint32_t ch_num, uint8_t security)
+{
+ DMACH_TypeDef * actual_frame;
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ actual_frame->CH_CMD = (actual_frame->CH_CMD) | DMA_CH_CMD_ENABLECMD_Msk;
+}
+
+uint8_t AdaGetEnable(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CMD;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CMD.w = actual_frame->CH_CMD;
+
+ // Return actual status
+ return CMD.b.ENABLECMD;
+}
+
+//
+// Dma Stop a Channel
+// Stop Current DMA Operation. Once set to '1', his will remain high until the DMA is stopped cleanly. Then this will return to '0' and ENABLECMD is also cleared.
+//
+void AdaStop(uint32_t ch_num, uint8_t security)
+{
+ DMACH_TypeDef * actual_frame;
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ actual_frame->CH_CMD = (actual_frame->CH_CMD) | DMA_CH_CMD_STOPCMD_Msk;
+}
+
+//
+// Dma Disable a Channel
+// Stop DMA Operation at the end of current DMA command operation. Once set to '1', this field will stay high and the current DMA command will be allowed to complete,
+// but the DMA will not fetch the next linked command or will it auto-restart the DMA command even if they are set. Once the DMA has stopped,
+// it will return to '0' and ENABLECMD is also cleared.
+//
+void AdaDisable(uint32_t ch_num, uint8_t security)
+{
+ DMACH_TypeDef * actual_frame;
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ actual_frame->CH_CMD = (actual_frame->CH_CMD) | DMA_CH_CMD_DISABLECMD_Msk;
+}
+
+//
+// Dma Clear a Channel
+// DMA Clear command. When set to '1', it will remain high until all DMA Channel registers and any internal queues and buffers are cleared,
+// before returning to '0'. When set while the DMA channel is enabled, the clear will only occur after any ongoing DMA operation is either completed,
+// stopped or disabled.
+//
+void AdaClear(uint32_t ch_num, uint8_t security)
+{
+ DMACH_TypeDef * actual_frame;
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ actual_frame->CH_CMD = (actual_frame->CH_CMD) | DMA_CH_CMD_CLEARCMD_Msk;
+}
+
+//
+// Dma Pause a Channel operation
+// Pause Current DMA Operation. Once set to '1' the status cannot change until the DMA operation reached the paused state indicated by the STAT_PAUSED and STAT_RESUMEWAIT bits.
+// The bit can be set by SW by writing it to '1', the current active DMA operation will be paused as soon as possible, but the ENABLECMD bit will remain HIGH to show that the
+// operation is still active. Cleared automatically when STAT_RESUMEWAIT is set and the RESUMECMD bit is written to '1', meaning that the SW continues the operation of the channel.
+// Note that each DMA channel can optionally have other sources of a pause request and this field will not reflect the state of the other sources.
+// The DMA Unit level ALLCHPAUSE request is also not reflected by this bit.
+//
+void AdaPause(uint32_t ch_num, uint8_t security)
+{
+ DMACH_TypeDef * actual_frame;
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ actual_frame->CH_CMD = (actual_frame->CH_CMD) | DMA_CH_CMD_PAUSECMD_Msk;
+}
+
+//
+// Dma Resume a Channel operation
+// Resume Current DMA Operation. Writing this bit to '1' means that the SW can continue the operation of a paused channel.
+// Can be set to '1' when the PAUSECMD or a STAT_DONE assertion with DONEPAUSEEN set HIGH results in pausing the current DMA channel operation
+// indicated by the STAT_PAUSED and STAT_RESUMEWAIT bits. Otherwise, writes to this bit are ignored. Always read as 0.
+//
+void AdaResume(uint32_t ch_num, uint8_t security)
+{
+ DMACH_TypeDef * actual_frame;
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ actual_frame->CH_CMD = (actual_frame->CH_CMD) | DMA_CH_CMD_RESUMECMD_Msk;
+}
+
+//
+// Set 1D Command registers
+//
+//
+
+void Ada1DCommand(AdaBaseCommandType command_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_XSIZE_Type CHXSIZE;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Write whole registers
+ actual_frame->CH_SRCADDR = (uint32_t)command_params.SRCADDR;
+ actual_frame->CH_DESADDR = (uint32_t)command_params.DESADDR;
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+ CHXSIZE.w = actual_frame->CH_XSIZE;
+
+ //Modify registers
+ CHCTRL.b.TRANSIZE = command_params.TRANSIZE;
+ // 0xFFFF is a bitmask, because the width of the SRC/DESXSIZE fields are 16 bit
+ CHXSIZE.b.SRCXSIZE = (0xFFFF & command_params.SRCXSIZE);
+ CHXSIZE.b.DESXSIZE = (0xFFFF & command_params.DESXSIZE);
+
+ //Write registers
+ actual_frame->CH_XSIZE = CHXSIZE.w;
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+uint32_t GetAdaActualSrcXSize(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_XSIZE_Type CHXSIZE;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHXSIZE.w = actual_frame->CH_XSIZE;
+
+ //Modify registers
+ return CHXSIZE.b.SRCXSIZE;
+}
+uint32_t GetAdaActualDesXSize(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_XSIZE_Type CHXSIZE;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHXSIZE.w = actual_frame->CH_XSIZE;
+
+ //Modify registers
+ return CHXSIZE.b.DESXSIZE;
+}
+
+void SetAdaLong1DRegs(AdaBaseCommandType command_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_XSIZEHI_Type CHXSIZEHI;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Write whole registers
+ actual_frame->CH_SRCADDRHI = (command_params.SRCADDR >> 32);
+ actual_frame->CH_DESADDRHI = (command_params.DESADDR >> 32);
+
+ //Read registers
+ CHXSIZEHI.w = actual_frame->CH_XSIZEHI;
+
+ //Modify registers
+ CHXSIZEHI.b.SRCXSIZEHI = (command_params.SRCXSIZE >> 16);
+ CHXSIZEHI.b.SRCXSIZEHI = (command_params.SRCXSIZE >> 16);
+
+ //Write registers
+ actual_frame->CH_XSIZEHI = CHXSIZEHI.w;
+}
+
+
+void AdaLong1DCommand(AdaBaseCommandType command_params, uint32_t ch_num, uint8_t security)
+{
+ //Call the Short 1D command
+ Ada1DCommand(command_params, ch_num, security);
+ //Write HI registers
+ SetAdaLong1DRegs(command_params, ch_num, security);
+}
+
+
+void AdaSetSrcTranAttrs(AdaChannelSrcAttrType src_attr, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_SRCTRANSCFG_Type CHSRCTRANSCFG;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHSRCTRANSCFG.w = actual_frame->CH_SRCTRANSCFG;
+
+ //Modify values
+ CHSRCTRANSCFG.b.SRCMEMATTRLO = src_attr.SRCMEMATTRLO;
+ CHSRCTRANSCFG.b.SRCMEMATTRHI = src_attr.SRCMEMATTRHI;
+ CHSRCTRANSCFG.b.SRCSHAREATTR = src_attr.SRCSHAREATTR;
+ CHSRCTRANSCFG.b.SRCNONSECATTR = src_attr.SRCNONSECATTR;
+ CHSRCTRANSCFG.b.SRCPRIVATTR = src_attr.SRCPRIVATTR;
+
+ //Write register
+ actual_frame->CH_SRCTRANSCFG = CHSRCTRANSCFG.w ;
+}
+
+void AdaSetDesTranAttrs(AdaChannelDesAttrType des_attr, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_DESTRANSCFG_Type CHDESTRANSCFG;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHDESTRANSCFG.w = actual_frame->CH_DESTRANSCFG;
+
+ //Modify values
+ CHDESTRANSCFG.b.DESMEMATTRLO = des_attr.DESMEMATTRLO;
+ CHDESTRANSCFG.b.DESMEMATTRHI = des_attr.DESMEMATTRHI;
+ CHDESTRANSCFG.b.DESSHAREATTR = des_attr.DESSHAREATTR;
+ CHDESTRANSCFG.b.DESNONSECATTR = des_attr.DESNONSECATTR;
+ CHDESTRANSCFG.b.DESPRIVATTR = des_attr.DESPRIVATTR;
+
+ actual_frame->CH_DESTRANSCFG = CHDESTRANSCFG.w ;
+}
+
+//Set the basic settings of a DMA channel: CHPRIO, REGRELOADTYPE
+void AdaChannelSettings(AdaChannelSettingsType ch_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+ volatile DMACH_CH_SRCTRANSCFG_Type CHSRCTRANSCFG;
+ volatile DMACH_CH_DESTRANSCFG_Type CHDESTRANSCFG;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCTRL.w = actual_frame->CH_CTRL;
+ CHCMD.w = actual_frame->CH_CMD;
+ CHSRCTRANSCFG.w = actual_frame->CH_SRCTRANSCFG;
+ CHDESTRANSCFG.w = actual_frame->CH_DESTRANSCFG;
+
+ //Modify values
+ CHCTRL.b.CHPRIO = ch_params.CHPRIO;
+ CHCTRL.b.REGRELOADTYPE = ch_params.REGRELOADTYPE;
+ CHCTRL.b.DONETYPE = ch_params.DONETYPE;
+ CHCTRL.b.DONEPAUSEEN = ch_params.DONEPAUSEEN;
+ CHCMD.b.CLEARCMD = ch_params.CLEARCMD;
+ CHSRCTRANSCFG.b.SRCMAXBURSTLEN = ch_params.SRCMAXBURSTLEN;
+ CHDESTRANSCFG.b.DESMAXBURSTLEN = ch_params.DESMAXBURSTLEN;
+
+ //Write registers
+ actual_frame->CH_CTRL = CHCTRL.w;
+ actual_frame->CH_CMD = CHCMD.w;
+ actual_frame->CH_SRCTRANSCFG = CHSRCTRANSCFG.w;
+ actual_frame->CH_DESTRANSCFG = CHDESTRANSCFG.w;
+}
+
+//Set the basic settings of a DMA channel
+void AdaChannelInit(AdaChannelSettingsType ch_params, AdaChannelSrcAttrType src_attr, AdaChannelDesAttrType des_attr, uint32_t ch_num, uint8_t security)
+{
+ AdaChannelSettings(ch_params, ch_num, security);
+ AdaSetSrcTranAttrs(src_attr, ch_num, security);
+ AdaSetDesTranAttrs(des_attr, ch_num, security);
+}
+
+void SetAda1DIncrRegs(Ada1DIncrCommandType incr_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_XADDRINC_Type CHXADDRINC;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHXADDRINC.w = actual_frame->CH_XADDRINC;
+
+ //Modify registers
+ CHXADDRINC.b.SRCXADDRINC = incr_params.SRCXADDRINC;
+ CHXADDRINC.b.DESXADDRINC = incr_params.DESXADDRINC;
+
+ //Write registers
+ actual_frame->CH_XADDRINC = CHXADDRINC.w;
+}
+
+void Ada1DIncrCommand(AdaBaseCommandType command_params, Ada1DIncrCommandType incr_params, uint32_t ch_num, uint8_t security)
+{
+ Ada1DCommand(command_params, ch_num, security);
+ SetAda1DIncrRegs(incr_params, ch_num, security);
+}
+
+
+void SetAda2DRegs(Ada2DCommandType y_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_YSIZE_Type YSIZE;
+ volatile DMACH_CH_YADDRSTRIDE_Type YADDRSTRIDE;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ YSIZE.w = actual_frame->CH_YSIZE;
+ YADDRSTRIDE.w = actual_frame->CH_YADDRSTRIDE;
+
+ //Modify registers
+ YSIZE.b.SRCYSIZE = y_params.SRCYSIZE;
+ YSIZE.b.DESYSIZE = y_params.DESYSIZE;
+ YADDRSTRIDE.b.SRCYADDRSTRIDE = y_params.SRCYADDRSTRIDE;
+ YADDRSTRIDE.b.DESYADDRSTRIDE = y_params.DESYADDRSTRIDE;
+
+ //Write registers
+ actual_frame->CH_YSIZE = YSIZE.w;
+ actual_frame->CH_YADDRSTRIDE = YADDRSTRIDE.w;
+}
+
+void Ada2DCommand(AdaBaseCommandType command_params, Ada2DCommandType y_params, uint32_t ch_num, uint8_t security)
+{
+ Ada1DCommand(command_params, ch_num, security);
+ SetAda2DRegs(y_params, ch_num, security);
+}
+
+
+void SetAdaWrapRegs(AdaWrapCommandType wrap_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+
+ //Modify registers
+ CHCTRL.b.XTYPE = wrap_params.XTYPE;
+ CHCTRL.b.YTYPE = wrap_params.YTYPE;
+
+ //Write registers
+ actual_frame->CH_CTRL = CHCTRL.w;
+ actual_frame->CH_FILLVAL = wrap_params.FILLVAL;
+}
+
+void AdaWrapCommand(AdaBaseCommandType command_params, AdaWrapCommandType wrap_params, uint32_t ch_num, uint8_t security)
+{
+ Ada1DCommand(command_params, ch_num, security);
+ SetAdaWrapRegs(wrap_params, ch_num, security);
+}
+
+void AdaWrap2DCommand(AdaBaseCommandType command_params, Ada2DCommandType y_params, AdaWrapCommandType wrap_params, uint32_t ch_num, uint8_t security)
+{
+ Ada1DCommand(command_params, ch_num, security);
+ SetAda2DRegs(y_params, ch_num, security);
+ SetAdaWrapRegs(wrap_params, ch_num, security);
+}
+
+
+void SetAdaTmpltRegs(AdaTMPLTCommandType tmplt_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_TMPLTCFG_Type TMPLTCFG;
+ volatile DMACH_CH_SRCTMPLT_Type SRCTMPLT;
+ volatile DMACH_CH_DESTMPLT_Type DESTMPLT;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ TMPLTCFG.w = actual_frame->CH_TMPLTCFG;
+
+ //Modify registers
+ TMPLTCFG.b.SRCTMPLTSIZE = tmplt_params.SRCTMPLTSIZE;
+ TMPLTCFG.b.DESTMPLTSIZE = tmplt_params.DESTMPLTSIZE;
+
+ SRCTMPLT.b.SRCTMPLT = (tmplt_params.SRCTMPLT >> 1);
+ DESTMPLT.b.DESTMPLT = (tmplt_params.DESTMPLT >> 1);
+
+ //Write registers
+ actual_frame->CH_TMPLTCFG = TMPLTCFG.w;
+ actual_frame->CH_SRCTMPLT = SRCTMPLT.w;
+ actual_frame->CH_DESTMPLT = DESTMPLT.w;
+}
+
+void AdaTmpltCommand(AdaBaseCommandType command_params, AdaTMPLTCommandType tmplt_params, uint32_t ch_num, uint8_t security)
+{
+ Ada1DCommand(command_params, ch_num, security);
+ SetAdaTmpltRegs( tmplt_params, ch_num, security);
+}
+
+AdaStatType AdaReadStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+ AdaStatType actual_stat;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set the Actual status to the struct
+ actual_stat.STAT_DONE = STATUS.b.STAT_DONE;
+ actual_stat.STAT_ERR = STATUS.b.STAT_ERR;
+ actual_stat.STAT_DISABLED = STATUS.b.STAT_DISABLED;
+ actual_stat.STAT_STOPPED = STATUS.b.STAT_STOPPED;
+ actual_stat.STAT_PAUSED = STATUS.b.STAT_PAUSED;
+ actual_stat.STAT_RESUMEWAIT = STATUS.b.STAT_RESUMEWAIT;
+
+ return actual_stat;
+}
+
+uint8_t AdaChDoneStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_DONE;
+}
+
+uint8_t AdaChErrorStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_ERR;
+}
+
+uint8_t AdaChDisabledStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_DISABLED;
+}
+
+uint8_t AdaChStoppedStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_STOPPED;
+}
+
+uint8_t AdaChPausedStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_PAUSED;
+}
+
+uint8_t AdaChResumeWaitStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_RESUMEWAIT;
+}
+
+void AdaClearChDone(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set W1C register to 1
+ STATUS.b.STAT_DONE = 1;
+ // Set other W1C registers to 0 (avoid clearing)
+ STATUS.b.STAT_ERR = 0;
+ STATUS.b.STAT_DISABLED = 0;
+ STATUS.b.STAT_STOPPED = 0;
+
+ //Wite register
+ actual_frame->CH_STATUS = STATUS.w;
+
+}
+
+void AdaClearChError(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set W1C register to 1
+ STATUS.b.STAT_ERR = 1;
+ // Set other W1C registers to 0 (avoid clearing)
+ STATUS.b.STAT_DONE = 0;
+ STATUS.b.STAT_DISABLED = 0;
+ STATUS.b.STAT_STOPPED = 0;
+
+ //Wite register
+ actual_frame->CH_STATUS = STATUS.w;
+}
+
+void AdaClearChDisabled(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set W1C register to 1
+ STATUS.b.STAT_DISABLED = 1;
+ // Set other W1C registers to 0 (avoid clearing)
+ STATUS.b.STAT_DONE = 0;
+ STATUS.b.STAT_ERR = 0;
+ STATUS.b.STAT_STOPPED = 0;
+
+ //Wite register
+ actual_frame->CH_STATUS = STATUS.w;
+}
+
+void AdaClearChStopped(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set W1C register to 1
+ STATUS.b.STAT_STOPPED = 1;
+ // Set other W1C registers to 0 (avoid clearing)
+ STATUS.b.STAT_DONE = 0;
+ STATUS.b.STAT_ERR = 0;
+ STATUS.b.STAT_DISABLED = 0;
+
+ //Wite register
+ actual_frame->CH_STATUS = STATUS.w;
+}
+
+void AdaClearAllChIrq(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set W1C register to 1
+ STATUS.b.STAT_STOPPED = 1;
+ STATUS.b.STAT_DONE = 1;
+ STATUS.b.STAT_ERR = 1;
+ STATUS.b.STAT_DISABLED = 1;
+
+ //Wite register
+ actual_frame->CH_STATUS = STATUS.w;
+}
+
+AdaTrigStatType AdaReadTrigStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+ AdaTrigStatType actual_trig_stat;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set the Actual status to the struct
+ actual_trig_stat.STAT_SRCTRIGINWAIT = STATUS.b.STAT_SRCTRIGINWAIT;
+ actual_trig_stat.STAT_DESTRIGINWAIT = STATUS.b.STAT_DESTRIGINWAIT;
+ actual_trig_stat.STAT_TRIGOUTACKWAIT = STATUS.b.STAT_TRIGOUTACKWAIT;
+
+ return actual_trig_stat;
+}
+
+uint8_t AdaChSrcTrigInWaitStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_SRCTRIGINWAIT;
+}
+
+uint8_t AdaChDesTrigInWaitStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_DESTRIGINWAIT;
+}
+
+uint8_t AdaChTrigOutAckWaitStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Return actual status
+ return STATUS.b.STAT_TRIGOUTACKWAIT;
+}
+
+
+AdaIrqType AdaReadIrqStatus(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STATUS_Type STATUS;
+ AdaIrqType actual_irq_stat;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ STATUS.w = actual_frame->CH_STATUS;
+
+ // Set the Actual status to the struct
+ actual_irq_stat.INTR_DONE = STATUS.b.INTR_DONE;
+ actual_irq_stat.INTR_ERR = STATUS.b.INTR_ERR;
+ actual_irq_stat.INTR_DISABLED = STATUS.b.INTR_DISABLED;
+ actual_irq_stat.INTR_STOPPED = STATUS.b.INTR_STOPPED;
+ actual_irq_stat.INTR_SRCTRIGINWAIT = STATUS.b.INTR_SRCTRIGINWAIT;
+ actual_irq_stat.INTR_DESTRIGINWAIT = STATUS.b.INTR_DESTRIGINWAIT;
+ actual_irq_stat.INTR_TRIGOUTACKWAIT = STATUS.b.INTR_TRIGOUTACKWAIT;
+
+ return actual_irq_stat;
+}
+
+void AdaSetIntEn(AdaIrqEnType int_en_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_DONE = int_en_params.INTREN_DONE;
+ INTREN.b.INTREN_ERR = int_en_params.INTREN_ERR;
+ INTREN.b.INTREN_DISABLED = int_en_params.INTREN_DISABLED;
+ INTREN.b.INTREN_STOPPED = int_en_params.INTREN_STOPPED;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetDoneIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_DONE = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetErrorIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_ERR = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetDisabledIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_DISABLED = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetStoppedIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_STOPPED = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetTrigIntEn(AdaTrigIrqEnType trig_int_en_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_SRCTRIGINWAIT = trig_int_en_params.INTREN_SRCTRIGINWAIT;
+ INTREN.b.INTREN_DESTRIGINWAIT = trig_int_en_params.INTREN_DESTRIGINWAIT;
+ INTREN.b.INTREN_TRIGOUTACKWAIT = trig_int_en_params.INTREN_TRIGOUTACKWAIT;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetSrcTrigInWaitIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_SRCTRIGINWAIT = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetDestTrigInWaitIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_DESTRIGINWAIT = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+void AdaSetTrigOutAckWaitIntEn(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_INTREN_Type INTREN;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ INTREN.w = actual_frame->CH_INTREN;
+
+ //Modify registers
+ INTREN.b.INTREN_TRIGOUTACKWAIT = en;
+
+ //Write registers
+ actual_frame->CH_INTREN = INTREN.w;
+}
+
+AdaErrInfoType AdaReadErrorInfo(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_ERRINFO_Type ERRINFO;
+ AdaErrInfoType actual_error_info;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ ERRINFO.w = actual_frame->CH_ERRINFO;
+
+ // Set the Actual status to the struct
+ actual_error_info.BUSERR = ERRINFO.b.BUSERR;
+ actual_error_info.CFGERR = ERRINFO.b.CFGERR;
+ actual_error_info.SRCTRIGINSELERR = ERRINFO.b.SRCTRIGINSELERR;
+ actual_error_info.DESTRIGINSELERR = ERRINFO.b.DESTRIGINSELERR;
+ actual_error_info.TRIGOUTSELERR = ERRINFO.b.TRIGOUTSELERR;
+ actual_error_info.STREAMERR = ERRINFO.b.STREAMERR;
+ actual_error_info.ERRINFO = ERRINFO.b.ERRINFO;
+
+ return actual_error_info;
+}
+
+AdaSwTrigInType AdaSrcSwTigInState(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+
+ //Trigger state struct
+ AdaSwTrigInType sw_trigin_state;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCMD.w = actual_frame->CH_CMD;
+
+ //Get values
+ sw_trigin_state.SWTRIGINREQ = CHCMD.b.SRCSWTRIGINREQ;
+ sw_trigin_state.SWTRIGINTYPE = CHCMD.b.SRCSWTRIGINTYPE;
+
+ //Return state
+ return sw_trigin_state;
+}
+
+AdaSwTrigInType AdaDesSwTigInState(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+
+ //Trigger state struct
+ AdaSwTrigInType sw_trigin_state;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCMD.w = actual_frame->CH_CMD;
+
+ //Get values
+ sw_trigin_state.SWTRIGINREQ = CHCMD.b.DESSWTRIGINREQ;
+ sw_trigin_state.SWTRIGINTYPE = CHCMD.b.DESSWTRIGINTYPE;
+
+ //Return state
+ return sw_trigin_state;
+}
+
+
+uint8_t AdaSwTrigOutState(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCMD.w = actual_frame->CH_CMD;
+
+ //Return state
+ return CHCMD.b.SWTRIGOUTACK;
+}
+
+void AdaDesSwTrigInReq(AdaSwTriggerType_t trigin_type, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCMD.w = actual_frame->CH_CMD;
+
+ //Set values
+ CHCMD.b.DESSWTRIGINREQ = 1;
+ CHCMD.b.DESSWTRIGINTYPE = trigin_type;
+ //Set W1S fields to 0
+ CHCMD.b.ENABLECMD = 0;
+ CHCMD.b.CLEARCMD = 0;
+ CHCMD.b.DISABLECMD = 0;
+ CHCMD.b.STOPCMD = 0;
+ CHCMD.b.PAUSECMD = 0;
+ CHCMD.b.RESUMECMD = 0;
+ CHCMD.b.SRCSWTRIGINREQ = 0;
+ CHCMD.b.SWTRIGOUTACK = 0;
+
+ actual_frame->CH_CMD = CHCMD.w;
+}
+
+void AdaSrcSwTrigInReq(AdaSwTriggerType_t trigin_type, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCMD.w = actual_frame->CH_CMD;
+
+ //Set values
+ CHCMD.b.SRCSWTRIGINREQ = 1;
+ CHCMD.b.SRCSWTRIGINTYPE = trigin_type;
+ //Set W1S fields to 0
+ CHCMD.b.ENABLECMD = 0;
+ CHCMD.b.CLEARCMD = 0;
+ CHCMD.b.DISABLECMD = 0;
+ CHCMD.b.STOPCMD = 0;
+ CHCMD.b.PAUSECMD = 0;
+ CHCMD.b.RESUMECMD = 0;
+ CHCMD.b.DESSWTRIGINREQ = 0;
+ CHCMD.b.SWTRIGOUTACK = 0;
+
+ actual_frame->CH_CMD = CHCMD.w;
+}
+
+void AdaSwTrigOutAck(uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CMD_Type CHCMD;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHCMD.w = actual_frame->CH_CMD;
+
+ //Set values
+ CHCMD.b.SWTRIGOUTACK = 1;
+ //Set W1S fields to 0
+ CHCMD.b.ENABLECMD = 0;
+ CHCMD.b.CLEARCMD = 0;
+ CHCMD.b.DISABLECMD = 0;
+ CHCMD.b.STOPCMD = 0;
+ CHCMD.b.PAUSECMD = 0;
+ CHCMD.b.RESUMECMD = 0;
+ CHCMD.b.DESSWTRIGINREQ = 0;
+ CHCMD.b.SRCSWTRIGINREQ = 0;
+
+ actual_frame->CH_CMD = CHCMD.w;
+}
+
+void AdaSrcTrigInInit(AdaTrigInType src_trigin_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ DMACH_CH_SRCTRIGINCFG_Type SRCTRIGINCFG;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+ SRCTRIGINCFG.w = actual_frame->CH_SRCTRIGINCFG;
+
+ //Modify registers
+ CHCTRL.b.USESRCTRIGIN = src_trigin_params.USETRIGIN;
+ SRCTRIGINCFG.b.SRCTRIGINSEL = src_trigin_params.TRIGINSEL;
+ SRCTRIGINCFG.b.SRCTRIGINTYPE = src_trigin_params.TRIGINTYPE;
+ SRCTRIGINCFG.b.SRCTRIGINMODE = src_trigin_params.TRIGINMODE;
+ SRCTRIGINCFG.b.SRCTRIGINBLKSIZE = src_trigin_params.TRIGINBLKSIZE;
+
+ //Write registers
+ actual_frame->CH_SRCTRIGINCFG = SRCTRIGINCFG.w;
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaSrcTrigInEnable(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+
+ //Modify registers
+ CHCTRL.b.USESRCTRIGIN = en;
+
+ //Write registers
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+
+void AdaDesTrigInInit(AdaTrigInType des_trigin_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_DESTRIGINCFG_Type DESTRIGINCFG;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+ DESTRIGINCFG.w = actual_frame->CH_DESTRIGINCFG;
+
+ //Modify registers
+ CHCTRL.b.USEDESTRIGIN = des_trigin_params.USETRIGIN;
+ DESTRIGINCFG.b.DESTRIGINSEL = des_trigin_params.TRIGINSEL;
+ DESTRIGINCFG.b.DESTRIGINTYPE = des_trigin_params.TRIGINTYPE;
+ DESTRIGINCFG.b.DESTRIGINMODE = des_trigin_params.TRIGINMODE;
+ DESTRIGINCFG.b.DESTRIGINBLKSIZE = des_trigin_params.TRIGINBLKSIZE;
+
+ //Write registers
+ actual_frame->CH_DESTRIGINCFG = DESTRIGINCFG.w;
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaDesTrigInEnable(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+
+ //Modify registers
+ CHCTRL.b.USEDESTRIGIN = en;
+
+ //Write registers
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaTrigOutInit(AdaTrigOutType trigout_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_TRIGOUTCFG_Type TRIGOUTCFG;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+ TRIGOUTCFG.w = actual_frame->CH_TRIGOUTCFG;
+
+ //Modify registers
+ CHCTRL.b.USETRIGOUT = trigout_params.USETRIGOUT;
+ TRIGOUTCFG.b.TRIGOUTSEL = trigout_params.TRIGOUTSEL;
+ TRIGOUTCFG.b.TRIGOUTTYPE = trigout_params.TRIGOUTTYPE;
+
+ //Write registers
+ actual_frame->CH_TRIGOUTCFG = TRIGOUTCFG.w;
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaTrigOutEnable(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+
+ //Modify registers
+ CHCTRL.b.USETRIGOUT = en;
+
+ //Write registers
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaStreamInit(AdaStreamType stream_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_STREAMINTCFG_Type STREAMINTCFG;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+ STREAMINTCFG.w = actual_frame->CH_STREAMINTCFG;
+
+ //Modify registers
+ STREAMINTCFG.b.STREAMTYPE = stream_params.STREAMTYPE;
+
+ //Write registers
+ actual_frame->CH_STREAMINTCFG = STREAMINTCFG.w;
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaStreamEnable(uint8_t en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+
+ //Modify registers
+ CHCTRL.b.USESTREAM = en;
+
+ //Write registers
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+void AdaSetLinkTranAttrs(AdaChannelLinkAttrType link_attr, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_LINKATTR_Type CHLINKATTR;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHLINKATTR.w = actual_frame->CH_LINKATTR;
+
+ //Modify values
+ CHLINKATTR.b.LINKMEMATTRLO = link_attr.LINKMEMATTRLO;
+ CHLINKATTR.b.LINKMEMATTRHI = link_attr.LINKMEMATTRHI;
+ CHLINKATTR.b.LINKSHAREATTR = link_attr.LINKSHAREATTR;
+
+ //Write register
+ actual_frame->CH_LINKATTR = CHLINKATTR.w ;
+}
+
+void AdaSetCmdLink(AdaCmdLinkType cmd_link_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_LINKADDR_Type LINKADDR;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ LINKADDR.w = actual_frame->CH_LINKADDR;
+
+ //Modify registers
+ LINKADDR.b.LINKADDREN = cmd_link_params.LINKADDREN;
+ LINKADDR.b.LINKADDR = (uint32_t)(0x3FFFFFFF & (cmd_link_params.LINKADDR >> 2));
+
+ //Write registers
+ actual_frame->CH_LINKADDR = LINKADDR.w;
+ actual_frame->CH_LINKADDRHI = (uint32_t)(cmd_link_params.LINKADDR >> 32);
+}
+
+uint8_t AdaGetLinkTranMemAttrs(uint32_t ch_num, uint8_t security)
+{
+ uint8_t return_value;
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_LINKATTR_Type CHLINKATTR;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHLINKATTR.w = actual_frame->CH_LINKATTR;
+
+ //Return value
+ return_value = (CHLINKATTR.b.LINKMEMATTRHI<<4) & CHLINKATTR.b.LINKMEMATTRLO;
+ return return_value;
+}
+
+uint8_t AdaGetLinkTranShareAttrs(uint32_t ch_num, uint8_t security)
+{
+ uint8_t return_value;
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_LINKATTR_Type CHLINKATTR;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read register
+ CHLINKATTR.w = actual_frame->CH_LINKATTR;
+
+ //Return value
+ return_value = CHLINKATTR.b.LINKSHAREATTR;
+ return return_value;
+}
+
+uint64_t AdaGetCmdLinkAddr(uint32_t ch_num, uint8_t security)
+{
+ uint64_t return_value=0;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_LINKADDR_Type CHLINKADDR;
+ volatile DMACH_CH_LINKADDRHI_Type CHLINKADDRHI;
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ CHLINKADDR.w = actual_frame->CH_LINKADDR;
+ CHLINKADDRHI.w = actual_frame->CH_LINKADDRHI;
+
+ // Return address
+ return_value = CHLINKADDRHI.b.LINKADDRHI;
+ return_value = (return_value<<32 ) | (CHLINKADDR.b.LINKADDR<<2);
+ return return_value;
+}
+
+
+void AdaAutoRestart(AdaAutoRestartType restart_params, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_AUTOCFG_Type AUTOCFG;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ AUTOCFG.w = actual_frame->CH_AUTOCFG;
+
+ //Modify registers
+ AUTOCFG.b.CMDRESTARTCNT = restart_params.CMDRESTARTCNT;
+ AUTOCFG.b.CMDRESTARTINFEN = restart_params.CMDRESTARTINFEN;
+
+ //Write registers
+ actual_frame->CH_AUTOCFG = AUTOCFG.w;
+}
+
+void AdaSetRestartCntr(uint16_t restartcnt, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_AUTOCFG_Type AUTOCFG;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ AUTOCFG.w = actual_frame->CH_AUTOCFG;
+
+ //Modify registers
+ AUTOCFG.b.CMDRESTARTCNT = restartcnt;
+
+ //Write registers
+ actual_frame->CH_AUTOCFG = AUTOCFG.w;
+}
+
+void AdaInfRestart(uint8_t inf_restart_en, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_AUTOCFG_Type AUTOCFG;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ AUTOCFG.w = actual_frame->CH_AUTOCFG;
+
+ //Modify registers
+ AUTOCFG.b.CMDRESTARTINFEN = inf_restart_en;
+
+ //Write registers
+ actual_frame->CH_AUTOCFG = AUTOCFG.w;
+}
+
+void AdaSetGPO(uint64_t gpo_value, uint32_t width, uint32_t ch_num, uint8_t security)
+{
+ //Pointer for the actual channel
+ DMACH_TypeDef * actual_frame;
+ //Temporary unions for register read-write
+ volatile DMACH_CH_GPOEN0_Type GPOEN0;
+ volatile DMACH_CH_GPOVAL0_Type GPOVAL0;
+ volatile DMACH_CH_CTRL_Type CHCTRL;
+ // Enable mask
+ uint32_t en_mask = 0;
+
+ //Get the actual channel frame
+ actual_frame = GetChannelPtr(ch_num, security);
+
+ //Read registers
+ CHCTRL.w = actual_frame->CH_CTRL;
+ GPOEN0.w = actual_frame->CH_GPOEN0;
+ GPOVAL0.w = actual_frame->CH_GPOVAL0;
+
+ //Modify registers
+ if(width<32){
+ for(int i = 0; i<width; i++){
+ en_mask = (en_mask<<1)+1;
+ }
+ GPOEN0.b.GPOEN0 = en_mask;
+ }
+ else{
+ GPOEN0.b.GPOEN0 = 0xFFFFFFFF;
+ }
+
+ GPOVAL0.b.GPOVAL0 = (0xFFFFFFFF & gpo_value);
+
+ CHCTRL.b.USEGPO = 1;
+
+
+ //Write registers
+ actual_frame->CH_GPOEN0 = GPOEN0.w;
+ actual_frame->CH_GPOVAL0 = GPOVAL0.w;
+ actual_frame->CH_CTRL = CHCTRL.w;
+}
+
+uint32_t GetNonSecCollIrqStat(void)
+{
+ return DMANSECCTRL_NS->NSEC_CHINTRSTATUS0;
+}
+uint32_t GetSecCollIrqStat(void)
+{
+ return DMASECCTRL_S->SEC_CHINTRSTATUS0;
+}
+
+AdaCombIrqType AdaReadNSecCombIrqStatus(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+ AdaCombIrqType actual_irq_stat;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Set the Actual status to the struct
+ actual_irq_stat.INTR_ANYCHINTR = STATUS.b.INTR_ANYCHINTR;
+ actual_irq_stat.INTR_ALLCHIDLE = STATUS.b.INTR_ALLCHIDLE;
+ actual_irq_stat.INTR_ALLCHSTOPPED = STATUS.b.INTR_ALLCHSTOPPED;
+ actual_irq_stat.INTR_ALLCHPAUSED = STATUS.b.INTR_ALLCHPAUSED;
+
+ return actual_irq_stat;
+}
+AdaCombIrqType AdaReadSecCombIrqStatus(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+ AdaCombIrqType actual_irq_stat;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Set the Actual status to the struct
+ actual_irq_stat.INTR_ANYCHINTR = STATUS.b.INTR_ANYCHINTR;
+ actual_irq_stat.INTR_ALLCHIDLE = STATUS.b.INTR_ALLCHIDLE;
+ actual_irq_stat.INTR_ALLCHSTOPPED = STATUS.b.INTR_ALLCHSTOPPED;
+ actual_irq_stat.INTR_ALLCHPAUSED = STATUS.b.INTR_ALLCHPAUSED;
+
+ return actual_irq_stat;
+}
+
+uint8_t AdaNSecCombinedIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ANYCHINTR;
+}
+
+uint8_t AdaSecCombinedIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ANYCHINTR;
+}
+
+uint8_t AdaNSecAllIdleIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ALLCHIDLE;
+}
+
+uint8_t AdaSecAllIdleIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ALLCHIDLE;
+}
+
+uint8_t AdaNSecAllStoppedIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ALLCHSTOPPED;
+}
+
+uint8_t AdaSecAllStoppedIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ALLCHSTOPPED;
+}
+
+uint8_t AdaNSecAllPausedIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ALLCHPAUSED;
+}
+
+uint8_t AdaSecAllPausedIrqState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.INTR_ALLCHPAUSED;
+}
+
+AdaCombIrqClrType AdaReadSecCombStatus(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+ AdaCombIrqClrType actual_stat;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Set the Actual status to the struct
+ actual_stat.STAT_ALLCHIDLE = STATUS.b.STAT_ALLCHIDLE;
+ actual_stat.STAT_ALLCHSTOPPED = STATUS.b.STAT_ALLCHSTOPPED;
+ actual_stat.STAT_ALLCHPAUSED = STATUS.b.STAT_ALLCHPAUSED;
+
+ return actual_stat;
+}
+
+AdaCombIrqClrType AdaReadNSecCombStatus(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+ AdaCombIrqClrType actual_stat;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Set the Actual status to the struct
+ actual_stat.STAT_ALLCHIDLE = STATUS.b.STAT_ALLCHIDLE;
+ actual_stat.STAT_ALLCHSTOPPED = STATUS.b.STAT_ALLCHSTOPPED;
+ actual_stat.STAT_ALLCHPAUSED = STATUS.b.STAT_ALLCHPAUSED;
+
+ return actual_stat;
+}
+
+void AdaClrSecCombIrq(AdaCombIrqClrType clr_state)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = clr_state.STAT_ALLCHIDLE;
+ STATUS.b.STAT_ALLCHSTOPPED = clr_state.STAT_ALLCHSTOPPED;
+ STATUS.b.STAT_ALLCHPAUSED = clr_state.STAT_ALLCHPAUSED;
+
+ DMASECCTRL_S->SEC_STATUS = STATUS.w;
+}
+
+void AdaClrNSecCombIrq(AdaCombIrqClrType clr_state)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = clr_state.STAT_ALLCHIDLE;
+ STATUS.b.STAT_ALLCHSTOPPED = clr_state.STAT_ALLCHSTOPPED;
+ STATUS.b.STAT_ALLCHPAUSED = clr_state.STAT_ALLCHPAUSED;
+
+ DMANSECCTRL_NS->NSEC_STATUS = STATUS.w;
+}
+
+void AdaClrSecAllChIdleIrq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = 1;
+ STATUS.b.STAT_ALLCHSTOPPED = 0;
+ STATUS.b.STAT_ALLCHPAUSED = 0;
+
+ DMASECCTRL_S->SEC_STATUS = STATUS.w;
+}
+
+void AdaClrNSecAllChIdleIrq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = 1;
+ STATUS.b.STAT_ALLCHSTOPPED = 0;
+ STATUS.b.STAT_ALLCHPAUSED = 0;
+
+ DMANSECCTRL_NS->NSEC_STATUS = STATUS.w;
+}
+
+void AdaClrSecAllChStoppedIrq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = 0;
+ STATUS.b.STAT_ALLCHSTOPPED = 1;
+ STATUS.b.STAT_ALLCHPAUSED = 0;
+
+ DMASECCTRL_S->SEC_STATUS = STATUS.w;
+}
+
+void AdaClrNSecAllChStoppedIrq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = 0;
+ STATUS.b.STAT_ALLCHSTOPPED = 1;
+ STATUS.b.STAT_ALLCHPAUSED = 0;
+
+ DMANSECCTRL_NS->NSEC_STATUS = STATUS.w;
+}
+
+void AdaClrSecAllChPausedIrq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = 0;
+ STATUS.b.STAT_ALLCHSTOPPED = 0;
+ STATUS.b.STAT_ALLCHPAUSED = 1;
+
+ DMASECCTRL_S->SEC_STATUS = STATUS.w;
+}
+
+void AdaClrNSecAllChPausedIrq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Set the Actual status to the struct
+ STATUS.b.STAT_ALLCHIDLE = 0;
+ STATUS.b.STAT_ALLCHSTOPPED = 0;
+ STATUS.b.STAT_ALLCHPAUSED = 1;
+
+ DMANSECCTRL_NS->NSEC_STATUS = STATUS.w;
+}
+
+void AdaSecCombIrqEn(AdaCombIrqEnType irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ANYCHINTR = irq_en.INTREN_ANYCHINTR;
+ CTRL.b.INTREN_ALLCHIDLE = irq_en.INTREN_ALLCHIDLE;
+ CTRL.b.INTREN_ALLCHSTOPPED = irq_en.INTREN_ALLCHSTOPPED;
+ CTRL.b.INTREN_ALLCHPAUSED = irq_en.INTREN_ALLCHPAUSED;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecCombIrqEn(AdaCombIrqEnType irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ANYCHINTR = irq_en.INTREN_ANYCHINTR;
+ CTRL.b.INTREN_ALLCHIDLE = irq_en.INTREN_ALLCHIDLE;
+ CTRL.b.INTREN_ALLCHSTOPPED = irq_en.INTREN_ALLCHSTOPPED;
+ CTRL.b.INTREN_ALLCHPAUSED = irq_en.INTREN_ALLCHPAUSED;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecCombCtrlIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ANYCHINTR = irq_en;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecCombCtrlIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ANYCHINTR = irq_en;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecAllChIdleIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ALLCHIDLE = irq_en;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecAllChIdleIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ALLCHIDLE = irq_en;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecAllChStoppedIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ALLCHSTOPPED = irq_en;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecAllChStoppedIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ALLCHSTOPPED = irq_en;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecAllChPausedIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ALLCHPAUSED = irq_en;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecAllChPausedIrqEn(uint8_t irq_en)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ALLCHPAUSED = irq_en;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+
+void AdaSecIrqCombine(uint8_t en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ANYCHINTR = en;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecIrqCombine(uint8_t en)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.INTREN_ANYCHINTR = en;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecAllChStopReq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.ALLCHSTOP = 1;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecAllChStopReq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.ALLCHSTOP = 1;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecAllChPauseReq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.ALLCHPAUSE = 1;
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecAllChPauseReq(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.ALLCHPAUSE = 1;
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecDisMinPwr(uint8_t dis_min_pwr)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMASECCTRL_S->SEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.DISMINPWR = (3 & dis_min_pwr);
+
+ DMASECCTRL_S->SEC_CTRL = CTRL.w;
+}
+
+void AdaNSecDisMinPwr(uint8_t dis_min_pwr)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CTRL_Type CTRL;
+
+ //Read registers
+ CTRL.w = DMANSECCTRL_NS->NSEC_CTRL;
+
+ // Set the Actual status to the struct
+ CTRL.b.DISMINPWR = (3 & dis_min_pwr);
+
+ DMANSECCTRL_NS->NSEC_CTRL = CTRL.w;
+}
+
+void AdaSecSetChParams(AdaCombChCfgType ch_params)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CHCFG_Type CHCFG;
+ volatile DMASECCTRL_SEC_CHPTR_Type CHPTR;
+
+ //Read registers
+ CHCFG.w = DMASECCTRL_S->SEC_CHCFG;
+ CHPTR.w = DMASECCTRL_S->SEC_CHPTR;
+
+ // Set the Actual status to the struct
+ CHPTR.b.CHPTR = ch_params.CHPTR;
+ CHCFG.b.CHID = ch_params.CHID;
+ CHCFG.b.CHIDVLD = ch_params.CHIDVLD;
+ CHCFG.b.CHPRIV = ch_params.CHPRIV;
+
+ DMASECCTRL_S->SEC_CHPTR = CHPTR.w;
+ DMASECCTRL_S->SEC_CHCFG = CHCFG.w;
+}
+
+void AdaNSecSetChParams(AdaCombChCfgType ch_params)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CHCFG_Type CHCFG;
+ volatile DMANSECCTRL_NSEC_CHPTR_Type CHPTR;
+
+ //Read registers
+ CHCFG.w = DMANSECCTRL_NS->NSEC_CHCFG;
+ CHPTR.w = DMANSECCTRL_NS->NSEC_CHPTR;
+
+ // Set the Actual status to the struct
+ CHPTR.b.CHPTR = ch_params.CHPTR;
+ CHCFG.b.CHID = ch_params.CHID;
+ CHCFG.b.CHIDVLD = ch_params.CHIDVLD;
+ CHCFG.b.CHPRIV = ch_params.CHPRIV;
+
+ DMANSECCTRL_NS->NSEC_CHPTR = CHPTR.w;
+ DMANSECCTRL_NS->NSEC_CHCFG = CHCFG.w;
+}
+
+void AdaSecSetChPtr(uint8_t ch)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CHPTR_Type CHPTR;
+
+ //Read registers
+ CHPTR.w = DMASECCTRL_S->SEC_CHPTR;
+
+ // Set the Actual channel pointer
+ CHPTR.b.CHPTR = ch;
+
+ DMASECCTRL_S->SEC_CHPTR = CHPTR.w;
+}
+
+void AdaNSecSetChPtr(uint8_t ch)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CHPTR_Type CHPTR;
+
+ //Read registers
+ CHPTR.w = DMANSECCTRL_NS->NSEC_CHPTR;
+
+ // Set the Actual channel pointer
+ CHPTR.b.CHPTR = ch;
+
+ DMANSECCTRL_NS->NSEC_CHPTR = CHPTR.w;
+}
+
+void AdaSecSetChId(uint8_t ch, uint16_t chid)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CHCFG_Type CHCFG;
+ // Set Channel pointer
+ printf("Set Channel Pointer");
+ AdaSecSetChPtr(ch);
+
+ printf("Read Secure config");
+ //Read registers
+ CHCFG.w = DMASECCTRL_S->SEC_CHCFG;
+ printf("Set CHID");
+
+ // Set the Actual channel pointer
+ CHCFG.b.CHID = chid;
+ CHCFG.b.CHIDVLD = 1;
+
+ DMASECCTRL_S->SEC_CHCFG = CHCFG.w;
+}
+
+void AdaNSecSetChId(uint8_t ch, uint16_t chid)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CHCFG_Type CHCFG;
+
+ // Set Channel pointer
+ AdaNSecSetChPtr(ch);
+
+ //Read registers
+ CHCFG.w = DMANSECCTRL_NS->NSEC_CHCFG;
+
+ // Set the Actual channel pointer
+ CHCFG.b.CHID = chid;
+ CHCFG.b.CHIDVLD = 1;
+
+ DMANSECCTRL_NS->NSEC_CHCFG = CHCFG.w;
+}
+
+void AdaSecSetChPrivileged(uint8_t ch, uint8_t privileged)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_CHCFG_Type CHCFG;
+ // Set Channel pointer
+ AdaSecSetChPtr(ch);
+
+ //Read registers
+ CHCFG.w = DMASECCTRL_S->SEC_CHCFG;
+
+ // Set the Actual channel pointer
+ CHCFG.b.CHPRIV = privileged;
+
+ DMASECCTRL_S->SEC_CHCFG = CHCFG.w;
+}
+
+void AdaNSecSetChPrivileged(uint8_t ch, uint8_t privileged)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_CHCFG_Type CHCFG;
+
+ // Set Channel pointer
+ AdaNSecSetChPtr(ch);
+
+ //Read registers
+ CHCFG.w = DMANSECCTRL_NS->NSEC_CHCFG;
+
+ // Set the Actual channel pointer
+ CHCFG.b.CHPRIV = privileged;
+
+ DMANSECCTRL_NS->NSEC_CHCFG = CHCFG.w;
+}
+
+//Set channel Security Configuration
+void AdaSetChSecMappig(uint32_t mapping)
+{
+ DMASECCFG_S->SCFG_CHSEC0 = mapping;
+}
+
+void AdaSetChSecurity(uint32_t ch_num, uint32_t security)
+{
+ volatile uint32_t actual_security;
+ volatile uint32_t ch_mask;
+ ch_mask = (1<<ch_num);
+ actual_security = DMASECCFG_S->SCFG_CHSEC0;
+ DMASECCFG_S->SCFG_CHSEC0 = (actual_security&(~ch_mask)) | ((security<<ch_num) & ch_mask);
+}
+void AdaSetTrigInSecMappig(uint32_t mapping)
+{
+ DMASECCFG_S->SCFG_TRIGINSEC0 = mapping;
+}
+
+void AdaSetTrigInSecurity(uint32_t trig_num, uint8_t security)
+{
+ uint32_t actual_security;
+ uint32_t trig_mask;
+ trig_mask = (1<<trig_num);
+ actual_security = DMASECCFG_S->SCFG_TRIGINSEC0;
+ DMASECCFG_S->SCFG_TRIGINSEC0 = (actual_security&(~trig_mask)) | ((security<<trig_num) & trig_mask);
+}
+
+void AdaSetTrigOutSecMappig(uint32_t mapping)
+{
+ DMASECCFG_S->SCFG_TRIGOUTSEC0 = mapping;
+}
+
+void AdaSetTrigOutSecurity(uint32_t trig_num, uint8_t security)
+{
+ uint32_t actual_security;
+ uint32_t trig_mask;
+ trig_mask = (1<<trig_num);
+ actual_security = DMASECCFG_S->SCFG_TRIGOUTSEC0;
+ DMASECCFG_S->SCFG_TRIGOUTSEC0 = (actual_security&(~trig_mask)) | ((security<<trig_num) & trig_mask);
+}
+
+void AdaSecViolationIrqEn(uint8_t en)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCFG_SCFG_CTRL_Type SCFG_CTRL;
+
+ //Read registers
+ SCFG_CTRL.w = DMASECCFG_S->SCFG_CTRL;
+
+ // Set the Actual irq enable
+ SCFG_CTRL.b.INTREN_SECACCVIO = en;
+
+ DMASECCFG_S->SCFG_CTRL = SCFG_CTRL.w;
+}
+
+void AdaSecViolationResp(uint8_t resp)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCFG_SCFG_CTRL_Type SCFG_CTRL;
+
+ //Read registers
+ SCFG_CTRL.w = DMASECCFG_S->SCFG_CTRL;
+
+ // Set the Actual irq enable
+ SCFG_CTRL.b.RSPTYPE_SECACCVIO = resp;
+
+ DMASECCFG_S->SCFG_CTRL = SCFG_CTRL.w;
+}
+
+
+void AdaSecConfigLock()
+{
+ //Temporary unions for register read-write
+ volatile DMASECCFG_SCFG_CTRL_Type SCFG_CTRL;
+
+ //Read registers
+ SCFG_CTRL.w = DMASECCFG_S->SCFG_CTRL;
+
+ // Lock Security config
+ SCFG_CTRL.b.SEC_CFG_LCK = 1;
+
+ DMASECCFG_S->SCFG_CTRL = SCFG_CTRL.w;
+}
+
+uint8_t AdaSecViolationIrqState(void)
+{
+ //Read registers
+ return (1 & DMASECCFG_S->SCFG_INTRSTATUS);
+}
+
+void AdaClrSecViolationIrq(void)
+{
+ //Read registers
+ DMASECCFG_S->SCFG_INTRSTATUS = 1;
+}
+
+uint8_t AdaNSecAllPausedState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMANSECCTRL_NSEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMANSECCTRL_NS->NSEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.STAT_ALLCHPAUSED;
+}
+
+uint8_t AdaSecAllPausedState(void)
+{
+ //Temporary unions for register read-write
+ volatile DMASECCTRL_SEC_STATUS_Type STATUS;
+
+ //Read registers
+ STATUS.w = DMASECCTRL_S->SEC_STATUS;
+
+ // Re the Actual status to the struct
+ return STATUS.b.STAT_ALLCHPAUSED;
+}
+
+
+uint32_t AdaGetChNum(uint8_t security) {
+ //Temporary unions for register read-write
+ volatile DMAINFO_DMA_BUILDCFG0_Type info_bcfg;
+ //Read registers
+ if(security==0){
+ info_bcfg.w = DMAINFO_S->DMA_BUILDCFG0;
+ }
+ else {
+ info_bcfg.w = DMAINFO_NS->DMA_BUILDCFG0;
+ }
+ //Return number of channels
+ return (info_bcfg.b.NUM_CHANNELS + 1);
+}
+uint32_t AdaGetTrigInNum(uint8_t security) {
+ //Temporary unions for register read-write
+ volatile DMAINFO_DMA_BUILDCFG1_Type info_bcfg;
+ //Read registers
+ if(security==0){
+ info_bcfg.w = DMAINFO_S->DMA_BUILDCFG1;
+ }
+ else {
+ info_bcfg.w = DMAINFO_NS->DMA_BUILDCFG1;
+ }
+ //Return number of trigger outputs
+ return info_bcfg.b.NUM_TRIGGER_IN;
+}
+uint32_t AdaGetTrigOutNum(uint8_t security) {
+ //Temporary unions for register read-write
+ volatile DMAINFO_DMA_BUILDCFG1_Type info_bcfg;
+ //Read registers
+ if(security==0){
+ info_bcfg.w = DMAINFO_S->DMA_BUILDCFG1;
+ }
+ else {
+ info_bcfg.w = DMAINFO_NS->DMA_BUILDCFG1;
+ }
+ //Return number of trigger inputs
+ return info_bcfg.b.NUM_TRIGGER_OUT;
+}
+
+uint32_t AdaSecurityViolationTestRead(void)
+{
+ return DMASECCTRL_NS->SEC_CHINTRSTATUS0;
+}
+
+ #endif /* __DMA_COMMAND_LIB_C */
+
diff --git a/software/lib/sw_lib/devices/src/uart_stdout.c b/software/lib/sw_lib/devices/src/uart_stdout.c
index bee199a4fef8ebe4c00f7f36bfb16514772226ee..0c294296c5d0576d50fa2baafec0973a0c42748f 100644
--- a/software/lib/sw_lib/devices/src/uart_stdout.c
+++ b/software/lib/sw_lib/devices/src/uart_stdout.c
@@ -39,6 +39,8 @@ void UartStdOutInit(void)
CMSDK_UART2->CTRL = 0x00; // disable whie reprogramming
CMSDK_UART2->BAUDDIV = BAUDCLKDIV; // (100MHz/BAUDRATE) in 16.4 format
CMSDK_UART2->CTRL = 0x01; // TX, standard UART2
+ CMSDK_USRT2->BAUDDIV = 3; // (prescaler value)
+ CMSDK_USRT2->CTRL = 0x03; // RX+TX, FT1248 USRT
return;
}
@@ -46,15 +48,22 @@ void UartStdOutInit(void)
// Output a character
unsigned char UartPutc(unsigned char my_ch)
{
+ if ((CMSDK_USRT2->CTRL & 1)==0) {
while (CMSDK_UART2->STATE & 1); // Wait if Transmit Holding register full
CMSDK_UART2->DATA = my_ch; // write to transmit holding register
- return (my_ch);
+ CMSDK_USRT2->DATA = my_ch; // (also write to transmit holding register)
+ } else {
+ while (CMSDK_USRT2->STATE & 1); // Wait if Transmit Holding register full
+ CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
+ }
+ return (my_ch);
}
// Get a character
unsigned char UartGetc(void)
{
- while (((CMSDK_UART2->STATE & 2)==0));
- return (CMSDK_UART2->DATA);
+ while (((CMSDK_UART2->STATE & 2)==0) & ((CMSDK_USRT2->STATE & 2)==0));
+ if ((CMSDK_UART2->STATE & 2)==2) return (CMSDK_UART2->DATA);
+ if ((CMSDK_USRT2->STATE & 2)==2) return (CMSDK_USRT2->DATA);
}
void UartEndSimulation(void)
diff --git a/software/lib/sw_lib/host/include/sys_intr_map.h b/software/lib/sw_lib/host/include/sys_intr_map.h
index ce61979329fded1bd0fb4ca7a96c01b80b91079c..0ddbc0ac9c0c19bc2ab62199da2c70517bdda530 100644
--- a/software/lib/sw_lib/host/include/sys_intr_map.h
+++ b/software/lib/sw_lib/host/include/sys_intr_map.h
@@ -21,9 +21,14 @@
#define CNTPS_INTR 29
#define CNTPNS_INTR 30
//SPIs
-#define UART0_TX_INTR 32
-#define UART0_RX_INTR 33
-#define UART0_TX_OVR_INTR 34
-#define UART0_RX_OVR_INTR 35
-#define UART0_COMB_INTR 36
-#define TIMER0_INTR 37
+#define DMA350_CH0_INTR 32
+#define DMA350_CH1_INTR 33
+#define DMA350_CH2_INTR 34
+#define DMA350_CH3_INTR 35
+#define DMA350_COM_INTR 36
+#define UART0_TX_INTR 37
+#define UART0_RX_INTR 38
+#define UART0_TX_OVR_INTR 39
+#define UART0_RX_OVR_INTR 40
+#define UART0_COMB_INTR 41
+#define TIMER0_INTR 42
diff --git a/software/lib/sw_lib/host/include/sys_memory_map.h b/software/lib/sw_lib/host/include/sys_memory_map.h
index f9915afeb5725553cb89a3cacd6a10f9baa00466..0b71e67f3d94d27098dbc78b49324285c31360ab 100644
--- a/software/lib/sw_lib/host/include/sys_memory_map.h
+++ b/software/lib/sw_lib/host/include/sys_memory_map.h
@@ -26,6 +26,7 @@
#define PERIPHERAL_BASE 0x40000000UL
#define SYS_UART0_BASE PERIPHERAL_BASE
#define TIMER0_BASE 0x40001000UL
+#define SYS_USRT0_BASE 0x40002000UL
#define DAP_DBG_BASE 0x60000000UL
diff --git a/software/src/dma350_tests/dma350_tests.c b/software/src/dma350_tests/dma350_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..9ea5904df44e536906487822e065b91a2a181898
--- /dev/null
+++ b/software/src/dma350_tests/dma350_tests.c
@@ -0,0 +1,205 @@
+#include "uart_stdout.h"
+#include <stdio.h>
+#include "system.h"
+#include "sys_memory_map.h"
+#include "dma_350_command_lib.h"
+#include "sys_intr_map.h"
+#include "gic400.h"
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
+
+#define COPY_ADDR_SRC 0x00800000UL
+#define COPY_ADDR_DST 0x00800F00UL
+#define COPY_ADDR_DST_long 0x80000000000UL
+#define DATA_SIZE 64
+
+// IRQ Handlers
+static void DMA_CH0_IRQ();
+static void DMA_CH1_IRQ();
+static void DMA_CH2_IRQ();
+static void DMA_CH3_IRQ();
+void DMAClearChIrq(uint8_t ch);
+
+
+AdaChannelSettingsType ch_settings = {
+ .CHPRIO = 0,
+ .CLEARCMD = 1,
+ .REGRELOADTYPE = RELOAD_DISABLED,
+ .DONETYPE = DONETYPE_EOF_CMD,
+ .DONEPAUSEEN = 0,
+ .SRCMAXBURSTLEN = 15,
+ .DESMAXBURSTLEN = 15
+ };
+AdaChannelSrcAttrType ch_srcattr = {
+ .SRCMEMATTRLO = 4,
+ .SRCMEMATTRHI = 4,
+ .SRCSHAREATTR = 0,
+ .SRCNONSECATTR = 1,
+ .SRCPRIVATTR = 0
+ };
+AdaChannelDesAttrType ch_desattr = {
+ .DESMEMATTRLO = 4,
+ .DESMEMATTRHI = 4,
+ .DESSHAREATTR = 0,
+ .DESNONSECATTR = 1,
+ .DESPRIVATTR = 0
+ };
+AdaChannelLinkAttrType ch_linkattr = {
+ .LINKMEMATTRLO = 4,
+ .LINKMEMATTRHI = 4,
+ .LINKSHAREATTR = 0
+ };
+AdaBaseCommandType command_base = {
+ .SRCADDR = COPY_ADDR_SRC, // Read from M0 interface
+ .DESADDR = COPY_ADDR_DST, // Write to M0 interface
+ .SRCXSIZE = DATA_SIZE,
+ .DESXSIZE = DATA_SIZE,
+ .TRANSIZE = BITS_32
+ };
+AdaBaseCommandType command_base_long = {
+ .SRCADDR = COPY_ADDR_SRC, // Read from M0 interface
+ .DESADDR = COPY_ADDR_DST_long, // Write to M0 interface
+ .SRCXSIZE = DATA_SIZE,
+ .DESXSIZE = DATA_SIZE,
+ .TRANSIZE = BITS_32
+ };
+
+Ada1DIncrCommandType command_1d_incr = {
+ .SRCXADDRINC = 1, // Autoincrement by transaction size
+ .DESXADDRINC = 1 // Autoincrement by transaction size
+ };
+
+ // Set the transfer types (2D and wrapping support)
+ // The transaction type is 1D basic transfer
+ AdaWrapCommandType command_1d_wrap = {
+ .FILLVAL = 0,
+ .XTYPE = OPTYPE_CONTINUE,
+ .YTYPE = OPTYPE_DISABLE
+ };
+AdaIrqEnType ch_irqs = {
+ .INTREN_DONE = 1,
+ .INTREN_ERR = 1,
+ .INTREN_DISABLED = 0,
+ .INTREN_STOPPED = 0
+ };
+
+
+
+int main(){
+ uint32_t ch_num;
+ uint32_t trig_in_num;
+ uint32_t trig_out_num;
+
+ UartStdOutInit();
+
+ printf("DMA 350 tests - SoCLabs MegaSoC\n");
+
+ gic_initialise_intr(DMA350_CH0_INTR, 0, 1, 0);
+ gic_install_handler(DMA350_CH0_INTR, &DMA_CH0_IRQ);
+ gic_enable_interrupt(DMA350_CH0_INTR);
+
+ gic_initialise_intr(DMA350_CH1_INTR, 0, 1, 0);
+ gic_install_handler(DMA350_CH1_INTR, &DMA_CH1_IRQ);
+ gic_enable_interrupt(DMA350_CH1_INTR);
+
+ gic_initialise_intr(DMA350_CH2_INTR, 0, 1, 0);
+ gic_install_handler(DMA350_CH2_INTR, &DMA_CH2_IRQ);
+ gic_enable_interrupt(DMA350_CH2_INTR);
+
+ gic_initialise_intr(DMA350_CH3_INTR, 0, 1, 0);
+ gic_install_handler(DMA350_CH3_INTR, &DMA_CH3_IRQ);
+ gic_enable_interrupt(DMA350_CH3_INTR);
+
+ enable_irq();
+
+
+ //Get the configuration information
+ ch_num = AdaGetChNum(SECURE);
+ trig_in_num = AdaGetTrigInNum(SECURE);
+ trig_out_num = AdaGetTrigOutNum(SECURE);
+
+ //Display the config parameters read
+ printf("Number of DMA channels: %d \n", ch_num);
+ printf("Number of DMA trigger inputs: %d \n", trig_in_num);
+ printf("Number of DMA trigger outputs: %d \n", trig_out_num);
+
+ AdaSecAllChStopReq();
+
+ printf("TEST 1: DMA transfer to/from CPU side SRAM\n");
+ for (uint32_t ch=0; ch < ch_num-1; ch++) {
+ //
+ // Write all settings to the DMA registers
+ AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
+ Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
+ SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
+ AdaSetIntEn(ch_irqs, ch, SECURE);
+ // Start DMA operation and wait for done IRQ
+ printf("DMA CH:%d Enabling\n",ch);
+ AdaEnable(ch, SECURE);
+ call_wfi();
+ printf("DMA CH:%d transfer finished\n",ch);
+ }
+ printf("TEST 2: DMA transfer from CPU side SRAM to System side\n");
+ for (uint32_t ch=0; ch < 2; ch++) {
+ //
+ // Write all settings to the DMA registers
+ AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
+ AdaLong1DCommand(command_base_long, ch, SECURE);
+ SetAda1DIncrRegs(command_1d_incr, ch, SECURE);
+ SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
+ AdaSetIntEn(ch_irqs, ch, SECURE);
+ // Start DMA operation and wait for done IRQ
+ printf("DMA CH:%d Enabling\n",ch);
+ AdaEnable(ch, SECURE);
+ call_wfi();
+ printf("DMA CH:%d transfer finished\n",ch);
+ }
+
+ UartEndSimulation();
+
+}
+
+void DMAClearChIrq(uint8_t ch) {
+ // Check the source of the interrupt and clear interrupts
+ AdaStatType ST = AdaReadStatus(ch, NON_SECURE);
+ if (ST.STAT_DONE == 1) {
+ AdaClearChDone(ch, NON_SECURE);
+ } else if (ST.STAT_ERR == 1) {
+ AdaClearChError(ch, NON_SECURE);
+ } else if (ST.STAT_DISABLED == 1) {
+ AdaClearChDisabled(ch, NON_SECURE);
+ } else if (ST.STAT_STOPPED == 1) {
+ AdaClearChStopped(ch, NON_SECURE);
+ } else {
+ printf("Unknown IRQ on CH%d!\n", ch);
+ }
+}
+
+void DMA_CH0_IRQ(){
+ disable_irq();
+ DMAClearChIrq(0);
+ printf("DMA CH0 IRQ\n");
+ enable_irq();
+}
+
+void DMA_CH1_IRQ(){
+ disable_irq();
+ DMAClearChIrq(1);
+ printf("DMA CH1 IRQ\n");
+ enable_irq();
+}
+
+void DMA_CH2_IRQ(){
+ disable_irq();
+ DMAClearChIrq(2);
+ printf("DMA CH2 IRQ\n");
+ enable_irq();
+}
+
+void DMA_CH3_IRQ(){
+ disable_irq();
+ DMAClearChIrq(3);
+ printf("DMA CH3 IRQ\n");
+ enable_irq();
+}
diff --git a/software/src/dma350_tests/makefile b/software/src/dma350_tests/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..67006019ad3aedae10b8b7d1ec45ac4594e1c2af
--- /dev/null
+++ b/software/src/dma350_tests/makefile
@@ -0,0 +1,63 @@
+##------------------------------------------------------------------------------
+## The confidential and proprietary information contained in this file may
+## only be used by a person authorised under and to the extent permitted
+## by a subsisting licensing agreement from Arm Limited or its affiliates.
+##
+## (C) COPYRIGHT 2018-2021 Arm Limited or its affiliates.
+## ALL RIGHTS RESERVED
+##
+## This entire notice must be reproduced on all copies of this file
+## and copies of this file may only be made by a person if such person is
+## permitted to do so under the terms of a subsisting license agreement
+## from Arm Limited or its affiliates.
+##
+## Release Information : SSE710-r0p0-00rel0
+##
+##------------------------------------------------------------------------------
+## Purpose : C test Makefile
+##------------------------------------------------------------------------------
+
+TEST_PATH := $(CURDIR)
+TEST_ID := $(notdir $(TEST_PATH))
+
+export TEST_PATH
+export TEST_ID
+
+#############################################################################
+#### Variables globally applied for all images ######
+#############################################################################
+
+ifeq ($(TEST_VERBOSITY), 1)
+ GLOBAL_TESTDEFINES := -DTEST_VERBOSITY_HIGH
+endif
+
+#############################################################################
+############# Variables necessary for compiling image for Cortex A53 ########
+#############################################################################
+
+APP_TESTDEFINES :=
+
+APP_SCAT := default
+APP_LD_FLAGS :=
+APP_AS_FLAGS := -DMASTER_CPU_REF=0x0 -DMASTER_CLUS_REF=0x0 -DTTBR0_BASE=0x02100000 -DVBAR_ADDR=0x02000000
+APP_AS_INC_DIR :=
+APP_C_FLAGS := $(APP_TESTDEFINES) $(GLOBAL_TESTDEFINES) -DTTBR0_BASE=0x02100000
+APP_C_INC_DIR := $(TEST_PATH)
+APP_SRC := dma350_tests.c
+
+export APP_SRC
+export APP_C_FLAGS
+export APP_C_INC_DIR
+export APP_AS_FLAGS
+export APP_AS_INC_DIR
+export APP_LD_FLAGS
+export APP_SCAT
+
+###############################################################################
+###############################################################################
+###############################################################################
+
+include $(SOCLABS_MEGASOC_TECH_DIR)/software/lib/common/Makefile.sim
+
+
+