From 1e2cc64e3dba67ec4d5f7ddd7f4d4fe0c77fd455 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Thu, 24 Oct 2024 14:36:35 +0100
Subject: [PATCH] v1.1 Added SL AHB QSPI, working but inefficient due to HSIZE
---
.gitignore | 2 +
flist/IP/AHB_SRAM.flist | 6 --
flist/IP/AHB_SRAM_BEHAV.flist | 4 -
flist/IP/Corstone101.flist | 4 +-
flist/megasoc_tech_BEHAV.flist | 4 +-
flist/megasoc_tech_FPGA.flist | 3 +-
logical/ahb_SRAM/FPGA/sl_ahb_sram.v | 56 -----------
logical/ahb_SRAM/behavioural/sl_ahb_sram.v | 63 -------------
logical/ahb_SRAM/sl_ahb_sram.v | 94 -------------------
logical/sl_ahb_qspi | 2 +-
.../top_megasoc_tech/megasoc_tech_wrapper.v | 71 ++++++--------
.../nic400_megasoc_main.xml | 27 +++---
software/lib/common/Makefile.c_host | 2 +-
software/lib/sw_lib/apps/src/system.c | 13 +--
software/lib/sw_lib/devices/src/qspi_flash.c | 4 +-
software/lib/sw_lib/host/src/sys_utils.c | 6 +-
software/src/bootloader/bootloader.c | 18 ++--
software/src/gic_tests/gic_tests.c | 6 ++
software/src/hello_world/hello_world.c | 3 +-
software/src/mem_tests/mem_tests.c | 4 +-
20 files changed, 86 insertions(+), 306 deletions(-)
delete mode 100644 flist/IP/AHB_SRAM.flist
delete mode 100644 flist/IP/AHB_SRAM_BEHAV.flist
delete mode 100644 logical/ahb_SRAM/FPGA/sl_ahb_sram.v
delete mode 100644 logical/ahb_SRAM/behavioural/sl_ahb_sram.v
delete mode 100644 logical/ahb_SRAM/sl_ahb_sram.v
diff --git a/.gitignore b/.gitignore
index 7c0e140..80af083 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,5 +7,7 @@ logical/nic400_megasoc_main
software/build
+socrates/CortexA53_1/build.log
+socrates/sie300/sie300_axi5_sram_ctrl_1/build.log
.ecmproject
.project
\ No newline at end of file
diff --git a/flist/IP/AHB_SRAM.flist b/flist/IP/AHB_SRAM.flist
deleted file mode 100644
index e51da72..0000000
--- a/flist/IP/AHB_SRAM.flist
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/ahb_SRAM/sl_ahb_sram.v
-$(ARM_IP_LIBRARY_PATH)/Corstone-101/BP210-r1p1-00rel0/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_fpga_sram.v
-$(ARM_IP_LIBRARY_PATH)/Corstone-101/BP210-r1p1-00rel0/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
-// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
diff --git a/flist/IP/AHB_SRAM_BEHAV.flist b/flist/IP/AHB_SRAM_BEHAV.flist
deleted file mode 100644
index e52ffd7..0000000
--- a/flist/IP/AHB_SRAM_BEHAV.flist
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/ahb_SRAM/behavioural/sl_ahb_sram.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
diff --git a/flist/IP/Corstone101.flist b/flist/IP/Corstone101.flist
index 7ab746b..224c29c 100644
--- a/flist/IP/Corstone101.flist
+++ b/flist/IP/Corstone101.flist
@@ -1,6 +1,6 @@
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v
\ No newline at end of file
diff --git a/flist/megasoc_tech_BEHAV.flist b/flist/megasoc_tech_BEHAV.flist
index 712991e..51769c0 100644
--- a/flist/megasoc_tech_BEHAV.flist
+++ b/flist/megasoc_tech_BEHAV.flist
@@ -24,8 +24,8 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM_wrapper.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
-// -f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/AHB_SRAM_BEHAV.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
+
// ARM IP
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/ARM_Cortex_A53.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/CA53_tarmac.flist
diff --git a/flist/megasoc_tech_FPGA.flist b/flist/megasoc_tech_FPGA.flist
index 5b8f6ba..5e1fd49 100644
--- a/flist/megasoc_tech_FPGA.flist
+++ b/flist/megasoc_tech_FPGA.flist
@@ -22,8 +22,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/logical/SRAM.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/logical/SRAM_wrapper.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
-// -f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/AHB_SRAM.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
// ARM IP
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/ARM_Cortex_A53.flist
-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/CA53_tarmac.flist
diff --git a/logical/ahb_SRAM/FPGA/sl_ahb_sram.v b/logical/ahb_SRAM/FPGA/sl_ahb_sram.v
deleted file mode 100644
index 4d2d734..0000000
--- a/logical/ahb_SRAM/FPGA/sl_ahb_sram.v
+++ /dev/null
@@ -1,56 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoCLabs FPGA SRAM Wrapper
-// - to be substitued with same name file in filelist when moving to ASIC
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module sl_ahb_sram #(
- // System Parameters
- parameter SYS_DATA_W = 32, // System Data Width
- parameter RAM_ADDR_W = 21, // Size of SRAM
- parameter RAM_DATA_W = 32 // Data Width of RAM
-)(
- // --------------------------------------------------------------------------
- // Port Definitions
- // --------------------------------------------------------------------------
- input wire HCLK, // system bus clock
- input wire HRESETn, // system bus reset
- input wire HSEL, // AHB peripheral select
- input wire HREADY, // AHB ready input
- input wire [1:0] HTRANS, // AHB transfer type
- input wire [2:0] HSIZE, // AHB hsize
- input wire HWRITE, // AHB hwrite
- input wire [RAM_ADDR_W-1:0] HADDR, // AHB address bus
- input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data bus
- output wire HREADYOUT, // AHB ready output to S->M mux
- output wire HRESP, // AHB response
- output wire [SYS_DATA_W-1:0] HRDATA // AHB read data bus
-);
-
-
- // AHB to SRAM Behavioural
-cmsdk_ahb_ram_beh #(
- .AW(21),
- .filename("app_flash.v8-a.hex"),
- .WS_N(0),
- .WS_S(0)) u_ahb_sram (
- .HCLK(HCLK), // Clock
- .HRESETn(HRESETn), // Reset
- .HSEL(HSEL), // Device select
- .HADDR(HADDR), // Address
- .HTRANS(HTRANS), // Transfer control
- .HSIZE(HSIZE), // Transfer size
- .HWRITE(HWRITE), // Write control
- .HWDATA(HWDATA), // Write data
- .HREADY(HREADY), // Transfer phase done
- .HREADYOUT(HREADYOUT), // Device ready
- .HRDATA(HRDATA), // Read data output
- .HRESP(HRESP)
- );
-endmodule
\ No newline at end of file
diff --git a/logical/ahb_SRAM/behavioural/sl_ahb_sram.v b/logical/ahb_SRAM/behavioural/sl_ahb_sram.v
deleted file mode 100644
index bf411e4..0000000
--- a/logical/ahb_SRAM/behavioural/sl_ahb_sram.v
+++ /dev/null
@@ -1,63 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoCLabs FPGA SRAM Wrapper
-// - to be substitued with same name file in filelist when moving to ASIC
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module sl_ahb_sram #(
- // System Parameters
- parameter SYS_DATA_W = 32, // System Data Width
- parameter RAM_ADDR_W = 19, // Size of SRAM
- parameter RAM_DATA_W = 32 // Data Width of RAM
-)(
- // --------------------------------------------------------------------------
- // Port Definitions
- // --------------------------------------------------------------------------
- input wire HCLK, // system bus clock
- input wire HRESETn, // system bus reset
- input wire HSEL, // AHB peripheral select
- input wire HREADY, // AHB ready input
- input wire [1:0] HTRANS, // AHB transfer type
- input wire [2:0] HSIZE, // AHB hsize
- input wire HWRITE, // AHB hwrite
- input wire [RAM_ADDR_W-1:0] HADDR, // AHB address bus
- input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data bus
- output wire HREADYOUT, // AHB ready output to S->M mux
- output wire HRESP, // AHB response
- output wire [SYS_DATA_W-1:0] HRDATA // AHB read data bus
-);
-
-
- // AHB to SRAM Behavioural
-
-wire [31:0] SRAMRDATA;
-wire [RAM_ADDR_W-3:0] SRAMADDR;
-wire [3:0] SRAMWEN;
-wire [31:0] SRAMWDATA;
-wire SRAMCS;
-
-cmsdk_ahb_ram_beh #(
- .AW(21),
- .filename("app_flash.v8-a.hex"),
- .WS_N(0),
- .WS_S(0)) u_ahb_sram (
- .HCLK(HCLK), // Clock
- .HRESETn(HRESETn), // Reset
- .HSEL(HSEL), // Device select
- .HADDR(HADDR), // Address
- .HTRANS(HTRANS), // Transfer control
- .HSIZE(HSIZE), // Transfer size
- .HWRITE(HWRITE), // Write control
- .HWDATA(HWDATA), // Write data
- .HREADY(HREADY), // Transfer phase done
- .HREADYOUT(HREADYOUT), // Device ready
- .HRDATA(HRDATA), // Read data output
- .HRESP(HRESP)
- );
-endmodule
\ No newline at end of file
diff --git a/logical/ahb_SRAM/sl_ahb_sram.v b/logical/ahb_SRAM/sl_ahb_sram.v
deleted file mode 100644
index ceb55b3..0000000
--- a/logical/ahb_SRAM/sl_ahb_sram.v
+++ /dev/null
@@ -1,94 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoCLabs FPGA SRAM Wrapper
-// - to be substitued with same name file in filelist when moving to ASIC
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module sl_ahb_sram #(
- // System Parameters
- parameter SYS_DATA_W = 32, // System Data Width
- parameter RAM_ADDR_W = 19, // Size of SRAM
- parameter RAM_DATA_W = 32 // Data Width of RAM
-)(
- // --------------------------------------------------------------------------
- // Port Definitions
- // --------------------------------------------------------------------------
- input wire HCLK, // system bus clock
- input wire HRESETn, // system bus reset
- input wire HSEL, // AHB peripheral select
- input wire HREADY, // AHB ready input
- input wire [1:0] HTRANS, // AHB transfer type
- input wire [2:0] HSIZE, // AHB hsize
- input wire HWRITE, // AHB hwrite
- input wire [RAM_ADDR_W-1:0] HADDR, // AHB address bus
- input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data bus
- output wire HREADYOUT, // AHB ready output to S->M mux
- output wire HRESP, // AHB response
- output wire [SYS_DATA_W-1:0] HRDATA // AHB read data bus
-);
-
-
- // AHB to SRAM Behavioural
-
-wire [31:0] SRAMRDATA;
-wire [RAM_ADDR_W-3:0] SRAMADDR;
-wire [3:0] SRAMWEN;
-wire [31:0] SRAMWDATA;
-wire SRAMCS;
-
-cmsdk_ahb_to_sram #(.AW(RAM_ADDR_W)) u_ahb_to_sram(
- .HCLK(HCLK), // Clock
- .HRESETn(HRESETn), // Reset
- .HSEL(HSEL), // Device select
- .HADDR(HADDR), // Address
- .HTRANS(HTRANS), // Transfer control
- .HSIZE(HSIZE), // Transfer size
- .HWRITE(HWRITE), // Write control
- .HWDATA(HWDATA), // Write data
- .HREADY(HREADY), // Transfer phase done
- .HREADYOUT(HREADYOUT), // Device ready
- .HRDATA(HRDATA), // Read data output
- .HRESP(HRESP),
-
- .SRAMRDATA(SRAMRDATA),
- .SRAMADDR(SRAMADDR),
- .SRAMWEN(SRAMWEN),
- .SRAMWDATA(SRAMWDATA),
- .SRAMCS(SRAMCS)
-);
-
-
-cmsdk_fpga_sram #(.AW(RAM_ADDR_W)) u_fpga_sram(
- .CLK(HCLK),
- .ADDR(SRAMADDR),
- .WDATA(SRAMWDATA),
- .WREN(SRAMWEN),
- .CS(SRAMCS),
- .RDATA(SRAMRDATA)
-);
-
-// cmsdk_ahb_ram_beh #(
-// .AW(21),
-// .filename("app_flash.v8-a.hex"),
-// .WS_N(0),
-// .WS_S(0)) u_ahb_sram (
-// .HCLK(HCLK), // Clock
-// .HRESETn(HRESETn), // Reset
-// .HSEL(HSEL), // Device select
-// .HADDR(HADDR), // Address
-// .HTRANS(HTRANS), // Transfer control
-// .HSIZE(HSIZE), // Transfer size
-// .HWRITE(HWRITE), // Write control
-// .HWDATA(HWDATA), // Write data
-// .HREADY(HREADY), // Transfer phase done
-// .HREADYOUT(HREADYOUT), // Device ready
-// .HRDATA(HRDATA), // Read data output
-// .HRESP(HRESP)
-// );
-endmodule
\ No newline at end of file
diff --git a/logical/sl_ahb_qspi b/logical/sl_ahb_qspi
index 88b0cf6..85fdd66 160000
--- a/logical/sl_ahb_qspi
+++ b/logical/sl_ahb_qspi
@@ -1 +1 @@
-Subproject commit 88b0cf65a75e05d52ef742745cce1c903753f7fd
+Subproject commit 85fdd66f1e488f4e689b62a7afe14f4f26d567ad
diff --git a/logical/top_megasoc_tech/megasoc_tech_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
index 93349ac..031913d 100644
--- a/logical/top_megasoc_tech/megasoc_tech_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
@@ -244,6 +244,7 @@ wire RLAST_DRAM;
wire RVALID_DRAM;
wire RREADY_DRAM;
+wire HSELx_FLASH;
wire [31:0] HADDR_FLASH;
wire [1:0] HTRANS_FLASH;
wire HWRITE_FLASH;
@@ -252,6 +253,7 @@ wire [2:0] HBURST_FLASH;
wire [3:0] HPROT_FLASH;
wire [31:0] HWDATA_FLASH;
wire [31:0] HRDATA_FLASH;
+wire HREADYOUT_FLASH;
wire HREADY_FLASH;
wire HRESP_FLASH;
@@ -520,6 +522,7 @@ nic400_megasoc_main u_nic400_megasoc_main(
.RVALID_DRAM(),
.RREADY_DRAM(),
+ .HSELx_FLASH(HSELx_FLASH),
.HADDR_FLASH(HADDR_FLASH),
.HTRANS_FLASH(HTRANS_FLASH),
.HWRITE_FLASH(HWRITE_FLASH),
@@ -528,6 +531,7 @@ nic400_megasoc_main u_nic400_megasoc_main(
.HPROT_FLASH(HPROT_FLASH),
.HWDATA_FLASH(HWDATA_FLASH),
.HRDATA_FLASH(HRDATA_FLASH),
+ .HREADYOUT_FLASH(HREADYOUT_FLASH),
.HREADY_FLASH(HREADY_FLASH),
.HRESP_FLASH(HRESP_FLASH),
@@ -766,53 +770,38 @@ ROM_wrapper u_ROM_wrapper(
.cfg_gate_resp(1'b0)
);
-// top_ahb_qspi #(.DATA_W(32)) u_sl_ahb_qspi(
-// .HCLK(SYS_CLK),
-// .HRESETn(SYS_RESETn),
-// .PCLK(SYS_CLK),
-// .PRESETn(SYS_RESETn),
-// .HADDR(HADDR_FLASH),
-// .HTRANS(HTRANS_FLASH),
-// .HWRITE(HWRITE_FLASH),
-// .HSIZE(HSIZE_FLASH),
-// .HBURST(HBURST_FLASH),
-// .HPROT(HPROT_FLASH),
-// .HWDATA(HWDATA_FLASH),
-// .HSELx(1'b1),
-// .HRDATA(HRDATA_FLASH),
-// .HREADY(1'b1),
-// .HREADYOUT(HREADY_FLASH),
-// .HRESP(HRESP_FLASH),
-// .PADDR(PADDR_FLASH_CTRL),
-// .PPROT(PPROT_FLASH_CTRL),
-// .PSEL(PSELx_FLASH_CTRL),
-// .PENABLE(PENABLE_FLASH_CTRL),
-// .PWRITE(PWRITE_FLASH_CTRL),
-// .PWDATA(PWDATA_FLASH_CTRL),
-// .PSTRB(PSTRB_FLASH_CTRL),
-// .PRDATA(PRDATA_FLASH_CTRL),
-// .PREADY(PREADY_FLASH_CTRL),
-// .PSLVERR(PSLVERR_FLASH_CTRL),
-// .QSPI_SCLK(QSPI_SCLK),
-// .QSPI_nCS(QSPI_nCS),
-// .QSPI_IO_o(QSPI_IO_o),
-// .QSPI_IO_i(QSPI_IO_i),
-// .QSPI_IO_e(QSPI_IO_e)
-// );
-
-sl_ahb_sram u_sl_ahb_sram(
+top_ahb_qspi #(.DATA_W(32)) u_sl_ahb_qspi(
.HCLK(SYS_CLK),
.HRESETn(SYS_RESETn),
- .HSEL(1'b1),
- .HREADY(1'b1),
+ .PCLK(SYS_CLK),
+ .PRESETn(SYS_RESETn),
+ .HADDR(HADDR_FLASH),
.HTRANS(HTRANS_FLASH),
- .HSIZE(HSIZE_FLASH),
.HWRITE(HWRITE_FLASH),
- .HADDR(HADDR_FLASH),
+ .HSIZE(HSIZE_FLASH),
+ .HBURST(HBURST_FLASH),
+ .HPROT(HPROT_FLASH),
.HWDATA(HWDATA_FLASH),
- .HREADYOUT(HREADY_FLASH),
+ .HSELx(HSELx_FLASH),
+ .HRDATA(HRDATA_FLASH),
+ .HREADY(HREADY_FLASH),
+ .HREADYOUT(HREADYOUT_FLASH),
.HRESP(HRESP_FLASH),
- .HRDATA(HRDATA_FLASH)
+ .PADDR(PADDR_FLASH_CTRL),
+ .PPROT(PPROT_FLASH_CTRL),
+ .PSEL(PSELx_FLASH_CTRL),
+ .PENABLE(PENABLE_FLASH_CTRL),
+ .PWRITE(PWRITE_FLASH_CTRL),
+ .PWDATA(PWDATA_FLASH_CTRL),
+ .PSTRB(PSTRB_FLASH_CTRL),
+ .PRDATA(PRDATA_FLASH_CTRL),
+ .PREADY(PREADY_FLASH_CTRL),
+ .PSLVERR(PSLVERR_FLASH_CTRL),
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e)
);
SRAM_wrapper u_SRAM_wrapper(
diff --git a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
index f263cea..863bdb0 100644
--- a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
+++ b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
@@ -111,18 +111,19 @@
</MasterInterface>
<MasterInterface>
<Name>FLASH</Name>
- <AHBLiteInitiatorMasterProtocol>
+ <AHBLiteTargetMasterProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
+ <AUSEREnabled>false</AUSEREnabled>
<RUSEREnabled>false</RUSEREnabled>
<WUSEREnabled>false</WUSEREnabled>
<ReadIssuing>1</ReadIssuing>
<WriteIssuing>1</WriteIssuing>
<TotalIssuing>1</TotalIssuing>
- <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <TrustZoneMaster>secure</TrustZoneMaster>
<MultiPorted>false</MultiPorted>
<LockSupport>false</LockSupport>
- </AHBLiteInitiatorMasterProtocol>
+ </AHBLiteTargetMasterProtocol>
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
@@ -697,7 +698,7 @@
<multi_ported>false</multi_ported>
<multi_region>false</multi_region>
<name>FLASH</name>
- <protocol>ahb_m</protocol>
+ <protocol>ahb_ms</protocol>
<qv_out>false</qv_out>
<reg>
<impl>present</impl>
@@ -771,7 +772,7 @@
<slave_if_data_width>128</slave_if_data_width>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
- <trustzone>nsec</trustzone>
+ <trustzone>sec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
@@ -1760,7 +1761,7 @@
<out_reads>1</out_reads>
<out_trans>1</out_trans>
<out_writes>1</out_writes>
- <protocol>ahb_m</protocol>
+ <protocol>ahb_ms</protocol>
<ruser>false</ruser>
<src>FLASH</src>
<src_port>FLASH_m</src_port>
@@ -1976,18 +1977,18 @@
<link>
<slave_if>
<name>A53</name>
- <master_if>apb_group0</master_if>
- <master_if>DRAM</master_if>
+ <master_if>ROM</master_if>
<master_if>FLASH</master_if>
- <master_if>DEBUG<parent>apb_group0</parent>
- </master_if>
+ <master_if>RAM</master_if>
+ <master_if>DRAM</master_if>
+ <master_if>GIC</master_if>
+ <master_if>apb_group0</master_if>
<master_if>PERIPHERAL<parent>apb_group0</parent>
</master_if>
<master_if>FLASH_CTRL<parent>apb_group0</parent>
</master_if>
- <master_if>GIC</master_if>
- <master_if>RAM</master_if>
- <master_if>ROM</master_if>
+ <master_if>DEBUG<parent>apb_group0</parent>
+ </master_if>
</slave_if>
</link>
</architecture>
diff --git a/software/lib/common/Makefile.c_host b/software/lib/common/Makefile.c_host
index 6e6ef35..ea6db5c 100644
--- a/software/lib/common/Makefile.c_host
+++ b/software/lib/common/Makefile.c_host
@@ -102,7 +102,7 @@ APP_SRC += $(SW_LIB_PATH)/apps/src/page_table.s
APP_SRC += $(SW_LIB_PATH)/devices/src/gic400.c
# APP_SRC += $(SW_LIB_PATH)/devices/src/watchdog_generic.c
APP_SRC += $(SW_LIB_PATH)/host/src/sys_utils.c
-# APP_SRC += $(SW_LIB_PATH)/devices/src/qspi_flash.c
+APP_SRC += $(SW_LIB_PATH)/devices/src/qspi_flash.c
APP_SRC += $(SW_LIB_PATH)/common/src/system_level_functions.c
APP_SRC += $(SW_LIB_PATH)/devices/src/uart_stdout.c
CPU := -mcpu=cortex-a53
diff --git a/software/lib/sw_lib/apps/src/system.c b/software/lib/sw_lib/apps/src/system.c
index 28de726..8cb2c79 100755
--- a/software/lib/sw_lib/apps/src/system.c
+++ b/software/lib/sw_lib/apps/src/system.c
@@ -217,11 +217,8 @@ int c_print_str(const char * fmt) {
__attribute__((weak)) void TEST_PASS(void) {
// Halt simulation
- char *tube_addr = (char *)SYS_UART0_BASE;
- c_print_str("TEST PASSED OK\n");
- *tube_addr = (char )4;
- __wfi();
-
+ printf("\n** TEST PASSED **\n");
+ UartEndSimulation();
}
/** @brief TEST_FAIL, Terminates Test by printing test FAIL message
@@ -230,10 +227,8 @@ __attribute__((weak)) void TEST_PASS(void) {
__attribute__((weak)) void TEST_FAIL(void) {
// Halt simulation
- char *tube_addr = (char *)SYS_UART0_BASE;
- c_print_str("TEST FAILED\n");
- *tube_addr = (char )4;
- __wfi();
+ printf("\n** TEST FAILED **\n");
+ UartEndSimulation();
}
diff --git a/software/lib/sw_lib/devices/src/qspi_flash.c b/software/lib/sw_lib/devices/src/qspi_flash.c
index 4ec8749..3529fd5 100644
--- a/software/lib/sw_lib/devices/src/qspi_flash.c
+++ b/software/lib/sw_lib/devices/src/qspi_flash.c
@@ -23,12 +23,14 @@ void SET_QPI_MODE(){
}
void qspi_enable_cache(){
+ // Don't enable prefetch, this causes problems for some reason
+ CACHE_CTRL->CCR = 0x00;
uint32_t QSPI_CTRL_tmp;
QSPI_CTRL_tmp=SL_AHB_QSPI->QSPI_CONTROL;
QSPI_CTRL_tmp = QSPI_CTRL_tmp | 1<<8;
SL_AHB_QSPI->QSPI_CONTROL = QSPI_CTRL_tmp;
- CACHE_CTRL->CCR = 0x61;
+ CACHE_CTRL->CCR = 0x01;
while((CACHE_CTRL->SR&0x3)!=2){;}
return;
diff --git a/software/lib/sw_lib/host/src/sys_utils.c b/software/lib/sw_lib/host/src/sys_utils.c
index 39fe34f..5eb90c8 100644
--- a/software/lib/sw_lib/host/src/sys_utils.c
+++ b/software/lib/sw_lib/host/src/sys_utils.c
@@ -98,7 +98,8 @@
------------------------------------------------------------------------------*/
void TEST_PASS(void) {
- call_wfi();
+ printf("\n** TEST PASSED **\n");
+ UartEndSimulation();
}
/**-----------------------------------------------------------------------------
@@ -109,6 +110,7 @@ void TEST_PASS(void) {
------------------------------------------------------------------------------*/
void TEST_FAIL(void) {
- call_wfi();
+ printf("\n** TEST FAILED **\n");
+ UartEndSimulation();
}
diff --git a/software/src/bootloader/bootloader.c b/software/src/bootloader/bootloader.c
index 7f4c0ad..cc6c74f 100644
--- a/software/src/bootloader/bootloader.c
+++ b/software/src/bootloader/bootloader.c
@@ -14,12 +14,18 @@ int main(void) {
printf("\n***SoCLabs MegaSoC***\n");
enable_caches();
enable_caches_el1();
- //spi_reset();
- //int32_t rID = SPI_READ_JEDIC();
- //SET_QPI_MODE();
- //rID = QPI_READ_JEDIC();
- //qspi_enable_cache();
- //qspi_xip_enable();
+ spi_reset();
+ int32_t rID = SPI_READ_JEDIC();
+ SET_QPI_MODE();
+ rID = QPI_READ_JEDIC();
+ qspi_enable_cache();
+ qspi_xip_enable();
+
+ // uint32_t rdata[16];
+ // for (int i=0;i<16;i++){
+ // rdata[i]= QSPI_CACHE->DATA[i];
+ // }
+
printf("***Flash Enabled...Booting***\n\n\n");
void (*main_code)(void) = (void (*)())0x00400000;
diff --git a/software/src/gic_tests/gic_tests.c b/software/src/gic_tests/gic_tests.c
index 29fd1f8..6dc43c5 100644
--- a/software/src/gic_tests/gic_tests.c
+++ b/software/src/gic_tests/gic_tests.c
@@ -1,6 +1,7 @@
#include "uart_stdout.h"
#include "sys_memory_map.h"
#include "sys_intr_map.h"
+#include "system.h"
#include <stdio.h>
#include "gic400.h"
#include "CMSDK.h"
@@ -49,6 +50,11 @@ int main(void) {
// Timer present - continue
errors += timer_interrupt_test_1(CMSDK_TIMER0);
+ if(errors==0){
+ TEST_PASS();
+ } else {
+ TEST_FAIL();
+ }
UartEndSimulation();
}
diff --git a/software/src/hello_world/hello_world.c b/software/src/hello_world/hello_world.c
index 6282327..4ef4171 100644
--- a/software/src/hello_world/hello_world.c
+++ b/software/src/hello_world/hello_world.c
@@ -1,4 +1,5 @@
#include "uart_stdout.h"
+#include "system.h"
#include <stdio.h>
int main(void) {
@@ -6,5 +7,5 @@ int main(void) {
UartStdOutInit();
printf("Hello SoCLabs MegaSoC\n");
- UartEndSimulation();
+ TEST_PASS();
}
\ No newline at end of file
diff --git a/software/src/mem_tests/mem_tests.c b/software/src/mem_tests/mem_tests.c
index 4d9a8db..90fd3d9 100644
--- a/software/src/mem_tests/mem_tests.c
+++ b/software/src/mem_tests/mem_tests.c
@@ -11,9 +11,9 @@ int main(void) {
errors += access_addr_wdata(0x00806000,16,0xCAFECAFE);
if(errors!=0){
- printf("Test Failed\n");
+ TEST_FAIL();
} else {
- printf("Test Passed\n");
+ TEST_PASS();
}
UartEndSimulation();
}
\ No newline at end of file
--
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