diff --git a/.gitignore b/.gitignore
index 80af083907a3066018a7897631bd93657eaf36ba..06cc3b08b3f972c7bb0b0fce9253119438ae3862 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,6 +4,7 @@ logical/sie300
logical/SMC
logical/shared
logical/nic400_megasoc_main
+logical/dma350
software/build
diff --git a/flist/IP/DMA350.flist b/flist/IP/DMA350.flist
new file mode 100644
index 0000000000000000000000000000000000000000..4dbe4f24031686dda214cc84f2ab5d2a8937b212
--- /dev/null
+++ b/flist/IP/DMA350.flist
@@ -0,0 +1,150 @@
+
+
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regmap_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_apb_regmap_conv_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_ro_ro_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_ro_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_rw_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_interface_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_flop.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_sync.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_mux2.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_or.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_idbit_v1.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_ecorevnum.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_top_sldma350_megasoc/verilog/ada_top_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_gen_regif_dmach_0_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_gen_regif_dmach_0_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_gen_regmap_dmach_0_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_gen_fields_coreif_dmach_0_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_gen_coreif_res_dmach_0_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_1d_wr_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_2d_wr_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_1d_rd_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_2d_rd_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_fifo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_cmdlink_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_axi_rd_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_axi_wr_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_axi_stop_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_reg_bank_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_inc_gen_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_stream_wrapper_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_stream_slave_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_stream_master_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_stream_bypass_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_trig_in_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350_megasoc/verilog/ada_channel_0_trig_out_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_gen_regif_dmach_1_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_gen_regif_dmach_1_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_gen_regmap_dmach_1_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_gen_fields_coreif_dmach_1_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_gen_coreif_res_dmach_1_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_1d_wr_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_2d_wr_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_1d_rd_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_2d_rd_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_fifo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_cmdlink_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_axi_rd_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_axi_wr_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_axi_stop_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_reg_bank_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_inc_gen_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_stream_wrapper_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_stream_slave_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_stream_master_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_stream_bypass_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_trig_in_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350_megasoc/verilog/ada_channel_1_trig_out_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_gen_regif_dmach_2_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_gen_regif_dmach_2_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_gen_regmap_dmach_2_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_gen_fields_coreif_dmach_2_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_gen_coreif_res_dmach_2_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_1d_wr_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_1d_rd_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_fifo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_cmdlink_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_axi_rd_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_axi_wr_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_axi_stop_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_reg_bank_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_trig_in_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350_megasoc/verilog/ada_channel_2_trig_out_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_gen_regif_dmach_3_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_gen_regif_dmach_3_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_gen_regmap_dmach_3_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_gen_fields_coreif_dmach_3_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_gen_coreif_res_dmach_3_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_1d_wr_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_1d_rd_ctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_fifo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_cmdlink_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_axi_rd_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_axi_wr_if_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_axi_stop_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_reg_bank_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_trig_in_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350_megasoc/verilog/ada_channel_3_trig_out_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_read_switch_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_read_switch_wrapper_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_write_switch_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_write_switch_wrapper_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_arbiter_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_qv_cmp_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_lrg_arb_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_grant_queue_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_full_f2s_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350_megasoc/verilog/ada_biu_reverse_s2f_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_regif_dmainfo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_regmap_dmainfo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_fields_coreif_dmainfo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_addrmap_dmainfo_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_coreif_dmansecctrl_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_regif_dmansecctrl_sldma350_megasoc_pkg.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_regif_dmansecctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_regmap_dmansecctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_gen_addrmap_dmansecctrl_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_apb_slave_mux_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_dmainfo_reg_bank_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_trigmask_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_trigin_used_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_trigout_used_sldma350_megasoc.sv
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350_megasoc/verilog/ada_ctrl_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_trigmtx_sldma350_megasoc/verilog/ada_trigmtx_sldma350_megasoc.sv
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/dma350/logical/ada_qctrl_sldma350_megasoc/verilog/ada_qctrl_sldma350_megasoc.sv
+
+
diff --git a/flist/IP/nic400_megasoc_main.flist b/flist/IP/nic400_megasoc_main.flist
index d86f90d581c91a9b1d48ad1d4679cc277f6c26b7..823d89cb3b1841de8f869e2458927997397b767e 100644
--- a/flist/IP/nic400_megasoc_main.flist
+++ b/flist/IP/nic400_megasoc_main.flist
@@ -36,6 +36,12 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog/nic400_asib_A53_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog/nic400_asib_A53_rd_spi_cdas_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog/nic400_asib_A53_wr_spi_cdas_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_chan_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_decode_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_maskcntl_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_rd_spi_cdas_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog/nic400_asib_DMA350_wr_spi_cdas_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_megasoc_main.v
@@ -60,11 +66,16 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog/nic400_bm0_wr_spi_tt_s0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml1_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml3_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml2_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml3_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_lrg_arb_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml2_megasoc_main.v
@@ -72,6 +83,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_build_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_map_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_megasoc_main.v
@@ -79,7 +91,9 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_2_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_3_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_4_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_qv_cmp_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml2_megasoc_main.v
@@ -91,6 +105,7 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml3_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml4_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s0_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s1_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_bypass_sync_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_capt_nosync_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog/nic400_cdc_capt_sync_megasoc_main.v
@@ -158,8 +173,8 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_maskcntl_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_master_domain_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog/nic400_ib_ib2_slave_domain_megasoc_main.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_ax_reg_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_ax4_reg_slice_megasoc_main.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_ax_reg_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_buf_reg_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_ful_regd_slice_megasoc_main.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog/nic400_fwd_regd_slice_megasoc_main.v
@@ -171,21 +186,22 @@ $(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_m
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_DRAM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_FLASH/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_GIC/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_PERIPHERAL/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_RAM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_ROM/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/amib_apb_group0/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_A53/verilog
++incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/asib_DMA350/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm0/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/busmatrix_bm1/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/cdc_blocks/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/default_slave_ds_3/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_FLASH_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_GIC_ib/verilog
-+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_PERIPHERAL_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_apb_group0_ib/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/ib_ib2/verilog
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/reg_slice/verilog
+
+
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/nic400/verilog/Axi
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/nic400/verilog/Axi4PC
+incdir+$(SOCLABS_MEGASOC_TECH_DIR)/logical/nic400_megasoc_main/logical/nic400_megasoc_main/nic400/verilog/Ahb
diff --git a/flist/megasoc_tech.flist b/flist/megasoc_tech.flist
new file mode 100644
index 0000000000000000000000000000000000000000..be2fa9195bba334eb6eb52c73d51b6e4b2615d3e
--- /dev/null
+++ b/flist/megasoc_tech.flist
@@ -0,0 +1,32 @@
+//-----------------------------------------------------------------------------
+// MegaSoC Tech Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for MegaSoC Tech IP
+//-----------------------------------------------------------------------------
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/top_megasoc_tech/megasoc_tech_wrapper.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
+
+$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
+
+
+// ARM IP
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/ARM_Cortex_A53.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/CA53_tarmac.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/GIC400.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/nic400_megasoc_main.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/SIE300_SRAM_controller.flist
+// -f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/PL011.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/Corstone101.flist
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/DMA350.flist
diff --git a/flist/megasoc_tech_BEHAV.flist b/flist/megasoc_tech_BEHAV.flist
index 4adcd79e132d4144ef522184462b4ba336ede1b8..a3d51b46d989a0bd9a483c8977be0bfdd3573f05 100644
--- a/flist/megasoc_tech_BEHAV.flist
+++ b/flist/megasoc_tech_BEHAV.flist
@@ -13,25 +13,12 @@
// Abstract : Verilog Command File for MegaSoC Tech IP
//-----------------------------------------------------------------------------
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/top_megasoc_tech/megasoc_tech_wrapper.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/megasoc_tech.flist
$(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/behavioural/ROM_wrapper.v
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/behavioural/SRAM_wrapper.v
-
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
-
-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
-// ARM IP
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/ARM_Cortex_A53.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/CA53_tarmac.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/GIC400.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/nic400_megasoc_main.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/SIE300_SRAM_controller.flist
-// -f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/PL011.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/Corstone101.flist
\ No newline at end of file
diff --git a/flist/megasoc_tech_FPGA.flist b/flist/megasoc_tech_FPGA.flist
index 051caecbdd192120e86ff7371cb946aaf620534b..0961433434a336243ba01f37558502b2d49ce396 100644
--- a/flist/megasoc_tech_FPGA.flist
+++ b/flist/megasoc_tech_FPGA.flist
@@ -13,22 +13,11 @@
// Abstract : Verilog Command File for MegaSoC Tech IP
//-----------------------------------------------------------------------------
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/top_megasoc_tech/megasoc_tech_wrapper.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_cpu_ss.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/megasoc_cpu_subsystem/megasoc_irq_sync.v
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/megasoc_tech.flist
$(SOCLABS_MEGASOC_TECH_DIR)/logical/ROM/behavioural/ROM_wrapper.v
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/logical/SRAM.v
$(SOCLABS_MEGASOC_TECH_DIR)/logical/SRAM/fpga/SRAM_wrapper.v
-$(SOCLABS_MEGASOC_TECH_DIR)/logical/megasoc_subsystems/peripheral_subsystem/megasoc_peripheral_subsystem.v
-f $(SOCLABS_MEGASOC_TECH_DIR)/logical/sl_ahb_qspi/flist/Top/ahb_QSPI_SIM.flist
-// ARM IP
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/ARM_Cortex_A53.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/CA53_tarmac.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/GIC400.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/nic400_megasoc_main.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/SIE300_SRAM_controller.flist
-// -f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/PL011.flist
--f $(SOCLABS_MEGASOC_TECH_DIR)/flist/IP/Corstone101.flist
\ No newline at end of file
diff --git a/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v b/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v
index c68e6b8447210a4cb16bb7a198e6a419e6986b35..3e718e8db658953b80f1f93b17c1440b2759fc3b 100644
--- a/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v
+++ b/logical/ROM/ASIC/TSMC16nm/ROM_wrapper.v
@@ -21,7 +21,7 @@ module ROM_wrapper(
input wire AWVALID,
output wire AWREADY,
- input wire [5:0] AWID,
+ input wire [6:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -39,12 +39,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [5:0] BID,
+ output wire [6:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [5:0] ARID,
+ input wire [6:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -55,7 +55,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [5:0] RID,
+ output wire [6:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/ROM/ROM_wrapper.v b/logical/ROM/ROM_wrapper.v
index 5ca6f54013a761a955bc85d535ad257788bdeb67..cec055291e395a7f762b4fe182d6cf244fc6ca50 100644
--- a/logical/ROM/ROM_wrapper.v
+++ b/logical/ROM/ROM_wrapper.v
@@ -18,7 +18,7 @@ module ROM_wrapper(
input wire AWVALID,
output wire AWREADY,
- input wire [5:0] AWID,
+ input wire [6:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +36,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [5:0] BID,
+ output wire [6:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [5:0] ARID,
+ input wire [6:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +52,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [5:0] RID,
+ output wire [6:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/ROM/behavioural/ROM_wrapper.v b/logical/ROM/behavioural/ROM_wrapper.v
index b490ed0a15ba971b901463b427e6fef7d2483499..466afbfbac98942f070374f422934e00beac537e 100644
--- a/logical/ROM/behavioural/ROM_wrapper.v
+++ b/logical/ROM/behavioural/ROM_wrapper.v
@@ -18,7 +18,7 @@ module ROM_wrapper(
input wire AWVALID,
output wire AWREADY,
- input wire [5:0] AWID,
+ input wire [6:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +36,12 @@ module ROM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [5:0] BID,
+ output wire [6:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [5:0] ARID,
+ input wire [6:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +52,7 @@ module ROM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [5:0] RID,
+ output wire [6:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/behavioural/SRAM_wrapper.v b/logical/SRAM/behavioural/SRAM_wrapper.v
index 408cc9e742290b31a5251cae0e4f59e7a6d3b88a..668ebac5d48010f0dcc6f212b70e5195ee6a3e8a 100644
--- a/logical/SRAM/behavioural/SRAM_wrapper.v
+++ b/logical/SRAM/behavioural/SRAM_wrapper.v
@@ -18,7 +18,7 @@ module SRAM_wrapper(
input wire AWVALID,
output wire AWREADY,
- input wire [5:0] AWID,
+ input wire [6:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +36,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [5:0] BID,
+ output wire [6:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [5:0] ARID,
+ input wire [6:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +52,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [5:0] RID,
+ output wire [6:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/fpga/SRAM_wrapper.v b/logical/SRAM/fpga/SRAM_wrapper.v
index 22e6267119cfa39ae8d4d6ceddf0b1c4f0bf3aa9..334924538359b68560df137d321193cb8933942f 100644
--- a/logical/SRAM/fpga/SRAM_wrapper.v
+++ b/logical/SRAM/fpga/SRAM_wrapper.v
@@ -18,7 +18,7 @@ module SRAM_wrapper(
input wire AWVALID,
output wire AWREADY,
- input wire [5:0] AWID,
+ input wire [6:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +36,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [5:0] BID,
+ output wire [6:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [5:0] ARID,
+ input wire [6:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +52,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [5:0] RID,
+ output wire [6:0] RID,
output wire [63:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
index f03dbf60d15b18f2f35bc4e0de46175aa6c59c9a..ccae6fd92ddc8a8bcf2fe094f3ac74334acf0aaa 100644
--- a/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_system_wrapper.v
@@ -14,15 +14,303 @@
// these peripherals to DRAM
//-----------------------------------------------------------------------------
// Modules instantiated:
-//
+// - ada_top_sldma350_megasoc
//-----------------------------------------------------------------------------
// To Do
// - Everything
module megasoc_tech_system_wrapper(
+ input wire CLK,
+ input wire RESETn,
+
+ input wire DMA350_PWAKEUP,
+ input wire DMA350_PDEBUG,
+ input wire DMA350_PSEL,
+ input wire DMA350_PENABLE,
+ input wire [2:0] DMA350_PPROT,
+ input wire DMA350_PWRITE,
+ input wire [12:0] DMA350_PADDR,
+ input wire [31:0] DMA350_PWDATA,
+ input wire [3:0] DMA350_PSTRB,
+ output wire DMA350_PREADY,
+ output wire DMA350_PSLVERR,
+ output wire [31:0] DMA350_PRDATA,
+
+ output wire DMA350_AWAKEUP_M0,
+ output wire DMA350_AWVALID_M0,
+ output wire [44-1:0] DMA350_AWADDR_M0,
+ output wire [1:0] DMA350_AWBURST_M0,
+ output wire [2-1:0] DMA350_AWID_M0,
+ output wire [7:0] DMA350_AWLEN_M0,
+ output wire [2:0] DMA350_AWSIZE_M0,
+ output wire [3:0] DMA350_AWQOS_M0,
+ output wire [2:0] DMA350_AWPROT_M0,
+ input wire DMA350_AWREADY_M0,
+ output wire [3:0] DMA350_AWCACHE_M0,
+ output wire [3:0] DMA350_AWINNER_M0,
+ output wire [1:0] DMA350_AWDOMAIN_M0,
+
+ output wire DMA350_ARVALID_M0,
+ output wire [44-1:0] DMA350_ARADDR_M0,
+ output wire [1:0] DMA350_ARBURST_M0,
+ output wire [2-1:0] DMA350_ARID_M0,
+ output wire [7:0] DMA350_ARLEN_M0,
+ output wire [2:0] DMA350_ARSIZE_M0,
+ output wire [3:0] DMA350_ARQOS_M0,
+ output wire [2:0] DMA350_ARPROT_M0,
+ input wire DMA350_ARREADY_M0,
+ output wire [3:0] DMA350_ARCACHE_M0,
+ output wire [3:0] DMA350_ARINNER_M0,
+ output wire [1:0] DMA350_ARDOMAIN_M0,
+ output wire DMA350_ARCMDLINK_M0,
+
+ output wire DMA350_WVALID_M0,
+ output wire DMA350_WLAST_M0,
+ output wire [16-1:0] DMA350_WSTRB_M0,
+ output wire [128-1:0] DMA350_WDATA_M0,
+ input wire DMA350_WREADY_M0,
+
+ input wire DMA350_RVALID_M0,
+ input wire [2-1:0] DMA350_RID_M0,
+ input wire DMA350_RLAST_M0,
+ input wire [128-1:0] DMA350_RDATA_M0,
+ input wire [2-1:0] DMA350_RPOISON_M0,
+ input wire [1:0] DMA350_RRESP_M0,
+ output wire DMA350_RREADY_M0,
+
+ input wire DMA350_BVALID_M0,
+ input wire [2-1:0] DMA350_BID_M0,
+ input wire [1:0] DMA350_BRESP_M0,
+ output wire DMA350_BREADY_M0,
+
+ output wire [4-1:0] DMA350_irq_channel,
+ output wire DMA350_irq_comb_nonsec
+
);
+wire DMA350_AWAKEUP_M1;
+wire DMA350_AWVALID_M1;
+wire [44-1:0] DMA350_AWADDR_M1;
+wire [1:0] DMA350_AWBURST_M1;
+wire [2-1:0] DMA350_AWID_M1;
+wire [7:0] DMA350_AWLEN_M1;
+wire [2:0] DMA350_AWSIZE_M1;
+wire [3:0] DMA350_AWQOS_M1;
+wire [2:0] DMA350_AWPROT_M1;
+wire DMA350_AWREADY_M1;
+wire [3:0] DMA350_AWCACHE_M1;
+wire [3:0] DMA350_AWINNER_M1;
+wire [1:0] DMA350_AWDOMAIN_M1;
+wire DMA350_ARVALID_M1;
+wire [44-1:0] DMA350_ARADDR_M1;
+wire [1:0] DMA350_ARBURST_M1;
+wire [2-1:0] DMA350_ARID_M1;
+wire [7:0] DMA350_ARLEN_M1;
+wire [2:0] DMA350_ARSIZE_M1;
+wire [3:0] DMA350_ARQOS_M1;
+wire [2:0] DMA350_ARPROT_M1;
+wire DMA350_ARREADY_M1;
+wire [3:0] DMA350_ARCACHE_M1;
+wire [3:0] DMA350_ARINNER_M1;
+wire [1:0] DMA350_ARDOMAIN_M1;
+wire DMA350_ARCMDLINK_M1;
+wire DMA350_WVALID_M1;
+wire DMA350_WLAST_M1;
+wire [16-1:0] DMA350_WSTRB_M1;
+wire [128-1:0] DMA350_WDATA_M1;
+wire DMA350_WREADY_M1;
+wire DMA350_RVALID_M1;
+wire [2-1:0] DMA350_RID_M1;
+wire DMA350_RLAST_M1;
+wire [128-1:0] DMA350_RDATA_M1;
+wire [2-1:0] DMA350_RPOISON_M1;
+wire [1:0] DMA350_RRESP_M1;
+wire DMA350_RREADY_M1;
+wire DMA350_BVALID_M1;
+wire [2-1:0] DMA350_BID_M1;
+wire [1:0] DMA350_BRESP_M1;
+wire DMA350_BREADY_M1;
+
+
+ada_top_sldma350_megasoc u_megasoc_dma350(
+ .clk(CLK),
+ .resetn(RESETn),
+ .aclken_m0(1'b1),
+ .aclken_m1(1'b1),
+ .pclken(1'b1),
+
+ .clk_qreqn(),
+ .clk_qacceptn(),
+ .clk_qdeny(),
+ .clk_qactive(),
+
+ .preq(),
+ .pstate(),
+ .paccept(),
+ .pdeny(),
+ .pactive(),
+
+ .pwakeup (DMA350_PWAKEUP),
+ .pdebug (DMA350_PDEBUG),
+ .psel (DMA350_PSEL),
+ .penable (DMA350_PENABLE),
+ .pprot (DMA350_PPROT),
+ .pwrite (DMA350_PWRITE),
+ .paddr (DMA350_PADDR),
+ .pwdata (DMA350_PWDATA),
+ .pstrb (DMA350_PSTRB),
+ .pready (DMA350_PREADY),
+ .pslverr (DMA350_PSLVERR),
+ .prdata (DMA350_PRDATA),
+
+ .awakeup_m0 (DMA350_AWAKEUP_M0),
+ .awvalid_m0 (DMA350_AWVALID_M0),
+ .awaddr_m0 (DMA350_AWADDR_M0),
+ .awburst_m0 (DMA350_AWBURST_M0),
+ .awid_m0 (DMA350_AWID_M0),
+ .awlen_m0 (DMA350_AWLEN_M0),
+ .awsize_m0 (DMA350_AWSIZE_M0),
+ .awqos_m0 (DMA350_AWQOS_M0),
+ .awprot_m0 (DMA350_AWPROT_M0),
+ .awready_m0 (DMA350_AWREADY_M0),
+ .awcache_m0 (DMA350_AWCACHE_M0),
+ .awinner_m0 (DMA350_AWINNER_M0),
+ .awdomain_m0 (DMA350_AWDOMAIN_M0),
+ .arvalid_m0 (DMA350_ARVALID_M0),
+ .araddr_m0 (DMA350_ARADDR_M0),
+ .arburst_m0 (DMA350_ARBURST_M0),
+ .arid_m0 (DMA350_ARID_M0),
+ .arlen_m0 (DMA350_ARLEN_M0),
+ .arsize_m0 (DMA350_ARSIZE_M0),
+ .arqos_m0 (DMA350_ARQOS_M0),
+ .arprot_m0 (DMA350_ARPROT_M0),
+ .arready_m0 (DMA350_ARREADY_M0),
+ .arcache_m0 (DMA350_ARCACHE_M0),
+ .arinner_m0 (DMA350_ARINNER_M0),
+ .ardomain_m0 (DMA350_ARDOMAIN_M0),
+ .arcmdlink_m0 (DMA350_ARCMDLINK_M0),
+ .wvalid_m0 (DMA350_WVALID_M0),
+ .wlast_m0 (DMA350_WLAST_M0),
+ .wstrb_m0 (DMA350_WSTRB_M0),
+ .wdata_m0 (DMA350_WDATA_M0),
+ .wready_m0 (DMA350_WREADY_M0),
+ .rvalid_m0 (DMA350_RVALID_M0),
+ .rid_m0 (DMA350_RID_M0),
+ .rlast_m0 (DMA350_RLAST_M0),
+ .rdata_m0 (DMA350_RDATA_M0),
+ .rpoison_m0 (DMA350_RPOISON_M0),
+ .rresp_m0 (DMA350_RRESP_M0),
+ .rready_m0 (DMA350_RREADY_M0),
+ .bvalid_m0 (DMA350_BVALID_M0),
+ .bid_m0 (DMA350_BID_M0),
+ .bresp_m0 (DMA350_BRESP_M0),
+ .bready_m0 (DMA350_BREADY_M0),
+
+ .awakeup_m1 (DMA350_AWAKEUP_M1),
+ .awvalid_m1 (DMA350_AWVALID_M1),
+ .awaddr_m1 (DMA350_AWADDR_M1),
+ .awburst_m1 (DMA350_AWBURST_M1),
+ .awid_m1 (DMA350_AWID_M1),
+ .awlen_m1 (DMA350_AWLEN_M1),
+ .awsize_m1 (DMA350_AWSIZE_M1),
+ .awqos_m1 (DMA350_AWQOS_M1),
+ .awprot_m1 (DMA350_AWPROT_M1),
+ .awready_m1 (DMA350_AWREADY_M1),
+ .awcache_m1 (DMA350_AWCACHE_M1),
+ .awinner_m1 (DMA350_AWINNER_M1),
+ .awdomain_m1 (DMA350_AWDOMAIN_M1),
+ .arvalid_m1 (DMA350_ARVALID_M1),
+ .araddr_m1 (DMA350_ARADDR_M1),
+ .arburst_m1 (DMA350_ARBURST_M1),
+ .arid_m1 (DMA350_ARID_M1),
+ .arlen_m1 (DMA350_ARLEN_M1),
+ .arsize_m1 (DMA350_ARSIZE_M1),
+ .arqos_m1 (DMA350_ARQOS_M1),
+ .arprot_m1 (DMA350_ARPROT_M1),
+ .arready_m1 (DMA350_ARREADY_M1),
+ .arcache_m1 (DMA350_ARCACHE_M1),
+ .arinner_m1 (DMA350_ARINNER_M1),
+ .ardomain_m1 (DMA350_ARDOMAIN_M1),
+ .arcmdlink_m1 (DMA350_ARCMDLINK_M1),
+ .wvalid_m1 (DMA350_WVALID_M1),
+ .wlast_m1 (DMA350_WLAST_M1),
+ .wstrb_m1 (DMA350_WSTRB_M1),
+ .wdata_m1 (DMA350_WDATA_M1),
+ .wready_m1 (DMA350_WREADY_M1),
+ .rvalid_m1 (DMA350_RVALID_M1),
+ .rid_m1 (DMA350_RID_M1),
+ .rlast_m1 (DMA350_RLAST_M1),
+ .rdata_m1 (DMA350_RDATA_M1),
+ .rpoison_m1 (DMA350_RPOISON_M1),
+ .rresp_m1 (DMA350_RRESP_M1),
+ .rready_m1 (DMA350_RREADY_M1),
+ .bvalid_m1 (DMA350_BVALID_M1),
+ .bid_m1 (DMA350_BID_M1),
+ .bresp_m1 (DMA350_BRESP_M1),
+ .bready_m1 (DMA350_BREADY_M1),
+
+ .trig_in_0_req(),
+ .trig_in_0_req_type(),
+ .trig_in_0_ack(),
+ .trig_in_0_ack_type(),
+ .trig_in_1_req(),
+ .trig_in_1_req_type(),
+ .trig_in_1_ack(),
+ .trig_in_1_ack_type(),
+ .trig_out_0_req(),
+ .trig_out_0_ack(),
+ .trig_out_1_req(),
+ .trig_out_1_ack(),
+
+ .irq_channel(),
+ .irq_comb_nonsec(),
+
+ .str_out_0_tvalid(),
+ .str_out_0_tready(),
+ .str_out_0_tdata(),
+ .str_out_0_tstrb(),
+ .str_out_0_tlast(),
+ .str_in_0_tvalid(),
+ .str_in_0_tready(),
+ .str_in_0_tdata(),
+ .str_in_0_tstrb(),
+ .str_in_0_tlast(),
+ .str_in_0_flush(),
+ .str_out_1_tvalid(),
+ .str_out_1_tready(),
+ .str_out_1_tdata(),
+ .str_out_1_tstrb(),
+ .str_out_1_tlast(),
+ .str_in_1_tvalid(),
+ .str_in_1_tready(),
+ .str_in_1_tdata(),
+ .str_in_1_tstrb(),
+ .str_in_1_tlast(),
+ .str_in_1_flush(),
+
+ .gpo_ch_0(),
+ .gpo_ch_1(),
+
+ .allch_stop_req_nonsec(),
+ .allch_stop_ack_nonsec(),
+ .allch_pause_req_nonsec(),
+ .allch_pause_ack_nonsec(),
+
+ .ch_enabled(),
+ .ch_err(),
+ .ch_stopped(),
+ .ch_paused(),
+ .ch_priv(),
+
+ .halt_req(),
+ .restart_req(),
+ .halted(),
+ .boot_en(),
+ .boot_addr(),
+ .boot_memattr(),
+ .boot_shareattr()
+);
endmodule
\ No newline at end of file
diff --git a/logical/top_megasoc_tech/megasoc_tech_wrapper.v b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
index 339dc4490ce4f4446fe274b2ef53358846fe7e90..fecd4441cff427949dc49379a01b468fdd6ec3cc 100644
--- a/logical/top_megasoc_tech/megasoc_tech_wrapper.v
+++ b/logical/top_megasoc_tech/megasoc_tech_wrapper.v
@@ -18,7 +18,7 @@
// sl_ahb_sram (u_sl_ahb_sram)
// SRAM_wrapper (u_SRAM_wrapper)
// megasoc_peripheral_subsystem (u_megasoc_peripheral_subsystem)
-//
+// megasoc_tech_system_wrapper (u_megasoc_tech_system_wrapper)
//-----------------------------------------------------------------------------
// To Do
// - Replace sl_ahb_sram with QSPI controller to use external flash
@@ -131,7 +131,7 @@ module megasoc_tech_wrapper(
);
-parameter ID_W=6;
+parameter ID_W=7;
parameter NUM_SPIS=480;
wire CPU_AWREADYM;
@@ -171,38 +171,38 @@ wire [127: 0] CPU_RDATAM;
wire [ 1: 0] CPU_RRESPM;
wire CPU_RLASTM;
-wire [ID_W-1:0] GIC_ARID;
-wire [31:0] GIC_ARADDR;
-wire [7:0] GIC_ARLEN;
-wire [2:0] GIC_ARSIZE;
-wire [1:0] GIC_ARBURST;
-wire [2:0] GIC_ARPROT;
-wire [2:0] GIC_ARUSER;
-wire GIC_ARVALID;
-wire GIC_ARREADY;
-wire [ID_W-1:0] GIC_RID;
-wire [31:0] GIC_RDATA;
-wire GIC_RLAST;
-wire [1:0] GIC_RRESP;
-wire GIC_RVALID;
-wire GIC_RREADY;
-wire [ID_W-1:0] GIC_AWID;
-wire [31:0] GIC_AWADDR;
-wire [7:0] GIC_AWLEN;
-wire [2:0] GIC_AWSIZE;
-wire [1:0] GIC_AWBURST;
-wire [2:0] GIC_AWPROT;
-wire [2:0] GIC_AWUSER;
-wire GIC_AWVALID;
-wire GIC_AWREADY;
-wire [31:0] GIC_WDATA;
-wire [3:0] GIC_WSTRB;
-wire GIC_WVALID;
-wire GIC_WREADY;
-wire [ID_W-1:0] GIC_BID;
-wire [1:0] GIC_BRESP;
-wire GIC_BVALID;
-wire GIC_BREADY;
+wire [ID_W-2:0] GIC_ARID;
+wire [31:0] GIC_ARADDR;
+wire [7:0] GIC_ARLEN;
+wire [2:0] GIC_ARSIZE;
+wire [1:0] GIC_ARBURST;
+wire [2:0] GIC_ARPROT;
+wire [2:0] GIC_ARUSER;
+wire GIC_ARVALID;
+wire GIC_ARREADY;
+wire [ID_W-2:0] GIC_RID;
+wire [31:0] GIC_RDATA;
+wire GIC_RLAST;
+wire [1:0] GIC_RRESP;
+wire GIC_RVALID;
+wire GIC_RREADY;
+wire [ID_W-2:0] GIC_AWID;
+wire [31:0] GIC_AWADDR;
+wire [7:0] GIC_AWLEN;
+wire [2:0] GIC_AWSIZE;
+wire [1:0] GIC_AWBURST;
+wire [2:0] GIC_AWPROT;
+wire [2:0] GIC_AWUSER;
+wire GIC_AWVALID;
+wire GIC_AWREADY;
+wire [31:0] GIC_WDATA;
+wire [3:0] GIC_WSTRB;
+wire GIC_WVALID;
+wire GIC_WREADY;
+wire [ID_W-2:0] GIC_BID;
+wire [1:0] GIC_BRESP;
+wire GIC_BVALID;
+wire GIC_BREADY;
assign GIC_ARUSER=3'h0;
assign GIC_AWUSER=3'h0;
@@ -361,6 +361,59 @@ wire [ 31: 0] CPU_PRDATADBG;
wire CPU_PREADYDBG;
wire CPU_PSLVERRDBG;
+// DMA 350 APB Interface Wires
+wire [31:0] PADDR_DMA_CTRL;
+wire [31:0] PWDATA_DMA_CTRL;
+wire PWRITE_DMA_CTRL;
+wire [2:0] PPROT_DMA_CTRL;
+wire [3:0] PSTRB_DMA_CTRL;
+wire PENABLE_DMA_CTRL;
+wire PSELx_DMA_CTRL;
+wire [31:0] PRDATA_DMA_CTRL;
+wire PSLVERR_DMA_CTRL;
+wire PREADY_DMA_CTRL;
+
+// DMA 350 AXI Interface Wires
+wire [1:0] AWID_DMA350;
+wire [43:0] AWADDR_DMA350;
+wire [7:0] AWLEN_DMA350;
+wire [2:0] AWSIZE_DMA350;
+wire [1:0] AWBURST_DMA350;
+wire AWLOCK_DMA350;
+wire [3:0] AWCACHE_DMA350;
+wire [2:0] AWPROT_DMA350;
+wire AWVALID_DMA350;
+wire AWREADY_DMA350;
+
+wire [127:0] WDATA_DMA350;
+wire [15:0] WSTRB_DMA350;
+wire WLAST_DMA350;
+wire WVALID_DMA350;
+wire WREADY_DMA350;
+
+wire [1:0] BID_DMA350;
+wire [1:0] BRESP_DMA350;
+wire BVALID_DMA350;
+wire BREADY_DMA350;
+
+wire [1:0] ARID_DMA350;
+wire [43:0] ARADDR_DMA350;
+wire [7:0] ARLEN_DMA350;
+wire [2:0] ARSIZE_DMA350;
+wire [1:0] ARBURST_DMA350;
+wire ARLOCK_DMA350;
+wire [3:0] ARCACHE_DMA350;
+wire [2:0] ARPROT_DMA350;
+wire ARVALID_DMA350;
+wire ARREADY_DMA350;
+
+wire [1:0] RID_DMA350;
+wire [127:0] RDATA_DMA350;
+wire [1:0] RRESP_DMA350;
+wire RLAST_DMA350;
+wire RVALID_DMA350;
+wire RREADY_DMA350;
+
assign CPU_nPRESETDBG = SYS_RESETn;
assign CPU_PCLKENDBG = 1'b1;
assign CPU_PADDRDBG31 = 1'b0;
@@ -371,8 +424,8 @@ wire [5:0] PERI_IRQS;
assign CPU_IRQS={{(NUM_SPIS-38){1'b0}}, PERI_IRQS};
megasoc_cpu_ss #(
- .NUM_GICRID_BITS(ID_W),
- .NUM_GICWID_BITS(ID_W),
+ .NUM_GICRID_BITS(ID_W-1),
+ .NUM_GICWID_BITS(ID_W-1),
.NUM_SPIS(NUM_SPIS)
) u_megasoc_cpu_ss(
.CPU_CLK(SYS_CLK),
@@ -662,6 +715,17 @@ nic400_megasoc_main u_nic400_megasoc_main(
.PSLVERR_DEBUG(CPU_PSLVERRDBG),
.PREADY_DEBUG(CPU_PREADYDBG),
+ .PADDR_DMA_CTRL(PADDR_DMA_CTRL),
+ .PWDATA_DMA_CTRL(PWDATA_DMA_CTRL),
+ .PWRITE_DMA_CTRL(PWRITE_DMA_CTRL),
+ .PPROT_DMA_CTRL(PPROT_DMA_CTRL),
+ .PSTRB_DMA_CTRL(PSTRB_DMA_CTRL),
+ .PENABLE_DMA_CTRL(PENABLE_DMA_CTRL),
+ .PSELx_DMA_CTRL(PSELx_DMA_CTRL),
+ .PRDATA_DMA_CTRL(PRDATA_DMA_CTRL),
+ .PSLVERR_DMA_CTRL(PSLVERR_DMA_CTRL),
+ .PREADY_DMA_CTRL(PREADY_DMA_CTRL),
+
.PADDR_FLASH_CTRL(PADDR_FLASH_CTRL),
.PWDATA_FLASH_CTRL(PWDATA_FLASH_CTRL),
@@ -710,6 +774,42 @@ nic400_megasoc_main u_nic400_megasoc_main(
.RVALID_A53(CPU_RVALIDM),
.RREADY_A53(CPU_RREADYM),
+ .AWID_DMA350(AWID_DMA350),
+ .AWADDR_DMA350(AWADDR_DMA350),
+ .AWLEN_DMA350(AWLEN_DMA350),
+ .AWSIZE_DMA350(AWSIZE_DMA350),
+ .AWBURST_DMA350(AWBURST_DMA350),
+ .AWLOCK_DMA350(AWLOCK_DMA350),
+ .AWCACHE_DMA350(AWCACHE_DMA350),
+ .AWPROT_DMA350(AWPROT_DMA350),
+ .AWVALID_DMA350(AWVALID_DMA350),
+ .AWREADY_DMA350(AWREADY_DMA350),
+ .WDATA_DMA350(WDATA_DMA350),
+ .WSTRB_DMA350(WSTRB_DMA350),
+ .WLAST_DMA350(WLAST_DMA350),
+ .WVALID_DMA350(WVALID_DMA350),
+ .WREADY_DMA350(WREADY_DMA350),
+ .BID_DMA350(BID_DMA350),
+ .BRESP_DMA350(BRESP_DMA350),
+ .BVALID_DMA350(BVALID_DMA350),
+ .BREADY_DMA350(BREADY_DMA350),
+ .ARID_DMA350(ARID_DMA350),
+ .ARADDR_DMA350(ARADDR_DMA350),
+ .ARLEN_DMA350(ARLEN_DMA350),
+ .ARSIZE_DMA350(ARSIZE_DMA350),
+ .ARBURST_DMA350(ARBURST_DMA350),
+ .ARLOCK_DMA350(ARLOCK_DMA350),
+ .ARCACHE_DMA350(ARCACHE_DMA350),
+ .ARPROT_DMA350(ARPROT_DMA350),
+ .ARVALID_DMA350(ARVALID_DMA350),
+ .ARREADY_DMA350(ARREADY_DMA350),
+ .RID_DMA350(RID_DMA350),
+ .RDATA_DMA350(RDATA_DMA350),
+ .RRESP_DMA350(RRESP_DMA350),
+ .RLAST_DMA350(RLAST_DMA350),
+ .RVALID_DMA350(RVALID_DMA350),
+ .RREADY_DMA350(RREADY_DMA350),
+
.clk0clk(SYS_CLK),
.clk0clken(SYS_CLKEN),
.clk0resetn(SYS_RESETn)
@@ -875,4 +975,72 @@ megasoc_peripheral_subsystem u_megasoc_peripheral_subsystem(
.PERI_IRQS(PERI_IRQS)
);
+megasoc_tech_system_wrapper u_megasoc_tech_system_wrapper(
+ .CLK(SYS_CLK),
+ .RESETn(SYS_RESETn),
+
+ .DMA350_PWAKEUP(1'b1),
+ .DMA350_PDEBUG(1'b0),
+ .DMA350_PSEL(PSELx_DMA_CTRL),
+ .DMA350_PENABLE(PENABLE_DMA_CTRL),
+ .DMA350_PPROT(PPROT_DMA_CTRL),
+ .DMA350_PWRITE(PWRITE_DMA_CTRL),
+ .DMA350_PADDR(PADDR_DMA_CTRL),
+ .DMA350_PWDATA(PWDATA_DMA_CTRL),
+ .DMA350_PSTRB(PSTRB_DMA_CTRL),
+ .DMA350_PREADY(PREADY_DMA_CTRL),
+ .DMA350_PSLVERR(PSLVERR_DMA_CTRL),
+ .DMA350_PRDATA(PRDATA_DMA_CTRL),
+
+ .DMA350_AWAKEUP_M0(),
+ .DMA350_AWVALID_M0(AWVALID_DMA350),
+ .DMA350_AWADDR_M0(AWADDR_DMA350),
+ .DMA350_AWBURST_M0(AWBURST_DMA350),
+ .DMA350_AWID_M0(AWID_DMA350),
+ .DMA350_AWLEN_M0(AWLEN_DMA350),
+ .DMA350_AWSIZE_M0(AWSIZE_DMA350),
+ .DMA350_AWQOS_M0(),
+ .DMA350_AWPROT_M0(AWPROT_DMA350),
+ .DMA350_AWREADY_M0(AWREADY_DMA350),
+ .DMA350_AWCACHE_M0(AWCACHE_DMA350),
+ .DMA350_AWINNER_M0(),
+ .DMA350_AWDOMAIN_M0(),
+
+ .DMA350_ARVALID_M0(ARVALID_DMA350),
+ .DMA350_ARADDR_M0(ARADDR_DMA350),
+ .DMA350_ARBURST_M0(ARBURST_DMA350),
+ .DMA350_ARID_M0(ARID_DMA350),
+ .DMA350_ARLEN_M0(ARLEN_DMA350),
+ .DMA350_ARSIZE_M0(ARSIZE_DMA350),
+ .DMA350_ARQOS_M0(),
+ .DMA350_ARPROT_M0(ARPROT_DMA350),
+ .DMA350_ARREADY_M0(ARREADY_DMA350),
+ .DMA350_ARCACHE_M0(ARCACHE_DMA350),
+ .DMA350_ARINNER_M0(),
+ .DMA350_ARDOMAIN_M0(),
+ .DMA350_ARCMDLINK_M0(),
+
+ .DMA350_WVALID_M0(WVALID_DMA350),
+ .DMA350_WLAST_M0(WLAST_DMA350),
+ .DMA350_WSTRB_M0(WSTRB_DMA350),
+ .DMA350_WDATA_M0(WDATA_DMA350),
+ .DMA350_WREADY_M0(WREADY_DMA350),
+
+ .DMA350_RVALID_M0(RVALID_DMA350),
+ .DMA350_RID_M0(RID_DMA350),
+ .DMA350_RLAST_M0(RLAST_DMA350),
+ .DMA350_RDATA_M0(RDATA_DMA350),
+ .DMA350_RPOISON_M0(2'b00),
+ .DMA350_RRESP_M0(RRESP_DMA350),
+ .DMA350_RREADY_M0(RREADY_DMA350),
+
+ .DMA350_BVALID_M0(BVALID_DMA350),
+ .DMA350_BID_M0(BID_DMA350),
+ .DMA350_BRESP_M0(BRESP_DMA350),
+ .DMA350_BREADY_M0(BREADY_DMA350),
+
+ .DMA350_irq_channel(),
+ .DMA350_irq_comb_nonsec()
+);
+
endmodule
\ No newline at end of file
diff --git a/make.cfg b/make.cfg
index b47d755789b772f98fd4af6ea1d310a3e97e04ca..25bf6545a4e318df886f5a5f75d12ccb155cfee9 100644
--- a/make.cfg
+++ b/make.cfg
@@ -2,3 +2,4 @@ CORTEX_A53_IP_LOGICAL_DIR:=/research/AAA/ip_library/Cortex-A53/MP030-r0p4-52rel2
SOC600_IP_DIR:=/research/AAA/ip_library/TM200/TM200-BU-50000-r4p1-00rel0/css600
PCK_600_IP_DIR:=/research/AAA/ip_library/PCK-600/PL608-BU-50000-r0p5-00rel0/pck600
SIE300_IP_LOGICAL_DIR:=$(ARM_IP_LIBRARY_PATH)/BP301/BP301-BU-50000-r1p2-00rel0/sie300/logical
+DMA350_IP_LOGICAL_DIR:=$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical
diff --git a/makefile b/makefile
index dc9ebe04ffe8b55463416b31cf1462dbe52e0b54..5116330a126046d42cb76d9d97b857a7a93fad77 100644
--- a/makefile
+++ b/makefile
@@ -20,8 +20,10 @@ build_cortex_a53:
mkdir $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/
mkdir $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/verilog
@$(CORTEX_A53_IP_LOGICAL_DIR)/shared/tools/bin/RenderCORTEXA53.pl -config $(SOCLABS_MEGASOC_TECH_DIR)/socrates/CortexA53_1/CORTEXA53.cfg -input $(CORTEX_A53_IP_LOGICAL_DIR)/cortexa53/verilog/CORTEXA53_unconfigured.v -output $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/verilog/CORTEXA53.v
+build_dma350:
+ @$(DMA350_IP_LOGICAL_DIR)/generate --config ./socrates/DMA350/config/cfg_dma_megasoc.yaml --output ./logical/dma350/
-build_ip: build_nic400 build_cortex_a53 build_sie300_sram_ctrl
+build_ip: build_nic400 build_cortex_a53 build_sie300_sram_ctrl build_dma350
make_project:
socrates_cli --project megasoc_tech -data ../ --flow AddNewProject
diff --git a/socrates/DMA350/config/cfg_dma_megasoc.yaml b/socrates/DMA350/config/cfg_dma_megasoc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..2de59513968b6368db571821e7d6fac56213a9ee
--- /dev/null
+++ b/socrates/DMA350/config/cfg_dma_megasoc.yaml
@@ -0,0 +1,168 @@
+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Release Information : DMA350-r0p0-00rel0
+#
+# -----------------------------------------------------------------------------
+# Abstract : User Configuration file for ADA DMA
+# -----------------------------------------------------------------------------
+
+#
+# CONFIG_NAME: Name of the configuration.
+# Each unifiqued element and top is suffixed with
+# _${CONFIG_NAME}
+#
+CONFIG_NAME: sldma350_megasoc
+
+#
+# ADDR_WIDTH: Address Bus width
+#
+# Valid values:
+# 32-64
+ADDR_WIDTH: 44
+
+#
+# DATA_WIDTH: Data Bus width
+#
+# Valid values:
+# [32,64,128]
+DATA_WIDTH: 128
+
+#
+# CHID_WIDTH: Width of the configurable channel ID user signal.
+# When set to 0, then the archid and awchid ports are not present on the module.
+#
+# Valid values:
+# 0-16
+CHID_WIDTH: 0
+
+#
+# GPO_WIDTH: Width of GPO output for every channel. When multiple channels have GPOs
+# then the width must be set to the maximum number of GPOs a channel can have,
+# and unused GPO ports need to be left unconnected. When all bits of CH_GPO_MASK
+# is 0, this parameter is not relevant.
+#
+# Valid values:
+# 1-32
+GPO_WIDTH: 1
+
+#
+# CH_GPO_MASK: A bitmask for enabling the GPO port for each channel. The width of the
+# bitmask is NUM_CHANNELS-1. When bit n is set to 1 then the GPO is enabled for
+# channel n and the gpo_ch_n[GPO_WIDTH-1:0] port appears on the module.
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_GPO_MASK: 0x3
+
+#
+# CH_STREAM_MASK: A bitmask for enabling the stream interfaces for each channel.
+# The width of the bitmask is NUM_CHANNELS-1. When bit n is set to 1 then
+# the stream interfaces are enabled for channel n and the relevant ports
+# appears on the module. NOTE: When streaming interface is enabled the actual
+# FIFO size of the channel will be the double of CH_<N>_FIFO_DEPTH
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_STREAM_MASK: 0x3
+
+#
+# CH_<N>_FIFO_DEPTH: Sets the FIFO depth for channel <N> that defines the number of
+# DATA_WIDTH size entries a channel can hold for a transfer. N goes from 0 to
+# NUM_CHANNELS-1. In combination with the TRANSIZE setting of the command, the
+# FIFO depth defines the maximum burst size a channel can support. This setting
+# needs to be aligned with the bandwidth requirements of the channel but it
+# highly affects the area of the design.
+#
+# Valid values:
+# [1,2,4,8,16,32,64]
+CH_0_FIFO_DEPTH: 32
+CH_1_FIFO_DEPTH: 32
+CH_2_FIFO_DEPTH: 32
+CH_3_FIFO_DEPTH: 32
+
+#
+# CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel.
+# The extension contains 2D, WRAP, TMPLT features. Default value enables it for
+# the number of channels.
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_EXT_FEAT_MASK: 0x3
+
+#
+# NUM_CHANNELS: Number of configurable DMA channels.
+#
+# Valid values:
+# 1-8
+NUM_CHANNELS: 4
+
+#
+# NUM_TRIGGER_IN: Number of trigger input ports.
+#
+# Valid values:
+# 0-32
+NUM_TRIGGER_IN: 2
+
+#
+# NUM_TRIGGER_OUT: Number of trigger output ports.
+#
+# Valid values:
+# 0-32
+NUM_TRIGGER_OUT: 2
+
+#
+# TRIG_IN_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger in
+# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_IN-1.
+# When bit n is set to 1 then the trigger in interface is considered asynchronous
+# and the synchronizer logic is placed on the selected input ports.
+#
+# Valid values:
+# 0-(2^NUM_TRIGGER_IN-1)
+TRIG_IN_SYNC_EN_MASK: 0x0
+
+#
+# TRIG_OUT_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger out
+# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_OUT-1.
+# When bit n is set to 1 then the trigger out interface is considered asynchronous
+# and the synchronizer logic is placed on the selected input ports.
+#
+# Valid values:
+# 0-(2^NUM_TRIGGER_OUT-1)
+TRIG_OUT_SYNC_EN_MASK: 0x0
+
+#
+# AXI5_M1_PRESENT: Enables an additional master port. When set the m1 master port is
+# present on the top level port list and additional include file can be used with
+# a System Verilog function that defines which address ranges are mapped to the m1
+# interface.
+#
+# Valid values:
+# [0,1]
+AXI5_M1_PRESENT: 1
+
+#
+# SECEXT_PRESENT: Enables TrustZone security support.
+#
+# Valid values:
+# [0,1]
+SECEXT_PRESENT: 0
+
+
+#
+# AXI5_M1_ADDR_MAP: Select AXI M1 master.
+#
+# Valid values:
+# relative path to logical
+AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_example1.sv
diff --git a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
index 863bdb0c1ecdd98d44bec618c7dfd5ce877cfa2e..ecedde4115f2c657053e672dd042e1ff9d511936 100644
--- a/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
+++ b/socrates/nic400_megasoc_main/nic400_megasoc_main.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>6</GlobalIDWidth>
+ <GlobalIDWidth>7</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -73,8 +73,8 @@
<VIDWidth>6</VIDWidth>
<MultiRegion>false</MultiRegion>
<TrustZoneSlave>secure</TrustZoneSlave>
- <ReadAcceptance>4</ReadAcceptance>
- <WriteAcceptance>4</WriteAcceptance>
+ <ReadAcceptance>32</ReadAcceptance>
+ <WriteAcceptance>32</WriteAcceptance>
<QoSTypeAXI>fixed</QoSTypeAXI>
<QoSValue>0</QoSValue>
<TransactionRateRegulation>false</TransactionRateRegulation>
@@ -226,10 +226,44 @@
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
+ <SlaveInterface>
+ <Name>DMA350</Name>
+ <AXI4SlaveProtocol>
+ <AddressWidth>44</AddressWidth>
+ <DataWidth>128</DataWidth>
+ <VIDWidth>2</VIDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneSlave>secure</TrustZoneSlave>
+ <ReadAcceptance>32</ReadAcceptance>
+ <WriteAcceptance>32</WriteAcceptance>
+ <QoSTypeAXI>fixed</QoSTypeAXI>
+ <QoSValue>0</QoSValue>
+ <TransactionRateRegulation>false</TransactionRateRegulation>
+ <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
+ <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
+ <VNExternal>false</VNExternal>
+ </AXI4SlaveProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ <MultiPorted>false</MultiPorted>
+ <CyclicDependencyAvoidanceScheme>slave_per_id</CyclicDependencyAvoidanceScheme>
+ <LowLatency>false</LowLatency>
+ </SlaveInterface>
+ <MasterInterface>
+ <Name>DMA_CTRL</Name>
+ <APB4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <TrustZoneMasterAPB>non_secure</TrustZoneMasterAPB>
+ <APBGroupRef>apb_group0</APBGroupRef>
+ </APB4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
</Interfaces>
<MemoryMaps>
<MemoryMap>
- <Name>mm0</Name>
+ <Name>CPU_MM</Name>
<MemoryMapSource>
<InterfaceRef>A53</InterfaceRef>
</MemoryMapSource>
@@ -281,6 +315,60 @@
<Range>32768</Range>
<Visibility>true</Visibility>
</MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>DMA_CTRL</InterfaceRef>
+ <Offset>16842752</Offset>
+ <Range>8192</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ </MemoryMap>
+ <MemoryMap>
+ <Name>DMA_MM</Name>
+ <MemoryMapSource>
+ <InterfaceRef>DMA350</InterfaceRef>
+ </MemoryMapSource>
+ <MappedBlock>
+ <InterfaceRef>ROM</InterfaceRef>
+ <Offset>0</Offset>
+ <Range>65536</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>FLASH</InterfaceRef>
+ <Offset>4194304</Offset>
+ <Range>4194304</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>RAM</InterfaceRef>
+ <Offset>8388608</Offset>
+ <Range>65536</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>PERIPHERAL</InterfaceRef>
+ <Offset>1073741824</Offset>
+ <Range>536870912</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>DRAM</InterfaceRef>
+ <Offset>2147483648</Offset>
+ <Range>2147483648</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>DEBUG</InterfaceRef>
+ <Offset>1610612736</Offset>
+ <Range>536870912</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>DMA_CTRL</InterfaceRef>
+ <Offset>16842752</Offset>
+ <Range>8192</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
</MemoryMap>
</MemoryMaps>
<Paths>
@@ -313,15 +401,44 @@
<Target>
<InterfaceRef>GIC</InterfaceRef>
</Target>
+ <Target>
+ <InterfaceRef>DMA_CTRL</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ <Path>
+ <Source>
+ <InterfaceRef>DMA350</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>ROM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>FLASH</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>RAM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>PERIPHERAL</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>DRAM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>DEBUG</InterfaceRef>
+ </Target>
</Targets>
</Path>
</Paths>
<VirtualNetworks/>
</Specification>
<Architecture>
- <NICConfigFile><periph>
- <product_version_info major_group="bu" major_revision="1" major_version="00" minor_code="50000" minor_revision="2" minor_version="0" part_quality="rel" product_code="nic400" />
- <validator_version_info major_revision="22" minor_revision="1" />
+ <NICConfigFile><?xml version="1.0" encoding="iso-8859-1" ?>
+<periph>
+ <product_version_info minor_code="50000" minor_version="0" major_group="bu" minor_revision="2" major_revision="1" product_code="nic400" major_version="00" part_quality="rel"/>
+ <validator_version_info minor_revision="1" major_revision="22"/>
<global>
<address0x0 def="true">bottom</address0x0>
<aruser_width>0</aruser_width>
@@ -336,7 +453,7 @@
<hcg_en>false</hcg_en>
<license_status>unlicensed_nic</license_status>
<periph_id3 def="true">0</periph_id3>
- <pl_id_width>6</pl_id_width>
+ <pl_id_width>7</pl_id_width>
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
@@ -345,7 +462,7 @@
<taxonomy>masterslave</taxonomy>
<thin_links_status def="true">false</thin_links_status>
<uppercase_ext_sig>true</uppercase_ext_sig>
- <virtual_networks />
+ <virtual_networks/>
<virtual_networks_status>false</virtual_networks_status>
<wuser_width>0</wuser_width>
</global>
@@ -354,7 +471,7 @@
</clocks>
<asib>
<address_ranges>
- <name>mm0</name>
+ <name>CPU_MM</name>
<range>
<addr_max>0xFFFF</addr_max>
<addr_min>0x0</addr_min>
@@ -435,6 +552,16 @@
<target>GIC</target>
</remap>
</range>
+ <range>
+ <addr_max>0x1011FFF</addr_max>
+ <addr_min>0x1010000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>DMA_CTRL</target>
+ </remap>
+ </range>
</address_ranges>
<apb_config>false</apb_config>
<apb_slave_no def="true">2</apb_slave_no>
@@ -559,11 +686,203 @@
<vid_width>6</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>20</y>
+ <x>110</x>
+ <y>91</y>
<master_if_port_name>A53_m</master_if_port_name>
<slave_if_port_name>A53_s</slave_if_port_name>
</asib>
+ <asib>
+ <address_ranges>
+ <name>DMA_MM</name>
+ <range>
+ <addr_max>0xFFFF</addr_max>
+ <addr_min>0x0</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>ROM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x7FFFFF</addr_max>
+ <addr_min>0x400000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>FLASH</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x80FFFF</addr_max>
+ <addr_min>0x800000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>RAM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x5FFFFFFF</addr_max>
+ <addr_min>0x40000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>PERIPHERAL</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0xFFFFFFFF</addr_max>
+ <addr_min>0x80000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>DRAM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x7FFFFFFF</addr_max>
+ <addr_min>0x60000000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>DEBUG</target>
+ </remap>
+ </range>
+ </address_ranges>
+ <apb_config>false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <cds>slaveperid</cds>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if_data_width>128</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>DMA350</name>
+ <protocol>axi4</protocol>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <qv>
+ <type>fixed</type>
+ <value>0</value>
+ </qv>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if_addr_width>44</slave_if_addr_width>
+ <slave_if_data_width>128</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>sec</trustzone>
+ <vid_width>2</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>110</x>
+ <y>61</y>
+ <master_if_port_name>DMA350_m</master_if_port_name>
+ <slave_if_port_name>DMA350_s</slave_if_port_name>
+ </asib>
<amib>
<apb_config>false</apb_config>
<apb_slave_no>65</apb_slave_no>
@@ -572,6 +891,7 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>64</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -680,8 +1000,8 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>20</y>
+ <x>890</x>
+ <y>296</y>
<master_if_port_name>ROM_m</master_if_port_name>
<slave_if_port_name>ROM_s</slave_if_port_name>
</amib>
@@ -693,6 +1013,7 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id def="true">false</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -775,8 +1096,8 @@
<trustzone>sec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>40</y>
+ <x>890</x>
+ <y>176</y>
<master_if_port_name>FLASH_m</master_if_port_name>
<slave_if_port_name>FLASH_s</slave_if_port_name>
</amib>
@@ -788,6 +1109,7 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>64</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -896,8 +1218,8 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>60</y>
+ <x>890</x>
+ <y>388</y>
<master_if_port_name>RAM_m</master_if_port_name>
<slave_if_port_name>RAM_s</slave_if_port_name>
</amib>
@@ -909,6 +1231,7 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>64</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1017,8 +1340,8 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>80</y>
+ <x>890</x>
+ <y>342</y>
<master_if_port_name>DRAM_m</master_if_port_name>
<slave_if_port_name>DRAM_s</slave_if_port_name>
</amib>
@@ -1030,6 +1353,7 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>true</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1138,8 +1462,8 @@
<trustzone>sec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>100</y>
+ <x>890</x>
+ <y>222</y>
<master_if_port_name>GIC_m</master_if_port_name>
<slave_if_port_name>GIC_s</slave_if_port_name>
</amib>
@@ -1149,22 +1473,29 @@
<clock_domain>clk0</clock_domain>
<name>PERIPHERAL</name>
<trustzone>nsec</trustzone>
- <x>0</x>
- <y>0</y>
+ <x>902</x>
+ <y>61</y>
</apb_port>
<apb_port>
<clock_domain>clk0</clock_domain>
<name>FLASH_CTRL</name>
<trustzone>nsec</trustzone>
- <x>0</x>
- <y>0</y>
+ <x>902</x>
+ <y>81</y>
</apb_port>
<apb_port>
<clock_domain>clk0</clock_domain>
<name>DEBUG</name>
<trustzone>nsec</trustzone>
- <x>0</x>
- <y>0</y>
+ <x>902</x>
+ <y>101</y>
+ </apb_port>
+ <apb_port>
+ <clock_domain>clk0</clock_domain>
+ <name>DMA_CTRL</name>
+ <trustzone>nsec</trustzone>
+ <x>902</x>
+ <y>121</y>
</apb_port>
<apb_slave_no>60</apb_slave_no>
<clock_boundary>none</clock_boundary>
@@ -1172,6 +1503,7 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id def="true">false</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>true</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -1254,41 +1586,41 @@
<trustzone>nsec</trustzone>
<vn_external def="true">none</vn_external>
<vn_external_bridge def="true">none</vn_external_bridge>
- <x>0</x>
- <y>120</y>
- <master_if_port_name>PERIPHERAL,FLASH_CTRL,DEBUG</master_if_port_name>
+ <x>890</x>
+ <y>61</y>
+ <master_if_port_name>PERIPHERAL,FLASH_CTRL,DEBUG,DMA_CTRL</master_if_port_name>
<slave_if_port_name>apb_group0_s</slave_if_port_name>
</amib>
<inter>
<clock_domain>clk0</clock_domain>
<data_width>64</data_width>
- <expanded>false</expanded>
- <height>40</height>
+ <expanded>true</expanded>
+ <height>127</height>
<impl>mlayer</impl>
<master_if>
<name>axi_m_0</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>63</y>
+ <x>673</x>
+ <y>296</y>
</master_if>
<master_if>
<name>axi_m_1</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>83</y>
+ <x>673</x>
+ <y>342</y>
</master_if>
<master_if>
<name>axi_m_2</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>103</y>
+ <x>673</x>
+ <y>388</y>
</master_if>
<name>bm0</name>
<protocol>axi4</protocol>
<slave_if>
<name>axi_s_0</name>
- <x>0</x>
- <y>63</y>
+ <x>580</x>
+ <y>296</y>
</slave_if>
<sparse>
<cds>slaveperid</cds>
@@ -1380,54 +1712,59 @@
</master_if_port>
</sparse>
<type>busmatrix</type>
- <width>0</width>
- <x>500</x>
- <y>45</y>
+ <width>94</width>
+ <x>626</x>
+ <y>342</y>
<master_if_port_name>axi_m_0,axi_m_1,axi_m_2</master_if_port_name>
<slave_if_port_name>axi_s_0</slave_if_port_name>
</inter>
<inter>
<clock_domain>clk0</clock_domain>
<data_width>128</data_width>
- <expanded>false</expanded>
- <height>80</height>
+ <expanded>true</expanded>
+ <height>242</height>
<impl>mlayer</impl>
<master_if>
<name>axi_m_0</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>108</y>
+ <x>420</x>
+ <y>176</y>
</master_if>
<master_if>
<name>axi_m_1</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>128</y>
+ <x>420</x>
+ <y>61</y>
</master_if>
<master_if>
<name>axi_m_2</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>148</y>
+ <x>420</x>
+ <y>222</y>
</master_if>
<master_if>
<name>axi_m_3</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>168</y>
+ <x>420</x>
+ <y>268</y>
</master_if>
<master_if>
<name>axi_m_4</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>188</y>
+ <x>420</x>
+ <y>91</y>
</master_if>
<name>bm1</name>
<protocol>axi4</protocol>
<slave_if>
<name>axi_s_0</name>
- <x>0</x>
- <y>108</y>
+ <x>327</x>
+ <y>61</y>
+ </slave_if>
+ <slave_if>
+ <name>axi_s_1</name>
+ <x>327</x>
+ <y>91</y>
</slave_if>
<sparse>
<cds>slaveperid</cds>
@@ -1489,6 +1826,123 @@
<type def="true">full</type>
</reg>
</master_if_port>
+ <master_if_port>
+ <name>axi_m_3</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_4</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <sparse>
+ <cds>slaveperid</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_1</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
<master_if_port>
<name>axi_m_2</name>
<reg>
@@ -1575,11 +2029,11 @@
</master_if_port>
</sparse>
<type>busmatrix</type>
- <width>0</width>
- <x>500</x>
- <y>90</y>
+ <width>94</width>
+ <x>373</x>
+ <y>164</y>
<master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3,axi_m_4</master_if_port_name>
- <slave_if_port_name>axi_s_0</slave_if_port_name>
+ <slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
</inter>
<inter>
<apb_config def="true">false</apb_config>
@@ -1589,8 +2043,8 @@
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<master_if>
<name>ib2_m</name>
- <x>0</x>
- <y>0</y>
+ <x>515</x>
+ <y>282</y>
</master_if>
<master_if_data_width>64</master_if_data_width>
<name>ib2</name>
@@ -1696,13 +2150,13 @@
</reg>
<slave_if>
<name>ib2_s</name>
- <x>0</x>
- <y>0</y>
+ <x>486</x>
+ <y>282</y>
</slave_if>
<slave_if_data_width>128</slave_if_data_width>
<type>ib</type>
- <x>0</x>
- <y>0</y>
+ <x>500</x>
+ <y>282</y>
<master_if_port_name>ib2_m</master_if_port_name>
<slave_if_port_name>ib2_s</slave_if_port_name>
</inter>
@@ -1710,13 +2164,13 @@
<name>ds_3</name>
<slave_if>
<name>axi_s_0</name>
- <x>0</x>
- <y>0</y>
+ <x>436</x>
+ <y>101</y>
</slave_if>
<type>default_slave</type>
- <x>500</x>
- <y>500</y>
- <master_if_port_name />
+ <x>450</x>
+ <y>101</y>
+ <master_if_port_name></master_if_port_name>
<slave_if_port_name>axi_s_0</slave_if_port_name>
</inter>
<connect>
@@ -1726,15 +2180,31 @@
<dest>A53</dest>
<dest_port>A53_s</dest_port>
<lock>false</lock>
- <out_reads>4</out_reads>
- <out_trans>8</out_trans>
- <out_writes>4</out_writes>
+ <out_reads>32</out_reads>
+ <out_trans>64</out_trans>
+ <out_writes>32</out_writes>
<protocol>axi4</protocol>
<ruser>false</ruser>
<src>external</src>
<src_port>A53</src_port>
<wuser>false</wuser>
</connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>DMA350</dest>
+ <dest_port>DMA350_s</dest_port>
+ <lock>false</lock>
+ <out_reads>32</out_reads>
+ <out_trans>64</out_trans>
+ <out_writes>32</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>DMA350</src_port>
+ <wuser>false</wuser>
+ </connect>
<connect>
<aruser>false</aruser>
<awuser>false</awuser>
@@ -1863,6 +2333,22 @@
<src_port>DEBUG</src_port>
<wuser>false</wuser>
</connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>DMA_CTRL</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>apb4</protocol>
+ <ruser>false</ruser>
+ <src>apb_group0</src>
+ <src_port>DMA_CTRL</src_port>
+ <wuser>false</wuser>
+ </connect>
<connect>
<dest>ROM</dest>
<dest_port>ROM_s</dest_port>
@@ -1900,9 +2386,20 @@
<dest>bm1</dest>
<dest_port>axi_s_0</dest_port>
<lock>false</lock>
- <out_reads>4</out_reads>
- <out_trans>8</out_trans>
- <out_writes>4</out_writes>
+ <out_reads def="true">32</out_reads>
+ <out_trans>64</out_trans>
+ <out_writes def="true">32</out_writes>
+ <protocol>axi4</protocol>
+ <src>DMA350</src>
+ <src_port>DMA350_m</src_port>
+ </connect>
+ <connect>
+ <dest>bm1</dest>
+ <dest_port>axi_s_1</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">32</out_reads>
+ <out_trans>64</out_trans>
+ <out_writes def="true">32</out_writes>
<protocol>axi4</protocol>
<src>A53</src>
<src_port>A53_m</src_port>
@@ -1977,18 +2474,34 @@
<link>
<slave_if>
<name>A53</name>
+ <master_if>RAM</master_if>
<master_if>ROM</master_if>
+ <master_if>PERIPHERAL<parent>apb_group0</parent>
+ </master_if>
<master_if>FLASH</master_if>
- <master_if>RAM</master_if>
<master_if>DRAM</master_if>
<master_if>GIC</master_if>
<master_if>apb_group0</master_if>
- <master_if>PERIPHERAL<parent>apb_group0</parent>
- </master_if>
<master_if>FLASH_CTRL<parent>apb_group0</parent>
</master_if>
<master_if>DEBUG<parent>apb_group0</parent>
</master_if>
+ <master_if>DMA_CTRL<parent>apb_group0</parent>
+ </master_if>
+ </slave_if>
+ </link>
+ <link>
+ <slave_if>
+ <name>DMA350</name>
+ <master_if>RAM</master_if>
+ <master_if>ROM</master_if>
+ <master_if>PERIPHERAL<parent>apb_group0</parent>
+ </master_if>
+ <master_if>FLASH</master_if>
+ <master_if>DRAM</master_if>
+ <master_if>apb_group0</master_if>
+ <master_if>DEBUG<parent>apb_group0</parent>
+ </master_if>
</slave_if>
</link>
</architecture>