diff --git a/.gitignore b/.gitignore
index 6404f20b813fe94136cb12348681622b669d05c7..331c9ff76b389207a36c97807dc7f131f5ce78f0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,4 +3,7 @@
CheckResults.log
CoherencyCheckConfiguration.config
simulate/
-imp/
\ No newline at end of file
+imp/
+
+system/src/bootrom
+system/src/defines
\ No newline at end of file
diff --git a/fpga/CICD/haps_verification.tcl b/fpga/CICD/haps_verification.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0d75fa0a0caf024e65bb9ff41f09bc5694a39111
--- /dev/null
+++ b/fpga/CICD/haps_verification.tcl
@@ -0,0 +1,16 @@
+# --------
+# main
+# --------
+
+# Connect hw server
+# This part of tcl commands are board related.
+# They can be copied from Vivado Tcl Console after connecting to FPGA successfully
+open_hw
+connect_zc702
+
+# send data to bram
+file2bram 0xc0000000 mat_to_fpga0.txt
+bram2file 0xc0000000 1024 fpga2mat0.txt
+
+# close hardware connection
+close_hw
\ No newline at end of file
diff --git a/fpga/CICD/procs.tcl b/fpga/CICD/procs.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5e3646baa5ba743fe0cf88096c76e920687b4827
--- /dev/null
+++ b/fpga/CICD/procs.tcl
@@ -0,0 +1,154 @@
+# Usage
+# > settings64.bat
+# > vivado -mode batch -source file2bram.tcl
+# Note: Bitstream needs to be downloaded and running first
+
+
+
+
+#################################################
+# file2bram
+# read data from file and send it to BRAM
+# data in file are regard as hex without 0x prefix
+#
+# file2bram $addr $file
+proc file2bram {addr in_fn} {
+
+ puts "----------------------------------------"
+ puts "Start to Write Data From File to BRAM"
+ puts "----------------------------------------"
+
+ # check input arguments
+
+ # open file
+ puts "Input File: $in_fn"
+ set fd [open $in_fn r]
+
+
+ # remove previously created txn if exist
+ if {[llength [get_hw_axi_txns wr_txn_* -quiet]] > 0} {
+ delete_hw_axi_txn [get_hw_axi_txns wr_txn_*]
+ }
+
+ # concatenate lines into a string
+ set data []
+ set line_number 0
+ set wr_nr 0
+ while {[gets $fd cur_line] > 0} {
+ append cur_line $data
+ set data $cur_line; #data should be (line2 line1) style
+ incr line_number
+
+ # create txn when line number gets to 256
+ # since max length of a burst is 256
+ if {$line_number >= 256} {
+ set addr_string [format "0x%x" [expr $addr + $wr_nr * 256 * 4]]
+ create_hw_axi_txn wr_txn_$wr_nr [get_hw_axis] -address $addr_string -data $data -len 256 -type write
+ set line_number 0
+ set data []
+ incr wr_nr
+ }
+
+ }
+
+
+ # create txn for the reminders if there's any
+ if {$line_number > 0} {
+ set addr_string [format "0x%x" [expr $addr + $wr_nr * 256 * 4]]
+ create_hw_axi_txn wr_txn_$wr_nr [get_hw_axis] -address $addr_string -data $data -len $line_number -type write
+ }
+
+ # write file
+ run_hw_axi [get_hw_axi_txns wr_txn_*]
+
+ # wait and check file write successful
+
+ # remove created txn
+ if {[llength [get_hw_axi_txns wr_txn_* -quiet]] > 0} {
+ delete_hw_axi_txn [get_hw_axi_txns wr_txn_*]
+ }
+ # close file
+ close $fd
+
+ puts "Data transfer completes"
+}
+
+
+
+#############################################
+# bram2file
+# read data from bram and save it to file
+# addr: start read address
+# len: length in words
+# out_fn: output file name
+proc bram2file {addr len out_fn} {
+ puts "Output File: $out_fn"
+ # open file for write. file will be replaced if it exists
+ set fd [open $out_fn w]
+
+ set line_number 0
+ set rd_nr 0
+
+
+ # remove previously created txn if exist
+ if {[llength [get_hw_axi_txns rd_txn_* -quiet]] > 0} {
+ delete_hw_axi_txn [get_hw_axi_txns rd_txn_*]
+ }
+
+ while {$len > 0} {
+
+ if {$len >= 256} {
+ set burst_length 256
+ } else {
+ set burst_length $len
+ }
+
+ # create read txn
+ set address_string [format "0x%x" [expr $addr + $rd_nr * $burst_length * 4]]
+ create_hw_axi_txn rd_txn_$rd_nr [get_hw_axis] -address $address_string -len $burst_length -type read
+ # read from jtag
+ run_hw_axi [get_hw_axi_txns rd_txn_$rd_nr]
+ # get read data
+ set data [report_hw_axi_txn -t x4 -w 4 [get_hw_axi_txns rd_txn_$rd_nr]]
+ # data is a list like [addr1 data1 addr2 data2]
+
+ # save data to file
+ for {set data_length [llength $data]; set i 1} { $i < $data_length } { incr i 2 } {
+ puts $fd [lindex $data $i]
+ }
+
+
+
+
+
+ incr rd_nr
+ set len [expr $len - 256]
+ }
+
+ # close file
+ close $fd
+
+ if {[llength [get_hw_axi_txns rd_txn_*]] > 0} {
+ delete_hw_axi_txn [get_hw_axi_txns rd_txn_*]
+ }
+
+
+}
+
+
+
+proc connect_zc702 {} {
+ connect_hw_server -host localhost -port 60001 -url localhost:3121
+ current_hw_target [get_hw_targets */xilinx_tcf/Digilent/210203326797A]
+ set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/210203326797A]
+ open_hw_target
+ current_hw_device [lindex [get_hw_devices] 1]
+ refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 1]
+}
+
+proc connect_haps_sx {} {
+
+}
+
+
+
diff --git a/fpga/targets/haps_sx/fpga_pinmap.xdc b/fpga/targets/haps_sx/fpga_pinmap.xdc
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..04d5014d84dced8fdb98a187240d8e55852186ae 100644
--- a/fpga/targets/haps_sx/fpga_pinmap.xdc
+++ b/fpga/targets/haps_sx/fpga_pinmap.xdc
@@ -0,0 +1,8 @@
+set_property PACKAGE_PIN BK44 [get_ports nRESET_0]
+set_property PACKAGE_PIN BM44 [get_ports CLK_IN_P]
+set_property PACKAGE_PIN BN44 [get_ports CLK_IN_N]
+
+
+set_property IOSTANDARD DIFF_SSTL12 [get_ports CLK_IN_P]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports CLK_IN_N]
+set_property IOSTANDARD LVCMOS12 [get_ports nRESET_0]
diff --git a/fpga/targets/haps_sx/fpga_timing.xdc b/fpga/targets/haps_sx/fpga_timing.xdc
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..71862a424f4440085d5ad3e9db16d35acf98fd07 100644
--- a/fpga/targets/haps_sx/fpga_timing.xdc
+++ b/fpga/targets/haps_sx/fpga_timing.xdc
@@ -0,0 +1 @@
+create_clock -name CLK_IN_P -period 10 [get_ports CLK_IN_P]
diff --git a/fpga/targets/haps_sx/megasoc_design_wrapper.v b/fpga/targets/haps_sx/megasoc_design_wrapper.v
index e73f2491d9d014a2e29a66fbb4131f7e7d49b0be..0959e0ed9e9d5ff473acd6df53702137f4ac8918 100644
--- a/fpga/targets/haps_sx/megasoc_design_wrapper.v
+++ b/fpga/targets/haps_sx/megasoc_design_wrapper.v
@@ -11,67 +11,41 @@
`timescale 1 ps / 1 ps
module megasoc_design_wrapper
- (
- inout wire QSPI_D0,
- inout wire QSPI_D1,
- inout wire QSPI_D2,
- inout wire QSPI_D3,
- output wire QSPI_SCLK,
- output wire QSPI_nCS,
+ (CLK_IN_P,
+ CLK_IN_N,
+ //QSPI_IO_e_0,
+ //QSPI_IO_i_0,
+ //QSPI_IO_o_0,
+ //QSPI_SCLK_0,
+ //QSPI_nCS_0,
+ nRESET_0);
- input wire CS_TDI,
- output wire CS_TDO, // SWV / JTAG TDO
- inout wire CS_TMS, // SWD I/O / JTAG TMS
- input wire CS_TCK, // SWD Clk / JTAG TCK
- input wire CS_nSRST,
- input wire CS_nTRST,
- input wire CS_nDET
-
-
-
- );
-wire SWDITMS_0;
-wire SWDOEN_0;
-wire SWDO_0;
-
-assign CS_TMS = (SWDOEN_0==1'b1) ? SWDO_0 : 1'bz;
-assign SWDITMS_0 = CS_TMS;
-
-wire [3:0] QSPI_IO_e;
-wire [3:0] QSPI_IO_i;
-wire [3:0] QSPI_IO_o;
-
-assign QSPI_D0 = (QSPI_IO_e[0]==1'b1)? QSPI_IO_o[0]:1'bz;
-assign QSPI_D1 = (QSPI_IO_e[1]==1'b1)? QSPI_IO_o[1]:1'bz;
-assign QSPI_D2 = (QSPI_IO_e[2]==1'b1)? QSPI_IO_o[2]:1'bz;
-assign QSPI_D3 = (QSPI_IO_e[3]==1'b1)? QSPI_IO_o[3]:1'bz;
-
-assign QSPI_IO_i[0] = QSPI_D0;
-assign QSPI_IO_i[1] = QSPI_D1;
-assign QSPI_IO_i[2] = QSPI_D2;
-assign QSPI_IO_i[3] = QSPI_D3;
+ input CLK_IN_P;
+ input CLK_IN_N;
+ //output [3:0]QSPI_IO_e_0;
+ //input [3:0]QSPI_IO_i_0;
+ //output [3:0]QSPI_IO_o_0;
+ //output QSPI_SCLK_0;
+ //output QSPI_nCS_0;
+ input nRESET_0;
+
+ wire CLK_IN_P;
+ wire CLK_IN_N;
+ wire [3:0]QSPI_IO_e_0;
+ wire [3:0]QSPI_IO_i_0;
+ wire [3:0]QSPI_IO_o_0;
+ wire QSPI_SCLK_0;
+ wire QSPI_nCS_0;
+ wire nRESET_0;
megasoc_design megasoc_design_i
- (.CLK_IN_0(CLK_IN_0),
- .nRESET_0(nRESET_0),
-
- .QSPI_IO_e_0(QSPI_IO_e),
- .QSPI_IO_i_0(QSPI_IO_i),
- .QSPI_IO_o_0(QSPI_IO_o),
- .QSPI_SCLK_0(QSPI_SCLK),
- .QSPI_nCS_0(QSPI_nCS),
-
- .SWCLKTCK_0(CS_TCK),
- .SWDITMS_0(SWDITMS_0),
- .SWDOEN_0(SWDOEN_0),
- .SWDO_0(SWDO_0),
- .TDI_0(CS_TDI),
- .TDO_0(CS_TDO),
-
- .UARTRXD_0(),
- .UARTTXD_0(),
- .UARTTXEN_0(),
-
- .nTDOEN_0(nTDOEN_0),
- .nTRST_0(CS_nTRST));
+ (.CLK_P(CLK_IN_P),
+ .CLK_N(CLK_IN_N),
+ .QSPI_IO_e_0(QSPI_IO_e_0),
+ .QSPI_IO_i_0(QSPI_IO_i_0),
+ .QSPI_IO_o_0(QSPI_IO_o_0),
+ .QSPI_SCLK_0(QSPI_SCLK_0),
+ .QSPI_nCS_0(QSPI_nCS_0),
+ .nRESET_0(nRESET_0)
+ );
endmodule
diff --git a/megasoc_tech b/megasoc_tech
index d8016f39f22ca4addea6875a96162404473f57b8..13691c8c10cb58199dc78da621b29d58b8b732de 160000
--- a/megasoc_tech
+++ b/megasoc_tech
@@ -1 +1 @@
-Subproject commit d8016f39f22ca4addea6875a96162404473f57b8
+Subproject commit 13691c8c10cb58199dc78da621b29d58b8b732de