diff --git a/.gitignore b/.gitignore
index c33874293d489c5bf605a963425764cd52ff54f2..6404f20b813fe94136cb12348681622b669d05c7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,6 @@
.socinit
.metadata
CheckResults.log
-CoherencyCheckConfiguration.config
\ No newline at end of file
+CoherencyCheckConfiguration.config
+simulate/
+imp/
\ No newline at end of file
diff --git a/env/dependency_env.sh b/env/dependency_env.sh
index 7ec5183d02dee867e7b1cf806063fc3ed0f67fb3..e34fbf8a900a1e1832f3c7b57d08992d31b0f4b4 100644
--- a/env/dependency_env.sh
+++ b/env/dependency_env.sh
@@ -15,7 +15,7 @@
#-----------------------------------------------------------------------------
# MilliSoC Tech
-export SOCLABS_MEGASOC_TECH_DIR="$SOCLABS_PROJECT_DIR/millisoc_tech"
+export SOCLABS_MEGASOC_TECH_DIR="$SOCLABS_PROJECT_DIR/megasoc_tech"
# MilliSoC Expansion Tech
export SOCLABS_MEGASOC_EXP_TECH_DIR="$SOCLABS_PROJECT_DIR/expansion_subsystem_tech"
@@ -26,3 +26,5 @@ export SOCLABS_MEGASOC_EXP_TECH_DIR="$SOCLABS_PROJECT_DIR/expansion_subsystem_te
# SoCTools - Toolkit of scripts related to SoCLabs projects
export SOCLABS_SOCTOOLS_FLOW_DIR="$SOCLABS_PROJECT_DIR/soctools_flow"
+
+export SOCLABS_AHB_QSPI_DIR="$SOCLABS_MEGASOC_TECH_DIR/logical/sl_ahb_qspi"
diff --git a/flist/project/megasoc_tb.flist b/flist/project/megasoc_tb.flist
new file mode 100644
index 0000000000000000000000000000000000000000..8bc51684d7529ecb09c4e33b982a098062efb5ea
--- /dev/null
+++ b/flist/project/megasoc_tb.flist
@@ -0,0 +1,27 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Testbench Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= MegaSoC Testbench search path =============
+
+// - Top-level testbench
+$(SOCLABS_PROJECT_DIR)/verif/testbench/logical/megasoc_tb.sv
+$(SOCLABS_PROJECT_DIR)/verif/trace/megasoc_uart_capture.v
+$(SOCLABS_PROJECT_DIR)/verif/control/logical/megasoc_clkreset.v
+
+// $(SOCLABS_MEGASOC_TECH_DIR)/logical/MS_QSPI_XIP_CACHE/verify/vip/sst26wf080b.v
+
diff --git a/flist/megasoc_project.flist b/flist/project/system.flist
similarity index 100%
rename from flist/megasoc_project.flist
rename to flist/project/system.flist
diff --git a/make.cfg b/flist/project/top_ASIC.flist
similarity index 100%
rename from make.cfg
rename to flist/project/top_ASIC.flist
diff --git a/flist/project/top_BEHAV.flist b/flist/project/top_BEHAV.flist
new file mode 100644
index 0000000000000000000000000000000000000000..6e5bb4e167ba5e728bb04782bd4d19bf04edf055
--- /dev/null
+++ b/flist/project/top_BEHAV.flist
@@ -0,0 +1,39 @@
+//-----------------------------------------------------------------------------
+// Project Top-level Filelist System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// DESIGN_TOP nanosoc_chip
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+
+// ============= System Filelist =========================
+// - Defines RTL
++incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
+
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+// MegaSoC Testbench
+-f $(SOCLABS_PROJECT_DIR)/flist/project/megasoc_tb.flist
+
+// ============= Arm-IP Specific Filelists =========================
+// - MegaSoC Chip IP
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/megasoc_tech_BEHAV.flist
+
+$(SOCLABS_PROJECT_DIR)/megasoc_chip/chip/logical/megasoc_chip.v
+$(SOCLABS_PROJECT_DIR)/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
+
+$(SOCLABS_PROJECT_DIR)/megasoc_system/logical/megasoc_system.v
+
+
diff --git a/flows/makefile.asic b/flows/makefile.asic
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/flows/makefile.fpga b/flows/makefile.fpga
new file mode 100644
index 0000000000000000000000000000000000000000..cdb86c1d8d62ee253e692a379e0266fe1f2c11da
--- /dev/null
+++ b/flows/makefile.fpga
@@ -0,0 +1,74 @@
+#-----------------------------------------------------------------------------
+# megaSoC FPGA Flow Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# Get properties for FPGA Boards
+include $(SOCLABS_PROJECT_DIR)/fpga/makefile.targets
+
+# Vivado Options
+VIVIADO_VERSION ?= 2021_1
+
+# MegaSoC Synthesis Properties
+MEGASOC_VENDOR ?= soclabs.org
+MEGASOC_CORE_REV ?= 1
+
+# Top-level of RTL design to Implement
+COMPONENT_TOP ?= megasoc_chip
+
+# Name of Implemented Chip Design (Including Socket IP)
+DESIGN_NAME ?= megasoc_design
+
+# Location to build FPGA files
+IMPLEMENTATION_DIR ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
+RUN_DIR := $(IMPLEMENTATION_DIR)/run
+IMP_MEGASOC_DIR := $(IMPLEMENTATION_DIR)/megasoc
+IMP_SOCKET_DIR := $(IMPLEMENTATION_DIR)/socket
+PROJECT_DIR := $(IMPLEMENTATION_DIR)/targets/$(BOARD_NAME)
+
+# Name of generated filelist by python script
+TCL_FLIST_DIR := $(IMP_MEGASOC_DIR)/flist
+TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
+
+
+# MegaSoC Tech Flow Dependencies
+MEGASOC_FPGA_FLOW_DIR := $(SOCLABS_PROJECT_DIR)/fpga
+
+# Directory to look for FPGA specific implementation files
+TARGET_DIR ?= $(MEGASOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
+TARGET_TCL_DIR := $(TARGET_DIR)/vivado_script/$(VIVIADO_VERSION)
+PINMAP_FILE ?= $(TARGET_DIR)/fpga_pinmap.xdc
+
+
+# Generate TCL filelist from flists
+flist_tcl_megasoc:
+ @mkdir -p $(TCL_FLIST_DIR)
+ @(cd $(TCL_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_MEGASOC_DIR)/src ;)
+
+
+# Environment Variables for Packaging NanoSoC
+package_megasoc: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
+package_megasoc: export FPGA_COMPONENT_LIB = $(IMP_MEGASOC_DIR)
+package_megasoc: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM)
+package_megasoc: export FPGA_COMPONENT_TOP = $(COMPONENT_TOP)
+package_megasoc: export FPGA_VENDOR = $(MEGASOC_VENDOR)
+package_megasoc: export FPGA_CORE_REV = $(MEGASOC_CORE_REV)
+
+# Package MegaSoC IP
+package_megasoc: code flist_tcl_megasoc
+ @echo Packaging MegaSoC
+ @mkdir -p $(RUN_DIR)
+ @cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
+ @mkdir -p $(IMP_MEGASOC_DIR)/logs
+ @cp $(RUN_DIR)/vivado.log $(IMP_MEGASOC_DIR)/logs
+ @echo MegaSoC Packaged
+
+
diff --git a/flows/makefile.lint b/flows/makefile.lint
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/flows/makefile.regression b/flows/makefile.regression
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/flows/makefile.simulate b/flows/makefile.simulate
new file mode 100644
index 0000000000000000000000000000000000000000..fd5979368bbf217acc5027ec16c6229134e96152
--- /dev/null
+++ b/flows/makefile.simulate
@@ -0,0 +1,169 @@
+#-----------------------------------------------------------------------------
+# MegaSoC Simulation Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# MTI options
+MTI_VC_OPTIONS = +acc
+MTI_VC_OPTIONS += -suppress 2892
+MTI_VC_OPTIONS += -f $(TBENCH_VC)
+MTI_VC_OPTIONS += -sv_lib $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
+MTI_RUN_OPTIONS = -voptargs=+acc
+MTI_RUN_OPTIONS += -sv_lib $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
+
+# VCS options
+VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug -debug_access+all
+VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
+VCS_VC_OPTIONS = -f $(TBENCH_VC)
+VCS_OPTIONS += -sverilog $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi.so
+CA53_TARMAC_EXECUTABLE = $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_32/bin/ca53_tarmac_decode --plain
+export CA53_TARMAC_EXECUTABLE
+
+# XM verilog options
+XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
+XM_VC_OPTIONS = -f $(TBENCH_VC)
+
+# ------- Cocotb Variables -----------
+# Convert Simulator Name for Cocotb
+COCOTB_SIMULATOR ?= questa
+
+ifeq ($(SIMULATOR),mti)
+ COCOTB_SIMULATOR := questa
+else ifeq ($(SIMULATOR),xm)
+ COCOTB_SIMULATOR := xcelium
+else ifeq ($(SIMULATOR),vcs)
+ COCOTB_SIMULATOR := vcs
+endif
+
+# Cocotb GUI Variable
+GUI ?= 0
+
+# Cocotb Test Location
+COCOTB_TEST_DIR := $(SOCLABS_PROJECT_DIR)/verif/cocotb
+
+# Cocotb Scratch Directory
+COCOTB_DIR := $(SIM_TOP_DIR)/cocotb
+COCOTB_SCRATCH_DIR := $(COCOTB_DIR)/scratch
+
+# Filelist for Cocotb
+MAKEFILE_FILELIST := $(COCOTB_DIR)/makefile.flist
+
+MODULE ?= test_adp
+
+# Create a List of PHONY Targets
+.PHONY: compile_$(SIMULATOR) run_$(SIMULATOR) sim_$(SIMULATOR)
+
+# ------- Simulator redirect -----------
+
+compile: compile_$(SIMULATOR)
+
+run: run_$(SIMULATOR)
+
+sim: sim_$(SIMULATOR)
+
+# Preload IMEM in Simulation
+compile_mti: MEGASOC_DEFINES += IMEM_0_RAM_PRELOAD
+compile_vcs: MEGASOC_DEFINES += IMEM_0_RAM_PRELOAD
+compile_xm: MEGASOC_DEFINES += IMEM_0_RAM_PRELOAD
+
+
+# Generate verilog .vc filelist from flists
+flist_vfiles_megasoc: gen_defs
+ @if [ ! -d $(SIM_DIR) ] ; then \
+ mkdir -p $(SIM_DIR); \
+ fi
+ @if [ ! -d $(SIM_DIR)/logs ] ; then \
+ mkdir -p $(SIM_DIR)/logs; \
+ fi
+ @cd $(SIM_DIR); python $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -f $(TBENCH_VC) -a -i $(FLIST_INCLUDES) -v -o tbench.vc
+
+
+# ------- VCS -----------
+
+# Compile RTL
+compile_vcs : gen_defs flist_vfiles_megasoc
+ cd $(SIM_DIR); vcs $(VCS_OPTIONS) -f tbench.vc -kdb $(DEFINES_VC) | tee compile_vcs.log
+
+
+# Run simulation in batch mode
+run_vcs : code compile_vcs
+ @echo quit > $(SIM_DIR)/quit.do
+ cd $(SIM_DIR); ./simv $(VCS_SIM_OPTION) +ca53_tarmac_enable -define ADP_FILE=adp.cmd < quit.do | tee logs/run_$(TESTNAME).log ;
+
+# Run simulation in interactive mode
+sim_vcs : code compile_vcs
+ cd $(SIM_DIR); ./simv -gui +vcs+lic+wait +vcs+flush+log +ca53_tarmac_enable &
+
+# ------- XM -----------
+
+# Compile RTL
+compile_xm : bootrom gen_defs flist_vfiles_megasoc
+ cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ns/1ps -top $(TB_TOP) | tee compile_xm.log
+ cd $(SIM_DIR); xmvlog -work worklib -f xmvlog_ver.args | tee -a compile_xm.log
+ cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
+
+# Note : If coverage is required, you can add -coverage all to xmelab
+
+# Run simulation in batch mode
+run_xm : code compile_xm
+ @echo run > $(SIM_DIR)/run.tcl.tmp
+ @echo exit >> $(SIM_DIR)/run.tcl.tmp
+ @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
+ cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
+
+# Run simulation in interactive mode
+sim_xm : code compile_xm
+ cd $(SIM_DIR); xmsim -gui $(XMSIM_OPTIONS)
+
+# ------- MTI -----------
+
+# Compile RTL
+compile_mti : gen_defs flist_vfiles_megasoc lib_mti
+ cd $(SIM_DIR); vlog -incr -lint +v2k -f tbench.vc +ca53_tarmac_enable $(DEFINES_VC) | tee compile_mti.log
+
+# Run simulation in batch mode
+run_mti : code compile_mti
+ @echo "run -all" > $(SIM_DIR)/run.tcl.tmp
+ @echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp
+ @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
+ cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) +ca53_tarmac_enable -c $(TB_TOP) -do run.tcl | tee $(SIM_DIR)/logs/run_$(TESTNAME).log ;
+
+run_mti_to:
+ timeout 2s $(MAKE) run_mti >> /dev/null 2>&1
+
+run_mti_wrap:
+ $(MAKE) run_mti_to
+
+# Run simulation in interactive mode
+sim_mti : code compile_mti
+ cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) +ca53_tarmac_enable -gui $(TB_TOP) &
+
+# Create work directory
+lib_mti :
+ @if [ -d $(SIM_DIR)/work ] ; then \
+ true ; \
+ else \
+ vlib $(SIM_DIR)/work; \
+ fi
+
+# Generate Make filelist from flists
+flist_makefile_megasoc: gen_defs
+ @mkdir -p $(COCOTB_DIR)
+ @(cd $(COCOTB_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -m -f $(DESIGN_VC) -o $(MAKEFILE_FILELIST);)
+
+run_cocotb: DEFINES_VC += COCOTB_SIM
+run_cocotb: flist_makefile_megasoc
+ @mkdir -p $(SIM_DIR)
+ @cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_PROJECT_DIR)/verif/cocotb clean SIM_BUILD=$(COCOTB_SCRATCH_DIR)
+ @cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_PROJECT_DIR)/verif/cocotb sim MODULE=$(MODULE) SIM=$(COCOTB_SIMULATOR) TESTCASE=$(TESTNAME) GUI=$(GUI) SIM_BUILD=$(COCOTB_SCRATCH_DIR) ACCELERATOR=$(ACCELERATOR)
+
+sim_cocotb: GUI=1
+sim_cocotb: run_cocotb
diff --git a/flows/makefile.software b/flows/makefile.software
new file mode 100644
index 0000000000000000000000000000000000000000..14599b68ce5252d0c4d99ea71a404ad634b52cd6
--- /dev/null
+++ b/flows/makefile.software
@@ -0,0 +1,189 @@
+#-----------------------------------------------------------------------------
+# MegaSoC Software Compilation Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# Software Directory
+MEGASOC_SW_DIR ?= $(SOCLABS_MEGASOC_TECH_DIR)/software
+
+# Default to DS-6 tool-chain
+TOOL_CHAIN = ds6
+
+# Software make options
+# - Pass onto the software makefile to define targetted CPU type
+# You can append additional make options for testcode here
+SW_MAKE_OPTIONS = CPU_PRODUCT=CORTEX_M0 TOOL_CHAIN=$(TOOL_CHAIN)
+
+# Bootrom Parameters:
+# Boot Loader image
+BOOTLOADER ?= bootloader
+BOOTROM_ADDRW ?= 8
+BOOTROM_HEX ?= $(SOCLABS_MEGASOC_TECH_DIR)/software/src/bootloader/$(BOOTLOADER).hex
+BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom
+
+# Debug Tester image
+DEBUGTESTER = debugtester
+
+# code target is used by other simulation targets (e.g. run_mti, sim_mti)
+# Before simulation, bootrom and testcode need to be compiled.
+code : testcode bootrom
+
+# Compile bootloader
+# Note : The use of ls after compile allows the computing server to sync up
+bootrom:
+ @cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\
+ echo CD $(TESTCODES_DIR)/$(BOOTLOADER) ;\
+ $(MAKE) boot_build $(SW_MAKE_OPTIONS) ;\
+ echo Bootrom Compile done ;\
+ ls > /dev/null ;\
+ echo Copy $(BOOTLOADER).hex ;\
+ while [ ! -e $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex ] ; do \
+ echo Wait for hex file ...; \
+ ls > /dev/null; \
+ sleep 5; \
+ done; \
+ if [ ! -e $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex ] ; then \
+ echo Problem reading hex file ;\
+ exit 1; \
+ else \
+ cp $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex $(SIM_DIR)/bootloader.hex ;\
+ fi ;\
+
+# Compile test code
+# Note : The use of ls after compile allows the computing server to sync up
+testcode:
+ifeq ($(TESTNAME),)
+ $(error Please specify TESTNAME on the make command line)
+endif
+ @(if [ -d "$(TESTCODES_DIR)/$(TESTNAME)" ] ; then \
+ cd $(TESTCODES_DIR)/$(TESTNAME) ;\
+ $(MAKE) all $(SW_MAKE_OPTIONS) ; \
+ echo Compile done ;\
+ echo cd $(TESTCODES_DIR)/ $(TESTNAME) ;\
+ ls > /dev/null ;\
+ echo Copy $(TESTCODES_DIR)/../build/$(TESTNAME)/host0/app_flash.v8-a.hex/EXEC_ROM ;\
+ if [ -e $(TESTCODES_DIR)/../build/$(TESTNAME)/host0/app_flash.v8-a.hex/EXEC_ROM ] ; then \
+ mkdir -p $(SIM_DIR) ; \
+ cp $(TESTCODES_DIR)/../build/$(TESTNAME)/host0/app_flash.v8-a.hex/EXEC_ROM $(SIM_DIR)/app_flash.v8-a.hex ; \
+ cp $(TESTCODES_DIR)/../build/$(TESTNAME)/host0/app_ram.v8-a.hex $(SIM_DIR)/app_ram.v8-a.hex ; \
+ else \
+ while [ ! -e $(TESTNAME).hex ] ; do \
+ echo Wait for $(TESTNAME).hex file ...; \
+ ls > /dev/null ; \
+ sleep 5 ; \
+ done; \
+ if [ -e $(TESTNAME).hex ] ; then \
+ mkdir -p $(SIM_DIR) ; \
+ cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
+ cp $(TESTNAME).hex ../../image.hex ; \
+ else \
+ echo Problem reading hex file ;\
+ exit 1; \
+ fi ;\
+ fi ;\
+ cd $(SIM_DIR) ;\
+ elif [ -d "$(PROJ_SW_DIR)/$(TESTNAME)" ] ; then \
+ cd $(PROJ_SW_DIR)/$(TESTNAME) ;\
+ echo cd $(PROJ_SW_DIR)/$(TESTNAME) ;\
+ $(MAKE) all $(SW_MAKE_OPTIONS) ; \
+ echo Compile done ;\
+ ls > /dev/null ;\
+ echo Copy $(TESTNAME).hex ;\
+ if [ -e $(TESTNAME).hex ] ; then \
+ mkdir -p $(SIM_DIR) ; \
+ cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
+ cp adp.cmd $(SIM_DIR)/adp.cmd ; \
+ else \
+ while [ ! -e $(TESTNAME).hex ] ; do \
+ echo Wait for $(TESTNAME).hex file ...; \
+ ls > /dev/null ; \
+ sleep 5 ; \
+ done; \
+ if [ -e $(TESTNAME).hex ] ; then \
+ mkdir -p $(SIM_DIR) ; \
+ cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
+ else \
+ echo Problem reading hex file ;\
+ exit 1; \
+ fi ;\
+ fi ;\
+ cd $(SIM_DIR) ;\
+ else \
+ echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\
+ exit 1 ;\
+ fi ;\
+ )
+
+
+# Compile debugtester
+# Note : The use of ls after compile allows the computing server to sync up
+debugtester:
+ @(cd $(MEGASOC_SW_DIR;)/debug_tester ;\
+ $(MAKE) all $(SW_MAKE_OPTIONS) ;\
+ echo Compile done ;\
+ ls > /dev/null ;\
+ echo Copy $(DEBUGTESTER)_le.hex ;\
+ if [ -e $(DEBUGTESTER)_le.hex ] ; then \
+ cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
+ else \
+ while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \
+ echo Wait for hex file ...; \
+ ls > /dev/null ; \
+ sleep 5 ; \
+ done; \
+ if [ -e $(DEBUGTESTER)_le.hex ] ; then \
+ mkdir -p $(SIM_DIR) ;\
+ cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
+ fi ;\
+ fi ;\
+ echo Copy $(DEBUGTESTER)_be.hex ;\
+ if [ -e $(DEBUGTESTER)_be.hex ] ; then \
+ mkdir -p $(SIM_DIR) ;\
+ cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
+ else \
+ while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \
+ echo Wait for hex file ...;\
+ ls > /dev/null ;\
+ sleep 5 ; \
+ done; \
+ if [ -e $(DEBUGTESTER)_be.hex ] ; then \
+ cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
+ fi ;\
+ fi ;\
+ if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \
+ echo Problem reading hex file ;\
+ exit 1 ;\
+ fi ;\
+ cd $(SIM_DIR) )
+
+# Compile all software including boot ROM
+compile_all_code: bootrom debugtester
+ for thistest in $(TEST_LIST) ; do \
+ echo Compiling $$thistest ; \
+ echo Removing old image.hex ;\
+ rm -f image.hex ;\
+ $(MAKE) testcode TESTNAME=$$thistest;\
+ if [ -e $(SIM_TOP_DIR)/$$thistest/image.hex ] ; then \
+ echo OK - image.hex created for test $$thistest ;\
+ else \
+ echo ERROR - image.hex NOT created for test $$thistest ;\
+ exit 1; \
+ fi ; \
+ done
+
+# Remove all software compilation results
+clean_all_code:
+ @rm -rf $(BOOTROM_BUILD_DIR)
+ @rm -rf $(TESTCODES_DIR)/../build
+
+# Remove only bootloader and default selected test
+clean_code:
+ @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; $(MAKE) clean; cd $(SIM_DIR); )
+ @(cd $(TESTCODES_DIR)/$(TESTNAME) ; $(MAKE) clean; cd $(SIM_DIR); )
\ No newline at end of file
diff --git a/fpga/makefile.targets b/fpga/makefile.targets
new file mode 100644
index 0000000000000000000000000000000000000000..99d49becaf7995e4ddf3c5320bf3af62ee914ab0
--- /dev/null
+++ b/fpga/makefile.targets
@@ -0,0 +1,25 @@
+#-----------------------------------------------------------------------------
+# NanoSoC FPGA Targets Declaration Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# FPGA Specific Options - More can be added later
+ifeq ($(FPGA),mps3)
+ XILINX_PART := xcku115-flvb1760-1-c
+ BOARD_NAME := arm_mps3
+ PLATFORM := bare
+else ifeq ($(FPGA),zcu104)
+ XILINX_PART := xczu7ev-ffvc1156-2-e
+ BOARD_NAME := pynq_zcu104
+ PLATFORM := pynq
+else # Default to MPS3
+ XILINX_PART := xcku115-flvb1760-1-c
+ BOARD_NAME := arm_mps3
+ PLATFORM := bare
+endif
diff --git a/fpga/targets/arm_mps3/fpga_pinmap.xdc b/fpga/targets/arm_mps3/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..88bb6d2abeba7c8fd16de7716393cca1d03f5d20
--- /dev/null
+++ b/fpga/targets/arm_mps3/fpga_pinmap.xdc
@@ -0,0 +1,986 @@
+set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
+# -----------------------------------------------------------------------------
+# Purpose : Main timing constraints and pin list for MPS3
+# -----------------------------------------------------------------------------
+
+####################################################################################
+# Pin Assigment
+####################################################################################
+
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_ADDR[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_FIFOSEL]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_nOE]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS18 [get_ports ETH_INT]
+set_property IOSTANDARD LVCMOS18 [get_ports ETH_nCS]
+set_property IOSTANDARD LVCMOS18 [get_ports ETH_nOE]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_DACK]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_DREQ]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_INT]
+set_property IOSTANDARD LVCMOS18 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CLCD_PD[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_BL]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_CS]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_RD]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_RS]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_RST]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TINT]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TNC]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TSCL]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_TSDA]
+set_property IOSTANDARD LVCMOS18 [get_ports CLCD_WR_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nLED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_SW[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nPB[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {USER_nPB[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports HDMI_CSCL]
+set_property IOSTANDARD LVCMOS18 [get_ports HDMI_CSDA]
+set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {CS_T_D[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TCK]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TDI]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TDO]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_TMS]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_T_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_T_CTL]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_nDET]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_nSRST]
+set_property IOSTANDARD LVCMOS18 [get_ports CS_nTRST]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_CK]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_CS]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_DI]
+set_property IOSTANDARD LVCMOS18 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_RX_F[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {UART_TX_F[0]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[23]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[22]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[21]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[20]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[18]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_DE]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_HS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_IDCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_VS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_WS]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CMD]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_DS]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_nRST]
+# not used
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[2]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[2]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_LRCK]
+set_property PACKAGE_PIN Y30 [get_ports AUD_LRCK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_MCLK]
+set_property PACKAGE_PIN AB29 [get_ports AUD_MCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_nRST]
+set_property PACKAGE_PIN AA27 [get_ports AUD_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCL]
+set_property PACKAGE_PIN AA28 [get_ports AUD_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCLK]
+set_property PACKAGE_PIN AB30 [get_ports AUD_SCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDA]
+set_property PACKAGE_PIN AA29 [get_ports AUD_SDA]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDIN]
+set_property PACKAGE_PIN AA30 [get_ports AUD_SDIN]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDOUT]
+set_property PACKAGE_PIN Y27 [get_ports AUD_SDOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nPOR]
+set_property PACKAGE_PIN AU22 [get_ports CB_nPOR]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nRST]
+set_property PACKAGE_PIN AV23 [get_ports CB_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_RUN]
+set_property PACKAGE_PIN AR25 [get_ports CB_RUN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_CLK]
+set_property PACKAGE_PIN AT20 [get_ports CFG_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAIN]
+set_property PACKAGE_PIN AT19 [get_ports CFG_DATAIN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAOUT]
+set_property PACKAGE_PIN AV18 [get_ports CFG_DATAOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_LOAD]
+set_property PACKAGE_PIN AW18 [get_ports CFG_LOAD]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_nRST]
+set_property PACKAGE_PIN AR20 [get_ports CFG_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AT18 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AJ16 [get_ports CLCD_BL]
+set_property PACKAGE_PIN AP15 [get_ports CLCD_CS]
+set_property PACKAGE_PIN AN17 [get_ports {CLCD_PD[10]}]
+set_property PACKAGE_PIN AP16 [get_ports {CLCD_PD[11]}]
+set_property PACKAGE_PIN AP18 [get_ports {CLCD_PD[12]}]
+set_property PACKAGE_PIN AR18 [get_ports {CLCD_PD[13]}]
+set_property PACKAGE_PIN AM16 [get_ports {CLCD_PD[14]}]
+set_property PACKAGE_PIN AN16 [get_ports {CLCD_PD[15]}]
+set_property PACKAGE_PIN AR17 [get_ports {CLCD_PD[16]}]
+set_property PACKAGE_PIN AR16 [get_ports {CLCD_PD[17]}]
+set_property PACKAGE_PIN AM15 [get_ports CLCD_RD]
+set_property PACKAGE_PIN AN14 [get_ports CLCD_RS]
+set_property PACKAGE_PIN AK18 [get_ports CLCD_RST]
+#set_property PACKAGE_PIN AN18 [get_ports CLCD_SDI]
+#set_property PACKAGE_PIN AH16 [get_ports CLCD_SDO]
+set_property PACKAGE_PIN AJ14 [get_ports CLCD_TINT]
+set_property PACKAGE_PIN AL17 [get_ports CLCD_TNC]
+set_property PACKAGE_PIN AL18 [get_ports CLCD_TSCL]
+set_property PACKAGE_PIN AJ15 [get_ports CLCD_TSDA]
+set_property PACKAGE_PIN AP14 [get_ports CLCD_WR_SCL]
+# not used
+# set_property PACKAGE_PIN N28 [get_ports {CLK_BIDIR_P[2]}]
+# set_property PACKAGE_PIN N29 [get_ports {CLK_BIDIR_N[2]}]
+# set_property PACKAGE_PIN E32 [get_ports {CLK_BIDIR_P[3]}]
+# set_property PACKAGE_PIN D33 [get_ports {CLK_BIDIR_N[3]}]
+# set_property PACKAGE_PIN G31 [get_ports {CLK_M2C_P[0]}]
+# set_property PACKAGE_PIN F32 [get_ports {CLK_M2C_N[0]}]
+# set_property PACKAGE_PIN E31 [get_ports {CLK_M2C_P[1]}]
+# set_property PACKAGE_PIN D31 [get_ports {CLK_M2C_N[1]}]
+set_property PACKAGE_PIN BB39 [get_ports CS_nDET]
+set_property PACKAGE_PIN BB36 [get_ports CS_nSRST]
+set_property PACKAGE_PIN BB37 [get_ports CS_nTRST]
+set_property PACKAGE_PIN AW33 [get_ports CS_T_CLK]
+set_property PACKAGE_PIN AY35 [get_ports CS_T_CTL]
+set_property PACKAGE_PIN AW34 [get_ports {CS_T_D[0]}]
+set_property PACKAGE_PIN AT34 [get_ports {CS_T_D[1]}]
+set_property PACKAGE_PIN AU34 [get_ports {CS_T_D[2]}]
+set_property PACKAGE_PIN AV36 [get_ports {CS_T_D[3]}]
+set_property PACKAGE_PIN AW36 [get_ports {CS_T_D[4]}]
+set_property PACKAGE_PIN AT35 [get_ports {CS_T_D[5]}]
+set_property PACKAGE_PIN AU35 [get_ports {CS_T_D[6]}]
+set_property PACKAGE_PIN AU36 [get_ports {CS_T_D[7]}]
+set_property PACKAGE_PIN AV37 [get_ports {CS_T_D[8]}]
+set_property PACKAGE_PIN AW35 [get_ports {CS_T_D[9]}]
+set_property PACKAGE_PIN AY36 [get_ports {CS_T_D[10]}]
+set_property PACKAGE_PIN AY37 [get_ports {CS_T_D[11]}]
+set_property PACKAGE_PIN BB34 [get_ports {CS_T_D[12]}]
+set_property PACKAGE_PIN BB35 [get_ports {CS_T_D[13]}]
+set_property PACKAGE_PIN BA37 [get_ports {CS_T_D[14]}]
+set_property PACKAGE_PIN BA38 [get_ports {CS_T_D[15]}]
+set_property PACKAGE_PIN AV33 [get_ports CS_TCK]
+set_property PACKAGE_PIN BA35 [get_ports CS_TDI]
+set_property PACKAGE_PIN AW38 [get_ports CS_TDO]
+set_property PACKAGE_PIN AY38 [get_ports CS_TMS]
+# not used
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[0]}]
+#set_property PACKAGE_PIN J19 [get_ports {DDR_CHIPID[0]}]
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[1]}]
+#set_property PACKAGE_PIN G20 [get_ports {DDR_CHIPID[1]}]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nALERT]
+#set_property PACKAGE_PIN P15 [get_ports DDR_nALERT]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nEVENT]
+#set_property PACKAGE_PIN C17 [get_ports DDR_nEVENT]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_PARITY]
+# set_property PACKAGE_PIN D18 [get_ports DDR_PARITY]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SCL]
+# set_property PACKAGE_PIN N21 [get_ports DDR_SCL]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SDA]
+# set_property PACKAGE_PIN P21 [get_ports DDR_SDA]
+# set_property PACKAGE_PIN AC42 [get_ports {DP_M2C_N[0]}]
+# set_property PACKAGE_PIN AJ42 [get_ports {DP_M2C_N[1]}]
+# set_property PACKAGE_PIN AE42 [get_ports {DP_M2C_N[2]}]
+# set_property PACKAGE_PIN W42 [get_ports {DP_M2C_N[3]}]
+# set_property PACKAGE_PIN R42 [get_ports {DP_M2C_N[4]}]
+# set_property PACKAGE_PIN L42 [get_ports {DP_M2C_N[5]}]
+# set_property PACKAGE_PIN N42 [get_ports {DP_M2C_N[6]}]
+# set_property PACKAGE_PIN U42 [get_ports {DP_M2C_N[7]}]
+# set_property PACKAGE_PIN AA42 [get_ports {DP_M2C_N[8]}]
+# set_property PACKAGE_PIN AG42 [get_ports {DP_M2C_N[9]}]
+# set_property PACKAGE_PIN AC41 [get_ports {DP_M2C_P[0]}]
+# set_property PACKAGE_PIN AJ41 [get_ports {DP_M2C_P[1]}]
+# set_property PACKAGE_PIN AE41 [get_ports {DP_M2C_P[2]}]
+# set_property PACKAGE_PIN W41 [get_ports {DP_M2C_P[3]}]
+# set_property PACKAGE_PIN R41 [get_ports {DP_M2C_P[4]}]
+# set_property PACKAGE_PIN L41 [get_ports {DP_M2C_P[5]}]
+# set_property PACKAGE_PIN N41 [get_ports {DP_M2C_P[6]}]
+# set_property PACKAGE_PIN U41 [get_ports {DP_M2C_P[7]}]
+# set_property PACKAGE_PIN AA41 [get_ports {DP_M2C_P[8]}]
+# set_property PACKAGE_PIN AG41 [get_ports {DP_M2C_P[9]}]
+set_property PACKAGE_PIN AG34 [get_ports HDMI_CSCL]
+set_property PACKAGE_PIN AE33 [get_ports HDMI_CSDA]
+set_property PACKAGE_PIN AF33 [get_ports HDMI_INT]
+set_property PACKAGE_PIN W29 [get_ports EMMC_CLK]
+set_property PACKAGE_PIN AC34 [get_ports EMMC_CMD]
+set_property PACKAGE_PIN Y32 [get_ports {EMMC_DAT[0]}]
+set_property PACKAGE_PIN Y33 [get_ports {EMMC_DAT[1]}]
+set_property PACKAGE_PIN W33 [get_ports {EMMC_DAT[2]}]
+set_property PACKAGE_PIN W34 [get_ports {EMMC_DAT[3]}]
+set_property PACKAGE_PIN AA34 [get_ports {EMMC_DAT[4]}]
+set_property PACKAGE_PIN AB34 [get_ports {EMMC_DAT[5]}]
+set_property PACKAGE_PIN W31 [get_ports {EMMC_DAT[6]}]
+set_property PACKAGE_PIN Y31 [get_ports {EMMC_DAT[7]}]
+set_property PACKAGE_PIN AE32 [get_ports EMMC_DS]
+set_property PACKAGE_PIN W30 [get_ports EMMC_nRST]
+set_property PACKAGE_PIN AK23 [get_ports ETH_INT]
+set_property PACKAGE_PIN AL24 [get_ports ETH_nCS]
+set_property PACKAGE_PIN AJ23 [get_ports ETH_nOE]
+# not used
+# set_property PACKAGE_PIN AV38 [get_ports FMC_CLK_DIR]
+# set_property PACKAGE_PIN AL42 [get_ports FMC_nPRSNT]
+# set_property PACKAGE_PIN BB40 [get_ports {HA_N[2]}]
+# set_property PACKAGE_PIN BA41 [get_ports {HA_N[3]}]
+# set_property PACKAGE_PIN AY40 [get_ports {HA_N[4]}]
+# set_property PACKAGE_PIN AU42 [get_ports {HA_N[5]}]
+# set_property PACKAGE_PIN AY42 [get_ports {HA_N[6]}]
+# set_property PACKAGE_PIN AW41 [get_ports {HA_N[7]}]
+# set_property PACKAGE_PIN AU37 [get_ports {HA_N[8]}]
+# set_property PACKAGE_PIN AT42 [get_ports {HA_N[9]}]
+# set_property PACKAGE_PIN AT38 [get_ports {HA_N[10]}]
+# set_property PACKAGE_PIN AV42 [get_ports {HA_N[11]}]
+# set_property PACKAGE_PIN AR37 [get_ports {HA_N[12]}]
+# set_property PACKAGE_PIN AN42 [get_ports {HA_N[13]}]
+# set_property PACKAGE_PIN AP38 [get_ports {HA_N[14]}]
+# set_property PACKAGE_PIN AN37 [get_ports {HA_N[15]}]
+# set_property PACKAGE_PIN AM42 [get_ports {HA_N[16]}]
+# set_property PACKAGE_PIN AR41 [get_ports {HA_N[18]}]
+# set_property PACKAGE_PIN AM39 [get_ports {HA_N[19]}]
+# set_property PACKAGE_PIN AR40 [get_ports {HA_N[20]}]
+# set_property PACKAGE_PIN AM40 [get_ports {HA_N[21]}]
+# set_property PACKAGE_PIN AK38 [get_ports {HA_N[22]}]
+# set_property PACKAGE_PIN AL38 [get_ports {HA_N[23]}]
+# set_property PACKAGE_PIN AT39 [get_ports {HA_P[0]}]
+# set_property PACKAGE_PIN AT40 [get_ports {HA_N[0]}]
+# set_property PACKAGE_PIN AU39 [get_ports {HA_P[1]}]
+# set_property PACKAGE_PIN AU40 [get_ports {HA_N[1]}]
+# set_property PACKAGE_PIN BA39 [get_ports {HA_P[2]}]
+# set_property PACKAGE_PIN BA40 [get_ports {HA_P[3]}]
+# set_property PACKAGE_PIN AW39 [get_ports {HA_P[4]}]
+# set_property PACKAGE_PIN AU41 [get_ports {HA_P[5]}]
+# set_property PACKAGE_PIN AY41 [get_ports {HA_P[6]}]
+# set_property PACKAGE_PIN AW40 [get_ports {HA_P[7]}]
+# set_property PACKAGE_PIN AT37 [get_ports {HA_P[8]}]
+# set_property PACKAGE_PIN AR42 [get_ports {HA_P[9]}]
+# set_property PACKAGE_PIN AR38 [get_ports {HA_P[10]}]
+# set_property PACKAGE_PIN AV41 [get_ports {HA_P[11]}]
+# set_property PACKAGE_PIN AR36 [get_ports {HA_P[12]}]
+# set_property PACKAGE_PIN AN41 [get_ports {HA_P[13]}]
+# set_property PACKAGE_PIN AN38 [get_ports {HA_P[14]}]
+# set_property PACKAGE_PIN AM37 [get_ports {HA_P[15]}]
+# set_property PACKAGE_PIN AM41 [get_ports {HA_P[16]}]
+# set_property PACKAGE_PIN AN39 [get_ports {HA_P[17]}]
+# set_property PACKAGE_PIN AP39 [get_ports {HA_N[17]}]
+# set_property PACKAGE_PIN AP41 [get_ports {HA_P[18]}]
+# set_property PACKAGE_PIN AL39 [get_ports {HA_P[19]}]
+# set_property PACKAGE_PIN AP40 [get_ports {HA_P[20]}]
+# set_property PACKAGE_PIN AL40 [get_ports {HA_P[21]}]
+# set_property PACKAGE_PIN AK37 [get_ports {HA_P[22]}]
+# set_property PACKAGE_PIN AL37 [get_ports {HA_P[23]}]
+# set_property PACKAGE_PIN T32 [get_ports {HB_N[1]}]
+# set_property PACKAGE_PIN V33 [get_ports {HB_N[2]}]
+# set_property PACKAGE_PIN V29 [get_ports {HB_N[3]}]
+# set_property PACKAGE_PIN T30 [get_ports {HB_N[4]}]
+# set_property PACKAGE_PIN T34 [get_ports {HB_N[5]}]
+# set_property PACKAGE_PIN R32 [get_ports {HB_N[7]}]
+# set_property PACKAGE_PIN P29 [get_ports {HB_N[8]}]
+# set_property PACKAGE_PIN P30 [get_ports {HB_N[9]}]
+# set_property PACKAGE_PIN K28 [get_ports {HB_N[10]}]
+# set_property PACKAGE_PIN L29 [get_ports {HB_N[11]}]
+# set_property PACKAGE_PIN K31 [get_ports {HB_N[12]}]
+# set_property PACKAGE_PIN L33 [get_ports {HB_N[13]}]
+# set_property PACKAGE_PIN U31 [get_ports {HB_N[14]}]
+# set_property PACKAGE_PIN N33 [get_ports {HB_N[15]}]
+# set_property PACKAGE_PIN L34 [get_ports {HB_N[16]}]
+# set_property PACKAGE_PIN R28 [get_ports {HB_N[18]}]
+# set_property PACKAGE_PIN N27 [get_ports {HB_N[19]}]
+# set_property PACKAGE_PIN U34 [get_ports {HB_N[20]}]
+# set_property PACKAGE_PIN N34 [get_ports {HB_N[21]}]
+# set_property PACKAGE_PIN N31 [get_ports {HB_P[0]}]
+# set_property PACKAGE_PIN M31 [get_ports {HB_N[0]}]
+# set_property PACKAGE_PIN U32 [get_ports {HB_P[1]}]
+# set_property PACKAGE_PIN V32 [get_ports {HB_P[2]}]
+# set_property PACKAGE_PIN V28 [get_ports {HB_P[3]}]
+# set_property PACKAGE_PIN U30 [get_ports {HB_P[4]}]
+# set_property PACKAGE_PIN T33 [get_ports {HB_P[5]}]
+# set_property PACKAGE_PIN M30 [get_ports {HB_P[6]}]
+# set_property PACKAGE_PIN L30 [get_ports {HB_N[6]}]
+# set_property PACKAGE_PIN R31 [get_ports {HB_P[7]}]
+# set_property PACKAGE_PIN P28 [get_ports {HB_P[8]}]
+# set_property PACKAGE_PIN R30 [get_ports {HB_P[9]}]
+# set_property PACKAGE_PIN L28 [get_ports {HB_P[10]}]
+# set_property PACKAGE_PIN M29 [get_ports {HB_P[11]}]
+# set_property PACKAGE_PIN K30 [get_ports {HB_P[12]}]
+# set_property PACKAGE_PIN L32 [get_ports {HB_P[13]}]
+# set_property PACKAGE_PIN V31 [get_ports {HB_P[14]}]
+# set_property PACKAGE_PIN P33 [get_ports {HB_P[15]}]
+# set_property PACKAGE_PIN M34 [get_ports {HB_P[16]}]
+# set_property PACKAGE_PIN N32 [get_ports {HB_P[17]}]
+# set_property PACKAGE_PIN M32 [get_ports {HB_N[17]}]
+# set_property PACKAGE_PIN T28 [get_ports {HB_P[18]}]
+# set_property PACKAGE_PIN N26 [get_ports {HB_P[19]}]
+# set_property PACKAGE_PIN V34 [get_ports {HB_P[20]}]
+# set_property PACKAGE_PIN P34 [get_ports {HB_P[21]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {CLK_CFG}]
+# set_property PACKAGE_PIN AT27 [get_ports {CLK_CFG}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_CSIB}]
+# set_property PACKAGE_PIN BA27 [get_ports {IOFPGA_CSIB}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[4]}]
+# set_property PACKAGE_PIN AV26 [get_ports {IOFPGA_D[4]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[5]}]
+# set_property PACKAGE_PIN AV27 [get_ports {IOFPGA_D[5]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[6]}]
+# set_property PACKAGE_PIN AU29 [get_ports {IOFPGA_D[6]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[7]}]
+# set_property PACKAGE_PIN AV29 [get_ports {IOFPGA_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NRST]
+set_property PACKAGE_PIN AV31 [get_ports IOFPGA_NRST]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NSPIR]
+set_property PACKAGE_PIN AV32 [get_ports IOFPGA_NSPIR]
+set_property IOSTANDARD LVCMOS33 [get_ports IOFPGA_SYSWDT]
+set_property PACKAGE_PIN AU20 [get_ports IOFPGA_SYSWDT]
+# not used
+# set_property PACKAGE_PIN AN27 [get_ports {LA_N[2]}]
+# set_property PACKAGE_PIN AP30 [get_ports {LA_N[3]}]
+# set_property PACKAGE_PIN AN29 [get_ports {LA_N[4]}]
+# set_property PACKAGE_PIN AR35 [get_ports {LA_N[5]}]
+# set_property PACKAGE_PIN AR33 [get_ports {LA_N[6]}]
+# set_property PACKAGE_PIN AN32 [get_ports {LA_N[7]}]
+# set_property PACKAGE_PIN AP31 [get_ports {LA_N[8]}]
+# set_property PACKAGE_PIN AN34 [get_ports {LA_N[9]}]
+# set_property PACKAGE_PIN AL35 [get_ports {LA_N[10]}]
+# set_property PACKAGE_PIN AM36 [get_ports {LA_N[11]}]
+# set_property PACKAGE_PIN AP34 [get_ports {LA_N[12]}]
+# set_property PACKAGE_PIN AL32 [get_ports {LA_N[13]}]
+# set_property PACKAGE_PIN AK36 [get_ports {LA_N[14]}]
+# set_property PACKAGE_PIN AJ34 [get_ports {LA_N[15]}]
+# set_property PACKAGE_PIN AL33 [get_ports {LA_N[16]}]
+# set_property PACKAGE_PIN AJ29 [get_ports {LA_N[19]}]
+# set_property PACKAGE_PIN AJ33 [get_ports {LA_N[20]}]
+# set_property PACKAGE_PIN AH29 [get_ports {LA_N[21]}]
+# set_property PACKAGE_PIN AH31 [get_ports {LA_N[22]}]
+# set_property PACKAGE_PIN AG30 [get_ports {LA_N[23]}]
+# set_property PACKAGE_PIN G32 [get_ports {LA_N[24]}]
+# set_property PACKAGE_PIN H34 [get_ports {LA_N[25]}]
+# set_property PACKAGE_PIN H31 [get_ports {LA_N[26]}]
+# set_property PACKAGE_PIN K33 [get_ports {LA_N[27]}]
+# set_property PACKAGE_PIN H29 [get_ports {LA_N[28]}]
+# set_property PACKAGE_PIN H33 [get_ports {LA_N[29]}]
+# set_property PACKAGE_PIN F34 [get_ports {LA_N[30]}]
+# set_property PACKAGE_PIN E33 [get_ports {LA_N[31]}]
+# set_property PACKAGE_PIN C34 [get_ports {LA_N[32]}]
+# set_property PACKAGE_PIN G30 [get_ports {LA_N[33]}]
+# set_property PACKAGE_PIN AM29 [get_ports {LA_P[0]}]
+# set_property PACKAGE_PIN AM30 [get_ports {LA_N[0]}]
+# set_property PACKAGE_PIN AL29 [get_ports {LA_P[1]}]
+# set_property PACKAGE_PIN AL30 [get_ports {LA_N[1]}]
+# set_property PACKAGE_PIN AM27 [get_ports {LA_P[2]}]
+# set_property PACKAGE_PIN AP29 [get_ports {LA_P[3]}]
+# set_property PACKAGE_PIN AN28 [get_ports {LA_P[4]}]
+# set_property PACKAGE_PIN AP35 [get_ports {LA_P[5]}]
+# set_property PACKAGE_PIN AP33 [get_ports {LA_P[6]}]
+# set_property PACKAGE_PIN AM32 [get_ports {LA_P[7]}]
+# set_property PACKAGE_PIN AN31 [get_ports {LA_P[8]}]
+# set_property PACKAGE_PIN AM34 [get_ports {LA_P[9]}]
+# set_property PACKAGE_PIN AL34 [get_ports {LA_P[10]}]
+# set_property PACKAGE_PIN AM35 [get_ports {LA_P[11]}]
+# set_property PACKAGE_PIN AN33 [get_ports {LA_P[12]}]
+# set_property PACKAGE_PIN AK32 [get_ports {LA_P[13]}]
+# set_property PACKAGE_PIN AK35 [get_ports {LA_P[14]}]
+# set_property PACKAGE_PIN AH34 [get_ports {LA_P[15]}]
+# set_property PACKAGE_PIN AK33 [get_ports {LA_P[16]}]
+# set_property PACKAGE_PIN AK30 [get_ports {LA_P[17]}]
+# set_property PACKAGE_PIN AK31 [get_ports {LA_N[17]}]
+# set_property PACKAGE_PIN AJ30 [get_ports {LA_P[18]}]
+# set_property PACKAGE_PIN AJ31 [get_ports {LA_N[18]}]
+# set_property PACKAGE_PIN AJ28 [get_ports {LA_P[19]}]
+# set_property PACKAGE_PIN AH33 [get_ports {LA_P[20]}]
+# set_property PACKAGE_PIN AH28 [get_ports {LA_P[21]}]
+# set_property PACKAGE_PIN AG31 [get_ports {LA_P[22]}]
+# set_property PACKAGE_PIN AG29 [get_ports {LA_P[23]}]
+# set_property PACKAGE_PIN H32 [get_ports {LA_P[24]}]
+# set_property PACKAGE_PIN J34 [get_ports {LA_P[25]}]
+# set_property PACKAGE_PIN J30 [get_ports {LA_P[26]}]
+# set_property PACKAGE_PIN K32 [get_ports {LA_P[27]}]
+# set_property PACKAGE_PIN J29 [get_ports {LA_P[28]}]
+# set_property PACKAGE_PIN J33 [get_ports {LA_P[29]}]
+# set_property PACKAGE_PIN G34 [get_ports {LA_P[30]}]
+# set_property PACKAGE_PIN F33 [get_ports {LA_P[31]}]
+# set_property PACKAGE_PIN D34 [get_ports {LA_P[32]}]
+# set_property PACKAGE_PIN G29 [get_ports {LA_P[33]}]
+set_property PACKAGE_PIN AM17 [get_ports {MMB_DATA[0]}]
+set_property PACKAGE_PIN AL14 [get_ports {MMB_DATA[1]}]
+set_property PACKAGE_PIN AK15 [get_ports {MMB_DATA[2]}]
+set_property PACKAGE_PIN AK17 [get_ports {MMB_DATA[3]}]
+set_property PACKAGE_PIN AM14 [get_ports {MMB_DATA[4]}]
+set_property PACKAGE_PIN AN13 [get_ports {MMB_DATA[5]}]
+set_property PACKAGE_PIN AM11 [get_ports {MMB_DATA[6]}]
+set_property PACKAGE_PIN AN11 [get_ports {MMB_DATA[7]}]
+set_property PACKAGE_PIN AR13 [get_ports {MMB_DATA[8]}]
+set_property PACKAGE_PIN AR12 [get_ports {MMB_DATA[9]}]
+set_property PACKAGE_PIN AL10 [get_ports {MMB_DATA[10]}]
+set_property PACKAGE_PIN AM10 [get_ports {MMB_DATA[11]}]
+set_property PACKAGE_PIN AM12 [get_ports {MMB_DATA[12]}]
+set_property PACKAGE_PIN AN12 [get_ports {MMB_DATA[13]}]
+set_property PACKAGE_PIN AP13 [get_ports {MMB_DATA[14]}]
+set_property PACKAGE_PIN AK13 [get_ports {MMB_DATA[15]}]
+set_property PACKAGE_PIN AK12 [get_ports {MMB_DATA[16]}]
+set_property PACKAGE_PIN AK11 [get_ports {MMB_DATA[17]}]
+set_property PACKAGE_PIN AK10 [get_ports {MMB_DATA[18]}]
+set_property PACKAGE_PIN AH13 [get_ports {MMB_DATA[19]}]
+set_property PACKAGE_PIN AJ13 [get_ports {MMB_DATA[20]}]
+set_property PACKAGE_PIN AJ11 [get_ports {MMB_DATA[21]}]
+set_property PACKAGE_PIN AJ10 [get_ports {MMB_DATA[22]}]
+set_property PACKAGE_PIN AH12 [get_ports {MMB_DATA[23]}]
+set_property PACKAGE_PIN AH11 [get_ports MMB_DE]
+set_property PACKAGE_PIN AG12 [get_ports MMB_HS]
+set_property PACKAGE_PIN AH14 [get_ports MMB_IDCLK]
+set_property PACKAGE_PIN AF29 [get_ports MMB_SCK]
+set_property PACKAGE_PIN AC28 [get_ports {MMB_SD[0]}]
+set_property PACKAGE_PIN AC29 [get_ports {MMB_SD[1]}]
+set_property PACKAGE_PIN AE27 [get_ports {MMB_SD[2]}]
+set_property PACKAGE_PIN AF34 [get_ports {MMB_SD[3]}]
+set_property PACKAGE_PIN AG11 [get_ports MMB_VS]
+set_property PACKAGE_PIN AF30 [get_ports MMB_WS]
+set_property PACKAGE_PIN AL15 [get_ports {OSCCLK[0]}]
+set_property PACKAGE_PIN AK16 [get_ports {OSCCLK[1]}]
+set_property PACKAGE_PIN AY32 [get_ports {OSCCLK[2]}]
+set_property PACKAGE_PIN AY30 [get_ports {OSCCLK[3]}]
+set_property PACKAGE_PIN AC31 [get_ports {OSCCLK[4]}]
+set_property PACKAGE_PIN AC32 [get_ports {OSCCLK[5]}]
+set_property PACKAGE_PIN AT29 [get_ports PB_IRQ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D0]
+set_property PACKAGE_PIN AU24 [get_ports QSPI_D0]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D1]
+set_property PACKAGE_PIN AV24 [get_ports QSPI_D1]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D2]
+set_property PACKAGE_PIN AV21 [get_ports QSPI_D2]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D3]
+set_property PACKAGE_PIN AV22 [get_ports QSPI_D3]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_nCS]
+set_property PACKAGE_PIN AT24 [get_ports QSPI_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_SCLK]
+set_property PACKAGE_PIN AT25 [get_ports QSPI_SCLK]
+# not used
+# set_property PACKAGE_PIN AL13 [get_ports SATA_CLK_P]
+# set_property PACKAGE_PIN AL12 [get_ports SATA_CLK_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[0]}]
+set_property PACKAGE_PIN AW14 [get_ports {SH0_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[1]}]
+set_property PACKAGE_PIN AW13 [get_ports {SH0_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[2]}]
+set_property PACKAGE_PIN AW15 [get_ports {SH0_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[3]}]
+set_property PACKAGE_PIN AY15 [get_ports {SH0_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[4]}]
+set_property PACKAGE_PIN AY13 [get_ports {SH0_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[5]}]
+set_property PACKAGE_PIN AY12 [get_ports {SH0_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[6]}]
+set_property PACKAGE_PIN BA15 [get_ports {SH0_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[7]}]
+set_property PACKAGE_PIN BB14 [get_ports {SH0_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[8]}]
+set_property PACKAGE_PIN BA12 [get_ports {SH0_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[9]}]
+set_property PACKAGE_PIN BB12 [get_ports {SH0_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[10]}]
+set_property PACKAGE_PIN BA14 [get_ports {SH0_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[11]}]
+set_property PACKAGE_PIN BA13 [get_ports {SH0_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[12]}]
+set_property PACKAGE_PIN BB15 [get_ports {SH0_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[13]}]
+set_property PACKAGE_PIN AU12 [get_ports {SH0_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[14]}]
+set_property PACKAGE_PIN AV12 [get_ports {SH0_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[15]}]
+set_property PACKAGE_PIN AV17 [get_ports {SH0_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[16]}]
+set_property PACKAGE_PIN AV16 [get_ports {SH0_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[17]}]
+set_property PACKAGE_PIN AT14 [get_ports {SH0_IO[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[0]}]
+set_property PACKAGE_PIN AT17 [get_ports {SH1_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[1]}]
+set_property PACKAGE_PIN AU17 [get_ports {SH1_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[2]}]
+set_property PACKAGE_PIN AV19 [get_ports {SH1_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[3]}]
+set_property PACKAGE_PIN AW19 [get_ports {SH1_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[4]}]
+set_property PACKAGE_PIN AW20 [get_ports {SH1_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[5]}]
+set_property PACKAGE_PIN BA19 [get_ports {SH1_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[6]}]
+set_property PACKAGE_PIN BA18 [get_ports {SH1_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[7]}]
+set_property PACKAGE_PIN AY20 [get_ports {SH1_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[8]}]
+set_property PACKAGE_PIN BA20 [get_ports {SH1_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[9]}]
+set_property PACKAGE_PIN BA17 [get_ports {SH1_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[10]}]
+set_property PACKAGE_PIN BB17 [get_ports {SH1_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[11]}]
+set_property PACKAGE_PIN BB20 [get_ports {SH1_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[12]}]
+set_property PACKAGE_PIN BB19 [get_ports {SH1_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[13]}]
+set_property PACKAGE_PIN AW16 [get_ports {SH1_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[14]}]
+set_property PACKAGE_PIN AY16 [get_ports {SH1_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[15]}]
+set_property PACKAGE_PIN AY18 [get_ports {SH1_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[16]}]
+set_property PACKAGE_PIN AY17 [get_ports {SH1_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN BB16 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN AL25 [get_ports SH_ADC_CK]
+set_property PACKAGE_PIN AM25 [get_ports SH_ADC_CS]
+set_property PACKAGE_PIN AP25 [get_ports SH_ADC_DI]
+set_property PACKAGE_PIN AP26 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS33 [get_ports SH_nRST]
+set_property PACKAGE_PIN AU14 [get_ports SH_nRST]
+set_property PACKAGE_PIN AK20 [get_ports {SMBF_ADDR[0]}]
+set_property PACKAGE_PIN AK21 [get_ports {SMBF_ADDR[1]}]
+set_property PACKAGE_PIN AJ18 [get_ports {SMBF_ADDR[2]}]
+set_property PACKAGE_PIN AJ19 [get_ports {SMBF_ADDR[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {SMBF_ADDR[4]}]
+set_property PACKAGE_PIN AJ21 [get_ports {SMBF_ADDR[5]}]
+set_property PACKAGE_PIN AH19 [get_ports {SMBF_ADDR[6]}]
+set_property PACKAGE_PIN AK22 [get_ports {SMBF_DATA[0]}]
+set_property PACKAGE_PIN AL22 [get_ports {SMBF_DATA[1]}]
+set_property PACKAGE_PIN AL19 [get_ports {SMBF_DATA[2]}]
+set_property PACKAGE_PIN AL20 [get_ports {SMBF_DATA[3]}]
+set_property PACKAGE_PIN AH18 [get_ports {SMBF_DATA[4]}]
+set_property PACKAGE_PIN AM19 [get_ports {SMBF_DATA[5]}]
+set_property PACKAGE_PIN AN19 [get_ports {SMBF_DATA[6]}]
+set_property PACKAGE_PIN AP19 [get_ports {SMBF_DATA[7]}]
+set_property PACKAGE_PIN AP20 [get_ports {SMBF_DATA[8]}]
+set_property PACKAGE_PIN AM20 [get_ports {SMBF_DATA[9]}]
+set_property PACKAGE_PIN AN21 [get_ports {SMBF_DATA[10]}]
+set_property PACKAGE_PIN AP21 [get_ports {SMBF_DATA[11]}]
+set_property PACKAGE_PIN AR22 [get_ports {SMBF_DATA[12]}]
+set_property PACKAGE_PIN AM21 [get_ports {SMBF_DATA[13]}]
+set_property PACKAGE_PIN AM22 [get_ports {SMBF_DATA[14]}]
+set_property PACKAGE_PIN AN22 [get_ports {SMBF_DATA[15]}]
+set_property PACKAGE_PIN AJ20 [get_ports SMBF_FIFOSEL]
+set_property PACKAGE_PIN AN23 [get_ports SMBF_nOE]
+set_property PACKAGE_PIN AL23 [get_ports SMBF_nRST]
+set_property PACKAGE_PIN AP23 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[16]}]
+set_property PACKAGE_PIN AR26 [get_ports {SMBM_A[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[17]}]
+set_property PACKAGE_PIN AT22 [get_ports {SMBM_A[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[18]}]
+set_property PACKAGE_PIN AT23 [get_ports {SMBM_A[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[19]}]
+set_property PACKAGE_PIN AU21 [get_ports {SMBM_A[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[20]}]
+set_property PACKAGE_PIN AY22 [get_ports {SMBM_A[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[21]}]
+set_property PACKAGE_PIN BA22 [get_ports {SMBM_A[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[22]}]
+set_property PACKAGE_PIN AW21 [get_ports {SMBM_A[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[23]}]
+set_property PACKAGE_PIN AY21 [get_ports {SMBM_A[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[24]}]
+set_property PACKAGE_PIN BA23 [get_ports {SMBM_A[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[25]}]
+set_property PACKAGE_PIN BA24 [get_ports {SMBM_A[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_CLK]
+set_property PACKAGE_PIN AY25 [get_ports SMBM_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[0]}]
+set_property PACKAGE_PIN BB21 [get_ports {SMBM_D[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[1]}]
+set_property PACKAGE_PIN BB22 [get_ports {SMBM_D[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[2]}]
+set_property PACKAGE_PIN AW24 [get_ports {SMBM_D[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {SMBM_D[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[4]}]
+set_property PACKAGE_PIN AW23 [get_ports {SMBM_D[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[5]}]
+set_property PACKAGE_PIN AY23 [get_ports {SMBM_D[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[6]}]
+set_property PACKAGE_PIN BB24 [get_ports {SMBM_D[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[7]}]
+set_property PACKAGE_PIN AY27 [get_ports {SMBM_D[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[8]}]
+set_property PACKAGE_PIN AY26 [get_ports {SMBM_D[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[9]}]
+set_property PACKAGE_PIN AY28 [get_ports {SMBM_D[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[10]}]
+set_property PACKAGE_PIN BA28 [get_ports {SMBM_D[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[11]}]
+set_property PACKAGE_PIN BA25 [get_ports {SMBM_D[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[12]}]
+set_property PACKAGE_PIN BB25 [get_ports {SMBM_D[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[13]}]
+set_property PACKAGE_PIN AW28 [get_ports {SMBM_D[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[14]}]
+set_property PACKAGE_PIN AW29 [get_ports {SMBM_D[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[15]}]
+set_property PACKAGE_PIN BB26 [get_ports {SMBM_D[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[0]}]
+set_property PACKAGE_PIN AU26 [get_ports {SMBM_nBL[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[1]}]
+set_property PACKAGE_PIN AR28 [get_ports {SMBM_nBL[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[1]}]
+set_property PACKAGE_PIN BB27 [get_ports {SMBM_nE[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[2]}]
+set_property PACKAGE_PIN AU27 [get_ports {SMBM_nE[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[3]}]
+set_property PACKAGE_PIN AV28 [get_ports {SMBM_nE[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[4]}]
+set_property PACKAGE_PIN AU25 [get_ports {SMBM_nE[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nOE]
+set_property PACKAGE_PIN AT28 [get_ports SMBM_nOE]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWAIT]
+set_property PACKAGE_PIN AP28 [get_ports SMBM_nWAIT]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AR27 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AF28 [get_ports {UART_RX_F[0]}]
+set_property PACKAGE_PIN AE31 [get_ports {UART_RX_F[1]}]
+set_property PACKAGE_PIN AE28 [get_ports {UART_RX_F[2]}]
+set_property PACKAGE_PIN AD30 [get_ports {UART_RX_F[3]}]
+set_property PACKAGE_PIN AF27 [get_ports {UART_TX_F[0]}]
+set_property PACKAGE_PIN AE30 [get_ports {UART_TX_F[1]}]
+set_property PACKAGE_PIN AD29 [get_ports {UART_TX_F[3]}]
+set_property PACKAGE_PIN AN26 [get_ports USB_DACK]
+set_property PACKAGE_PIN AN24 [get_ports USB_DREQ]
+set_property PACKAGE_PIN AP24 [get_ports USB_INT]
+set_property PACKAGE_PIN AM26 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CLK]
+set_property PACKAGE_PIN AU15 [get_ports USD_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CMD]
+set_property PACKAGE_PIN AU16 [get_ports USD_CMD]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[0]}]
+set_property PACKAGE_PIN AV14 [get_ports {USD_DAT[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[1]}]
+set_property PACKAGE_PIN AV13 [get_ports {USD_DAT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[2]}]
+set_property PACKAGE_PIN AT13 [get_ports {USD_DAT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[3]}]
+set_property PACKAGE_PIN AT12 [get_ports {USD_DAT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_NCD]
+set_property PACKAGE_PIN AT15 [get_ports USD_NCD]
+set_property PACKAGE_PIN AU32 [get_ports {USER_nLED[0]}]
+set_property PACKAGE_PIN AU30 [get_ports {USER_nLED[1]}]
+set_property PACKAGE_PIN AU31 [get_ports {USER_nLED[2]}]
+set_property PACKAGE_PIN AR32 [get_ports {USER_nLED[3]}]
+set_property PACKAGE_PIN AT33 [get_ports {USER_nLED[4]}]
+set_property PACKAGE_PIN AW30 [get_ports {USER_nLED[5]}]
+set_property PACKAGE_PIN AW31 [get_ports {USER_nLED[6]}]
+set_property PACKAGE_PIN AR30 [get_ports {USER_nLED[7]}]
+set_property PACKAGE_PIN BB31 [get_ports {USER_nLED[8]}]
+set_property PACKAGE_PIN BB32 [get_ports {USER_nLED[9]}]
+set_property PACKAGE_PIN AT30 [get_ports {USER_nPB[0]}]
+set_property PACKAGE_PIN AT32 [get_ports {USER_nPB[1]}]
+set_property PACKAGE_PIN BA29 [get_ports {USER_SW[0]}]
+set_property PACKAGE_PIN BB29 [get_ports {USER_SW[1]}]
+set_property PACKAGE_PIN BA32 [get_ports {USER_SW[2]}]
+set_property PACKAGE_PIN BA33 [get_ports {USER_SW[3]}]
+set_property PACKAGE_PIN BA30 [get_ports {USER_SW[4]}]
+set_property PACKAGE_PIN BB30 [get_ports {USER_SW[5]}]
+set_property PACKAGE_PIN AY33 [get_ports {USER_SW[6]}]
+set_property PACKAGE_PIN AY31 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports WDOG_RREQ]
+set_property PACKAGE_PIN AU19 [get_ports WDOG_RREQ]
+
+# native DDR pin names
+
+# set_property PACKAGE_PIN A17 [get_ports {c0_ddr4_dq[37]}]
+# set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[54]}]
+# set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[55]}]
+# set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_dq[28]}]
+# set_property PACKAGE_PIN D23 [get_ports {c0_ddr4_dq[52]}]
+# set_property PACKAGE_PIN D24 [get_ports {c0_ddr4_dq[53]}]
+# set_property PACKAGE_PIN C24 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+# set_property PACKAGE_PIN A22 [get_ports {c0_ddr4_dq[46]}]
+# set_property PACKAGE_PIN A23 [get_ports {c0_ddr4_dq[47]}]
+# set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_dq[29]}]
+# set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_dq[27]}]
+# set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dqs_t[6]}]
+# set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dqs_c[6]}]
+# set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dq[50]}]
+# set_property PACKAGE_PIN G21 [get_ports {c0_ddr4_dq[51]}]
+# set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+# set_property PACKAGE_PIN A24 [get_ports {c0_ddr4_dq[42]}]
+# set_property PACKAGE_PIN B22 [get_ports {c0_ddr4_dqs_t[5]}]
+# set_property PACKAGE_PIN B21 [get_ports {c0_ddr4_dqs_c[5]}]
+# set_property PACKAGE_PIN B17 [get_ports {c0_ddr4_dqs_t[4]}]
+# set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_dqs_c[4]}]
+# set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dq[38]}]
+# set_property PACKAGE_PIN A12 [get_ports {c0_ddr4_dq[31]}]
+# set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[48]}]
+# set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[49]}]
+# set_property PACKAGE_PIN C23 [get_ports {c0_ddr4_dq[40]}]
+# set_property PACKAGE_PIN A25 [get_ports {c0_ddr4_dq[43]}]
+# set_property PACKAGE_PIN C22 [get_ports {c0_ddr4_dq[44]}]
+# set_property PACKAGE_PIN B14 [get_ports {c0_ddr4_dq[24]}]
+# set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_adr[4]}]
+# set_property PACKAGE_PIN C21 [get_ports {c0_ddr4_dq[41]}]
+# set_property PACKAGE_PIN D21 [get_ports {c0_ddr4_dq[45]}]
+# set_property PACKAGE_PIN C16 [get_ports {c0_ddr4_dq[32]}]
+# set_property PACKAGE_PIN E12 [get_ports {c0_ddr4_dq[16]}]
+# set_property PACKAGE_PIN D13 [get_ports {c0_ddr4_dq[25]}]
+# set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_dqs_t[3]}]
+# set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_dqs_c[3]}]
+# set_property PACKAGE_PIN E15 [get_ports {c0_ddr4_dq[18]}]
+# #set_property PACKAGE_PIN P18 [get_ports {c0_ddr4_ck_t[1]}]
+# #set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_ck_c[1]}]
+# set_property PACKAGE_PIN L19 [get_ports {c0_ddr4_adr[0]}]
+# set_property PACKAGE_PIN J18 [get_ports {c0_ddr4_adr[5]}]
+# #set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke[0]}]
+# set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke}]
+# set_property PACKAGE_PIN D19 [get_ports c0_ddr4_act_n]
+# set_property PACKAGE_PIN F12 [get_ports {c0_ddr4_dq[17]}]
+# set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_dq[19]}]
+# set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_adr[2]}]
+# set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_adr[3]}]
+# set_property PACKAGE_PIN J16 [get_ports {c0_ddr4_adr[1]}]
+# #set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_cke[1]}]
+# set_property PACKAGE_PIN E18 [get_ports c0_ddr4_reset_n]
+# set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_dqs_t[2]}]
+# set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_dqs_c[2]}]
+# #set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t[0]}]
+# set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t}]
+# #set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c[0]}]
+# set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c}]
+# set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_bg[0]}]
+# #set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_bg[1]}]
+# #set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt[0]}]
+# set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt}]
+# #set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n[0]}]
+# set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n}]
+# #set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_cs_n[1]}]
+# #set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_odt[1]}]
+# set_property PACKAGE_PIN K13 [get_ports {c0_ddr4_dq[10]}]
+# set_property PACKAGE_PIN J14 [get_ports {c0_ddr4_dq[11]}]
+# set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_adr[16]}]
+# set_property PACKAGE_PIN G17 [get_ports {c0_ddr4_ba[0]}]
+# set_property PACKAGE_PIN H16 [get_ports {c0_ddr4_adr[14]}]
+# set_property PACKAGE_PIN G19 [get_ports {c0_ddr4_ba[1]}]
+# set_property PACKAGE_PIN N11 [get_ports {c0_ddr4_dqs_t[0]}]
+# set_property PACKAGE_PIN M11 [get_ports {c0_ddr4_dqs_c[0]}]
+# set_property PACKAGE_PIN J15 [get_ports {c0_ddr4_dq[8]}]
+# set_property PACKAGE_PIN K15 [get_ports {c0_ddr4_dq[9]}]
+# set_property PACKAGE_PIN G16 [get_ports {c0_ddr4_adr[15]}]
+# set_property PACKAGE_PIN M10 [get_ports {c0_ddr4_dq[6]}]
+# set_property PACKAGE_PIN L10 [get_ports {c0_ddr4_dq[7]}]
+# set_property PACKAGE_PIN J11 [get_ports {c0_ddr4_dqs_t[1]}]
+# set_property PACKAGE_PIN J10 [get_ports {c0_ddr4_dqs_c[1]}]
+# set_property PACKAGE_PIN L17 [get_ports {c0_ddr4_adr[6]}]
+# set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_adr[8]}]
+# set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_adr[9]}]
+# set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_adr[7]}]
+# set_property PACKAGE_PIN M19 [get_ports {c0_ddr4_adr[10]}]
+# set_property PACKAGE_PIN M15 [get_ports {c0_ddr4_adr[11]}]
+# set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_adr[12]}]
+# set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_adr[13]}]
+# set_property PACKAGE_PIN L22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+# set_property PACKAGE_PIN P11 [get_ports {c0_ddr4_dq[0]}]
+# set_property PACKAGE_PIN P10 [get_ports {c0_ddr4_dq[1]}]
+# set_property PACKAGE_PIN L12 [get_ports {c0_ddr4_dq[2]}]
+# set_property PACKAGE_PIN M12 [get_ports {c0_ddr4_dq[3]}]
+# set_property PACKAGE_PIN N13 [get_ports {c0_ddr4_dq[4]}]
+# set_property PACKAGE_PIN N12 [get_ports {c0_ddr4_dq[5]}]
+# set_property PACKAGE_PIN K11 [get_ports {c0_ddr4_dq[12]}]
+# set_property PACKAGE_PIN K10 [get_ports {c0_ddr4_dq[13]}]
+# set_property PACKAGE_PIN J13 [get_ports {c0_ddr4_dq[14]}]
+# set_property PACKAGE_PIN K12 [get_ports {c0_ddr4_dq[15]}]
+# set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[20]}]
+# set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[21]}]
+# set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_dq[22]}]
+# set_property PACKAGE_PIN G14 [get_ports {c0_ddr4_dq[23]}]
+# set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_dq[26]}]
+# set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_dq[30]}]
+# set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[33]}]
+# set_property PACKAGE_PIN B19 [get_ports {c0_ddr4_dq[34]}]
+# set_property PACKAGE_PIN A20 [get_ports {c0_ddr4_dq[35]}]
+# set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[36]}]
+# set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dq[39]}]
+# set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[56]}]
+# set_property PACKAGE_PIN J23 [get_ports {c0_ddr4_dq[57]}]
+# set_property PACKAGE_PIN K20 [get_ports {c0_ddr4_dq[58]}]
+# set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dq[59]}]
+# set_property PACKAGE_PIN H21 [get_ports {c0_ddr4_dq[60]}]
+# set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[61]}]
+# set_property PACKAGE_PIN K23 [get_ports {c0_ddr4_dq[62]}]
+# set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[63]}]
+# set_property PACKAGE_PIN N14 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+# set_property PACKAGE_PIN L14 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+# set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+# set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+# set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+# set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dqs_t[7]}]
+
+#set_property CFGBVS GND [current_design]
+#set_property CONFIG_VOLTAGE 1.8 [current_design]
+
+# set_property PACKAGE_PIN H19 [get_ports c0_sys_clk_p]
+# set_property PACKAGE_PIN H18 [get_ports c0_sys_clk_n]
+
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[1]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[0]}]
+
+# set_property PACKAGE_PIN AB31 [get_ports GTX_CLK_P]
+# set_property PACKAGE_PIN AB32 [get_ports GTX_CLK_N]
+
+# set_property PACKAGE_PIN AH39 [get_ports {DP_C2M_N[0]}]
+# set_property PACKAGE_PIN AF39 [get_ports {DP_C2M_N[1]}]
+# set_property PACKAGE_PIN AD39 [get_ports {DP_C2M_N[2]}]
+# set_property PACKAGE_PIN AB39 [get_ports {DP_C2M_N[3]}]
+# set_property PACKAGE_PIN Y39 [get_ports {DP_C2M_N[4]}]
+# set_property PACKAGE_PIN V39 [get_ports {DP_C2M_N[5]}]
+# set_property PACKAGE_PIN K39 [get_ports {DP_C2M_N[6]}]
+# set_property PACKAGE_PIN M39 [get_ports {DP_C2M_N[7]}]
+# set_property PACKAGE_PIN P39 [get_ports {DP_C2M_N[8]}]
+# set_property PACKAGE_PIN T39 [get_ports {DP_C2M_N[9]}]
+# set_property PACKAGE_PIN AH38 [get_ports {DP_C2M_P[0]}]
+# set_property PACKAGE_PIN AF38 [get_ports {DP_C2M_P[1]}]
+# set_property PACKAGE_PIN AD38 [get_ports {DP_C2M_P[2]}]
+# set_property PACKAGE_PIN AB38 [get_ports {DP_C2M_P[3]}]
+# set_property PACKAGE_PIN Y38 [get_ports {DP_C2M_P[4]}]
+# set_property PACKAGE_PIN V38 [get_ports {DP_C2M_P[5]}]
+# set_property PACKAGE_PIN K38 [get_ports {DP_C2M_P[6]}]
+# set_property PACKAGE_PIN M38 [get_ports {DP_C2M_P[7]}]
+# set_property PACKAGE_PIN P38 [get_ports {DP_C2M_P[8]}]
+# set_property PACKAGE_PIN T38 [get_ports {DP_C2M_P[9]}]
+# set_property PACKAGE_PIN AE36 [get_ports {GBTCLK_M2C_P[0]}]
+# set_property PACKAGE_PIN AE37 [get_ports {GBTCLK_M2C_N[0]}]
+# set_property PACKAGE_PIN AA36 [get_ports {GBTCLK_M2C_P[1]}]
+# set_property PACKAGE_PIN AA37 [get_ports {GBTCLK_M2C_N[1]}]
+
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y4_p [get_ports {GBTCLK_M2C_P[0]}]
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y7_p [get_ports {GBTCLK_M2C_P[1]}]
+
+# # False path constraints
+# # ----------------------------------------------------------------------------------------------------------------------
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]
+
+#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iACLK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CFG_CLK_IBUF_inst/O]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iGPUCLK]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iMCLK]
+
+set_property PULLUP true [get_ports QSPI_D0]
+set_property PULLUP true [get_ports QSPI_D1]
+set_property PULLUP true [get_ports QSPI_D2]
+set_property PULLUP true [get_ports QSPI_D3]
+
+# set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
+# set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports "c0_ddr4_bg[0]"]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
+set_property BITSTREAM.CONFIG.PERSIST Yes [current_design]
+set_property BITSTREAM.STARTUP.MATCH_CYCLE Auto [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
+set_property CONFIG_MODE S_SELECTMAP [current_design]
+
+
diff --git a/fpga/targets/arm_mps3/fpga_timing.xdc b/fpga/targets/arm_mps3/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..23677a726e5026e2ad86b27165879129dad79b4a
--- /dev/null
+++ b/fpga/targets/arm_mps3/fpga_timing.xdc
@@ -0,0 +1,22 @@
+##################################################################################
+## ##
+## Arm MPS3 Rev-C timing XDC ##
+## ##
+##################################################################################
+
+create_clock -period 100.000 -name CS_TCK -waveform {0.000 50.000} [get_ports CS_TCK]
+create_clock -period 20.000 -name {OSCCLK[1]} -waveform {0.000 10.000} [get_ports {OSCCLK[1]}]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports {UART_RX_F[*]}]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports {UART_RX_F[*]}]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports CB_nRST]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports CB_nRST]
+set_input_delay -clock [get_clocks CS_TCK] -min -add_delay 5.000 [get_ports CS_TMS]
+set_input_delay -clock [get_clocks CS_TCK] -max -add_delay 9.000 [get_ports CS_TMS]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports CS_nSRST]
+set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports CS_nSRST]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay -5.000 [get_ports {SH0_IO[*]}]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports {SH0_IO[*]}]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 0.000 [get_ports {UART_TX_F[*]}]
+set_output_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 6.000 [get_ports {UART_TX_F[*]}]
+set_output_delay -clock [get_clocks CS_TCK] -min -add_delay -1.000 [get_ports CS_TMS]
+set_output_delay -clock [get_clocks CS_TCK] -max -add_delay 5.000 [get_ports CS_TMS]
diff --git a/fpga/targets/arm_mps3/megasoc_design_wrapper.v b/fpga/targets/arm_mps3/megasoc_design_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..dbcafe44666ca2bfba4a111c729dd3bfcef8f207
--- /dev/null
+++ b/fpga/targets/arm_mps3/megasoc_design_wrapper.v
@@ -0,0 +1,318 @@
+`timescale 1 ps / 1 ps
+
+module megasoc_design_wrapper(
+//------------------------------------------------------
+// Port declarations
+//------------------------------------------------------
+
+// DDR
+ // output wire c0_ddr4_act_n,
+ // output wire [16:0] c0_ddr4_adr,
+ // output wire [1:0] c0_ddr4_ba,
+ // output wire [0:0] c0_ddr4_bg,
+ // output wire [0:0] c0_ddr4_cke,
+ // output wire [0:0] c0_ddr4_odt,
+ // output wire [0:0] c0_ddr4_cs_n,
+ // output wire [0:0] c0_ddr4_ck_t,
+ // output wire [0:0] c0_ddr4_ck_c,
+ // output wire c0_ddr4_reset_n,
+ // inout wire [7:0] c0_ddr4_dm_dbi_n,
+ // inout wire [63:0] c0_ddr4_dq,
+ // inout wire [7:0] c0_ddr4_dqs_t,
+ // inout wire [7:0] c0_ddr4_dqs_c,
+ // input wire c0_sys_clk_p,
+ // input wire c0_sys_clk_n,
+ // input wire DDR_nALERT,
+ // output wire DDR_PARITY,
+ // input DDR_nEVENT,
+ // output wire DDR_SCL,
+ // inout wire DDR_SDA,
+
+// SMB
+//-----------
+ output wire [6:0] SMBF_ADDR,
+ output wire SMBF_FIFOSEL,
+ inout wire [15:0] SMBF_DATA,
+ output wire SMBF_nOE,
+ output wire SMBF_nWE,
+ output wire SMBF_nRST,
+
+ output wire ETH_nCS,
+ output wire ETH_nOE,
+ input wire ETH_INT,
+
+ output wire USB_nCS,
+ output wire USB_DACK,
+ input wire USB_DREQ,
+ input wire USB_INT,
+
+// HDMI
+//-----------
+ output wire [23:0] MMB_DATA,
+ output wire MMB_DE,
+ output wire MMB_HS,
+ output wire MMB_VS,
+ output wire MMB_IDCLK,
+ output wire MMB_SCK,
+ output wire MMB_WS,
+ output wire [3:0] MMB_SD,
+
+ output wire HDMI_CSCL,
+ inout wire HDMI_CSDA,
+ input wire HDMI_INT,
+
+// Audio
+//-----------
+ output wire AUD_MCLK,
+ output wire AUD_SCLK,
+ output wire AUD_LRCK,
+ output wire AUD_SDIN,
+ input wire AUD_SDOUT,
+
+ output wire AUD_nRST,
+ output wire AUD_SCL,
+ inout wire AUD_SDA,
+
+// EMMC
+//-----------
+ inout wire [7:0] EMMC_DAT,
+ inout wire EMMC_CMD,
+ output wire EMMC_CLK,
+ output wire EMMC_nRST,
+ input wire EMMC_DS,
+
+// CLCD
+//-----------
+ inout wire [17:10] CLCD_PD,
+ output wire CLCD_RD,
+ output wire CLCD_RS,
+ output wire CLCD_CS,
+ output wire CLCD_WR_SCL,
+ output wire CLCD_BL,
+ output wire CLCD_RST,
+
+ output wire CLCD_TSCL,
+ inout wire CLCD_TSDA,
+ input wire CLCD_TINT,
+ output wire CLCD_TNC,
+
+// UART
+//-----------
+ output wire [3:0] UART_TX_F,
+
+ input wire [3:0] UART_RX_F,
+
+// DEBUG
+//-----------
+ input wire CS_TDI,
+ output wire CS_TDO, // SWV / JTAG TDO
+ inout wire CS_TMS, // SWD I/O / JTAG TMS
+ input wire CS_TCK, // SWD Clk / JTAG TCK
+ input wire CS_nSRST,
+ input wire CS_nTRST,
+ input wire CS_nDET,
+
+ output wire [15:0] CS_T_D, // Trace data
+ output wire CS_T_CLK, // Trace clock
+ output wire CS_T_CTL, // Trace control
+
+// LED SW
+//-----------
+ output wire [9:0] USER_nLED,
+ input wire [7:0] USER_SW,
+ input wire [1:0] USER_nPB,
+
+// OSCCLK
+//-----------
+ input wire [5:0] OSCCLK,
+
+// FMC
+//-----------
+ // input wire [1:0] CLK_M2C_P,
+ // input wire [1:0] CLK_M2C_N,
+
+ // input wire FMC_CLK_DIR,
+
+ // inout wire [3:2] CLK_BIDIR_P,
+ // inout wire [3:2] CLK_BIDIR_N,
+
+ // inout wire [23:0] HA_P, // HA CLK=0,1,17
+ // inout wire [23:0] HA_N,
+
+ // inout wire [21:0] HB_P, // HB CLK=0,6,17
+ // inout wire [21:0] HB_N,
+
+ // inout wire [33:0] LA_P, // LA CLK=0,1,17,18
+ // inout wire [33:0] LA_N,
+
+ // input wire [1:0] GBTCLK_M2C_P,
+ // input wire [1:0] GBTCLK_M2C_N,
+// `ifdef GTH
+ // input wire [9:0] DP_M2C_P,
+ // input wire [9:0] DP_M2C_N,
+
+ // output wire [9:0] DP_C2M_P,
+ // output wire [9:0] DP_C2M_N,
+// `endif
+ // input wire FMC_nPRSNT,
+
+ // input wire GTX_CLK_N,
+ // input wire GTX_CLK_P,
+
+ // input wire SATA_CLK_N,
+ // input wire SATA_CLK_P,
+
+// Quad SPI
+//-----------
+ inout wire QSPI_D0,
+ inout wire QSPI_D1,
+ inout wire QSPI_D2,
+ inout wire QSPI_D3,
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+
+// USER SD
+//-----------
+ inout wire [3:0] USD_DAT,
+ inout wire USD_CMD,
+ output wire USD_CLK,
+ input wire USD_NCD,
+
+// RESET
+//-----------
+ input wire CB_nPOR,
+ input wire CB_nRST,
+ input wire CB_RUN,
+
+ input wire IOFPGA_NRST,
+ input wire IOFPGA_NSPIR,
+
+ output wire IOFPGA_SYSWDT,
+ input wire PB_IRQ,
+ output wire WDOG_RREQ,
+
+// SCC
+//-----------
+ output wire CFG_DATAOUT,
+ input wire CFG_LOAD,
+ input wire CFG_nRST,
+ input wire CFG_CLK,
+ input wire CFG_DATAIN,
+ input wire CFG_WnR,
+
+// MCC SMB
+//-----------
+ input wire [25:16] SMBM_A,
+ inout wire [15:0] SMBM_D,
+ input wire [4:1] SMBM_nE,
+ input wire SMBM_CLK,
+ input wire [1:0] SMBM_nBL,
+ input wire SMBM_nOE,
+ input wire SMBM_nWE,
+ output wire SMBM_nWAIT,
+
+// SHIELD
+//-----------
+ inout wire [17:0] SH0_IO,
+ inout wire [17:0] SH1_IO,
+ output wire SH_nRST,
+
+ output wire SH_ADC_CS,
+ output wire SH_ADC_CK,
+ output wire SH_ADC_DI,
+ input wire SH_ADC_DO
+// (PMOD0_0,
+// PMOD0_1,
+// PMOD0_2,
+// PMOD0_3,
+// PMOD0_4,
+// PMOD0_5,
+// PMOD0_6,
+// PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+
+
+//REFCLK24MHZ 24 MHz
+//******************************************************************************
+BUFG uBUFG_REFCLK24MHZ (.I(OSCCLK[0]), .O(REFCLK24MHZ));
+
+//ACLK Big CPU 50 MHz
+//******************************************************************************
+BUFG uBUFG_iACLK (.I(OSCCLK[1]), .O(ACLK)); //Big CPU 50 MHz
+BUFG uBUFG_iBCLK (.I(OSCCLK[2]), .O(BCLK));
+//******************************************************************************
+// SMBMCLK Micro SMB 25 MHz
+//******************************************************************************
+BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
+
+//******************************************************************************
+// Main body of code
+// =================
+//******************************************************************************
+ assign SMBF_FIFOSEL = 1'b0;
+ assign SMBF_ADDR = {7{1'b0}};
+ assign CLCD_BL = 1'b0; // Extinguish LCD back light
+ // Minimum design tie-offs
+ assign MMB_IDCLK = 1'b0;
+ assign EMMC_CLK = 1'b0;
+ assign QSPI_nCS = 1'b1;
+ assign QSPI_SCLK = 1'b0;
+ assign IOFPGA_SYSWDT = 1'b0;
+ assign WDOG_RREQ = 1'b0;
+ assign SMBM_nWAIT = 1'b1;
+ assign CFG_DATAOUT = 1'b0;
+ wire nRST;
+ reg rst_sync0, rst_sync1, rst_sync2;
+ assign nRST_in = CB_nRST || CS_nSRST;
+ assign nRST = rst_sync2;
+
+ always @(posedge ACLK)
+ if (~nRST_in) begin
+ rst_sync0 <= 1'b0;
+ rst_sync1 <= 1'b0;
+ end else begin
+ rst_sync0 <= 1'b1;
+ rst_sync1 <= rst_sync0;
+ rst_sync2 <= rst_sync1;
+ end
+
+ wire SWDITMS_0;
+ wire SWDOEN_0;
+ wire SWDO_0;
+
+ assign CS_TMS = (SWDOEN_0==1'b1) ? SWDO_0 : 1'bz;
+ assign SWDITMS_0 = CS_TMS;
+
+ megasoc_design megasoc_design_i
+ (.CLK_IN_0(ACLK),
+ .nRESET_0(nRST),
+
+ .QSPI_IO_e_0(),
+ .QSPI_IO_i_0(),
+ .QSPI_IO_o_0(),
+ .QSPI_SCLK_0(),
+ .QSPI_nCS_0(),
+
+ .UARTRXD_0(1'b0),
+ .UARTTXD_0(UART_TX_F[1]),
+
+ .SWCLKTCK_0(CS_TCK),
+ .SWDITMS_0(SWDITMS_0),
+ .SWDOEN_0(SWDOEN_0),
+ .SWDO_0(SWDO_0),
+ .TDI_0(),
+ .TDO_0(),
+ .nTDOEN_0(),
+ .nTRST_0(CS_nTRST));
+endmodule
diff --git a/makefile b/makefile
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..e4bbcf0be4dac86a2742ad5e836b829e48e6f5a1 100644
--- a/makefile
+++ b/makefile
@@ -0,0 +1,122 @@
+#-----------------------------------------------------------------------------
+# MegaSoC Top-Level Makefile
+# - Includes other Makefiles in flow directory
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+include $(SOCLABS_PROJECT_DIR)/megasoc.config
+
+#-------------------------------------
+# - Commonly Overloaded Variables
+#-------------------------------------
+# Name of test directory - Default Test is Hello World
+TESTNAME ?= hello_world
+
+# Simulator type (mti/vcs/xm)
+SIMULATOR = vcs
+
+# IS this for an ASIC Flow?
+ASIC ?= no
+
+# Are simulations to be run in fast mode? (i.e. RAMs preloaded)
+FAST_SIM ?= yes
+
+# Include the expansion subsystem?
+INC_EXP ?= no
+
+COMPILE_GCC ?= 0
+AARCH64 ?= 1
+export COMPILE_GCC
+export AARCH64
+#-------------------------------------
+# - Directory Setups
+#-------------------------------------
+# Directory of Testcodes
+TESTCODES_DIR := $(SOCLABS_MEGASOC_TECH_DIR)/software/src
+TESTCODES_BUILD_DIR := $(SOCLABS_MEGASOC_TECH_DIR)/software/build
+export TESTCODES_BUILD_DIR
+
+# Project System Directory
+FPGA_IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga
+
+# Directory to put simulation files
+SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
+SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
+
+#-------------------------------------
+# - Test List Variables
+#-------------------------------------
+# List of all tests (this is used when running 'make all/clean')
+TEST_LIST_FILE ?= $(TESTCODES_DIR)/software_list.txt
+TEST_LIST = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do echo $$line; done)
+
+#-------------------------------------
+# - Verilog Defines and Filelists
+#-------------------------------------
+# Simulator/Lint Defines
+DEFINES_VC += +define+CORTEX_A53 +define+USE_TARMAC
+
+# Set Variables depending on whether Expansion subsystem is included
+ifeq ($(INC_EXP),yes)
+ DEFINES_VC += +define+INC_EXP
+ MEGASOC_DEFINES += INC_EXP
+endif
+
+ifeq ($(ASIC),yes)
+ DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
+ MEGASOC_DEFINES += ASIC_TEST_PORTS POWER_PINS
+else
+ DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_BEHAV.flist
+ TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_BEHAV.flist
+ TB_TOP ?= megasoc_tb
+endif
+
+FPGA_DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_FPGA.flist
+
+# Make variables visible to target shells
+export ARM_CORTEX_M0_DIR
+export ARM_CORSTONE_101_DIR
+export FLIST_INCLUDES
+export AMS
+# Location of Defines File
+DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/
+DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v
+
+#------------------------------------------
+# - Include Makefiles for Specific Flows
+#------------------------------------------
+# Include Software Compilation Makefile
+include $(SOCLABS_PROJECT_DIR)/flows/makefile.software
+
+# Include Linting Makefile
+include $(SOCLABS_PROJECT_DIR)/flows/makefile.lint
+
+# Include Simulation Makefile
+include $(SOCLABS_PROJECT_DIR)/flows/makefile.simulate
+
+# Include Regression Simulation Makefile
+include $(SOCLABS_PROJECT_DIR)/flows/makefile.regression
+
+# Include FPGA Makefile
+include $(SOCLABS_PROJECT_DIR)/flows/makefile.fpga
+
+# Include Synthesis Makefile
+include $(SOCLABS_PROJECT_DIR)/flows/makefile.asic
+
+#------------------------------------------
+# - Common Targets Across Flows
+#------------------------------------------
+# Generate Defines File for MegaSoC
+gen_defs:
+ @mkdir -p $(DEFINES_DIR)
+ @$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(MEGASOC_DEFINES) -o $(DEFINES_FILE)
+
+clean_sim:
+ @rm -rf ./simulate
+
+clean: clean_sim clean_all_code
\ No newline at end of file
diff --git a/megasoc.config b/megasoc.config
new file mode 100644
index 0000000000000000000000000000000000000000..9e4e773beea50916a14d27039bc76e45d0e0df13
--- /dev/null
+++ b/megasoc.config
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------------------------
+# MegaSoC Configuration file
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### IP Configuration
+# !!EDIT this to point to the relevant logical directories of IP
+ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
+ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+
diff --git a/megasoc_chip/chip/logical/megasoc_chip.v b/megasoc_chip/chip/logical/megasoc_chip.v
new file mode 100644
index 0000000000000000000000000000000000000000..b6233e14d980d11f4d24318f079cfacc9a8d48e7
--- /dev/null
+++ b/megasoc_chip/chip/logical/megasoc_chip.v
@@ -0,0 +1,63 @@
+//-----------------------------------------------------------------------------
+// MegaSoC Chip
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// megasoc_system
+
+module megasoc_chip(
+ input wire CLK_IN,
+ input wire nRESET,
+
+ // QSPI signals
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+ output wire [3:0] QSPI_IO_o,
+ input wire [3:0] QSPI_IO_i,
+ output wire [3:0] QSPI_IO_e,
+
+ // UART signals
+ input wire UARTRXD,
+ output wire UARTTXD,
+ output wire UARTTXEN,
+
+ // DAP-lite Signals
+ input wire nTRST,
+ input wire SWCLKTCK,
+ input wire SWDITMS,
+ input wire TDI,
+ output wire TDO,
+ output wire nTDOEN,
+ output wire SWDO,
+ output wire SWDOEN
+
+);
+
+megasoc_system u_megasoc_system(
+ .CLK_IN(CLK_IN),
+ .nRESET(nRESET),
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e),
+ .UARTRXD(UARTRXD),
+ .UARTTXD(UARTTXD),
+ .UARTTXEN(UARTTXEN),
+ .nTRST(nTRST),
+ .SWCLKTCK(SWCLKTCK),
+ .SWDITMS(SWDITMS),
+ .TDI(TDI),
+ .TDO(TDO),
+ .nTDOEN(nTDOEN),
+ .SWDO(SWDO),
+ .SWDOEN(SWDOEN)
+);
+
+endmodule
\ No newline at end of file
diff --git a/megasoc_chip/chip/logical/millisoc_chip.v b/megasoc_chip/chip/logical/millisoc_chip.v
deleted file mode 100644
index 7073420d85278f1a6d5cedbffa203470b2c31f64..0000000000000000000000000000000000000000
--- a/megasoc_chip/chip/logical/millisoc_chip.v
+++ /dev/null
@@ -1,20 +0,0 @@
-//-----------------------------------------------------------------------------
-// MegaSoC Chip
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// Daniel Newbrook (d.newbrook@soton.ac.uk)
-//
-// Copyright � 2021-4, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// Modules instantiated:
-// megasoc_system
-
-module megasoc_chip(
-
-);
-
-
-
-endmodule
\ No newline at end of file
diff --git a/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v b/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
index 4048dc442a0f7bfef7e08fd3ebd417533ee5aa14..ccd5c1986245980a316ff050fbef7d2efb6d8f3f 100644
--- a/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
+++ b/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
@@ -12,12 +12,73 @@
// megasoc_chip
module megasoc_chip_pads(
+`ifdef POWER_PINS
+ inout wire VDD,
+ inout wire VSS,
+ inout wire AVDD,
+ inout wire AVSS,
+ inout wire VDDACC,
+`endif
+ // Clocks and Reset
+ input wire REF_CLK_XTAL1,
+ output wire REF_CLK_XTAL2,
+ input wire PORESTn,
+ input wire nSRST,
+
+ // GPIO
+ inout wire [15:0] GPIO_P0,
+ inout wire [15:0] GPIO_P1,
+
+ // SWD/JTAG TRACE - for Mictor 38
+ output wire TDO_SWO,
+ input wire RTCK,
+ input wire TDI,
+ input wire TCK_SWCLK,
+ inout wire TMS_SWDIO,
+ input wire nTRST,
+ output wire [15:0] TRACEDATA,
+ input wire TRACECLK,
+ input wire TRACECTL,
+ input wire DBGRQ,
+ output wire DBGACK,
+
+ // QSPI Interface
+ output wire QSPI_SCLK,
+ inout wire [3:0] QSPI_IO,
+ output wire QSPI_nCS
+
+ // Ethernet
+
+ // DDR
+
+ // USB
+
);
+wire [3:0] QSPI_IO_o;
+wire [3:0] QSPI_IO_i;
+wire [3:0] QSPI_IO_e;
-megasoc_chip u_megasoc_chip(
+assign QSPI_IO[0] = QSPI_IO_e[0] ? QSPI_IO_o[0] : 1'bz;
+assign QSPI_IO[1] = QSPI_IO_e[1] ? QSPI_IO_o[1] : 1'bz;
+assign QSPI_IO[2] = QSPI_IO_e[2] ? QSPI_IO_o[2] : 1'bz;
+assign QSPI_IO[3] = QSPI_IO_e[3] ? QSPI_IO_o[3] : 1'bz;
+
+assign QSPI_IO_i[0] = QSPI_IO[0];
+assign QSPI_IO_i[1] = QSPI_IO[1];
+assign QSPI_IO_i[2] = QSPI_IO[2];
+assign QSPI_IO_i[3] = QSPI_IO[3];
+
+megasoc_chip u_megasoc_chip(
+ .CLK_IN(REF_CLK_XTAL1),
+ .nRESET(PORESTn),
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e)
);
diff --git a/megasoc_system/logical/megasoc_system.v b/megasoc_system/logical/megasoc_system.v
index 87c0dba565c93e8d5fe1e6b5fdce5849daf7d002..31bc96365ca48e7e81c81d28048bf468a3e205a8 100644
--- a/megasoc_system/logical/megasoc_system.v
+++ b/megasoc_system/logical/megasoc_system.v
@@ -12,18 +12,302 @@
// megasoc_tech_wrapper
// expansion_subsystem_wrapper
+`include "gen_defines.v"
module megasoc_system(
+ input wire CLK_IN,
+ input wire nRESET,
+
+ // QSPI Signals
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+ output wire [3:0] QSPI_IO_o,
+ input wire [3:0] QSPI_IO_i,
+ output wire [3:0] QSPI_IO_e,
+
+ // UART signals
+ input wire UARTRXD,
+ output wire UARTTXD,
+ output wire UARTTXEN,
+
+ // DAP-LITE external signals
+ input wire nTRST,
+ input wire SWCLKTCK,
+ input wire SWDITMS,
+ input wire TDI,
+ output wire TDO,
+ output wire nTDOEN,
+ output wire SWDO,
+ output wire SWDOEN
+
);
+wire [1:0] AXI_SYS_EXP_awid;
+wire [31:0] AXI_SYS_EXP_awaddr;
+wire [7:0] AXI_SYS_EXP_awlen;
+wire [2:0] AXI_SYS_EXP_awsize;
+wire [1:0] AXI_SYS_EXP_awburst;
+wire AXI_SYS_EXP_awlock;
+wire [3:0] AXI_SYS_EXP_awcache;
+wire [2:0] AXI_SYS_EXP_awprot;
+wire AXI_SYS_EXP_awvalid;
+wire AXI_SYS_EXP_awready;
+wire [63:0] AXI_SYS_EXP_wdata;
+wire [7:0] AXI_SYS_EXP_wstrb;
+wire AXI_SYS_EXP_wlast;
+wire AXI_SYS_EXP_wvalid;
+wire AXI_SYS_EXP_wready;
+wire [1:0] AXI_SYS_EXP_bid;
+wire [1:0] AXI_SYS_EXP_bresp;
+wire AXI_SYS_EXP_bvalid;
+wire AXI_SYS_EXP_bready;
+wire [1:0] AXI_SYS_EXP_arid;
+wire [31:0] AXI_SYS_EXP_araddr;
+wire [7:0] AXI_SYS_EXP_arlen;
+wire [2:0] AXI_SYS_EXP_arsize;
+wire [1:0] AXI_SYS_EXP_arburst;
+wire AXI_SYS_EXP_arlock;
+wire [3:0] AXI_SYS_EXP_arcache;
+wire [2:0] AXI_SYS_EXP_arprot;
+wire AXI_SYS_EXP_arvalid;
+wire AXI_SYS_EXP_arready;
+wire [1:0] AXI_SYS_EXP_rid;
+wire [63:0] AXI_SYS_EXP_rdata;
+wire [1:0] AXI_SYS_EXP_rresp;
+wire AXI_SYS_EXP_rlast;
+wire AXI_SYS_EXP_rvalid;
+wire AXI_SYS_EXP_rready;
+wire AXI_EXP_SYS_awid;
+wire [31:0] AXI_EXP_SYS_awaddr;
+wire [7:0] AXI_EXP_SYS_awlen;
+wire [2:0] AXI_EXP_SYS_awsize;
+wire [1:0] AXI_EXP_SYS_awburst;
+wire AXI_EXP_SYS_awlock;
+wire [3:0] AXI_EXP_SYS_awcache;
+wire [2:0] AXI_EXP_SYS_awprot;
+wire AXI_EXP_SYS_awvalid;
+wire AXI_EXP_SYS_awready;
+wire [63:0] AXI_EXP_SYS_wdata;
+wire [7:0] AXI_EXP_SYS_wstrb;
+wire AXI_EXP_SYS_wlast;
+wire AXI_EXP_SYS_wvalid;
+wire AXI_EXP_SYS_wready;
+wire AXI_EXP_SYS_bid;
+wire [1:0] AXI_EXP_SYS_bresp;
+wire AXI_EXP_SYS_bvalid;
+wire AXI_EXP_SYS_bready;
+wire AXI_EXP_SYS_arid;
+wire [31:0] AXI_EXP_SYS_araddr;
+wire [7:0] AXI_EXP_SYS_arlen;
+wire [2:0] AXI_EXP_SYS_arsize;
+wire [1:0] AXI_EXP_SYS_arburst;
+wire AXI_EXP_SYS_arlock;
+wire [3:0] AXI_EXP_SYS_arcache;
+wire [2:0] AXI_EXP_SYS_arprot;
+wire AXI_EXP_SYS_arvalid;
+wire AXI_EXP_SYS_arready;
+wire AXI_EXP_SYS_rid;
+wire [63:0] AXI_EXP_SYS_rdata;
+wire [1:0] AXI_EXP_SYS_rresp;
+wire AXI_EXP_SYS_rlast;
+wire AXI_EXP_SYS_rvalid;
+wire AXI_EXP_SYS_rready;
megasoc_tech_wrapper u_megasoc_tech_wrapper(
+ .SYS_CLK(CLK_IN),
+ .SYS_CLKEN(1'b1),
+ .SYS_RESETn(nRESET),
+
+ // Millisoc system AXI Manager
+ .AXI_SYS_EXP_awid(AXI_SYS_EXP_awid),
+ .AXI_SYS_EXP_awaddr(AXI_SYS_EXP_awaddr),
+ .AXI_SYS_EXP_awlen(AXI_SYS_EXP_awlen),
+ .AXI_SYS_EXP_awsize(AXI_SYS_EXP_awsize),
+ .AXI_SYS_EXP_awburst(AXI_SYS_EXP_awburst),
+ .AXI_SYS_EXP_awlock(AXI_SYS_EXP_awlock),
+ .AXI_SYS_EXP_awcache(AXI_SYS_EXP_awcache),
+ .AXI_SYS_EXP_awprot(AXI_SYS_EXP_awprot),
+ .AXI_SYS_EXP_awvalid(AXI_SYS_EXP_awvalid),
+ .AXI_SYS_EXP_awready(AXI_SYS_EXP_awready),
+ .AXI_SYS_EXP_wdata(AXI_SYS_EXP_wdata),
+ .AXI_SYS_EXP_wstrb(AXI_SYS_EXP_wstrb),
+ .AXI_SYS_EXP_wlast(AXI_SYS_EXP_wlast),
+ .AXI_SYS_EXP_wvalid(AXI_SYS_EXP_wvalid),
+ .AXI_SYS_EXP_wready(AXI_SYS_EXP_wready),
+ .AXI_SYS_EXP_bid(AXI_SYS_EXP_bid),
+ .AXI_SYS_EXP_bresp(AXI_SYS_EXP_bresp),
+ .AXI_SYS_EXP_bvalid(AXI_SYS_EXP_bvalid),
+ .AXI_SYS_EXP_bready(AXI_SYS_EXP_bready),
+ .AXI_SYS_EXP_arid(AXI_SYS_EXP_arid),
+ .AXI_SYS_EXP_araddr(AXI_SYS_EXP_araddr),
+ .AXI_SYS_EXP_arlen(AXI_SYS_EXP_arlen),
+ .AXI_SYS_EXP_arsize(AXI_SYS_EXP_arsize),
+ .AXI_SYS_EXP_arburst(AXI_SYS_EXP_arburst),
+ .AXI_SYS_EXP_arlock(AXI_SYS_EXP_arlock),
+ .AXI_SYS_EXP_arcache(AXI_SYS_EXP_arcache),
+ .AXI_SYS_EXP_arprot(AXI_SYS_EXP_arprot),
+ .AXI_SYS_EXP_arvalid(AXI_SYS_EXP_arvalid),
+ .AXI_SYS_EXP_arready(AXI_SYS_EXP_arready),
+ .AXI_SYS_EXP_rid(AXI_SYS_EXP_rid),
+ .AXI_SYS_EXP_rdata(AXI_SYS_EXP_rdata),
+ .AXI_SYS_EXP_rresp(AXI_SYS_EXP_rresp),
+ .AXI_SYS_EXP_rlast(AXI_SYS_EXP_rlast),
+ .AXI_SYS_EXP_rvalid(AXI_SYS_EXP_rvalid),
+ .AXI_SYS_EXP_rready(AXI_SYS_EXP_rready),
+
+ // Millisoc system AXI Subordinate
+ .AXI_EXP_SYS_awid(AXI_EXP_SYS_awid),
+ .AXI_EXP_SYS_awaddr(AXI_EXP_SYS_awaddr),
+ .AXI_EXP_SYS_awlen(AXI_EXP_SYS_awlen),
+ .AXI_EXP_SYS_awsize(AXI_EXP_SYS_awsize),
+ .AXI_EXP_SYS_awburst(AXI_EXP_SYS_awburst),
+ .AXI_EXP_SYS_awlock(AXI_EXP_SYS_awlock),
+ .AXI_EXP_SYS_awcache(AXI_EXP_SYS_awcache),
+ .AXI_EXP_SYS_awprot(AXI_EXP_SYS_awprot),
+ .AXI_EXP_SYS_awvalid(AXI_EXP_SYS_awvalid),
+ .AXI_EXP_SYS_awready(AXI_EXP_SYS_awready),
+ .AXI_EXP_SYS_wdata(AXI_EXP_SYS_wdata),
+ .AXI_EXP_SYS_wstrb(AXI_EXP_SYS_wstrb),
+ .AXI_EXP_SYS_wlast(AXI_EXP_SYS_wlast),
+ .AXI_EXP_SYS_wvalid(AXI_EXP_SYS_wvalid),
+ .AXI_EXP_SYS_wready(AXI_EXP_SYS_wready),
+ .AXI_EXP_SYS_bid(AXI_EXP_SYS_bid),
+ .AXI_EXP_SYS_bresp(AXI_EXP_SYS_bresp),
+ .AXI_EXP_SYS_bvalid(AXI_EXP_SYS_bvalid),
+ .AXI_EXP_SYS_bready(AXI_EXP_SYS_bready),
+ .AXI_EXP_SYS_arid(AXI_EXP_SYS_arid),
+ .AXI_EXP_SYS_araddr(AXI_EXP_SYS_araddr),
+ .AXI_EXP_SYS_arlen(AXI_EXP_SYS_arlen),
+ .AXI_EXP_SYS_arsize(AXI_EXP_SYS_arsize),
+ .AXI_EXP_SYS_arburst(AXI_EXP_SYS_arburst),
+ .AXI_EXP_SYS_arlock(AXI_EXP_SYS_arlock),
+ .AXI_EXP_SYS_arcache(AXI_EXP_SYS_arcache),
+ .AXI_EXP_SYS_arprot(AXI_EXP_SYS_arprot),
+ .AXI_EXP_SYS_arvalid(AXI_EXP_SYS_arvalid),
+ .AXI_EXP_SYS_arready(AXI_EXP_SYS_arready),
+ .AXI_EXP_SYS_rid(AXI_EXP_SYS_rid),
+ .AXI_EXP_SYS_rdata(AXI_EXP_SYS_rdata),
+ .AXI_EXP_SYS_rresp(AXI_EXP_SYS_rresp),
+ .AXI_EXP_SYS_rlast(AXI_EXP_SYS_rlast),
+ .AXI_EXP_SYS_rvalid(AXI_EXP_SYS_rvalid),
+ .AXI_EXP_SYS_rready(AXI_EXP_SYS_rready),
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_nCS(QSPI_nCS),
+ .QSPI_IO_o(QSPI_IO_o),
+ .QSPI_IO_i(QSPI_IO_i),
+ .QSPI_IO_e(QSPI_IO_e),
+ .UARTRXD(UARTRXD),
+ .UARTTXD(UARTTXD),
+ .UARTTXEN(UARTTXEN),
+ .nTRST(nTRST),
+ .SWCLKTCK(SWCLKTCK),
+ .SWDITMS(SWDITMS),
+ .TDI(TDI),
+ .TDO(TDO),
+ .nTDOEN(nTDOEN),
+ .SWDO(SWDO),
+ .SWDOEN(SWDOEN)
);
+`ifdef INC_EXP
expansion_subsystem_wrapper u_megasoc_expansion_wrapper(
+ .sys_clk(),
+ .resetn(),
+ .exp_clk(),
+ .exp_clken(),
+ .expresetn(),
-);
+ // System Clock domain control
+ .CSYSREQ_CD_sys(),
+ .CSYSACK_CD_sys(),
+ .CACTIVE_CD_sys(),
+
+ // Expansion Clock domain control
+ .CSYSREQ_CD_exp(),
+ .CSYSACK_CD_exp(),
+ .CACTIVE_CD_exp(),
+
+ // AXI Expansion input port
+ .AXI_EXP_SS_awid(AXI_SYS_EXP_awid),
+ .AXI_EXP_SS_awaddr(AXI_SYS_EXP_awaddr),
+ .AXI_EXP_SS_awlen(AXI_SYS_EXP_awlen),
+ .AXI_EXP_SS_awsize(AXI_SYS_EXP_awsize),
+ .AXI_EXP_SS_awburst(AXI_SYS_EXP_awburst),
+ .AXI_EXP_SS_awlock(AXI_SYS_EXP_awlock),
+ .AXI_EXP_SS_awcache(AXI_SYS_EXP_awcache),
+ .AXI_EXP_SS_awprot(AXI_SYS_EXP_awprot),
+ .AXI_EXP_SS_awvalid(AXI_SYS_EXP_awvalid),
+ .AXI_EXP_SS_awready(AXI_SYS_EXP_awready),
+ .AXI_EXP_SS_wdata(AXI_SYS_EXP_wdata),
+ .AXI_EXP_SS_wstrb(AXI_SYS_EXP_wstrb),
+ .AXI_EXP_SS_wlast(AXI_SYS_EXP_wlast),
+ .AXI_EXP_SS_wvalid(AXI_SYS_EXP_wvalid),
+ .AXI_EXP_SS_wready(AXI_SYS_EXP_wready),
+ .AXI_EXP_SS_bid(AXI_SYS_EXP_bid),
+ .AXI_EXP_SS_bresp(AXI_SYS_EXP_bresp),
+ .AXI_EXP_SS_bvalid(AXI_SYS_EXP_bvalid),
+ .AXI_EXP_SS_bready(AXI_SYS_EXP_bready),
+ .AXI_EXP_SS_arid(AXI_SYS_EXP_arid),
+ .AXI_EXP_SS_araddr(AXI_SYS_EXP_araddr),
+ .AXI_EXP_SS_arlen(AXI_SYS_EXP_arlen),
+ .AXI_EXP_SS_arsize(AXI_SYS_EXP_arsize),
+ .AXI_EXP_SS_arburst(AXI_SYS_EXP_arburst),
+ .AXI_EXP_SS_arlock(AXI_SYS_EXP_arlock),
+ .AXI_EXP_SS_arcache(AXI_SYS_EXP_arcache),
+ .AXI_EXP_SS_arprot(AXI_SYS_EXP_arprot),
+ .AXI_EXP_SS_arvalid(AXI_SYS_EXP_arvalid),
+ .AXI_EXP_SS_arready(AXI_SYS_EXP_arready),
+ .AXI_EXP_SS_rid(AXI_SYS_EXP_rid),
+ .AXI_EXP_SS_rdata(AXI_SYS_EXP_rdata),
+ .AXI_EXP_SS_rresp(AXI_SYS_EXP_rresp),
+ .AXI_EXP_SS_rlast(AXI_SYS_EXP_rlast),
+ .AXI_EXP_SS_rvalid(AXI_SYS_EXP_rvalid),
+ .AXI_EXP_SS_rready(AXI_SYS_EXP_rready),
+ // AXI System output port
+ .AXI_SYS_awid(AXI_EXP_SYS_awid),
+ .AXI_SYS_awaddr(AXI_EXP_SYS_awaddr),
+ .AXI_SYS_awlen(AXI_EXP_SYS_awlen),
+ .AXI_SYS_awsize(AXI_EXP_SYS_awsize),
+ .AXI_SYS_awburst(AXI_EXP_SYS_awburst),
+ .AXI_SYS_awlock(AXI_EXP_SYS_awlock),
+ .AXI_SYS_awcache(AXI_EXP_SYS_awcache),
+ .AXI_SYS_awprot(AXI_EXP_SYS_awprot),
+ .AXI_SYS_awvalid(AXI_EXP_SYS_awvalid),
+ .AXI_SYS_awready(AXI_EXP_SYS_awready),
+ .AXI_SYS_wdata(AXI_EXP_SYS_wdata),
+ .AXI_SYS_wstrb(AXI_EXP_SYS_wstrb),
+ .AXI_SYS_wlast(AXI_EXP_SYS_wlast),
+ .AXI_SYS_wvalid(AXI_EXP_SYS_wvalid),
+ .AXI_SYS_wready(AXI_EXP_SYS_wready),
+ .AXI_SYS_bid(AXI_EXP_SYS_bid),
+ .AXI_SYS_bresp(AXI_EXP_SYS_bresp),
+ .AXI_SYS_bvalid(AXI_EXP_SYS_bvalid),
+ .AXI_SYS_bready(AXI_EXP_SYS_bready),
+ .AXI_SYS_arid(AXI_EXP_SYS_arid),
+ .AXI_SYS_araddr(AXI_EXP_SYS_araddr),
+ .AXI_SYS_arlen(AXI_EXP_SYS_arlen),
+ .AXI_SYS_arsize(AXI_EXP_SYS_arsize),
+ .AXI_SYS_arburst(AXI_EXP_SYS_arburst),
+ .AXI_SYS_arlock(AXI_EXP_SYS_arlock),
+ .AXI_SYS_arcache(AXI_EXP_SYS_arcache),
+ .AXI_SYS_arprot(AXI_EXP_SYS_arprot),
+ .AXI_SYS_arvalid(AXI_EXP_SYS_arvalid),
+ .AXI_SYS_arready(AXI_EXP_SYS_arready),
+ .AXI_SYS_rid(AXI_EXP_SYS_rid),
+ .AXI_SYS_rdata(AXI_EXP_SYS_rdata),
+ .AXI_SYS_rresp(AXI_EXP_SYS_rresp),
+ .AXI_SYS_rlast(AXI_EXP_SYS_rlast),
+ .AXI_SYS_rvalid(AXI_EXP_SYS_rvalid),
+ .AXI_SYS_rready(AXI_EXP_SYS_rready),
+
+ // Interrupts
+ .irq_dma_channel(),
+ .irq_dma_comb_nonsec()
+);
+`else
+ assign AXI_EXP_SYS_rready=1'b0;
+`endif
endmodule
diff --git a/megasoc_tech b/megasoc_tech
index 8f3b1ab2d812186541a6ce85be26cd2d900bd044..1d407a5f8ab1a828ab9933ae004e0e1bd7a04d58 160000
--- a/megasoc_tech
+++ b/megasoc_tech
@@ -1 +1 @@
-Subproject commit 8f3b1ab2d812186541a6ce85be26cd2d900bd044
+Subproject commit 1d407a5f8ab1a828ab9933ae004e0e1bd7a04d58
diff --git a/verif/control/logical/megasoc_clkreset.v b/verif/control/logical/megasoc_clkreset.v
new file mode 100644
index 0000000000000000000000000000000000000000..a26ac6258e5b512fc685a2e7f2fa55c08ba458b8
--- /dev/null
+++ b/verif/control/logical/megasoc_clkreset.v
@@ -0,0 +1,75 @@
+//-----------------------------------------------------------------------------
+// MegaSoC clock and power on generator adapted from Arm CMSDK Simple clock and power on reset generator
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple clock and power on reset generator
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ps
+
+module megasoc_clkreset(
+ output wire CLK,
+ output wire NRST,
+ output wire NRST_early,
+ output wire NRST_late,
+ output wire NRST_ext
+ );
+
+ reg clock_q;
+
+ reg [15:0] shifter;
+
+ initial
+ begin
+ clock_q <= 1'b0;
+ shifter <= 16'h0000;
+ #40 clock_q <= 1'b1;
+ end
+
+ always @(clock_q)
+ #5 clock_q <= !clock_q; // 10ns period, 100MHz
+
+ assign CLK = clock_q;
+
+ always @(posedge clock_q)
+ if (! (&shifter)) // until full...
+ shifter <= {shifter[14:0], 1'b1}; // shift left, fill with 1's
+
+ assign NRST_early = shifter[ 7];
+ assign NRST = shifter[ 8];
+ assign NRST_late = shifter[9] ;
+ assign NRST_ext = shifter[15];
+
+endmodule
+
+
+
diff --git a/verif/testbench/logical/megasoc_project_tb.v b/verif/testbench/logical/megasoc_project_tb.v
deleted file mode 100644
index 649f56d41a8636bb4373fc5d4c4b27d80abb973c..0000000000000000000000000000000000000000
--- a/verif/testbench/logical/megasoc_project_tb.v
+++ /dev/null
@@ -1,25 +0,0 @@
-//-----------------------------------------------------------------------------
-// MegaSoC Chip testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// Daniel Newbrook (d.newbrook@soton.ac.uk)
-//
-// Copyright � 2021-4, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// Modules instantiated:
-// megasoc_chip_pads
-`timescale 1ns/1ps
-
-module megasoc_chip_tb
-
-
-
-
-megasoc_chip_pads u_megasoc_chip_pads(
-
-)
-
-
-endmodule
diff --git a/verif/testbench/logical/megasoc_tb.sv b/verif/testbench/logical/megasoc_tb.sv
new file mode 100644
index 0000000000000000000000000000000000000000..813c0d9f52abf54dd3d26b0b0962d0769262dc09
--- /dev/null
+++ b/verif/testbench/logical/megasoc_tb.sv
@@ -0,0 +1,120 @@
+//-----------------------------------------------------------------------------
+// MegaSoC Chip testbench
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// megasoc_chip_pads
+`timescale 1ns/1ps
+
+module megasoc_tb();
+
+`define CORTEXA53_UNIVENT_DPI_CAPTURE
+`define CORTEXA53_UNIVENT
+
+wire EXT_CLK;
+wire nRESET;
+
+wire QSPI_SCLK;
+wire [3:0] QSPI_IO;
+wire QSPI_nCS;
+
+megasoc_clkreset u_megasoc_clkreset(
+ .CLK(EXT_CLK),
+ .NRST(nRESET)
+);
+
+`define MEGASOC_TECH_WRAPPER u_megasoc_chip_pads.u_megasoc_chip.u_megasoc_system.u_megasoc_tech_wrapper
+`define MEGASOC_ROM `MEGASOC_TECH_WRAPPER.u_ROM_wrapper.u_ROM
+`define MEGASOC_SRAM `MEGASOC_TECH_WRAPPER.u_SRAM_wrapper.u_SRAM
+
+initial begin
+ $readmemh("bootloader.hex", `MEGASOC_ROM.mem, 32'h0000_0000);
+ $readmemh("app_ram.v8-a.hex", `MEGASOC_SRAM.mem, 32'h0000_0000);
+ //#1 $readmemh("app_flash.v8-a.hex", FLASH.I0.memory);
+
+end
+
+megasoc_chip_pads u_megasoc_chip_pads(
+ .REF_CLK_XTAL1(EXT_CLK),
+ .REF_CLK_XTAL2(),
+ .PORESTn(nRESET),
+ .nSRST(nRESET),
+ .GPIO_P0(),
+ .GPIO_P1(),
+ .TDO_SWO(),
+ .RTCK(),
+ .TDI(),
+ .TCK_SWCLK(),
+ .TMS_SWDIO(),
+ .nTRST(),
+ .TRACEDATA(),
+ .TRACECLK(),
+ .TRACECTL(),
+ .DBGRQ(),
+ .DBGACK(),
+ .QSPI_SCLK(QSPI_SCLK),
+ .QSPI_IO(QSPI_IO),
+ .QSPI_nCS(QSPI_nCS)
+);
+
+// sst26vf064b FLASH(
+// .SCK(QSPI_SCLK),
+// .SIO(QSPI_IO),
+// .CEb(QSPI_nCS)
+// );
+
+`define MEGASOC_PERIPHERALS u_megasoc_chip_pads.u_megasoc_chip.u_megasoc_system.u_megasoc_tech_wrapper.u_megasoc_peripheral_subsystem
+`define MEGASOC_UART `MEGASOC_PERIPHERALS.u_apb_uart_0
+
+// Clock 100 MHz
+// Baudrate 115200
+wire BAUDx16;
+assign BAUDx16 = `MEGASOC_UART.BAUDTICK;
+
+
+wire UARTXD = `MEGASOC_UART.TXD;
+reg UARTXD_del;
+always @(negedge nRESET or posedge BAUDx16) begin
+ if (!nRESET)
+ UARTXD_del <= 1'b0;
+ else
+ UARTXD_del <= UARTXD; // delay one BAUD_TICK-time
+end
+
+wire UARTXD_edge = UARTXD_del ^ UARTXD; // edge detect
+
+
+reg [3:0] pllq;
+always @(negedge nRESET or posedge BAUDx16) begin
+ if(~nRESET)
+ pllq <= 4'h0;
+ else begin
+ if (UARTXD_edge)
+ pllq[3:0] <= 4'b0110;
+ else
+ pllq[3:0] <= pllq[3:0] -1'b1;
+ end
+end
+
+wire baud_clk = pllq[3];
+
+wire uart_clk;
+
+megasoc_uart_capture #(.LOGFILENAME("logs/uart.log"), .VERBOSE(1)) u_uart_capture(
+ .RESETn(nRESET),
+ .CLK(baud_clk),
+ .RXD(UARTXD),
+ .DEBUG_TESTER_ENABLE (),
+ .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
+ .AUXCTRL ()
+);
+
+
+
+endmodule
diff --git a/verif/trace/megasoc_uart_capture.v b/verif/trace/megasoc_uart_capture.v
new file mode 100644
index 0000000000000000000000000000000000000000..3e50fe4ff84cfef676820fc9fe742c0498c217cd
--- /dev/null
+++ b/verif/trace/megasoc_uart_capture.v
@@ -0,0 +1,251 @@
+//-----------------------------------------------------------------------------
+// NanoSoC UART RXD capture with file logging adapted from Arm CMSDK Uart Capture
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : A device to capture serial data
+//-----------------------------------------------------------------------------
+// This module assume CLK is same frequency as baud rate.
+// In the example UART a test mode is used to enable data output as maximum
+// speed (PCLK). In such case we can connect CLK signal directly to PCLK.
+// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
+// accordingly as well.
+//
+// This module stop the simulation when character 0x04 is received.
+// An output called SIMULATION_END is set for 1 cycle before simulation is
+// terminated to allow other testbench component like profiler (if any)
+// to output reports before the simulation stop.
+//
+// This model also support ESCAPE (0x1B, decimal 27) code sequence
+// ESC - 0x10 - XY Capture XY to AUXCTRL output
+// ESC - 0x11 Set DEBUG_TESTER_ENABLE to 1
+// ESC - 0x12 Clear DEBUG_TESTER_ENABLE to 0
+
+
+module megasoc_uart_capture
+ #(parameter LOGFILENAME = "uart.log",
+ parameter VERBOSE = 0)
+ (
+ input wire RESETn, // Power on reset
+ input wire CLK, // Clock (baud rate)
+ input wire RXD, // Received data
+ output wire SIMULATIONEND, // Simulation end indicator
+ output wire DEBUG_TESTER_ENABLE, // Enable debug tester
+ output wire [7:0] AUXCTRL); // Auxiliary control
+
+ reg [8:0] rx_shift_reg;
+ wire [8:0] nxt_rx_shift;
+ reg [6:0] string_length;
+ reg [7:0] tube_string [127:0];
+ reg [7:0] text_char;
+ integer i;
+ reg nxt_end_simulation;
+ reg reg_end_simulation;
+ wire char_received;
+ reg reg_esc_code_mode; // Escape code mode
+ reg reg_aux_ctrl_mode; // Auxiliary control capture mode
+ reg [7:0] reg_aux_ctrl; // Registered Auxiliary control
+ reg reg_dbgtester_enable;
+
+ integer mcd; // channel descriptor for log file output
+ reg [40*8-1:0] log_file; // File name can't be > *40* characters
+
+`define UartSTDOUT 32'h00000001
+ initial
+ begin
+ $timeformat(-9, 0, " ns", 14);
+ log_file = LOGFILENAME;
+ mcd = $fopen(log_file);
+ mcd = mcd | `UartSTDOUT; // always echo to console
+ if(mcd == 0) begin
+ $fwrite(mcd,"tarmac: Error, zero returned in response to $fopen\n");
+ $finish(2);
+ end
+ $fwrite(mcd,"uartcapture: Generating output file %0s using MCD %x @ %m\n",
+ log_file, mcd);
+ end
+
+ // Receive shift register
+ assign nxt_rx_shift = {RXD,rx_shift_reg[8:1]};
+ assign char_received = (rx_shift_reg[0]==1'b0);
+
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ rx_shift_reg <= {9{1'b1}};
+ else
+ if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
+ rx_shift_reg <= {9{1'b1}};
+ else
+ rx_shift_reg <= nxt_rx_shift;
+ end
+
+ // Escape code mode register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_esc_code_mode <= 1'b0;
+ else // Set to escape mode if ESC code is detected
+ if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
+ reg_esc_code_mode <= 1'b1;
+ else if (char_received)
+ reg_esc_code_mode <= 1'b0;
+ end
+
+ // Aux Ctrl capture mode register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_aux_ctrl_mode <= 1'b0;
+ else // Set to Aux control capture mode if ESC-0x10 sequence is detected
+ if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
+ reg_aux_ctrl_mode <= 1'b1;
+ else if (char_received)
+ reg_aux_ctrl_mode <= 1'b0;
+ end
+
+ // Aux Ctrl capture data register
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_aux_ctrl <= {8{1'b0}};
+ else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
+ if (char_received & (reg_aux_ctrl_mode==1'b1))
+ reg_aux_ctrl <= rx_shift_reg[8:1];
+ end
+
+ assign AUXCTRL = reg_aux_ctrl;
+
+ // Debug tester enable
+ always @(posedge CLK or negedge RESETn)
+ begin
+ if (~RESETn)
+ reg_dbgtester_enable <= 1'b0;
+ else // Enable debug tester if ESC-0x11 sequence is detected
+ if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
+ reg_dbgtester_enable <= 1'b1;
+ else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
+ // Disable debug tester if ESC-0x12 sequence is detected
+ reg_dbgtester_enable <= 1'b0;
+ end
+
+ assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
+
+ // Message display
+ always @ (posedge CLK or negedge RESETn)
+ begin: p_tube
+ if (~RESETn)
+ begin
+ string_length = 7'b0;
+ nxt_end_simulation <= 1'b0;
+ for (i=0; i<= 127; i=i+1) begin
+ tube_string [i] = 8'h00;
+ end
+ end
+ else
+ if (char_received)
+ begin
+ if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
+ begin
+ // Escape code, or in escape code mode
+ // Data receive can be command, aux ctrl data
+ // Ignore this data
+ end
+ else if (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
+ nxt_end_simulation <= 1'b1;
+ else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
+ // New line
+ begin
+ tube_string[string_length] = 8'h00;
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: ",$time);
+
+ for (i=0; i<= string_length; i=i+1)
+ begin
+ text_char = tube_string[i];
+ $fwrite(mcd,"%s",text_char);
+ end
+
+ $fwrite(mcd,"\n");
+ string_length = 7'b0;
+ end
+ else
+ begin
+ tube_string[string_length] = rx_shift_reg[8:1];
+ string_length = string_length + 1;
+ if (string_length >79) // line too long, display and clear buffer
+ begin
+ tube_string[string_length] = 8'h00;
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: ",$time);
+
+ for (i=0; i<= string_length; i=i+1)
+ begin
+ text_char = tube_string[i];
+ $fwrite(mcd,"%s",text_char);
+ end
+
+ $fwrite(mcd,"\n");
+ string_length = 7'b0;
+
+ end
+
+ end
+
+ end
+
+ end // p_TUBE
+
+ // Delay for simulation end
+ always @ (posedge CLK or negedge RESETn)
+ begin: p_sim_end
+ if (~RESETn)
+ begin
+ reg_end_simulation <= 1'b0;
+ end
+ else
+ begin
+ reg_end_simulation <= nxt_end_simulation;
+ if (reg_end_simulation==1'b1)
+ begin
+ if (VERBOSE != 0)
+ $fwrite(mcd,"%t UART<%m>: Test Ended\n",$time);
+ else
+ $fwrite(mcd,"Test Ended\n");
+ $stop;
+ end
+ end
+ end
+
+ assign SIMULATIONEND = nxt_end_simulation & (~reg_end_simulation);
+
+endmodule