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hostio4

Project information

SoC Labs developed Hostio controller (implemented in the SoC) and target (implemented in testbench, FPGA, RPi Pico dev board). This supports 4x byte-wide AXI-stream virtual channels over a 7-pin off-chip interface for nanosoc reference design

soclabs

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README
BSD 2-Clause "Simplified" License

Created on

March 05, 2026

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