diff --git a/mem/verilog/SROM_Ax32.v b/mem/verilog/SROM_Ax32.v
index f2c3a9a576a89fe1f23305ed7e2921ad4c3ebb2b..f7210a7aa612c0a7c61b8cf13940c8f5cb105637 100644
--- a/mem/verilog/SROM_Ax32.v
+++ b/mem/verilog/SROM_Ax32.v
@@ -13,7 +13,7 @@
 //
 // David Flynn (d.w.flynn@soton.ac.uk)
 //
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module SROM_Ax32
@@ -27,8 +27,8 @@ module SROM_Ax32
     output wire [31:0] RDATA);        //Read Data
     
    localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
-   localparam romgenfile = "bootrom.v";
-   localparam bingenfile = "bootrom.bintxt";
+   localparam romgenfile = "bootrom/verilog/bootrom.v";
+   localparam bingenfile = "bootrom/bintxt/bootrom.bintxt";
 
    // Reg declarations
    reg  [7:0] rombyte0 [0:MEMDEPTH];